From ea7bc5ad89464c11ff7161aecccf65828ae60175 Mon Sep 17 00:00:00 2001 From: rtel Date: Fri, 6 May 2016 12:40:27 +0000 Subject: [PATCH] Update some more standard demos for use on 64-bit architectures. Update the Xilinx Ultrascale+ Cortex-A53 (64-bit) and Cortex-R5 (32-bit) demos to use version 2016.1 of the SDK. git-svn-id: https://svn.code.sf.net/p/freertos/code/trunk@2455 1d2547de-c912-0410-9cb9-b8ca96c0e9e2 --- .../RTOSDemo_A53/.project | 58 +- .../src/Blinky_Demo/main_blinky.c | 27 +- .../RTOSDemo_A53/src/FreeRTOSConfig.h | 10 +- .../RTOSDemo_A53/src/Full_Demo/main_full.c | 127 +- .../RTOSDemo_A53/src/main.c | 129 +- .../RTOSDemo_R5/.cproject | 178 + .../RTOSDemo_R5/.project | 267 + .../RTOSDemo_R5/src/Blinky_Demo/main_blinky.c | 227 + .../RTOSDemo_R5/src/FreeRTOSConfig.h | 222 + .../RTOSDemo_R5/src/FreeRTOS_asm_vectors.S | 103 + .../RTOSDemo_R5/src/FreeRTOS_tick_config.c | 177 + .../RTOSDemo_R5/src/Full_Demo/IntQueueTimer.c | 266 + .../src/Full_Demo/IntQueueTimer.h} | 39 +- .../RTOSDemo_R5/src/Full_Demo/main_full.c | 502 + .../RTOSDemo_R5/src/Full_Demo/reg_test.S | 462 + .../RTOSDemo_R5/src/lscript.ld | 310 + .../RTOSDemo_R5/src/main.c | 314 + .../RTOSDemo_R5/src/platform.c | 105 + .../RTOSDemo_R5/src/platform.h | 41 + .../RTOSDemo_R5/src/platform_config.h | 6 + .../RTOSDemo_R5_bsp/.cproject | 13 + .../RTOSDemo_R5_bsp/.project | 75 + .../RTOSDemo_R5_bsp/.sdkproject | 4 + .../RTOSDemo_R5_bsp/Makefile | 31 + .../psu_cortexr5_0/include/xparameters.h | 1346 + .../libsrc/axipmon_v6_4/src/Makefile | 27 + .../libsrc/axipmon_v6_4/src/xaxipmon.c | 2123 ++ .../libsrc/axipmon_v6_4/src/xaxipmon.h | 938 + .../libsrc/axipmon_v6_4/src/xaxipmon_g.c | 127 + .../libsrc/axipmon_v6_4/src/xaxipmon_hw.h | 571 + .../axipmon_v6_4/src/xaxipmon_selftest.c | 152 + .../libsrc/axipmon_v6_4/src/xaxipmon_sinit.c | 104 + .../libsrc/canps_v3_1/src/Makefile | 40 + .../libsrc/canps_v3_1/src/xcanps.c | 1205 + .../libsrc/canps_v3_1/src/xcanps.h | 575 + .../libsrc/canps_v3_1/src/xcanps_g.c | 55 + .../libsrc/canps_v3_1/src/xcanps_hw.c | 93 + .../libsrc/canps_v3_1/src/xcanps_hw.h | 369 + .../libsrc/canps_v3_1/src/xcanps_intr.c | 421 + .../libsrc/canps_v3_1/src/xcanps_selftest.c | 234 + .../libsrc/canps_v3_1/src/xcanps_sinit.c | 103 + .../libsrc/coresightps_dcc_v1_2/src/Makefile | 40 + .../src/xcoresightpsdcc.c | 181 + .../src/xcoresightpsdcc.h | 70 + .../libsrc/cpu_cortexr5_v1_1/src/Makefile | 22 + .../cpu_cortexr5_v1_1/src/xcpu_cortexr5.h | 43 + .../libsrc/csudma_v1_0/src/Makefile | 40 + .../libsrc/csudma_v1_0/src/xcsudma.c | 767 + .../libsrc/csudma_v1_0/src/xcsudma.h | 418 + .../libsrc/csudma_v1_0/src/xcsudma_g.c | 55 + .../libsrc/csudma_v1_0/src/xcsudma_hw.h | 311 + .../libsrc/csudma_v1_0/src/xcsudma_intr.c | 274 + .../libsrc/csudma_v1_0/src/xcsudma_selftest.c | 125 + .../libsrc/csudma_v1_0/src/xcsudma_sinit.c | 107 + .../libsrc/emacps_v3_2/src/Makefile | 40 + .../libsrc/emacps_v3_2/src/xemacps.c | 489 + .../libsrc/emacps_v3_2/src/xemacps.h | 792 + .../libsrc/emacps_v3_2/src/xemacps_bd.h | 804 + .../libsrc/emacps_v3_2/src/xemacps_bdring.c | 1075 + .../libsrc/emacps_v3_2/src/xemacps_bdring.h | 238 + .../libsrc/emacps_v3_2/src/xemacps_control.c | 1174 + .../libsrc/emacps_v3_2/src/xemacps_g.c | 55 + .../libsrc/emacps_v3_2/src/xemacps_hw.c | 123 + .../libsrc/emacps_v3_2/src/xemacps_hw.h | 656 + .../libsrc/emacps_v3_2/src/xemacps_intr.c | 268 + .../libsrc/emacps_v3_2/src/xemacps_sinit.c | 97 + .../libsrc/gpiops_v3_1/src/Makefile | 40 + .../libsrc/gpiops_v3_1/src/xgpiops.c | 628 + .../libsrc/gpiops_v3_1/src/xgpiops.h | 268 + .../libsrc/gpiops_v3_1/src/xgpiops_g.c | 55 + .../libsrc/gpiops_v3_1/src/xgpiops_hw.c | 169 + .../libsrc/gpiops_v3_1/src/xgpiops_hw.h | 164 + .../libsrc/gpiops_v3_1/src/xgpiops_intr.c | 731 + .../libsrc/gpiops_v3_1/src/xgpiops_selftest.c | 133 + .../libsrc/gpiops_v3_1/src/xgpiops_sinit.c | 101 + .../libsrc/iicps_v3_1/src/Makefile | 40 + .../libsrc/iicps_v3_1/src/xiicps.c | 332 + .../libsrc/iicps_v3_1/src/xiicps.h | 420 + .../libsrc/iicps_v3_1/src/xiicps_g.c | 61 + .../libsrc/iicps_v3_1/src/xiicps_hw.c | 111 + .../libsrc/iicps_v3_1/src/xiicps_hw.h | 383 + .../libsrc/iicps_v3_1/src/xiicps_intr.c | 101 + .../libsrc/iicps_v3_1/src/xiicps_master.c | 987 + .../libsrc/iicps_v3_1/src/xiicps_options.c | 496 + .../libsrc/iicps_v3_1/src/xiicps_selftest.c | 132 + .../libsrc/iicps_v3_1/src/xiicps_sinit.c | 102 + .../libsrc/iicps_v3_1/src/xiicps_slave.c | 590 + .../libsrc/ipipsu_v2_0/src/Makefile | 40 + .../libsrc/ipipsu_v2_0/src/xipipsu.c | 352 + .../libsrc/ipipsu_v2_0/src/xipipsu.h | 281 + .../libsrc/ipipsu_v2_0/src/xipipsu_g.c | 161 + .../libsrc/ipipsu_v2_0/src/xipipsu_hw.h | 79 + .../libsrc/ipipsu_v2_0/src/xipipsu_sinit.c | 90 + .../libsrc/qspipsu_v1_0/src/Makefile | 40 + .../libsrc/qspipsu_v1_0/src/xqspipsu.c | 1290 + .../libsrc/qspipsu_v1_0/src/xqspipsu.h | 272 + .../libsrc/qspipsu_v1_0/src/xqspipsu_g.c | 58 + .../libsrc/qspipsu_v1_0/src/xqspipsu_hw.h | 841 + .../qspipsu_v1_0/src/xqspipsu_options.c | 449 + .../libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c | 100 + .../libsrc/rtcpsu_v1_2/src/Makefile | 40 + .../libsrc/rtcpsu_v1_2/src/xrtcpsu.c | 422 + .../libsrc/rtcpsu_v1_2/src/xrtcpsu.h | 387 + .../libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c | 55 + .../libsrc/rtcpsu_v1_2/src/xrtcpsu_hw.h | 362 + .../libsrc/rtcpsu_v1_2/src/xrtcpsu_intr.c | 232 + .../libsrc/rtcpsu_v1_2/src/xrtcpsu_selftest.c | 112 + .../libsrc/rtcpsu_v1_2/src/xrtcpsu_sinit.c | 102 + .../libsrc/scugic_v3_2/src/Makefile | 40 + .../libsrc/scugic_v3_2/src/xscugic.c | 769 + .../libsrc/scugic_v3_2/src/xscugic.h | 327 + .../libsrc/scugic_v3_2/src/xscugic_g.c | 56 + .../libsrc/scugic_v3_2/src/xscugic_hw.c | 570 + .../libsrc/scugic_v3_2/src/xscugic_hw.h | 642 + .../libsrc/scugic_v3_2/src/xscugic_intr.c | 173 + .../libsrc/scugic_v3_2/src/xscugic_selftest.c | 115 + .../libsrc/scugic_v3_2/src/xscugic_sinit.c | 103 + .../libsrc/sdps_v2_7/src/Makefile | 40 + .../libsrc/sdps_v2_7/src/xsdps.c | 1507 + .../libsrc/sdps_v2_7/src/xsdps.h | 228 + .../libsrc/sdps_v2_7/src/xsdps_g.c | 58 + .../libsrc/sdps_v2_7/src/xsdps_hw.h | 1186 + .../libsrc/sdps_v2_7/src/xsdps_options.c | 1152 + .../libsrc/sdps_v2_7/src/xsdps_sinit.c | 99 + .../libsrc/standalone_v5_4/src/Makefile | 74 + .../libsrc/standalone_v5_4/src/_exit.c | 87 + .../libsrc/standalone_v5_4/src/_open.c | 53 + .../libsrc/standalone_v5_4/src/_sbrk.c | 70 + .../libsrc/standalone_v5_4/src/abort.c | 42 + .../libsrc/standalone_v5_4/src/asm_vectors.S | 121 + .../libsrc/standalone_v5_4/src/boot.S | 300 + .../libsrc/standalone_v5_4/src/bspconfig.h | 40 + .../libsrc/standalone_v5_4/src/changelog.txt | 324 + .../libsrc/standalone_v5_4/src/close.c | 47 + .../libsrc/standalone_v5_4/src/config.make | 2 + .../libsrc/standalone_v5_4/src/cpu_init.S | 79 + .../libsrc/standalone_v5_4/src/errno.c | 51 + .../libsrc/standalone_v5_4/src/fcntl.c | 46 + .../libsrc/standalone_v5_4/src/fstat.c | 50 + .../libsrc/standalone_v5_4/src/getpid.c | 51 + .../libsrc/standalone_v5_4/src/inbyte.c | 14 + .../src/includes_ps/xddr_xmpu0_cfg.h | 1304 + .../src/includes_ps/xddr_xmpu1_cfg.h | 1304 + .../src/includes_ps/xddr_xmpu2_cfg.h | 1304 + .../src/includes_ps/xddr_xmpu3_cfg.h | 1304 + .../src/includes_ps/xddr_xmpu4_cfg.h | 1304 + .../src/includes_ps/xddr_xmpu5_cfg.h | 1304 + .../src/includes_ps/xfpd_slcr.h | 382 + .../src/includes_ps/xfpd_slcr_secure.h | 277 + .../src/includes_ps/xfpd_xmpu_cfg.h | 1304 + .../src/includes_ps/xfpd_xmpu_sink.h | 81 + .../src/includes_ps/xiou_secure_slcr.h | 174 + .../src/includes_ps/xiou_slcr.h | 4029 +++ .../src/includes_ps/xlpd_slcr.h | 5667 ++++ .../src/includes_ps/xlpd_slcr_secure.h | 141 + .../src/includes_ps/xlpd_xppu.h | 858 + .../src/includes_ps/xlpd_xppu_sink.h | 81 + .../src/includes_ps/xocm_xmpu_cfg.h | 1304 + .../libsrc/standalone_v5_4/src/isatty.c | 56 + .../libsrc/standalone_v5_4/src/kill.c | 60 + .../libsrc/standalone_v5_4/src/lseek.c | 61 + .../libsrc/standalone_v5_4/src/mpu.c | 283 + .../libsrc/standalone_v5_4/src/open.c | 57 + .../libsrc/standalone_v5_4/src/outbyte.c | 15 + .../libsrc/standalone_v5_4/src/print.c | 32 + .../libsrc/standalone_v5_4/src/putnum.c | 59 + .../libsrc/standalone_v5_4/src/read.c | 115 + .../libsrc/standalone_v5_4/src/sbrk.c | 65 + .../libsrc/standalone_v5_4/src/sleep.c | 125 + .../libsrc/standalone_v5_4/src/sleep.h | 49 + .../libsrc/standalone_v5_4/src/uart.c | 160 + .../libsrc/standalone_v5_4/src/unlink.c | 50 + .../libsrc/standalone_v5_4/src/usleep.c | 127 + .../libsrc/standalone_v5_4/src/vectors.c | 168 + .../libsrc/standalone_v5_4/src/vectors.h | 81 + .../libsrc/standalone_v5_4/src/write.c | 116 + .../libsrc/standalone_v5_4/src/xbasic_types.h | 119 + .../libsrc/standalone_v5_4/src/xdebug.h | 32 + .../libsrc/standalone_v5_4/src/xenv.h | 187 + .../standalone_v5_4/src/xenv_standalone.h | 368 + .../libsrc/standalone_v5_4/src/xil-crt0.S | 130 + .../libsrc/standalone_v5_4/src/xil_assert.c | 146 + .../libsrc/standalone_v5_4/src/xil_assert.h | 189 + .../libsrc/standalone_v5_4/src/xil_cache.c | 580 + .../libsrc/standalone_v5_4/src/xil_cache.h | 89 + .../standalone_v5_4/src/xil_cache_vxworks.h | 93 + .../standalone_v5_4/src/xil_exception.c | 218 + .../standalone_v5_4/src/xil_exception.h | 215 + .../libsrc/standalone_v5_4/src/xil_hal.h | 61 + .../libsrc/standalone_v5_4/src/xil_io.c | 380 + .../libsrc/standalone_v5_4/src/xil_io.h | 244 + .../standalone_v5_4/src/xil_macroback.h | 1052 + .../libsrc/standalone_v5_4/src/xil_mmu.h | 80 + .../libsrc/standalone_v5_4/src/xil_mpu.c | 258 + .../libsrc/standalone_v5_4/src/xil_mpu.h | 80 + .../libsrc/standalone_v5_4/src/xil_printf.c | 360 + .../libsrc/standalone_v5_4/src/xil_printf.h | 44 + .../standalone_v5_4/src/xil_testcache.c | 366 + .../standalone_v5_4/src/xil_testcache.h | 63 + .../libsrc/standalone_v5_4/src/xil_testio.c | 301 + .../libsrc/standalone_v5_4/src/xil_testio.h | 91 + .../libsrc/standalone_v5_4/src/xil_testmem.c | 882 + .../libsrc/standalone_v5_4/src/xil_testmem.h | 162 + .../libsrc/standalone_v5_4/src/xil_types.h | 200 + .../standalone_v5_4/src/xparameters_ps.h | 358 + .../standalone_v5_4/src/xplatform_info.c | 133 + .../standalone_v5_4/src/xplatform_info.h | 91 + .../libsrc/standalone_v5_4/src/xpm_counter.c | 292 + .../libsrc/standalone_v5_4/src/xpm_counter.h | 571 + .../libsrc/standalone_v5_4/src/xpseudo_asm.h | 54 + .../standalone_v5_4/src/xpseudo_asm_gcc.h | 175 + .../standalone_v5_4/src/xreg_cortexr5.h | 445 + .../libsrc/standalone_v5_4/src/xstatus.h | 430 + .../libsrc/standalone_v5_4/src/xtime_l.c | 187 + .../libsrc/standalone_v5_4/src/xtime_l.h | 99 + .../libsrc/sysmonpsu_v1_0/src/Makefile | 40 + .../libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c | 1749 ++ .../libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h | 592 + .../libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c | 55 + .../libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h | 2268 ++ .../sysmonpsu_v1_0/src/xsysmonpsu_intr.c | 250 + .../sysmonpsu_v1_0/src/xsysmonpsu_selftest.c | 132 + .../sysmonpsu_v1_0/src/xsysmonpsu_sinit.c | 99 + .../libsrc/ttcps_v3_1/src/Makefile | 40 + .../libsrc/ttcps_v3_1/src/xttcps.c | 441 + .../libsrc/ttcps_v3_1/src/xttcps.h | 412 + .../libsrc/ttcps_v3_1/src/xttcps_g.c | 111 + .../libsrc/ttcps_v3_1/src/xttcps_hw.h | 212 + .../libsrc/ttcps_v3_1/src/xttcps_options.c | 243 + .../libsrc/ttcps_v3_1/src/xttcps_selftest.c | 109 + .../libsrc/ttcps_v3_1/src/xttcps_sinit.c | 98 + .../libsrc/uartps_v3_1/src/Makefile | 40 + .../libsrc/uartps_v3_1/src/xuartps.c | 644 + .../libsrc/uartps_v3_1/src/xuartps.h | 511 + .../libsrc/uartps_v3_1/src/xuartps_g.c | 63 + .../libsrc/uartps_v3_1/src/xuartps_hw.c | 180 + .../libsrc/uartps_v3_1/src/xuartps_hw.h | 449 + .../libsrc/uartps_v3_1/src/xuartps_intr.c | 450 + .../libsrc/uartps_v3_1/src/xuartps_options.c | 761 + .../libsrc/uartps_v3_1/src/xuartps_selftest.c | 166 + .../libsrc/uartps_v3_1/src/xuartps_sinit.c | 99 + .../libsrc/wdtps_v3_0/src/Makefile | 40 + .../libsrc/wdtps_v3_0/src/xwdtps.c | 486 + .../libsrc/wdtps_v3_0/src/xwdtps.h | 223 + .../libsrc/wdtps_v3_0/src/xwdtps_g.c | 59 + .../libsrc/wdtps_v3_0/src/xwdtps_hw.h | 193 + .../libsrc/wdtps_v3_0/src/xwdtps_selftest.c | 173 + .../libsrc/wdtps_v3_0/src/xwdtps_sinit.c | 96 + .../libsrc/zdma_v1_1/src/Makefile | 40 + .../libsrc/zdma_v1_1/src/xzdma.c | 1275 + .../libsrc/zdma_v1_1/src/xzdma.h | 681 + .../libsrc/zdma_v1_1/src/xzdma_g.c | 131 + .../libsrc/zdma_v1_1/src/xzdma_hw.h | 383 + .../libsrc/zdma_v1_1/src/xzdma_intr.c | 205 + .../libsrc/zdma_v1_1/src/xzdma_selftest.c | 119 + .../libsrc/zdma_v1_1/src/xzdma_sinit.c | 106 + .../RTOSDemo_R5_bsp/system.mss | 694 + .../ZynqMP_ZCU102_hw_platform/.project | 41 + .../ZynqMP_ZCU102_hw_platform/psu_init.c | 19394 ++++++++++++ .../ZynqMP_ZCU102_hw_platform/psu_init.h | 26160 ++++++++++++++++ .../ZynqMP_ZCU102_hw_platform/psu_init.tcl | 13537 ++++++++ .../ZynqMP_ZCU102_hw_platform/psu_init_gpl.c | 19357 ++++++++++++ .../ZynqMP_ZCU102_hw_platform/psu_init_gpl.h | 26148 +++++++++++++++ .../ZynqMP_ZCU102_hw_platform/system.hdf | Bin 0 -> 809917 bytes FreeRTOS/Demo/Common/Minimal/AbortDelay.c | 3 +- .../Demo/Common/Minimal/StaticAllocation.c | 3 - FreeRTOS/Source/portable/GCC/ARM_CR5/port.c | 2 +- .../Source/portable/GCC/ARM_CR5/portASM.S | 4 - FreeRTOS/Source/portable/MemMang/heap_4.c | 2 +- 269 files changed, 193984 insertions(+), 176 deletions(-) create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.cproject create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.project create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Blinky_Demo/main_blinky.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOSConfig.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOS_asm_vectors.S create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOS_tick_config.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/IntQueueTimer.c rename FreeRTOS/Demo/{CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/ParTest.c => CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/IntQueueTimer.h} (80%) create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/reg_test.S create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/lscript.ld create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/main.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform_config.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.sdkproject create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/xcpu_cortexr5.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bd.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_control.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_master.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_options.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_slave.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_options.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_exit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_open.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_sbrk.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/abort.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/asm_vectors.S create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/boot.S create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/bspconfig.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/changelog.txt create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/close.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/config.make create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/cpu_init.S create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/errno.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fcntl.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fstat.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/getpid.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/inbyte.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu0_cfg.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu1_cfg.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu2_cfg.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu3_cfg.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu4_cfg.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu5_cfg.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr_secure.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_cfg.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_sink.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_secure_slcr.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr_secure.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu_sink.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xocm_xmpu_cfg.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/isatty.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/kill.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/lseek.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/mpu.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/open.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/outbyte.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/uart.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xbasic_types.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xdebug.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv_standalone.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_hal.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_macroback.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mmu.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_types.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xreg_cortexr5.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_options.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/Makefile create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_hw.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_intr.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_selftest.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_sinit.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/.project create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h create mode 100644 FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.project b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.project index 6d144a479..d2866c629 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.project +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/.project @@ -69,7 +69,7 @@ - 1461847438191 + 1462537732456 src/Full_Demo/Standard_Demo_Tasks 5 @@ -78,7 +78,7 @@ - 1461847438201 + 1462537732456 src/Full_Demo/Standard_Demo_Tasks 5 @@ -87,7 +87,7 @@ - 1461847438221 + 1462537732466 src/Full_Demo/Standard_Demo_Tasks 5 @@ -96,7 +96,7 @@ - 1461847438241 + 1462537732466 src/Full_Demo/Standard_Demo_Tasks 5 @@ -105,7 +105,7 @@ - 1461847438251 + 1462537732476 src/Full_Demo/Standard_Demo_Tasks 5 @@ -114,7 +114,7 @@ - 1461847438251 + 1462537732486 src/Full_Demo/Standard_Demo_Tasks 5 @@ -123,7 +123,7 @@ - 1461847438261 + 1462537732486 src/Full_Demo/Standard_Demo_Tasks 5 @@ -132,7 +132,7 @@ - 1461847438261 + 1462537732496 src/Full_Demo/Standard_Demo_Tasks 5 @@ -141,7 +141,7 @@ - 1461847438271 + 1462537732506 src/Full_Demo/Standard_Demo_Tasks 5 @@ -150,7 +150,7 @@ - 1461847438281 + 1462537732506 src/Full_Demo/Standard_Demo_Tasks 5 @@ -159,7 +159,7 @@ - 1461847438301 + 1462537732516 src/Full_Demo/Standard_Demo_Tasks 5 @@ -167,6 +167,42 @@ 1.0-name-matches-false-false-IntSemTest.c + + 1462537732516 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-StaticAllocation.c + + + + 1462537732526 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-AbortDelay.c + + + + 1462537732536 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1462537732546 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TimerDemo.c + + 1461847264041 src/FreeRTOS_Source/portable/GCC diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c index 91702ed4b..d5d8aad77 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Blinky_Demo/main_blinky.c @@ -75,7 +75,7 @@ * implements the simply blinky style version. * * NOTE 2: This file only contains the source code that is specific to the - * basic demo. Generic functions, such FreeRTOS hook functions, and functions + * simple demo. Generic functions, such FreeRTOS hook functions, and functions * required to configure the hardware are defined in main.c. ****************************************************************************** * @@ -94,14 +94,14 @@ * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly * blocks on attempts to read data from the queue that was created within * main_blinky(). When data is received, the task checks the value of the - * data, and if the value equals the expected 100, toggles an LED. The 'block - * time' parameter passed to the queue receive function specifies that the - * task should be held in the Blocked state indefinitely to wait for data to - * be available on the queue. The queue receive task will only leave the - * Blocked state when the queue send task writes to the queue. As the queue - * send task writes to the queue every 200 milliseconds, the queue receive - * task leaves the Blocked state every 200 milliseconds, and therefore toggles - * the LED every 200 milliseconds. + * data, and if the value equals the expected 100, outputs a message to the + * UART. The 'block time' parameter passed to the queue receive function + * specifies that the task should be held in the Blocked state indefinitely to + * wait for data to be available on the queue. The queue receive task will only + * leave the Blocked state when the queue send task writes to the queue. As the + * queue send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore outputs + * a message every 200 milliseconds. */ /* Kernel includes. */ @@ -109,8 +109,8 @@ #include "task.h" #include "semphr.h" -/* Standard demo includes. */ -#include "partest.h" +/* Xilinx includes. */ +#include "xil_printf.h" /* Priorities at which the tasks are created. */ #define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) @@ -125,9 +125,6 @@ will remove items as they are added, meaning the send task should always find the queue empty. */ #define mainQUEUE_LENGTH ( 1 ) -/* The LED toggled by the Rx task. */ -#define mainTASK_LED ( 0 ) - /*-----------------------------------------------------------*/ /* @@ -221,7 +218,7 @@ const uint32_t ulExpectedValue = 100UL; it the expected value? If it is, toggle the LED. */ if( ulReceivedValue == ulExpectedValue ) { - vParTestToggleLED( mainTASK_LED ); + xil_printf( "100 received\r\n" ); ulReceivedValue = 0U; } } diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h index 8e46f43b4..b426d9b93 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/FreeRTOSConfig.h @@ -132,6 +132,10 @@ #define configUSE_COUNTING_SEMAPHORES 1 #define configUSE_QUEUE_SETS 1 +/* This demo creates RTOS objects using both static and dynamic allocation. */ +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 /* Defaults to 1 anyway. */ + /* Co-routine definitions. */ #define configUSE_CO_ROUTINES 0 #define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) @@ -153,6 +157,8 @@ to exclude the API function. */ #define INCLUDE_vTaskDelay 1 #define INCLUDE_xTimerPendFunctionCall 1 #define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xTaskGetHandle 1 /* This demo makes use of one or more example stats formatting functions. These format the raw data provided by the uxTaskGetSystemState() function in to human @@ -176,8 +182,8 @@ command interpreter running. */ /* Normal assert() semantics without relying on the provision of an assert.h header file. */ -void vAssertCalled( const char * pcFile, unsigned long ulLine ); -#define configASSERT( x ) if( ( x ) == 0 ) vAssertCalled( __FILE__, __LINE__ ); +void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber ); +#define configASSERT( x ) if( ( x ) == 0 ) { vMainAssertCalled( __FILE__, __LINE__ ); } /* If configTASK_RETURN_ADDRESS is not defined then a task that attempts to return from its implementing function will end up in a "task exit error" diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c index 5a7bbceea..b54af1729 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/Full_Demo/main_full.c @@ -101,16 +101,10 @@ * frequently. A register containing an unexpected value is indicative of an * error in the context switching mechanism. * - * "Check" task - The check task period is initially set to three seconds. The - * task checks that all the standard demo tasks, and the register check tasks, - * are not only still executing, but are executing without reporting any errors. - * If the check task discovers that a task has either stalled, or reported an - * error, then it changes its own execution period from the initial three - * seconds, to just 200ms. The check task also toggles an LED each time it is - * called. This provides a visual indication of the system status: If the LED - * toggles every five seconds, then no issues have been discovered. If the LED - * toggles every 200ms, then an issue has been discovered with at least one - * task. + * "Check" task - The check task period is set to five seconds. Each time it + * executes it checks all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors, + * then outputs the system status to the UART. */ /* Standard includes. */ @@ -130,11 +124,17 @@ #include "countsem.h" #include "GenQTest.h" #include "recmutex.h" -#include "partest.h" #include "IntQueue.h" #include "EventGroupsDemo.h" #include "TaskNotify.h" #include "IntSemTest.h" +#include "StaticAllocation.h" +#include "AbortDelay.h" +#include "QueueOverwrite.h" +#include "TimerDemo.h" + +/* Xilinx includes. */ +#include "xil_printf.h" /* Priorities for the demo application tasks. */ #define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 1 ) @@ -144,23 +144,14 @@ #define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * ( UBaseType_t ) 3 ) #define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 2 ) #define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - ( UBaseType_t ) 1 ) - -/* The LED used by the check task. */ -#define mainCHECK_LED ( 0 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) /* A block time of zero simply means "don't block". */ #define mainDONT_BLOCK ( ( TickType_t ) 0 ) -/* The period of the check task, in ms, provided no errors have been reported by -any of the standard demo tasks. ms are converted to the equivalent in ticks -using the pdMS_TO_TICKS() macro constant. */ +/* The period of the check task, in ms. */ #define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( ( TickType_t ) 5000 ) -/* The period of the check task, in ms, if an error has been reported in one of -the standard demo tasks. ms are converted to the equivalent in ticks using the -pdMS_TO_TICKS() macro. */ -#define mainERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( ( TickType_t ) ( 200 ) ) - /* Parameters that are passed into the register check tasks solely for the purpose of ensuring parameters are passed into tasks correctly. */ #define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) @@ -207,6 +198,13 @@ extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriori */ static void prvPseudoRandomiser( void *pvParameters ); +/* + * The full demo uses the tick hook function to include test code in the tick + * interrupt. vFullDemoTickHook() is called by vApplicationTickHook(), which + * is defined in main.c. + */ +void vFullDemoTickHook( void ); + /*-----------------------------------------------------------*/ /* The following two variables are used to communicate the status of the @@ -233,6 +231,10 @@ void main_full( void ) vStartEventGroupTasks(); vStartTaskNotifyTask(); vStartInterruptSemaphoreTasks(); + vStartStaticallyAllocatedTasks(); + vCreateAbortDelayTasks(); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); /* Create the register check tasks, as described at the top of this file */ xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); @@ -266,6 +268,7 @@ TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; TickType_t xLastExecutionTime; static uint64_t ullLastRegTest1Value = 0, ullLastRegTest2Value = 0; uint64_t ullErrorFound = pdFALSE; +const char *pcStatusString = "Pass"; /* Just to stop compiler warnings. */ ( void ) pvParameters; @@ -275,11 +278,8 @@ uint64_t ullErrorFound = pdFALSE; xLastExecutionTime = xTaskGetTickCount(); /* Cycle for ever, delaying then checking all the other tasks are still - operating without error. The onboard LED is toggled on each iteration. - If an error is detected then the delay period is decreased from - mainNO_ERROR_CHECK_TASK_PERIOD to mainERROR_CHECK_TASK_PERIOD. This has the - effect of increasing the rate at which the onboard LED toggles, and in so - doing gives visual feedback of the system status. */ + operating without error. The system status is written to the UART on each + iteration. */ for( ;; ) { /* Delay until it is time to execute again. */ @@ -290,85 +290,111 @@ uint64_t ullErrorFound = pdFALSE; if( xAreIntQueueTasksStillRunning() != pdTRUE ) { ullErrorFound |= 1ULL << 0ULL; + pcStatusString = "Error: IntQ"; } if( xAreMathsTaskStillRunning() != pdTRUE ) { ullErrorFound |= 1ULL << 1ULL; + pcStatusString = "Error: Math"; } if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) { ullErrorFound |= 1ULL << 2ULL; + pcStatusString = "Error: Dynamic"; } if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) { ullErrorFound |= 1ULL << 4ULL; + pcStatusString = "Error: Block Time"; } if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) { ullErrorFound |= 1ULL << 5ULL; + pcStatusString = "Error: Generic Queue"; } if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) { ullErrorFound |= 1ULL << 6ULL; + pcStatusString = "Error: Recursive Mutex"; } if( xAreSemaphoreTasksStillRunning() != pdTRUE ) { ullErrorFound |= 1ULL << 8ULL; + pcStatusString = "Error: Semaphore"; } if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) { ullErrorFound |= 1ULL << 10ULL; + pcStatusString = "Error: Counting Semaphore"; } if( xAreEventGroupTasksStillRunning() != pdPASS ) { ullErrorFound |= 1ULL << 12ULL; + pcStatusString = "Error: Event Group"; } if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) { ullErrorFound |= 1ULL << 13ULL; + pcStatusString = "Error: Task Notifications"; } if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) { ullErrorFound |= 1ULL << 14ULL; + pcStatusString = "Error: Interrupt Semaphore"; + } + + if( xAreStaticAllocationTasksStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 15ULL; + pcStatusString = "Error: Static Allocation"; + } + + if( xAreAbortDelayTestTasksStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 16ULL; + pcStatusString = "Error: Abort Delay"; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) + { + ullErrorFound |= 1ULL << 17ULL; + pcStatusString = "Error: Queue Overwrite"; + } + + if( xAreTimerDemoTasksStillRunning( xDelayPeriod ) != pdTRUE ) + { + ullErrorFound |= 1ULL << 18ULL; + pcStatusString = "Error: Timer Demo"; } /* Check that the register test 1 task is still running. */ if( ullLastRegTest1Value == ullRegTest1LoopCounter ) { - ullErrorFound |= 1ULL << 15ULL; + ullErrorFound |= 1ULL << 17ULL; + pcStatusString = "Error: Reg Test 1"; } ullLastRegTest1Value = ullRegTest1LoopCounter; /* Check that the register test 2 task is still running. */ if( ullLastRegTest2Value == ullRegTest2LoopCounter ) { - ullErrorFound |= 1ULL << 16ULL; + ullErrorFound |= 1ULL << 18ULL; + pcStatusString = "Error: Reg Test 2"; } ullLastRegTest2Value = ullRegTest2LoopCounter; - /* Toggle the check LED to give an indication of the system status. If - the LED toggles every mainNO_ERROR_CHECK_TASK_PERIOD milliseconds then - everything is ok. A faster toggle indicates an error. */ - vParTestToggleLED( mainCHECK_LED ); - - if( ullErrorFound != pdFALSE ) - { - /* An error has been detected in one of the tasks - flash the LED - at a higher frequency to give visible feedback that something has - gone wrong (it might just be that the loop back connector required - by the comtest tasks has not been fitted). */ - xDelayPeriod = mainERROR_CHECK_TASK_PERIOD; - } + /* Output the system status string. */ + xil_printf( "%s, status code = %lu, tick count = %lu\r\n", pcStatusString, ullErrorFound, xTaskGetTickCount() ); configASSERT( ullErrorFound == pdFALSE ); } @@ -451,9 +477,26 @@ volatile uint64_t ullNextRand = ( uint64_t ) &pvParameters, ullValue; } } } +/*-----------------------------------------------------------*/ +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Call the ISR component of the interrupt semaphore test. */ + vInterruptSemaphorePeriodicTest(); + + /* Call the code that 'gives' a task notification from an ISR. */ + xNotifyTaskFromISR(); +} diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c index 724d4328d..a2189fcf1 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c +++ b/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/main.c @@ -68,29 +68,14 @@ */ /****************************************************************************** - * This project provides two demo applications. A simple blinky style project, - * and a more comprehensive test and demo application. The - * mainSELECTED_APPLICATION setting (defined in this file) is used to select - * between the two. The simply blinky demo is implemented and described in - * main_blinky.c. The more comprehensive test and demo application is - * implemented and described in main_full.c. - * - * This file implements the code that is not demo specific, including the - * hardware setup and FreeRTOS hook functions. - * - * !!! IMPORTANT NOTE !!! - * Some GCC libraries can make use of the floating point registers. To avoid - * this causing corruption it is necessary to avoid their use. For this reason - * main.c contains very basic C implementations of the standard C library - * functions memset(), memcpy() and memcmp(), which are are used by FreeRTOS - * itself. Defining these functions in the project prevents the linker pulling - * them in from the library. Any other standard C library functions that are - * used by the application must likewise be defined in C. - * - * ENSURE TO READ THE DOCUMENTATION PAGE FOR THIS PORT AND DEMO APPLICATION ON - * THE http://www.FreeRTOS.org WEB SITE FOR FULL INFORMATION ON USING THIS DEMO - * APPLICATION, AND ITS ASSOCIATE FreeRTOS ARCHITECTURE PORT! + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainSELECTED_APPLICATION setting in main.c is used to select between the two. + * See the notes on using mainSELECTED_APPLICATION where it is defined below. * + * NOTE 2: This file only contains the source code that is not specific to + * either the simply blinky or full demos - this includes initialisation code + * and callback functions. */ /* Standard includes. */ @@ -99,14 +84,6 @@ /* Scheduler include files. */ #include "FreeRTOS.h" #include "task.h" -#include "semphr.h" - -/* Standard demo includes. */ -#include "partest.h" -#include "QueueOverwrite.h" -#include "EventGroupsDemo.h" -#include "TaskNotify.h" -#include "IntSemTest.h" /* Xilinx includes. */ #include "platform.h" @@ -122,7 +99,7 @@ * When mainSELECTED_APPLICATION is set to 1 the comprehensive test and demo * application will be run. */ -#define mainSELECTED_APPLICATION 0 +#define mainSELECTED_APPLICATION 1 /*-----------------------------------------------------------*/ @@ -249,46 +226,65 @@ volatile size_t xFreeHeapSpace; } /*-----------------------------------------------------------*/ -void vAssertCalled( const char * pcFile, unsigned long ulLine ) +void vApplicationTickHook( void ) { -volatile unsigned long ul = 0; - - ( void ) pcFile; - ( void ) ulLine; - - taskENTER_CRITICAL(); + #if( mainSELECTED_APPLICATION == 1 ) { - #if( configUSE_TRACE_FACILITY == 1 ) - { - vTraceStop(); - } - #endif - - /* Set ul to a non-zero value using the debugger to step out of this - function. */ - while( ul == 0 ) - { - portNOP(); - } + /* Only the comprehensive demo actually uses the tick hook. */ + extern void vFullDemoTickHook( void ); + vFullDemoTickHook(); } - taskEXIT_CRITICAL(); + #endif } /*-----------------------------------------------------------*/ -void vApplicationTickHook( void ) +/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an +implementation of vApplicationGetIdleTaskMemory() to provide the memory that is +used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) { - #if( mainSELECTED_APPLICATION == 1 ) - { - /* Call the periodic event group from ISR demo. */ - vPeriodicEventGroupsProcessing(); - - /* Use task notifications from an interrupt. */ - xNotifyTaskFromISR(); +/* If the buffers to be provided to the Idle task are declared inside this +function then they must be declared static - otherwise they will be allocated on +the stack and so not exists after this function exits. */ +static StaticTask_t xIdleTaskTCB; +static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*-----------------------------------------------------------*/ - /* Use mutexes from interrupts. */ - vInterruptSemaphorePeriodicTest(); - } - #endif +/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the +application must provide an implementation of vApplicationGetTimerTaskMemory() +to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) +{ +/* If the buffers to be provided to the Timer task are declared inside this +function then they must be declared static - otherwise they will be allocated on +the stack and so not exists after this function exits. */ +static StaticTask_t xTimerTaskTCB; +static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; } /*-----------------------------------------------------------*/ @@ -350,3 +346,10 @@ volatile size_t x; } /*-----------------------------------------------------------*/ +void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber ) +{ + xil_printf( "ASSERT! Line %lu of file %s\r\n", ulLineNumber, pcFileName ); + taskENTER_CRITICAL(); + for( ;; ); +} + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.cproject b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.cproject new file mode 100644 index 000000000..e67ed8330 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.cproject @@ -0,0 +1,178 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.project b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.project new file mode 100644 index 000000000..19cf84fa4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/.project @@ -0,0 +1,267 @@ + + + RTOSDemo_R5 + Created by SDK v2016.1. RTOSDemo_R5_bsp - psu_cortexr5_0 + + RTOSDemo_R5_bsp + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + src/FreeRTOS_Source + 2 + FREERTOS_ROOT/FreeRTOS/Source + + + src/Full_Demo/Standard_Demo_Tasks + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/Minimal + + + src/Full_Demo/Standard_Demo_Tasks/include + 2 + FREERTOS_ROOT/FreeRTOS/Demo/Common/include + + + + + 1462455164616 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-event_groups.c + + + + 1462455164616 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-list.c + + + + 1462455164726 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-queue.c + + + + 1462455164766 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-tasks.c + + + + 1462455164786 + src/FreeRTOS_Source + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-timers.c + + + + 1462455201203 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-MemMang + + + + 1462455201293 + src/FreeRTOS_Source/portable + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GCC + + + + 1462461825645 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-AbortDelay.c + + + + 1462461825653 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-blocktim.c + + + + 1462461825660 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-countsem.c + + + + 1462461825677 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-dynamic.c + + + + 1462461825687 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-EventGroupsDemo.c + + + + 1462461825706 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-flop.c + + + + 1462461825718 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-GenQTest.c + + + + 1462461825723 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntQueue.c + + + + 1462461825728 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-IntSemTest.c + + + + 1462461825733 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-recmutex.c + + + + 1462461825757 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-semtest.c + + + + 1462461825757 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-StaticAllocation.c + + + + 1462461825757 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TaskNotify.c + + + + 1462461825767 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-TimerDemo.c + + + + 1462461825787 + src/Full_Demo/Standard_Demo_Tasks + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-QueueOverwrite.c + + + + 1462455232956 + src/FreeRTOS_Source/portable/GCC + 9 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-ARM_CR5 + + + + 1462455929868 + src/FreeRTOS_Source/portable/MemMang + 5 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-heap_4.c + + + + + + FREERTOS_ROOT + $%7BPARENT-4-PROJECT_LOC%7D + + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Blinky_Demo/main_blinky.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Blinky_Demo/main_blinky.c new file mode 100644 index 000000000..d5d8aad77 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Blinky_Demo/main_blinky.c @@ -0,0 +1,227 @@ +/* + FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainSELECTED_APPLICATION setting in main.c is used to select between the + * two. See the notes on using mainSELECTED_APPLICATION in main.c. This file + * implements the simply blinky style version. + * + * NOTE 2: This file only contains the source code that is specific to the + * simple demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware are defined in main.c. + ****************************************************************************** + * + * main_blinky() creates one queue, and two tasks. It then starts the + * scheduler. + * + * The Queue Send Task: + * The queue send task is implemented by the prvQueueSendTask() function in + * this file. prvQueueSendTask() sits in a loop that causes it to repeatedly + * block for 200 milliseconds, before sending the value 100 to the queue that + * was created within main_blinky(). Once the value is sent, the task loops + * back around to block for another 200 milliseconds...and so on. + * + * The Queue Receive Task: + * The queue receive task is implemented by the prvQueueReceiveTask() function + * in this file. prvQueueReceiveTask() sits in a loop where it repeatedly + * blocks on attempts to read data from the queue that was created within + * main_blinky(). When data is received, the task checks the value of the + * data, and if the value equals the expected 100, outputs a message to the + * UART. The 'block time' parameter passed to the queue receive function + * specifies that the task should be held in the Blocked state indefinitely to + * wait for data to be available on the queue. The queue receive task will only + * leave the Blocked state when the queue send task writes to the queue. As the + * queue send task writes to the queue every 200 milliseconds, the queue receive + * task leaves the Blocked state every 200 milliseconds, and therefore outputs + * a message every 200 milliseconds. + */ + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" + +/* Xilinx includes. */ +#include "xil_printf.h" + +/* Priorities at which the tasks are created. */ +#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 ) +#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 ) + +/* The rate at which data is sent to the queue. The 200ms value is converted +to ticks using the portTICK_PERIOD_MS constant. */ +#define mainQUEUE_SEND_FREQUENCY_MS pdMS_TO_TICKS( 200 ) + +/* The number of items the queue can hold. This is 1 as the receive task +will remove items as they are added, meaning the send task should always find +the queue empty. */ +#define mainQUEUE_LENGTH ( 1 ) + +/*-----------------------------------------------------------*/ + +/* + * The tasks as described in the comments at the top of this file. + */ +static void prvQueueReceiveTask( void *pvParameters ); +static void prvQueueSendTask( void *pvParameters ); + +/*-----------------------------------------------------------*/ + +/* The queue used by both tasks. */ +static QueueHandle_t xQueue = NULL; + +/*-----------------------------------------------------------*/ + +void main_blinky( void ) +{ + /* Create the queue. */ + xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) ); + + if( xQueue != NULL ) + { + /* Start the two tasks as described in the comments at the top of this + file. */ + xTaskCreate( prvQueueReceiveTask, /* The function that implements the task. */ + "Rx", /* The text name assigned to the task - for debug only as it is not used by the kernel. */ + configMINIMAL_STACK_SIZE, /* The size of the stack to allocate to the task. */ + NULL, /* The parameter passed to the task - not used in this case. */ + mainQUEUE_RECEIVE_TASK_PRIORITY, /* The priority assigned to the task. */ + NULL ); /* The task handle is not required, so NULL is passed. */ + + xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL ); + + /* Start the tasks and timer running. */ + vTaskStartScheduler(); + } + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvQueueSendTask( void *pvParameters ) +{ +TickType_t xNextWakeTime; +const uint32_t ulValueToSend = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + /* Initialise xNextWakeTime - this only needs to be done once. */ + xNextWakeTime = xTaskGetTickCount(); + + for( ;; ) + { + /* Place this task in the blocked state until it is time to run again. */ + vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS ); + + /* Send to the queue - causing the queue receive task to unblock and + toggle the LED. 0 is used as the block time so the sending operation + will not block - it shouldn't need to block as the queue should always + be empty at this point in the code. */ + xQueueSend( xQueue, &ulValueToSend, 0U ); + } +} +/*-----------------------------------------------------------*/ + +static void prvQueueReceiveTask( void *pvParameters ) +{ +uint32_t ulReceivedValue; +const uint32_t ulExpectedValue = 100UL; + + /* Remove compiler warning about unused parameter. */ + ( void ) pvParameters; + + for( ;; ) + { + /* Wait until something arrives in the queue - this task will block + indefinitely provided INCLUDE_vTaskSuspend is set to 1 in + FreeRTOSConfig.h. */ + xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY ); + + /* To get here something must have been received from the queue, but is + it the expected value? If it is, toggle the LED. */ + if( ulReceivedValue == ulExpectedValue ) + { + xil_printf( "100 received\r\n" ); + ulReceivedValue = 0U; + } + } +} +/*-----------------------------------------------------------*/ + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOSConfig.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOSConfig.h new file mode 100644 index 000000000..2b8292a61 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOSConfig.h @@ -0,0 +1,222 @@ +/* + FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +#ifndef FREERTOS_CONFIG_H +#define FREERTOS_CONFIG_H + +#include "xparameters.h" + +/*----------------------------------------------------------- + * Application specific definitions. + * + * These definitions should be adjusted for your particular hardware and + * application requirements. + * + * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE + * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE. + * + * See http://www.freertos.org/a00110.html. + *----------------------------------------------------------*/ + +/* + * The FreeRTOS Cortex-A port implements a full interrupt nesting model. + * + * Interrupts that are assigned a priority at or below + * configMAX_API_CALL_INTERRUPT_PRIORITY (which counter-intuitively in the ARM + * generic interrupt controller [GIC] means a priority that has a numerical + * value above configMAX_API_CALL_INTERRUPT_PRIORITY) can call FreeRTOS safe API + * functions and will nest. + * + * Interrupts that are assigned a priority above + * configMAX_API_CALL_INTERRUPT_PRIORITY (which in the GIC means a numerical + * value below configMAX_API_CALL_INTERRUPT_PRIORITY) cannot call any FreeRTOS + * API functions, will nest, and will not be masked by FreeRTOS critical + * sections (although it is necessary for interrupts to be globally disabled + * extremely briefly as the interrupt mask is updated in the GIC). + * + * FreeRTOS functions that can be called from an interrupt are those that end in + * "FromISR". FreeRTOS maintains a separate interrupt safe API to enable + * interrupt entry to be shorter, faster, simpler and smaller. + * + * For the purpose of setting configMAX_API_CALL_INTERRUPT_PRIORITY 255 + * represents the lowest priority. + */ +#define configMAX_API_CALL_INTERRUPT_PRIORITY 18 + + +#define configCPU_CLOCK_HZ 100000000UL +#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1 +#define configUSE_TICKLESS_IDLE 0 +#define configTICK_RATE_HZ ( ( TickType_t ) 1000 ) +#define configPERIPHERAL_CLOCK_HZ ( 33333000UL ) +#define configUSE_PREEMPTION 1 +#define configUSE_IDLE_HOOK 1 +#define configUSE_TICK_HOOK 1 +#define configMAX_PRIORITIES ( 7 ) +#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 200 ) +#define configTOTAL_HEAP_SIZE ( 50 * 1024 ) +#define configMAX_TASK_NAME_LEN ( 10 ) +#define configUSE_TRACE_FACILITY 1 +#define configUSE_16_BIT_TICKS 0 +#define configIDLE_SHOULD_YIELD 1 +#define configUSE_MUTEXES 1 +#define configQUEUE_REGISTRY_SIZE 8 +#define configCHECK_FOR_STACK_OVERFLOW 2 +#define configUSE_RECURSIVE_MUTEXES 1 +#define configUSE_MALLOC_FAILED_HOOK 1 +#define configUSE_APPLICATION_TASK_TAG 0 +#define configUSE_COUNTING_SEMAPHORES 1 +#define configUSE_QUEUE_SETS 1 +#define configUSE_TASK_NOTIFICATIONS 1 + +/* This demo creates RTOS objects using both static and dynamic allocation. */ +#define configSUPPORT_STATIC_ALLOCATION 1 +#define configSUPPORT_DYNAMIC_ALLOCATION 1 /* Defaults to 1 anyway. */ + +/* Co-routine definitions. */ +#define configUSE_CO_ROUTINES 0 +#define configMAX_CO_ROUTINE_PRIORITIES ( 2 ) + +/* Software timer definitions. */ +#define configUSE_TIMERS 1 +#define configTIMER_TASK_PRIORITY ( configMAX_PRIORITIES - 1 ) +#define configTIMER_QUEUE_LENGTH 5 +#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 ) + +/* Set the following definitions to 1 to include the API function, or zero +to exclude the API function. */ +#define INCLUDE_vTaskPrioritySet 1 +#define INCLUDE_uxTaskPriorityGet 1 +#define INCLUDE_vTaskDelete 1 +#define INCLUDE_vTaskCleanUpResources 1 +#define INCLUDE_vTaskSuspend 1 +#define INCLUDE_vTaskDelayUntil 1 +#define INCLUDE_vTaskDelay 1 +#define INCLUDE_xTimerPendFunctionCall 1 +#define INCLUDE_eTaskGetState 1 +#define INCLUDE_xTaskAbortDelay 1 +#define INCLUDE_xTaskGetHandle 1 + +/* This demo makes use of one or more example stats formatting functions. These +format the raw data provided by the uxTaskGetSystemState() function in to human +readable ASCII form. See the notes in the implementation of vTaskList() within +FreeRTOS/Source/tasks.c for limitations. */ +#define configUSE_STATS_FORMATTING_FUNCTIONS 0 + +/* Run time stats are not generated. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS and +portGET_RUN_TIME_COUNTER_VALUE must be defined if configGENERATE_RUN_TIME_STATS +is set to 1. */ +#define configGENERATE_RUN_TIME_STATS 0 +#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() +#define portGET_RUN_TIME_COUNTER_VALUE() + +/* The size of the global output buffer that is available for use when there +are multiple command interpreters running at once (for example, one on a UART +and one on TCP/IP). This is done to prevent an output buffer being defined by +each implementation - which would waste RAM. In this case, there is only one +command interpreter running. */ +#define configCOMMAND_INT_MAX_OUTPUT_SIZE 2096 + +/* Normal assert() semantics without relying on the provision of an assert.h +header file. */ +void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber ); +#define configASSERT( x ) if( ( x ) == 0 ) { vMainAssertCalled( __FILE__, __LINE__ ); } + +/* If configTASK_RETURN_ADDRESS is not defined then a task that attempts to +return from its implementing function will end up in a "task exit error" +function - which contains a call to configASSERT(). However this can give GCC +some problems when it tries to unwind the stack, as the exit error function has +nothing to return to. To avoid this define configTASK_RETURN_ADDRESS to 0. */ +#define configTASK_RETURN_ADDRESS NULL + + +/****** Hardware specific settings. *******************************************/ + +/* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. This file contains a function + * that is suitable for use on the Zynq MPU. FreeRTOS_Tick_Handler() must + * be installed as the peripheral's interrupt handler. + */ +void vConfigureTickInterrupt( void ); +#define configSETUP_TICK_INTERRUPT() vConfigureTickInterrupt() + +void vClearTickInterrupt( void ); +#define configCLEAR_TICK_INTERRUPT() vClearTickInterrupt() + +/* The following constant describe the hardware, and are correct for the +Zynq MPU. */ +#define configINTERRUPT_CONTROLLER_BASE_ADDRESS ( XPAR_SCUGIC_0_DIST_BASEADDR ) +#define configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ( 0x1000 ) +#define configUNIQUE_INTERRUPT_PRIORITIES 32 + + +#endif /* FREERTOS_CONFIG_H */ + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOS_asm_vectors.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOS_asm_vectors.S new file mode 100644 index 000000000..14222fb20 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOS_asm_vectors.S @@ -0,0 +1,103 @@ +/****************************************************************************** +* +* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* @file asm_vectors.s +* +* This file contains the initial vector table for the Cortex R5 processor +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	02/10/14 Initial version
+*
+* +* @note +* +* None. +* +******************************************************************************/ +.org 0 +.text + +.globl _boot +.globl _freertos_vector_table + +.globl FreeRTOS_FIQInterrupt +.globl FreeRTOS_DataAbortHandler +.globl FreeRTOS_PrefetchAbortHandler +.globl vPortInstallFreeRTOSVectorTable + +.globl IRQHandler +.globl prof_pc + +.extern FreeRTOS_IRQ_Handler +.extern FreeRTOS_SWI_Handler + + +.section .freertos_vectors +_freertos_vector_table: + ldr pc,=_boot + ldr pc,=FreeRTOS_Undefined + LDR pc, _swi + ldr pc,=FreeRTOS_PrefetchAbortHandler + ldr pc,=FreeRTOS_DataAbortHandler + NOP /* Placeholder for address exception vector*/ + LDR pc, _irq + ldr pc,=FreeRTOS_FIQHandler + +_irq: .word FreeRTOS_IRQ_Handler +_swi: .word FreeRTOS_SWI_Handler + + +.text + +FreeRTOS_FIQHandler: /* FIQ vector handler */ + stmdb sp!,{r0-r3,r12,lr} /* state save from compiled code */ +FreeRTOS_FIQLoop: + bl FIQInterrupt /* FIQ vector */ + ldmia sp!,{r0-r3,r12,lr} /* state restore from compiled code */ + subs pc, lr, #4 /* adjust return */ + +FreeRTOS_Undefined: /* Undefined handler */ + b FreeRTOS_Undefined + +FreeRTOS_DataAbortHandler: /* Data Abort handler */ + b FreeRTOS_DataAbortHandler + +FreeRTOS_PrefetchAbortHandler: /* Prefetch Abort handler */ + b FreeRTOS_PrefetchAbortHandler + + +.end diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOS_tick_config.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOS_tick_config.c new file mode 100644 index 000000000..e55323fd6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/FreeRTOS_tick_config.c @@ -0,0 +1,177 @@ +/* + FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" +#include "Task.h" + +/* Xilinx includes. */ +#include "xscugic.h" +#include "xttcps.h" + +/* Settings to generate the tick from channel 0 of TTC 0. */ +#define tickTTC_ID XPAR_PSU_TTC_0_DEVICE_ID +#define tickINTERRUPT_ID XPAR_XTTCPS_0_INTR + +/* The timer used to generate the tick interrupt. */ +static XTtcPs xTimerInstance; + +/* + * The application must provide a function that configures a peripheral to + * create the FreeRTOS tick interrupt, then define configSETUP_TICK_INTERRUPT() + * in FreeRTOSConfig.h to call the function. This file contains a function + * that is suitable for use on the Zynq SoC. + */ +void vConfigureTickInterrupt( void ) +{ +XTtcPs_Config *pxTimerConfig; +BaseType_t xStatus; +XScuGic_Config *pxGICConfig; +static XScuGic xInterruptController; /* Interrupt controller instance */ +uint16_t usInterval; +uint8_t ucPrescale = 0; +const uint8_t ucRisingEdge = 3; + + /* This function is called with the IRQ interrupt disabled, and the IRQ + interrupt should be left disabled. It is enabled automatically when the + scheduler is started. */ + + /* Ensure XScuGic_CfgInitialize() has been called. In this demo it has + already been called from prvSetupHardware() in main(). */ + pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID ); + xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ + + /* The interrupt priority must be the lowest possible. */ + XScuGic_SetPriorityTriggerType( &xInterruptController, tickINTERRUPT_ID, portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT, ucRisingEdge ); + + /* Install the FreeRTOS tick handler. */ + xStatus = XScuGic_Connect( &xInterruptController, tickINTERRUPT_ID, (Xil_ExceptionHandler) FreeRTOS_Tick_Handler, NULL ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ + + /* Initialise the Triple Timer Counter (TTC) that is going to be used to + generate the tick interrupt. */ + pxTimerConfig = XTtcPs_LookupConfig( tickTTC_ID ); + xStatus = XTtcPs_CfgInitialize( &xTimerInstance, pxTimerConfig, pxTimerConfig->BaseAddress ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ + + /* Configure the interval to be the require tick rate. */ + XTtcPs_CalcIntervalFromFreq( &xTimerInstance, configTICK_RATE_HZ, &usInterval, &ucPrescale ); + XTtcPs_SetInterval( &xTimerInstance, usInterval ); + XTtcPs_SetPrescaler( &xTimerInstance, ucPrescale ); + + /* Interval mode used. */ + XTtcPs_SetOptions( &xTimerInstance, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE ); + + /* Start the timer. */ + XTtcPs_Start( &xTimerInstance ); + + /* Enable the interrupt in the interrupt controller. */ + XScuGic_Enable( &xInterruptController, tickINTERRUPT_ID ); + + /* Enable the interrupt in the timer itself. */ + XTtcPs_EnableInterrupts( &xTimerInstance, XTTCPS_IXR_INTERVAL_MASK ); +} +/*-----------------------------------------------------------*/ + +void vClearTickInterrupt( void ) +{ +volatile uint32_t ulStatus; + + ulStatus = XTtcPs_GetInterruptStatus( &xTimerInstance ); + ( void ) ulStatus; +} +/*-----------------------------------------------------------*/ + +void vApplicationIRQHandler( uint32_t ulICCIAR ) +{ +extern const XScuGic_Config XScuGic_ConfigTable[]; +static const XScuGic_VectorTableEntry *pxVectorTable = XScuGic_ConfigTable[ XPAR_SCUGIC_SINGLE_DEVICE_ID ].HandlerTable; +uint32_t ulInterruptID; +const XScuGic_VectorTableEntry *pxVectorEntry; + + /* Re-enable interrupts. */ + __asm ( "cpsie i" ); + + /* The ID of the interrupt is obtained by bitwise anding the ICCIAR value + with 0x3FF. */ + ulInterruptID = ulICCIAR & 0x3FFUL; + if( ulInterruptID < XSCUGIC_MAX_NUM_INTR_INPUTS ) + { + /* Call the function installed in the array of installed handler + functions. */ + pxVectorEntry = &( pxVectorTable[ ulInterruptID ] ); + pxVectorEntry->Handler( pxVectorEntry->CallBackRef ); + } +} + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/IntQueueTimer.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/IntQueueTimer.c new file mode 100644 index 000000000..732b7cea7 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/IntQueueTimer.c @@ -0,0 +1,266 @@ +/* + FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/* + * This file initialises three timers as follows: + * + * Timer 0 and Timer 1 provide the interrupts that are used with the IntQ + * standard demo tasks, which test interrupt nesting and using queues from + * interrupts. Both these interrupts operate below the maximum syscall + * interrupt priority. + * + * Timer 2 is a much higher frequency timer that tests the nesting of interrupts + * that execute above the maximum syscall interrupt priority. + * + * All the timers can nest with the tick interrupt - creating a maximum + * interrupt nesting depth of 4. + * + * For convenience, the high frequency timer is also used to provide the time + * base for the run time stats. + */ + +/* Scheduler includes. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Demo includes. */ +#include "IntQueueTimer.h" +#include "IntQueue.h" + +/* Xilinx includes. */ +#include "xttcps.h" +#include "xscugic.h" + +/* The frequencies at which the first two timers expire are slightly offset to +ensure they don't remain synchronised. The frequency of the interrupt that +operates above the max syscall interrupt priority is 10 times faster so really +hammers the interrupt entry and exit code. */ +#define tmrTIMERS_USED 3 +#define tmrTIMER_0_FREQUENCY ( 2000UL ) +#define tmrTIMER_1_FREQUENCY ( 2001UL ) +#define tmrTIMER_2_FREQUENCY ( 20000UL ) + +/*-----------------------------------------------------------*/ + +/* + * The single interrupt service routines that is used to service all three + * timers. + */ +static void prvTimerHandler( void *CallBackRef ); + +/*-----------------------------------------------------------*/ + +/* Hardware constants. */ +static const BaseType_t xDeviceIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_2_DEVICE_ID, XPAR_XTTCPS_3_DEVICE_ID, XPAR_XTTCPS_4_DEVICE_ID }; +static const BaseType_t xInterruptIDs[ tmrTIMERS_USED ] = { XPAR_XTTCPS_2_INTR, XPAR_XTTCPS_3_INTR, XPAR_XTTCPS_4_INTR }; + +/* Timer configuration settings. */ +typedef struct +{ + uint32_t OutputHz; /* Output frequency. */ + uint16_t Interval; /* Interval value. */ + uint8_t Prescaler; /* Prescaler value. */ + uint16_t Options; /* Option settings. */ +} TmrCntrSetup; + +static TmrCntrSetup xTimerSettings[ tmrTIMERS_USED ] = +{ + { tmrTIMER_0_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }, + { tmrTIMER_1_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE }, + { tmrTIMER_2_FREQUENCY, 0, 0, XTTCPS_OPTION_INTERVAL_MODE | XTTCPS_OPTION_WAVE_DISABLE } +}; + +/* Lower priority number means higher logical priority, so +configMAX_API_CALL_INTERRUPT_PRIORITY - 1 is above the maximum system call +interrupt priority. */ +static const UBaseType_t uxInterruptPriorities[ tmrTIMERS_USED ] = +{ + configMAX_API_CALL_INTERRUPT_PRIORITY + 1, + configMAX_API_CALL_INTERRUPT_PRIORITY, + configMAX_API_CALL_INTERRUPT_PRIORITY - 1 +}; + +static XTtcPs xTimerInstances[ tmrTIMERS_USED ]; + +/* Used to provide a means of ensuring the intended interrupt nesting depth is +actually being reached. */ +extern uint32_t ulPortInterruptNesting; +static uint32_t ulMaxRecordedNesting = 0; + +/* Used to ensure the high frequency timer is running at the expected +frequency. */ +static volatile uint32_t ulHighFrequencyTimerCounts = 0; + +/*-----------------------------------------------------------*/ + +void vInitialiseTimerForIntQueueTest( void ) +{ +BaseType_t xStatus; +TmrCntrSetup *pxTimerSettings; +extern XScuGic xInterruptController; +BaseType_t xTimer; +XTtcPs *pxTimerInstance; +XTtcPs_Config *pxTimerConfiguration; +const uint8_t ucRisingEdge = 3; + + for( xTimer = 0; xTimer < tmrTIMERS_USED; xTimer++ ) + { + /* Look up the timer's configuration. */ + pxTimerInstance = &( xTimerInstances[ xTimer ] ); + pxTimerConfiguration = XTtcPs_LookupConfig( xDeviceIDs[ xTimer ] ); + configASSERT( pxTimerConfiguration ); + + pxTimerSettings = &( xTimerSettings[ xTimer ] ); + + /* Initialise the device. */ + xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress ); + if( xStatus != XST_SUCCESS ) + { + /* Not sure how to do this before XTtcPs_CfgInitialize is called + as pxTimerInstance is set within XTtcPs_CfgInitialize(). */ + XTtcPs_Stop( pxTimerInstance ); + xStatus = XTtcPs_CfgInitialize( pxTimerInstance, pxTimerConfiguration, pxTimerConfiguration->BaseAddress ); + configASSERT( xStatus == XST_SUCCESS ); + } + + /* Set the options. */ + XTtcPs_SetOptions( pxTimerInstance, pxTimerSettings->Options ); + + /* The timer frequency is preset in the pxTimerSettings structure. + Derive the values for the other structure members. */ + XTtcPs_CalcIntervalFromFreq( pxTimerInstance, pxTimerSettings->OutputHz, &( pxTimerSettings->Interval ), &( pxTimerSettings->Prescaler ) ); + + /* Set the interval and prescale. */ + XTtcPs_SetInterval( pxTimerInstance, pxTimerSettings->Interval ); + XTtcPs_SetPrescaler( pxTimerInstance, pxTimerSettings->Prescaler ); + + /* The priority must be the lowest possible. */ + XScuGic_SetPriorityTriggerType( &xInterruptController, xInterruptIDs[ xTimer ], uxInterruptPriorities[ xTimer ] << portPRIORITY_SHIFT, ucRisingEdge ); + + /* Connect to the interrupt controller. */ + xStatus = XScuGic_Connect( &xInterruptController, xInterruptIDs[ xTimer ], ( Xil_InterruptHandler ) prvTimerHandler, ( void * ) pxTimerInstance ); + configASSERT( xStatus == XST_SUCCESS); + + /* Enable the interrupt in the GIC. */ + XScuGic_Enable( &xInterruptController, xInterruptIDs[ xTimer ] ); + + /* Enable the interrupts in the timer. */ + XTtcPs_EnableInterrupts( pxTimerInstance, XTTCPS_IXR_INTERVAL_MASK ); + + /* Start the timer. */ + XTtcPs_Start( pxTimerInstance ); + } +} +/*-----------------------------------------------------------*/ + +static void prvTimerHandler( void *pvCallBackRef ) +{ +uint32_t ulInterruptStatus; +XTtcPs *pxTimer = ( XTtcPs * ) pvCallBackRef; +BaseType_t xYieldRequired; + + /* Read the interrupt status, then write it back to clear the interrupt. */ + ulInterruptStatus = XTtcPs_GetInterruptStatus( pxTimer ); + XTtcPs_ClearInterruptStatus( pxTimer, ulInterruptStatus ); + + /* Only one interrupt event type is expected. */ + configASSERT( ( XTTCPS_IXR_INTERVAL_MASK & ulInterruptStatus ) != 0 ); + + /* Check the device ID to know which IntQueue demo to call. */ + if( pxTimer->Config.DeviceId == xDeviceIDs[ 0 ] ) + { + xYieldRequired = xFirstTimerHandler(); + } + else if( pxTimer->Config.DeviceId == xDeviceIDs[ 1 ] ) + { + xYieldRequired = xSecondTimerHandler(); + } + else + { + /* Used to check the timer is running at the expected frequency. */ + ulHighFrequencyTimerCounts++; + + /* Latch the highest interrupt nesting count detected. */ + if( ulPortInterruptNesting > ulMaxRecordedNesting ) + { + ulMaxRecordedNesting = ulPortInterruptNesting; + } + + xYieldRequired = pdFALSE; + } + + /* If xYieldRequired is not pdFALSE then calling either xFirstTimerHandler() + or xSecondTimerHandler() resulted in a task leaving the blocked state and + the task that left the blocked state had a priority higher than the currently + running task (the task this interrupt interrupted) - so a context switch + should be performed so the interrupt returns directly to the higher priority + task. xYieldRequired is tested inside the following macro. */ + portYIELD_FROM_ISR( xYieldRequired ); +} + diff --git a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/ParTest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/IntQueueTimer.h similarity index 80% rename from FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/ParTest.c rename to FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/IntQueueTimer.h index 439cef6cd..4b16bc503 100644 --- a/FreeRTOS/Demo/CORTEX_A53_64-bit_UltraScale_MPSoC/RTOSDemo_A53/src/ParTest.c +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/IntQueueTimer.h @@ -67,39 +67,12 @@ 1 tab == 4 spaces! */ -/*----------------------------------------------------------- - * Simple IO routines to control the LEDs. - * This file is called ParTest.c for historic reasons. Originally it stood for - * PARallel port TEST. - *-----------------------------------------------------------*/ - -/* Scheduler includes. */ -#include "FreeRTOS.h" -#include "task.h" - -/* Demo includes. */ -#include "partest.h" - - -/* Don't have any real LEDs yet! */ -volatile uint64_t ullLEDToggles = 0; - -/*-----------------------------------------------------------*/ - -void vParTestInitialise( void ) -{ -} -/*-----------------------------------------------------------*/ - -void vParTestSetLED( UBaseType_t uxLED, BaseType_t xValue ) -{ -} -/*-----------------------------------------------------------*/ - -void vParTestToggleLED( unsigned portBASE_TYPE uxLED ) -{ - ullLEDToggles++; -} +#ifndef INT_QUEUE_TIMER_H +#define INT_QUEUE_TIMER_H +void vInitialiseTimerForIntQueueTest( void ); +portBASE_TYPE xTimer0Handler( void ); +portBASE_TYPE xTimer1Handler( void ); +#endif diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c new file mode 100644 index 000000000..73a4dc06a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/main_full.c @@ -0,0 +1,502 @@ +/* + FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainSELECTED_APPLICATION setting in main.c is used to select between the two. + * See the notes on using mainSELECTED_APPLICATION in main.c. This file + * implements the comprehensive version. + * + * NOTE 2: This file only contains the source code that is specific to the + * full demo. Generic functions, such FreeRTOS hook functions, and functions + * required to configure the hardware, are defined in main.c. + * + * NOTE 3: The full demo includes a test that checks the floating point context + * is maintained correctly across task switches. The standard GCC libraries can + * use floating point registers and made this test fail (unless the tasks that + * use the library are given a floating point context as described on the + * documentation page for this demo). + * + ****************************************************************************** + * + * main_full() creates all the demo application tasks and software timers, then + * starts the scheduler. The web documentation provides more details of the + * standard demo application tasks, which provide no particular functionality, + * but do provide a good example of how to use the FreeRTOS API. + * + * In addition to the standard demo tasks, the following tasks and tests are + * defined and/or created within this file: + * + * "Reg test" tasks - These fill both the core and floating point registers with + * known values, then check that each register maintains its expected value for + * the lifetime of the task. Each task uses a different set of values. The reg + * test tasks execute with a very low priority, so get preempted very + * frequently. A register containing an unexpected value is indicative of an + * error in the context switching mechanism. + * + * "Check" task - The check task period is set to five seconds. Each time it + * executes it checks all the standard demo tasks, and the register check tasks, + * are not only still executing, but are executing without reporting any errors, + * then outputs the system status to the UART. + */ + +/* Standard includes. */ +#include + +/* Kernel includes. */ +#include "FreeRTOS.h" +#include "task.h" +#include "timers.h" +#include "semphr.h" + +/* Standard demo application includes. */ +#include "flop.h" +#include "semtest.h" +#include "dynamic.h" +#include "blocktim.h" +#include "countsem.h" +#include "GenQTest.h" +#include "recmutex.h" +#include "IntQueue.h" +#include "EventGroupsDemo.h" +#include "TaskNotify.h" +#include "IntSemTest.h" +#include "StaticAllocation.h" +#include "AbortDelay.h" +#include "QueueOverwrite.h" +#include "TimerDemo.h" + +/* Xilinx includes. */ +#include "xil_printf.h" + +/* Priorities for the demo application tasks. */ +#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 1 ) +#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 2 ) +#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 3 ) +#define mainFLOP_TASK_PRIORITY ( tskIDLE_PRIORITY ) +#define mainUART_COMMAND_CONSOLE_STACK_SIZE ( configMINIMAL_STACK_SIZE * ( UBaseType_t ) 3 ) +#define mainCOM_TEST_TASK_PRIORITY ( tskIDLE_PRIORITY + ( UBaseType_t ) 2 ) +#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - ( UBaseType_t ) 1 ) +#define mainQUEUE_OVERWRITE_PRIORITY ( tskIDLE_PRIORITY ) + +/* A block time of zero simply means "don't block". */ +#define mainDONT_BLOCK ( ( TickType_t ) 0 ) + +/* The period of the check task, in ms. */ +#define mainNO_ERROR_CHECK_TASK_PERIOD pdMS_TO_TICKS( ( TickType_t ) 5000 ) + +/* Parameters that are passed into the register check tasks solely for the +purpose of ensuring parameters are passed into tasks correctly. */ +#define mainREG_TEST_TASK_1_PARAMETER ( ( void * ) 0x12345678 ) +#define mainREG_TEST_TASK_2_PARAMETER ( ( void * ) 0x87654321 ) + +/* The base period used by the timer test tasks. */ +#define mainTIMER_TEST_PERIOD ( 50 ) + +/*-----------------------------------------------------------*/ + + +/* + * The check task, as described at the top of this file. + */ +static void prvCheckTask( void *pvParameters ); + +/* + * Register check tasks, and the tasks used to write over and check the contents + * of the FPU registers, as described at the top of this file. The nature of + * these files necessitates that they are written in an assembly file, but the + * entry points are kept in the C file for the convenience of checking the task + * parameter. + */ +static void prvRegTestTaskEntry1( void *pvParameters ); +extern void vRegTest1Implementation( void ); +static void prvRegTestTaskEntry2( void *pvParameters ); +extern void vRegTest2Implementation( void ); + +/* + * Register commands that can be used with FreeRTOS+CLI. The commands are + * defined in CLI-Commands.c and File-Related-CLI-Command.c respectively. + */ +extern void vRegisterSampleCLICommands( void ); + +/* + * The task that manages the FreeRTOS+CLI input and output. + */ +extern void vUARTCommandConsoleStart( uint16_t usStackSize, UBaseType_t uxPriority ); + +/* + * A high priority task that does nothing other than execute at a pseudo random + * time to ensure the other test tasks don't just execute in a repeating + * pattern. + */ +static void prvPseudoRandomiser( void *pvParameters ); + +/* + * The full demo uses the tick hook function to include test code in the tick + * interrupt. vFullDemoTickHook() is called by vApplicationTickHook(), which + * is defined in main.c. + */ +void vFullDemoTickHook( void ); + +/*-----------------------------------------------------------*/ + +/* The following two variables are used to communicate the status of the +register check tasks to the check task. If the variables keep incrementing, +then the register check tasks have not discovered any errors. If a variable +stops incrementing, then an error has been found. */ +volatile uint32_t ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL; + +/*-----------------------------------------------------------*/ + +void main_full( void ) +{ + /* Start all the other standard demo/test tasks. They have no particular + functionality, but do demonstrate how to use the FreeRTOS API and test the + kernel port. */ + vStartInterruptQueueTasks(); + vStartDynamicPriorityTasks(); + vCreateBlockTimeTasks(); + vStartCountingSemaphoreTasks(); + vStartGenericQueueTasks( tskIDLE_PRIORITY ); + vStartRecursiveMutexTasks(); + vStartSemaphoreTasks( mainSEM_TEST_PRIORITY ); + vStartMathTasks( mainFLOP_TASK_PRIORITY ); + vStartEventGroupTasks(); + vStartTaskNotifyTask(); + vStartInterruptSemaphoreTasks(); + vStartStaticallyAllocatedTasks(); + vCreateAbortDelayTasks(); + vStartQueueOverwriteTask( mainQUEUE_OVERWRITE_PRIORITY ); + vStartTimerDemoTask( mainTIMER_TEST_PERIOD ); + + /* Create the register check tasks, as described at the top of this file */ + xTaskCreate( prvRegTestTaskEntry1, "Reg1", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_1_PARAMETER, tskIDLE_PRIORITY, NULL ); + xTaskCreate( prvRegTestTaskEntry2, "Reg2", configMINIMAL_STACK_SIZE, mainREG_TEST_TASK_2_PARAMETER, tskIDLE_PRIORITY, NULL ); + + /* Create the task that just adds a little random behaviour. */ + xTaskCreate( prvPseudoRandomiser, "Rnd", configMINIMAL_STACK_SIZE, NULL, configMAX_PRIORITIES - 1, NULL ); + + /* Create the task that performs the 'check' functionality, as described at + the top of this file. */ + xTaskCreate( prvCheckTask, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL ); + + /* Start the scheduler. */ + vTaskStartScheduler(); + + /* If all is well, the scheduler will now be running, and the following + line will never be reached. If the following line does execute, then + there was either insufficient FreeRTOS heap memory available for the idle + and/or timer tasks to be created, or vTaskStartScheduler() was called from + User mode. See the memory management section on the FreeRTOS web site for + more details on the FreeRTOS heap http://www.freertos.org/a00111.html. The + mode from which main() is called is set in the C start up code and must be + a privileged mode (not user mode). */ + for( ;; ); +} +/*-----------------------------------------------------------*/ + +static void prvCheckTask( void *pvParameters ) +{ +TickType_t xDelayPeriod = mainNO_ERROR_CHECK_TASK_PERIOD; +TickType_t xLastExecutionTime; +static uint32_t ulLastRegTest1Value = 0, ulLastRegTest2Value = 0; +uint32_t ulErrorFound = pdFALSE; +const char *pcStatusString = "Pass"; + + /* Just to stop compiler warnings. */ + ( void ) pvParameters; + + /* Initialise xLastExecutionTime so the first call to vTaskDelayUntil() + works correctly. */ + xLastExecutionTime = xTaskGetTickCount(); + + /* Cycle for ever, delaying then checking all the other tasks are still + operating without error. The system status is written to the UART on each + iteration. */ + for( ;; ) + { + /* Delay until it is time to execute again. */ + vTaskDelayUntil( &xLastExecutionTime, xDelayPeriod ); + + /* Check all the demo tasks (other than the flash tasks) to ensure + that they are all still running, and that none have detected an error. */ + if( xAreIntQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 0UL; + pcStatusString = "Error: IntQ"; + } + + if( xAreMathsTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 1UL; + pcStatusString = "Error: Math"; + } + + if( xAreDynamicPriorityTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 2UL; + pcStatusString = "Error: Dynamic"; + } + + if ( xAreBlockTimeTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 4UL; + pcStatusString = "Error: Block Time"; + } + + if ( xAreGenericQueueTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 5UL; + pcStatusString = "Error: Generic Queue"; + } + + if ( xAreRecursiveMutexTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 6UL; + pcStatusString = "Error: Recursive Mutex"; + } + + if( xAreSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 8UL; + pcStatusString = "Error: Semaphore"; + } + + if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 10UL; + pcStatusString = "Error: Counting Semaphore"; + } + + if( xAreEventGroupTasksStillRunning() != pdPASS ) + { + ulErrorFound |= 1UL << 12UL; + pcStatusString = "Error: Event Group"; + } + + if( xAreTaskNotificationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 13UL; + pcStatusString = "Error: Task Notifications"; + } + + if( xAreInterruptSemaphoreTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 14UL; + pcStatusString = "Error: Interrupt Semaphore"; + } + + if( xAreStaticAllocationTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 15UL; + pcStatusString = "Error: Static Allocation"; + } + + if( xAreAbortDelayTestTasksStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 16UL; + pcStatusString = "Error: Abort Delay"; + } + + if( xIsQueueOverwriteTaskStillRunning() != pdTRUE ) + { + ulErrorFound |= 1UL << 17UL; + pcStatusString = "Error: Queue Overwrite"; + } + + if( xAreTimerDemoTasksStillRunning( xDelayPeriod ) != pdTRUE ) + { + ulErrorFound |= 1UL << 18UL; + pcStatusString = "Error: Timer Demo"; + } + + /* Check that the register test 1 task is still running. */ + if( ulLastRegTest1Value == ulRegTest1LoopCounter ) + { + ulErrorFound |= 1UL << 19UL; + pcStatusString = "Error: Reg Test 1"; + } + ulLastRegTest1Value = ulRegTest1LoopCounter; + + /* Check that the register test 2 task is still running. */ + if( ulLastRegTest2Value == ulRegTest2LoopCounter ) + { + ulErrorFound |= 1UL << 20UL; + pcStatusString = "Error: Reg Test 2"; + } + ulLastRegTest2Value = ulRegTest2LoopCounter; + + /* Output the system status string. */ + xil_printf( "%s, status code = %lu, tick count = %lu\r\n", pcStatusString, ulErrorFound, xTaskGetTickCount() ); + + configASSERT( ulErrorFound == pdFALSE ); + } +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry1( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_1_PARAMETER ) + { + /* The reg test task also tests the floating point registers. Tasks + that use the floating point unit must call vPortTaskUsesFPU() before + any floating point instructions are executed. */ + vPortTaskUsesFPU(); + + /* Start the part of the test that is written in assembler. */ + vRegTest1Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check task will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvRegTestTaskEntry2( void *pvParameters ) +{ + /* Although the regtest task is written in assembler, its entry point is + written in C for convenience of checking the task parameter is being passed + in correctly. */ + if( pvParameters == mainREG_TEST_TASK_2_PARAMETER ) + { + /* The reg test task also tests the floating point registers. Tasks + that use the floating point unit must call vPortTaskUsesFPU() before + any floating point instructions are executed. */ + vPortTaskUsesFPU(); + + /* Start the part of the test that is written in assembler. */ + vRegTest2Implementation(); + } + + /* The following line will only execute if the task parameter is found to + be incorrect. The check task will detect that the regtest loop counter is + not being incremented and flag an error. */ + vTaskDelete( NULL ); +} +/*-----------------------------------------------------------*/ + +static void prvPseudoRandomiser( void *pvParameters ) +{ +const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL, ulMinDelay = pdMS_TO_TICKS( 95 ); +volatile uint32_t ulNextRand = ( uint32_t ) &pvParameters, ulValue; + + /* This task does nothing other than ensure there is a little bit of + disruption in the scheduling pattern of the other tasks. Normally this is + done by generating interrupts at pseudo random times. */ + for( ;; ) + { + ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement; + ulValue = ( ulNextRand >> 16UL ) & 0xffUL; + + if( ulValue < ulMinDelay ) + { + ulValue = ulMinDelay; + } + + vTaskDelay( ulValue ); + + while( ulValue > 0 ) + { + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + __asm volatile( "NOP" ); + ulValue--; + } + } +} +/*-----------------------------------------------------------*/ + +void vFullDemoTickHook( void ) +{ + /* The full demo includes a software timer demo/test that requires + prodding periodically from the tick interrupt. */ + vTimerPeriodicISRTests(); + + /* Call the periodic queue overwrite from ISR demo. */ + vQueueOverwritePeriodicISRDemo(); + + /* Call the periodic event group from ISR demo. */ + vPeriodicEventGroupsProcessing(); + + /* Call the ISR component of the interrupt semaphore test. */ + vInterruptSemaphorePeriodicTest(); + + /* Call the code that 'gives' a task notification from an ISR. */ + xNotifyTaskFromISR(); +} + + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/reg_test.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/reg_test.S new file mode 100644 index 000000000..3393005af --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/Full_Demo/reg_test.S @@ -0,0 +1,462 @@ +/* + FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. + + FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT + http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + *************************************************************************** + * * + * FreeRTOS tutorial books are available in pdf and paperback. * + * Complete, revised, and edited pdf reference manuals are also * + * available. * + * * + * Purchasing FreeRTOS documentation will not only help you, by * + * ensuring you get running as quickly as possible and with an * + * in-depth knowledge of how to use FreeRTOS, it will also help * + * the FreeRTOS project to continue with its mission of providing * + * professional grade, cross platform, de facto standard solutions * + * for microcontrollers - completely free of charge! * + * * + * >>> See http://www.FreeRTOS.org/Documentation for details. <<< * + * * + * Thank you for using FreeRTOS, and thank you for your support! * + * * + *************************************************************************** + + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation AND MODIFIED BY the FreeRTOS exception. + + >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to + distribute a combined work that includes FreeRTOS without being obliged to + provide the source code for proprietary components outside of the FreeRTOS + kernel. + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. See the GNU General Public License for more + details. You should have received a copy of the GNU General Public License + and the FreeRTOS license exception along with FreeRTOS; if not itcan be + viewed here: http://www.freertos.org/a00114.html and also obtained by + writing to Real Time Engineers Ltd., contact details for whom are available + on the FreeRTOS WEB site. + + 1 tab == 4 spaces! + + *************************************************************************** + * * + * Having a problem? Start by reading the FAQ "My application does * + * not run, what could be wrong?" * + * * + * http://www.FreeRTOS.org/FAQHelp.html * + * * + *************************************************************************** + + + http://www.FreeRTOS.org - Documentation, books, training, latest versions, + license and Real Time Engineers Ltd. contact details. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, and our new + fully thread aware and reentrant UDP/IP stack. + + http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High + Integrity Systems, who sell the code with commercial support, + indemnification and middleware, under the OpenRTOS brand. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. +*/ + + .global vRegTest1Implementation + .global vRegTest2Implementation + .extern ulRegTest1LoopCounter + .extern ulRegTest2LoopCounter + + .text + .arm + + /* This function is explained in the comments at the top of main-full.c. */ +.type vRegTest1Implementation, %function +vRegTest1Implementation: + + /* Fill each general purpose register with a known value. */ + mov r0, #0xFF + mov r1, #0x11 + mov r2, #0x22 + mov r3, #0x33 + mov r4, #0x44 + mov r5, #0x55 + mov r6, #0x66 + mov r7, #0x77 + mov r8, #0x88 + mov r9, #0x99 + mov r10, #0xAA + mov r11, #0xBB + mov r12, #0xCC + mov r14, #0xEE + + /* Fill each FPU register with a known value. */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + + /* Loop, checking each iteration that each register still contains the + expected value. */ +reg1_loop: + /* Yield to increase test coverage */ + svc 0 + + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d1 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d2 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d3 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + vmov r0, r1, d4 + cmp r0, #0x88 + bne reg1_error_loopf + cmp r1, #0x99 + bne reg1_error_loopf + vmov r0, r1, d5 + cmp r0, #0xAA + bne reg1_error_loopf + cmp r1, #0xBB + bne reg1_error_loopf + vmov r0, r1, d6 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d7 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d8 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d9 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + vmov r0, r1, d10 + cmp r0, #0x88 + bne reg1_error_loopf + cmp r1, #0x99 + bne reg1_error_loopf + vmov r0, r1, d11 + cmp r0, #0xAA + bne reg1_error_loopf + cmp r1, #0xBB + bne reg1_error_loopf + vmov r0, r1, d12 + cmp r0, #0xFF + bne reg1_error_loopf + cmp r1, #0x11 + bne reg1_error_loopf + vmov r0, r1, d13 + cmp r0, #0x22 + bne reg1_error_loopf + cmp r1, #0x33 + bne reg1_error_loopf + vmov r0, r1, d14 + cmp r0, #0x44 + bne reg1_error_loopf + cmp r1, #0x55 + bne reg1_error_loopf + vmov r0, r1, d15 + cmp r0, #0x66 + bne reg1_error_loopf + cmp r1, #0x77 + bne reg1_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg1_loopf_pass + +reg1_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg1_error_loopf + +reg1_loopf_pass: + + /* Test each general purpose register to check that it still contains the + expected known value, jumping to reg1_error_loop if any register contains + an unexpected value. */ + cmp r0, #0xFF + bne reg1_error_loop + cmp r1, #0x11 + bne reg1_error_loop + cmp r2, #0x22 + bne reg1_error_loop + cmp r3, #0x33 + bne reg1_error_loop + cmp r4, #0x44 + bne reg1_error_loop + cmp r5, #0x55 + bne reg1_error_loop + cmp r6, #0x66 + bne reg1_error_loop + cmp r7, #0x77 + bne reg1_error_loop + cmp r8, #0x88 + bne reg1_error_loop + cmp r9, #0x99 + bne reg1_error_loop + cmp r10, #0xAA + bne reg1_error_loop + cmp r11, #0xBB + bne reg1_error_loop + cmp r12, #0xCC + bne reg1_error_loop + cmp r14, #0xEE + bne reg1_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest1LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg1_loop + +reg1_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg1_error_loop + nop + +/*-----------------------------------------------------------*/ + +.type vRegTest2Implementation, %function +vRegTest2Implementation: + + /* Put a known value in each register. */ + mov r0, #0xFF000000 + mov r1, #0x11000000 + mov r2, #0x22000000 + mov r3, #0x33000000 + mov r4, #0x44000000 + mov r5, #0x55000000 + mov r6, #0x66000000 + mov r7, #0x77000000 + mov r8, #0x88000000 + mov r9, #0x99000000 + mov r10, #0xAA000000 + mov r11, #0xBB000000 + mov r12, #0xCC000000 + mov r14, #0xEE000000 + + /* Likewise the floating point registers */ + vmov d0, r0, r1 + vmov d1, r2, r3 + vmov d2, r4, r5 + vmov d3, r6, r7 + vmov d4, r8, r9 + vmov d5, r10, r11 + vmov d6, r0, r1 + vmov d7, r2, r3 + vmov d8, r4, r5 + vmov d9, r6, r7 + vmov d10, r8, r9 + vmov d11, r10, r11 + vmov d12, r0, r1 + vmov d13, r2, r3 + vmov d14, r4, r5 + vmov d15, r6, r7 + + /* Loop, checking each iteration that each register still contains the + expected value. */ +reg2_loop: + /* Check all the VFP registers still contain the values set above. + First save registers that are clobbered by the test. */ + push { r0-r1 } + + vmov r0, r1, d0 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d1 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d2 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d3 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + vmov r0, r1, d4 + cmp r0, #0x88000000 + bne reg2_error_loopf + cmp r1, #0x99000000 + bne reg2_error_loopf + vmov r0, r1, d5 + cmp r0, #0xAA000000 + bne reg2_error_loopf + cmp r1, #0xBB000000 + bne reg2_error_loopf + vmov r0, r1, d6 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d7 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d8 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d9 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + vmov r0, r1, d10 + cmp r0, #0x88000000 + bne reg2_error_loopf + cmp r1, #0x99000000 + bne reg2_error_loopf + vmov r0, r1, d11 + cmp r0, #0xAA000000 + bne reg2_error_loopf + cmp r1, #0xBB000000 + bne reg2_error_loopf + vmov r0, r1, d12 + cmp r0, #0xFF000000 + bne reg2_error_loopf + cmp r1, #0x11000000 + bne reg2_error_loopf + vmov r0, r1, d13 + cmp r0, #0x22000000 + bne reg2_error_loopf + cmp r1, #0x33000000 + bne reg2_error_loopf + vmov r0, r1, d14 + cmp r0, #0x44000000 + bne reg2_error_loopf + cmp r1, #0x55000000 + bne reg2_error_loopf + vmov r0, r1, d15 + cmp r0, #0x66000000 + bne reg2_error_loopf + cmp r1, #0x77000000 + bne reg2_error_loopf + + /* Restore the registers that were clobbered by the test. */ + pop {r0-r1} + + /* VFP register test passed. Jump to the core register test. */ + b reg2_loopf_pass + +reg2_error_loopf: + /* If this line is hit then a VFP register value was found to be + incorrect. */ + b reg2_error_loopf + +reg2_loopf_pass: + + cmp r0, #0xFF000000 + bne reg2_error_loop + cmp r1, #0x11000000 + bne reg2_error_loop + cmp r2, #0x22000000 + bne reg2_error_loop + cmp r3, #0x33000000 + bne reg2_error_loop + cmp r4, #0x44000000 + bne reg2_error_loop + cmp r5, #0x55000000 + bne reg2_error_loop + cmp r6, #0x66000000 + bne reg2_error_loop + cmp r7, #0x77000000 + bne reg2_error_loop + cmp r8, #0x88000000 + bne reg2_error_loop + cmp r9, #0x99000000 + bne reg2_error_loop + cmp r10, #0xAA000000 + bne reg2_error_loop + cmp r11, #0xBB000000 + bne reg2_error_loop + cmp r12, #0xCC000000 + bne reg2_error_loop + cmp r14, #0xEE000000 + bne reg2_error_loop + + /* Everything passed, increment the loop counter. */ + push { r0-r1 } + ldr r0, =ulRegTest2LoopCounter + ldr r1, [r0] + adds r1, r1, #1 + str r1, [r0] + pop { r0-r1 } + + /* Start again. */ + b reg2_loop + +reg2_error_loop: + /* If this line is hit then there was an error in a core register value. + The loop ensures the loop counter stops incrementing. */ + b reg2_error_loop + nop + + + .end + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/lscript.ld b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/lscript.ld new file mode 100644 index 000000000..e1f1bcfea --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/lscript.ld @@ -0,0 +1,310 @@ +/*******************************************************************/ +/* */ +/* This file is automatically generated by linker script generator.*/ +/* */ +/* Version: */ +/* */ +/* Copyright (c) 2010 Xilinx, Inc. All rights reserved. */ +/* */ +/* Description : ARM-v7 Linker Script */ +/* */ +/*******************************************************************/ + +_STACK_SIZE = DEFINED(_STACK_SIZE) ? _STACK_SIZE : 0x2000; +_HEAP_SIZE = DEFINED(_HEAP_SIZE) ? _HEAP_SIZE : 0x2000; + +_ABORT_STACK_SIZE = DEFINED(_ABORT_STACK_SIZE) ? _ABORT_STACK_SIZE : 1024; +_SUPERVISOR_STACK_SIZE = DEFINED(_SUPERVISOR_STACK_SIZE) ? _SUPERVISOR_STACK_SIZE : 2048; +_IRQ_STACK_SIZE = DEFINED(_IRQ_STACK_SIZE) ? _IRQ_STACK_SIZE : 1024; +_FIQ_STACK_SIZE = DEFINED(_FIQ_STACK_SIZE) ? _FIQ_STACK_SIZE : 1024; +_UNDEF_STACK_SIZE = DEFINED(_UNDEF_STACK_SIZE) ? _UNDEF_STACK_SIZE : 1024; + +/* Define Memories in the system */ + +MEMORY +{ + psu_bbram_0_S_AXI_BASEADDR : ORIGIN = 0xFFCD0000, LENGTH = 0x10000 + psu_ocm_S_AXI_BASEADDR : ORIGIN = 0xFF960000, LENGTH = 0x10000 + psu_ocm_ram_0_S_AXI_BASEADDR : ORIGIN = 0xFFFC0000, LENGTH = 0x30000 + psu_ocm_ram_1_S_AXI_BASEADDR : ORIGIN = 0xFFFF0000, LENGTH = 0x10000 + psu_pmu_ram_S_AXI_BASEADDR : ORIGIN = 0xFFDC0000, LENGTH = 0x20000 + psu_qspi_linear_0_S_AXI_BASEADDR : ORIGIN = 0xC0000000, LENGTH = 0x20000000 + psu_r5_0_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE00000, LENGTH = 0x10000 + psu_r5_0_atcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE10000, LENGTH = 0x10000 + psu_r5_0_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFE20000, LENGTH = 0x10000 + psu_r5_0_btcm_lockstep_S_AXI_BASEADDR : ORIGIN = 0xFFE30000, LENGTH = 0x10000 + psu_r5_1_atcm_S_AXI_BASEADDR : ORIGIN = 0xFFE90000, LENGTH = 0x10000 + psu_r5_1_btcm_S_AXI_BASEADDR : ORIGIN = 0xFFEB0000, LENGTH = 0x10000 + psu_r5_ddr_0_S_AXI_BASEADDR : ORIGIN = 0x100000, LENGTH = 0x7FF00000 + psu_r5_tcm_ram_0_S_AXI_BASEADDR : ORIGIN = 0x100, LENGTH = 0x1FF01 +} + +/* Specify the default entry point to the program */ + +ENTRY(_boot) + +/* Define the sections, and where they are mapped in memory */ + +SECTIONS +{ +.vectors 0x0 : { + KEEP (*(.freertos_vectors)) + KEEP (*(.vectors)) +} + +.text : { + *(.boot) + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + *(.plt) + *(.gnu_warning) + *(.gcc_execpt_table) + *(.glue_7) + *(.glue_7t) + *(.vfp11_veneer) + *(.ARM.extab) + *(.gnu.linkonce.armextab.*) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.init : { + KEEP (*(.init)) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.fini : { + KEEP (*(.fini)) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.interp : { + KEEP (*(.interp)) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.note-ABI-tag : { + KEEP (*(.note-ABI-tag)) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.rodata : { + __rodata_start = .; + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + __rodata_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.rodata1 : { + __rodata1_start = .; + *(.rodata1) + *(.rodata1.*) + __rodata1_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.sdata2 : { + __sdata2_start = .; + *(.sdata2) + *(.sdata2.*) + *(.gnu.linkonce.s2.*) + __sdata2_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.sbss2 : { + __sbss2_start = .; + *(.sbss2) + *(.sbss2.*) + *(.gnu.linkonce.sb2.*) + __sbss2_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.data : { + __data_start = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + *(.jcr) + *(.got) + *(.got.plt) + __data_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.data1 : { + __data1_start = .; + *(.data1) + *(.data1.*) + __data1_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.got : { + *(.got) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.ctors : { + __CTOR_LIST__ = .; + ___CTORS_LIST___ = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + __CTOR_END__ = .; + ___CTORS_END___ = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.dtors : { + __DTOR_LIST__ = .; + ___DTORS_LIST___ = .; + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE(*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + __DTOR_END__ = .; + ___DTORS_END___ = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.fixup : { + __fixup_start = .; + *(.fixup) + __fixup_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.eh_frame : { + *(.eh_frame) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.eh_framehdr : { + __eh_framehdr_start = .; + *(.eh_framehdr) + __eh_framehdr_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.gcc_except_table : { + *(.gcc_except_table) +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.mmu_tbl (ALIGN(16384)) : { + __mmu_tbl_start = .; + *(.mmu_tbl) + __mmu_tbl_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.ARM.exidx : { + __exidx_start = .; + *(.ARM.exidx*) + *(.gnu.linkonce.armexidix.*.*) + __exidx_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.preinit_array : { + __preinit_array_start = .; + KEEP (*(SORT(.preinit_array.*))) + KEEP (*(.preinit_array)) + __preinit_array_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.init_array : { + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.fini_array : { + __fini_array_start = .; + KEEP (*(SORT(.fini_array.*))) + KEEP (*(.fini_array)) + __fini_array_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.ARM.attributes : { + __ARM.attributes_start = .; + *(.ARM.attributes) + __ARM.attributes_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.sdata : { + __sdata_start = .; + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + __sdata_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.sbss (NOLOAD) : { + __sbss_start = .; + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + __sbss_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.tdata : { + __tdata_start = .; + *(.tdata) + *(.tdata.*) + *(.gnu.linkonce.td.*) + __tdata_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.tbss : { + __tbss_start = .; + *(.tbss) + *(.tbss.*) + *(.gnu.linkonce.tb.*) + __tbss_end = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.bss (NOLOAD) : { + . = ALIGN(4); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +_SDA_BASE_ = __sdata_start + ((__sbss_end - __sdata_start) / 2 ); + +_SDA2_BASE_ = __sdata2_start + ((__sbss2_end - __sdata2_start) / 2 ); + +/* Generate Stack and Heap definitions */ + +.heap (NOLOAD) : { + . = ALIGN(16); + _heap = .; + HeapBase = .; + _heap_start = .; + . += _HEAP_SIZE; + _heap_end = .; + HeapLimit = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +.stack (NOLOAD) : { + . = ALIGN(16); + _stack_end = .; + . += _STACK_SIZE; + _stack = .; + __stack = _stack; + . = ALIGN(16); + _irq_stack_end = .; + . += _IRQ_STACK_SIZE; + __irq_stack = .; + _supervisor_stack_end = .; + . += _SUPERVISOR_STACK_SIZE; + . = ALIGN(16); + __supervisor_stack = .; + _abort_stack_end = .; + . += _ABORT_STACK_SIZE; + . = ALIGN(16); + __abort_stack = .; + _fiq_stack_end = .; + . += _FIQ_STACK_SIZE; + . = ALIGN(16); + __fiq_stack = .; + _undef_stack_end = .; + . += _UNDEF_STACK_SIZE; + . = ALIGN(16); + __undef_stack = .; +} > psu_r5_ddr_0_S_AXI_BASEADDR + +_end = .; +} + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/main.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/main.c new file mode 100644 index 000000000..5c6c602a5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/main.c @@ -0,0 +1,314 @@ +/* + FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd. + All rights reserved + + VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION. + + This file is part of the FreeRTOS distribution. + + FreeRTOS is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License (version 2) as published by the + Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception. + + *************************************************************************** + >>! NOTE: The modification to the GPL is included to allow you to !<< + >>! distribute a combined work that includes FreeRTOS without being !<< + >>! obliged to provide the source code for proprietary components !<< + >>! outside of the FreeRTOS kernel. !<< + *************************************************************************** + + FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY + WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS + FOR A PARTICULAR PURPOSE. Full license text is available on the following + link: http://www.freertos.org/a00114.html + + *************************************************************************** + * * + * FreeRTOS provides completely free yet professionally developed, * + * robust, strictly quality controlled, supported, and cross * + * platform software that is more than just the market leader, it * + * is the industry's de facto standard. * + * * + * Help yourself get started quickly while simultaneously helping * + * to support the FreeRTOS project by purchasing a FreeRTOS * + * tutorial book, reference manual, or both: * + * http://www.FreeRTOS.org/Documentation * + * * + *************************************************************************** + + http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading + the FAQ page "My application does not run, what could be wrong?". Have you + defined configASSERT()? + + http://www.FreeRTOS.org/support - In return for receiving this top quality + embedded software for free we request you assist our global community by + participating in the support forum. + + http://www.FreeRTOS.org/training - Investing in training allows your team to + be as productive as possible as early as possible. Now you can receive + FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers + Ltd, and the world's leading authority on the world's leading RTOS. + + http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products, + including FreeRTOS+Trace - an indispensable productivity tool, a DOS + compatible FAT file system, and our tiny thread aware UDP/IP stack. + + http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate. + Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS. + + http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High + Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS + licenses offer ticketed support, indemnification and commercial middleware. + + http://www.SafeRTOS.com - High Integrity Systems also provide a safety + engineered and independently SIL3 certified version for use in safety and + mission critical applications that require provable dependability. + + 1 tab == 4 spaces! +*/ + +/****************************************************************************** + * NOTE 1: This project provides two demo applications. A simple blinky + * style project, and a more comprehensive test and demo application. The + * mainSELECTED_APPLICATION setting in main.c is used to select between the two. + * See the notes on using mainSELECTED_APPLICATION where it is defined below. + * + * NOTE 2: This file only contains the source code that is not specific to + * either the simply blinky or full demos - this includes initialisation code + * and callback functions. + */ + +/* Standard includes. */ +#include + +/* Scheduler include files. */ +#include "FreeRTOS.h" +#include "task.h" + +/* Xilinx includes. */ +#include "platform.h" +#include "xparameters.h" +#include "xscugic.h" +#include "xil_printf.h" + +/* mainSELECTED_APPLICATION is used to select between two demo applications, + * as described at the top of this file. + * + * When mainSELECTED_APPLICATION is set to 0 the simple blinky example will + * be run. + * + * When mainSELECTED_APPLICATION is set to 1 the comprehensive test and demo + * application will be run. + */ +#define mainSELECTED_APPLICATION 0 + +/*-----------------------------------------------------------*/ + +/* + * Configure the hardware as necessary to run this demo. + */ +static void prvSetupHardware( void ); + +/* + * See the comments at the top of this file and above the + * mainSELECTED_APPLICATION definition. + */ +#if ( mainSELECTED_APPLICATION == 0 ) + extern void main_blinky( void ); +#elif ( mainSELECTED_APPLICATION == 1 ) + extern void main_full( void ); +#else + #error Invalid mainSELECTED_APPLICATION setting. See the comments at the top of this file and above the mainSELECTED_APPLICATION definition. +#endif + +/* Prototypes for the standard FreeRTOS callback/hook functions implemented +within this file. */ +void vApplicationMallocFailedHook( void ); +void vApplicationIdleHook( void ); +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ); +void vApplicationTickHook( void ); + +/*-----------------------------------------------------------*/ + +/* The interrupt controller is initialised in this file, and made available to +other modules. */ +XScuGic xInterruptController; + +/*-----------------------------------------------------------*/ + +int main( void ) +{ + /* Configure the hardware ready to run the demo. */ + prvSetupHardware(); + + /* The mainSELECTED_APPLICATION setting is described at the top + of this file. */ + #if( mainSELECTED_APPLICATION == 0 ) + { + main_blinky(); + } + #elif( mainSELECTED_APPLICATION == 1 ) + { + main_full(); + } + #endif + + /* Don't expect to reach here. */ + return 0; +} +/*-----------------------------------------------------------*/ + +static void prvSetupHardware( void ) +{ +BaseType_t xStatus; +XScuGic_Config *pxGICConfig; + + /* Ensure no interrupts execute while the scheduler is in an inconsistent + state. Interrupts are automatically enabled when the scheduler is + started. */ + portDISABLE_INTERRUPTS(); + + init_platform(); + + /* Obtain the configuration of the GIC. */ + pxGICConfig = XScuGic_LookupConfig( XPAR_SCUGIC_SINGLE_DEVICE_ID ); + + /* Sanity check the FreeRTOSConfig.h settings are correct for the + hardware. */ + configASSERT( pxGICConfig ); + configASSERT( pxGICConfig->CpuBaseAddress == ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET ) ); + configASSERT( pxGICConfig->DistBaseAddress == configINTERRUPT_CONTROLLER_BASE_ADDRESS ); + + /* Install a default handler for each GIC interrupt. */ + xStatus = XScuGic_CfgInitialize( &xInterruptController, pxGICConfig, pxGICConfig->CpuBaseAddress ); + configASSERT( xStatus == XST_SUCCESS ); + ( void ) xStatus; /* Remove compiler warning if configASSERT() is not defined. */ + + /* Ensure the FPU is accessible by enabling access to CP 10 and 11. */ + __asm volatile( "MRC p15, 0, r0, c1, c0, 2 \n" \ + "ORR r0, r0, #(0xF << 20) \n" \ + "MCR p15, 0, r0, c1, c0, 2 \n" \ + "ISB " ); + + + /* Ensure the FPU is enabled. */ + __asm volatile( "VMRS r0, FPEXC \n" \ + "ORR r1, r0, #(1<<30) \n" \ + "VMSR FPEXC, r1 \n" \ + ::: "r0", "r1" ); +} +/*-----------------------------------------------------------*/ + +void vApplicationMallocFailedHook( void ) +{ + /* Called if a call to pvPortMalloc() fails because there is insufficient + free memory available in the FreeRTOS heap. pvPortMalloc() is called + internally by FreeRTOS API functions that create tasks, queues, software + timers, and semaphores. The size of the FreeRTOS heap is set by the + configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName ) +{ + ( void ) pcTaskName; + ( void ) pxTask; + + /* Run time stack overflow checking is performed if + configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook + function is called if a stack overflow is detected. */ + taskDISABLE_INTERRUPTS(); + for( ;; ); +} +/*-----------------------------------------------------------*/ + +void vApplicationIdleHook( void ) +{ +volatile size_t xFreeHeapSpace; + + /* This is just a trivial example of an idle hook. It is called on each + cycle of the idle task. It must *NOT* attempt to block. In this case the + idle task just queries the amount of FreeRTOS heap that remains. See the + memory management section on the http://www.FreeRTOS.org web site for memory + management options. If there is a lot of heap memory free then the + configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up + RAM. */ + xFreeHeapSpace = xPortGetFreeHeapSize(); + + /* Remove compiler warning about xFreeHeapSpace being set but never used. */ + ( void ) xFreeHeapSpace; +} +/*-----------------------------------------------------------*/ + +void vApplicationTickHook( void ) +{ + #if( mainSELECTED_APPLICATION == 1 ) + { + /* Only the comprehensive demo actually uses the tick hook. */ + extern void vFullDemoTickHook( void ); + vFullDemoTickHook(); + } + #endif +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an +implementation of vApplicationGetIdleTaskMemory() to provide the memory that is +used by the Idle task. */ +void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) +{ +/* If the buffers to be provided to the Idle task are declared inside this +function then they must be declared static - otherwise they will be allocated on +the stack and so not exists after this function exits. */ +static StaticTask_t xIdleTaskTCB; +static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Idle task's + state will be stored. */ + *ppxIdleTaskTCBBuffer = &xIdleTaskTCB; + + /* Pass out the array that will be used as the Idle task's stack. */ + *ppxIdleTaskStackBuffer = uxIdleTaskStack; + + /* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulIdleTaskStackSize = configMINIMAL_STACK_SIZE; +} +/*-----------------------------------------------------------*/ + +/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the +application must provide an implementation of vApplicationGetTimerTaskMemory() +to provide the memory that is used by the Timer service task. */ +void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) +{ +/* If the buffers to be provided to the Timer task are declared inside this +function then they must be declared static - otherwise they will be allocated on +the stack and so not exists after this function exits. */ +static StaticTask_t xTimerTaskTCB; +static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ]; + + /* Pass out a pointer to the StaticTask_t structure in which the Timer + task's state will be stored. */ + *ppxTimerTaskTCBBuffer = &xTimerTaskTCB; + + /* Pass out the array that will be used as the Timer task's stack. */ + *ppxTimerTaskStackBuffer = uxTimerTaskStack; + + /* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer. + Note that, as the array is necessarily of type StackType_t, + configMINIMAL_STACK_SIZE is specified in words, not bytes. */ + *pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH; +} +/*-----------------------------------------------------------*/ + +void vMainAssertCalled( const char *pcFileName, uint32_t ulLineNumber ) +{ + xil_printf( "ASSERT! Line %lu of file %s\r\n", ulLineNumber, pcFileName ); + taskENTER_CRITICAL(); + for( ;; ); +} + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform.c new file mode 100644 index 000000000..315dcb0ce --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform.c @@ -0,0 +1,105 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#include "xparameters.h" +#include "xil_cache.h" + +#include "platform_config.h" + +/* + * Uncomment one of the following two lines, depending on the target, + * if ps7/psu init source files are added in the source directory for + * compiling example outside of SDK. + */ +/*#include "ps7_init.h"*/ +/*#include "psu_init.h"*/ + +#ifdef STDOUT_IS_16550 + #include "xuartns550_l.h" + + #define UART_BAUD 9600 +#endif + +void +enable_caches() +{ +#ifdef __PPC__ + Xil_ICacheEnableRegion(CACHEABLE_REGION_MASK); + Xil_DCacheEnableRegion(CACHEABLE_REGION_MASK); +#elif __MICROBLAZE__ +#ifdef XPAR_MICROBLAZE_USE_ICACHE + Xil_ICacheEnable(); +#endif +#ifdef XPAR_MICROBLAZE_USE_DCACHE + Xil_DCacheEnable(); +#endif +#endif +} + +void +disable_caches() +{ + Xil_DCacheDisable(); + Xil_ICacheDisable(); +} + +void +init_uart() +{ +#ifdef STDOUT_IS_16550 + XUartNs550_SetBaud(STDOUT_BASEADDR, XPAR_XUARTNS550_CLOCK_HZ, UART_BAUD); + XUartNs550_SetLineControlReg(STDOUT_BASEADDR, XUN_LCR_8_DATA_BITS); +#endif + /* Bootrom/BSP configures PS7/PSU UART to 115200 bps */ +} + +void +init_platform() +{ + /* + * If you want to run this example outside of SDK, + * uncomment one of the following two lines and also #include "ps7_init.h" + * or #include "ps7_init.h" at the top, depending on the target. + * Make sure that the ps7/psu_init.c and ps7/psu_init.h files are included + * along with this example source files for compilation. + */ + /* ps7_init();*/ + /* psu_init();*/ + enable_caches(); + init_uart(); +} + +void +cleanup_platform() +{ + disable_caches(); +} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform.h new file mode 100644 index 000000000..e273e3718 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform.h @@ -0,0 +1,41 @@ +/****************************************************************************** +* +* Copyright (C) 2008 - 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +#ifndef __PLATFORM_H_ +#define __PLATFORM_H_ + +#include "platform_config.h" + +void init_platform(); +void cleanup_platform(); + +#endif diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform_config.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform_config.h new file mode 100644 index 000000000..fea03914b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5/src/platform_config.h @@ -0,0 +1,6 @@ +#ifndef __PLATFORM_CONFIG_H_ +#define __PLATFORM_CONFIG_H_ + +#define STDOUT_IS_PSU_UART +#define UART_DEVICE_ID 0 +#endif diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject new file mode 100644 index 000000000..25054143d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.cproject @@ -0,0 +1,13 @@ + + + + + + + + + + + + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project new file mode 100644 index 000000000..be846c648 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.project @@ -0,0 +1,75 @@ + + + RTOSDemo_R5_bsp + Created by SDK v2016.1 + + + + + org.eclipse.cdt.make.core.makeBuilder + + + org.eclipse.cdt.core.errorOutputParser + org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser; + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.build.arguments + + + + org.eclipse.cdt.make.core.build.command + make + + + org.eclipse.cdt.make.core.build.target.auto + all + + + org.eclipse.cdt.make.core.build.target.clean + clean + + + org.eclipse.cdt.make.core.build.target.inc + all + + + org.eclipse.cdt.make.core.enableAutoBuild + true + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.enabledIncrementalBuild + true + + + org.eclipse.cdt.make.core.environment + + + + org.eclipse.cdt.make.core.stopOnError + false + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + + com.xilinx.sdk.sw.SwProjectNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.make.core.makeNature + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.sdkproject b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.sdkproject new file mode 100644 index 000000000..49c8e0954 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/.sdkproject @@ -0,0 +1,4 @@ +THIRPARTY=false +HW_PROJECT_REFERENCE=ZynqMP_ZCU102_hw_platform +PROCESSOR=psu_cortexr5_0 +MSS_FILE=system.mss diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile new file mode 100644 index 000000000..91c3fcf13 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/Makefile @@ -0,0 +1,31 @@ +# Makefile generated by Xilinx. + +PROCESSOR = psu_cortexr5_0 +LIBRARIES = ${PROCESSOR}/lib/libxil.a +BSP_MAKEFILES := $(wildcard $(PROCESSOR)/libsrc/*/src/Makefile) +SUBDIRS := $(patsubst %/Makefile, %, $(BSP_MAKEFILES)) + +ifneq (,$(findstring win,$(RDI_PLATFORM))) + SHELL = CMD +endif + +all: libs + @echo 'Finished building libraries' + +include: $(addsuffix /make.include,$(SUBDIRS)) + +libs: $(addsuffix /make.libs,$(SUBDIRS)) + +$(PROCESSOR)/lib/libxil.a: $(PROCESSOR)/lib/libxil_init.a + cp -f $< $@ + +%/make.include: $(if $(wildcard $(PROCESSOR)/lib/libxil_init.a),$(PROCESSOR)/lib/libxil.a,) + @echo "Running Make include in $(subst /make.include,,$@)" + $(MAKE) -C $(subst /make.include,,$@) -s include "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS= -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -mfpu=vfpv3-d16" + +%/make.libs: include + @echo "Running Make libs in $(subst /make.libs,,$@)" + $(MAKE) -C $(subst /make.libs,,$@) -s libs "SHELL=$(SHELL)" "COMPILER=armr5-none-eabi-gcc" "ARCHIVER=armr5-none-eabi-ar" "COMPILER_FLAGS= -O2 -c -mcpu=cortex-r5" "EXTRA_COMPILER_FLAGS=-g -DARMR5 -mfpu=vfpv3-d16" + +clean: + rm -f ${PROCESSOR}/lib/libxil.a diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h new file mode 100644 index 000000000..7e9e79ff2 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/include/xparameters.h @@ -0,0 +1,1346 @@ +/* Definition for CPU ID */ +#define XPAR_CPU_ID 0 + +/* Definitions for peripheral PSU_CORTEXR5_0 */ +#define XPAR_PSU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_CORTEXR5_0 */ +#define XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 499994995 + + +/******************************************************************/ + +#include "xparameters_ps.h" + +/******************************************************************/ + +/* + * Definitions of PSU_TTC_3 counter 0 base address and frequency used + * by sleep and usleep APIs + */ + +#define SLEEP_TIMER_BASEADDR 0xFF140000 +#define SLEEP_TIMER_FREQUENCY 100000000 + +/******************************************************************/ + +#define STDIN_BASEADDRESS 0xFF000000 +#define STDOUT_BASEADDRESS 0xFF000000 + +/******************************************************************/ + +/* Definitions for driver AXIPMON */ +#define XPAR_XAXIPMON_NUM_INSTANCES 4 + +/* Definitions for peripheral PSU_APM_0 */ +#define XPAR_PSU_APM_0_DEVICE_ID 0 +#define XPAR_PSU_APM_0_BASEADDR 0xFD0B0000 +#define XPAR_PSU_APM_0_HIGHADDR 0xFD0BFFFF +#define XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH 32 +#define XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_PSU_APM_0_ENABLE_EVENT_COUNT 1 +#define XPAR_PSU_APM_0_NUM_MONITOR_SLOTS 6 +#define XPAR_PSU_APM_0_NUM_OF_COUNTERS 10 +#define XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_PSU_APM_0_ENABLE_EVENT_LOG 0 +#define XPAR_PSU_APM_0_FIFO_AXIS_DEPTH 32 +#define XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_PSU_APM_0_METRIC_COUNT_SCALE 1 +#define XPAR_PSU_APM_0_ENABLE_ADVANCED 1 +#define XPAR_PSU_APM_0_ENABLE_PROFILE 0 +#define XPAR_PSU_APM_0_ENABLE_TRACE 0 +#define XPAR_PSU_APM_0_S_AXI4_BASEADDR 0x00000000 +#define XPAR_PSU_APM_0_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID 1 + + +/* Definitions for peripheral PSU_APM_1 */ +#define XPAR_PSU_APM_1_DEVICE_ID 1 +#define XPAR_PSU_APM_1_BASEADDR 0xFFA00000 +#define XPAR_PSU_APM_1_HIGHADDR 0xFFA0FFFF +#define XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH 32 +#define XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_PSU_APM_1_ENABLE_EVENT_COUNT 1 +#define XPAR_PSU_APM_1_NUM_MONITOR_SLOTS 1 +#define XPAR_PSU_APM_1_NUM_OF_COUNTERS 3 +#define XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_PSU_APM_1_ENABLE_EVENT_LOG 0 +#define XPAR_PSU_APM_1_FIFO_AXIS_DEPTH 32 +#define XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_PSU_APM_1_METRIC_COUNT_SCALE 1 +#define XPAR_PSU_APM_1_ENABLE_ADVANCED 1 +#define XPAR_PSU_APM_1_ENABLE_PROFILE 0 +#define XPAR_PSU_APM_1_ENABLE_TRACE 0 +#define XPAR_PSU_APM_1_S_AXI4_BASEADDR 0x00000000 +#define XPAR_PSU_APM_1_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID 1 + + +/* Definitions for peripheral PSU_APM_2 */ +#define XPAR_PSU_APM_2_DEVICE_ID 2 +#define XPAR_PSU_APM_2_BASEADDR 0xFFA10000 +#define XPAR_PSU_APM_2_HIGHADDR 0xFFA1FFFF +#define XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH 32 +#define XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_PSU_APM_2_ENABLE_EVENT_COUNT 1 +#define XPAR_PSU_APM_2_NUM_MONITOR_SLOTS 1 +#define XPAR_PSU_APM_2_NUM_OF_COUNTERS 3 +#define XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_PSU_APM_2_ENABLE_EVENT_LOG 0 +#define XPAR_PSU_APM_2_FIFO_AXIS_DEPTH 32 +#define XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_PSU_APM_2_METRIC_COUNT_SCALE 1 +#define XPAR_PSU_APM_2_ENABLE_ADVANCED 1 +#define XPAR_PSU_APM_2_ENABLE_PROFILE 0 +#define XPAR_PSU_APM_2_ENABLE_TRACE 0 +#define XPAR_PSU_APM_2_S_AXI4_BASEADDR 0x00000000 +#define XPAR_PSU_APM_2_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID 1 + + +/* Definitions for peripheral PSU_APM_5 */ +#define XPAR_PSU_APM_5_DEVICE_ID 3 +#define XPAR_PSU_APM_5_BASEADDR 0xFD490000 +#define XPAR_PSU_APM_5_HIGHADDR 0xFD49FFFF +#define XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH 32 +#define XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_PSU_APM_5_ENABLE_EVENT_COUNT 1 +#define XPAR_PSU_APM_5_NUM_MONITOR_SLOTS 1 +#define XPAR_PSU_APM_5_NUM_OF_COUNTERS 3 +#define XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_PSU_APM_5_ENABLE_EVENT_LOG 0 +#define XPAR_PSU_APM_5_FIFO_AXIS_DEPTH 32 +#define XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_PSU_APM_5_METRIC_COUNT_SCALE 1 +#define XPAR_PSU_APM_5_ENABLE_ADVANCED 1 +#define XPAR_PSU_APM_5_ENABLE_PROFILE 0 +#define XPAR_PSU_APM_5_ENABLE_TRACE 0 +#define XPAR_PSU_APM_5_S_AXI4_BASEADDR 0x00000000 +#define XPAR_PSU_APM_5_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID 1 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_APM_0 */ +#define XPAR_AXIPMON_0_DEVICE_ID XPAR_PSU_APM_0_DEVICE_ID +#define XPAR_AXIPMON_0_BASEADDR 0xFD0B0000 +#define XPAR_AXIPMON_0_HIGHADDR 0xFD0BFFFF +#define XPAR_AXIPMON_0_GLOBAL_COUNT_WIDTH 32 +#define XPAR_AXIPMON_0_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_AXIPMON_0_ENABLE_EVENT_COUNT 1 +#define XPAR_AXIPMON_0_NUM_MONITOR_SLOTS 6 +#define XPAR_AXIPMON_0_NUM_OF_COUNTERS 10 +#define XPAR_AXIPMON_0_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_AXIPMON_0_ENABLE_EVENT_LOG 0 +#define XPAR_AXIPMON_0_FIFO_AXIS_DEPTH 32 +#define XPAR_AXIPMON_0_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_AXIPMON_0_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_AXIPMON_0_METRIC_COUNT_SCALE 1 +#define XPAR_AXIPMON_0_ENABLE_ADVANCED 1 +#define XPAR_AXIPMON_0_ENABLE_PROFILE 0 +#define XPAR_AXIPMON_0_ENABLE_TRACE 0 +#define XPAR_AXIPMON_0_S_AXI4_BASEADDR 0x00000000 +#define XPAR_AXIPMON_0_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_AXIPMON_0_ENABLE_32BIT_FILTER_ID 1 + +/* Canonical definitions for peripheral PSU_APM_1 */ +#define XPAR_AXIPMON_1_DEVICE_ID XPAR_PSU_APM_1_DEVICE_ID +#define XPAR_AXIPMON_1_BASEADDR 0xFFA00000 +#define XPAR_AXIPMON_1_HIGHADDR 0xFFA0FFFF +#define XPAR_AXIPMON_1_GLOBAL_COUNT_WIDTH 32 +#define XPAR_AXIPMON_1_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_AXIPMON_1_ENABLE_EVENT_COUNT 1 +#define XPAR_AXIPMON_1_NUM_MONITOR_SLOTS 1 +#define XPAR_AXIPMON_1_NUM_OF_COUNTERS 3 +#define XPAR_AXIPMON_1_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_AXIPMON_1_ENABLE_EVENT_LOG 0 +#define XPAR_AXIPMON_1_FIFO_AXIS_DEPTH 32 +#define XPAR_AXIPMON_1_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_AXIPMON_1_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_AXIPMON_1_METRIC_COUNT_SCALE 1 +#define XPAR_AXIPMON_1_ENABLE_ADVANCED 1 +#define XPAR_AXIPMON_1_ENABLE_PROFILE 0 +#define XPAR_AXIPMON_1_ENABLE_TRACE 0 +#define XPAR_AXIPMON_1_S_AXI4_BASEADDR 0x00000000 +#define XPAR_AXIPMON_1_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_AXIPMON_1_ENABLE_32BIT_FILTER_ID 1 + +/* Canonical definitions for peripheral PSU_APM_2 */ +#define XPAR_AXIPMON_2_DEVICE_ID XPAR_PSU_APM_2_DEVICE_ID +#define XPAR_AXIPMON_2_BASEADDR 0xFFA10000 +#define XPAR_AXIPMON_2_HIGHADDR 0xFFA1FFFF +#define XPAR_AXIPMON_2_GLOBAL_COUNT_WIDTH 32 +#define XPAR_AXIPMON_2_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_AXIPMON_2_ENABLE_EVENT_COUNT 1 +#define XPAR_AXIPMON_2_NUM_MONITOR_SLOTS 1 +#define XPAR_AXIPMON_2_NUM_OF_COUNTERS 3 +#define XPAR_AXIPMON_2_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_AXIPMON_2_ENABLE_EVENT_LOG 0 +#define XPAR_AXIPMON_2_FIFO_AXIS_DEPTH 32 +#define XPAR_AXIPMON_2_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_AXIPMON_2_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_AXIPMON_2_METRIC_COUNT_SCALE 1 +#define XPAR_AXIPMON_2_ENABLE_ADVANCED 1 +#define XPAR_AXIPMON_2_ENABLE_PROFILE 0 +#define XPAR_AXIPMON_2_ENABLE_TRACE 0 +#define XPAR_AXIPMON_2_S_AXI4_BASEADDR 0x00000000 +#define XPAR_AXIPMON_2_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_AXIPMON_2_ENABLE_32BIT_FILTER_ID 1 + +/* Canonical definitions for peripheral PSU_APM_5 */ +#define XPAR_AXIPMON_3_DEVICE_ID XPAR_PSU_APM_5_DEVICE_ID +#define XPAR_AXIPMON_3_BASEADDR 0xFD490000 +#define XPAR_AXIPMON_3_HIGHADDR 0xFD49FFFF +#define XPAR_AXIPMON_3_GLOBAL_COUNT_WIDTH 32 +#define XPAR_AXIPMON_3_METRICS_SAMPLE_COUNT_WIDTH 32 +#define XPAR_AXIPMON_3_ENABLE_EVENT_COUNT 1 +#define XPAR_AXIPMON_3_NUM_MONITOR_SLOTS 1 +#define XPAR_AXIPMON_3_NUM_OF_COUNTERS 3 +#define XPAR_AXIPMON_3_HAVE_SAMPLED_METRIC_CNT 1 +#define XPAR_AXIPMON_3_ENABLE_EVENT_LOG 0 +#define XPAR_AXIPMON_3_FIFO_AXIS_DEPTH 32 +#define XPAR_AXIPMON_3_FIFO_AXIS_TDATA_WIDTH 56 +#define XPAR_AXIPMON_3_FIFO_AXIS_TID_WIDTH 1 +#define XPAR_AXIPMON_3_METRIC_COUNT_SCALE 1 +#define XPAR_AXIPMON_3_ENABLE_ADVANCED 1 +#define XPAR_AXIPMON_3_ENABLE_PROFILE 0 +#define XPAR_AXIPMON_3_ENABLE_TRACE 0 +#define XPAR_AXIPMON_3_S_AXI4_BASEADDR 0x00000000 +#define XPAR_AXIPMON_3_S_AXI4_HIGHADDR 0x00000000 +#define XPAR_AXIPMON_3_ENABLE_32BIT_FILTER_ID 1 + + +/******************************************************************/ + +/* Definitions for driver CANPS */ +#define XPAR_XCANPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_CAN_1 */ +#define XPAR_PSU_CAN_1_DEVICE_ID 0 +#define XPAR_PSU_CAN_1_BASEADDR 0xFF070000 +#define XPAR_PSU_CAN_1_HIGHADDR 0xFF07FFFF +#define XPAR_PSU_CAN_1_CAN_CLK_FREQ_HZ 99998999 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_CAN_1 */ +#define XPAR_XCANPS_0_DEVICE_ID XPAR_PSU_CAN_1_DEVICE_ID +#define XPAR_XCANPS_0_BASEADDR 0xFF070000 +#define XPAR_XCANPS_0_HIGHADDR 0xFF07FFFF +#define XPAR_XCANPS_0_CAN_CLK_FREQ_HZ 99998999 + + +/******************************************************************/ + +/* Definitions for driver CSUDMA */ +#define XPAR_XCSUDMA_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_CSUDMA */ +#define XPAR_PSU_CSUDMA_DEVICE_ID 0 +#define XPAR_PSU_CSUDMA_BASEADDR 0xFFC80000 +#define XPAR_PSU_CSUDMA_HIGHADDR 0xFFC9FFFF +#define XPAR_PSU_CSUDMA_CSUDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_CSUDMA */ +#define XPAR_XCSUDMA_0_DEVICE_ID XPAR_PSU_CSUDMA_DEVICE_ID +#define XPAR_XCSUDMA_0_BASEADDR 0xFFC80000 +#define XPAR_XCSUDMA_0_HIGHADDR 0xFFC9FFFF +#define XPAR_XCSUDMA_0_CSUDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +/* Definitions for driver EMACPS */ +#define XPAR_XEMACPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_ETHERNET_3 */ +#define XPAR_PSU_ETHERNET_3_DEVICE_ID 0 +#define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000 +#define XPAR_PSU_ETHERNET_3_HIGHADDR 0xFF0EFFFF +#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 50000000 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 50000000 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 50000000 +#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 50000000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_ETHERNET_3 */ +#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID +#define XPAR_XEMACPS_0_BASEADDR 0xFF0E0000 +#define XPAR_XEMACPS_0_HIGHADDR 0xFF0EFFFF +#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 50000000 +#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 50000000 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 50000000 +#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 50000000 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 50000000 +#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50000000 + + +/******************************************************************/ + + +/* Definitions for peripheral PSU_AFI_0 */ +#define XPAR_PSU_AFI_0_S_AXI_BASEADDR 0xFD360000 +#define XPAR_PSU_AFI_0_S_AXI_HIGHADDR 0xFD36FFFF + + +/* Definitions for peripheral PSU_AFI_1 */ +#define XPAR_PSU_AFI_1_S_AXI_BASEADDR 0xFD370000 +#define XPAR_PSU_AFI_1_S_AXI_HIGHADDR 0xFD37FFFF + + +/* Definitions for peripheral PSU_AFI_2 */ +#define XPAR_PSU_AFI_2_S_AXI_BASEADDR 0xFD380000 +#define XPAR_PSU_AFI_2_S_AXI_HIGHADDR 0xFD38FFFF + + +/* Definitions for peripheral PSU_AFI_3 */ +#define XPAR_PSU_AFI_3_S_AXI_BASEADDR 0xFD390000 +#define XPAR_PSU_AFI_3_S_AXI_HIGHADDR 0xFD39FFFF + + +/* Definitions for peripheral PSU_AFI_4 */ +#define XPAR_PSU_AFI_4_S_AXI_BASEADDR 0xFD3A0000 +#define XPAR_PSU_AFI_4_S_AXI_HIGHADDR 0xFD3AFFFF + + +/* Definitions for peripheral PSU_AFI_5 */ +#define XPAR_PSU_AFI_5_S_AXI_BASEADDR 0xFD3B0000 +#define XPAR_PSU_AFI_5_S_AXI_HIGHADDR 0xFD3BFFFF + + +/* Definitions for peripheral PSU_AFI_6 */ +#define XPAR_PSU_AFI_6_S_AXI_BASEADDR 0xFF9B0000 +#define XPAR_PSU_AFI_6_S_AXI_HIGHADDR 0xFF9BFFFF + + +/* Definitions for peripheral PSU_APU */ +#define XPAR_PSU_APU_S_AXI_BASEADDR 0xFD5C0000 +#define XPAR_PSU_APU_S_AXI_HIGHADDR 0xFD5CFFFF + + +/* Definitions for peripheral PSU_BBRAM_0 */ +#define XPAR_PSU_BBRAM_0_S_AXI_BASEADDR 0xFFCD0000 +#define XPAR_PSU_BBRAM_0_S_AXI_HIGHADDR 0xFFCDFFFF + + +/* Definitions for peripheral PSU_CCI_GPV */ +#define XPAR_PSU_CCI_GPV_S_AXI_BASEADDR 0xFD6E0000 +#define XPAR_PSU_CCI_GPV_S_AXI_HIGHADDR 0xFD6EFFFF + + +/* Definitions for peripheral PSU_CCI_REG */ +#define XPAR_PSU_CCI_REG_S_AXI_BASEADDR 0xFD5E0000 +#define XPAR_PSU_CCI_REG_S_AXI_HIGHADDR 0xFD5EFFFF + + +/* Definitions for peripheral PSU_CRF_APB */ +#define XPAR_PSU_CRF_APB_S_AXI_BASEADDR 0xFD1A0000 +#define XPAR_PSU_CRF_APB_S_AXI_HIGHADDR 0xFD2DFFFF + + +/* Definitions for peripheral PSU_CRL_APB */ +#define XPAR_PSU_CRL_APB_S_AXI_BASEADDR 0xFF5E0000 +#define XPAR_PSU_CRL_APB_S_AXI_HIGHADDR 0xFF85FFFF + + +/* Definitions for peripheral PSU_CSU_0 */ +#define XPAR_PSU_CSU_0_S_AXI_BASEADDR 0xFFCA0000 +#define XPAR_PSU_CSU_0_S_AXI_HIGHADDR 0xFFCAFFFF + + +/* Definitions for peripheral PSU_DDR_PHY */ +#define XPAR_PSU_DDR_PHY_S_AXI_BASEADDR 0xFD080000 +#define XPAR_PSU_DDR_PHY_S_AXI_HIGHADDR 0xFD08FFFF + + +/* Definitions for peripheral PSU_DDR_QOS_CTRL */ +#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_BASEADDR 0xFD090000 +#define XPAR_PSU_DDR_QOS_CTRL_S_AXI_HIGHADDR 0xFD09FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU0_CFG */ +#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_BASEADDR 0xFD000000 +#define XPAR_PSU_DDR_XMPU0_CFG_S_AXI_HIGHADDR 0xFD00FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU1_CFG */ +#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_BASEADDR 0xFD010000 +#define XPAR_PSU_DDR_XMPU1_CFG_S_AXI_HIGHADDR 0xFD01FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU2_CFG */ +#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_BASEADDR 0xFD020000 +#define XPAR_PSU_DDR_XMPU2_CFG_S_AXI_HIGHADDR 0xFD02FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU3_CFG */ +#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_BASEADDR 0xFD030000 +#define XPAR_PSU_DDR_XMPU3_CFG_S_AXI_HIGHADDR 0xFD03FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU4_CFG */ +#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_BASEADDR 0xFD040000 +#define XPAR_PSU_DDR_XMPU4_CFG_S_AXI_HIGHADDR 0xFD04FFFF + + +/* Definitions for peripheral PSU_DDR_XMPU5_CFG */ +#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_BASEADDR 0xFD050000 +#define XPAR_PSU_DDR_XMPU5_CFG_S_AXI_HIGHADDR 0xFD05FFFF + + +/* Definitions for peripheral PSU_DDRC_0 */ +#define XPAR_PSU_DDRC_0_S_AXI_BASEADDR 0xFD070000 +#define XPAR_PSU_DDRC_0_S_AXI_HIGHADDR 0xFD070FFF + + +/* Definitions for peripheral PSU_DP */ +#define XPAR_PSU_DP_S_AXI_BASEADDR 0xFD4A0000 +#define XPAR_PSU_DP_S_AXI_HIGHADDR 0xFD4AFFFF + + +/* Definitions for peripheral PSU_DPDMA */ +#define XPAR_PSU_DPDMA_S_AXI_BASEADDR 0xFD4C0000 +#define XPAR_PSU_DPDMA_S_AXI_HIGHADDR 0xFD4CFFFF + + +/* Definitions for peripheral PSU_EFUSE */ +#define XPAR_PSU_EFUSE_S_AXI_BASEADDR 0xFFCC0000 +#define XPAR_PSU_EFUSE_S_AXI_HIGHADDR 0xFFCCFFFF + + +/* Definitions for peripheral PSU_FPD_GPV */ +#define XPAR_PSU_FPD_GPV_S_AXI_BASEADDR 0xFD700000 +#define XPAR_PSU_FPD_GPV_S_AXI_HIGHADDR 0xFD7FFFFF + + +/* Definitions for peripheral PSU_FPD_SLCR */ +#define XPAR_PSU_FPD_SLCR_S_AXI_BASEADDR 0xFD610000 +#define XPAR_PSU_FPD_SLCR_S_AXI_HIGHADDR 0xFD68FFFF + + +/* Definitions for peripheral PSU_FPD_SLCR_SECURE */ +#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_BASEADDR 0xFD690000 +#define XPAR_PSU_FPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFD6CFFFF + + +/* Definitions for peripheral PSU_FPD_XMPU_CFG */ +#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_BASEADDR 0xFD5D0000 +#define XPAR_PSU_FPD_XMPU_CFG_S_AXI_HIGHADDR 0xFD5DFFFF + + +/* Definitions for peripheral PSU_FPD_XMPU_SINK */ +#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_BASEADDR 0xFD4F0000 +#define XPAR_PSU_FPD_XMPU_SINK_S_AXI_HIGHADDR 0xFD4FFFFF + + +/* Definitions for peripheral PSU_GPU */ +#define XPAR_PSU_GPU_S_AXI_BASEADDR 0xFD4B0000 +#define XPAR_PSU_GPU_S_AXI_HIGHADDR 0xFD4BFFFF + + +/* Definitions for peripheral PSU_IOU_S */ +#define XPAR_PSU_IOU_S_S_AXI_BASEADDR 0xFF000000 +#define XPAR_PSU_IOU_S_S_AXI_HIGHADDR 0xFF2AFFFF + + +/* Definitions for peripheral PSU_IOU_SCNTR */ +#define XPAR_PSU_IOU_SCNTR_S_AXI_BASEADDR 0xFF250000 +#define XPAR_PSU_IOU_SCNTR_S_AXI_HIGHADDR 0xFF25FFFF + + +/* Definitions for peripheral PSU_IOU_SCNTRS */ +#define XPAR_PSU_IOU_SCNTRS_S_AXI_BASEADDR 0xFF260000 +#define XPAR_PSU_IOU_SCNTRS_S_AXI_HIGHADDR 0xFF26FFFF + + +/* Definitions for peripheral PSU_IOUSECURE_SLCR */ +#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_BASEADDR 0xFF240000 +#define XPAR_PSU_IOUSECURE_SLCR_S_AXI_HIGHADDR 0xFF24FFFF + + +/* Definitions for peripheral PSU_IOUSLCR_0 */ +#define XPAR_PSU_IOUSLCR_0_S_AXI_BASEADDR 0xFF180000 +#define XPAR_PSU_IOUSLCR_0_S_AXI_HIGHADDR 0xFF23FFFF + + +/* Definitions for peripheral PSU_LPD_SLCR */ +#define XPAR_PSU_LPD_SLCR_S_AXI_BASEADDR 0xFF410000 +#define XPAR_PSU_LPD_SLCR_S_AXI_HIGHADDR 0xFF4AFFFF + + +/* Definitions for peripheral PSU_LPD_SLCR_SECURE */ +#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_BASEADDR 0xFF4B0000 +#define XPAR_PSU_LPD_SLCR_SECURE_S_AXI_HIGHADDR 0xFF4DFFFF + + +/* Definitions for peripheral PSU_LPD_XPPU */ +#define XPAR_PSU_LPD_XPPU_S_AXI_BASEADDR 0xFF980000 +#define XPAR_PSU_LPD_XPPU_S_AXI_HIGHADDR 0xFF99FFFF + + +/* Definitions for peripheral PSU_LPD_XPPU_SINK */ +#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_BASEADDR 0xFF9C0000 +#define XPAR_PSU_LPD_XPPU_SINK_S_AXI_HIGHADDR 0xFF9CFFFF + + +/* Definitions for peripheral PSU_MBISTJTAG */ +#define XPAR_PSU_MBISTJTAG_S_AXI_BASEADDR 0xFFCF0000 +#define XPAR_PSU_MBISTJTAG_S_AXI_HIGHADDR 0xFFCFFFFF + + +/* Definitions for peripheral PSU_OCM */ +#define XPAR_PSU_OCM_S_AXI_BASEADDR 0xFF960000 +#define XPAR_PSU_OCM_S_AXI_HIGHADDR 0xFF96FFFF + + +/* Definitions for peripheral PSU_OCM_RAM_0 */ +#define XPAR_PSU_OCM_RAM_0_S_AXI_BASEADDR 0xFFFC0000 +#define XPAR_PSU_OCM_RAM_0_S_AXI_HIGHADDR 0xFFFEFFFF + + +/* Definitions for peripheral PSU_OCM_RAM_1 */ +#define XPAR_PSU_OCM_RAM_1_S_AXI_BASEADDR 0xFFFF0000 +#define XPAR_PSU_OCM_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF + + +/* Definitions for peripheral PSU_OCM_XMPU_CFG */ +#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_BASEADDR 0xFFA70000 +#define XPAR_PSU_OCM_XMPU_CFG_S_AXI_HIGHADDR 0xFFA7FFFF + + +/* Definitions for peripheral PSU_PCIE */ +#define XPAR_PSU_PCIE_S_AXI_BASEADDR 0xFD0E0000 +#define XPAR_PSU_PCIE_S_AXI_HIGHADDR 0xFD0EFFFF + + +/* Definitions for peripheral PSU_PCIE_ATTRIB_0 */ +#define XPAR_PSU_PCIE_ATTRIB_0_S_AXI_BASEADDR 0xFD480000 +#define XPAR_PSU_PCIE_ATTRIB_0_S_AXI_HIGHADDR 0xFD48FFFF + + +/* Definitions for peripheral PSU_PCIE_DMA */ +#define XPAR_PSU_PCIE_DMA_S_AXI_BASEADDR 0xFD0F0000 +#define XPAR_PSU_PCIE_DMA_S_AXI_HIGHADDR 0xFD0FFFFF + + +/* Definitions for peripheral PSU_PMU_GLOBAL_0 */ +#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_BASEADDR 0xFFD80000 +#define XPAR_PSU_PMU_GLOBAL_0_S_AXI_HIGHADDR 0xFFDBFFFF + + +/* Definitions for peripheral PSU_PMU_IOMODULE */ +#define XPAR_PSU_PMU_IOMODULE_S_AXI_BASEADDR 0xFFD40000 +#define XPAR_PSU_PMU_IOMODULE_S_AXI_HIGHADDR 0xFFD5FFFF + + +/* Definitions for peripheral PSU_PMU_RAM */ +#define XPAR_PSU_PMU_RAM_S_AXI_BASEADDR 0xFFDC0000 +#define XPAR_PSU_PMU_RAM_S_AXI_HIGHADDR 0xFFDDFFFF + + +/* Definitions for peripheral PSU_QSPI_LINEAR_0 */ +#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_BASEADDR 0xC0000000 +#define XPAR_PSU_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xDFFFFFFF + + +/* Definitions for peripheral PSU_R5_0_ATCM */ +#define XPAR_PSU_R5_0_ATCM_S_AXI_BASEADDR 0xFFE00000 +#define XPAR_PSU_R5_0_ATCM_S_AXI_HIGHADDR 0xFFE0FFFF + + +/* Definitions for peripheral PSU_R5_0_ATCM_LOCKSTEP */ +#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE10000 +#define XPAR_PSU_R5_0_ATCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE1FFFF + + +/* Definitions for peripheral PSU_R5_0_BTCM */ +#define XPAR_PSU_R5_0_BTCM_S_AXI_BASEADDR 0xFFE20000 +#define XPAR_PSU_R5_0_BTCM_S_AXI_HIGHADDR 0xFFE2FFFF + + +/* Definitions for peripheral PSU_R5_0_BTCM_LOCKSTEP */ +#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_BASEADDR 0xFFE30000 +#define XPAR_PSU_R5_0_BTCM_LOCKSTEP_S_AXI_HIGHADDR 0xFFE3FFFF + + +/* Definitions for peripheral PSU_R5_1_ATCM */ +#define XPAR_PSU_R5_1_ATCM_S_AXI_BASEADDR 0xFFE90000 +#define XPAR_PSU_R5_1_ATCM_S_AXI_HIGHADDR 0xFFE9FFFF + + +/* Definitions for peripheral PSU_R5_1_BTCM */ +#define XPAR_PSU_R5_1_BTCM_S_AXI_BASEADDR 0xFFEB0000 +#define XPAR_PSU_R5_1_BTCM_S_AXI_HIGHADDR 0xFFEBFFFF + + +/* Definitions for peripheral PSU_R5_DDR_0 */ +#define XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR 0x00100000 +#define XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR 0xFFFFFFFF + + +/* Definitions for peripheral PSU_R5_TCM_RAM_0 */ +#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_BASEADDR 0x00000000 +#define XPAR_PSU_R5_TCM_RAM_0_S_AXI_HIGHADDR 0x00020000 + + +/* Definitions for peripheral PSU_RPU */ +#define XPAR_PSU_RPU_S_AXI_BASEADDR 0xFF9A0000 +#define XPAR_PSU_RPU_S_AXI_HIGHADDR 0xFF9AFFFF + + +/* Definitions for peripheral PSU_RSA */ +#define XPAR_PSU_RSA_S_AXI_BASEADDR 0xFFCE0000 +#define XPAR_PSU_RSA_S_AXI_HIGHADDR 0xFFCEFFFF + + +/* Definitions for peripheral PSU_SATA */ +#define XPAR_PSU_SATA_S_AXI_BASEADDR 0xFD0C0000 +#define XPAR_PSU_SATA_S_AXI_HIGHADDR 0xFD0CFFFF + + +/* Definitions for peripheral PSU_SERDES */ +#define XPAR_PSU_SERDES_S_AXI_BASEADDR 0xFD400000 +#define XPAR_PSU_SERDES_S_AXI_HIGHADDR 0xFD47FFFF + + +/* Definitions for peripheral PSU_SIOU */ +#define XPAR_PSU_SIOU_S_AXI_BASEADDR 0xFD3D0000 +#define XPAR_PSU_SIOU_S_AXI_HIGHADDR 0xFD3DFFFF + + +/* Definitions for peripheral PSU_SMMU_GPV */ +#define XPAR_PSU_SMMU_GPV_S_AXI_BASEADDR 0xFD800000 +#define XPAR_PSU_SMMU_GPV_S_AXI_HIGHADDR 0xFDFFFFFF + + +/* Definitions for peripheral PSU_SMMU_REG */ +#define XPAR_PSU_SMMU_REG_S_AXI_BASEADDR 0xFD5F0000 +#define XPAR_PSU_SMMU_REG_S_AXI_HIGHADDR 0xFD5FFFFF + + +/* Definitions for peripheral PSU_USB_0 */ +#define XPAR_PSU_USB_0_S_AXI_BASEADDR 0xFE200000 +#define XPAR_PSU_USB_0_S_AXI_HIGHADDR 0xFE20FFFF + + +/******************************************************************/ + +/* Definitions for driver GPIOPS */ +#define XPAR_XGPIOPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_GPIO_0 */ +#define XPAR_PSU_GPIO_0_DEVICE_ID 0 +#define XPAR_PSU_GPIO_0_BASEADDR 0xFF0A0000 +#define XPAR_PSU_GPIO_0_HIGHADDR 0xFF0AFFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_GPIO_0 */ +#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PSU_GPIO_0_DEVICE_ID +#define XPAR_XGPIOPS_0_BASEADDR 0xFF0A0000 +#define XPAR_XGPIOPS_0_HIGHADDR 0xFF0AFFFF + + +/******************************************************************/ + +/* Definitions for driver IICPS */ +#define XPAR_XIICPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PSU_I2C_0 */ +#define XPAR_PSU_I2C_0_DEVICE_ID 0 +#define XPAR_PSU_I2C_0_BASEADDR 0xFF020000 +#define XPAR_PSU_I2C_0_HIGHADDR 0xFF02FFFF +#define XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ 99998999 + + +/* Definitions for peripheral PSU_I2C_1 */ +#define XPAR_PSU_I2C_1_DEVICE_ID 1 +#define XPAR_PSU_I2C_1_BASEADDR 0xFF030000 +#define XPAR_PSU_I2C_1_HIGHADDR 0xFF03FFFF +#define XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ 99998999 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_I2C_0 */ +#define XPAR_XIICPS_0_DEVICE_ID XPAR_PSU_I2C_0_DEVICE_ID +#define XPAR_XIICPS_0_BASEADDR 0xFF020000 +#define XPAR_XIICPS_0_HIGHADDR 0xFF02FFFF +#define XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 99998999 + +/* Canonical definitions for peripheral PSU_I2C_1 */ +#define XPAR_XIICPS_1_DEVICE_ID XPAR_PSU_I2C_1_DEVICE_ID +#define XPAR_XIICPS_1_BASEADDR 0xFF030000 +#define XPAR_XIICPS_1_HIGHADDR 0xFF03FFFF +#define XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 99998999 + + +/******************************************************************/ + +#define XPAR_XIPIPSU_NUM_INSTANCES 2 + +/* Parameter definitions for peripheral psu_ipi_1 */ +#define XPAR_PSU_IPI_1_DEVICE_ID 0 +#define XPAR_PSU_IPI_1_BASE_ADDRESS 0xFF310000 +#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100 +#define XPAR_PSU_IPI_1_BUFFER_INDEX 0 +#define XPAR_PSU_IPI_1_INT_ID 65 + +/* Parameter definitions for peripheral psu_ipi_2 */ +#define XPAR_PSU_IPI_2_DEVICE_ID 1 +#define XPAR_PSU_IPI_2_BASE_ADDRESS 0xFF320000 +#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200 +#define XPAR_PSU_IPI_2_BUFFER_INDEX 1 +#define XPAR_PSU_IPI_2_INT_ID 66 + +/* Canonical definitions for peripheral psu_ipi_1 */ +#define XPAR_XIPIPSU_0_DEVICE_ID XPAR_PSU_IPI_1_DEVICE_ID +#define XPAR_XIPIPSU_0_BASE_ADDRESS XPAR_PSU_IPI_1_BASE_ADDRESS +#define XPAR_XIPIPSU_0_BIT_MASK XPAR_PSU_IPI_1_BIT_MASK +#define XPAR_XIPIPSU_0_BUFFER_INDEX XPAR_PSU_IPI_1_BUFFER_INDEX +#define XPAR_XIPIPSU_0_INT_ID XPAR_PSU_IPI_1_INT_ID + +/* Canonical definitions for peripheral psu_ipi_2 */ +#define XPAR_XIPIPSU_1_DEVICE_ID XPAR_PSU_IPI_2_DEVICE_ID +#define XPAR_XIPIPSU_1_BASE_ADDRESS XPAR_PSU_IPI_2_BASE_ADDRESS +#define XPAR_XIPIPSU_1_BIT_MASK XPAR_PSU_IPI_2_BIT_MASK +#define XPAR_XIPIPSU_1_BUFFER_INDEX XPAR_PSU_IPI_2_BUFFER_INDEX +#define XPAR_XIPIPSU_1_INT_ID XPAR_PSU_IPI_2_INT_ID + +#define XPAR_XIPIPSU_NUM_TARGETS 11 + +#define XPAR_PSU_IPI_0_BIT_MASK 0x00000001 +#define XPAR_PSU_IPI_0_BUFFER_INDEX 2 +#define XPAR_PSU_IPI_1_BIT_MASK 0x00000100 +#define XPAR_PSU_IPI_1_BUFFER_INDEX 0 +#define XPAR_PSU_IPI_2_BIT_MASK 0x00000200 +#define XPAR_PSU_IPI_2_BUFFER_INDEX 1 +#define XPAR_PSU_IPI_3_BIT_MASK 0x00010000 +#define XPAR_PSU_IPI_3_BUFFER_INDEX 7 +#define XPAR_PSU_IPI_4_BIT_MASK 0x00020000 +#define XPAR_PSU_IPI_4_BUFFER_INDEX 7 +#define XPAR_PSU_IPI_5_BIT_MASK 0x00040000 +#define XPAR_PSU_IPI_5_BUFFER_INDEX 7 +#define XPAR_PSU_IPI_6_BIT_MASK 0x00080000 +#define XPAR_PSU_IPI_6_BUFFER_INDEX 7 +#define XPAR_PSU_IPI_7_BIT_MASK 0x01000000 +#define XPAR_PSU_IPI_7_BUFFER_INDEX 3 +#define XPAR_PSU_IPI_8_BIT_MASK 0x02000000 +#define XPAR_PSU_IPI_8_BUFFER_INDEX 4 +#define XPAR_PSU_IPI_9_BIT_MASK 0x04000000 +#define XPAR_PSU_IPI_9_BUFFER_INDEX 5 +#define XPAR_PSU_IPI_10_BIT_MASK 0x08000000 +#define XPAR_PSU_IPI_10_BUFFER_INDEX 6 +/* Target List for referring to processor IPI Targets */ + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_0_CH0_INDEX 0 + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_1_CH0_INDEX 0 + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_2_CH0_INDEX 0 + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_MASK XPAR_PSU_IPI_0_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXA53_3_CH0_INDEX 0 + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH0_INDEX 1 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_0_CH1_INDEX 2 + +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_MASK XPAR_PSU_IPI_1_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH0_INDEX 1 +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_MASK XPAR_PSU_IPI_2_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_CORTEXR5_1_CH1_INDEX 2 + +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_MASK XPAR_PSU_IPI_3_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH0_INDEX 3 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_MASK XPAR_PSU_IPI_4_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH1_INDEX 4 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_MASK XPAR_PSU_IPI_5_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH2_INDEX 5 +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_MASK XPAR_PSU_IPI_6_BIT_MASK +#define XPAR_XIPIPS_TARGET_PSU_PMU_0_CH3_INDEX 6 + +/* Definitions for driver QSPIPSU */ +#define XPAR_XQSPIPSU_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_QSPI_0 */ +#define XPAR_PSU_QSPI_0_DEVICE_ID 0 +#define XPAR_PSU_QSPI_0_BASEADDR 0xFF0F0000 +#define XPAR_PSU_QSPI_0_HIGHADDR 0xFF0FFFFF +#define XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ 124998749 +#define XPAR_PSU_QSPI_0_QSPI_MODE 2 +#define XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH 2 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_QSPI_0 */ +#define XPAR_XQSPIPSU_0_DEVICE_ID XPAR_PSU_QSPI_0_DEVICE_ID +#define XPAR_XQSPIPSU_0_BASEADDR 0xFF0F0000 +#define XPAR_XQSPIPSU_0_HIGHADDR 0xFF0FFFFF +#define XPAR_XQSPIPSU_0_QSPI_CLK_FREQ_HZ 124998749 +#define XPAR_XQSPIPSU_0_QSPI_MODE 2 +#define XPAR_XQSPIPSU_0_QSPI_BUS_WIDTH 2 + + +/******************************************************************/ + +/* Definitions for driver RTCPSU */ +#define XPAR_XRTCPSU_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_RTC */ +#define XPAR_PSU_RTC_DEVICE_ID 0 +#define XPAR_PSU_RTC_BASEADDR 0xFFA60000 +#define XPAR_PSU_RTC_HIGHADDR 0xFFA6FFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_RTC */ +#define XPAR_XRTCPSU_0_DEVICE_ID XPAR_PSU_RTC_DEVICE_ID +#define XPAR_XRTCPSU_0_BASEADDR 0xFFA60000 +#define XPAR_XRTCPSU_0_HIGHADDR 0xFFA6FFFF + + +/******************************************************************/ + +/* Definitions for driver SCUGIC */ +#define XPAR_XSCUGIC_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_RCPU_GIC */ +#define XPAR_PSU_RCPU_GIC_DEVICE_ID 0 +#define XPAR_PSU_RCPU_GIC_BASEADDR 0xF9001000 +#define XPAR_PSU_RCPU_GIC_HIGHADDR 0xF9001FFF +#define XPAR_PSU_RCPU_GIC_DIST_BASEADDR 0xF9000000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_RCPU_GIC */ +#define XPAR_SCUGIC_0_DEVICE_ID 0 +#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF9001000 +#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF9001FFF +#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9000000 + + +/******************************************************************/ + +/* Definitions for driver SDPS */ +#define XPAR_XSDPS_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_SD_1 */ +#define XPAR_PSU_SD_1_DEVICE_ID 0 +#define XPAR_PSU_SD_1_BASEADDR 0xFF170000 +#define XPAR_PSU_SD_1_HIGHADDR 0xFF17FFFF +#define XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ 199998006 +#define XPAR_PSU_SD_1_HAS_CD 1 +#define XPAR_PSU_SD_1_HAS_WP 1 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_SD_1 */ +#define XPAR_XSDPS_0_DEVICE_ID XPAR_PSU_SD_1_DEVICE_ID +#define XPAR_XSDPS_0_BASEADDR 0xFF170000 +#define XPAR_XSDPS_0_HIGHADDR 0xFF17FFFF +#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 199998006 +#define XPAR_XSDPS_0_HAS_CD 1 +#define XPAR_XSDPS_0_HAS_WP 1 + + +/******************************************************************/ + +/* Definitions for driver SYSMONPSU */ +#define XPAR_XSYSMONPSU_NUM_INSTANCES 1 + +/* Definitions for peripheral PSU_AMS */ +#define XPAR_PSU_AMS_DEVICE_ID 0 +#define XPAR_PSU_AMS_BASEADDR 0xFFA50000 +#define XPAR_PSU_AMS_HIGHADDR 0xFFA5FFFF + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_AMS */ +#define XPAR_XSYSMONPSU_0_DEVICE_ID XPAR_PSU_AMS_DEVICE_ID +#define XPAR_XSYSMONPSU_0_BASEADDR 0xFFA50000 +#define XPAR_XSYSMONPSU_0_HIGHADDR 0xFFA5FFFF + + +/******************************************************************/ + +/* Definitions for driver TTCPS */ +#define XPAR_XTTCPS_NUM_INSTANCES 12 + +/* Definitions for peripheral PSU_TTC_0 */ +#define XPAR_PSU_TTC_0_DEVICE_ID 0 +#define XPAR_PSU_TTC_0_BASEADDR 0XFF110000 +#define XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_0_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_1_DEVICE_ID 1 +#define XPAR_PSU_TTC_1_BASEADDR 0XFF110004 +#define XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_1_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_2_DEVICE_ID 2 +#define XPAR_PSU_TTC_2_BASEADDR 0XFF110008 +#define XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_2_TTC_CLK_CLKSRC 0 + + +/* Definitions for peripheral PSU_TTC_1 */ +#define XPAR_PSU_TTC_3_DEVICE_ID 3 +#define XPAR_PSU_TTC_3_BASEADDR 0XFF120000 +#define XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_3_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_4_DEVICE_ID 4 +#define XPAR_PSU_TTC_4_BASEADDR 0XFF120004 +#define XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_4_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_5_DEVICE_ID 5 +#define XPAR_PSU_TTC_5_BASEADDR 0XFF120008 +#define XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_5_TTC_CLK_CLKSRC 0 + + +/* Definitions for peripheral PSU_TTC_2 */ +#define XPAR_PSU_TTC_6_DEVICE_ID 6 +#define XPAR_PSU_TTC_6_BASEADDR 0XFF130000 +#define XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_6_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_7_DEVICE_ID 7 +#define XPAR_PSU_TTC_7_BASEADDR 0XFF130004 +#define XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_7_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_8_DEVICE_ID 8 +#define XPAR_PSU_TTC_8_BASEADDR 0XFF130008 +#define XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_8_TTC_CLK_CLKSRC 0 + + +/* Definitions for peripheral PSU_TTC_3 */ +#define XPAR_PSU_TTC_9_DEVICE_ID 9 +#define XPAR_PSU_TTC_9_BASEADDR 0XFF140000 +#define XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_9_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_10_DEVICE_ID 10 +#define XPAR_PSU_TTC_10_BASEADDR 0XFF140004 +#define XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_10_TTC_CLK_CLKSRC 0 +#define XPAR_PSU_TTC_11_DEVICE_ID 11 +#define XPAR_PSU_TTC_11_BASEADDR 0XFF140008 +#define XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_PSU_TTC_11_TTC_CLK_CLKSRC 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_TTC_0 */ +#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PSU_TTC_0_DEVICE_ID +#define XPAR_XTTCPS_0_BASEADDR 0xFF110000 +#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PSU_TTC_1_DEVICE_ID +#define XPAR_XTTCPS_1_BASEADDR 0xFF110004 +#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PSU_TTC_2_DEVICE_ID +#define XPAR_XTTCPS_2_BASEADDR 0xFF110008 +#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0 + +/* Canonical definitions for peripheral PSU_TTC_1 */ +#define XPAR_XTTCPS_3_DEVICE_ID XPAR_PSU_TTC_3_DEVICE_ID +#define XPAR_XTTCPS_3_BASEADDR 0xFF120000 +#define XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_3_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_4_DEVICE_ID XPAR_PSU_TTC_4_DEVICE_ID +#define XPAR_XTTCPS_4_BASEADDR 0xFF120004 +#define XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_4_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_5_DEVICE_ID XPAR_PSU_TTC_5_DEVICE_ID +#define XPAR_XTTCPS_5_BASEADDR 0xFF120008 +#define XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_5_TTC_CLK_CLKSRC 0 + +/* Canonical definitions for peripheral PSU_TTC_2 */ +#define XPAR_XTTCPS_6_DEVICE_ID XPAR_PSU_TTC_6_DEVICE_ID +#define XPAR_XTTCPS_6_BASEADDR 0xFF130000 +#define XPAR_XTTCPS_6_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_6_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_7_DEVICE_ID XPAR_PSU_TTC_7_DEVICE_ID +#define XPAR_XTTCPS_7_BASEADDR 0xFF130004 +#define XPAR_XTTCPS_7_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_7_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_8_DEVICE_ID XPAR_PSU_TTC_8_DEVICE_ID +#define XPAR_XTTCPS_8_BASEADDR 0xFF130008 +#define XPAR_XTTCPS_8_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_8_TTC_CLK_CLKSRC 0 + +/* Canonical definitions for peripheral PSU_TTC_3 */ +#define XPAR_XTTCPS_9_DEVICE_ID XPAR_PSU_TTC_9_DEVICE_ID +#define XPAR_XTTCPS_9_BASEADDR 0xFF140000 +#define XPAR_XTTCPS_9_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_9_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_10_DEVICE_ID XPAR_PSU_TTC_10_DEVICE_ID +#define XPAR_XTTCPS_10_BASEADDR 0xFF140004 +#define XPAR_XTTCPS_10_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_10_TTC_CLK_CLKSRC 0 + +#define XPAR_XTTCPS_11_DEVICE_ID XPAR_PSU_TTC_11_DEVICE_ID +#define XPAR_XTTCPS_11_BASEADDR 0xFF140008 +#define XPAR_XTTCPS_11_TTC_CLK_FREQ_HZ 100000000 +#define XPAR_XTTCPS_11_TTC_CLK_CLKSRC 0 + + +/******************************************************************/ + +/* Definitions for driver UARTPS */ +#define XPAR_XUARTPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PSU_UART_0 */ +#define XPAR_PSU_UART_0_DEVICE_ID 0 +#define XPAR_PSU_UART_0_BASEADDR 0xFF000000 +#define XPAR_PSU_UART_0_HIGHADDR 0xFF00FFFF +#define XPAR_PSU_UART_0_UART_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_UART_0_HAS_MODEM 0 + + +/* Definitions for peripheral PSU_UART_1 */ +#define XPAR_PSU_UART_1_DEVICE_ID 1 +#define XPAR_PSU_UART_1_BASEADDR 0xFF010000 +#define XPAR_PSU_UART_1_HIGHADDR 0xFF01FFFF +#define XPAR_PSU_UART_1_UART_CLK_FREQ_HZ 99998999 +#define XPAR_PSU_UART_1_HAS_MODEM 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_UART_0 */ +#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PSU_UART_0_DEVICE_ID +#define XPAR_XUARTPS_0_BASEADDR 0xFF000000 +#define XPAR_XUARTPS_0_HIGHADDR 0xFF00FFFF +#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 99998999 +#define XPAR_XUARTPS_0_HAS_MODEM 0 + +/* Canonical definitions for peripheral PSU_UART_1 */ +#define XPAR_XUARTPS_1_DEVICE_ID XPAR_PSU_UART_1_DEVICE_ID +#define XPAR_XUARTPS_1_BASEADDR 0xFF010000 +#define XPAR_XUARTPS_1_HIGHADDR 0xFF01FFFF +#define XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 99998999 +#define XPAR_XUARTPS_1_HAS_MODEM 0 + + +/******************************************************************/ + +/* Definitions for driver WDTPS */ +#define XPAR_XWDTPS_NUM_INSTANCES 2 + +/* Definitions for peripheral PSU_WDT_0 */ +#define XPAR_PSU_WDT_0_DEVICE_ID 0 +#define XPAR_PSU_WDT_0_BASEADDR 0xFF150000 +#define XPAR_PSU_WDT_0_HIGHADDR 0xFF15FFFF +#define XPAR_PSU_WDT_0_WDT_CLK_FREQ_HZ 25000000 + + +/* Definitions for peripheral PSU_WDT_1 */ +#define XPAR_PSU_WDT_1_DEVICE_ID 1 +#define XPAR_PSU_WDT_1_BASEADDR 0xFD4D0000 +#define XPAR_PSU_WDT_1_HIGHADDR 0xFD4DFFFF +#define XPAR_PSU_WDT_1_WDT_CLK_FREQ_HZ 25000000 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_WDT_0 */ +#define XPAR_XWDTPS_0_DEVICE_ID XPAR_PSU_WDT_0_DEVICE_ID +#define XPAR_XWDTPS_0_BASEADDR 0xFF150000 +#define XPAR_XWDTPS_0_HIGHADDR 0xFF15FFFF +#define XPAR_XWDTPS_0_WDT_CLK_FREQ_HZ 25000000 + +/* Canonical definitions for peripheral PSU_WDT_1 */ +#define XPAR_XWDTPS_1_DEVICE_ID XPAR_PSU_WDT_1_DEVICE_ID +#define XPAR_XWDTPS_1_BASEADDR 0xFD4D0000 +#define XPAR_XWDTPS_1_HIGHADDR 0xFD4DFFFF +#define XPAR_XWDTPS_1_WDT_CLK_FREQ_HZ 25000000 + + +/******************************************************************/ + +/* Definitions for driver ZDMA */ +#define XPAR_XZDMA_NUM_INSTANCES 16 + +/* Definitions for peripheral PSU_ADMA_0 */ +#define XPAR_PSU_ADMA_0_DEVICE_ID 0 +#define XPAR_PSU_ADMA_0_BASEADDR 0xFFA80000 +#define XPAR_PSU_ADMA_0_DMA_MODE 1 +#define XPAR_PSU_ADMA_0_HIGHADDR 0xFFA8FFFF +#define XPAR_PSU_ADMA_0_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_1 */ +#define XPAR_PSU_ADMA_1_DEVICE_ID 1 +#define XPAR_PSU_ADMA_1_BASEADDR 0xFFA90000 +#define XPAR_PSU_ADMA_1_DMA_MODE 1 +#define XPAR_PSU_ADMA_1_HIGHADDR 0xFFA9FFFF +#define XPAR_PSU_ADMA_1_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_2 */ +#define XPAR_PSU_ADMA_2_DEVICE_ID 2 +#define XPAR_PSU_ADMA_2_BASEADDR 0xFFAA0000 +#define XPAR_PSU_ADMA_2_DMA_MODE 1 +#define XPAR_PSU_ADMA_2_HIGHADDR 0xFFAAFFFF +#define XPAR_PSU_ADMA_2_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_3 */ +#define XPAR_PSU_ADMA_3_DEVICE_ID 3 +#define XPAR_PSU_ADMA_3_BASEADDR 0xFFAB0000 +#define XPAR_PSU_ADMA_3_DMA_MODE 1 +#define XPAR_PSU_ADMA_3_HIGHADDR 0xFFABFFFF +#define XPAR_PSU_ADMA_3_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_4 */ +#define XPAR_PSU_ADMA_4_DEVICE_ID 4 +#define XPAR_PSU_ADMA_4_BASEADDR 0xFFAC0000 +#define XPAR_PSU_ADMA_4_DMA_MODE 1 +#define XPAR_PSU_ADMA_4_HIGHADDR 0xFFACFFFF +#define XPAR_PSU_ADMA_4_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_5 */ +#define XPAR_PSU_ADMA_5_DEVICE_ID 5 +#define XPAR_PSU_ADMA_5_BASEADDR 0xFFAD0000 +#define XPAR_PSU_ADMA_5_DMA_MODE 1 +#define XPAR_PSU_ADMA_5_HIGHADDR 0xFFADFFFF +#define XPAR_PSU_ADMA_5_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_6 */ +#define XPAR_PSU_ADMA_6_DEVICE_ID 6 +#define XPAR_PSU_ADMA_6_BASEADDR 0xFFAE0000 +#define XPAR_PSU_ADMA_6_DMA_MODE 1 +#define XPAR_PSU_ADMA_6_HIGHADDR 0xFFAEFFFF +#define XPAR_PSU_ADMA_6_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_ADMA_7 */ +#define XPAR_PSU_ADMA_7_DEVICE_ID 7 +#define XPAR_PSU_ADMA_7_BASEADDR 0xFFAF0000 +#define XPAR_PSU_ADMA_7_DMA_MODE 1 +#define XPAR_PSU_ADMA_7_HIGHADDR 0xFFAFFFFF +#define XPAR_PSU_ADMA_7_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_0 */ +#define XPAR_PSU_GDMA_0_DEVICE_ID 8 +#define XPAR_PSU_GDMA_0_BASEADDR 0xFD500000 +#define XPAR_PSU_GDMA_0_DMA_MODE 0 +#define XPAR_PSU_GDMA_0_HIGHADDR 0xFD50FFFF +#define XPAR_PSU_GDMA_0_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_1 */ +#define XPAR_PSU_GDMA_1_DEVICE_ID 9 +#define XPAR_PSU_GDMA_1_BASEADDR 0xFD510000 +#define XPAR_PSU_GDMA_1_DMA_MODE 0 +#define XPAR_PSU_GDMA_1_HIGHADDR 0xFD51FFFF +#define XPAR_PSU_GDMA_1_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_2 */ +#define XPAR_PSU_GDMA_2_DEVICE_ID 10 +#define XPAR_PSU_GDMA_2_BASEADDR 0xFD520000 +#define XPAR_PSU_GDMA_2_DMA_MODE 0 +#define XPAR_PSU_GDMA_2_HIGHADDR 0xFD52FFFF +#define XPAR_PSU_GDMA_2_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_3 */ +#define XPAR_PSU_GDMA_3_DEVICE_ID 11 +#define XPAR_PSU_GDMA_3_BASEADDR 0xFD530000 +#define XPAR_PSU_GDMA_3_DMA_MODE 0 +#define XPAR_PSU_GDMA_3_HIGHADDR 0xFD53FFFF +#define XPAR_PSU_GDMA_3_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_4 */ +#define XPAR_PSU_GDMA_4_DEVICE_ID 12 +#define XPAR_PSU_GDMA_4_BASEADDR 0xFD540000 +#define XPAR_PSU_GDMA_4_DMA_MODE 0 +#define XPAR_PSU_GDMA_4_HIGHADDR 0xFD54FFFF +#define XPAR_PSU_GDMA_4_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_5 */ +#define XPAR_PSU_GDMA_5_DEVICE_ID 13 +#define XPAR_PSU_GDMA_5_BASEADDR 0xFD550000 +#define XPAR_PSU_GDMA_5_DMA_MODE 0 +#define XPAR_PSU_GDMA_5_HIGHADDR 0xFD55FFFF +#define XPAR_PSU_GDMA_5_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_6 */ +#define XPAR_PSU_GDMA_6_DEVICE_ID 14 +#define XPAR_PSU_GDMA_6_BASEADDR 0xFD560000 +#define XPAR_PSU_GDMA_6_DMA_MODE 0 +#define XPAR_PSU_GDMA_6_HIGHADDR 0xFD56FFFF +#define XPAR_PSU_GDMA_6_ZDMA_CLK_FREQ_HZ 0 + + +/* Definitions for peripheral PSU_GDMA_7 */ +#define XPAR_PSU_GDMA_7_DEVICE_ID 15 +#define XPAR_PSU_GDMA_7_BASEADDR 0xFD570000 +#define XPAR_PSU_GDMA_7_DMA_MODE 0 +#define XPAR_PSU_GDMA_7_HIGHADDR 0xFD57FFFF +#define XPAR_PSU_GDMA_7_ZDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + +/* Canonical definitions for peripheral PSU_ADMA_0 */ +#define XPAR_XZDMA_0_DEVICE_ID XPAR_PSU_ADMA_0_DEVICE_ID +#define XPAR_XZDMA_0_BASEADDR 0xFFA80000 +#define XPAR_XZDMA_0_DMA_MODE 1 +#define XPAR_XZDMA_0_HIGHADDR 0xFFA8FFFF +#define XPAR_XZDMA_0_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_1 */ +#define XPAR_XZDMA_1_DEVICE_ID XPAR_PSU_ADMA_1_DEVICE_ID +#define XPAR_XZDMA_1_BASEADDR 0xFFA90000 +#define XPAR_XZDMA_1_DMA_MODE 1 +#define XPAR_XZDMA_1_HIGHADDR 0xFFA9FFFF +#define XPAR_XZDMA_1_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_2 */ +#define XPAR_XZDMA_2_DEVICE_ID XPAR_PSU_ADMA_2_DEVICE_ID +#define XPAR_XZDMA_2_BASEADDR 0xFFAA0000 +#define XPAR_XZDMA_2_DMA_MODE 1 +#define XPAR_XZDMA_2_HIGHADDR 0xFFAAFFFF +#define XPAR_XZDMA_2_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_3 */ +#define XPAR_XZDMA_3_DEVICE_ID XPAR_PSU_ADMA_3_DEVICE_ID +#define XPAR_XZDMA_3_BASEADDR 0xFFAB0000 +#define XPAR_XZDMA_3_DMA_MODE 1 +#define XPAR_XZDMA_3_HIGHADDR 0xFFABFFFF +#define XPAR_XZDMA_3_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_4 */ +#define XPAR_XZDMA_4_DEVICE_ID XPAR_PSU_ADMA_4_DEVICE_ID +#define XPAR_XZDMA_4_BASEADDR 0xFFAC0000 +#define XPAR_XZDMA_4_DMA_MODE 1 +#define XPAR_XZDMA_4_HIGHADDR 0xFFACFFFF +#define XPAR_XZDMA_4_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_5 */ +#define XPAR_XZDMA_5_DEVICE_ID XPAR_PSU_ADMA_5_DEVICE_ID +#define XPAR_XZDMA_5_BASEADDR 0xFFAD0000 +#define XPAR_XZDMA_5_DMA_MODE 1 +#define XPAR_XZDMA_5_HIGHADDR 0xFFADFFFF +#define XPAR_XZDMA_5_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_6 */ +#define XPAR_XZDMA_6_DEVICE_ID XPAR_PSU_ADMA_6_DEVICE_ID +#define XPAR_XZDMA_6_BASEADDR 0xFFAE0000 +#define XPAR_XZDMA_6_DMA_MODE 1 +#define XPAR_XZDMA_6_HIGHADDR 0xFFAEFFFF +#define XPAR_XZDMA_6_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_ADMA_7 */ +#define XPAR_XZDMA_7_DEVICE_ID XPAR_PSU_ADMA_7_DEVICE_ID +#define XPAR_XZDMA_7_BASEADDR 0xFFAF0000 +#define XPAR_XZDMA_7_DMA_MODE 1 +#define XPAR_XZDMA_7_HIGHADDR 0xFFAFFFFF +#define XPAR_XZDMA_7_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_0 */ +#define XPAR_XZDMA_8_DEVICE_ID XPAR_PSU_GDMA_0_DEVICE_ID +#define XPAR_XZDMA_8_BASEADDR 0xFD500000 +#define XPAR_XZDMA_8_DMA_MODE 0 +#define XPAR_XZDMA_8_HIGHADDR 0xFD50FFFF +#define XPAR_XZDMA_8_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_1 */ +#define XPAR_XZDMA_9_DEVICE_ID XPAR_PSU_GDMA_1_DEVICE_ID +#define XPAR_XZDMA_9_BASEADDR 0xFD510000 +#define XPAR_XZDMA_9_DMA_MODE 0 +#define XPAR_XZDMA_9_HIGHADDR 0xFD51FFFF +#define XPAR_XZDMA_9_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_2 */ +#define XPAR_XZDMA_10_DEVICE_ID XPAR_PSU_GDMA_2_DEVICE_ID +#define XPAR_XZDMA_10_BASEADDR 0xFD520000 +#define XPAR_XZDMA_10_DMA_MODE 0 +#define XPAR_XZDMA_10_HIGHADDR 0xFD52FFFF +#define XPAR_XZDMA_10_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_3 */ +#define XPAR_XZDMA_11_DEVICE_ID XPAR_PSU_GDMA_3_DEVICE_ID +#define XPAR_XZDMA_11_BASEADDR 0xFD530000 +#define XPAR_XZDMA_11_DMA_MODE 0 +#define XPAR_XZDMA_11_HIGHADDR 0xFD53FFFF +#define XPAR_XZDMA_11_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_4 */ +#define XPAR_XZDMA_12_DEVICE_ID XPAR_PSU_GDMA_4_DEVICE_ID +#define XPAR_XZDMA_12_BASEADDR 0xFD540000 +#define XPAR_XZDMA_12_DMA_MODE 0 +#define XPAR_XZDMA_12_HIGHADDR 0xFD54FFFF +#define XPAR_XZDMA_12_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_5 */ +#define XPAR_XZDMA_13_DEVICE_ID XPAR_PSU_GDMA_5_DEVICE_ID +#define XPAR_XZDMA_13_BASEADDR 0xFD550000 +#define XPAR_XZDMA_13_DMA_MODE 0 +#define XPAR_XZDMA_13_HIGHADDR 0xFD55FFFF +#define XPAR_XZDMA_13_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_6 */ +#define XPAR_XZDMA_14_DEVICE_ID XPAR_PSU_GDMA_6_DEVICE_ID +#define XPAR_XZDMA_14_BASEADDR 0xFD560000 +#define XPAR_XZDMA_14_DMA_MODE 0 +#define XPAR_XZDMA_14_HIGHADDR 0xFD56FFFF +#define XPAR_XZDMA_14_ZDMA_CLK_FREQ_HZ 0 + +/* Canonical definitions for peripheral PSU_GDMA_7 */ +#define XPAR_XZDMA_15_DEVICE_ID XPAR_PSU_GDMA_7_DEVICE_ID +#define XPAR_XZDMA_15_BASEADDR 0xFD570000 +#define XPAR_XZDMA_15_DMA_MODE 0 +#define XPAR_XZDMA_15_HIGHADDR 0xFD57FFFF +#define XPAR_XZDMA_15_ZDMA_CLK_FREQ_HZ 0 + + +/******************************************************************/ + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/Makefile new file mode 100644 index 000000000..926b20c4e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/Makefile @@ -0,0 +1,27 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +INCLUDEFILES=*.h +LIBSOURCES=*.c +OUTS = *.o + + +libs: + echo "Compiling axipmon" + $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES) + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS} + make clean + +include: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OUTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.c new file mode 100644 index 000000000..fbb867839 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.c @@ -0,0 +1,2123 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xaxipmon.c +* @addtogroup axipmon_v6_3 +* @{ +* +* This file contains the driver API functions that can be used to access +* the AXI Performance Monitor device. +* +* Refer to the xaxipmon.h header file for more information about this driver. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss   02/27/12  First release
+* 2.00a bss   06/23/12  Updated to support v2_00a version of IP.
+* 3.00a bss   09/03/12  Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
+*			modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
+*			to support v2_01a version of IP.
+* 3.01a bss   10/25/12  Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
+*			APIs (CR #683799).
+*			Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
+*			APIs (CR #683801).
+*			Added XAxiPmon_GetMetricName API (CR #683803).
+*			Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
+*			(CR #683746)
+*			Added XAxiPmon_EnableEventLog,
+*			XAxiPmon_DisableMetricsCounter,
+*			XAxiPmon_EnableMetricsCounter APIs to replace macros.
+*			Added XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs to support new
+*			version of IP.
+* 4.00a bss   01/17/13  To support new version of IP:
+* 			Added XAxiPmon_SetLogEnableRanges,
+*	  		XAxiPmon_GetLogEnableRanges,
+*			XAxiPmon_EnableMetricCounterTrigger,
+*			XAxiPmon_DisableMetricCounterTrigger,
+*			XAxiPmon_EnableEventLogTrigger,
+*			XAxiPmon_DisableEventLogTrigger,
+*			XAxiPmon_SetWriteLatencyId,
+*			XAxiPmon_SetReadLatencyId,
+*			XAxiPmon_GetWriteLatencyId,
+*			XAxiPmon_GetReadLatencyId APIs and removed
+*			XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs
+* 5.00a bss   08/26/13  To support new version of IP:
+*			Modified XAxiPmon_CfgInitialize to add Mode of APM and
+*			ScaleFactor parameter.
+*			Modified Assert functions depending on Mode.
+*			Modified XAxiPmon_GetMetricCounter and
+*			XAxiPmon_GetSampledMetricCounter to include
+*			new Counters.
+*			Modified XAxiPmon_SetSampleInterval and
+*			XAxiPmon_GetSampleInterval to remove higher 32 bit
+*			value of SampleInterval since Sample Interval Register
+*			is only 32 bit.
+*			Added XAxiPmon_SetWrLatencyStart,
+*			XAxiPmon_SetWrLatencyEnd, XAxiPmon_SetRdLatencyStart
+*			XAxiPmon_SetRdLatencyEnd, XAxiPmon_GetWrLatencyStart,
+*			XAxiPmon_GetWrLatencyEnd, XAxiPmon_GetRdLatencyStart,
+*			XAxiPmon_GetRdLatencyEnd, XAxiPmon_SetWriteIdMask,
+*			XAxiPmon_SetReadIdMask,
+*			XAxiPmon_GetWriteIdMask and
+*			XAxiPmon_GetReadIdMask APIs.
+*			Renamed:
+*			XAxiPmon_SetWriteLatencyId to XAxiPmon_SetWriteId
+*			XAxiPmon_SetReadLatencyId to XAxiPmon_SetReadId
+*			XAxiPmon_GetWriteLatencyId to XAxiPmon_GetWriteId
+*			XAxiPmon_SetReadLatencyId to XAxiPmon_GetReadId.
+* 6.2   bss  04/21/14   Updated XAxiPmon_CfgInitialize to Reset counters
+*			and FIFOs based on Modes(CR#782671). And if both
+*			profile and trace modes are present set mode as
+*			Advanced.
+* 6.2	bss  03/02/15	Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
+*						XAxiPmon_GetWriteId, XAxiPmon_GetReadId
+*						XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
+*						XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
+*						functions to support Zynq MP APM.
+* 6.3	kvn  07/02/15	Modified code according to MISRA-C:2012 guidelines.
+* 6.4   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+*                     Changed the prototype of XAxiPmon_CfgInitialize API.
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xaxipmon.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* This function initializes a specific XAxiPmon device/instance. This function +* must be called prior to using the AXI Performance Monitor device. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param ConfigPtr points to the XAxiPmon device configuration structure. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. If the address translation is not used then the +* physical address is passed. +* Unexpected errors may occur if the address mapping is changed +* after this function is invoked. +* +* @return +* - XST_SUCCESS if successful. +* +* @note The user needs to first call the XAxiPmon_LookupConfig() API +* which returns the Configuration structure pointer which is +* passed as a parameter to the XAxiPmon_CfgInitialize() API. +* +******************************************************************************/ +s32 XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, XAxiPmon_Config *ConfigPtr, + UINTPTR EffectiveAddr) +{ + /* + * Assert the input arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * Set the values read from the device config and the base address. + */ + InstancePtr->Config.DeviceId = ConfigPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddr; + InstancePtr->Config.GlobalClkCounterWidth = + ConfigPtr->GlobalClkCounterWidth; + InstancePtr->Config.MetricSampleCounterWidth = + ConfigPtr->MetricSampleCounterWidth; + InstancePtr->Config.IsEventCount = + ConfigPtr->IsEventCount; + InstancePtr->Config.NumberofSlots = + ConfigPtr->NumberofSlots; + InstancePtr->Config.NumberofCounters = + ConfigPtr->NumberofCounters; + InstancePtr->Config.HaveSampledCounters = + ConfigPtr->HaveSampledCounters; + InstancePtr->Config.IsEventLog = + ConfigPtr->IsEventLog; + InstancePtr->Config.FifoDepth = + ConfigPtr->FifoDepth; + InstancePtr->Config.FifoWidth = + ConfigPtr->FifoWidth; + InstancePtr->Config.TidWidth = + ConfigPtr->TidWidth; + InstancePtr->Config.Is32BitFiltering = ConfigPtr->Is32BitFiltering; + + InstancePtr->Config.ScaleFactor = ConfigPtr->ScaleFactor; + + if ((ConfigPtr->ModeProfile == ConfigPtr->ModeTrace) + || (ConfigPtr->ModeAdvanced == 1U)) + { + InstancePtr->Mode = XAPM_MODE_ADVANCED; + } else if (ConfigPtr->ModeTrace == 1U) { + InstancePtr->Mode = XAPM_MODE_TRACE; + } else { + InstancePtr->Mode = XAPM_MODE_PROFILE; + } + + /* + * Indicate the instance is now ready to use, initialized without error. + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + /* + * Reset the Counters and FIFO based on Modes. + */ + + /* Advanced and Profile */ + if((InstancePtr->Mode == XAPM_MODE_ADVANCED) || + (InstancePtr->Mode == XAPM_MODE_PROFILE)) + { + (void)XAxiPmon_ResetMetricCounter(InstancePtr); + } + /* Advanced */ + if(InstancePtr->Mode == XAPM_MODE_ADVANCED) + { + XAxiPmon_ResetGlobalClkCounter(InstancePtr); + } + /* Advanced and Trace */ + if((InstancePtr->Mode == XAPM_MODE_ADVANCED) || + (InstancePtr->Mode == XAPM_MODE_TRACE)) + { + (void)XAxiPmon_ResetFifo(InstancePtr); + } + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function resets all Metric Counters and Sampled Metric Counters of +* AXI Performance Monitor. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return XST_SUCCESS +* +* +* @note None. +* +******************************************************************************/ +s32 XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr) +{ + + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE); + + /* + * Write the reset value to the Control register to reset + * Metric counters + */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue | XAPM_CR_MCNTR_RESET_MASK)); + /* + * Release from Reset + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue & ~(XAPM_CR_MCNTR_RESET_MASK))); + return XST_SUCCESS; + +} + +/*****************************************************************************/ +/** +* +* This function resets Global Clock Counter of AXI Performance Monitor +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr) +{ + + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + + /* + * Write the reset value to the Control register to reset + * Global Clock Counter + */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue | XAPM_CR_GCC_RESET_MASK)); + + /* + * Release from Reset + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue & ~(XAPM_CR_GCC_RESET_MASK))); + +} + +/*****************************************************************************/ +/** +* +* This function resets Streaming FIFO of AXI Performance Monitor +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return XST_SUCCESS +* +* @note None. +* +******************************************************************************/ +s32 XAxiPmon_ResetFifo(XAxiPmon *InstancePtr) +{ + + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_PROFILE); + + /* Check Event Logging is enabled in Hardware */ + if((InstancePtr->Config.IsEventLog == 0U) && + (InstancePtr->Mode == XAPM_MODE_ADVANCED)) + { + /*Event logging not enabled in Hardware*/ + return XST_SUCCESS; + } + /* + * Write the reset value to the Control register to reset + * FIFO + */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue | XAPM_CR_FIFO_RESET_MASK)); + /* + * Release from Reset + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + (RegValue & ~(XAPM_CR_FIFO_RESET_MASK))); + + return XST_SUCCESS; + +} + +/****************************************************************************/ +/** +* +* This function sets Ranges for Incrementers depending on parameters passed. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param IncrementerNum specifies the Incrementer for which Ranges +* need to be set +* @param RangeUpper specifies the Upper limit in 32 bit Register +* @param RangeLower specifies the Lower limit in 32 bit Register +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum, + u16 RangeUpper, u16 RangeLower) + { + + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + Xil_AssertVoid(IncrementerNum < XAPM_MAX_COUNTERS); + + /* + * Write to the specified Range register + */ + RegValue = (u32)RangeUpper << 16; + RegValue |= RangeLower; + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_RANGE0_OFFSET + ((u32)IncrementerNum * (u32)16)), + RegValue); + } + +/****************************************************************************/ +/** +* +* This function returns the Ranges of Incrementers Registers. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param IncrementerNum specifies the Incrementer for which Ranges +* need to be returned. +* @param RangeUpper specifies the user reference variable which returns +* the Upper Range Value of the specified Incrementer. +* @param RangeLower specifies the user reference variable which returns +* the Lower Range Value of the specified Incrementer. +* +* @return None. +* +* @note None +* +*****************************************************************************/ +void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum, + u16 *RangeUpper, u16 *RangeLower) + { + + u32 RegValue; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + Xil_AssertVoid(IncrementerNum < XAPM_MAX_COUNTERS); + + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_RANGE0_OFFSET + ((u32)IncrementerNum * (u32)16))); + + *RangeLower = (u16)(RegValue & 0x0000FFFFU); + *RangeUpper = (u16)((RegValue >> 16) & 0x0000FFFFU); + } + +/****************************************************************************/ +/** +* +* This function sets the Sample Interval Register +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param SampleInterval is the Sample Interval value to be set +* +* @return None +* +* @note None. +* +*****************************************************************************/ +void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval) +{ + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE); + + /* + * Set Sample Interval Lower + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_SI_LOW_OFFSET, SampleInterval); + +} + +/****************************************************************************/ +/** +* +* This function returns the contents of Sample Interval Register +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param SampleInterval is a pointer where the Sample Interval +* Counter value is returned. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE); + + /* + * Set Sample Interval Lower + */ + *SampleInterval = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_SI_LOW_OFFSET); + +} + +/****************************************************************************/ +/** +* +* This function sets Metrics for specified Counter in the corresponding +* Metric Selector Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Slot is the slot ID for which specified counter has to +* be connected. +* @param Metrics is one of the Metric Sets. User has to use +* XAPM_METRIC_SET_* macros in xaxipmon.h for this parameter +* @param CounterNum is the Counter Number. +* The valid values are 0 to 9. +* +* @return XST_SUCCESS if Success +* XST_FAILURE if Failure +* +* @note None. +* +*****************************************************************************/ +s32 XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics, + u8 CounterNum) +{ + u32 RegValue; + u32 Mask; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + Xil_AssertNonvoid(Slot < XAPM_MAX_AGENTS); + Xil_AssertNonvoid((Metrics <= XAPM_METRIC_SET_22) || + (Metrics == XAPM_METRIC_SET_30)); + Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS); + + /* Find Mask value to force zero in counternum byte range */ + if ((CounterNum == 0U) || (CounterNum == 4U) || (CounterNum == 8U)) { + Mask = 0xFFFFFF00U; + } + else if ((CounterNum == 1U) || (CounterNum == 5U) || (CounterNum == 9U)) { + Mask = 0xFFFF00FFU; + } + else if ((CounterNum == 2U) || (CounterNum == 6U)) { + Mask = 0xFF00FFFFU; + } + else { + Mask = 0x00FFFFFFU; + } + + if(CounterNum <= 3U) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_MSR0_OFFSET); + + RegValue = RegValue & Mask; + RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8)); + RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5)); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_MSR0_OFFSET,RegValue); + } + else if((CounterNum >= 4U) && (CounterNum <= 7U)) { + CounterNum = CounterNum - 4U; + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_MSR1_OFFSET); + + RegValue = RegValue & Mask; + RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8)); + RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5)); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_MSR1_OFFSET,RegValue); + } + else { + CounterNum = CounterNum - 8U; + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_MSR2_OFFSET); + + RegValue = RegValue & Mask; + RegValue = RegValue | ((u32)Metrics << (CounterNum * (u8)8)); + RegValue = RegValue | ((u32)Slot << ((CounterNum * (u8)8) + (u8)5)); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_MSR2_OFFSET,RegValue); + } + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function returns Metrics in the specified Counter from the corresponding +* Metric Selector Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CounterNum is the Counter Number. +* The valid values are 0 to 9. +* @param Metrics is a reference parameter from application where metrics +* of specified counter is filled. +* @praram Slot is a reference parameter in which slot Id of +* specified counter is filled +* @return XST_SUCCESS if Success +* XST_FAILURE if Failure +* +* @note None. +* +*****************************************************************************/ +s32 XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics, + u8 *Slot) +{ + u32 RegValue; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + Xil_AssertNonvoid(CounterNum <= XAPM_MAX_COUNTERS); + + if(CounterNum <= 3U) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_MSR0_OFFSET); + *Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU; + *Slot = (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U; + + } + else if((CounterNum >= 4U) && (CounterNum <= 7U)) { + CounterNum = CounterNum - 4U; + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_MSR1_OFFSET); + *Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU; + *Slot = (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U; + } + else { + CounterNum = CounterNum - 8U; + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_MSR2_OFFSET); + *Metrics = (u8)(RegValue >> (CounterNum * (u8)8)) & 0x1FU; + *Slot = (u8)(RegValue >> ((CounterNum * (u8)8) + (u8)5)) & 0x07U; + } + return XST_SUCCESS; +} + +/****************************************************************************/ +/** +* +* This function returns the contents of the Global Clock Counter Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CntHighValue is the user space pointer with which upper 32 bits +* of Global Clock Counter has to be filled +* @param CntLowValue is the user space pointer with which lower 32 bits +* of Global Clock Counter has to be filled +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue, + u32 *CntLowValue) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode == XAPM_MODE_ADVANCED); + + *CntHighValue = 0x0U; + *CntLowValue = 0x0U; + + /* + * If Counter width is 64 bit then Counter Value has to be + * filled at CntHighValue address also. + */ + if(InstancePtr->Config.GlobalClkCounterWidth == 64) { + + /* Bits[63:32] exists at XAPM_GCC_HIGH_OFFSET */ + *CntHighValue = XAxiPmon_ReadReg(InstancePtr-> + Config.BaseAddress, XAPM_GCC_HIGH_OFFSET); + } + /* Bits[31:0] exists at XAPM_GCC_LOW_OFFSET */ + *CntLowValue = XAxiPmon_ReadReg(InstancePtr-> + Config.BaseAddress, XAPM_GCC_LOW_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function returns the contents of the Metric Counter Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CounterNum is the number of the Metric Counter to be read. +* Use the XAPM_METRIC_COUNTER* defines for the counter number in +* xaxipmon.h. The valid values are 0 (XAPM_METRIC_COUNTER_0) to +* 47(XAPM_METRIC_COUNTER_47). +* @return RegValue is the content of specified Metric Counter. +* +* @note None. +* +*****************************************************************************/ +u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum) +{ + + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE); + Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS_PROFILE); + + if (CounterNum < 10U ) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_MC0_OFFSET + (CounterNum * (u32)16))); + } + else if ((CounterNum >= 10U) && (CounterNum < 12U)) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_MC10_OFFSET + ((CounterNum - (u32)10) * (u32)16))); + } + else if ((CounterNum >= 12U) && (CounterNum < 24U)) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_MC12_OFFSET + ((CounterNum - (u32)12) * (u32)16))); + } + else if ((CounterNum >= 24U) && (CounterNum < 36U)) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_MC24_OFFSET + ((CounterNum - (u32)24) * (u32)16))); + } + else { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_MC36_OFFSET + ((CounterNum - (u32)36) * (u32)16))); + } + + return RegValue; +} + +/****************************************************************************/ +/** +* +* This function returns the contents of the Sampled Metric Counter Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CounterNum is the number of the Sampled Metric Counter to read. +* Use the XAPM_METRIC_COUNTER* defines for the counter number in +* xaxipmon.h. The valid values are 0 (XAPM_METRIC_COUNTER_0) to +* 47(XAPM_METRIC_COUNTER_47). +* +* @return RegValue is the content of specified Sampled Metric Counter. +* +* @note None. +* +*****************************************************************************/ +u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(InstancePtr->Mode != XAPM_MODE_TRACE); + Xil_AssertNonvoid(CounterNum < XAPM_MAX_COUNTERS_PROFILE); + Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.HaveSampledCounters == 1U))); + + if (CounterNum < 10U ) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_SMC0_OFFSET + (CounterNum * (u32)16))); + } + else if ((CounterNum >= 10U) && (CounterNum < 12U)) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_SMC10_OFFSET + ((CounterNum - (u32)10) * (u32)16))); + } + else if ((CounterNum >= 12U) && (CounterNum < 24U)) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_SMC12_OFFSET + ((CounterNum - (u32)12) * (u32)16))); + } + else if ((CounterNum >= 24U) && (CounterNum < 36U)) { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_SMC24_OFFSET + ((CounterNum - (u32)24) * (u32)16))); + } + else { + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_SMC36_OFFSET + ((CounterNum - (u32)36) * (u32)16))); + } + + return RegValue; +} + +/****************************************************************************/ +/** +* +* This function returns the contents of the Incrementer Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param IncrementerNum is the number of the Incrementer register to +* read.Use the XAPM_INCREMENTER_* defines for the Incrementer +* number.The valid values are 0 (XAPM_INCREMENTER_0) to +* 9 (XAPM_INCREMENTER_9). +* @param IncrementerNum is the number of the specified Incrementer +* register +* @return RegValue is content of specified Metric Incrementer register. +* +* @note None. +* +*****************************************************************************/ +u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1U)); + Xil_AssertNonvoid(IncrementerNum < XAPM_MAX_COUNTERS); + + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_INC0_OFFSET + (IncrementerNum * (u32)16))); + + return RegValue; +} + +/****************************************************************************/ +/** +* +* This function returns the contents of the Sampled Incrementer Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param IncrementerNum is the number of the Sampled Incrementer +* register to read.Use the XAPM_INCREMENTER_* defines for the +* Incrementer number.The valid values are 0 (XAPM_INCREMENTER_0) +* to 9 (XAPM_INCREMENTER_9). +* @param IncrementerNum is the number of the specified Sampled +* Incrementer register +* @return RegValue is content of specified Sampled Incrementer register. +* +* @note None. +* +*****************************************************************************/ +u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1U) && + (InstancePtr->Config.HaveSampledCounters == 1U)); + Xil_AssertNonvoid(IncrementerNum < XAPM_MAX_COUNTERS); + + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_SINC0_OFFSET + (IncrementerNum * (u32)16))); + return RegValue; +} + +/****************************************************************************/ +/** +* +* This function sets Software-written Data Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param SwData is the Software written Data. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData) +{ + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Set Software-written Data Register + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_SWD_OFFSET, + SwData); +} + +/****************************************************************************/ +/** +* +* This function returns contents of Software-written Data Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return SwData. +* +* @note None. +* +*****************************************************************************/ +u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr) +{ + u32 SwData; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Set Metric Selector Register + */ + SwData = (u32)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_SWD_OFFSET); + return SwData; +} + +/*****************************************************************************/ +/** +* +* This function enables the following in the AXI Performance Monitor: +* - Event logging +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param FlagEnables is a value to write to the flag enables +* register defined by XAPM_FEC_OFFSET. It is recommended +* to use the XAPM_FEC_*_MASK mask bits to generate. +* A value of 0x0 will disable all events to the event +* log streaming FIFO. +* +* @return XST_SUCCESS +* +* @note None +* +******************************************************************************/ +s32 XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_TRACE) || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventLog == 1U))); + + /* Read current register value */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_CTL_OFFSET); + /* Flag Enable register is present only in Advanced Mode */ + if(InstancePtr->Mode == XAPM_MODE_ADVANCED) + { + /* Now write to flag enables register */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_FEC_OFFSET, FlagEnables); + } + + /* Write the new value to the Control register to + * enable event logging */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET, + RegValue | XAPM_CR_EVENTLOG_ENABLE_MASK); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function disables the following in the AXI Performance Monitor: +* - Event logging +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return XST_SUCCESS +* +* @note None +* +******************************************************************************/ +s32 XAxiPmon_StopEventLog(XAxiPmon *InstancePtr) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_TRACE) || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventLog == 1U))); + + /* Read current register value */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_CTL_OFFSET); + + /* Write the new value to the Control register to disable + * event logging */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET, + RegValue & ~XAPM_CR_EVENTLOG_ENABLE_MASK); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function enables the following in the AXI Performance Monitor: +* - Global clock counter +* - All metric counters +* - All sampled metric counters +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* SampleInterval is the sample interval for the sampled metric +* counters +* +* @return XST_SUCCESS +* +* @note None +******************************************************************************/ +s32 XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1U))); + + /* Read current register value */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_CTL_OFFSET); + /* Globlal Clock Counter is present in Advanced mode only */ + if(InstancePtr->Mode == XAPM_MODE_ADVANCED) + { + RegValue = RegValue | XAPM_CR_GCC_ENABLE_MASK; + } + + /* + * Write the new value to the Control register to enable + * global clock counter and metric counters + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET, + RegValue | XAPM_CR_MCNTR_ENABLE_MASK); + + /* Set, enable, and load sampled counters */ + XAxiPmon_SetSampleInterval(InstancePtr, SampleInterval); + XAxiPmon_LoadSampleIntervalCounter(InstancePtr); + XAxiPmon_EnableSampleIntervalCounter(InstancePtr); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function disables the following in the AXI Performance Monitor: +* - Global clock counter +* - All metric counters +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return XST_SUCCESS +* +* @note None +* +******************************************************************************/ +s32 XAxiPmon_StopCounters(XAxiPmon *InstancePtr) +{ + u32 RegValue; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((InstancePtr->Mode == XAPM_MODE_PROFILE) || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1U))); + + /* Read current register value */ + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_CTL_OFFSET); + /* Globlal Clock Counter is present in Advanced mode only */ + if(InstancePtr->Mode == XAPM_MODE_ADVANCED) + { + RegValue = RegValue & ~XAPM_CR_GCC_ENABLE_MASK; + } + + /* + * Write the new value to the Control register to disable + * global clock counter and metric counters + */ + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET, + RegValue & ~XAPM_CR_MCNTR_ENABLE_MASK); + + return XST_SUCCESS; +} + +/*****************************************************************************/ +/** +* +* This function enables Metric Counters. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*******************************************************************************/ +void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_PROFILE) || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1U))); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal | XAPM_CR_MCNTR_ENABLE_MASK); +} +/****************************************************************************/ +/** +* +* This function disables the Metric Counters. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*****************************************************************************/ +void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_PROFILE) || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1U))); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_CTL_OFFSET); + + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, (u32)XAPM_CTL_OFFSET, + RegVal & ~(XAPM_CR_MCNTR_ENABLE_MASK)); +} + +/****************************************************************************/ +/** +* +* This function sets the Upper and Lower Ranges for specified Metric Counter +* Log Enable Register.Event Logging starts when corresponding Metric Counter +* value falls in between these ranges +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CounterNum is the Metric Counter number for which +* Ranges are to be assigned.Use the XAPM_METRIC_COUNTER* +* defines for the counter number in xaxipmon.h. +* The valid values are 0 (XAPM_METRIC_COUNTER_0) to +* 9 (XAPM_METRIC_COUNTER_9). +* @param RangeUpper specifies the Upper limit in 32 bit Register +* @param RangeLower specifies the Lower limit in 32 bit Register +* @return None +* +* @note None. +* +*****************************************************************************/ +void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum, + u16 RangeUpper, u16 RangeLower) +{ + u32 RegValue; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(CounterNum < XAPM_MAX_COUNTERS); + Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1U)); + + + /* + * Write the specified Ranges to corresponding Metric Counter Log + * Enable Register + */ + RegValue = (u32)RangeUpper << 16; + RegValue |= RangeLower; + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_MC0LOGEN_OFFSET + (CounterNum * (u32)16)), RegValue); + +} + +/****************************************************************************/ +/** +* +* This function returns the Ranges of specified Metric Counter Log +* Enable Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param CounterNum is the Metric Counter number for which +* Ranges are to be returned.Use the XAPM_METRIC_COUNTER* +* defines for the counter number in xaxipmon.h. +* The valid values are 0 (XAPM_METRIC_COUNTER_0) to +* 9 (XAPM_METRIC_COUNTER_9). +* +* @param RangeUpper specifies the user reference variable which returns +* the Upper Range Value of the specified Metric Counter +* Log Enable Register. +* @param RangeLower specifies the user reference variable which returns +* the Lower Range Value of the specified Metric Counter +* Log Enable Register. +* +* @note None. +* +*****************************************************************************/ +void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum, + u16 *RangeUpper, u16 *RangeLower) +{ + u32 RegValue; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(CounterNum < XAPM_MAX_COUNTERS); + Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventCount == 1U)); + + + RegValue = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)XAPM_MC0LOGEN_OFFSET + (CounterNum * (u32)16))); + + *RangeLower = (u16)RegValue & 0xFFFFU; + *RangeUpper = (u16)(RegValue >> 16) & 0xFFFFU; +} + +/*****************************************************************************/ +/** +* +* This function enables Event Logging. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*******************************************************************************/ +void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((InstancePtr->Mode == XAPM_MODE_TRACE) || + ((InstancePtr->Mode == XAPM_MODE_ADVANCED) && + (InstancePtr->Config.IsEventLog == 1U))); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal | XAPM_CR_EVENTLOG_ENABLE_MASK); +} + +/*****************************************************************************/ +/** +* +* This function enables External trigger pulse so that Metric Counters can be +* started on external trigger pulse for a Slot. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*******************************************************************************/ +void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal | XAPM_CR_MCNTR_EXTTRIGGER_MASK); +} + +/****************************************************************************/ +/** +* +* This function disables the External trigger pulse used to start Metric +* Counters on external trigger pulse for a Slot. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*****************************************************************************/ +void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_TRACE); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal & ~(XAPM_CR_MCNTR_EXTTRIGGER_MASK)); +} + +/*****************************************************************************/ +/** +* +* This function enables External trigger pulse for Event Log +* so that Event Logging can be started on external trigger pulse for a Slot. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*******************************************************************************/ +void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_PROFILE); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal | XAPM_CR_EVTLOG_EXTTRIGGER_MASK); +} + +/****************************************************************************/ +/** +* +* This function disables the External trigger pulse used to start Event +* Log on external trigger pulse for a Slot. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note None +* +*****************************************************************************/ +void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(InstancePtr->Mode != XAPM_MODE_PROFILE); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, XAPM_CTL_OFFSET, + RegVal & ~(XAPM_CR_EVTLOG_EXTTRIGGER_MASK)); +} + +/****************************************************************************/ +/** +* +* This function returns a name for a given Metric. +* +* @param Metrics is one of the Metric Sets. User has to use +* XAPM_METRIC_SET_* macros in xaxipmon.h for this parameter +* +* @return const char * +* +* @note None +* +*****************************************************************************/ +const char * XAxiPmon_GetMetricName(u8 Metrics) +{ + if (Metrics == XAPM_METRIC_SET_0 ){ + return "Write Transaction Count"; + } + if (Metrics == XAPM_METRIC_SET_1 ){ + return "Read Transaction Count"; + } + if (Metrics == XAPM_METRIC_SET_2 ){ + return "Write Byte Count"; + } + if (Metrics == XAPM_METRIC_SET_3 ){ + return "Read Byte Count"; + } + if (Metrics == XAPM_METRIC_SET_4 ){ + return "Write Beat Count"; + } + if (Metrics == XAPM_METRIC_SET_5 ){ + return "Total Read Latency"; + } + if (Metrics == XAPM_METRIC_SET_6 ){ + return "Total Write Latency"; + } + if (Metrics == XAPM_METRIC_SET_7 ){ + return "Slv_Wr_Idle_Cnt"; + } + if (Metrics == XAPM_METRIC_SET_8 ){ + return "Mst_Rd_Idle_Cnt"; + } + if (Metrics == XAPM_METRIC_SET_9 ){ + return "Num_BValids"; + } + if (Metrics == XAPM_METRIC_SET_10){ + return "Num_WLasts"; + } + if (Metrics == XAPM_METRIC_SET_11){ + return "Num_RLasts"; + } + if (Metrics == XAPM_METRIC_SET_12){ + return "Minimum Write Latency"; + } + if (Metrics == XAPM_METRIC_SET_13){ + return "Maximum Write Latency"; + } + if (Metrics == XAPM_METRIC_SET_14){ + return "Minimum Read Latency"; + } + if (Metrics == XAPM_METRIC_SET_15){ + return "Maximum Read Latency"; + } + if (Metrics == XAPM_METRIC_SET_16){ + return "Transfer Cycle Count"; + } + if (Metrics == XAPM_METRIC_SET_17){ + return "Packet Count"; + } + if (Metrics == XAPM_METRIC_SET_18){ + return "Data Byte Count"; + } + if (Metrics == XAPM_METRIC_SET_19){ + return "Position Byte Count"; + } + if (Metrics == XAPM_METRIC_SET_20){ + return "Null Byte Count"; + } + if (Metrics == XAPM_METRIC_SET_21){ + return "Slv_Idle_Cnt"; + } + if (Metrics == XAPM_METRIC_SET_22){ + return "Mst_Idle_Cnt"; + } + if (Metrics == XAPM_METRIC_SET_30){ + return "External event count"; + } + return "Unsupported"; +} + +/****************************************************************************/ +/** +* +* This function sets Write ID in ID register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param WriteId is the Write ID to be written in ID register. +* +* @return None. +* +* @note +* If ID filtering for write is of 32 bits(for Zynq MP APM) width then +* WriteID is written to XAPM_ID_OFFSET or if it is 16 bit width +* then lower 16 bits of WriteID are written to XAPM_ID_OFFSET. +* +*****************************************************************************/ +void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0U) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET); + RegVal = RegVal & ~(XAPM_ID_WID_MASK); + RegVal = RegVal | WriteId; + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET, RegVal); + } else { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET, WriteId); + } +} + +/****************************************************************************/ +/** +* +* This function sets Read ID in ID register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param ReadId is the Read ID to be written in ID register. +* +* @return None. +* +* @note +* If ID filtering for read is of 32 bits(for Zynq MP APM) width then +* ReadId is written to XAPM_RID_OFFSET or if it is 16 bit width +* then lower 16 bits of ReadId are written to XAPM_ID_OFFSET. +* +*****************************************************************************/ +void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0U) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET); + RegVal = RegVal & ~(XAPM_ID_RID_MASK); + RegVal = RegVal | (ReadId << 16); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET, RegVal); + } else { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_RID_OFFSET, ReadId); + } +} + +/****************************************************************************/ +/** +* +* This function returns Write ID in ID register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return WriteId is the required Write ID in ID register. +* +* @note None. +* If ID filtering for write is of 32 bits(for Zynq MP APM) width then +* 32 bit XAPM_ID_OFFSET contents are returned or if it is 16 bit +* width then lower 16 bits of XAPM_ID_OFFSET register are returned. +* +*****************************************************************************/ +u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr) +{ + + u32 WriteId; + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0U) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET); + WriteId = RegVal & XAPM_ID_WID_MASK; + } else { + WriteId = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET); + } + + return WriteId; +} + +/****************************************************************************/ +/** +* +* This function returns Read ID in ID register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return ReadId is the required Read ID in ID register. +* +* @note None. +* If ID filtering for write is of 32 bits(for Zynq MP APM) width then +* 32 bit XAPM_RID_OFFSET contents are returned or if it is 16 bit +* width then higher 16 bits of XAPM_ID_OFFSET register are returned. +* +*****************************************************************************/ +u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr) +{ + + u32 ReadId; + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0U) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_ID_OFFSET); + RegVal = RegVal & XAPM_ID_RID_MASK; + ReadId = RegVal >> 16; + } else { + ReadId = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_RID_OFFSET); + } + + return ReadId; +} + +/*****************************************************************************/ +/** +* +* This function sets Latency Start point to calculate write latency. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Param is XAPM_LATENCY_ADDR_ISSUE or XAPM_LATENCY_ADDR_ACCEPT +* in xaxipmon.h. +* @return None +* +* @note Param can be 0 - XAPM_LATENCY_ADDR_ISSUE +* or 1 - XAPM_LATENCY_ADDR_ACCEPT +* +*******************************************************************************/ +void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + if (Param == XAPM_LATENCY_ADDR_ACCEPT) { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET, RegVal | XAPM_CR_WRLATENCY_START_MASK); + } + else { + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET, + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET) & ~(XAPM_CR_WRLATENCY_START_MASK)); + } +} + +/*****************************************************************************/ +/** +* +* This function sets Latency End point to calculate write latency. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Param is XAPM_LATENCY_LASTWR or XAPM_LATENCY_FIRSTWR +* in xaxipmon.h. +* +* @return None +* +* @note Param can be 0 - XAPM_LATENCY_LASTWR +* or 1 - XAPM_LATENCY_FIRSTWR +* +*******************************************************************************/ +void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + if (Param == XAPM_LATENCY_FIRSTWR) { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET, RegVal | XAPM_CR_WRLATENCY_END_MASK); + } + else { + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET, + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET) & ~(XAPM_CR_WRLATENCY_END_MASK)); + } +} + +/*****************************************************************************/ +/** +* +* This function sets Latency Start point to calculate read latency. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Param is XAPM_LATENCY_ADDR_ISSUE or XAPM_LATENCY_ADDR_ACCEPT +* in xaxipmon.h. +* +* @return None +* +* @note Param can be 0 - XAPM_LATENCY_ADDR_ISSUE +* or 1 - XAPM_LATENCY_ADDR_ACCEPT +* +*******************************************************************************/ +void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + if (Param == XAPM_LATENCY_ADDR_ACCEPT) { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET, RegVal | XAPM_CR_RDLATENCY_START_MASK); + } + else { + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET, + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET) & ~(XAPM_CR_RDLATENCY_START_MASK)); + } +} + +/*****************************************************************************/ +/** +* +* This function sets Latency End point to calculate read latency. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Param is XAPM_LATENCY_LASTRD or XAPM_LATENCY_FIRSTRD +* in xaxipmon.h. +* +* @return None +* +* @note Param can be 0 - XAPM_LATENCY_LASTRD +* or 1 - XAPM_LATENCY_FIRSTRD +* +*******************************************************************************/ +void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param) +{ + u32 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET); + if (Param == XAPM_LATENCY_FIRSTRD) { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_CTL_OFFSET, RegVal | XAPM_CR_RDLATENCY_END_MASK); + } + else { + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET, + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, + XAPM_CTL_OFFSET) & ~(XAPM_CR_RDLATENCY_END_MASK)); + } +} + +/*****************************************************************************/ +/** +* +* This function returns Write Latency Start point. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Returns 0 - XAPM_LATENCY_ADDR_ISSUE or +* 1 - XAPM_LATENCY_ADDR_ACCEPT +* +* @note None +* +*******************************************************************************/ +u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr) +{ + u8 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_CTL_OFFSET); + RegVal = RegVal & XAPM_CR_WRLATENCY_START_MASK; + if (RegVal != XAPM_LATENCY_ADDR_ISSUE) { + return (u8)XAPM_LATENCY_ADDR_ACCEPT; + } + else { + return (u8)XAPM_LATENCY_ADDR_ISSUE; + } +} + +/*****************************************************************************/ +/** +* +* This function returns Write Latency End point. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Returns 0 - XAPM_LATENCY_LASTWR or +* 1 - XAPM_LATENCY_FIRSTWR. +* +* @note None +* +*******************************************************************************/ +u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr) +{ + u8 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_CTL_OFFSET); + RegVal = RegVal & XAPM_CR_WRLATENCY_END_MASK; + if (RegVal != XAPM_LATENCY_LASTWR) { + return (u8)XAPM_LATENCY_FIRSTWR; + } + else { + return (u8)XAPM_LATENCY_LASTWR; + } +} + +/*****************************************************************************/ +/** +* +* This function returns read Latency Start point. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Returns 0 - XAPM_LATENCY_ADDR_ISSUE or +* 1 - XAPM_LATENCY_ADDR_ACCEPT +* +* @note None +* +*******************************************************************************/ +u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr) +{ + u8 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_CTL_OFFSET); + RegVal = RegVal & XAPM_CR_RDLATENCY_START_MASK; + + if (RegVal != XAPM_LATENCY_ADDR_ISSUE) { + return (u8)XAPM_LATENCY_ADDR_ACCEPT; + } + else { + return (u8)XAPM_LATENCY_ADDR_ISSUE; + } +} + +/*****************************************************************************/ +/** +* +* This function returns Read Latency End point. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Returns 0 - XAPM_LATENCY_LASTRD or +* 1 - XAPM_LATENCY_FIRSTRD. +* +* @note None +* +*******************************************************************************/ +u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr) +{ + u8 RegVal; + + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + RegVal = (u8)XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + (u32)XAPM_CTL_OFFSET); + RegVal = RegVal & XAPM_CR_RDLATENCY_END_MASK; + if (RegVal != XAPM_LATENCY_LASTRD) { + return (u8)XAPM_LATENCY_FIRSTRD; + } + else { + return (u8)XAPM_LATENCY_LASTRD; + } + +} + +/****************************************************************************/ +/** +* +* This function sets Write ID Mask in ID Mask register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param WrMask is the Write ID mask to be written in ID register. +* +* @return None. +* +* @note +* If ID masking for write is of 32 bits(for Zynq MP APM) width then +* WrMask is written to XAPM_IDMASK_OFFSET or if it is 16 bit width +* then lower 16 bits of WrMask are written to XAPM_IDMASK_OFFSET. +* +*****************************************************************************/ +void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0U) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET); + RegVal = RegVal & ~(XAPM_MASKID_WID_MASK); + RegVal = RegVal | WrMask; + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET, RegVal); + } else { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET, WrMask); + } +} + +/****************************************************************************/ +/** +* +* This function sets Read ID Mask in ID Mask register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param RdMask is the Read ID mask to be written in ID Mask register. +* +* @return None. +* +* @note +* If ID masking for read is of 32 bits(for Zynq MP APM) width then +* RdMask is written to XAPM_RIDMASK_OFFSET or if it is 16 bit width +* then lower 16 bits of RdMask are written to XAPM_IDMASK_OFFSET. +* +*****************************************************************************/ +void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask) +{ + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0U) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET); + RegVal = RegVal & ~(XAPM_MASKID_RID_MASK); + RegVal = RegVal | (RdMask << 16); + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET, RegVal); + } else { + XAxiPmon_WriteReg(InstancePtr->Config.BaseAddress, + XAPM_RIDMASK_OFFSET, RdMask); + } +} + +/****************************************************************************/ +/** +* +* This function returns Write ID Mask in ID Mask register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return WrMask is the required Write ID Mask in ID Mask register. +* +* @note +* If ID masking for write is of 32 bits(for Zynq MP APM) width then +* 32 bit XAPM_IDMASK_OFFSET contents are returned or if it is 16 bit +* width then lower 16 bits of XAPM_IDMASK_OFFSET register +* are returned. +* +*****************************************************************************/ +u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr) +{ + + u32 WrMask; + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0U) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET); + WrMask = RegVal & XAPM_MASKID_WID_MASK; + } else { + WrMask = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET); + } + + return WrMask; +} + +/****************************************************************************/ +/** +* +* This function returns Read ID Mask in ID Mask register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return RdMask is the required Read ID Mask in ID Mask register. +* +* @note +* If ID masking for read is of 32 bits(for Zynq MP APM) width then +* 32 bit XAPM_RIDMASK_OFFSET contents are returned or if it is 16 bit +* width then higher 16 bits of XAPM_IDMASK_OFFSET register +* are returned. +* +*****************************************************************************/ +u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr) +{ + + u32 RdMask; + u32 RegVal; + /* + * Assert the arguments. + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (InstancePtr->Config.Is32BitFiltering == 0U) + { + RegVal = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_IDMASK_OFFSET); + RegVal = RegVal & XAPM_MASKID_RID_MASK; + RdMask = RegVal >> 16; + } else { + RdMask = XAxiPmon_ReadReg(InstancePtr->Config.BaseAddress, + XAPM_RIDMASK_OFFSET); + } + + return RdMask; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.h new file mode 100644 index 000000000..f8d4d6467 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon.h @@ -0,0 +1,938 @@ +/****************************************************************************** +* +* Copyright (C) 2007 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xaxipmon.h +* @addtogroup axipmon_v6_3 +* @{ +* @details +* +* The XAxiPmon driver supports the Xilinx AXI Performance Monitor device. +* +* The AXI Performance Monitor device provides following features: +* +* Configurable number of Metric Counters and Incrementers +* Computes performance metrics for Agents connected to +* monitor slots (Up to 8 slots) +* +* The following Metrics can be computed: +* +* Metrics computed for an AXI4 MM agent: +* Write Request Count: Total number of write requests by/to the agent. +* Read Request Count: Total number of read requests given by/to the +* agent. +* Read Latency: It is defined as the time from the start of read address +* transaction to the beginning of the read data service. +* Write Latency: It is defined as the period needed a master completes +* write data transaction, i.e. from write address +* transaction to write response from slave. +* Write Byte Count: Total number of bytes written by/to the agent. +* This metric is helpful when calculating the +* throughput of the system. +* Read Byte Count: Total number of bytes read from/by the agent. +* Average Write Latency: Average write latency seen by the agent. +* It can be derived from total write latency +* and the write request count. +* Average Read Latency: Average read latency seen by the agent. It can be +* derived from total read latency and the read +* request count. +* Master Write Idle Cycle Count: Number of idle cycles caused by the +* masters during write transactions to +* the slave. +* Slave Write Idle Cycle Count: Number of idle cycles caused by this slave +* during write transactions to the slave. +* Master Read Idle Cycle Count: Number of idle cycles caused by the +* master during read transactions to the +* slave. +* Slave Read Idle Cycle Count: Number of idle cycles caused by this slave +* during read transactions to the slave. +* +* Metrics computed for an AXI4-Stream agent: +* +* Transfer Cycle Count: Total number of writes by/to the agent. +* Data Byte Count: Total number of data bytes written by/to the agent. +* This metric helps in calculating the throughput +* of the system. +* Position Byte Count: Total number of position bytes transferred. +* Null Byte Count: Total number of null bytes transferred. +* Packet Count: Total number of packets transferred. +* +* There are three modes : Advanced, Profile and Trace. +* - Advanced mode has 10 Mertic Counters, Sampled Metric Counters, Incrementors +* and Sampled Incrementors. +* - Profile mode has only 47 Metric Counters and Sampled Metric Counters. +* - Trace mode has no Counters. +* User should refer to the hardware device specification for detailed +* information about the device. +* +* This header file contains the prototypes of driver functions that can +* be used to access the AXI Performance Monitor device. +* +* +* Initialization and Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the AXI Performance Monitor device. +* +* XAxiPmon_CfgInitialize() API is used to initialize the AXI Performance Monitor +* device. The user needs to first call the XAxiPmon_LookupConfig() API which +* returns the Configuration structure pointer which is passed as a parameter to +* the XAxiPmon_CfgInitialize() API. +* +* +* Interrupts +* +* The AXI Performance Monitor does not support Interrupts +* +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* +* Building the driver +* +* The XAxiPmon driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* Limitations of the driver +* +* +*

+* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    02/27/12 First release
+* 2.00a bss    06/23/12 Updated to support v2_00a version of IP.
+* 3.00a bss    09/03/12 To support v2_01_a version of IP:
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
+*			added XAPM_FLAG_EVENT, XAPM_FLAG_EVNTSTAR,
+*			XAPM_FLAG_EVNTSTOP.
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent APIs and
+*			modified XAxiPmon_SetMetrics, XAxiPmon_GetMetrics APIs
+*			in xaxipmon.c
+*			Deleted XAPM_AGENT_OFFSET Macro in xaxipmon_hw.h
+* 3.01a bss    10/25/12 To support new version of IP:
+*			Added XAPM_MCXLOGEN_OFFSET macros in xaxipmon_hw.h.
+*			Added XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
+*			Modified XAxiPmon_SetMetrics and XAxiPmon_GetMetrics
+*			(CR #683746) in xaxipmon.c
+*			Added XAxiPmon_EnableEventLog,
+*			XAxiPmon_DisableMetricsCounter,
+*			XAxiPmon_EnableMetricsCounter APIs in xaxipmon.c to
+*			replace macros in this file.
+*			Added XAPM_FLAG_XXX macros.
+*			Added XAxiPmon_StartCounters and XAxiPmon_StopCounters
+*			APIs (CR #683799).
+*			Added XAxiPmon_StartEventLog and XAxiPmon_StopEventLog
+*			APIs (CR #683801).
+*			Added XAxiPmon_GetMetricName API (CR #683803).
+*			Deleted XAxiPmon_SetAgent, XAxiPmon_GetAgent
+*			declarations (CR #677337)
+* 4.00a bss    01/17/13 To support new version of IP:
+*			Added XAPM_METRIC_SET_12 to XAPM_METRIC_SET_15 macros.
+*			Added XAxiPmon_SetLogEnableRanges,
+*	  		XAxiPmon_GetLogEnableRanges,
+*			XAxiPmon_EnableMetricCounterTrigger,
+*			XAxiPmon_DisableMetricCounterTrigger,
+*			XAxiPmon_EnableEventLogTrigger,
+*			XAxiPmon_DisableEventLogTrigger,
+*			XAxiPmon_SetWriteLatencyId,
+*			XAxiPmon_SetReadLatencyId,
+*			XAxiPmon_GetWriteLatencyId,
+*			XAxiPmon_GetReadLatencyId APIs and removed
+*			XAxiPmon_SetMetricCounterCutOff,
+*			XAxiPmon_GetMetricCounterCutOff,
+*			XAxiPmon_EnableExternalTrigger and
+*			XAxiPmon_DisableExternalTrigger APIs in xaxipmon.c
+*			Added XAPM_LATENCYID_OFFSET,
+*			XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
+*			XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK in
+*			xaxipmon_hw.h
+* 5.00a bss   08/26/13  To support new version of IP:
+*			XAxiPmon_SampleMetrics Macro.
+*			Modified XAxiPmon_CfgInitialize, Assert functions
+*			Added XAxiPmon_GetMetricCounter,
+*			XAxiPmon_SetSampleInterval, XAxiPmon_GetSampleInterval,
+*			XAxiPmon_SetWrLatencyStart, XAxiPmon_SetWrLatencyEnd,
+*			XAxiPmon_SetRdLatencyStart, XAxiPmon_SetRdLatencyEnd,
+*			XAxiPmon_GetWrLatencyStart, XAxiPmon_GetWrLatencyEnd,
+*			XAxiPmon_GetRdLatencyStart, XAxiPmon_GetRdLatencyEnd,
+*			XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask,
+*			XAxiPmon_GetWriteIdMask and XAxiPmon_GetReadIdMask APIs
+*			Renamed :
+*			XAxiPmon_SetWriteLatencyId to
+*			XAxiPmon_SetWriteId, XAxiPmon_SetReadLatencyId to
+*			XAxiPmon_SetReadId, XAxiPmon_GetWriteLatencyId to
+*			XAxiPmon_GetWriteId and XAxiPmon_SetReadLatencyId to
+*			XAxiPmon_GetReadId. in xaxipmon.c
+*			Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
+*			XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET,
+*			XAPM_IDMASK_OFFSET, XAPM_CR_IDFILTER_ENABLE_MASK,
+*			XAPM_CR_WRLATENCY_START_MASK,
+*			XAPM_CR_WRLATENCY_END_MASK,
+*			XAPM_CR_RDLATENCY_START_MASK,
+*			XAPM_CR_RDLATENCY_END_MASK and
+*			XAPM_MAX_COUNTERS_PROFILE.
+*			Renamed:
+*			XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
+*			XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
+*			XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
+*			in xaxipmon_hw.h.
+*			Modified driver tcl to generate new parameters
+*			ScaleFactor, ModeProfile, ModeTrace and ModeAdvanced
+*			in Config structure.
+* 6.0   adk  19/12/13 Updated as per the New Tcl API's
+* 6.1   adk  16/04/14 Updated the driver tcl for the newly added parameters in
+* 		      The Axi pmon IP.
+* 6.2   bss  04/21/14   Updated XAxiPmon_CfgInitialize in xaxipmon.c to Reset
+*			counters and FIFOs based on Modes(CR#782671). And if
+*			both profile and trace modes are present set mode as
+*			Advanced.
+* 6.2	bss  03/02/15	To support Zynq MP APM:
+*						Added Is32BitFiltering in XAxiPmon_Config structure.
+*						Updated XAxiPmon_SetWriteId, XAxiPmon_SetReadId,
+*						XAxiPmon_GetWriteId, XAxiPmon_GetReadId
+*						XAxiPmon_SetWriteIdMask, XAxiPmon_SetReadIdMask
+*						XAxiPmon_GetWriteIdMask, XAxiPmon_GetReadIdMask
+*						functions in xaxipmon.c.
+*						Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET in
+*						xaxipmon_hw.h
+*
+* 6.3	kvn  07/02/15	Modified code according to MISRA-C:2012 guidelines.
+* 6.4   sk   11/10/15 Used UINTPTR instead of u32 for Baseaddress CR# 867425.
+*                     Changed the prototype of XAxiPmon_CfgInitialize API.
+*
+* +*****************************************************************************/ +#ifndef XAXIPMON_H /* Prevent circular inclusions */ +#define XAXIPMON_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xaxipmon_hw.h" + +/************************** Constant Definitions ****************************/ + + +/** + * @name Macro for Maximum number of Counters + * + * @{ + */ +#define XAPM_MAX_COUNTERS 10U /**< Maximum number of Counters */ +#define XAPM_MAX_COUNTERS_PROFILE 48U /**< Maximum number of Counters */ + +/*@}*/ + + +/** + * @name Indices for Metric Counters and Sampled Metric Coounters used with + * XAxiPmon_GetMetricCounter and XAxiPmon_GetSampledMetricCounter APIs + * @{ + */ + +#define XAPM_METRIC_COUNTER_0 0U /**< Metric Counter 0 Register Index */ +#define XAPM_METRIC_COUNTER_1 1U /**< Metric Counter 1 Register Index */ +#define XAPM_METRIC_COUNTER_2 2U /**< Metric Counter 2 Register Index */ +#define XAPM_METRIC_COUNTER_3 3U /**< Metric Counter 3 Register Index */ +#define XAPM_METRIC_COUNTER_4 4U /**< Metric Counter 4 Register Index */ +#define XAPM_METRIC_COUNTER_5 5U /**< Metric Counter 5 Register Index */ +#define XAPM_METRIC_COUNTER_6 6U /**< Metric Counter 6 Register Index */ +#define XAPM_METRIC_COUNTER_7 7U /**< Metric Counter 7 Register Index */ +#define XAPM_METRIC_COUNTER_8 8U /**< Metric Counter 8 Register Index */ +#define XAPM_METRIC_COUNTER_9 9U /**< Metric Counter 9 Register Index */ + +/*@}*/ + +/** + * @name Indices for Incrementers and Sampled Incrementers used with + * XAxiPmon_GetIncrementer and XAxiPmon_GetSampledIncrementer APIs + * @{ + */ + +#define XAPM_INCREMENTER_0 0U /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_1 1U /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_2 2U /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_3 3U /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_4 4U /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_5 5U /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_6 6U /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_7 7U /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_8 8U /**< Metric Counter 0 Register Index */ +#define XAPM_INCREMENTER_9 9U /**< Metric Counter 0 Register Index */ + +/*@}*/ + +/** + * @name Macros for Metric Selector Settings + * @{ + */ + +#define XAPM_METRIC_SET_0 0U /**< Write Transaction Count */ +#define XAPM_METRIC_SET_1 1U /**< Read Transaction Count */ +#define XAPM_METRIC_SET_2 2U /**< Write Byte Count */ +#define XAPM_METRIC_SET_3 3U /**< Read Byte Count */ +#define XAPM_METRIC_SET_4 4U /**< Write Beat Count */ +#define XAPM_METRIC_SET_5 5U /**< Total Read Latency */ +#define XAPM_METRIC_SET_6 6U /**< Total Write Latency */ +#define XAPM_METRIC_SET_7 7U /**< Slv_Wr_Idle_Cnt */ +#define XAPM_METRIC_SET_8 8U /**< Mst_Rd_Idle_Cnt */ +#define XAPM_METRIC_SET_9 9U /**< Num_BValids */ +#define XAPM_METRIC_SET_10 10U /**< Num_WLasts */ +#define XAPM_METRIC_SET_11 11U /**< Num_RLasts */ +#define XAPM_METRIC_SET_12 12U /**< Minimum Write Latency */ +#define XAPM_METRIC_SET_13 13U /**< Maximum Write Latency */ +#define XAPM_METRIC_SET_14 14U /**< Minimum Read Latency */ +#define XAPM_METRIC_SET_15 15U /**< Maximum Read Latency */ +#define XAPM_METRIC_SET_16 16U /**< Transfer Cycle Count */ +#define XAPM_METRIC_SET_17 17U /**< Packet Count */ +#define XAPM_METRIC_SET_18 18U /**< Data Byte Count */ +#define XAPM_METRIC_SET_19 19U /**< Position Byte Count */ +#define XAPM_METRIC_SET_20 20U /**< Null Byte Count */ +#define XAPM_METRIC_SET_21 21U /**< Slv_Idle_Cnt */ +#define XAPM_METRIC_SET_22 22U /**< Mst_Idle_Cnt */ +#define XAPM_METRIC_SET_30 30U /**< External event count */ + + +/*@}*/ + + +/** + * @name Macros for Maximum number of Agents + * @{ + */ + +#define XAPM_MAX_AGENTS 8U /**< Maximum number of Agents */ + +/*@}*/ + +/** + * @name Macros for Flags in Flag Enable Control Register + * @{ + */ + +#define XAPM_FLAG_WRADDR 0x00000001 /**< Write Address Flag */ +#define XAPM_FLAG_FIRSTWR 0x00000002 /**< First Write Flag */ +#define XAPM_FLAG_LASTWR 0x00000004 /**< Last Write Flag */ +#define XAPM_FLAG_RESPONSE 0x00000008 /**< Response Flag */ +#define XAPM_FLAG_RDADDR 0x00000010 /**< Read Address Flag */ +#define XAPM_FLAG_FIRSTRD 0x00000020 /**< First Read Flag */ +#define XAPM_FLAG_LASTRD 0x00000040 /**< Last Read Flag */ +#define XAPM_FLAG_SWDATA 0x00010000 /**< Software-written Data Flag */ +#define XAPM_FLAG_EVENT 0x00020000 /**< Last Read Flag */ +#define XAPM_FLAG_EVNTSTOP 0x00040000 /**< Last Read Flag */ +#define XAPM_FLAG_EVNTSTART 0x00080000 /**< Last Read Flag */ +#define XAPM_FLAG_GCCOVF 0x00100000 /**< Global Clock Counter Overflow + * Flag */ +#define XAPM_FLAG_SCLAPSE 0x00200000 /**< Sample Counter Lapse Flag */ +#define XAPM_FLAG_MC0 0x00400000U /**< Metric Counter 0 Flag */ +#define XAPM_FLAG_MC1 0x00800000U /**< Metric Counter 1 Flag */ +#define XAPM_FLAG_MC2 0x01000000U /**< Metric Counter 2 Flag */ +#define XAPM_FLAG_MC3 0x02000000U /**< Metric Counter 3 Flag */ +#define XAPM_FLAG_MC4 0x04000000U /**< Metric Counter 4 Flag */ +#define XAPM_FLAG_MC5 0x08000000U /**< Metric Counter 5 Flag */ +#define XAPM_FLAG_MC6 0x10000000U /**< Metric Counter 6 Flag */ +#define XAPM_FLAG_MC7 0x20000000U /**< Metric Counter 7 Flag */ +#define XAPM_FLAG_MC8 0x40000000U /**< Metric Counter 8 Flag */ +#define XAPM_FLAG_MC9 0x80000000U /**< Metric Counter 9 Flag */ + +/*@}*/ + +/** + * @name Macros for Read/Write Latency Start and End points + * @{ + */ +#define XAPM_LATENCY_ADDR_ISSUE 0U /**< Address Issue as start + point for Latency calculation*/ +#define XAPM_LATENCY_ADDR_ACCEPT 1U /**< Address Acceptance as start + point for Latency calculation*/ +#define XAPM_LATENCY_LASTRD 0U /**< Last Read as end point for + Latency calculation */ +#define XAPM_LATENCY_LASTWR 0U /**< Last Write as end point for + Latency calculation */ +#define XAPM_LATENCY_FIRSTRD 1U /**< First Read as end point for + Latency calculation */ +#define XAPM_LATENCY_FIRSTWR 1U /**< First Write as end point for + Latency calculation */ + +/*@}*/ + +/** + * @name Macros for Modes of APM + * @{ + */ + +#define XAPM_MODE_TRACE 2U /**< APM in Trace mode */ + +#define XAPM_MODE_PROFILE 1U /**< APM in Profile mode */ + +#define XAPM_MODE_ADVANCED 0U /**< APM in Advanced mode */ + +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for the AXI Performance + * Monitor device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + UINTPTR BaseAddress; /**< Device base address */ + s32 GlobalClkCounterWidth; /**< Global Clock Counter Width */ + s32 MetricSampleCounterWidth ; /**< Metric Sample Counters Width */ + u8 IsEventCount; /**< Event Count Enabled 1 - enabled + 0 - not enabled */ + u8 NumberofSlots; /**< Number of Monitor Slots */ + u8 NumberofCounters; /**< Number of Counters */ + u8 HaveSampledCounters; /**< Have Sampled Counters 1 - present + 0 - Not present */ + u8 IsEventLog; /**< Event Logging Enabled 1 - enabled + 0 - Not enabled */ + u32 FifoDepth; /**< Event Log FIFO Depth */ + u32 FifoWidth; /**< Event Log FIFO Width */ + u32 TidWidth; /**< Streaming Interface TID Width */ + u8 ScaleFactor; /**< Event Count Scaling factor */ + u8 ModeAdvanced; /**< Advanced Mode */ + u8 ModeProfile; /**< Profile Mode */ + u8 ModeTrace; /**< Trace Mode */ + u8 Is32BitFiltering; /**< 32 bit filtering enabled */ +} XAxiPmon_Config; + + +/** + * The driver's instance data. The user is required to allocate a variable + * of this type for every AXI Performance Monitor device in system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XAxiPmon_Config Config; /**< XAxiPmon_Config of current device */ + u32 IsReady; /**< Device is initialized and ready */ + u8 Mode; /**< APM Mode */ +} XAxiPmon; + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/****************************************************************************/ +/** +* +* This routine enables the Global Interrupt. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrGlobalEnable(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_IntrGlobalEnable(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \ + XAPM_GIE_OFFSET, 1) + + +/****************************************************************************/ +/** +* +* This routine disables the Global Interrupt. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrGlobalDisable(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_IntrGlobalDisable(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, \ + XAPM_GIE_OFFSET, 0) + + +/****************************************************************************/ +/** +* +* This routine enables interrupt(s). Use the XAPM_IXR_* constants defined in +* xaxipmon_hw.h to create the bit-mask to enable interrupts. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Mask is the mask to enable. Bit positions of 1 will be enabled. +* Bit positions of 0 will keep the previous setting. This mask is +* formed by OR'ing XAPM_IXR__* bits defined in xaxipmon_hw.h. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XAxiPmon_IntrEnable(InstancePtr, Mask) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IE_OFFSET) | (Mask)); + + +/****************************************************************************/ +/** +* +* This routine disable interrupt(s). Use the XAPM_IXR_* constants defined in +* xaxipmon_hw.h to create the bit-mask to disable interrupts. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Mask is the mask to disable. Bit positions of 1 will be +* disabled. Bit positions of 0 will keep the previous setting. +* This mask is formed by OR'ing XAPM_IXR_* bits defined in +* xaxipmon_hw.h. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrEnable(XAxiPmon *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XAxiPmon_IntrDisable(InstancePtr, Mask) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IE_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IE_OFFSET) | (Mask)); + +/****************************************************************************/ +/** +* +* This routine clears the specified interrupt(s). +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Mask is the mask to clear. Bit positions of 1 will be cleared. +* This mask is formed by OR'ing XAPM_IXR_* bits defined in +* xaxipmon_hw.h. +* +* @return None. +* +* @note C-Style signature: +* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XAxiPmon_IntrClear(InstancePtr, Mask) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_IS_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IS_OFFSET) | (Mask)); + +/****************************************************************************/ +/** +* +* This routine returns the Interrupt Status Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Interrupt Status Register contents +* +* @note C-Style signature: +* void XAxiPmon_IntrClear(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_IntrGetStatus(InstancePtr) \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_IS_OFFSET); + +/****************************************************************************/ +/** +* +* This function enables the Global Clock Counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableGlobalClkCounter(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_EnableGlobalClkCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) | XAPM_CR_GCC_ENABLE_MASK); + +/****************************************************************************/ +/** +* +* This function disbles the Global Clock Counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableGlobalClkCounter(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_DisableGlobalClkCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) & ~(XAPM_CR_GCC_ENABLE_MASK)); + +/****************************************************************************/ +/** +* +* This function enables the specified flag in Flag Control Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableFlag(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_EnableFlag(InstancePtr, Flag) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_FEC_OFFSET) | (Flag)); + +/****************************************************************************/ +/** +* +* This function disables the specified flag in Flag Control Register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* @param Flag is one of the XAPM_FLAG_* masks defined in xaxipmon.h* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableFlag(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_DisableFlag(InstancePtr, Flag) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_FEC_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_FEC_OFFSET) & ~(Flag)); + +/****************************************************************************/ +/** +* +* This function loads the sample interval register value into the sample +* interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_LoadSampleIntervalCounter(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_LoadSampleIntervalCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \ + XAPM_SICR_LOAD_MASK); + + + +/****************************************************************************/ +/** +* +* This enables the down count of the sample interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableSampleIntervalCounter(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_EnableSampleIntervalCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\ + XAPM_SICR_ENABLE_MASK); + + +/****************************************************************************/ +/** +* +* This disables the down count of the sample interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableSampleIntervalCounter(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_DisableSampleIntervalCounter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_SICR_OFFSET) & ~(XAPM_SICR_ENABLE_MASK)); + +/****************************************************************************/ +/** +* +* This enables Reset of Metric Counters when Sample Interval Counter lapses. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableMetricCounterReset(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_EnableMetricCounterReset(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET,\ + XAPM_SICR_MCNTR_RST_MASK); + +/****************************************************************************/ +/** +* +* This disables the down count of the sample interval counter. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableMetricCounterReset(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_DisableMetricCounterReset(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_SICR_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_SICR_OFFSET) & ~(XAPM_SICR_MCNTR_RST_MASK)); + +/****************************************************************************/ +/** +* +* This function enables the ID Filter Masking. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_EnableIDFilter(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_EnableIDFilter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) | XAPM_CR_IDFILTER_ENABLE_MASK); + +/****************************************************************************/ +/** +* +* This function disbles the ID Filter masking. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return None +* +* @note C-Style signature: +* void XAxiPmon_DisableIDFilter(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_DisableIDFilter(InstancePtr) \ + XAxiPmon_WriteReg((InstancePtr)->Config.BaseAddress, XAPM_CTL_OFFSET, \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, \ + XAPM_CTL_OFFSET) & ~(XAPM_CR_IDFILTER_ENABLE_MASK)); + +/****************************************************************************/ +/** +* +* This function samples Metric Counters to Sampled Metric Counters by +* reading Sample Register and also returns interval. i.e. the number of +* clocks in between previous read to the current read of sample register. +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return Interval. i.e. the number of clocks in between previous +* read to the current read of sample register. +* +* @note C-Style signature: +* u32 XAxiPmon_SampleMetrics(XAxiPmon *InstancePtr) +* +*****************************************************************************/ +#define XAxiPmon_SampleMetrics(InstancePtr) \ + XAxiPmon_ReadReg((InstancePtr)->Config.BaseAddress, XAPM_SR_OFFSET); + + +/************************** Function Prototypes *****************************/ + +/** + * Functions in xaxipmon_sinit.c + */ +XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId); + +/** + * Functions in xaxipmon.c + */ +s32 XAxiPmon_CfgInitialize(XAxiPmon *InstancePtr, + XAxiPmon_Config *ConfigPtr, UINTPTR EffectiveAddr); + +s32 XAxiPmon_ResetMetricCounter(XAxiPmon *InstancePtr); + +void XAxiPmon_ResetGlobalClkCounter(XAxiPmon *InstancePtr); + +s32 XAxiPmon_ResetFifo(XAxiPmon *InstancePtr); + +void XAxiPmon_SetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum, + u16 RangeUpper, u16 RangeLower); + +void XAxiPmon_GetIncrementerRange(XAxiPmon *InstancePtr, u8 IncrementerNum, + u16 *RangeUpper, u16 *RangeLower); + +void XAxiPmon_SetSampleInterval(XAxiPmon *InstancePtr, u32 SampleInterval); + +void XAxiPmon_GetSampleInterval(XAxiPmon *InstancePtr, u32 *SampleInterval); + +s32 XAxiPmon_SetMetrics(XAxiPmon *InstancePtr, u8 Slot, u8 Metrics, + u8 CounterNum); + +s32 XAxiPmon_GetMetrics(XAxiPmon *InstancePtr, u8 CounterNum, u8 *Metrics, + u8 *Slot); +void XAxiPmon_GetGlobalClkCounter(XAxiPmon *InstancePtr,u32 *CntHighValue, + u32 *CntLowValue); + +u32 XAxiPmon_GetMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum); + +u32 XAxiPmon_GetSampledMetricCounter(XAxiPmon *InstancePtr, u32 CounterNum); + +u32 XAxiPmon_GetIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum); + +u32 XAxiPmon_GetSampledIncrementer(XAxiPmon *InstancePtr, u32 IncrementerNum); + +void XAxiPmon_SetSwDataReg(XAxiPmon *InstancePtr, u32 SwData); + +u32 XAxiPmon_GetSwDataReg(XAxiPmon *InstancePtr); + +s32 XAxiPmon_StartEventLog(XAxiPmon *InstancePtr, u32 FlagEnables); + +s32 XAxiPmon_StopEventLog(XAxiPmon *InstancePtr); + +s32 XAxiPmon_StartCounters(XAxiPmon *InstancePtr, u32 SampleInterval); + +s32 XAxiPmon_StopCounters(XAxiPmon *InstancePtr); + +void XAxiPmon_EnableMetricsCounter(XAxiPmon *InstancePtr); + +void XAxiPmon_DisableMetricsCounter(XAxiPmon *InstancePtr); + +void XAxiPmon_SetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum, + u16 RangeUpper, u16 RangeLower); + +void XAxiPmon_GetLogEnableRanges(XAxiPmon *InstancePtr, u32 CounterNum, + u16 *RangeUpper, u16 *RangeLower); + +void XAxiPmon_EnableEventLog(XAxiPmon *InstancePtr); + +void XAxiPmon_EnableMetricCounterTrigger(XAxiPmon *InstancePtr); + +void XAxiPmon_DisableMetricCounterTrigger(XAxiPmon *InstancePtr); + +void XAxiPmon_EnableEventLogTrigger(XAxiPmon *InstancePtr); + +void XAxiPmon_DisableEventLogTrigger(XAxiPmon *InstancePtr); + +const char * XAxiPmon_GetMetricName(u8 Metrics); + +void XAxiPmon_SetWriteId(XAxiPmon *InstancePtr, u32 WriteId); + +void XAxiPmon_SetReadId(XAxiPmon *InstancePtr, u32 ReadId); + +u32 XAxiPmon_GetWriteId(XAxiPmon *InstancePtr); + +u32 XAxiPmon_GetReadId(XAxiPmon *InstancePtr); + +void XAxiPmon_SetWrLatencyStart(XAxiPmon *InstancePtr, u8 Param); + +void XAxiPmon_SetWrLatencyEnd(XAxiPmon *InstancePtr, u8 Param); + +void XAxiPmon_SetRdLatencyStart(XAxiPmon *InstancePtr, u8 Param); + +void XAxiPmon_SetRdLatencyEnd(XAxiPmon *InstancePtr, u8 Param); + +u8 XAxiPmon_GetWrLatencyStart(XAxiPmon *InstancePtr); + +u8 XAxiPmon_GetWrLatencyEnd(XAxiPmon *InstancePtr); + +u8 XAxiPmon_GetRdLatencyStart(XAxiPmon *InstancePtr); + +u8 XAxiPmon_GetRdLatencyEnd(XAxiPmon *InstancePtr); + +void XAxiPmon_SetWriteIdMask(XAxiPmon *InstancePtr, u32 WrMask); + +void XAxiPmon_SetReadIdMask(XAxiPmon *InstancePtr, u32 RdMask); + +u32 XAxiPmon_GetWriteIdMask(XAxiPmon *InstancePtr); + +u32 XAxiPmon_GetReadIdMask(XAxiPmon *InstancePtr); + + +/** + * Functions in xaxipmon_selftest.c + */ +s32 XAxiPmon_SelfTest(XAxiPmon *InstancePtr); + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c new file mode 100644 index 000000000..a33878ef5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_g.c @@ -0,0 +1,127 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xaxipmon.h" + +/* +* The configuration table for devices +*/ + +XAxiPmon_Config XAxiPmon_ConfigTable[] = +{ + { + XPAR_PSU_APM_0_DEVICE_ID, + XPAR_PSU_APM_0_BASEADDR, + XPAR_PSU_APM_0_GLOBAL_COUNT_WIDTH, + XPAR_PSU_APM_0_METRICS_SAMPLE_COUNT_WIDTH, + XPAR_PSU_APM_0_ENABLE_EVENT_COUNT, + XPAR_PSU_APM_0_NUM_MONITOR_SLOTS, + XPAR_PSU_APM_0_NUM_OF_COUNTERS, + XPAR_PSU_APM_0_HAVE_SAMPLED_METRIC_CNT, + XPAR_PSU_APM_0_ENABLE_EVENT_LOG, + XPAR_PSU_APM_0_FIFO_AXIS_DEPTH, + XPAR_PSU_APM_0_FIFO_AXIS_TDATA_WIDTH, + XPAR_PSU_APM_0_FIFO_AXIS_TID_WIDTH, + XPAR_PSU_APM_0_METRIC_COUNT_SCALE, + XPAR_PSU_APM_0_ENABLE_ADVANCED, + XPAR_PSU_APM_0_ENABLE_PROFILE, + XPAR_PSU_APM_0_ENABLE_TRACE, + XPAR_PSU_APM_0_ENABLE_32BIT_FILTER_ID + }, + { + XPAR_PSU_APM_1_DEVICE_ID, + XPAR_PSU_APM_1_BASEADDR, + XPAR_PSU_APM_1_GLOBAL_COUNT_WIDTH, + XPAR_PSU_APM_1_METRICS_SAMPLE_COUNT_WIDTH, + XPAR_PSU_APM_1_ENABLE_EVENT_COUNT, + XPAR_PSU_APM_1_NUM_MONITOR_SLOTS, + XPAR_PSU_APM_1_NUM_OF_COUNTERS, + XPAR_PSU_APM_1_HAVE_SAMPLED_METRIC_CNT, + XPAR_PSU_APM_1_ENABLE_EVENT_LOG, + XPAR_PSU_APM_1_FIFO_AXIS_DEPTH, + XPAR_PSU_APM_1_FIFO_AXIS_TDATA_WIDTH, + XPAR_PSU_APM_1_FIFO_AXIS_TID_WIDTH, + XPAR_PSU_APM_1_METRIC_COUNT_SCALE, + XPAR_PSU_APM_1_ENABLE_ADVANCED, + XPAR_PSU_APM_1_ENABLE_PROFILE, + XPAR_PSU_APM_1_ENABLE_TRACE, + XPAR_PSU_APM_1_ENABLE_32BIT_FILTER_ID + }, + { + XPAR_PSU_APM_2_DEVICE_ID, + XPAR_PSU_APM_2_BASEADDR, + XPAR_PSU_APM_2_GLOBAL_COUNT_WIDTH, + XPAR_PSU_APM_2_METRICS_SAMPLE_COUNT_WIDTH, + XPAR_PSU_APM_2_ENABLE_EVENT_COUNT, + XPAR_PSU_APM_2_NUM_MONITOR_SLOTS, + XPAR_PSU_APM_2_NUM_OF_COUNTERS, + XPAR_PSU_APM_2_HAVE_SAMPLED_METRIC_CNT, + XPAR_PSU_APM_2_ENABLE_EVENT_LOG, + XPAR_PSU_APM_2_FIFO_AXIS_DEPTH, + XPAR_PSU_APM_2_FIFO_AXIS_TDATA_WIDTH, + XPAR_PSU_APM_2_FIFO_AXIS_TID_WIDTH, + XPAR_PSU_APM_2_METRIC_COUNT_SCALE, + XPAR_PSU_APM_2_ENABLE_ADVANCED, + XPAR_PSU_APM_2_ENABLE_PROFILE, + XPAR_PSU_APM_2_ENABLE_TRACE, + XPAR_PSU_APM_2_ENABLE_32BIT_FILTER_ID + }, + { + XPAR_PSU_APM_5_DEVICE_ID, + XPAR_PSU_APM_5_BASEADDR, + XPAR_PSU_APM_5_GLOBAL_COUNT_WIDTH, + XPAR_PSU_APM_5_METRICS_SAMPLE_COUNT_WIDTH, + XPAR_PSU_APM_5_ENABLE_EVENT_COUNT, + XPAR_PSU_APM_5_NUM_MONITOR_SLOTS, + XPAR_PSU_APM_5_NUM_OF_COUNTERS, + XPAR_PSU_APM_5_HAVE_SAMPLED_METRIC_CNT, + XPAR_PSU_APM_5_ENABLE_EVENT_LOG, + XPAR_PSU_APM_5_FIFO_AXIS_DEPTH, + XPAR_PSU_APM_5_FIFO_AXIS_TDATA_WIDTH, + XPAR_PSU_APM_5_FIFO_AXIS_TID_WIDTH, + XPAR_PSU_APM_5_METRIC_COUNT_SCALE, + XPAR_PSU_APM_5_ENABLE_ADVANCED, + XPAR_PSU_APM_5_ENABLE_PROFILE, + XPAR_PSU_APM_5_ENABLE_TRACE, + XPAR_PSU_APM_5_ENABLE_32BIT_FILTER_ID + } +}; + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_hw.h new file mode 100644 index 000000000..68ed57aaf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_hw.h @@ -0,0 +1,571 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** +* +* @file xaxipmon_hw.h +* @addtogroup axipmon_v6_3 +* @{ +* +* This header file contains identifiers and basic driver functions (or +* macros) that can be used to access the AXI Performance Monitor. +* +* Refer to the device specification for more information about this driver. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss    02/27/12 First release
+* 2.00a bss    06/23/12 Updated to support v2_00a version of IP.
+* 3.00a bss    09/03/12 Deleted XAPM_AGENT_OFFSET Macro to support
+*			v2_01a version of IP.
+* 3.01a bss    10/25/12 To support new version of IP:
+*			Added XAPM_MCXLOGEN_OFFSET and
+*			XAPM_CR_EXTERNAL_TRIGGER_MASK macros.
+* 4.00a bss    01/17/13 To support new version of IP:
+*			Added XAPM_LATENCYID_OFFSET,
+*			XAPM_CR_EVTLOG_EXTTRIGGER_MASK,
+*			XAPM_LATENCYID_RID_MASK and XAPM_LATENCYID_WID_MASK
+* 5.00a bss   08/26/13  To support new version of IP:
+*			Added Macros XAPM_MC10_OFFSET to XAPM_MC47_OFFSET,
+*			XAPM_SMC10_OFFSET to XAPM_SMC47_OFFSET.
+*			Added macro XAPM_IDMASK_OFFSET, XAPM_SR_OFFSET.
+*			Added XAPM_CR_IDFILTER_ENABLE_MASK,
+*			XAPM_CR_WRLATENCY_START_MASK,
+*			XAPM_CR_WRLATENCY_END_MASK,
+*			XAPM_CR_RDLATENCY_START_MASK,
+*			XAPM_CR_RDLATENCY_END_MASK, XAPM_MASKID_RID_MASK
+*			and XAPM_MASKID_WID_MASK macros.
+*			Renamed:
+*			XAPM_LATENCYID_OFFSET to XAPM_ID_OFFSET,
+*			XAPM_LATENCYID_RID_MASK to XAPM_ID_RID_MASK,
+*			XAPM_LATENCYID_WID_MASK to XAPM_ID_WID_MASK.
+*
+* 6.2  bss  03/02/15 Added XAPM_RID_OFFSET and XAPM_RIDMASK_OFFSET to support
+*					 Zynq MP APM.
+*
+* 6.3  kvn  07/02/15 Modified code according to MISRA-C:2012 guidelines.
+*
+* +*****************************************************************************/ +#ifndef XAXIPMON_HW_H /* Prevent circular inclusions */ +#define XAXIPMON_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions ****************************/ + + +/**@name Register offsets of AXIMONITOR in the Device Config + * + * The following constants provide access to each of the registers of the + * AXI PERFORMANCE MONITOR device. + * @{ + */ + +#define XAPM_GCC_HIGH_OFFSET 0x00000000U /**< Global Clock Counter + 32 to 63 bits */ +#define XAPM_GCC_LOW_OFFSET 0x00000004U /**< Global Clock Counter Lower + 0-31 bits */ +#define XAPM_SI_HIGH_OFFSET 0x00000020U /**< Sample Interval MSB */ +#define XAPM_SI_LOW_OFFSET 0x00000024U /**< Sample Interval LSB */ +#define XAPM_SICR_OFFSET 0x00000028U /**< Sample Interval Control + Register */ +#define XAPM_SR_OFFSET 0x0000002CU /**< Sample Register */ +#define XAPM_GIE_OFFSET 0x00000030U /**< Global Interrupt Enable + Register */ +#define XAPM_IE_OFFSET 0x00000034U /**< Interrupt Enable Register */ +#define XAPM_IS_OFFSET 0x00000038U /**< Interrupt Status Register */ + +#define XAPM_MSR0_OFFSET 0x00000044U /**< Metric Selector 0 Register */ +#define XAPM_MSR1_OFFSET 0x00000048U /**< Metric Selector 1 Register */ +#define XAPM_MSR2_OFFSET 0x0000004CU /**< Metric Selector 2 Register */ + +#define XAPM_MC0_OFFSET 0x00000100U /**< Metric Counter 0 Register */ +#define XAPM_INC0_OFFSET 0x00000104U /**< Incrementer 0 Register */ +#define XAPM_RANGE0_OFFSET 0x00000108U /**< Range 0 Register */ +#define XAPM_MC0LOGEN_OFFSET 0x0000010CU /**< Metric Counter 0 + Log Enable Register */ +#define XAPM_MC1_OFFSET 0x00000110U /**< Metric Counter 1 Register */ +#define XAPM_INC1_OFFSET 0x00000114U /**< Incrementer 1 Register */ +#define XAPM_RANGE1_OFFSET 0x00000118U /**< Range 1 Register */ +#define XAPM_MC1LOGEN_OFFSET 0x0000011CU /**< Metric Counter 1 + Log Enable Register */ +#define XAPM_MC2_OFFSET 0x00000120U /**< Metric Counter 2 Register */ +#define XAPM_INC2_OFFSET 0x00000124U /**< Incrementer 2 Register */ +#define XAPM_RANGE2_OFFSET 0x00000128U /**< Range 2 Register */ +#define XAPM_MC2LOGEN_OFFSET 0x0000012CU /**< Metric Counter 2 + Log Enable Register */ +#define XAPM_MC3_OFFSET 0x00000130U /**< Metric Counter 3 Register */ +#define XAPM_INC3_OFFSET 0x00000134U /**< Incrementer 3 Register */ +#define XAPM_RANGE3_OFFSET 0x00000138U /**< Range 3 Register */ +#define XAPM_MC3LOGEN_OFFSET 0x0000013CU /**< Metric Counter 3 + Log Enable Register */ +#define XAPM_MC4_OFFSET 0x00000140U /**< Metric Counter 4 Register */ +#define XAPM_INC4_OFFSET 0x00000144U /**< Incrementer 4 Register */ +#define XAPM_RANGE4_OFFSET 0x00000148U /**< Range 4 Register */ +#define XAPM_MC4LOGEN_OFFSET 0x0000014CU /**< Metric Counter 4 + Log Enable Register */ +#define XAPM_MC5_OFFSET 0x00000150U /**< Metric Counter 5 + Register */ +#define XAPM_INC5_OFFSET 0x00000154U /**< Incrementer 5 Register */ +#define XAPM_RANGE5_OFFSET 0x00000158U /**< Range 5 Register */ +#define XAPM_MC5LOGEN_OFFSET 0x0000015CU /**< Metric Counter 5 + Log Enable Register */ +#define XAPM_MC6_OFFSET 0x00000160U /**< Metric Counter 6 + Register */ +#define XAPM_INC6_OFFSET 0x00000164U /**< Incrementer 6 Register */ +#define XAPM_RANGE6_OFFSET 0x00000168U /**< Range 6 Register */ +#define XAPM_MC6LOGEN_OFFSET 0x0000016CU /**< Metric Counter 6 + Log Enable Register */ +#define XAPM_MC7_OFFSET 0x00000170U /**< Metric Counter 7 + Register */ +#define XAPM_INC7_OFFSET 0x00000174U /**< Incrementer 7 Register */ +#define XAPM_RANGE7_OFFSET 0x00000178U /**< Range 7 Register */ +#define XAPM_MC7LOGEN_OFFSET 0x0000017CU /**< Metric Counter 7 + Log Enable Register */ +#define XAPM_MC8_OFFSET 0x00000180U /**< Metric Counter 8 + Register */ +#define XAPM_INC8_OFFSET 0x00000184U /**< Incrementer 8 Register */ +#define XAPM_RANGE8_OFFSET 0x00000188U /**< Range 8 Register */ +#define XAPM_MC8LOGEN_OFFSET 0x0000018CU /**< Metric Counter 8 + Log Enable Register */ +#define XAPM_MC9_OFFSET 0x00000190U /**< Metric Counter 9 + Register */ +#define XAPM_INC9_OFFSET 0x00000194U /**< Incrementer 9 Register */ +#define XAPM_RANGE9_OFFSET 0x00000198U /**< Range 9 Register */ +#define XAPM_MC9LOGEN_OFFSET 0x0000019CU /**< Metric Counter 9 + Log Enable Register */ +#define XAPM_SMC0_OFFSET 0x00000200U /**< Sampled Metric Counter + 0 Register */ +#define XAPM_SINC0_OFFSET 0x00000204U /**< Sampled Incrementer + 0 Register */ +#define XAPM_SMC1_OFFSET 0x00000210U /**< Sampled Metric Counter + 1 Register */ +#define XAPM_SINC1_OFFSET 0x00000214U /**< Sampled Incrementer + 1 Register */ +#define XAPM_SMC2_OFFSET 0x00000220U /**< Sampled Metric Counter + 2 Register */ +#define XAPM_SINC2_OFFSET 0x00000224U /**< Sampled Incrementer + 2 Register */ +#define XAPM_SMC3_OFFSET 0x00000230U /**< Sampled Metric Counter + 3 Register */ +#define XAPM_SINC3_OFFSET 0x00000234U /**< Sampled Incrementer + 3 Register */ +#define XAPM_SMC4_OFFSET 0x00000240U /**< Sampled Metric Counter + 4 Register */ +#define XAPM_SINC4_OFFSET 0x00000244U /**< Sampled Incrementer + 4 Register */ +#define XAPM_SMC5_OFFSET 0x00000250U /**< Sampled Metric Counter + 5 Register */ +#define XAPM_SINC5_OFFSET 0x00000254U /**< Sampled Incrementer + 5 Register */ +#define XAPM_SMC6_OFFSET 0x00000260U /**< Sampled Metric Counter + 6 Register */ +#define XAPM_SINC6_OFFSET 0x00000264U /**< Sampled Incrementer + 6 Register */ +#define XAPM_SMC7_OFFSET 0x00000270U /**< Sampled Metric Counter + 7 Register */ +#define XAPM_SINC7_OFFSET 0x00000274U /**< Sampled Incrementer + 7 Register */ +#define XAPM_SMC8_OFFSET 0x00000280U /**< Sampled Metric Counter + 8 Register */ +#define XAPM_SINC8_OFFSET 0x00000284U /**< Sampled Incrementer + 8 Register */ +#define XAPM_SMC9_OFFSET 0x00000290U /**< Sampled Metric Counter + 9 Register */ +#define XAPM_SINC9_OFFSET 0x00000294U /**< Sampled Incrementer + 9 Register */ + +#define XAPM_MC10_OFFSET 0x000001A0U /**< Metric Counter 10 + Register */ +#define XAPM_MC11_OFFSET 0x000001B0U /**< Metric Counter 11 + Register */ +#define XAPM_MC12_OFFSET 0x00000500U /**< Metric Counter 12 + Register */ +#define XAPM_MC13_OFFSET 0x00000510U /**< Metric Counter 13 + Register */ +#define XAPM_MC14_OFFSET 0x00000520U /**< Metric Counter 14 + Register */ +#define XAPM_MC15_OFFSET 0x00000530U /**< Metric Counter 15 + Register */ +#define XAPM_MC16_OFFSET 0x00000540U /**< Metric Counter 16 + Register */ +#define XAPM_MC17_OFFSET 0x00000550U /**< Metric Counter 17 + Register */ +#define XAPM_MC18_OFFSET 0x00000560U /**< Metric Counter 18 + Register */ +#define XAPM_MC19_OFFSET 0x00000570U /**< Metric Counter 19 + Register */ +#define XAPM_MC20_OFFSET 0x00000580U /**< Metric Counter 20 + Register */ +#define XAPM_MC21_OFFSET 0x00000590U /**< Metric Counter 21 + Register */ +#define XAPM_MC22_OFFSET 0x000005A0U /**< Metric Counter 22 + Register */ +#define XAPM_MC23_OFFSET 0x000005B0U /**< Metric Counter 23 + Register */ +#define XAPM_MC24_OFFSET 0x00000700U /**< Metric Counter 24 + Register */ +#define XAPM_MC25_OFFSET 0x00000710U /**< Metric Counter 25 + Register */ +#define XAPM_MC26_OFFSET 0x00000720U /**< Metric Counter 26 + Register */ +#define XAPM_MC27_OFFSET 0x00000730U /**< Metric Counter 27 + Register */ +#define XAPM_MC28_OFFSET 0x00000740U /**< Metric Counter 28 + Register */ +#define XAPM_MC29_OFFSET 0x00000750U /**< Metric Counter 29 + Register */ +#define XAPM_MC30_OFFSET 0x00000760U /**< Metric Counter 30 + Register */ +#define XAPM_MC31_OFFSET 0x00000770U /**< Metric Counter 31 + Register */ +#define XAPM_MC32_OFFSET 0x00000780U /**< Metric Counter 32 + Register */ +#define XAPM_MC33_OFFSET 0x00000790U /**< Metric Counter 33 + Register */ +#define XAPM_MC34_OFFSET 0x000007A0U /**< Metric Counter 34 + Register */ +#define XAPM_MC35_OFFSET 0x000007B0U /**< Metric Counter 35 + Register */ +#define XAPM_MC36_OFFSET 0x00000900U /**< Metric Counter 36 + Register */ +#define XAPM_MC37_OFFSET 0x00000910U /**< Metric Counter 37 + Register */ +#define XAPM_MC38_OFFSET 0x00000920U /**< Metric Counter 38 + Register */ +#define XAPM_MC39_OFFSET 0x00000930U /**< Metric Counter 39 + Register */ +#define XAPM_MC40_OFFSET 0x00000940U /**< Metric Counter 40 + Register */ +#define XAPM_MC41_OFFSET 0x00000950U /**< Metric Counter 41 + Register */ +#define XAPM_MC42_OFFSET 0x00000960U /**< Metric Counter 42 + Register */ +#define XAPM_MC43_OFFSET 0x00000970U /**< Metric Counter 43 + Register */ +#define XAPM_MC44_OFFSET 0x00000980U /**< Metric Counter 44 + Register */ +#define XAPM_MC45_OFFSET 0x00000990U /**< Metric Counter 45 + Register */ +#define XAPM_MC46_OFFSET 0x000009A0U /**< Metric Counter 46 + Register */ +#define XAPM_MC47_OFFSET 0x000009B0U /**< Metric Counter 47 + Register */ + +#define XAPM_SMC10_OFFSET 0x000002A0U /**< Sampled Metric Counter + 10 Register */ +#define XAPM_SMC11_OFFSET 0x000002B0U /**< Sampled Metric Counter + 11 Register */ +#define XAPM_SMC12_OFFSET 0x00000600U /**< Sampled Metric Counter + 12 Register */ +#define XAPM_SMC13_OFFSET 0x00000610U /**< Sampled Metric Counter + 13 Register */ +#define XAPM_SMC14_OFFSET 0x00000620U /**< Sampled Metric Counter + 14 Register */ +#define XAPM_SMC15_OFFSET 0x00000630U /**< Sampled Metric Counter + 15 Register */ +#define XAPM_SMC16_OFFSET 0x00000640U /**< Sampled Metric Counter + 16 Register */ +#define XAPM_SMC17_OFFSET 0x00000650U /**< Sampled Metric Counter + 17 Register */ +#define XAPM_SMC18_OFFSET 0x00000660U /**< Sampled Metric Counter + 18 Register */ +#define XAPM_SMC19_OFFSET 0x00000670U /**< Sampled Metric Counter + 19 Register */ +#define XAPM_SMC20_OFFSET 0x00000680U /**< Sampled Metric Counter + 20 Register */ +#define XAPM_SMC21_OFFSET 0x00000690U /**< Sampled Metric Counter + 21 Register */ +#define XAPM_SMC22_OFFSET 0x000006A0U /**< Sampled Metric Counter + 22 Register */ +#define XAPM_SMC23_OFFSET 0x000006B0U /**< Sampled Metric Counter + 23 Register */ +#define XAPM_SMC24_OFFSET 0x00000800U /**< Sampled Metric Counter + 24 Register */ +#define XAPM_SMC25_OFFSET 0x00000810U /**< Sampled Metric Counter + 25 Register */ +#define XAPM_SMC26_OFFSET 0x00000820U /**< Sampled Metric Counter + 26 Register */ +#define XAPM_SMC27_OFFSET 0x00000830U /**< Sampled Metric Counter + 27 Register */ +#define XAPM_SMC28_OFFSET 0x00000840U /**< Sampled Metric Counter + 28 Register */ +#define XAPM_SMC29_OFFSET 0x00000850U /**< Sampled Metric Counter + 29 Register */ +#define XAPM_SMC30_OFFSET 0x00000860U /**< Sampled Metric Counter + 30 Register */ +#define XAPM_SMC31_OFFSET 0x00000870U /**< Sampled Metric Counter + 31 Register */ +#define XAPM_SMC32_OFFSET 0x00000880U /**< Sampled Metric Counter + 32 Register */ +#define XAPM_SMC33_OFFSET 0x00000890U /**< Sampled Metric Counter + 33 Register */ +#define XAPM_SMC34_OFFSET 0x000008A0U /**< Sampled Metric Counter + 34 Register */ +#define XAPM_SMC35_OFFSET 0x000008B0U /**< Sampled Metric Counter + 35 Register */ +#define XAPM_SMC36_OFFSET 0x00000A00U /**< Sampled Metric Counter + 36 Register */ +#define XAPM_SMC37_OFFSET 0x00000A10U /**< Sampled Metric Counter + 37 Register */ +#define XAPM_SMC38_OFFSET 0x00000A20U /**< Sampled Metric Counter + 38 Register */ +#define XAPM_SMC39_OFFSET 0x00000A30U /**< Sampled Metric Counter + 39 Register */ +#define XAPM_SMC40_OFFSET 0x00000A40U /**< Sampled Metric Counter + 40 Register */ +#define XAPM_SMC41_OFFSET 0x00000A50U /**< Sampled Metric Counter + 41 Register */ +#define XAPM_SMC42_OFFSET 0x00000A60U /**< Sampled Metric Counter + 42 Register */ +#define XAPM_SMC43_OFFSET 0x00000A70U /**< Sampled Metric Counter + 43 Register */ +#define XAPM_SMC44_OFFSET 0x00000A80U /**< Sampled Metric Counter + 44 Register */ +#define XAPM_SMC45_OFFSET 0x00000A90U /**< Sampled Metric Counter + 45 Register */ +#define XAPM_SMC46_OFFSET 0x00000AA0U /**< Sampled Metric Counter + 46 Register */ +#define XAPM_SMC47_OFFSET 0x00000AB0U /**< Sampled Metric Counter + 47 Register */ + +#define XAPM_CTL_OFFSET 0x00000300U /**< Control Register */ + +#define XAPM_ID_OFFSET 0x00000304U /**< Latency ID Register */ + +#define XAPM_IDMASK_OFFSET 0x00000308U /**< ID Mask Register */ + +#define XAPM_RID_OFFSET 0x0000030CU /**< Latency Write ID Register */ + +#define XAPM_RIDMASK_OFFSET 0x00000310U /**< Read ID Mask Register */ + +#define XAPM_FEC_OFFSET 0x00000400U /**< Flag Enable + Control Register */ + +#define XAPM_SWD_OFFSET 0x00000404U /**< Software-written + Data Register */ + +/* @} */ + +/** + * @name AXI Monitor Sample Interval Control Register mask(s) + * @{ + */ + +#define XAPM_SICR_MCNTR_RST_MASK 0x00000100U /**< Enable the Metric + Counter Reset */ +#define XAPM_SICR_LOAD_MASK 0x00000002U /**< Load the Sample Interval + * Register Value into the + * counter */ +#define XAPM_SICR_ENABLE_MASK 0x00000001U /**< Enable the downcounter */ + +/*@}*/ + + +/** @name Interrupt Status/Enable Register Bit Definitions and Masks + * @{ + */ + +#define XAPM_IXR_MC9_OVERFLOW_MASK 0x00001000U /**< Metric Counter 9 + * Overflow> */ +#define XAPM_IXR_MC8_OVERFLOW_MASK 0x00000800U /**< Metric Counter 8 + * Overflow> */ +#define XAPM_IXR_MC7_OVERFLOW_MASK 0x00000400U /**< Metric Counter 7 + * Overflow> */ +#define XAPM_IXR_MC6_OVERFLOW_MASK 0x00000200U /**< Metric Counter 6 + * Overflow> */ +#define XAPM_IXR_MC5_OVERFLOW_MASK 0x00000100U /**< Metric Counter 5 + * Overflow> */ +#define XAPM_IXR_MC4_OVERFLOW_MASK 0x00000080U /**< Metric Counter 4 + * Overflow> */ +#define XAPM_IXR_MC3_OVERFLOW_MASK 0x00000040U /**< Metric Counter 3 + * Overflow> */ +#define XAPM_IXR_MC2_OVERFLOW_MASK 0x00000020U /**< Metric Counter 2 + * Overflow> */ +#define XAPM_IXR_MC1_OVERFLOW_MASK 0x00000010U /**< Metric Counter 1 + * Overflow> */ +#define XAPM_IXR_MC0_OVERFLOW_MASK 0x00000008U /**< Metric Counter 0 + * Overflow> */ +#define XAPM_IXR_FIFO_FULL_MASK 0x00000004U /**< Event Log FIFO + * full> */ +#define XAPM_IXR_SIC_OVERFLOW_MASK 0x00000002U /**< Sample Interval + * Counter Overflow> */ +#define XAPM_IXR_GCC_OVERFLOW_MASK 0x00000001U /**< Global Clock Counter + * Overflow> */ +#define XAPM_IXR_ALL_MASK (XAPM_IXR_SIC_OVERFLOW_MASK | \ + XAPM_IXR_GCC_OVERFLOW_MASK | \ + XAPM_IXR_FIFO_FULL_MASK | \ + XAPM_IXR_MC0_OVERFLOW_MASK | \ + XAPM_IXR_MC1_OVERFLOW_MASK | \ + XAPM_IXR_MC2_OVERFLOW_MASK | \ + XAPM_IXR_MC3_OVERFLOW_MASK | \ + XAPM_IXR_MC4_OVERFLOW_MASK | \ + XAPM_IXR_MC5_OVERFLOW_MASK | \ + XAPM_IXR_MC6_OVERFLOW_MASK | \ + XAPM_IXR_MC7_OVERFLOW_MASK | \ + XAPM_IXR_MC8_OVERFLOW_MASK | \ + XAPM_IXR_MC9_OVERFLOW_MASK) +/* @} */ + +/** + * @name AXI Monitor Control Register mask(s) + * @{ + */ + +#define XAPM_CR_FIFO_RESET_MASK 0x02000000U + /**< FIFO Reset */ +#define XAPM_CR_GCC_RESET_MASK 0x00020000U + /**< Global Clk + Counter Reset */ +#define XAPM_CR_GCC_ENABLE_MASK 0x00010000U + /**< Global Clk + Counter Enable */ +#define XAPM_CR_EVTLOG_EXTTRIGGER_MASK 0x00000200U + /**< Enable External trigger + to start event Log */ +#define XAPM_CR_EVENTLOG_ENABLE_MASK 0x00000100U + /**< Event Log Enable */ + +#define XAPM_CR_RDLATENCY_END_MASK 0x00000080U + /**< Write Latency + End point */ +#define XAPM_CR_RDLATENCY_START_MASK 0x00000040U + /**< Read Latency + Start point */ +#define XAPM_CR_WRLATENCY_END_MASK 0x00000020U + /**< Write Latency + End point */ +#define XAPM_CR_WRLATENCY_START_MASK 0x00000010U + /**< Write Latency + Start point */ +#define XAPM_CR_IDFILTER_ENABLE_MASK 0x00000008U + /**< ID Filter Enable */ + +#define XAPM_CR_MCNTR_EXTTRIGGER_MASK 0x00000004U + /**< Enable External + trigger to start + Metric Counters */ +#define XAPM_CR_MCNTR_RESET_MASK 0x00000002U + /**< Metrics Counter + Reset */ +#define XAPM_CR_MCNTR_ENABLE_MASK 0x00000001U + /**< Metrics Counter + Enable */ +/*@}*/ + +/** + * @name AXI Monitor ID Register mask(s) + * @{ + */ + +#define XAPM_ID_RID_MASK 0xFFFF0000U /**< Read ID */ + +#define XAPM_ID_WID_MASK 0x0000FFFFU /**< Write ID */ + +/*@}*/ + +/** + * @name AXI Monitor ID Mask Register mask(s) + * @{ + */ + +#define XAPM_MASKID_RID_MASK 0xFFFF0000U /**< Read ID Mask */ + +#define XAPM_MASKID_WID_MASK 0x0000FFFFU /**< Write ID Mask*/ + +/*@}*/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* +* Read a register of the AXI Performance Monitor device. This macro provides +* register access to all registers using the register offsets defined above. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset is the offset of the register to read. +* +* @return The contents of the register. +* +* @note C-style Signature: +* u32 XAxiPmon_ReadReg(u32 BaseAddress, u32 RegOffset); +* +******************************************************************************/ +#define XAxiPmon_ReadReg(BaseAddress, RegOffset) \ + (Xil_In32((BaseAddress) + (RegOffset))) + +/*****************************************************************************/ +/** +* +* Write a register of the AXI Performance Monitor device. This macro provides +* register access to all registers using the register offsets defined above. +* +* @param BaseAddress contains the base address of the device. +* @param RegOffset is the offset of the register to write. +* @param Data is the value to write to the register. +* +* @return None. +* +* @note C-style Signature: +* void XAxiPmon_WriteReg(u32 BaseAddress, +* u32 RegOffset,u32 Data) +* +******************************************************************************/ +#define XAxiPmon_WriteReg(BaseAddress, RegOffset, Data) \ + (Xil_Out32((BaseAddress) + (RegOffset), (Data))) + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* End of protection macro. */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_selftest.c new file mode 100644 index 000000000..df2a9da66 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_selftest.c @@ -0,0 +1,152 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xaxipmon_selftest.c +* @addtogroup axipmon_v6_3 +* @{ +* +* This file contains a diagnostic self test function for the XAxiPmon driver. +* The self test function does a simple read/write test of the Alarm Threshold +* Register. +* +* See XAxiPmon.h for more information. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss  02/24/12 First release
+* 2.00a bss  06/23/12 Updated to support v2_00a version of IP.
+* 6.3   kvn  07/02/15 Modified code according to MISRA-C:2012 guidelines.
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xaxipmon.h" + +/************************** Constant Definitions ****************************/ + +/* + * The following constant defines the test value to be written + * to the Range Registers of Incrementers + */ + +#define XAPM_TEST_RANGEUPPER_VALUE 16U /**< Test Value for Upper Range */ +#define XAPM_TEST_RANGELOWER_VALUE 8U /**< Test Value for Lower Range */ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/************************** Function Prototypes *****************************/ + +/*****************************************************************************/ +/** +* +* Run a self-test on the driver/device. The test +* - Resets the device, +* - Writes a value into the Range Registers of Incrementer 0 and reads +* it back for comparison. +* - Resets the device again. +* +* +* @param InstancePtr is a pointer to the XAxiPmon instance. +* +* @return +* - XST_SUCCESS if the value read from the Range Register of +* Incrementer 0 is the same as the value written. +* - XST_FAILURE Otherwise +* +* @note This is a destructive test in that resets of the device are +* performed. Refer to the device specification for the +* device status after the reset operation. +* +******************************************************************************/ +s32 XAxiPmon_SelfTest(XAxiPmon *InstancePtr) +{ + s32 Status; + u16 RangeUpper = 0U; + u16 RangeLower = 0U; + + /* + * Assert the argument + */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + /* + * Reset the device to get it back to its default state + */ + (void)XAxiPmon_ResetMetricCounter(InstancePtr); + XAxiPmon_ResetGlobalClkCounter(InstancePtr); + + /* + * Write a value into the Incrementer register and + * read it back, and do the comparison + */ + XAxiPmon_SetIncrementerRange(InstancePtr, XAPM_INCREMENTER_0, + XAPM_TEST_RANGEUPPER_VALUE, + XAPM_TEST_RANGELOWER_VALUE); + + XAxiPmon_GetIncrementerRange(InstancePtr, XAPM_INCREMENTER_0, + &RangeUpper, &RangeLower); + + if ((RangeUpper == XAPM_TEST_RANGEUPPER_VALUE) && + (RangeLower == XAPM_TEST_RANGELOWER_VALUE)) { + Status = XST_SUCCESS; + } else { + Status = XST_FAILURE; + } + + /* + * Reset the device again to its default state. + */ + (void)XAxiPmon_ResetMetricCounter(InstancePtr); + XAxiPmon_ResetGlobalClkCounter(InstancePtr); + + /* + * Return the test result. + */ + return Status; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_sinit.c new file mode 100644 index 000000000..737d80b48 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/axipmon_v6_4/src/xaxipmon_sinit.c @@ -0,0 +1,104 @@ +/****************************************************************************** +* +* Copyright (C) 2012 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xaxipmon_sinit.c +* @addtogroup axipmon_v6_3 +* @{ +* +* This file contains the implementation of the XAxiPmon driver's static +* initialization functionality. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.00a bss  02/27/12 First release
+* 2.00a bss  06/23/12 Updated to support v2_00a version of IP.
+* 6.3   kvn  07/02/15 Modified code according to MISRA-C:2012 guidelines.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xaxipmon.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ +extern XAxiPmon_Config XAxiPmon_ConfigTable[]; + +/*****************************************************************************/ +/** +* +* This function looks up the device configuration based on the unique device ID. +* The table XAxiPmon_ConfigTable contains the configuration info for each device +* in the system. +* +* @param DeviceId contains the ID of the device for which the +* device configuration pointer is to be returned. +* +* @return +* - A pointer to the configuration found. +* - NULL if the specified device ID was not found. +* +* @note None. +* +******************************************************************************/ +XAxiPmon_Config *XAxiPmon_LookupConfig(u16 DeviceId) +{ + XAxiPmon_Config *CfgPtr = NULL; + u32 Index; + + for (Index=0U; Index < (u32)XPAR_XAXIPMON_NUM_INSTANCES; Index++) { + if (XAxiPmon_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XAxiPmon_ConfigTable[Index]; + break; + } + } + + return (XAxiPmon_Config *)CfgPtr; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/Makefile new file mode 100644 index 000000000..55565709b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xcanps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling canps" + +xcanps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xcanps_includes + +xcanps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.c new file mode 100644 index 000000000..243b3a81b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.c @@ -0,0 +1,1205 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps.c +* @addtogroup canps_v3_0 +* @{ +* +* Functions in this file are the minimum required functions for the XCanPs +* driver. See xcanps.h for a detailed description of the driver. +* +* @note None. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +static void StubHandler(void); + +/*****************************************************************************/ +/* +* +* This function initializes a XCanPs instance/driver. +* +* The initialization entails: +* - Initialize all members of the XCanPs structure. +* - Reset the CAN device. The CAN device will enter Configuration Mode +* immediately after the reset is finished. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param ConfigPtr points to the XCanPs device configuration structure. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. If the address translation is not used then the +* physical address is passed. +* Unexpected errors may occur if the address mapping is changed +* after this function is invoked. +* +* @return XST_SUCCESS always. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr, + u32 EffectiveAddr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(ConfigPtr != NULL); + + /* + * Set some default values for instance data, don't indicate the device + * is ready to use until everything has been initialized successfully. + */ + InstancePtr->IsReady = 0U; + InstancePtr->CanConfig.BaseAddr = EffectiveAddr; + InstancePtr->CanConfig.DeviceId = ConfigPtr->DeviceId; + + /* + * Set all handlers to stub values, let user configure this data later. + */ + InstancePtr->SendHandler = (XCanPs_SendRecvHandler) StubHandler; + InstancePtr->RecvHandler = (XCanPs_SendRecvHandler) StubHandler; + InstancePtr->ErrorHandler = (XCanPs_ErrorHandler) StubHandler; + InstancePtr->EventHandler = (XCanPs_EventHandler) StubHandler; + + /* + * Indicate the component is now ready to use. + */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + + /* + * Reset the device to get it into its initial state. + */ + XCanPs_Reset(InstancePtr); + + Status = XST_SUCCESS; + return Status; +} + +/*****************************************************************************/ +/** +* +* This function resets the CAN device. Calling this function resets the device +* immediately, and any pending transmission or reception is terminated at once. +* Both Object Layer and Transfer Layer are reset. This function does not reset +* the Physical Layer. All registers are reset to the default values, and no +* previous status will be restored. TX FIFO, RX FIFO and TX High Priority +* Buffer are also reset. +* +* When a reset is required due to an internal error, the driver notifies the +* upper layer software of this need through the error status code or interrupts. +* The upper layer software is responsible for calling this Reset function and +* then re-configuring the device. +* +* The CAN device will be in Configuration Mode immediately after this function +* returns. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_Reset(XCanPs *InstancePtr) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_SRR_OFFSET, \ + XCANPS_SRR_SRST_MASK); +} + +/****************************************************************************/ +/** +* +* This routine returns the current operation mode of the CAN device. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - XCANPS_MODE_CONFIG if the device is in Configuration Mode. +* - XCANPS_MODE_SLEEP if the device is in Sleep Mode. +* - XCANPS_MODE_NORMAL if the device is in Normal Mode. +* - XCANPS_MODE_LOOPBACK if the device is in Loop Back Mode. +* - XCANPS_MODE_SNOOP if the device is in Snoop Mode. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetMode(XCanPs *InstancePtr) +{ + u32 StatusReg; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + StatusReg = XCanPs_GetStatus(InstancePtr); + + if ((StatusReg & XCANPS_SR_CONFIG_MASK) != (u32)0) { + return (u8)XCANPS_MODE_CONFIG; + + } + else if ((StatusReg & XCANPS_SR_SLEEP_MASK) != (u32)0) { + return (u8)XCANPS_MODE_SLEEP; + + } + else if ((StatusReg & XCANPS_SR_NORMAL_MASK) != (u32)0) { + if ((StatusReg & XCANPS_SR_SNOOP_MASK) != (u32)0) { + return (u8)XCANPS_MODE_SNOOP; + } else { + return (u8)XCANPS_MODE_NORMAL; + } + } + else { + /* + * If this line is reached, the device is in Loop Back Mode. + */ + return (u8)XCANPS_MODE_LOOPBACK; + } +} + +/*****************************************************************************/ +/** +* +* This function allows the CAN device to enter one of the following operation +* modes: +* - Configuration Mode: Pass in parameter XCANPS_MODE_CONFIG +* - Sleep Mode: Pass in parameter XCANPS_MODE_SLEEP +* - Normal Mode: Pass in parameter XCANPS_MODE_NORMAL +* - Loop Back Mode: Pass in parameter XCANPS_MODE_LOOPBACK. +* - Snoop Mode: Pass in parameter XCANPS_MODE_SNOOP. +* +* Read the xcanps.h file and device specification for detailed description of +* each operation mode. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param OperationMode specify which operation mode to enter. Valid value +* is any of XCANPS_MODE_* defined in xcanps.h. Multiple modes +* can not be entered at the same time. +* +* @return None. +* +* @note +* +* This function does NOT ensure CAN device enters the specified operation mode +* before it returns the control to the caller. The caller is responsible for +* checking current operation mode using XCanPs_GetMode(). +* +******************************************************************************/ +void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode) +{ + u8 CurrentMode; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((OperationMode == (u8)XCANPS_MODE_CONFIG) || + (OperationMode == (u8)XCANPS_MODE_SLEEP) || + (OperationMode == (u8)XCANPS_MODE_NORMAL) || + (OperationMode == (u8)XCANPS_MODE_LOOPBACK) || + (OperationMode == (u8)XCANPS_MODE_SNOOP)); + + CurrentMode = XCanPs_GetMode(InstancePtr); + + /* + * If current mode is Normal Mode and the mode to enter is Sleep Mode, + * or if current mode is Sleep Mode and the mode to enter is Normal + * Mode, no transition through Configuration Mode is needed. + */ + if ((CurrentMode == (u8)XCANPS_MODE_NORMAL) && + (OperationMode == (u8)XCANPS_MODE_SLEEP)) { + /* + * Normal Mode ---> Sleep Mode + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK); + return; + + } else if ((CurrentMode == (u8)XCANPS_MODE_SLEEP) && + (OperationMode == (u8)XCANPS_MODE_NORMAL)) { + /* + * Sleep Mode ---> Normal Mode + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, 0U); + return; + } + else { + /*This else was made for misra-c compliance*/ + ; + } + + /* + * If the mode transition is not any of the two cases above, CAN must + * enter Configuration Mode before switching into the target operation + * mode. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, 0U); + + /* + * Check if the device has entered Configuration Mode, if not, return to + * the caller. + */ + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + return; + } + + switch (OperationMode) { + case XCANPS_MODE_CONFIG: + /* + * As CAN is in Configuration Mode already. + * Nothing is needed to be done here. + */ + break; + + case XCANPS_MODE_SLEEP: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SLEEP_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_NORMAL: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, 0U); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_LOOPBACK: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_LBACK_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + case XCANPS_MODE_SNOOP: + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_MSR_OFFSET, XCANPS_MSR_SNOOP_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SRR_OFFSET, XCANPS_SRR_CEN_MASK); + break; + + default: + /*This default was made for misra-c compliance*/ + break; + + } +} + +/*****************************************************************************/ +/** +* +* This function returns Status value from Status Register (SR). Use the +* XCANPS_SR_* constants defined in xcanps_hw.h to interpret the returned +* value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The 32-bit value read from Status Register. +* +* @note None. +* +******************************************************************************/ +u32 XCanPs_GetStatus(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_SR_OFFSET); +} + +/*****************************************************************************/ +/** +* +* This function reads Receive and Transmit error counters. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param RxErrorCount is a pointer to data in which the Receive Error +* counter value is returned. +* @param TxErrorCount is a pointer to data in which the Transmit Error +* counter value is returned. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount, + u8 *TxErrorCount) +{ + u32 ErrorCount; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(RxErrorCount != NULL); + Xil_AssertVoid(TxErrorCount != NULL); + /* + * Read Error Counter Register and parse it. + */ + ErrorCount = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ECR_OFFSET); + *RxErrorCount = (u8)((ErrorCount & XCANPS_ECR_REC_MASK) >> + XCANPS_ECR_REC_SHIFT); + *TxErrorCount = (u8)(ErrorCount & XCANPS_ECR_TEC_MASK); +} + +/*****************************************************************************/ +/** +* +* This function reads Error Status value from Error Status Register (ESR). Use +* the XCANPS_ESR_* constants defined in xcanps_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The 32-bit value read from Error Status Register. +* +* @note None. +* +******************************************************************************/ +u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ESR_OFFSET); +} + +/*****************************************************************************/ +/** +* +* This function clears Error Status bit(s) previously set in Error +* Status Register (ESR). Use the XCANPS_ESR_* constants defined in xcanps_hw.h +* to create the value to pass in. If a bit was cleared in Error Status Register +* before this function is called, it will not be modified. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @param Mask is he 32-bit mask used to clear bits in Error Status +* Register. Multiple XCANPS_ESR_* values can be 'OR'ed to clear +* multiple bits. +* +* @note None. +* +******************************************************************************/ +void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ESR_OFFSET, Mask); +} + +/*****************************************************************************/ +/** +* +* This function sends a CAN Frame. If the TX FIFO is not full then the given +* frame is written into the the TX FIFO otherwise, it returns an error code +* immediately. +* This function does not wait for the given frame being sent to CAN bus. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer containing the +* CAN frame to be sent. +* +* @return +* - XST_SUCCESS if TX FIFO was not full and the given frame was +* written into the FIFO. +* - XST_FIFO_NO_ROOM if there is no room in the TX FIFO for the +* given frame. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsTxFifoFull(InstancePtr) == TRUE) { + Status = XST_FIFO_NO_ROOM; + } else { + + /* + * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_ID_OFFSET, FramePtr[0]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DLC_OFFSET, FramePtr[1]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DW1_OFFSET, Xil_EndianSwap32(FramePtr[2])); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXFIFO_DW2_OFFSET, Xil_EndianSwap32(FramePtr[3])); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This function receives a CAN Frame. This function first checks if RX FIFO is +* empty, if not, it then reads a frame from the RX FIFO into the given buffer. +* This function returns error code immediately if there is no frame in the RX +* FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer where the CAN +* frame to be written. +* +* @return +* - XST_SUCCESS if RX FIFO was not empty and a frame was read from +* RX FIFO successfully and written into the given buffer. +* - XST_NO_DATA if there is no frame to be received from the FIFO. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsRxEmpty(InstancePtr) == TRUE) { + Status = XST_NO_DATA; + } else { + + /* + * Read IDR, DLC, Data Word 1 and Data Word 2 from the CAN device. + */ + FramePtr[0] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_ID_OFFSET); + FramePtr[1] = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DLC_OFFSET); + FramePtr[2] = Xil_EndianSwap32(XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DW1_OFFSET)); + FramePtr[3] = Xil_EndianSwap32(XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_RXFIFO_DW2_OFFSET)); + + /* + * Clear RXNEMP bit in ISR. This allows future XCanPs_IsRxEmpty() call + * returns correct RX FIFO occupancy/empty condition. + */ + XCanPs_IntrClear(InstancePtr, XCANPS_IXR_RXNEMP_MASK); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine sends a CAN High Priority frame. This function first checks if +* TX High Priority Buffer is empty. If yes, it then writes the given frame into +* the Buffer. If not, this function returns immediately. This function does not +* wait for the given frame being sent to CAN bus. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FramePtr is a pointer to a 32-bit aligned buffer containing the +* CAN High Priority frame to be sent. +* +* @return +* - XST_SUCCESS if TX High Priority Buffer was not full and the +* given frame was written into the buffer. +* - XST_FIFO_NO_ROOM if there is no room in the TX High Priority +* Buffer for this frame. +* +* @note +* +* If the frame needs to be sent immediately and not delayed by processor's +* interrupt handling, the caller should disable interrupt at processor +* level before invoking this function. +* +******************************************************************************/ +s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(FramePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_IsHighPriorityBufFull(InstancePtr) == TRUE) { + Status = XST_FIFO_NO_ROOM; + } else { + + /* + * Write IDR, DLC, Data Word 1 and Data Word 2 to the CAN device. + */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_ID_OFFSET, FramePtr[0]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DLC_OFFSET, FramePtr[1]); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DW1_OFFSET, Xil_EndianSwap32(FramePtr[2])); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_TXHPB_DW2_OFFSET, Xil_EndianSwap32(FramePtr[3])); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine enables individual acceptance filters. Up to 4 filters could +* be enabled. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndexes specifies which filter(s) to enable. Use +* any XCANPS_AFR_UAF*_MASK to enable one filter, and "Or" +* multiple XCANPS_AFR_UAF*_MASK values if multiple filters need +* to be enabled. Any filter not specified in this parameter will +* keep its previous enable/disable setting. +* +* @return None. +* +* @note None. +* +* +******************************************************************************/ +void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes) +{ + u32 EnabledFilters; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Calculate the new value and write to AFR. + */ + EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + EnabledFilters |= FilterIndexes; + EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET, + EnabledFilters); +} + +/*****************************************************************************/ +/** +* +* This routine disables individual acceptance filters. Up to 4 filters could +* be disabled. If all acceptance filters are disabled then all the received +* frames are stored in the RX FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndexes specifies which filter(s) to disable. Use +* any XCANPS_AFR_UAF*_MASK to disable one filter, and "Or" +* multiple XCANPS_AFR_UAF*_MASK values if multiple filters need +* to be disabled. Any filter not specified in this parameter will +* keep its previous enable/disable setting. If all acceptance +* filters are disabled then all received frames are stored in the +* RX FIFO. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes) +{ + u32 EnabledFilters; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Calculate the new value and write to AFR. + */ + EnabledFilters = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + EnabledFilters &= (u32)XCANPS_AFR_UAF_ALL_MASK & (~FilterIndexes); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_AFR_OFFSET, + EnabledFilters); +} + +/*****************************************************************************/ +/** +* +* This function returns enabled acceptance filters. Use XCANPS_AFR_UAF*_MASK +* defined in xcanps_hw.h to interpret the returned value. If no acceptance +* filters are enabled then all received frames are stored in the RX FIFO. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The value stored in Acceptance Filter Register. +* +* @note None. +* +* +******************************************************************************/ +u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFR_OFFSET); + +} + +/*****************************************************************************/ +/** +* +* This function sets values to the Acceptance Filter Mask Register (AFMR) and +* Acceptance Filter ID Register (AFIR) for the specified Acceptance Filter. +* Use XCANPS_IDR_* defined in xcanps_hw.h to create the values to set the +* filter. Read the xcanps.h file and device specification for details. +* +* This function should be called only after: +* - The given filter is disabled by calling XCanPs_AcceptFilterDisable() +* - And the CAN device is ready to accept writes to AFMR and AFIR, i.e., +* XCanPs_IsAcceptFilterBusy() returns FALSE. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndex defines which Acceptance Filter Mask and ID Register +* to set. Use any single XCANPS_AFR_UAF*_MASK value. +* @param MaskValue is the value to write to the chosen Acceptance Filter +* Mask Register. +* @param IdValue is the value to write to the chosen Acceptance Filter +* ID Register. +* +* @return +* - XST_SUCCESS if the values were set successfully. +* - XST_FAILURE if the given filter was not disabled, or the CAN +* device was not ready to accept writes to AFMR and AFIR. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex, + u32 MaskValue, u32 IdValue) +{ + u32 EnabledFilters; + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid((FilterIndex == XCANPS_AFR_UAF4_MASK) || + (FilterIndex == XCANPS_AFR_UAF3_MASK) || + (FilterIndex == XCANPS_AFR_UAF2_MASK) || + (FilterIndex == XCANPS_AFR_UAF1_MASK)); + + /* + * Return an error if the given filter is currently enabled. + */ + EnabledFilters = XCanPs_AcceptFilterGetEnabled(InstancePtr); + if ((EnabledFilters & FilterIndex) == FilterIndex) { + Status = XST_FAILURE; + } else { + + /* + * If the CAN device is not ready to accept writes to AFMR and AFIR, + * return error code. + */ + if (XCanPs_IsAcceptFilterBusy(InstancePtr) == TRUE) { + Status = XST_FAILURE; + } else { + + /* + * Write to the AFMR and AFIR of the specified filter. + */ + switch (FilterIndex) { + case XCANPS_AFR_UAF1_MASK: /* Acceptance Filter No. 1 */ + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR1_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR1_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF2_MASK: /* Acceptance Filter No. 2 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR2_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR2_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF3_MASK: /* Acceptance Filter No. 3 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR3_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR3_OFFSET, IdValue); + break; + + case XCANPS_AFR_UAF4_MASK: /* Acceptance Filter No. 4 */ + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR4_OFFSET, MaskValue); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR4_OFFSET, IdValue); + break; + + default: + /*This default was made for misra-c compliance*/ + break; + } + + Status = XST_SUCCESS; + } + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This function reads the values of the Acceptance Filter Mask and ID Register +* for the specified Acceptance Filter. Use XCANPS_IDR_* defined in xcanps_hw.h +* to interpret the values. Read the xcanps.h file and device specification for +* details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param FilterIndex defines which Acceptance Filter Mask Register to get +* Mask and ID from. Use any single XCANPS_FILTER_* value. +* @param MaskValue is a pointer to the data in which the Mask value read +* from the chosen Acceptance Filter Mask Register is returned. +* @param IdValue is a pointer to the data in which the ID value read +* from the chosen Acceptance Filter ID Register is returned. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex, + u32 *MaskValue, u32 *IdValue) +{ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid((FilterIndex == XCANPS_AFR_UAF4_MASK) || + (FilterIndex == XCANPS_AFR_UAF3_MASK) || + (FilterIndex == XCANPS_AFR_UAF2_MASK) || + (FilterIndex == XCANPS_AFR_UAF1_MASK)); + Xil_AssertVoid(MaskValue != NULL); + Xil_AssertVoid(IdValue != NULL); + + /* + * Read from the AFMR and AFIR of the specified filter. + */ + switch (FilterIndex) { + case XCANPS_AFR_UAF1_MASK: /* Acceptance Filter No. 1 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR1_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR1_OFFSET); + break; + + case XCANPS_AFR_UAF2_MASK: /* Acceptance Filter No. 2 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR2_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR2_OFFSET); + break; + + case XCANPS_AFR_UAF3_MASK: /* Acceptance Filter No. 3 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR3_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR3_OFFSET); + break; + + case XCANPS_AFR_UAF4_MASK: /* Acceptance Filter No. 4 */ + *MaskValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFMR4_OFFSET); + *IdValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_AFIR4_OFFSET); + break; + + default: + /*This default was made for misra-c compliance*/ + break; + } +} + +/*****************************************************************************/ +/** +* +* This routine sets Baud Rate Prescaler value. The system clock for the CAN +* controller is divided by (Prescaler + 1) to generate the quantum clock +* needed for sampling and synchronization. Read the device specification +* for details. +* +* Baud Rate Prescaler can be set only if the CAN device is in Configuration +* Mode. Call XCanPs_EnterMode() to enter Configuration Mode before using this +* function. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Prescaler is the value to set. Valid values are from 0 to 255. +* +* @return +* - XST_SUCCESS if the Baud Rate Prescaler value is set +* successfully. +* - XST_FAILURE if CAN device is not in Configuration Mode. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_BRPR_OFFSET, + (u32)Prescaler); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine gets Baud Rate Prescaler value. The system clock for the CAN +* controller is divided by (Prescaler + 1) to generate the quantum clock +* needed for sampling and synchronization. Read the device specification for +* details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return Current used Baud Rate Prescaler value. The value's range is +* from 0 to 255. +* +* @note None. +* +******************************************************************************/ +u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr) +{ + u32 ReadValue; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + ReadValue = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BRPR_OFFSET); + return ((u8)ReadValue); +} + +/*****************************************************************************/ +/** +* +* This routine sets Bit time. Time segment 1, Time segment 2 and +* Synchronization Jump Width are set in this function. Device specification +* requires the values passed into this function be one less than the actual +* values of these fields. Read the device specification for details. +* +* Bit time can be set only if the CAN device is in Configuration Mode. +* Call XCanPs_EnterMode() to enter Configuration Mode before using this +* function. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param SyncJumpWidth is the Synchronization Jump Width value to set. +* Valid values are from 0 to 3. +* @param TimeSegment2 is the Time Segment 2 value to set. Valid values +* are from 0 to 7. +* @param TimeSegment1 is the Time Segment 1 value to set. Valid values +* are from 0 to 15. +* +* @return +* - XST_SUCCESS if the Bit time is set successfully. +* - XST_FAILURE if CAN device is not in Configuration Mode. +* +* @note None. +* +******************************************************************************/ +s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth, + u8 TimeSegment2, u8 TimeSegment1) +{ + u32 Value; + s32 Status; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(SyncJumpWidth <= (u8)3U); + Xil_AssertNonvoid(TimeSegment2 <= (u8)7U); + Xil_AssertNonvoid(TimeSegment1 <= (u8)15U ); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + Value = ((u32) TimeSegment1) & XCANPS_BTR_TS1_MASK; + Value |= (((u32) TimeSegment2) << XCANPS_BTR_TS2_SHIFT) & + XCANPS_BTR_TS2_MASK; + Value |= (((u32) SyncJumpWidth) << XCANPS_BTR_SJW_SHIFT) & + XCANPS_BTR_SJW_MASK; + + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BTR_OFFSET, Value); + + Status = XST_SUCCESS; + } + return Status; +} + +/*****************************************************************************/ +/** +* +* This routine gets Bit time. Time segment 1, Time segment 2 and +* Synchronization Jump Width values are read in this function. According to +* device specification, the actual value of each of these fields is one +* more than the value read. Read the device specification for details. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param SyncJumpWidth will store the Synchronization Jump Width value +* after this function returns. Its value ranges from 0 to 3. +* @param TimeSegment2 will store the Time Segment 2 value after this +* function returns. Its value ranges from 0 to 7. +* @param TimeSegment1 will store the Time Segment 1 value after this +* function returns. Its value ranges from 0 to 15. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth, + u8 *TimeSegment2, u8 *TimeSegment1) +{ + u32 Value; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertVoid(SyncJumpWidth != NULL); + Xil_AssertVoid(TimeSegment2 != NULL); + Xil_AssertVoid(TimeSegment1 != NULL); + + Value = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_BTR_OFFSET); + + *TimeSegment1 = (u8) (Value & XCANPS_BTR_TS1_MASK); + *TimeSegment2 = + (u8) ((Value & XCANPS_BTR_TS2_MASK) >> XCANPS_BTR_TS2_SHIFT); + *SyncJumpWidth = + (u8) ((Value & XCANPS_BTR_SJW_MASK) >> XCANPS_BTR_SJW_SHIFT); +} + + +/****************************************************************************/ +/** +* +* This routine sets the Rx Full threshold in the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Threshold is the threshold to be set. The valid values are +* from 1 to 63. +* +* @return +* - XST_FAILURE - If the CAN device is not in Configuration Mode. +* - XST_SUCCESS - If the Rx Full threshold is set in Watermark +* Interrupt Register. +* +* @note The threshold can only be set when the CAN device is in the +* configuration mode. +* +*****************************************************************************/ +s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold) +{ + + u32 ThrReg; + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Threshold <= (u8)63); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET); + + ThrReg &= XCANPS_WIR_EW_MASK; + ThrReg |= ((u32)Threshold & XCANPS_WIR_FW_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET, ThrReg); + + Status = XST_SUCCESS; + } + return Status; +} + +/****************************************************************************/ +/** +* +* This routine gets the Rx Full threshold from the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The Rx FIFO full watermark threshold value. The valid values +* are 1 to 63. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + return (u8) (XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET) & + XCANPS_WIR_FW_MASK); +} + + +/****************************************************************************/ +/** +* +* This routine sets the Tx Empty Threshold in the Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Threshold is the threshold to be set. The valid values are +* from 1 to 63. +* +* @return +* - XST_FAILURE - If the CAN device is not in Configuration Mode. +* - XST_SUCCESS - If the threshold is set in Watermark +* Interrupt Register. +* +* @note The threshold can only be set when the CAN device is in the +* configuration mode. +* +*****************************************************************************/ +s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold) +{ + u32 ThrReg; + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + Xil_AssertNonvoid(Threshold <= (u8)63); + + if (XCanPs_GetMode(InstancePtr) != (u8)XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + } else { + + ThrReg = XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET); + + ThrReg &= XCANPS_WIR_FW_MASK; + ThrReg |= (((u32)Threshold << XCANPS_WIR_EW_SHIFT) + & XCANPS_WIR_EW_MASK); + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET, ThrReg); + + Status = XST_SUCCESS; + } + return Status; +} + +/****************************************************************************/ +/** +* +* This routine gets the Tx Empty threshold from Watermark Interrupt Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The Tx Empty FIFO threshold value. The valid values are 1 to 63. +* +* @note None. +* +*****************************************************************************/ +u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + + return (u8) ((XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_WIR_OFFSET) & XCANPS_WIR_EW_MASK) >> + XCANPS_WIR_EW_SHIFT); +} + + + +/******************************************************************************/ +/* + * This routine is a stub for the asynchronous callbacks. The stub is here in + * case the upper layer forgot to set the handler(s). On initialization, all + * handlers are set to this callback. It is considered an error for this handler + * to be invoked. + * + ******************************************************************************/ +static void StubHandler(void) +{ + Xil_AssertVoidAlways(); +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.h new file mode 100644 index 000000000..b180e37ec --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps.h @@ -0,0 +1,575 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps.h +* @addtogroup canps_v3_0 +* @{ +* @details +* +* The Xilinx CAN driver component. This component supports the Xilinx +* CAN Controller. +* +* The CAN Controller supports the following features: +* - Confirms to the ISO 11898-1, CAN 2.0A and CAN 2.0B standards. +* - Supports both Standard (11 bit Identifier) and Extended (29 bit +* Identifier) frames. +* - Supports Bit Rates up to 1 Mbps. +* - Transmit message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Transmit prioritization through one TX High Priority Buffer. +* - Receive message object FIFO with a user configurable depth of +* up to 64 message objects. +* - Watermark interrupts for Rx FIFO with configurable Watermark. +* - Acceptance filtering with 4 acceptance filters. +* - Sleep mode with automatic wake up. +* - Loop Back mode for diagnostic applications. +* - Snoop mode for diagnostic applications. +* - Maskable Error and Status Interrupts. +* - Readable Error Counters. +* - External PHY chip required. +* - Receive Timestamp. +* +* The device driver supports all the features listed above, if applicable. +* +* Driver Description +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CAN. The driver handles transmission and reception of +* CAN frames, as well as configuration of the controller. The driver is simply a +* pass-through mechanism between a protocol stack and the CAN. A single device +* driver can support multiple CANs. +* +* Since the driver is a simple pass-through mechanism between a protocol stack +* and the CAN, no assembly or disassembly of CAN frames is done at the +* driver-level. This assumes that the protocol stack passes a correctly +* formatted CAN frame to the driver for transmission, and that the driver +* does not validate the contents of an incoming frame +* +* Operation Modes +* +* The CAN controller supports the following modes of operation: +* - Configuration Mode: In this mode the CAN timing parameters and +* Baud Rate Pre-scalar parameters can be changed. In this mode the CAN +* controller loses synchronization with the CAN bus and drives a +* constant recessive bit on the bus line. The Error Counter Register are +* reset. The CAN controller does not receive or transmit any messages +* even if there are pending transmit requests from the TX FIFO or the TX +* High Priority Buffer. The Storage FIFOs and the CAN configuration +* registers are still accessible. +* - Normal Mode:In Normal Mode the CAN controller participates in bus +* communication, by transmitting and receiving messages. +* - Sleep Mode: In Sleep Mode the CAN Controller does not transmit any +* messages. However, if any other node transmits a message, then the CAN +* Controller receives the transmitted message and exits from Sleep Mode. +* If there are new transmission requests from either the TX FIFO or the +* TX High Priority Buffer when the CAN Controller is in Sleep Mode, these +* requests are not serviced, and the CAN Controller continues to remain +* in Sleep Mode. Interrupts are generated when the CAN controller enters +* Sleep mode or Wakes up from Sleep mode. +* - Loop Back Mode: In Loop Back mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus. Any message that is transmitted +* is looped back to the �Rx� line and acknowledged. The CAN controller +* thus receives any message that it transmits. It does not participate in +* normal bus communication and does not receive any messages that are +* transmitted by other CAN nodes. This mode is used for diagnostic +* purposes. +* - Snoop Mode: In Snoop mode, the CAN controller transmits a +* recessive bit stream on to the CAN Bus and does not participate +* in normal bus communication but receives messages that are transmitted +* by other CAN nodes. This mode is used for diagnostic purposes. +* +* +* Buffer Alignment +* +* It is important to note that frame buffers passed to the driver must be +* 32-bit aligned. +* +* Receive Address Filtering +* +* The device can be set to accept frames whose Identifiers match any of the +* 4 filters set in the Acceptance Filter Mask/ID registers. +* +* The incoming Identifier is masked with the bits in the Acceptance Filter Mask +* Register. This value is compared with the result of masking the bits in the +* Acceptance Filter ID Register with the Acceptance Filter Mask Register. If +* both these values are equal, the message will be stored in the RX FIFO. +* +* Acceptance Filtering is performed by each of the defined acceptance filters. +* If the incoming identifier passes through any acceptance filter then the +* frame is stored in the RX FIFO. +* +* If the Accpetance Filters are not set up then all the received messages are +* stroed in the RX FIFO. +* +* PHY Communication +* +* This driver does not provide any mechanism for directly programming PHY. +* +* Interrupts +* +* The driver has no dependencies on the interrupt controller. The driver +* provides an interrupt handler. User of this driver needs to provide +* callback functions. An interrupt handler example is available with +* the driver. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Device Reset +* +* Bus Off interrupt that can occur in the device requires a device reset. +* The user is responsible for resetting the device and re-configuring it +* based on its needs (the driver does not save the current configuration). +* When integrating into an RTOS, these reset and re-configure obligations are +* taken care of by the OS adapter software if it exists for that RTOS. +* +* Device Configuration +* +* The device can be configured in various ways during the FPGA implementation +* process. Configuration parameters are stored in the xcanps_g.c files. +* A table is defined where each entry contains configuration information +* for a CAN device. This information includes such things as the base address +* of the memory-mapped device. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XCanPs driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +*

+* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a bss    12/27/11 Added the APIs XCanPs_SetTxIntrWatermark and
+* 			XCanPs_GetTxIntrWatermark.
+*			Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET to XCANPS_TXHPB_DW2_OFFSET
+* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+*			SDK claims a 40kbps baud rate but it's not.
+* 3.0 adk     09/12/14  Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+* 3.1 adk     10/11/15  Fixed CR#911958 Add support for Tx Watermark example.
+*			Data mismatch while sending data less than 8 bytes.
+* 3.1 nsk     12/21/15  Updated XCanPs_IntrHandler in xcanps_intr.c to handle
+*			error interrupts correctly. CR#925615
+*
+* +******************************************************************************/ +#ifndef XCANPS_H /* prevent circular inclusions */ +#define XCANPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xcanps_hw.h" +#include "xil_types.h" + +/************************** Constant Definitions *****************************/ + +/** @name CAN operation modes + * @{ + */ +#define XCANPS_MODE_CONFIG 0x00000001U /**< Configuration mode */ +#define XCANPS_MODE_NORMAL 0x00000002U /**< Normal mode */ +#define XCANPS_MODE_LOOPBACK 0x00000004U /**< Loop Back mode */ +#define XCANPS_MODE_SLEEP 0x00000008U /**< Sleep mode */ +#define XCANPS_MODE_SNOOP 0x00000010U /**< Snoop mode */ +/* @} */ + +/** @name Callback identifiers used as parameters to XCanPs_SetHandler() + * @{ + */ +#define XCANPS_HANDLER_SEND 1U /**< Handler type for frame sending interrupt */ +#define XCANPS_HANDLER_RECV 2U /**< Handler type for frame reception interrupt*/ +#define XCANPS_HANDLER_ERROR 3U /**< Handler type for error interrupt */ +#define XCANPS_HANDLER_EVENT 4U /**< Handler type for all other interrupts */ +/* @} */ + +/**************************** Type Definitions *******************************/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + u32 BaseAddr; /**< Register base address */ +} XCanPs_Config; + +/******************************************************************************/ +/** + * Callback type for frame sending and reception interrupts. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. +*******************************************************************************/ +typedef void (*XCanPs_SendRecvHandler) (void *CallBackRef); + +/******************************************************************************/ +/** + * Callback type for error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param ErrorMask is a bit mask indicating the cause of the error. Its + * value equals 'OR'ing one or more XCANPS_ESR_* values defined in + * xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_ErrorHandler) (void *CallBackRef, u32 ErrorMask); + +/******************************************************************************/ +/** + * Callback type for all kinds of interrupts except sending frame interrupt, + * receiving frame interrupt, and error interrupt. + * + * @param CallBackRef is a callback reference passed in by the upper layer + * when setting the callback functions, and passed back to the + * upper layer when the callback is invoked. + * @param Mask is a bit mask indicating the pending interrupts. Its value + * equals 'OR'ing one or more XCANPS_IXR_* defined in xcanps_hw.h +*******************************************************************************/ +typedef void (*XCanPs_EventHandler) (void *CallBackRef, u32 Mask); + +/** + * The XCanPs driver instance data. The user is required to allocate a + * variable of this type for every CAN device in the system. A pointer + * to a variable of this type is then passed to the driver API functions. + */ +typedef struct { + XCanPs_Config CanConfig; /**< Device configuration */ + u32 IsReady; /**< Device is initialized and ready */ + + /** + * Callback and callback reference for TXOK interrupt. + */ + XCanPs_SendRecvHandler SendHandler; + void *SendRef; + + /** + * Callback and callback reference for RXOK/RXNEMP/RXFLL interrupts. + */ + XCanPs_SendRecvHandler RecvHandler; + void *RecvRef; + + /** + * Callback and callback reference for ERROR interrupt. + */ + XCanPs_ErrorHandler ErrorHandler; + void *ErrorRef; + + /** + * Callback and callback reference for RXOFLW/RXUFLW/TXBFLL/TXFLL/ + * Wakeup/Sleep/Bus off/ARBLST interrupts. + */ + XCanPs_EventHandler EventHandler; + void *EventRef; + +} XCanPs; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro checks if the transmission is complete. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the transmission is done. +* - FALSE if the transmission is not done. +* +* @note C-Style signature: +* int XCanPs_IsTxDone(XCanPs *InstancePtr) +* +*******************************************************************************/ +#define XCanPs_IsTxDone(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_TXOK_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the transmission FIFO is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if TX FIFO is full. +* - FALSE if the TX FIFO is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsTxFifoFull(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsTxFifoFull(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXFLL_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the Transmission High Priority Buffer is full. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the TX High Priority Buffer is full. +* - FALSE if the TX High Priority Buffer is NOT full. +* +* @note C-Style signature: +* int XCanPs_IsHighPriorityBufFull(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsHighPriorityBufFull(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_TXBFLL_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro checks if the receive FIFO is empty. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if RX FIFO is empty. +* - FALSE if the RX FIFO is NOT empty. +* +* @note C-Style signature: +* int XCanPs_IsRxEmpty(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsRxEmpty(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK) != (u32)0) ? FALSE : TRUE) + + +/****************************************************************************/ +/** +* +* This macro checks if the CAN device is ready for the driver to change +* Acceptance Filter Identifier Registers (AFIR) and Acceptance Filter Mask +* Registers (AFMR). +* +* AFIR and AFMR for a filter are changeable only after the filter is disabled +* and this routine returns FALSE. The filter can be disabled using the +* XCanPs_AcceptFilterDisable function. +* +* Use the XCanPs_Accept_* functions for configuring the acceptance filters. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - TRUE if the device is busy and NOT ready to accept writes to +* AFIR and AFMR. +* - FALSE if the device is ready to accept writes to AFIR and +* AFMR. +* +* @note C-Style signature: +* int XCanPs_IsAcceptFilterBusy(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_IsAcceptFilterBusy(InstancePtr) \ + (((XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), \ + XCANPS_SR_OFFSET) & XCANPS_SR_ACFBSY_MASK) != (u32)0) ? TRUE : FALSE) + + +/****************************************************************************/ +/** +* +* This macro calculates CAN message identifier value given identifier field +* values. +* +* @param StandardId contains Standard Message ID value. +* @param SubRemoteTransReq contains Substitute Remote Transmission +* Request value. +* @param IdExtension contains Identifier Extension value. +* @param ExtendedId contains Extended Message ID value. +* @param RemoteTransReq contains Remote Transmission Request value. +* +* @return Message Identifier value. +* +* @note C-Style signature: +* u32 XCanPs_CreateIdValue(u32 StandardId, +* u32 SubRemoteTransReq, +* u32 IdExtension, u32 ExtendedId, +* u32 RemoteTransReq) +* +* Read the CAN specification for meaning of each parameter. +* +*****************************************************************************/ +#define XCanPs_CreateIdValue(StandardId, SubRemoteTransReq, IdExtension, \ + ExtendedId, RemoteTransReq) \ + ((((StandardId) << XCANPS_IDR_ID1_SHIFT) & XCANPS_IDR_ID1_MASK) | \ + (((SubRemoteTransReq) << XCANPS_IDR_SRR_SHIFT) & XCANPS_IDR_SRR_MASK)|\ + (((IdExtension) << XCANPS_IDR_IDE_SHIFT) & XCANPS_IDR_IDE_MASK) | \ + (((ExtendedId) << XCANPS_IDR_ID2_SHIFT) & XCANPS_IDR_ID2_MASK) | \ + ((RemoteTransReq) & XCANPS_IDR_RTR_MASK)) + + +/****************************************************************************/ +/** +* +* This macro calculates value for Data Length Code register given Data +* Length Code value. +* +* @param DataLengCode indicates Data Length Code value. +* +* @return Value that can be assigned to Data Length Code register. +* +* @note C-Style signature: +* u32 XCanPs_CreateDlcValue(u32 DataLengCode) +* +* Read the CAN specification for meaning of Data Length Code. +* +*****************************************************************************/ +#define XCanPs_CreateDlcValue(DataLengCode) \ + (((DataLengCode) << XCANPS_DLCR_DLC_SHIFT) & XCANPS_DLCR_DLC_MASK) + + +/****************************************************************************/ +/** +* +* This macro clears the timestamp in the Timestamp Control Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return None. +* +* @note C-Style signature: +* void XCanPs_ClearTimestamp(XCanPs *InstancePtr) +* +*****************************************************************************/ +#define XCanPs_ClearTimestamp(InstancePtr) \ + XCanPs_WriteReg((InstancePtr)->CanConfig.BaseAddr, \ + XCANPS_TCR_OFFSET, XCANPS_TCR_CTS_MASK) + +/************************** Function Prototypes ******************************/ + +/* + * Functions in xcanps.c + */ +s32 XCanPs_CfgInitialize(XCanPs *InstancePtr, XCanPs_Config *ConfigPtr, + u32 EffectiveAddr); + +void XCanPs_Reset(XCanPs *InstancePtr); +u8 XCanPs_GetMode(XCanPs *InstancePtr); +void XCanPs_EnterMode(XCanPs *InstancePtr, u8 OperationMode); +u32 XCanPs_GetStatus(XCanPs *InstancePtr); +void XCanPs_GetBusErrorCounter(XCanPs *InstancePtr, u8 *RxErrorCount, + u8 *TxErrorCount); +u32 XCanPs_GetBusErrorStatus(XCanPs *InstancePtr); +void XCanPs_ClearBusErrorStatus(XCanPs *InstancePtr, u32 Mask); +s32 XCanPs_Send(XCanPs *InstancePtr, u32 *FramePtr); +s32 XCanPs_Recv(XCanPs *InstancePtr, u32 *FramePtr); +s32 XCanPs_SendHighPriority(XCanPs *InstancePtr, u32 *FramePtr); +void XCanPs_AcceptFilterEnable(XCanPs *InstancePtr, u32 FilterIndexes); +void XCanPs_AcceptFilterDisable(XCanPs *InstancePtr, u32 FilterIndexes); +u32 XCanPs_AcceptFilterGetEnabled(XCanPs *InstancePtr); +s32 XCanPs_AcceptFilterSet(XCanPs *InstancePtr, u32 FilterIndex, + u32 MaskValue, u32 IdValue); +void XCanPs_AcceptFilterGet(XCanPs *InstancePtr, u32 FilterIndex, + u32 *MaskValue, u32 *IdValue); + +s32 XCanPs_SetBaudRatePrescaler(XCanPs *InstancePtr, u8 Prescaler); +u8 XCanPs_GetBaudRatePrescaler(XCanPs *InstancePtr); +s32 XCanPs_SetBitTiming(XCanPs *InstancePtr, u8 SyncJumpWidth, + u8 TimeSegment2, u8 TimeSegment1); +void XCanPs_GetBitTiming(XCanPs *InstancePtr, u8 *SyncJumpWidth, + u8 *TimeSegment2, u8 *TimeSegment1); + +s32 XCanPs_SetRxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetRxIntrWatermark(XCanPs *InstancePtr); +s32 XCanPs_SetTxIntrWatermark(XCanPs *InstancePtr, u8 Threshold); +u8 XCanPs_GetTxIntrWatermark(XCanPs *InstancePtr); + +/* + * Diagnostic functions in xcanps_selftest.c + */ +s32 XCanPs_SelfTest(XCanPs *InstancePtr); + +/* + * Functions in xcanps_intr.c + */ +void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask); +u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr); +u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr); +void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask); +void XCanPs_IntrHandler(void *InstancePtr); +s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef); + +/* + * Functions in xcanps_sinit.c + */ +XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_g.c new file mode 100644 index 000000000..b45c5b2d6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_g.c @@ -0,0 +1,55 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xcanps.h" + +/* +* The configuration table for devices +*/ + +XCanPs_Config XCanPs_ConfigTable[] = +{ + { + XPAR_PSU_CAN_1_DEVICE_ID, + XPAR_PSU_CAN_1_BASEADDR + } +}; + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.c new file mode 100644 index 000000000..bbb96120a --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.c @@ -0,0 +1,93 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_hw.c +* @addtogroup canps_v3_0 +* @{ +* +* This file contains the implementation of the canps interface reset sequence +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.02a adk  08/08/13 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps_hw.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +/*****************************************************************************/ +/** +* +* This function resets the CAN device. Calling this function resets the device +* immediately, and any pending transmission or reception is terminated at once. +* Both Object Layer and Transfer Layer are reset. This function does not reset +* the Physical Layer. All registers are reset to the default values, and no +* previous status will be restored. TX FIFO, RX FIFO and TX High Priority +* Buffer are also reset. +* +* The CAN device will be in Configuration Mode immediately after this function +* returns. +* +* @param BaseAddr is the baseaddress of the interface. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_ResetHw(u32 BaseAddr) +{ + XCanPs_WriteReg(BaseAddr, XCANPS_SRR_OFFSET, \ + XCANPS_SRR_SRST_MASK); +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.h new file mode 100644 index 000000000..9fe681aaf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_hw.h @@ -0,0 +1,369 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_hw.h +* @addtogroup canps_v3_0 +* @{ +* +* This header file contains the identifiers and basic driver functions (or +* macros) that can be used to access the device. Other driver functions +* are defined in xcanps.h. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 1.01a sbs    12/27/11 Updated the Register/bit definitions
+*                       Changed XCANPS_RXFWIR_RXFLL_MASK to XCANPS_WIR_FW_MASK
+*                       Changed XCANPS_RXWIR_OFFSET to XCANPS_WIR_OFFSET
+*			Added XCANPS_IXR_TXFEMP_MASK for Tx Fifo Empty
+*			Changed XCANPS_IXR_RXFLL_MASK to
+*			XCANPS_IXR_RXFWMFLL_MASK
+* 			Changed
+*			XCANPS_TXBUF_ID_OFFSET to XCANPS_TXHPB_ID_OFFSET
+* 			XCANPS_TXBUF_DLC_OFFSET to XCANPS_TXHPB_DLC_OFFSET
+*			XCANPS_TXBUF_DW1_OFFSET  to XCANPS_TXHPB_DW1_OFFSET
+*			XCANPS_TXBUF_DW2_OFFSET  to XCANPS_TXHPB_DW2_OFFSET
+* 1.02a adk   08/08/13  Updated for inclding the function prototype
+* 3.00  kvn   02/13/15  Modified code for MISRA-C:2012 compliance.
+*
+* +******************************************************************************/ + +#ifndef XCANPS_HW_H /* prevent circular inclusions */ +#define XCANPS_HW_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + + +/***************************** Include Files *********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Register offsets for the CAN. Each register is 32 bits. + * @{ + */ +#define XCANPS_SRR_OFFSET 0x00000000U /**< Software Reset Register */ +#define XCANPS_MSR_OFFSET 0x00000004U /**< Mode Select Register */ +#define XCANPS_BRPR_OFFSET 0x00000008U /**< Baud Rate Prescaler */ +#define XCANPS_BTR_OFFSET 0x0000000CU /**< Bit Timing Register */ +#define XCANPS_ECR_OFFSET 0x00000010U /**< Error Counter Register */ +#define XCANPS_ESR_OFFSET 0x00000014U /**< Error Status Register */ +#define XCANPS_SR_OFFSET 0x00000018U /**< Status Register */ + +#define XCANPS_ISR_OFFSET 0x0000001CU /**< Interrupt Status Register */ +#define XCANPS_IER_OFFSET 0x00000020U /**< Interrupt Enable Register */ +#define XCANPS_ICR_OFFSET 0x00000024U /**< Interrupt Clear Register */ +#define XCANPS_TCR_OFFSET 0x00000028U /**< Timestamp Control Register */ +#define XCANPS_WIR_OFFSET 0x0000002CU /**< Watermark Interrupt Reg */ + +#define XCANPS_TXFIFO_ID_OFFSET 0x00000030U /**< TX FIFO ID */ +#define XCANPS_TXFIFO_DLC_OFFSET 0x00000034U /**< TX FIFO DLC */ +#define XCANPS_TXFIFO_DW1_OFFSET 0x00000038U /**< TX FIFO Data Word 1 */ +#define XCANPS_TXFIFO_DW2_OFFSET 0x0000003CU /**< TX FIFO Data Word 2 */ + +#define XCANPS_TXHPB_ID_OFFSET 0x00000040U /**< TX High Priority Buffer ID */ +#define XCANPS_TXHPB_DLC_OFFSET 0x00000044U /**< TX High Priority Buffer DLC */ +#define XCANPS_TXHPB_DW1_OFFSET 0x00000048U /**< TX High Priority Buf Data 1 */ +#define XCANPS_TXHPB_DW2_OFFSET 0x0000004CU /**< TX High Priority Buf Data Word 2 */ + +#define XCANPS_RXFIFO_ID_OFFSET 0x00000050U /**< RX FIFO ID */ +#define XCANPS_RXFIFO_DLC_OFFSET 0x00000054U /**< RX FIFO DLC */ +#define XCANPS_RXFIFO_DW1_OFFSET 0x00000058U /**< RX FIFO Data Word 1 */ +#define XCANPS_RXFIFO_DW2_OFFSET 0x0000005CU /**< RX FIFO Data Word 2 */ + +#define XCANPS_AFR_OFFSET 0x00000060U /**< Acceptance Filter Register */ +#define XCANPS_AFMR1_OFFSET 0x00000064U /**< Acceptance Filter Mask 1 */ +#define XCANPS_AFIR1_OFFSET 0x00000068U /**< Acceptance Filter ID 1 */ +#define XCANPS_AFMR2_OFFSET 0x0000006CU /**< Acceptance Filter Mask 2 */ +#define XCANPS_AFIR2_OFFSET 0x00000070U /**< Acceptance Filter ID 2 */ +#define XCANPS_AFMR3_OFFSET 0x00000074U /**< Acceptance Filter Mask 3 */ +#define XCANPS_AFIR3_OFFSET 0x00000078U /**< Acceptance Filter ID 3 */ +#define XCANPS_AFMR4_OFFSET 0x0000007CU /**< Acceptance Filter Mask 4 */ +#define XCANPS_AFIR4_OFFSET 0x00000080U /**< Acceptance Filter ID 4 */ +/* @} */ + +/** @name Software Reset Register (SRR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SRR_CEN_MASK 0x00000002U /**< Can Enable */ +#define XCANPS_SRR_SRST_MASK 0x00000001U /**< Reset */ +/* @} */ + +/** @name Mode Select Register (MSR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_MSR_SNOOP_MASK 0x00000004U /**< Snoop Mode Select */ +#define XCANPS_MSR_LBACK_MASK 0x00000002U /**< Loop Back Mode Select */ +#define XCANPS_MSR_SLEEP_MASK 0x00000001U /**< Sleep Mode Select */ +/* @} */ + +/** @name Baud Rate Prescaler register (BRPR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BRPR_BRP_MASK 0x000000FFU /**< Baud Rate Prescaler */ +/* @} */ + +/** @name Bit Timing Register (BTR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_BTR_SJW_MASK 0x00000180U /**< Synchronization Jump Width */ +#define XCANPS_BTR_SJW_SHIFT 7U +#define XCANPS_BTR_TS2_MASK 0x00000070U /**< Time Segment 2 */ +#define XCANPS_BTR_TS2_SHIFT 4U +#define XCANPS_BTR_TS1_MASK 0x0000000FU /**< Time Segment 1 */ +/* @} */ + +/** @name Error Counter Register (ECR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ECR_REC_MASK 0x0000FF00U /**< Receive Error Counter */ +#define XCANPS_ECR_REC_SHIFT 8U +#define XCANPS_ECR_TEC_MASK 0x000000FFU /**< Transmit Error Counter */ +/* @} */ + +/** @name Error Status Register (ESR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_ESR_ACKER_MASK 0x00000010U /**< ACK Error */ +#define XCANPS_ESR_BERR_MASK 0x00000008U /**< Bit Error */ +#define XCANPS_ESR_STER_MASK 0x00000004U /**< Stuff Error */ +#define XCANPS_ESR_FMER_MASK 0x00000002U /**< Form Error */ +#define XCANPS_ESR_CRCER_MASK 0x00000001U /**< CRC Error */ +/* @} */ + +/** @name Status Register (SR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_SR_SNOOP_MASK 0x00001000U /**< Snoop Mask */ +#define XCANPS_SR_ACFBSY_MASK 0x00000800U /**< Acceptance Filter busy */ +#define XCANPS_SR_TXFLL_MASK 0x00000400U /**< TX FIFO is full */ +#define XCANPS_SR_TXBFLL_MASK 0x00000200U /**< TX High Priority Buffer full */ +#define XCANPS_SR_ESTAT_MASK 0x00000180U /**< Error Status */ +#define XCANPS_SR_ESTAT_SHIFT 7U +#define XCANPS_SR_ERRWRN_MASK 0x00000040U /**< Error Warning */ +#define XCANPS_SR_BBSY_MASK 0x00000020U /**< Bus Busy */ +#define XCANPS_SR_BIDLE_MASK 0x00000010U /**< Bus Idle */ +#define XCANPS_SR_NORMAL_MASK 0x00000008U /**< Normal Mode */ +#define XCANPS_SR_SLEEP_MASK 0x00000004U /**< Sleep Mode */ +#define XCANPS_SR_LBACK_MASK 0x00000002U /**< Loop Back Mode */ +#define XCANPS_SR_CONFIG_MASK 0x00000001U /**< Configuration Mode */ +/* @} */ + +/** @name Interrupt Status/Enable/Clear Register Bit Definitions and Masks + * @{ + */ +#define XCANPS_IXR_TXFEMP_MASK 0x00004000U /**< Tx Fifo Empty Interrupt */ +#define XCANPS_IXR_TXFWMEMP_MASK 0x00002000U /**< Tx Fifo Watermark Empty */ +#define XCANPS_IXR_RXFWMFLL_MASK 0x00001000U /**< Rx FIFO Watermark Full */ +#define XCANPS_IXR_WKUP_MASK 0x00000800U /**< Wake up Interrupt */ +#define XCANPS_IXR_SLP_MASK 0x00000400U /**< Sleep Interrupt */ +#define XCANPS_IXR_BSOFF_MASK 0x00000200U /**< Bus Off Interrupt */ +#define XCANPS_IXR_ERROR_MASK 0x00000100U /**< Error Interrupt */ +#define XCANPS_IXR_RXNEMP_MASK 0x00000080U /**< RX FIFO Not Empty Interrupt */ +#define XCANPS_IXR_RXOFLW_MASK 0x00000040U /**< RX FIFO Overflow Interrupt */ +#define XCANPS_IXR_RXUFLW_MASK 0x00000020U /**< RX FIFO Underflow Interrupt */ +#define XCANPS_IXR_RXOK_MASK 0x00000010U /**< New Message Received Intr */ +#define XCANPS_IXR_TXBFLL_MASK 0x00000008U /**< TX High Priority Buf Full */ +#define XCANPS_IXR_TXFLL_MASK 0x00000004U /**< TX FIFO Full Interrupt */ +#define XCANPS_IXR_TXOK_MASK 0x00000002U /**< TX Successful Interrupt */ +#define XCANPS_IXR_ARBLST_MASK 0x00000001U /**< Arbitration Lost Interrupt */ +#define XCANPS_IXR_ALL ((u32)XCANPS_IXR_RXFWMFLL_MASK | \ + (u32)XCANPS_IXR_WKUP_MASK | \ + (u32)XCANPS_IXR_SLP_MASK | \ + (u32)XCANPS_IXR_BSOFF_MASK | \ + (u32)XCANPS_IXR_ERROR_MASK | \ + (u32)XCANPS_IXR_RXNEMP_MASK | \ + (u32)XCANPS_IXR_RXOFLW_MASK | \ + (u32)XCANPS_IXR_RXUFLW_MASK | \ + (u32)XCANPS_IXR_RXOK_MASK | \ + (u32)XCANPS_IXR_TXBFLL_MASK | \ + (u32)XCANPS_IXR_TXFLL_MASK | \ + (u32)XCANPS_IXR_TXOK_MASK | \ + (u32)XCANPS_IXR_ARBLST_MASK) +/* @} */ + +/** @name CAN Timestamp Control Register (TCR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_TCR_CTS_MASK 0x00000001U /**< Clear Timestamp counter mask */ +/* @} */ + +/** @name CAN Watermark Register (WIR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_WIR_FW_MASK 0x0000003FU /**< Rx Full Threshold mask */ +#define XCANPS_WIR_EW_MASK 0x00003F00U /**< Tx Empty Threshold mask */ +#define XCANPS_WIR_EW_SHIFT 0x00000008U /**< Tx Empty Threshold shift */ + +/* @} */ + +/** @name CAN Frame Identifier (TX High Priority Buffer/TX/RX/Acceptance Filter + Mask/Acceptance Filter ID) + * @{ + */ +#define XCANPS_IDR_ID1_MASK 0xFFE00000U /**< Standard Messg Identifier */ +#define XCANPS_IDR_ID1_SHIFT 21U +#define XCANPS_IDR_SRR_MASK 0x00100000U /**< Substitute Remote TX Req */ +#define XCANPS_IDR_SRR_SHIFT 20U +#define XCANPS_IDR_IDE_MASK 0x00080000U /**< Identifier Extension */ +#define XCANPS_IDR_IDE_SHIFT 19U +#define XCANPS_IDR_ID2_MASK 0x0007FFFEU /**< Extended Message Ident */ +#define XCANPS_IDR_ID2_SHIFT 1U +#define XCANPS_IDR_RTR_MASK 0x00000001U /**< Remote TX Request */ +/* @} */ + +/** @name CAN Frame Data Length Code (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DLCR_DLC_MASK 0xF0000000U /**< Data Length Code */ +#define XCANPS_DLCR_DLC_SHIFT 28U +#define XCANPS_DLCR_TIMESTAMP_MASK 0x0000FFFFU /**< Timestamp Mask (Rx only) */ + +/* @} */ + +/** @name CAN Frame Data Word 1 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW1R_DB0_MASK 0xFF000000U /**< Data Byte 0 */ +#define XCANPS_DW1R_DB0_SHIFT 24U +#define XCANPS_DW1R_DB1_MASK 0x00FF0000U /**< Data Byte 1 */ +#define XCANPS_DW1R_DB1_SHIFT 16U +#define XCANPS_DW1R_DB2_MASK 0x0000FF00U /**< Data Byte 2 */ +#define XCANPS_DW1R_DB2_SHIFT 8U +#define XCANPS_DW1R_DB3_MASK 0x000000FFU /**< Data Byte 3 */ +/* @} */ + +/** @name CAN Frame Data Word 2 (TX High Priority Buffer/TX/RX) + * @{ + */ +#define XCANPS_DW2R_DB4_MASK 0xFF000000U /**< Data Byte 4 */ +#define XCANPS_DW2R_DB4_SHIFT 24U +#define XCANPS_DW2R_DB5_MASK 0x00FF0000U /**< Data Byte 5 */ +#define XCANPS_DW2R_DB5_SHIFT 16U +#define XCANPS_DW2R_DB6_MASK 0x0000FF00U /**< Data Byte 6 */ +#define XCANPS_DW2R_DB6_SHIFT 8U +#define XCANPS_DW2R_DB7_MASK 0x000000FFU /**< Data Byte 7 */ +/* @} */ + +/** @name Acceptance Filter Register (AFR) Bit Definitions and Masks + * @{ + */ +#define XCANPS_AFR_UAF4_MASK 0x00000008U /**< Use Acceptance Filter No.4 */ +#define XCANPS_AFR_UAF3_MASK 0x00000004U /**< Use Acceptance Filter No.3 */ +#define XCANPS_AFR_UAF2_MASK 0x00000002U /**< Use Acceptance Filter No.2 */ +#define XCANPS_AFR_UAF1_MASK 0x00000001U /**< Use Acceptance Filter No.1 */ +#define XCANPS_AFR_UAF_ALL_MASK ((u32)XCANPS_AFR_UAF4_MASK | \ + (u32)XCANPS_AFR_UAF3_MASK | \ + (u32)XCANPS_AFR_UAF2_MASK | \ + (u32)XCANPS_AFR_UAF1_MASK) +/* @} */ + +/** @name CAN frame length constants + * @{ + */ +#define XCANPS_MAX_FRAME_SIZE sizeof(u32)*16U /**< Maximum CAN frame length in bytes */ +/* @} */ + +/* For backwards compatibilty */ +#define XCANPS_TXBUF_ID_OFFSET XCANPS_TXHPB_ID_OFFSET +#define XCANPS_TXBUF_DLC_OFFSET XCANPS_TXHPB_DLC_OFFSET +#define XCANPS_TXBUF_DW1_OFFSET XCANPS_TXHPB_DW1_OFFSET +#define XCANPS_TXBUF_DW2_OFFSET XCANPS_TXHPB_DW2_OFFSET + +#define XCANPS_RXFWIR_RXFLL_MASK XCANPS_WIR_FW_MASK +#define XCANPS_RXWIR_OFFSET XCANPS_WIR_OFFSET +#define XCANPS_IXR_RXFLL_MASK XCANPS_IXR_RXFWMFLL_MASK + + + + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be read. +* +* @return The 32-bit value of the register +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_ReadReg(BaseAddr, RegOffset) \ + Xil_In32((BaseAddr) + (u32)(RegOffset)) + + +/****************************************************************************/ +/** +* +* This macro writes the given register. +* +* @param BaseAddr is the base address of the device. +* @param RegOffset is the register offset to be written. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +#define XCanPs_WriteReg(BaseAddr, RegOffset, Data) \ + Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data)) + +/************************** Function Prototypes ******************************/ +/* + * Perform reset operation to the CanPs interface + */ +void XCanPs_ResetHw(u32 BaseAddr); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_intr.c new file mode 100644 index 000000000..f6721ca75 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_intr.c @@ -0,0 +1,421 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_intr.c +* @addtogroup canps_v3_0 +* @{ +* +* This file contains functions related to CAN interrupt handling. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1   nsk    12/21/15 Updated XCanPs_IntrHandler to handle error
+*			interrupts correctly. CR#925615
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Variable Definitions *****************************/ + +/************************** Function Prototypes ******************************/ + +/****************************************************************************/ +/** +* +* This routine enables interrupt(s). Use the XCANPS_IXR_* constants defined in +* xcanps_hw.h to create the bit-mask to enable interrupts. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to enable. Bit positions of 1 will be enabled. +* Bit positions of 0 will keep the previous setting. This mask is +* formed by OR'ing XCANPS_IXR_* bits defined in xcanps_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrEnable(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Write to the IER to enable the specified interrupts. + */ + IntrValue = XCanPs_IntrGetEnabled(InstancePtr); + IntrValue |= Mask; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET, IntrValue); +} + +/****************************************************************************/ +/** +* +* This routine disables interrupt(s). Use the XCANPS_IXR_* constants defined in +* xcanps_hw.h to create the bit-mask to disable interrupt(s). +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to disable. Bit positions of 1 will be +* disabled. Bit positions of 0 will keep the previous setting. +* This mask is formed by OR'ing XCANPS_IXR_* bits defined in +* xcanps_hw.h. +* +* @return None. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrDisable(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Write to the IER to disable the specified interrupts. + */ + IntrValue = XCanPs_IntrGetEnabled(InstancePtr); + IntrValue &= ~Mask; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET, IntrValue); +} + +/****************************************************************************/ +/** +* +* This routine returns enabled interrupt(s). Use the XCANPS_IXR_* constants +* defined in xcanps_hw.h to interpret the returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return Enabled interrupt(s) in a 32-bit format. +* +* @note None. +* +*****************************************************************************/ +u32 XCanPs_IntrGetEnabled(XCanPs *InstancePtr) +{ + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_IER_OFFSET); +} + + +/****************************************************************************/ +/** +* +* This routine returns interrupt status read from Interrupt Status Register. +* Use the XCANPS_IXR_* constants defined in xcanps_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return The value stored in Interrupt Status Register. +* +* @note None. +* +*****************************************************************************/ +u32 XCanPs_IntrGetStatus(XCanPs *InstancePtr) +{ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + return XCanPs_ReadReg(InstancePtr->CanConfig.BaseAddr, + XCANPS_ISR_OFFSET); +} + +/****************************************************************************/ +/** +* +* This function clears interrupt(s). Every bit set in Interrupt Status +* Register indicates that a specific type of interrupt is occurring, and this +* function clears one or more interrupts by writing a bit mask to Interrupt +* Clear Register. +* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param Mask is the mask to clear. Bit positions of 1 will be cleared. +* Bit positions of 0 will not change the previous interrupt +* status. This mask is formed by OR'ing XCANPS_IXR_* bits defined +* in xcanps_hw.h. +* +* @note None. +* +*****************************************************************************/ +void XCanPs_IntrClear(XCanPs *InstancePtr, u32 Mask) +{ + u32 IntrValue; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + /* + * Clear the currently pending interrupts. + */ + IntrValue = XCanPs_IntrGetStatus(InstancePtr); + IntrValue &= Mask; + XCanPs_WriteReg(InstancePtr->CanConfig.BaseAddr, XCANPS_ICR_OFFSET, + IntrValue); +} + +/*****************************************************************************/ +/** +* +* This routine is the interrupt handler for the CAN driver. +* +* This handler reads the interrupt status from the ISR, determines the source of +* the interrupts, calls according callbacks, and finally clears the interrupts. +* +* Application beyond this driver is responsible for providing callbacks to +* handle interrupts and installing the callbacks using XCanPs_SetHandler() +* during initialization phase. An example delivered with this driver +* demonstrates how this could be done. +* +* @param InstancePtr is a pointer to the XCanPs instance that just +* interrupted. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCanPs_IntrHandler(void *InstancePtr) +{ + u32 PendingIntr; + u32 EventIntr; + u32 ErrorStatus; + XCanPs *CanPtr = (XCanPs *) ((void *)InstancePtr); + + Xil_AssertVoid(CanPtr != NULL); + Xil_AssertVoid(CanPtr->IsReady == XIL_COMPONENT_IS_READY); + + PendingIntr = XCanPs_IntrGetStatus(CanPtr); + PendingIntr &= XCanPs_IntrGetEnabled(CanPtr); + + /* + * Clear all pending interrupts. + * Rising Edge interrupt + */ + XCanPs_IntrClear(CanPtr, PendingIntr); + + /* + * An error interrupt is occurring. + */ + if (((PendingIntr & XCANPS_IXR_ERROR_MASK) != (u32)0) && + (CanPtr->ErrorHandler != NULL)) { + ErrorStatus = XCanPs_GetBusErrorStatus(CanPtr); + CanPtr->ErrorHandler(CanPtr->ErrorRef,ErrorStatus); + /* + * Clear Error Status Register. + */ + XCanPs_ClearBusErrorStatus(CanPtr,ErrorStatus); + } + + /* + * Check if any following event interrupt is pending: + * - RX FIFO Overflow + * - RX FIFO Underflow + * - TX High Priority Buffer full + * - TX FIFO Full + * - Wake up from sleep mode + * - Enter sleep mode + * - Enter Bus off status + * - Arbitration is lost + * + * If so, call event callback provided by upper level. + */ + EventIntr = PendingIntr & ((u32)XCANPS_IXR_RXOFLW_MASK | + (u32)XCANPS_IXR_RXUFLW_MASK | + (u32)XCANPS_IXR_TXBFLL_MASK | + (u32)XCANPS_IXR_TXFLL_MASK | + (u32)XCANPS_IXR_WKUP_MASK | + (u32)XCANPS_IXR_SLP_MASK | + (u32)XCANPS_IXR_BSOFF_MASK | + (u32)XCANPS_IXR_ARBLST_MASK); + if ((EventIntr != (u32)0) && (CanPtr->EventHandler != NULL)) { + CanPtr->EventHandler(CanPtr->EventRef, EventIntr); + + if ((EventIntr & XCANPS_IXR_BSOFF_MASK) != (u32)0) { + /* + * Event callback should reset whole device if "Enter + * Bus Off Status" interrupt occurred. All pending + * interrupts are cleared and no further checking and + * handling of other interrupts is needed any more. + */ + return; + } else { + /*This else was made for misra-c compliance*/ + ; + } + } + + + if (((PendingIntr & (XCANPS_IXR_RXFWMFLL_MASK | + XCANPS_IXR_RXNEMP_MASK)) != (u32)0) && + (CanPtr->RecvHandler != NULL)) { + + /* + * This case happens when + * A number of frames depending on the Rx FIFO Watermark + * threshold are received. + * And also when frame was received and is sitting in RX FIFO. + * + * XCANPS_IXR_RXOK_MASK is not used because the bit is set + * just once even if there are multiple frames sitting + * in the RX FIFO. + * + * XCANPS_IXR_RXNEMP_MASK is used because the bit can be + * set again and again automatically as long as there is + * at least one frame in RX FIFO. + */ + CanPtr->RecvHandler(CanPtr->RecvRef); + } + + /* + * A frame was transmitted successfully. + */ + if (((PendingIntr & (XCANPS_IXR_TXOK_MASK | XCANPS_IXR_TXFWMEMP_MASK)) != (u32)0) && + (CanPtr->SendHandler != NULL)) { + CanPtr->SendHandler(CanPtr->SendRef); + } +} + + +/*****************************************************************************/ +/** +* +* This routine installs an asynchronous callback function for the given +* HandlerType: +* +* 
+* HandlerType			Callback Function Type
+* -----------------------	------------------------
+* XCANPS_HANDLER_SEND		XCanPs_SendRecvHandler
+* XCANPS_HANDLER_RECV		XCanPs_SendRecvHandler
+* XCANPS_HANDLER_ERROR		XCanPs_ErrorHandler
+* XCANPS_HANDLER_EVENT		XCanPs_EventHandler
+*
+* HandlerType			Invoked by this driver when:
+* -------------------------------------------------------------------------
+* XCANPS_HANDLER_SEND		A frame transmitted by a call to
+*				XCanPs_Send() has been sent successfully.
+*
+* XCANPS_HANDLER_RECV		A frame(s) has been received and is sitting in
+*				the RX FIFO.
+*
+* XCANPS_HANDLER_ERROR		An error interrupt is occurring.
+*
+* XCANPS_HANDLER_EVENT		Any other kind of interrupt is occurring.
+*
+* +* @param InstancePtr is a pointer to the XCanPs instance. +* @param HandlerType specifies which handler is to be attached. +* @param CallBackFunc is the address of the callback function. +* @param CallBackRef is a user data item that will be passed to the +* callback function when it is invoked. +* +* @return +* - XST_SUCCESS when handler is installed. +* - XST_INVALID_PARAM when HandlerType is invalid. +* +* @note +* Invoking this function for a handler that already has been installed replaces +* it with the new handler. +* +******************************************************************************/ +s32 XCanPs_SetHandler(XCanPs *InstancePtr, u32 HandlerType, + void *CallBackFunc, void *CallBackRef) +{ + s32 Status; + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + switch (HandlerType) { + case XCANPS_HANDLER_SEND: + InstancePtr->SendHandler = + (XCanPs_SendRecvHandler) CallBackFunc; + InstancePtr->SendRef = CallBackRef; + Status = XST_SUCCESS; + break; + + case XCANPS_HANDLER_RECV: + InstancePtr->RecvHandler = + (XCanPs_SendRecvHandler) CallBackFunc; + InstancePtr->RecvRef = CallBackRef; + Status = XST_SUCCESS; + break; + + case XCANPS_HANDLER_ERROR: + InstancePtr->ErrorHandler = + (XCanPs_ErrorHandler) CallBackFunc; + InstancePtr->ErrorRef = CallBackRef; + Status = XST_SUCCESS; + break; + + case XCANPS_HANDLER_EVENT: + InstancePtr->EventHandler = + (XCanPs_EventHandler) CallBackFunc; + InstancePtr->EventRef = CallBackRef; + Status = XST_SUCCESS; + break; + + default: + Status = XST_INVALID_PARAM; + break; + } + return Status; +} + +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_selftest.c new file mode 100644 index 000000000..8bc77d7f4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_selftest.c @@ -0,0 +1,234 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_selftest.c +* @addtogroup canps_v3_0 +* @{ +* +* This file contains a diagnostic self-test function for the XCanPs driver. +* +* Read xcanps.h file for more information. +* +* @note +* The Baud Rate Prescaler Register (BRPR) and Bit Timing Register(BTR) +* are setup such that CAN baud rate equals 40Kbps, given the CAN clock +* equal to 24MHz. These need to be changed based on the desired baudrate +* and CAN clock frequency. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 2.1 adk 		23/08/14 Fixed CR:798792 Peripheral test for CANPS IP in
+*						 SDK claims a 40kbps baud rate but it's not.
+* 3.00  kvn    02/13/15 Modified code for MISRA_C:2012 compliance.
+*
+* +*****************************************************************************/ + +/***************************** Include Files ********************************/ + +#include "xstatus.h" +#include "xcanps.h" + +/************************** Constant Definitions ****************************/ + +#define XCANPS_MAX_FRAME_SIZE_IN_WORDS ((XCANPS_MAX_FRAME_SIZE) / (sizeof(u32))) + +#define FRAME_DATA_LENGTH 8U /* Frame Data field length */ + +/**************************** Type Definitions ******************************/ + +/***************** Macros (Inline Functions) Definitions ********************/ + +/************************** Variable Definitions ****************************/ + +/* + * Buffers to hold frames to send and receive. These are declared as global so + * that they are not on the stack. + */ +static u32 TxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; +static u32 RxFrame[XCANPS_MAX_FRAME_SIZE_IN_WORDS]; + +/************************** Function Prototypes *****************************/ + +/*****************************************************************************/ +/** +* +* This function runs a self-test on the CAN driver/device. The test resets +* the device, sets up the Loop Back mode, sends a standard frame, receives the +* frame, verifies the contents, and resets the device again. +* +* Note that this is a destructive test in that resets of the device are +* performed. Refer the device specification for the device status after +* the reset operation. +* +* +* @param InstancePtr is a pointer to the XCanPs instance. +* +* @return +* - XST_SUCCESS if the self-test passed. i.e., the frame +* received via the internal loop back has the same contents as +* the frame sent. +* - XST_FAILURE Otherwise. +* +* @note +* +* If the CAN device does not work properly, this function may enter an +* infinite loop and will never return to the caller. +*

+* If XST_FAILURE is returned, the device is not reset so that the caller could +* have a chance to check reason(s) causing the failure. +* +******************************************************************************/ +s32 XCanPs_SelfTest(XCanPs *InstancePtr) +{ + u8 *FramePtr; + s32 Status; + u32 Index; + u8 GetModeResult; + u32 RxEmptyResult; + + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY); + + XCanPs_Reset(InstancePtr); + + /* + * The device should enter Configuration Mode immediately after + * reset above is finished. Now check the mode and return error code if + * it is not Configuration Mode. + */ + if (XCanPs_GetMode(InstancePtr) != XCANPS_MODE_CONFIG) { + Status = XST_FAILURE; + return Status; + } + + /* + * Setup Baud Rate Prescaler Register (BRPR) and Bit Timing Register + * (BTR) such that CAN baud rate equals 40Kbps, given the CAN clock + * equal to 24MHz. For more information see the CAN 2.0A, CAN 2.0B, + * ISO 11898-1 specifications. + */ + (void)XCanPs_SetBaudRatePrescaler(InstancePtr, (u8)29U); + (void)XCanPs_SetBitTiming(InstancePtr, (u8)3U, (u8)2U, (u8)15U); + + /* + * Enter the loop back mode. + */ + XCanPs_EnterMode(InstancePtr, XCANPS_MODE_LOOPBACK); + GetModeResult = XCanPs_GetMode(InstancePtr); + while (GetModeResult != ((u8)XCANPS_MODE_LOOPBACK)) { + GetModeResult = XCanPs_GetMode(InstancePtr); + } + + /* + * Create a frame to send with known values so we can verify them + * on receive. + */ + TxFrame[0] = (u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U); + TxFrame[1] = (u32)XCanPs_CreateDlcValue((u32)8U); + + FramePtr = (u8 *)((void *)(&TxFrame[2])); + for (Index = 0U; Index < 8U; Index++) { + if(*FramePtr != 0U) { + *FramePtr = (u8)Index; + *FramePtr++; + } + } + + /* + * Send the frame. + */ + Status = XCanPs_Send(InstancePtr, TxFrame); + if (Status != (s32)XST_SUCCESS) { + Status = XST_FAILURE; + return Status; + } + + /* + * Wait until the frame arrives RX FIFO via internal loop back. + */ + RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK; + + while (RxEmptyResult == (u32)0U) { + RxEmptyResult = XCanPs_ReadReg(((InstancePtr)->CanConfig.BaseAddr), + XCANPS_ISR_OFFSET) & XCANPS_IXR_RXNEMP_MASK; + } + + /* + * Receive the frame. + */ + Status = XCanPs_Recv(InstancePtr, RxFrame); + if (Status != (s32)XST_SUCCESS) { + Status = XST_FAILURE; + return Status; + } + + /* + * Verify Identifier and Data Length Code. + */ + if (RxFrame[0] != + (u32)XCanPs_CreateIdValue((u32)2000U, (u32)0U, (u32)0U, (u32)0U, (u32)0U)) { + Status = XST_FAILURE; + return Status; + } + + if ((RxFrame[1] & ~XCANPS_DLCR_TIMESTAMP_MASK) != TxFrame[1]) { + Status = XST_FAILURE; + return Status; + } + + + for (Index = 2U; Index < (XCANPS_MAX_FRAME_SIZE_IN_WORDS); Index++) { + if (RxFrame[Index] != TxFrame[Index]) { + Status = XST_FAILURE; + return Status; + } + } + + /* + * Reset device again before returning to the caller. + */ + XCanPs_Reset(InstancePtr); + + Status = XST_SUCCESS; + return Status; +} + + +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_sinit.c new file mode 100644 index 000000000..230c429b3 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/canps_v3_1/src/xcanps_sinit.c @@ -0,0 +1,103 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcanps_sinit.c +* @addtogroup canps_v3_0 +* @{ +* +* This file contains the implementation of the XCanPs driver's static +* initialization functionality. +* +* @note None. +* +* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a xd/sv  01/12/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcanps.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Variable Definitions *****************************/ + +extern XCanPs_Config XCanPs_ConfigTable[XPAR_XCANPS_NUM_INSTANCES]; + +/*****************************************************************************/ +/** +* +* This function looks for the device configuration based on the unique device +* ID. The table XCanPs_ConfigTable[] contains the configuration information for +* each device in the system. +* +* @param DeviceId is the unique device ID of the device being looked up. +* +* @return A pointer to the configuration table entry corresponding to the +* given device ID, or NULL if no match is found. +* +* @note None. +* +******************************************************************************/ +XCanPs_Config *XCanPs_LookupConfig(u16 DeviceId) +{ + XCanPs_Config *CfgPtr = NULL; + u32 Index; + + for (Index = 0U; Index < (u32)XPAR_XCANPS_NUM_INSTANCES; Index++) { + if (XCanPs_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XCanPs_ConfigTable[Index]; + break; + } + } + + return (XCanPs_Config *)CfgPtr; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/Makefile new file mode 100644 index 000000000..007162d8c --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner coresightps_dcc_comp_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling coresightps_dcc" + +coresightps_dcc_comp_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: coresightps_dcc_includes + +coresightps_dcc_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c new file mode 100644 index 000000000..e999f6f5d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.c @@ -0,0 +1,181 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcoresightpsdcc.c +* @addtogroup coresightps_dcc_v1_1 +* @{ +* +* Functions in this file are the minimum required functions for the +* XCoreSightPs driver. +* +* @note None. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+* 1.2   kvn    10/09/15 Add support for IAR Compiler.
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include +#include + +#ifdef __ICCARM__ +#define INLINE +#else +#define INLINE __inline +#endif + +/* DCC Status Bits */ +#define XCORESIGHTPS_DCC_STATUS_RX (1 << 30) +#define XCORESIGHTPS_DCC_STATUS_TX (1 << 29) + +static INLINE u32 XCoresightPs_DccGetStatus(void); + +/****************************************************************************/ +/** +* +* This functions sends a single byte using the DCC. It is blocking in that it +* waits for the transmitter to become non-full before it writes the byte to +* the transmit register. +* +* @param BaseAddress is a dummy parameter to match the function proto +* of functions for other stdio devices. +* @param Data is the byte of data to send +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data) +{ + (void) BaseAddress; + while (XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_TX) + dsb(); +#ifdef __aarch64__ + asm volatile ("msr dbgdtrtx_el0, %0" : : "r" (Data)); +#elif defined (__GNUC__) || defined (__ICCARM__) + asm volatile("mcr p14, 0, %0, c0, c5, 0" + : : "r" (Data)); +#else + { + volatile register u32 Reg __asm("cp14:0:c0:c5:0"); + Reg = Data; + } +#endif + isb(); + +} + +/****************************************************************************/ +/** +* +* This functions receives a single byte using the DCC. It is blocking in that +* it waits for the receiver to become non-empty before it reads from the +* receive register. +* +* @param BaseAddress is a dummy parameter to match the function proto +* of functions for other stdio devices. +* +* @return The byte of data received. +* +* @note None. +* +******************************************************************************/ +u8 XCoresightPs_DccRecvByte(u32 BaseAddress) +{ + u8 Data; + (void) BaseAddress; + + while (!(XCoresightPs_DccGetStatus() & XCORESIGHTPS_DCC_STATUS_RX)) + dsb(); + +#ifdef __aarch64__ + asm volatile ("mrs %0, dbgdtrrx_el0" : "=r" (Data)); +#elif defined (__GNUC__) || defined (__ICCARM__) + asm volatile("mrc p14, 0, %0, c0, c5, 0" + : "=r" (Data)); +#else + { + volatile register u32 Reg __asm("cp14:0:c0:c5:0"); + Data = Reg; + } +#endif + isb(); + + return Data; +} + + +/****************************************************************************/ +/**INLINE +* +* This functions read the status register of the DCC. +* +* @param BaseAddress is the base address of the device +* +* @return The contents of the Status Register. +* +* @note None. +* +******************************************************************************/ +static INLINE u32 XCoresightPs_DccGetStatus(void) +{ + u32 Status; + +#ifdef __aarch64__ + asm volatile ("mrs %0, mdccsr_el0" : "=r" (Status)); +#elif defined (__GNUC__) || defined (__ICCARM__) + asm volatile("mrc p14, 0, %0, c0, c1, 0" + : "=r" (Status) : : "cc"); +#else + { + volatile register u32 Reg __asm("cp14:0:c0:c1:0"); + Status = Reg; + } +#endif + return Status; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h new file mode 100644 index 000000000..6bab7ae09 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/coresightps_dcc_v1_2/src/xcoresightpsdcc.h @@ -0,0 +1,70 @@ +/****************************************************************************** +* +* Copyright (C) 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcoresightpsdcc.h +* @addtogroup coresightps_dcc_v1_1 +* @{ +* @details +* +* CoreSight driver component. +* +* The coresight is a part of debug communication channel (DCC) group. Jtag UART +* for ARM uses DCC. Each ARM core has its own DCC, so one need to select an +* ARM target in XSDB console before running the jtag terminal command. Using the +* coresight driver component, the output stream can be directed to a log file. +* +* @note None. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date		Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    02/14/15 First release
+* 1.1   kvn    06/12/15 Add support for Zynq Ultrascale+ MP.
+*       kvn    08/18/15 Modified Makefile according to compiler changes.
+*
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include + +void XCoresightPs_DccSendByte(u32 BaseAddress, u8 Data); + +u8 XCoresightPs_DccRecvByte(u32 BaseAddress); +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/Makefile new file mode 100644 index 000000000..648f83a29 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/Makefile @@ -0,0 +1,22 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES=*.c +INCLUDEFILES=*.h + +libs: + echo "Compiling cpu_cortexr5" + +.PHONY: include +include: + ${CP} $(INCLUDEFILES) $(INCLUDEDIR) diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/xcpu_cortexr5.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/xcpu_cortexr5.h new file mode 100644 index 000000000..7b21dcd21 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/cpu_cortexr5_v1_1/src/xcpu_cortexr5.h @@ -0,0 +1,43 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcpu_cortexr5.h +* @addtogroup cpu_cortexr5_v1_1 +* @{ +* @details +* +* dummy file +* +******************************************************************************/ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/Makefile new file mode 100644 index 000000000..778797bcf --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner csudma_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling csudma" + +csudma_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: csudma_includes + +csudma_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.c new file mode 100644 index 000000000..2f6a62e50 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.c @@ -0,0 +1,767 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma.c +* @addtogroup csudma_v1_0 +* @{ +* +* This file contains the implementation of the interface functions for CSU_DMA +* driver. Refer to the header file xcsudma.h for more detailed information. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" + +/************************** Function Prototypes ******************************/ + + +/************************** Function Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* This function initializes an CSU_DMA core. This function must be called +* prior to using an CSU_DMA core. Initialization of an CSU_DMA includes setting +* up the instance data and ensuring the hardware is in a quiescent state. +* +* @param InstancePtr is a pointer to the XCsuDma instance. +* @param CfgPtr is a reference to a structure containing information +* about a specific XCsuDma instance. +* @param EffectiveAddr is the device base address in the virtual memory +* address space. The caller is responsible for keeping the +* address mapping from EffectiveAddr to the device physical +* base address unchanged once this function is invoked. +* Unexpected errors may occur if the address mapping changes +* after this function is called. If address translation is not +* used, pass in the physical address instead. +* +* @return +* - XST_SUCCESS if initialization was successful. +* +* @note None. +* +******************************************************************************/ +s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr, + u32 EffectiveAddr) +{ + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(CfgPtr != NULL); + Xil_AssertNonvoid(EffectiveAddr != ((u32)0x0)); + + /* Setup the instance */ + (void)memcpy((void *)&(InstancePtr->Config), (const void *)CfgPtr, + sizeof(XCsuDma_Config)); + InstancePtr->Config.BaseAddress = EffectiveAddr; + + XCsuDma_Reset(); + + InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY); + + return (XST_SUCCESS); + +} + +/*****************************************************************************/ +/** +* +* This function sets the starting address and amount(size) of the data to be +* transfered from/to the memory through the AXI interface. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Addr is a 64 bit variable which holds the starting address of +* data which needs to write into the memory(DST) (or read from +* the memory(SRC)). +* @param Size is a 32 bit variable which represents the number of 4 byte +* words needs to be transfered from starting address. +* @param EnDataLast is to trigger an end of message. It will enable or +* disable data_inp_last signal to stream interface when current +* command is completed. It is applicable only to source channel +* and neglected for destination channel. +* - 1 - Asserts data_inp_last signal. +* - 0 - data_inp_last will not be asserted. +* +* @return None. +* +* @note Data_inp_last signal is asserted simultaneously with the +* data_inp_valid signal associated with the final 32-bit word +* transfer. +* +******************************************************************************/ +void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + UINTPTR Addr, u32 Size, u8 EnDataLast) +{ + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(((Addr) & (u64)(XCSUDMA_ADDR_LSB_MASK)) == (u64)0x00); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(Size <= (u32)(XCSUDMA_SIZE_MAX)); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + /* Flushing cache memory */ + if (Channel == (XCSUDMA_SRC_CHANNEL)) { + Xil_DCacheFlushRange(Addr, Size << (u32)(XCSUDMA_SIZE_SHIFT)); + } + /* Invalidating cache memory */ + else { + Xil_DCacheInvalidateRange(Addr, Size << + (u32)(XCSUDMA_SIZE_SHIFT)); + } + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + ((u32)(Addr) & (u32)(XCSUDMA_ADDR_MASK))); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_MSB_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (((u64)Addr >> (u32)(XCSUDMA_MSB_ADDR_SHIFT)) & + (u32)(XCSUDMA_MSB_ADDR_MASK))); + + if (EnDataLast == (u8)(XCSUDMA_LAST_WORD_MASK)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + ((Size << (u32)(XCSUDMA_SIZE_SHIFT)) | + (u32)(XCSUDMA_LAST_WORD_MASK))); + } + else { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Size << (u32)(XCSUDMA_SIZE_SHIFT))); + } +} + +/*****************************************************************************/ +/** +* +* This function returns the current address location of the memory, from where +* it has to read the data(SRC) or the location where it has to write the data +* (DST) based on the channel selection. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Address is a 64 bit variable which holds the current address. +* - From this location data has to be read(SRC) +* - At this location data has to be written(DST) +* +* @note None. +* +******************************************************************************/ +u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + u64 FullAddr; + + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + FullAddr = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + FullAddr |= (u64)((u64)XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_ADDR_MSB_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) << + (u64)(XCSUDMA_MSB_ADDR_SHIFT)); + + return FullAddr; +} + +/*****************************************************************************/ +/** +* +* This function returns the size of the data yet to be transfered from memory +* to CSU_DMA or CSU_DMA to memory based on the channel selection. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Size is amount of data yet to be transfered. +* +* @note None. +* +******************************************************************************/ +u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + u32 Size; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + Size = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_SIZE_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) >> + (u32)(XCSUDMA_SIZE_SHIFT); + + return Size; +} + +/*****************************************************************************/ +/** +* +* This function pause the Channel data tranfer to/from memory or to/from stream +* based on pause type. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Type is type of the pause to be enabled. +* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory +* - SRC Stops issuing of new read commands to memory. +* - DST Stops issuing of new write commands to memory. +* - XCSUDMA_PAUSE_STREAM(1) - Pause stream +* - SRC Stops transfer of data from FIFO to Stream. +* - DST Stops transfer of data from stream to FIFO. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type) +{ + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) || + (Type == (XCSUDMA_PAUSE_STREAM))); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + /* Pause Memory Read/Write/Stream operations */ + if (Type == (XCSUDMA_PAUSE_MEMORY)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) | + (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK))); + } + if (Type == (XCSUDMA_PAUSE_STREAM)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + (Channel * (u32)XCSUDMA_OFFSET_DIFF))) | + (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK))); + } +} + +/*****************************************************************************/ +/** +* +* This functions checks whether Channel's memory or stream is paused or not +* based on the given pause type. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Type is type of the pause which needs to be checked. +* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory +* - SRC Stops issuing of new read commands to memory. +* - DST Stops issuing of new write commands to memory. +* - XCSUDMA_PAUSE_STREAM(1) - Pause stream +* - SRC Stops transfer of data from FIFO to Stream. +* - DST Stops transfer of data from stream to FIFO. +* +* @return Returns the pause status. +* - TRUE if it is in paused state. +* - FALSE if it is not in pause state. +* +* @note None. +* +******************************************************************************/ +s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type) +{ + + u32 Data; + s32 PauseState; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertNonvoid((Type == (XCSUDMA_PAUSE_MEMORY)) || + (Type == (XCSUDMA_PAUSE_STREAM))); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + /* To know Pause condition of Memory Read/Write/Stream operations */ + if (Type == (XCSUDMA_PAUSE_MEMORY)) { + if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_MEM_MASK)) == + (u32)0x00) { + PauseState = (s32)(FALSE); + } + else { + PauseState = (s32)(TRUE); + } + } + else { + if ((Data & (u32)(XCSUDMA_CTRL_PAUSE_STRM_MASK)) == + (u32)0x00) { + PauseState = (s32)(FALSE); + } + else { + PauseState = (s32)(TRUE); + } + } + + return (s32)PauseState; + +} + +/*****************************************************************************/ +/** +* +* This function resumes the channel if it is in paused state and continues +* where it has left or no effect if it is not in paused state, based on the +* type of pause. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Type is type of the pause to be Resume if it is in pause +* state. +* - XCSUDMA_PAUSE_MEMORY(0) - Pause memory +* - SRC Stops issuing of new read commands to memory. +* - DST Stops issuing of new write commands to memory. +* - XCSUDMA_PAUSE_STREAM(1) - Pause stream +* - SRC Stops transfer of data from FIFO to Stream. +* - DST Stops transfer of data from stream to FIFO. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type) +{ + u32 Data; + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Type == (XCSUDMA_PAUSE_MEMORY)) || + (Type == (XCSUDMA_PAUSE_STREAM))); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + if (Type == (XCSUDMA_PAUSE_MEMORY)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Data & + (~(XCSUDMA_CTRL_PAUSE_MEM_MASK)))); + } + if (Type == (XCSUDMA_PAUSE_STREAM)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + (((u32)Channel) * (u32)(XCSUDMA_OFFSET_DIFF))), + ( Data & + (~(XCSUDMA_CTRL_PAUSE_STRM_MASK)))); + } +} + +/*****************************************************************************/ +/** +* +* This function returns the sum of all the data read from AXI memory. It is +* valid only one we use CSU_DMA source channel. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* +* @return Returns the sum of all the data read from memory. +* +* @note Before start of the transfer need to clear this register to get +* correct sum otherwise it adds to previous value which results +* to wrong output. +* Valid only for source channel +* +******************************************************************************/ +u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr) +{ + u32 ChkSum; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(InstancePtr->IsReady == + (u32)(XIL_COMPONENT_IS_READY)); + + ChkSum = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CRC_OFFSET)); + + return ChkSum; + +} +/*****************************************************************************/ +/** +* +* This function clears the check sum of the data read from AXI memory. It is +* valid only for CSU_DMA source channel. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* +* @return Returns the sum of all the data read from memory. +* +* @note Before start of the transfer need to clear this register to get +* correct sum otherwise it adds to previous value which results +* to wrong output. +* +******************************************************************************/ +void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr) +{ + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CRC_OFFSET), (u32)(XCSUDMA_CRC_RESET_MASK)); +} + +/*****************************************************************************/ +/** +* This function cofigures all the values of CSU_DMA's Channels with the values +* of updated XCsuDma_Configure structure. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param ConfigurValues is a pointer to the structure XCsuDma_Configure +* whose values are used to configure CSU_DMA core. +* - SssFifoThesh When the DST FIFO level >= this value, +* the SSS interface signal, "data_out_fifo_level_hit" will be +* asserted. This mechanism can be used by the SSS to flow +* control data that is being looped back from the SRC DMA. +* - Range is (0x10 to 0x7A) threshold is 17 to 123 +* entries. +* - It is valid only for DST CSU_DMA IP. +* - ApbErr When accessed to invalid APB the resulting +* pslerr will be +* - 0 - 1'b0 +* - 1 - 1'b1 +* - EndianType Type of endianness +* - 0 doesn't change order +* - 1 will flip the order. +* - AxiBurstType....Type of the burst +* - 0 will issue INCR type burst +* - 1 will issue FIXED type burst +* - TimeoutValue Time out value for timers +* - 0x000 to 0xFFE are valid inputs +* - 0xFFF clears both timers +* - FifoThresh......Programmed watermark value +* - Range is 0x00 to 0x80 (0 to 128 entries). +* - Acache Sets the AXI CACHE bits on the AXI Write/Read +* channel. +* - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] +* for DST channel are always 1, we need to configure +* remaining 3 signal support +* (Bufferable, Read allocate and Write allocate). +* Valid inputs are: +* - 0x000 - Cacheable, but do not allocate +* - 0x001 - Cacheable and bufferable, but do not allocate +* - 0x010 - Cacheable write-through, allocate on reads +* only +* - 0x011 - Cacheable write-back, allocate on reads only +* - 0x100 - Cacheable write-through, allocate on writes +* only +* - 0x101 - Cacheable write-back, allocate on writes only +* - 0x110 - Cacheable write-through, allocate on both +* reads and writes +* - 0x111 - Cacheable write-back, allocate on both reads +* and writes +* - RouteBit To select route +* - 0 : Command will be routed normally +* - 1 : Command will be routed to APU's cache controller +* - TimeoutEn To enable or disable time out counters +* - 0 : The 2 Timeout counters are disabled +* - 1 : The 2 Timeout counters are enabled +* - TimeoutPre Set the prescaler value for the timeout in +* clk (~2.5ns) cycles +* - Range is 0x000(Prescaler enables timer every cycles) +* to 0xFFF(Prescaler enables timer every 4096 cycles) +* - MaxOutCmds Controls the maximumum number of outstanding +* AXI read commands issued. +* - Range is 0x0(Up to 1 Outstanding Read command +* allowed) to 0x8 (Up to 9 Outstanding Read +* command allowed) +* +* @return None. +* +* @note To use timers timeout value Timeout enable field should be +* enabled. +* +******************************************************************************/ +void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues) +{ + u32 Data; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)(XIL_COMPONENT_IS_READY)); + Xil_AssertVoid(ConfigurValues != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + Xil_AssertVoid(XCsuDma_IsBusy(InstancePtr, Channel) != (s32)(TRUE)); + + Data = (((ConfigurValues->EndianType << + (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)) & + (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) | + ((ConfigurValues->ApbErr << + (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)) & + (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) | + ((ConfigurValues->AxiBurstType << + (u32)(XCSUDMA_CTRL_BURST_SHIFT)) & + (u32)(XCSUDMA_CTRL_BURST_MASK)) | + ((ConfigurValues->TimeoutValue << + (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)) & + (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) | + ((ConfigurValues->FifoThresh << + (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)) & + (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK))); + if(Channel == XCSUDMA_DST_CHANNEL) { + Data = Data | (u32)((ConfigurValues->SssFifoThesh << + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)) & + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)); + } + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); + + Data = (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL2_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))) & + (u32)(XCSUDMA_CTRL2_RESERVED_MASK)); + Data |= (((ConfigurValues->Acache << + (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)) & + (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) | + ((ConfigurValues->RouteBit << + (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)) & + (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) | + ((ConfigurValues->TimeoutEn << + (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)) & + (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) | + ((ConfigurValues->TimeoutPre << + (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)) & + (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) | + ((ConfigurValues->MaxOutCmds) & + (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK))); + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL2_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); +} + +/*****************************************************************************/ +/** +* +* This function updates XCsuDma_Configure structure members with the cofigured +* values of CSU_DMA's Channel. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param ConfigurValues is a pointer to the structure XCsuDma_Configure +* whose members are updated with configurations of CSU_DMA core. +* - SssFifoThesh When the DST FIFO level >= this value, +* the SSS interface signal, "data_out_fifo_level_hit" will be +* asserted. This mechanism can be used by the SSS to flow +* control data that is being looped back from the SRC DMA. +* - Range is (0x10 to 0x7A) threshold is 17 to 123 +* entries. +* - It is valid only for DST CSU_DMA IP. +* - ApbErr When accessed to invalid APB the resulting +* pslerr will be +* - 0 - 1'b0 +* - 1 - 1'b1 +* - EndianType Type of endianness +* - 0 doesn't change order +* - 1 will flip the order. +* - AxiBurstType....Type of the burst +* - 0 will issue INCR type burst +* - 1 will issue FIXED type burst +* - TimeoutValue Time out value for timers +* - 0x000 to 0xFFE are valid inputs +* - 0xFFF clears both timers +* - FifoThresh......Programmed watermark value +* - Range is 0x00 to 0x80 (0 to 128 entries). +* - Acache Sets the AXI CACHE bits on the AXI Write/Read +* channel. +* - Cacheable ARCACHE[1] for SRC Channel and AWCACHE[1] +* for DST channel are always 1, we need to configure +* remaining 3 signal support +* (Bufferable, Read allocate and Write allocate). +* Valid inputs are: +* - 0x000 - Cacheable, but do not allocate +* - 0x001 - Cacheable and bufferable, but do not allocate +* - 0x010 - Cacheable write-through, allocate on reads +* only +* - 0x011 - Cacheable write-back, allocate on reads only +* - 0x100 - Cacheable write-through, allocate on writes +* only +* - 0x101 - Cacheable write-back, allocate on writes only +* - 0x110 - Cacheable write-through, allocate on both +* reads and writes +* - 0x111 - Cacheable write-back, allocate on both reads +* and writes +* - RouteBit To select route +* - 0 : Command will be routed based normally +* - 1 : Command will be routed to APU's cache controller +* - TimeoutEn To enable or disable time out counters +* - 0 : The 2 Timeout counters are disabled +* - 1 : The 2 Timeout counters are enabled +* - TimeoutPre Set the prescaler value for the timeout in +* clk (~2.5ns) cycles +* - Range is 0x000(Prescaler enables timer every cycles) +* to 0xFFF(Prescaler enables timer every 4096 cycles) +* - MaxOutCmds Controls the maximumum number of outstanding +* AXI read commands issued. +* - Range is 0x0(Up to 1 Outstanding Read command +* allowed) to 0x8 (Up to 9 Outstanding Read command +* allowed) +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues) +{ + u32 Data; + + /* Verify arguments. */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(ConfigurValues != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + if (Channel == (XCSUDMA_DST_CHANNEL)) { + ConfigurValues->SssFifoThesh = + (u8)((Data & + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK)) >> + (u32)(XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT)); + } + ConfigurValues->ApbErr = + (u8)((Data & (u32)(XCSUDMA_CTRL_APB_ERR_MASK)) >> + (u32)(XCSUDMA_CTRL_APB_ERR_SHIFT)); + ConfigurValues->EndianType = + (u8)((Data & (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) >> + (u32)(XCSUDMA_CTRL_ENDIAN_SHIFT)); + ConfigurValues->AxiBurstType = + (u8)((Data & (u32)(XCSUDMA_CTRL_BURST_MASK)) >> + (u32)(XCSUDMA_CTRL_BURST_SHIFT)); + ConfigurValues->TimeoutValue = + ((Data & (u32)(XCSUDMA_CTRL_TIMEOUT_MASK)) >> + (u32)(XCSUDMA_CTRL_TIMEOUT_SHIFT)); + ConfigurValues->FifoThresh = + (u8)((Data & (u32)(XCSUDMA_CTRL_FIFO_THRESH_MASK)) >> + (u32)(XCSUDMA_CTRL_FIFO_THRESH_SHIFT)); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_CTRL2_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF)))); + + ConfigurValues->Acache = + (u8)((Data & (u32)(XCSUDMA_CTRL2_ACACHE_MASK)) >> + (u32)(XCSUDMA_CTRL2_ACACHE_SHIFT)); + ConfigurValues->RouteBit = + (u8)((Data & (u32)(XCSUDMA_CTRL2_ROUTE_MASK)) >> + (u32)(XCSUDMA_CTRL2_ROUTE_SHIFT)); + ConfigurValues->TimeoutEn = + (u8)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_MASK)) >> + (u32)(XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT)); + ConfigurValues->TimeoutPre = + (u16)((Data & (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_MASK)) >> + (u32)(XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT)); + ConfigurValues->MaxOutCmds = + (u8)((Data & (u32)(XCSUDMA_CTRL2_MAXCMDS_MASK))); + +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.h new file mode 100644 index 000000000..fe63530a5 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma.h @@ -0,0 +1,418 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* The CSU_DMA is present inside CSU (Configuration Security Unit) module which +* is located within the Low-Power Subsystem (LPS) internal to the PS. +* CSU_DMA allows the CSU to move data efficiently between the memory (32 bit +* AXI interface) and the CSU stream peripherals (SHA, AES and PCAP) via Secure +* Stream Switch (SSS). +* +* The CSU_DMA is a 2 channel simple DMA, allowing separate control of the SRC +* (read) channel and DST (write) channel. The DMA is effectively able to +* transfer data: +* - From PS-side to the SSS-side (SRC DMA only) +* - From SSS-side to the PS-side (DST DMA only) +* - Simultaneous PS-side to SSS_side and SSS-side to the PS-side +* +* Initialization & Configuration +* +* The device driver enables higher layer software (e.g., an application) to +* communicate to the CSU_DMA core. +* +* XCsuDma_CfgInitialize() API is used to initialize the CSU_DMA core. +* The user needs to first call the XCsuDma_LookupConfig() API which returns +* the Configuration structure pointer which is passed as a parameter to the +* XCsuDma_CfgInitialize() API. +* +* Interrupts +* This driver will not support handling of interrupts user should write handler +* to handle the interrupts. +* +* Virtual Memory +* +* This driver supports Virtual Memory. The RTOS is responsible for calculating +* the correct device base address in Virtual Memory space. +* +* Threads +* +* This driver is not thread safe. Any needs for threads or thread mutual +* exclusion must be satisfied by the layer above this driver. +* +* Asserts +* +* Asserts are used within all Xilinx drivers to enforce constraints on argument +* values. Asserts can be turned off on a system-wide basis by defining, at +* compile time, the NDEBUG identifier. By default, asserts are turned on and it +* is recommended that users leave asserts on during development. +* +* Building the driver +* +* The XCsuDma driver is composed of several source files. This allows the user +* to build and link only those parts of the driver that are necessary. +* +* @file xcsudma.h +* @addtogroup csudma_v1_0 +* @{ +* @details +* +* This header file contains identifiers and register-level driver functions (or +* macros), range macros, structure typedefs that can be used to access the +* Xilinx CSU_DMA core instance. +* +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +#ifndef XCSUDMA_H_ +#define XCSUDMA_H_ /**< Prevent circular inclusions + * by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xcsudma_hw.h" +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xil_cache.h" + +/************************** Constant Definitions *****************************/ + +/** @name CSU_DMA Channels + * @{ + */ +typedef enum { + XCSUDMA_SRC_CHANNEL = 0U, /**< Source Channel of CSU_DMA */ + XCSUDMA_DST_CHANNEL /**< Destination Channel of CSU_DMA */ +}XCsuDma_Channel; +/*@}*/ + +/** @name CSU_DMA pause types + * @{ + */ +typedef enum { + XCSUDMA_PAUSE_MEMORY, /**< Pauses memory data transfer + * to/from CSU_DMA */ + XCSUDMA_PAUSE_STREAM, /**< Pauses stream data transfer + * to/from CSU_DMA */ +}XCsuDma_PauseType; + +/*@}*/ + + +/** @name Ranges of Size + * @{ + */ +#define XCSUDMA_SIZE_MAX 0x07FFFFFF /**< Maximum allowed no of words */ + +/*@}*/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** +* +* This function resets the CSU_DMA core. +* +* @param None. +* +* @return None. +* +* @note None. +* C-style signature: +* void XCsuDma_Reset() +* +******************************************************************************/ +#define XCsuDma_Reset() \ + Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \ + (u32)(XCSUDMA_RESET_SET_MASK)); \ + Xil_Out32(((u32)(XCSU_BASEADDRESS) + (u32)(XCSU_DMA_RESET_OFFSET)), \ + (u32)(XCSUDMA_RESET_UNSET_MASK)); + +/*****************************************************************************/ +/** +* This function will be in busy while loop until the data transfer is +* completed. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return None. +* +* @note This function should be called after XCsuDma_Transfer in polled +* mode to wait until the data gets transfered completely. +* C-style signature: +* void XCsuDma_WaitForDone(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_WaitForDone(InstancePtr,Channel) \ + while((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_I_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_IXR_DONE_MASK)) != (XCSUDMA_IXR_DONE_MASK)) + +/*****************************************************************************/ +/** +* +* This function returns the number of completed SRC/DST DMA transfers that +* have not been acknowledged by software based on the channel selection. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Count is number of completed DMA transfers but not acknowledged +* (Range is 0 to 7). +* - 000 - All finished transfers have been acknowledged. +* - Count - Count number of finished transfers are still +* outstanding. +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetDoneCount(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetDoneCount(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_DONE_CNT_MASK)) >> \ + (u32)(XCSUDMA_STS_DONE_CNT_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the current SRC/DST FIFO level in 32 bit words of the +* selected channel +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return FIFO level. (Range is 0 to 128) +* - 0 Indicates empty +* - Any number 1 to 128 indicates the number of entries in FIFO. +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetFIFOLevel(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetFIFOLevel(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_FIFO_LEVEL_MASK)) >> \ + (u32)(XCSUDMA_STS_FIFO_LEVEL_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the current number of read(src)/write(dst) outstanding +* commands based on the type of channel selected. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Count of outstanding commands. (Range is 0 to 9). +* +* @note None. +* C-style signature: +* u8 XCsuDma_GetWROutstandCount(XCsuDma *InstancePtr, +* XCsuDma_Channel Channel) +* +******************************************************************************/ +#define XCsuDma_GetWROutstandCount(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCUSDMA_STS_OUTSTDG_MASK)) >> \ + (u32)(XCUSDMA_STS_OUTSTDG_SHIFT)) + +/*****************************************************************************/ +/** +* +* This function returns the status of Channel either it is busy or not. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return Returns the current status of the core. +* - TRUE represents core is currently busy. +* - FALSE represents core is not involved in any transfers. +* +* @note None. +* C-style signature: +* s32 XCsuDma_IsBusy(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +* +******************************************************************************/ + +#define XCsuDma_IsBusy(InstancePtr, Channel) \ + ((XCsuDma_ReadReg(((InstancePtr)->Config.BaseAddress), \ + ((u32)(XCSUDMA_STS_OFFSET) + \ + ((u32)(Channel) * (u32)(XCSUDMA_OFFSET_DIFF)))) & \ + (u32)(XCSUDMA_STS_BUSY_MASK)) == (XCSUDMA_STS_BUSY_MASK)) ? \ + (TRUE) : (FALSE) + + +/**************************** Type Definitions *******************************/ + +/** +* This typedef contains configuration information for a CSU_DMA core. +* Each CSU_DMA core should have a configuration structure associated. +*/ +typedef struct { + u16 DeviceId; /**< DeviceId is the unique ID of the + * device */ + u32 BaseAddress; /**< BaseAddress is the physical base address + * of the device's registers */ +} XCsuDma_Config; + + +/******************************************************************************/ +/** +* +* The XCsuDma driver instance data structure. A pointer to an instance data +* structure is passed around by functions to refer to a specific driver +* instance. +*/ +typedef struct { + XCsuDma_Config Config; /**< Hardware configuration */ + u32 IsReady; /**< Device and the driver instance + * are initialized */ +}XCsuDma; + + +/******************************************************************************/ +/** +* This typedef contains all the configuration feilds which needs to be set +* before the start of the data transfer. All these feilds of CSU_DMA can be +* configured by using XCsuDma_SetConfig API. +*/ +typedef struct { + u8 SssFifoThesh; /**< SSS FIFO threshold value */ + u8 ApbErr; /**< ABP invalid access error */ + u8 EndianType; /**< Type of endianess */ + u8 AxiBurstType; /**< Type of AXI bus */ + u32 TimeoutValue; /**< Time out value */ + u8 FifoThresh; /**< FIFO threshold value */ + u8 Acache; /**< AXI CACHE selection */ + u8 RouteBit; /**< Selection of Route */ + u8 TimeoutEn; /**< Enable of time out counters */ + u16 TimeoutPre; /**< Pre scaler value */ + u8 MaxOutCmds; /**< Maximum number of outstanding + * commands */ +}XCsuDma_Configure; + +/*****************************************************************************/ + + +/************************** Function Prototypes ******************************/ + +XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId); + +s32 XCsuDma_CfgInitialize(XCsuDma *InstancePtr, XCsuDma_Config *CfgPtr, + u32 EffectiveAddr); +void XCsuDma_Transfer(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + UINTPTR Addr, u32 Size, u8 EnDataLast); +void XCsuDma_LoopBackTransfer(XCsuDma *InstancePtr, u64 SrcAddr, u64 DstAddr, + u32 Size); +u64 XCsuDma_GetAddr(XCsuDma *InstancePtr, XCsuDma_Channel Channel); +u32 XCsuDma_GetSize(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +void XCsuDma_Pause(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); +s32 XCsuDma_IsPaused(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); +void XCsuDma_Resume(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_PauseType Type); + +u32 XCsuDma_GetCheckSum(XCsuDma *InstancePtr); +void XCsuDma_ClearCheckSum(XCsuDma *InstancePtr); + +void XCsuDma_SetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues); +void XCsuDma_GetConfig(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + XCsuDma_Configure *ConfigurValues); +void XCsuDma_ClearDoneCount(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +void XCsuDma_SetSafetyCheck(XCsuDma *InstancePtr, u32 Value); +u32 XCsuDma_GetSafetyCheck(XCsuDma *InstancePtr); + +/* Interrupt related APIs */ +u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel); +void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask); +u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel); + +s32 XCsuDma_SelfTest(XCsuDma *InstancePtr); + +/******************************************************************************/ + +#ifdef __cplusplus +} + +#endif + +#endif /* End of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_g.c new file mode 100644 index 000000000..b3fb65f5b --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_g.c @@ -0,0 +1,55 @@ + +/******************************************************************* +* +* CAUTION: This file is automatically generated by HSI. +* Version: +* DO NOT EDIT. +* +* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.* +*Permission is hereby granted, free of charge, to any person obtaining a copy +*of this software and associated documentation files (the Software), to deal +*in the Software without restriction, including without limitation the rights +*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +*copies of the Software, and to permit persons to whom the Software is +*furnished to do so, subject to the following conditions: +* +*The above copyright notice and this permission notice shall be included in +*all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +*(a) running on a Xilinx device, or +*(b) that interact with a Xilinx device through a bus or interconnect. +* +*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT +*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +* +*Except as contained in this notice, the name of the Xilinx shall not be used +*in advertising or otherwise to promote the sale, use or other dealings in +*this Software without prior written authorization from Xilinx. +* + +* +* Description: Driver configuration +* +*******************************************************************/ + +#include "xparameters.h" +#include "xcsudma.h" + +/* +* The configuration table for devices +*/ + +XCsuDma_Config XCsuDma_ConfigTable[] = +{ + { + XPAR_PSU_CSUDMA_DEVICE_ID, + XPAR_PSU_CSUDMA_BASEADDR + } +}; + + diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_hw.h new file mode 100644 index 000000000..6b2c2cdb8 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_hw.h @@ -0,0 +1,311 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xcsudma_hw.h +* @addtogroup csudma_v1_0 +* @{ +* +* This header file contains identifiers and register-level driver functions (or +* macros) that can be used to access the Xilinx CSU_DMA core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vnsld  22/10/14 First release
+*
+* +******************************************************************************/ + +#ifndef XCSUDMA_HW_H_ +#define XCSUDMA_HW_H_ /**< Prevent circular inclusions + * by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include "xil_io.h" + +/************************** Constant Definitions *****************************/ + +/** @name Registers offsets + * @{ + */ +#define XCSUDMA_ADDR_OFFSET 0x000 /**< Address Register Offset */ +#define XCSUDMA_SIZE_OFFSET 0x004 /**< Size Register Offset */ +#define XCSUDMA_STS_OFFSET 0x008 /**< Status Register Offset */ +#define XCSUDMA_CTRL_OFFSET 0x00C /**< Control Register Offset */ +#define XCSUDMA_CRC_OFFSET 0x010 /**< CheckSum Register Offset */ +#define XCSUDMA_I_STS_OFFSET 0x014 /**< Interrupt Status Register + * Offset */ +#define XCSUDMA_I_EN_OFFSET 0x018 /**< Interrupt Enable Register + * Offset */ +#define XCSUDMA_I_DIS_OFFSET 0x01C /**< Interrupt Disable Register + * Offset */ +#define XCSUDMA_I_MASK_OFFSET 0x020 /**< Interrupt Mask Register Offset */ +#define XCSUDMA_CTRL2_OFFSET 0x024 /**< Interrupt Control Register 2 + * Offset */ +#define XCSUDMA_ADDR_MSB_OFFSET 0x028 /**< Address's MSB Register Offset */ +#define XCSUDMA_SAFETY_CHK_OFFSET 0xFF8 /**< Safety Check Field Offset */ +#define XCSUDMA_FUTURE_ECO_OFFSET 0xFFC /**< Future potential ECO Offset */ +/*@}*/ + +/** @name CSU Base address and CSU_DMA reset offset + * @{ + */ +#define XCSU_BASEADDRESS 0xFFCA0000 + /**< CSU Base Address */ +#define XCSU_DMA_RESET_OFFSET 0x0000000CU /**< CSU_DMA Reset offset */ +/*@}*/ + +/** @name CSU_DMA Reset register bit masks + * @{ + */ +#define XCSUDMA_RESET_SET_MASK 0x00000001U /**< Reset set mask */ +#define XCSUDMA_RESET_UNSET_MASK 0x00000000U /**< Reset unset mask*/ +/*@}*/ + +/** @name Offset difference for Source and destination + * @{ + */ +#define XCSUDMA_OFFSET_DIFF 0x00000800U /**< Offset difference for + * source and + * destination channels */ +/*@}*/ + +/** @name Address register bit masks + * @{ + */ +#define XCSUDMA_ADDR_MASK 0xFFFFFFFCU /**< Address mask */ +#define XCSUDMA_ADDR_LSB_MASK 0x00000003U /**< Address alignment check + * mask */ +/*@}*/ + +/** @name Size register bit masks and shifts + * @{ + */ +#define XCSUDMA_SIZE_MASK 0x1FFFFFFCU /**< Mask for size */ +#define XCSUDMA_LAST_WORD_MASK 0x00000001U /**< Last word check bit mask*/ +#define XCSUDMA_SIZE_SHIFT 2U /**< Shift for size */ +/*@}*/ + +/** @name Status register bit masks and shifts + * @{ + */ +#define XCSUDMA_STS_DONE_CNT_MASK 0x0000E000U /**< Count done mask */ +#define XCSUDMA_STS_FIFO_LEVEL_MASK 0x00001FE0U /**< FIFO level mask */ +#define XCUSDMA_STS_OUTSTDG_MASK 0x0000001EU /**< No.of outstanding + * read/write + * commands mask */ +#define XCSUDMA_STS_BUSY_MASK 0x00000001U /**< Busy mask */ +#define XCSUDMA_STS_DONE_CNT_SHIFT 13U /**< Shift for Count + * done */ +#define XCSUDMA_STS_FIFO_LEVEL_SHIFT 5U /**< Shift for FIFO + * level */ +#define XCUSDMA_STS_OUTSTDG_SHIFT 1U /**< Shift for No.of + * outstanding + * read/write + * commands */ +/*@}*/ + +/** @name Control register bit masks and shifts + * @{ + */ +#define XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK 0xFE000000U /**< SSS FIFO threshold + * value mask */ +#define XCSUDMA_CTRL_APB_ERR_MASK 0x01000000U /**< APB register + * access error + * mask */ +#define XCSUDMA_CTRL_ENDIAN_MASK 0x00800000U /**< Endianess mask */ +#define XCSUDMA_CTRL_BURST_MASK 0x00400000U /**< AXI burst type + * mask */ +#define XCSUDMA_CTRL_TIMEOUT_MASK 0x003FFC00U /**< Time out value + * mask */ +#define XCSUDMA_CTRL_FIFO_THRESH_MASK 0x000003FCU /**< FIFO threshold + * mask */ +#define XCSUDMA_CTRL_PAUSE_MEM_MASK 0x00000001U /**< Memory pause + * mask */ +#define XCSUDMA_CTRL_PAUSE_STRM_MASK 0x00000002U /**< Stream pause + * mask */ +#define XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT 25U /**< SSS FIFO threshold + * shift */ +#define XCSUDMA_CTRL_APB_ERR_SHIFT 24U /**< APB error shift */ +#define XCSUDMA_CTRL_ENDIAN_SHIFT 23U /**< Endianess shift */ +#define XCSUDMA_CTRL_BURST_SHIFT 22U /**< AXI burst type + * shift */ +#define XCSUDMA_CTRL_TIMEOUT_SHIFT 10U /**< Time out value + * shift */ +#define XCSUDMA_CTRL_FIFO_THRESH_SHIFT 2U /**< FIFO thresh + * shift */ +/*@}*/ + +/** @name CheckSum register bit masks + * @{ + */ +#define XCSUDMA_CRC_RESET_MASK 0x00000000U /**< Mask to reset + * value of + * check sum */ +/*@}*/ + +/** @name Interrupt Enable/Disable/Mask/Status registers bit masks + * @{ + */ +#define XCSUDMA_IXR_FIFO_OVERFLOW_MASK 0x00000001U /**< FIFO overflow + * mask, it is valid + * only to Destination + * Channel */ +#define XCSUDMA_IXR_INVALID_APB_MASK 0x00000040U /**< Invalid APB access + * mask */ +#define XCSUDMA_IXR_FIFO_THRESHHIT_MASK 0x00000020U /**< FIFO threshold hit + * indicator mask */ +#define XCSUDMA_IXR_TIMEOUT_MEM_MASK 0x00000010U /**< Time out counter + * expired to access + * memory mask */ +#define XCSUDMA_IXR_TIMEOUT_STRM_MASK 0x00000008U /**< Time out counter + * expired to access + * stream mask */ +#define XCSUDMA_IXR_AXI_WRERR_MASK 0x00000004U /**< AXI Read/Write + * error mask */ +#define XCSUDMA_IXR_DONE_MASK 0x00000002U /**< Done mask */ +#define XCSUDMA_IXR_MEM_DONE_MASK 0x00000001U /**< Memory done + * mask, it is valid + * only for source + * channel*/ +#define XCSUDMA_IXR_SRC_MASK 0x0000007FU + /**< ((XCSUDMA_IXR_INVALID_APB_MASK)| + (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | + (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | + (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | + (XCSUDMA_IXR_AXI_WRERR_MASK) | + (XCSUDMA_IXR_DONE_MASK) | + (XCSUDMA_IXR_MEM_DONE_MASK)) */ + /**< All interrupt mask + * for source */ +#define XCSUDMA_IXR_DST_MASK 0x000000FEU + /**< ((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) | + (XCSUDMA_IXR_INVALID_APB_MASK) | + (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | + (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | + (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | + (XCSUDMA_IXR_AXI_WRERR_MASK) | + (XCSUDMA_IXR_DONE_MASK)) */ + /**< All interrupt mask + * for destination */ +/*@}*/ + +/** @name Control register 2 bit masks and shifts + * @{ + */ +#define XCSUDMA_CTRL2_RESERVED_MASK 0x083F0000U /**< Reserved bits + * mask */ +#define XCSUDMA_CTRL2_ACACHE_MASK 0X07000000U /**< AXI CACHE mask */ +#define XCSUDMA_CTRL2_ROUTE_MASK 0x00800000U /**< Route mask */ +#define XCSUDMA_CTRL2_TIMEOUT_EN_MASK 0x00400000U /**< Time out counters + * enable mask */ +#define XCSUDMA_CTRL2_TIMEOUT_PRE_MASK 0x0000FFF0U /**< Time out pre + * mask */ +#define XCSUDMA_CTRL2_MAXCMDS_MASK 0x0000000FU /**< Maximum commands + * mask */ +#define XCSUDMA_CTRL2_RESET_MASK 0x0000FFF8U /**< Reset mask */ +#define XCSUDMA_CTRL2_ACACHE_SHIFT 24U /**< Shift for + * AXI R/W CACHE */ +#define XCSUDMA_CTRL2_ROUTE_SHIFT 23U /**< Shift for route */ +#define XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT 22U /**< Shift for Timeout + * enable feild */ +#define XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT 4U /**< Shift for Timeout + * pre feild */ +/*@}*/ + +/** @name MSB Address register bit masks and shifts + * @{ + */ +#define XCSUDMA_MSB_ADDR_MASK 0x0001FFFFU /**< MSB bits of address + * mask */ +#define XCSUDMA_MSB_ADDR_SHIFT 32U /**< Shift for MSB bits of + * address */ +/*@}*/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define XCsuDma_In32 Xil_In32 /**< Input operation */ +#define XCsuDma_Out32 Xil_Out32 /**< Output operation */ + +/*****************************************************************************/ +/** +* +* This macro reads the given register. +* +* @param BaseAddress is the Xilinx base address of the CSU_DMA core. +* @param RegOffset is the register offset of the register. +* +* @return The 32-bit value of the register. +* +* @note C-style signature: +* u32 XCsuDma_ReadReg(u32 BaseAddress, u32 RegOffset) +* +******************************************************************************/ +#define XCsuDma_ReadReg(BaseAddress, RegOffset) \ + XCsuDma_In32((BaseAddress) + (u32)(RegOffset)) + +/*****************************************************************************/ +/** +* +* This macro writes the value into the given register. +* +* @param BaseAddress is the Xilinx base address of the CSU_DMA core. +* @param RegOffset is the register offset of the register. +* @param Data is the 32-bit value to write to the register. +* +* @return None. +* +* @note C-style signature: +* void XCsuDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data) +* +******************************************************************************/ +#define XCsuDma_WriteReg(BaseAddress, RegOffset, Data) \ + XCsuDma_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)) + + +#ifdef __cplusplus +} + +#endif + + +#endif /* End of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_intr.c new file mode 100644 index 000000000..9f37e4582 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_intr.c @@ -0,0 +1,274 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_intr.c +* @addtogroup csudma_v1_0 +* @{ +* +* This file contains interrupt related functions of Xilinx CSU_DMA core. +* Please see xcsudma.h for more details of the driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld  22/10/14  First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" + +/************************** Function Prototypes ******************************/ + + +/************************** Function Definitions *****************************/ + + +/*****************************************************************************/ +/** +* +* This function returns interrupt status read from Interrupt Status Register. +* Use the XCSUDMA_IXR_*_MASK constants defined in xcsudma_hw.h to interpret the +* returned value. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return The pending interrupts of the CSU_DMA. Use th following masks +* to interpret the returned value. +* XCSUDMA_IXR_SRC_MASK - For Source channel +* XCSUDMA_IXR_DST_MASK - For Destination channel +* +* @note None. +* +******************************************************************************/ +u32 XCsuDma_IntrGetStatus(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + u32 Data; + + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_I_STS_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))); + + return Data; + +} + +/*****************************************************************************/ +/** +* +* This function clears interrupt(s). Every bit set in Interrupt Status +* Register indicates that a specific type of interrupt is occurring, and this +* function clears one or more interrupts by writing a bit mask to Interrupt +* Clear Register. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Mask is the mask to clear. Bit positions of 1 will be cleared. +* Bit positions of 0 will not change the previous interrupt +* status. This mask is formed by OR'ing XCSUDMA_IXR_* bits +* defined in xcsudma_hw.h. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_IntrClear(XCsuDma *InstancePtr, XCsuDma_Channel Channel, u32 Mask) +{ + + + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + if (Channel == (XCSUDMA_SRC_CHANNEL)) { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_I_STS_OFFSET), + (Mask & (u32)(XCSUDMA_IXR_SRC_MASK))); + } + else { + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_STS_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), + (Mask & (u32)(XCSUDMA_IXR_DST_MASK))); + } +} + +/*****************************************************************************/ +/** +* +* This function enables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants +* defined in xcsudma_hw.h to create the bit-mask to enable interrupts. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Mask contains interrupts to be enabled. +* - Bit positions of 1 will be enabled. +* This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined +* in xcsudma_hw.h. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_EnableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask) +{ + u32 Data; + + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + if (Channel == (XCSUDMA_SRC_CHANNEL)) { + Data = Mask & (u32)(XCSUDMA_IXR_SRC_MASK); + } + else { + Data = Mask & (u32)(XCSUDMA_IXR_DST_MASK); + } + /* + * Write the mask to the IER Register + */ + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_EN_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); + +} + +/*****************************************************************************/ +/** +* +* This function disables the interrupt(s). Use the XCSUDMA_IXR_*_MASK constants +* defined in xcsudma_hw.h to create the bit-mask to disable interrupts. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* @param Mask contains interrupts to be disabled. +* - Bit positions of 1 will be disabled. +* This mask is formed by OR'ing XCSUDMA_IXR_*_MASK bits defined +* in xcsudma_hw.h. +* +* @return None. +* +* @note None. +* +******************************************************************************/ +void XCsuDma_DisableIntr(XCsuDma *InstancePtr, XCsuDma_Channel Channel, + u32 Mask) +{ + u32 Data; + + /* Verify arguments */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + if (Channel == XCSUDMA_SRC_CHANNEL) { + Data = (Mask) & (u32)(XCSUDMA_IXR_SRC_MASK); + } + else { + Data = (Mask) & (u32)(XCSUDMA_IXR_DST_MASK); + } + + /* + * Write the mask to the IDR Register + */ + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_DIS_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))), Data); + +} + +/*****************************************************************************/ +/** +* +* This function returns the interrupt mask to know which interrupts are +* enabled and which of them were disaled. +* +* @param InstancePtr is a pointer to XCsuDma instance to be worked on. +* @param Channel represents the type of channel either it is Source or +* Destination. +* Source channel - XCSUDMA_SRC_CHANNEL +* Destination Channel - XCSUDMA_DST_CHANNEL +* +* @return The current interrupt mask. The mask indicates which interrupts +* are enabled/disabled. +* 0 bit represents .....corresponding interrupt is enabled. +* 1 bit represents .....Corresponding interrupt is disabled. +* To interpret returned mask use +* XCSUDMA_IXR_SRC_MASK........For source channel +* XCSUDMA_IXR_DST_MASK........For destination channel +* +* @note None. +* +******************************************************************************/ +u32 XCsuDma_GetIntrMask(XCsuDma *InstancePtr, XCsuDma_Channel Channel) +{ + + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid((Channel == (XCSUDMA_SRC_CHANNEL)) || + (Channel == (XCSUDMA_DST_CHANNEL))); + + /* + * Read the Interrupt Mask register + */ + return (XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + ((u32)(XCSUDMA_I_MASK_OFFSET) + + ((u32)Channel * (u32)(XCSUDMA_OFFSET_DIFF))))); +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c new file mode 100644 index 000000000..f61910fd4 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_selftest.c @@ -0,0 +1,125 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_selftest.c +* @addtogroup csudma_v1_0 +* @{ +* +* This file contains a diagnostic self-test function for the CSU_DMA driver. +* Refer to the header file xcsudma.h for more detailed information. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" + +/************************** Constant Definitions ****************************/ + + +/**************************** Type Definitions ******************************/ + + +/***************** Macros (Inline Functions) Definitions ********************/ + + +/************************** Variable Definitions ****************************/ + + +/************************** Function Prototypes *****************************/ + + +/************************** Function Definitions *****************************/ + + +/*****************************************************************************/ +/** +* +* This function runs a self-test on the driver and hardware device. Performs +* reset of both source and destination channels and checks if reset is working +* properly or not. +* +* @param InstancePtr is a pointer to the XCsuDma instance. +* +* @return +* - XST_SUCCESS if the self-test passed. +* - XST_FAILURE otherwise. +* +* @note None. +* +******************************************************************************/ +s32 XCsuDma_SelfTest(XCsuDma *InstancePtr) +{ + u32 Data; + s32 Status; + + /* Verify arguments. */ + Xil_AssertNonvoid(InstancePtr != NULL); + + Data = XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET)); + + /* Changing Endianess of Source channel */ + + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET), + ((Data) | (u32)(XCSUDMA_CTRL_ENDIAN_MASK))); + + if ((XCsuDma_ReadReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET)) & + (u32)(XCSUDMA_CTRL_ENDIAN_MASK)) == + (XCSUDMA_CTRL_ENDIAN_MASK)) { + Status = (s32)(XST_SUCCESS); + } + else { + Status = (s32)(XST_FAILURE); + } + + /* Changes made are being reverted back */ + XCsuDma_WriteReg(InstancePtr->Config.BaseAddress, + (u32)(XCSUDMA_CTRL_OFFSET), Data); + + return Status; + +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c new file mode 100644 index 000000000..10e5c14f6 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/csudma_v1_0/src/xcsudma_sinit.c @@ -0,0 +1,107 @@ +/****************************************************************************** +* +* Copyright (C) 2014 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ + +/*****************************************************************************/ +/** +* +* @file xcsudma_sinit.c +* @addtogroup csudma_v1_0 +* @{ +* +* This file contains static initialization methods for Xilinx CSU_DMA core. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ---------------------------------------------------
+* 1.0   vnsld   22/10/14 First release
+*
+* +******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xcsudma.h" +#include "xparameters.h" + +/************************** Constant Definitions *****************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/**************************** Type Definitions *******************************/ + + +/************************** Function Prototypes ******************************/ + + +/************************** Variable Definitions *****************************/ + + +/************************** Function Definitions *****************************/ + +/*****************************************************************************/ +/** +* +* XCsuDma_LookupConfig returns a reference to an XCsuDma_Config structure +* based on the unique device id, DeviceId. The return value will refer +* to an entry in the device configuration table defined in the xcsudma_g.c +* file. +* +* @param DeviceId is the unique device ID of the device for the lookup +* operation. +* +* @return CfgPtr is a reference to a config record in the configuration +* table (in xcsudma_g.c) corresponding to DeviceId, or +* NULL if no match is found. +* +* @note None. +******************************************************************************/ +XCsuDma_Config *XCsuDma_LookupConfig(u16 DeviceId) +{ + extern XCsuDma_Config XCsuDma_ConfigTable[XPAR_XCSUDMA_NUM_INSTANCES]; + XCsuDma_Config *CfgPtr = NULL; + u32 Index; + + /* Checks all the instances */ + for (Index = (u32)0x0; Index < (u32)(XPAR_XCSUDMA_NUM_INSTANCES); + Index++) { + if (XCsuDma_ConfigTable[Index].DeviceId == DeviceId) { + CfgPtr = &XCsuDma_ConfigTable[Index]; + break; + } + } + + return (XCsuDma_Config *)CfgPtr; +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/Makefile new file mode 100644 index 000000000..7002e6223 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/Makefile @@ -0,0 +1,40 @@ +COMPILER= +ARCHIVER= +CP=cp +COMPILER_FLAGS= +EXTRA_COMPILER_FLAGS= +LIB=libxil.a + +CC_FLAGS = $(COMPILER_FLAGS) +ECC_FLAGS = $(EXTRA_COMPILER_FLAGS) + +RELEASEDIR=../../../lib +INCLUDEDIR=../../../include +INCLUDES=-I./. -I${INCLUDEDIR} + +OUTS = *.o + +LIBSOURCES:=*.c +INCLUDEFILES:=*.h + +OBJECTS = $(addsuffix .o, $(basename $(wildcard *.c))) + +libs: banner xemacps_libs clean + +%.o: %.c + ${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $< + +banner: + echo "Compiling emacps" + +xemacps_libs: ${OBJECTS} + $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS} + +.PHONY: include +include: xemacps_includes + +xemacps_includes: + ${CP} ${INCLUDEFILES} ${INCLUDEDIR} + +clean: + rm -rf ${OBJECTS} diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.c new file mode 100644 index 000000000..26df03c3d --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.c @@ -0,0 +1,489 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps.c +* @addtogroup emacps_v3_1 +* @{ +* +* The XEmacPs driver. Functions in this file are the minimum required functions +* for this driver. See xemacps.h for a detailed description of the driver. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1  srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and
+*		      64-bit changes.
+* 3.00 kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   02/20/15 Added support for jumbo frames. Increase AHB burst.
+*                    Disable extended mode. Perform all 64 bit changes under
+*                    check for arch64.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr registers
+*
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xemacps.h" + +/************************** Constant Definitions *****************************/ + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +void XEmacPs_StubHandler(void); /* Default handler routine */ + +/************************** Variable Definitions *****************************/ + + +/*****************************************************************************/ +/** +* Initialize a specific XEmacPs instance/driver. The initialization entails: +* - Initialize fields of the XEmacPs instance structure +* - Reset hardware and apply default options +* - Configure the DMA channels +* +* The PHY is setup independently from the device. Use the MII or whatever other +* interface may be present for setup. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param CfgPtr is the device configuration structure containing required +* hardware build data. +* @param EffectiveAddress is the base address of the device. If address +* translation is not utilized, this parameter can be passed in using +* CfgPtr->Config.BaseAddress to specify the physical base address. +* +* @return +* - XST_SUCCESS if initialization was successful +* +******************************************************************************/ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config * CfgPtr, + UINTPTR EffectiveAddress) +{ + /* Verify arguments */ + Xil_AssertNonvoid(InstancePtr != NULL); + Xil_AssertNonvoid(CfgPtr != NULL); + + /* Set device base address and ID */ + InstancePtr->Config.DeviceId = CfgPtr->DeviceId; + InstancePtr->Config.BaseAddress = EffectiveAddress; + + /* Set callbacks to an initial stub routine */ + InstancePtr->SendHandler = ((XEmacPs_Handler)((void*)XEmacPs_StubHandler)); + InstancePtr->RecvHandler = ((XEmacPs_Handler)(void*)XEmacPs_StubHandler); + InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void*)XEmacPs_StubHandler); + + /* Reset the hardware and set default options */ + InstancePtr->IsReady = XIL_COMPONENT_IS_READY; + XEmacPs_Reset(InstancePtr); + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** +* Start the Ethernet controller as follows: +* - Enable transmitter if XTE_TRANSMIT_ENABLE_OPTION is set +* - Enable receiver if XTE_RECEIVER_ENABLE_OPTION is set +* - Start the SG DMA send and receive channels and enable the device +* interrupt +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @return N/A +* +* @note +* Hardware is configured with scatter-gather DMA, the driver expects to start +* the scatter-gather channels and expects that the user has previously set up +* the buffer descriptor lists. +* +* This function makes use of internal resources that are shared between the +* Start, Stop, and Set/ClearOptions functions. So if one task might be setting +* device options while another is trying to start the device, the user is +* required to provide protection of this shared data (typically using a +* semaphore). +* +* This function must not be preempted by an interrupt that may service the +* device. +* +******************************************************************************/ +void XEmacPs_Start(XEmacPs *InstancePtr) +{ + u32 Reg; + + /* Assert bad arguments and conditions */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Start DMA */ + /* When starting the DMA channels, both transmit and receive sides + * need an initialized BD list. + */ + if (InstancePtr->Version == 2) { + Xil_AssertVoid(InstancePtr->RxBdRing.BaseBdAddr != 0); + Xil_AssertVoid(InstancePtr->TxBdRing.BaseBdAddr != 0); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXQBASE_OFFSET, + InstancePtr->RxBdRing.BaseBdAddr); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQBASE_OFFSET, + InstancePtr->TxBdRing.BaseBdAddr); + } + + /* clear any existed int status */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + /* Enable transmitter if not already enabled */ + if ((InstancePtr->Options & (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION)!=0x00000000U) { + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + if ((!(Reg & XEMACPS_NWCTRL_TXEN_MASK))==TRUE) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + Reg | (u32)XEMACPS_NWCTRL_TXEN_MASK); + } + } + + /* Enable receiver if not already enabled */ + if ((InstancePtr->Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) { + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + if ((!(Reg & XEMACPS_NWCTRL_RXEN_MASK))==TRUE) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + Reg | (u32)XEMACPS_NWCTRL_RXEN_MASK); + } + } + + /* Enable TX and RX interrupts */ + XEmacPs_IntEnable(InstancePtr, (XEMACPS_IXR_TX_ERR_MASK | + XEMACPS_IXR_RX_ERR_MASK | (u32)XEMACPS_IXR_FRAMERX_MASK | + (u32)XEMACPS_IXR_TXCOMPL_MASK)); + + /* Enable TX Q1 Interrupts */ + if (InstancePtr->Version > 2) + XEmacPs_IntQ1Enable(InstancePtr, XEMACPS_INTQ1_IXR_ALL_MASK); + + /* Mark as started */ + InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED; + + return; +} + + +/*****************************************************************************/ +/** +* Gracefully stop the Ethernet MAC as follows: +* - Disable all interrupts from this device +* - Stop DMA channels +* - Disable the tansmitter and receiver +* +* Device options currently in effect are not changed. +* +* This function will disable all interrupts. Default interrupts settings that +* had been enabled will be restored when XEmacPs_Start() is called. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +* @note +* This function makes use of internal resources that are shared between the +* Start, Stop, SetOptions, and ClearOptions functions. So if one task might be +* setting device options while another is trying to start the device, the user +* is required to provide protection of this shared data (typically using a +* semaphore). +* +* Stopping the DMA channels causes this function to block until the DMA +* operation is complete. +* +******************************************************************************/ +void XEmacPs_Stop(XEmacPs *InstancePtr) +{ + u32 Reg; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Disable all interrupts */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + /* Disable the receiver & transmitter */ + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK); + Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); + + /* Mark as stopped */ + InstancePtr->IsStarted = 0U; +} + + +/*****************************************************************************/ +/** +* Perform a graceful reset of the Ethernet MAC. Resets the DMA channels, the +* transmitter, and the receiver. +* +* Steps to reset +* - Stops transmit and receive channels +* - Stops DMA +* - Configure transmit and receive buffer size to default +* - Clear transmit and receive status register and counters +* - Clear all interrupt sources +* - Clear phy (if there is any previously detected) address +* - Clear MAC addresses (1-4) as well as Type IDs and hash value +* +* All options are placed in their default state. Any frames in the +* descriptor lists will remain in the lists. The side effect of doing +* this is that after a reset and following a restart of the device, frames +* were in the list before the reset may be transmitted or received. +* +* The upper layer software is responsible for re-configuring (if necessary) +* and restarting the MAC after the reset. Note also that driver statistics +* are not cleared on reset. It is up to the upper layer software to clear the +* statistics if needed. +* +* When a reset is required, the driver notifies the upper layer software of +* this need through the ErrorHandler callback and specific status codes. +* The upper layer software is responsible for calling this Reset function +* and then re-configuring the device. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* +******************************************************************************/ +void XEmacPs_Reset(XEmacPs *InstancePtr) +{ + u32 Reg; + u8 i; + s8 EmacPs_zero_MAC[6] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }; + + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* Stop the device and reset hardware */ + XEmacPs_Stop(InstancePtr); + InstancePtr->Options = XEMACPS_DEFAULT_OPTIONS; + + InstancePtr->Version = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, 0xFC); + + InstancePtr->Version = (InstancePtr->Version >> 16) & 0xFFF; + + InstancePtr->MaxMtuSize = XEMACPS_MTU; + InstancePtr->MaxFrameSize = XEMACPS_MTU + XEMACPS_HDR_SIZE + + XEMACPS_TRL_SIZE; + InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize + + XEMACPS_HDR_VLAN_SIZE; + InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK; + + /* Setup hardware with default values */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, + (XEMACPS_NWCTRL_STATCLR_MASK | + XEMACPS_NWCTRL_MDEN_MASK) & + (u32)(~XEMACPS_NWCTRL_LOOPEN_MASK)); + + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCFG_OFFSET); + Reg &= XEMACPS_NWCFG_MDCCLKDIV_MASK; + + Reg = Reg | (u32)XEMACPS_NWCFG_100_MASK | + (u32)XEMACPS_NWCFG_FDEN_MASK | + (u32)XEMACPS_NWCFG_UCASTHASHEN_MASK; + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCFG_OFFSET, Reg); + if (InstancePtr->Version > 2) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET, + (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_NWCFG_OFFSET) | + XEMACPS_NWCFG_DWIDTH_64_MASK)); + } + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_DMACR_OFFSET, + (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) + + (((((u32)XEMACPS_RX_BUF_SIZE % + (u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) << + (u32)(XEMACPS_DMACR_RXBUF_SHIFT)) & + (u32)(XEMACPS_DMACR_RXBUF_MASK)) | + (u32)XEMACPS_DMACR_RXSIZE_MASK | + (u32)XEMACPS_DMACR_TXSIZE_MASK); + + + /* Single bursts */ + /* FIXME: Why Single bursts? */ + if (InstancePtr->Version > 2) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET, + (XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET) | +#ifdef __aarch64__ + (u32)XEMACPS_DMACR_ADDR_WIDTH_64 | +#endif + (u32)XEMACPS_DMACR_INCR16_AHB_BURST)); + } + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXSR_OFFSET, 0x0U); + + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_SEND); + if (InstancePtr->Version > 2) + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x01U, (u16)XEMACPS_SEND); + XEmacPs_SetQueuePtr(InstancePtr, 0, 0x00U, (u16)XEMACPS_RECV); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXSR_OFFSET, 0x0U); + + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_IDR_OFFSET, + XEMACPS_IXR_ALL_MASK); + + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_ISR_OFFSET); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET, + Reg); + + XEmacPs_ClearHash(InstancePtr); + + for (i = 1U; i < 5U; i++) { + (void)XEmacPs_SetMacAddress(InstancePtr, EmacPs_zero_MAC, i); + (void)XEmacPs_SetTypeIdCheck(InstancePtr, 0x00000000U, i); + } + + /* clear all counters */ + for (i = 0U; i < (u8)((XEMACPS_LAST_OFFSET - XEMACPS_OCTTXL_OFFSET) / 4U); + i++) { + (void)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_OCTTXL_OFFSET + (u32)(((u32)i) * ((u32)4))); + } + + /* Disable the receiver */ + Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET); + Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK); + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_NWCTRL_OFFSET, Reg); + + /* Sync default options with hardware but leave receiver and + * transmitter disabled. They get enabled with XEmacPs_Start() if + * XEMACPS_TRANSMITTER_ENABLE_OPTION and + * XEMACPS_RECEIVER_ENABLE_OPTION are set. + */ + (void)XEmacPs_SetOptions(InstancePtr, InstancePtr->Options & + ~((u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | + (u32)XEMACPS_RECEIVER_ENABLE_OPTION)); + + (void)XEmacPs_ClearOptions(InstancePtr, ~InstancePtr->Options); +} + + +/******************************************************************************/ +/** + * This is a stub for the asynchronous callbacks. The stub is here in case the + * upper layer forgot to set the handler(s). On initialization, all handlers are + * set to this callback. It is considered an error for this handler to be + * invoked. + * + ******************************************************************************/ +void XEmacPs_StubHandler(void) +{ + Xil_AssertVoidAlways(); +} + +/*****************************************************************************/ +/** +* This function sets the start address of the transmit/receive buffer queue. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @QPtr Address of the Queue to be written +* @QueueNum Buffer Queue Index +* @Direction Transmit/Recive +* +* @note +* The buffer queue addresses has to be set before starting the transfer, so +* this function has to be called in prior to XEmacPs_Start() +* +******************************************************************************/ +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction) +{ + /* Assert bad arguments and conditions */ + Xil_AssertVoid(InstancePtr != NULL); + Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY); + + /* If already started, then there is nothing to do */ + if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) { + return; + } + + if (QueueNum == 0x00U) { + if (Direction == XEMACPS_SEND) { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQBASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } else { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_RXQBASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } + } + else { + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_TXQ1BASE_OFFSET, + (QPtr & ULONG64_LO_MASK)); + } +#ifdef __aarch64__ + if (Direction == XEMACPS_SEND) { + /* Set the MSB of TX Queue start address */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_MSBBUF_TXQBASE_OFFSET, + (u32)((QPtr & ULONG64_HI_MASK) >> 32U)); + } else { + /* Set the MSB of RX Queue start address */ + XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, + XEMACPS_MSBBUF_RXQBASE_OFFSET, + (u32)((QPtr & ULONG64_HI_MASK) >> 32U)); + } +#endif +} +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.h new file mode 100644 index 000000000..f12092bec --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps.h @@ -0,0 +1,792 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2016 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/****************************************************************************/ +/** + * + * @file xemacps.h +* @addtogroup emacps_v3_1 +* @{ +* @details + * + * The Xilinx Embedded Processor Block Ethernet driver. + * + * For a full description of XEMACPS features, please see the hardware spec. + * This driver supports the following features: + * - Memory mapped access to host interface registers + * - Statistics counter registers for RMON/MIB + * - API for interrupt driven frame transfers for hardware configured DMA + * - Virtual memory support + * - Unicast, broadcast, and multicast receive address filtering + * - Full and half duplex operation + * - Automatic PAD & FCS insertion and stripping + * - Flow control + * - Support up to four 48bit addresses + * - Address checking for four specific 48bit addresses + * - VLAN frame support + * - Pause frame support + * - Large frame support up to 1536 bytes + * - Checksum offload + * + * Driver Description + * + * The device driver enables higher layer software (e.g., an application) to + * communicate to the XEmacPs. The driver handles transmission and reception + * of Ethernet frames, as well as configuration and control. No pre or post + * processing of frame data is performed. The driver does not validate the + * contents of an incoming frame in addition to what has already occurred in + * hardware. + * A single device driver can support multiple devices even when those devices + * have significantly different configurations. + * + * Initialization & Configuration + * + * The XEmacPs_Config structure is used by the driver to configure itself. + * This configuration structure is typically created by the tool-chain based + * on hardware build properties. + * + * The driver instance can be initialized in + * + * - XEmacPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddress): Uses a + * configuration structure provided by the caller. If running in a system + * with address translation, the provided virtual memory base address + * replaces the physical address present in the configuration structure. + * + * The device supports DMA only as current development plan. No FIFO mode is + * supported. The driver expects to start the DMA channels and expects that + * the user has set up the buffer descriptor lists. + * + * Interrupts and Asynchronous Callbacks + * + * The driver has no dependencies on the interrupt controller. When an + * interrupt occurs, the handler will perform a small amount of + * housekeeping work, determine the source of the interrupt, and call the + * appropriate callback function. All callbacks are registered by the user + * level application. + * + * Virtual Memory + * + * All virtual to physical memory mappings must occur prior to accessing the + * driver API. + * + * For DMA transactions, user buffers supplied to the driver must be in terms + * of their physical address. + * + * DMA + * + * The DMA engine uses buffer descriptors (BDs) to describe Ethernet frames. + * These BDs are typically chained together into a list the hardware follows + * when transferring data in and out of the packet buffers. Each BD describes + * a memory region containing either a full or partial Ethernet packet. + * + * Interrupt coalescing is not suppoted from this built-in DMA engine. + * + * This API requires the user to understand how the DMA operates. The + * following paragraphs provide some explanation, but the user is encouraged + * to read documentation in xemacps_bdring.h as well as study example code + * that accompanies this driver. + * + * The API is designed to get BDs to and from the DMA engine in the most + * efficient means possible. The first step is to establish a memory region + * to contain all BDs for a specific channel. This is done with + * XEmacPs_BdRingCreate(). This function sets up a BD ring that hardware will + * follow as BDs are processed. The ring will consist of a user defined number + * of BDs which will all be partially initialized. For example on the transmit + * channel, the driver will initialize all BDs' so that they are configured + * for transmit. The more fields that can be permanently setup at + * initialization, then the fewer accesses will be needed to each BD while + * the DMA engine is in operation resulting in better throughput and CPU + * utilization. The best case initialization would require the user to set + * only a frame buffer address and length prior to submitting the BD to the + * engine. + * + * BDs move through the engine with the help of functions + * XEmacPs_BdRingAlloc(), XEmacPs_BdRingToHw(), XEmacPs_BdRingFromHw(), + * and XEmacPs_BdRingFree(). + * All these functions handle BDs that are in place. That is, there are no + * copies of BDs kept anywhere and any BD the user interacts with is an actual + * BD from the same ring hardware accesses. + * + * BDs in the ring go through a series of states as follows: + * 1. Idle. The driver controls BDs in this state. + * 2. The user has data to transfer. XEmacPs_BdRingAlloc() is called to + * reserve BD(s). Once allocated, the user may setup the BD(s) with + * frame buffer address, length, and other attributes. The user controls + * BDs in this state. + * 3. The user submits BDs to the DMA engine with XEmacPs_BdRingToHw. BDs + * in this state are either waiting to be processed by hardware, are in + * process, or have been processed. The DMA engine controls BDs in this + * state. + * 4. Processed BDs are retrieved with XEmacEpv_BdRingFromHw() by the + * user. Once retrieved, the user can examine each BD for the outcome of + * the DMA transfer. The user controls BDs in this state. After examining + * the BDs the user calls XEmacPs_BdRingFree() which places the BDs back + * into state 1. + * + * Each of the four BD accessor functions operate on a set of BDs. A set is + * defined as a segment of the BD ring consisting of one or more BDs. The user + * views the set as a pointer to the first BD along with the number of BDs for + * that set. The set can be navigated by using macros XEmacPs_BdNext(). The + * user must exercise extreme caution when changing BDs in a set as there is + * nothing to prevent doing a mBdNext past the end of the set and modifying a + * BD out of bounds. + * + * XEmacPs_BdRingAlloc() + XEmacPs_BdRingToHw(), as well as + * XEmacPs_BdRingFromHw() + XEmacPs_BdRingFree() are designed to be used in + * tandem. The same BD set retrieved with BdRingAlloc should be the same one + * provided to hardware with BdRingToHw. Same goes with BdRingFromHw and + * BdRIngFree. + * + * Alignment & Data Cache Restrictions + * + * Due to the design of the hardware, all RX buffers, BDs need to be 4-byte + * aligned. Please reference xemacps_bd.h for cache related macros. + * + * DMA Tx: + * + * - If frame buffers exist in cached memory, then they must be flushed + * prior to committing them to hardware. + * + * DMA Rx: + * + * - If frame buffers exist in cached memory, then the cache must be + * invalidated for the memory region containing the frame prior to data + * access + * + * Both cache invalidate/flush are taken care of in driver code. + * + * Buffer Copying + * + * The driver is designed for a zero-copy buffer scheme. That is, the driver + * will not copy buffers. This avoids potential throughput bottlenecks within + * the driver. If byte copying is required, then the transfer will take longer + * to complete. + * + * Checksum Offloading + * + * The Embedded Processor Block Ethernet can be configured to perform IP, TCP + * and UDP checksum offloading in both receive and transmit directions. + * + * IP packets contain a 16-bit checksum field, which is the 16-bit 1s + * complement of the 1s complement sum of all 16-bit words in the header. + * TCP and UDP packets contain a 16-bit checksum field, which is the 16-bit + * 1s complement of the 1s complement sum of all 16-bit words in the header, + * the data and a conceptual pseudo header. + * + * To calculate these checksums in software requires each byte of the packet + * to be read. For TCP and UDP this can use a large amount of processing power. + * Offloading the checksum calculation to hardware can result in significant + * performance improvements. + * + * The transmit checksum offload is only available to use DMA in packet buffer + * mode. This is because the complete frame to be transmitted must be read + * into the packet buffer memory before the checksum can be calculated and + * written to the header at the beginning of the frame. + * + * For IP, TCP or UDP receive checksum offload to be useful, the operating + * system containing the protocol stack must be aware that this offload is + * available so that it can make use of the fact that the hardware has verified + * the checksum. + * + * When receive checksum offloading is enabled in the hardware, the IP header + * checksum is checked, where the packet meets the following criteria: + * + * 1. If present, the VLAN header must be four octets long and the CFI bit + * must not be set. + * 2. Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP + * encoding. + * 3. IP v4 packet. + * 4. IP header is of a valid length. + * 5. Good IP header checksum. + * 6. No IP fragmentation. + * 7. TCP or UDP packet. + * + * When an IP, TCP or UDP frame is received, the receive buffer descriptor + * gives an indication if the hardware was able to verify the checksums. + * There is also an indication if the frame had SNAP encapsulation. These + * indication bits will replace the type ID match indication bits when the + * receive checksum offload is enabled. + * + * If any of the checksums are verified incorrect by the hardware, the packet + * is discarded and the appropriate statistics counter incremented. + * + * PHY Interfaces + * + * RGMII 1.3 is the only interface supported. + * + * Asserts + * + * Asserts are used within all Xilinx drivers to enforce constraints on + * parameters. Asserts can be turned off on a system-wide basis by defining, + * at compile time, the NDEBUG identifier. By default, asserts are turned on + * and it is recommended that users leave asserts on during development. For + * deployment use -DNDEBUG compiler switch to remove assert code. + * + * @note + * + * Xilinx drivers are typically composed of two parts, one is the driver + * and the other is the adapter. The driver is independent of OS and processor + * and is intended to be highly portable. The adapter is OS-specific and + * facilitates communication between the driver and an OS. + * This driver is intended to be RTOS and processor independent. Any needs for + * dynamic memory management, threads or thread mutual exclusion, or cache + * control must be satisfied bythe layer above this driver. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Earlier it was checking for
+ *		       "BdLimit"(passed argument) number of BDs for finding out
+ *		       which BDs are successfully processed. Now one more check
+ *		       is added. It looks for BDs till the current BD pointer
+ *		       reaches HwTail. By doing this processing time is saved.
+ * 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+ *		       xemacps_bdring.c is modified. Now start of packet is
+ *		       searched for returning the number of BDs processed.
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *		       registers. Added a new API to set the bust length.
+ *		       Added some new hash-defines.
+ * 1.03a asa  01/23/12 Fix for CR #692702 which updates error handling for
+ *		       Rx errors. Under heavy Rx traffic, there will be a large
+ *		       number of errors related to receive buffer not available.
+ *		       Because of a HW bug (SI #692601), under such heavy errors,
+ *		       the Rx data path can become unresponsive. To reduce the
+ *		       probabilities for hitting this HW bug, the SW writes to
+ *		       bit 18 to flush a packet from Rx DPRAM immediately. The
+ *		       changes for it are done in the function
+ *		       XEmacPs_IntrHandler.
+ * 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+ *		       removed. It is expected that all BDs are allocated in
+ *		       from uncached area.
+ * 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+ *				to 0x1fff. This fixes the CR#744902.
+ *			  Made changes in example file xemacps_example.h to fix compilation
+ *			  issues with iarcc compiler.
+ * 2.0   adk  10/12/13 Updated as per the New Tcl API's
+ * 2.1   adk  11/08/14 Fixed the CR#811288. Changes are made in the driver tcl file.
+ * 2.1   bss  09/08/14 Modified driver tcl to fix CR#820349 to export phy
+ *		       address in xparameters.h when GMII to RGMII converter
+ *		       is present in hw.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification and 64-bit
+ *		       changes.
+ * 2.2   adk  29/10/14 Fixed CR#827686 when PCS/PMA core is configured with
+ *                    1000BASE-X mode export proper values to the xparameters.h
+ *                    file. Changes are made in the driver tcl file.
+ * 3.0   adk  08/1/15  Don't include gem in peripheral test when gem is
+ *                    configured with PCS/PMA Core. Changes are made in the
+ *		       test app tcl(CR:827686).
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   03/18/15 Added support for jumbo frames. Increase AHB burst.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ *                     Remove "used bit set" from TX error interrupt masks.
+ * 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+ *                     there is no error. CR# 869403
+ *            08/10/15 Update upper 32 bit tx and rx queue ptr registers.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ *
+ * + ****************************************************************************/ + +#ifndef XEMACPS_H /* prevent circular inclusions */ +#define XEMACPS_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files ********************************/ + +#include "xil_types.h" +#include "xil_assert.h" +#include "xstatus.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions ****************************/ + +/* + * Device information + */ +#define XEMACPS_DEVICE_NAME "xemacps" +#define XEMACPS_DEVICE_DESC "Xilinx PS 10/100/1000 MAC" + + +/** @name Configuration options + * + * Device configuration options. See the XEmacPs_SetOptions(), + * XEmacPs_ClearOptions() and XEmacPs_GetOptions() for information on how to + * use options. + * + * The default state of the options are noted and are what the device and + * driver will be set to after calling XEmacPs_Reset() or + * XEmacPs_Initialize(). + * + * @{ + */ + +#define XEMACPS_PROMISC_OPTION 0x00000001U +/**< Accept all incoming packets. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FRAME1536_OPTION 0x00000002U +/**< Frame larger than 1516 support for Tx & Rx. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_VLAN_OPTION 0x00000004U +/**< VLAN Rx & Tx frame support. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_FLOW_CONTROL_OPTION 0x00000010U +/**< Enable recognition of flow control frames on Rx + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_STRIP_OPTION 0x00000020U +/**< Strip FCS and PAD from incoming frames. Note: PAD from VLAN frames is not + * stripped. + * This option defaults to enabled (set) */ + +#define XEMACPS_FCS_INSERT_OPTION 0x00000040U +/**< Generate FCS field and add PAD automatically for outgoing frames. + * This option defaults to disabled (cleared) */ + +#define XEMACPS_LENTYPE_ERR_OPTION 0x00000080U +/**< Enable Length/Type error checking for incoming frames. When this option is + * set, the MAC will filter frames that have a mismatched type/length field + * and if XEMACPS_REPORT_RXERR_OPTION is set, the user is notified when these + * types of frames are encountered. When this option is cleared, the MAC will + * allow these types of frames to be received. + * + * This option defaults to disabled (cleared) */ + +#define XEMACPS_TRANSMITTER_ENABLE_OPTION 0x00000100U +/**< Enable the transmitter. + * This option defaults to enabled (set) */ + +#define XEMACPS_RECEIVER_ENABLE_OPTION 0x00000200U +/**< Enable the receiver + * This option defaults to enabled (set) */ + +#define XEMACPS_BROADCAST_OPTION 0x00000400U +/**< Allow reception of the broadcast address + * This option defaults to enabled (set) */ + +#define XEMACPS_MULTICAST_OPTION 0x00000800U +/**< Allows reception of multicast addresses programmed into hash + * This option defaults to disabled (clear) */ + +#define XEMACPS_RX_CHKSUM_ENABLE_OPTION 0x00001000U +/**< Enable the RX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_TX_CHKSUM_ENABLE_OPTION 0x00002000U +/**< Enable the TX checksum offload + * This option defaults to enabled (set) */ + +#define XEMACPS_JUMBO_ENABLE_OPTION 0x00004000U +#define XEMACPS_SGMII_ENABLE_OPTION 0x00008000U + +#define XEMACPS_DEFAULT_OPTIONS \ + ((u32)XEMACPS_FLOW_CONTROL_OPTION | \ + (u32)XEMACPS_FCS_INSERT_OPTION | \ + (u32)XEMACPS_FCS_STRIP_OPTION | \ + (u32)XEMACPS_BROADCAST_OPTION | \ + (u32)XEMACPS_LENTYPE_ERR_OPTION | \ + (u32)XEMACPS_TRANSMITTER_ENABLE_OPTION | \ + (u32)XEMACPS_RECEIVER_ENABLE_OPTION | \ + (u32)XEMACPS_RX_CHKSUM_ENABLE_OPTION | \ + (u32)XEMACPS_TX_CHKSUM_ENABLE_OPTION) + +/**< Default options set when device is initialized or reset */ +/*@}*/ + +/** @name Callback identifiers + * + * These constants are used as parameters to XEmacPs_SetHandler() + * @{ + */ +#define XEMACPS_HANDLER_DMASEND 1U +#define XEMACPS_HANDLER_DMARECV 2U +#define XEMACPS_HANDLER_ERROR 3U +/*@}*/ + +/* Constants to determine the configuration of the hardware device. They are + * used to allow the driver to verify it can operate with the hardware. + */ +#define XEMACPS_MDIO_DIV_DFT MDC_DIV_32 /**< Default MDIO clock divisor */ + +/* The next few constants help upper layers determine the size of memory + * pools used for Ethernet buffers and descriptor lists. + */ +#define XEMACPS_MAC_ADDR_SIZE 6U /* size of Ethernet header */ + +#define XEMACPS_MTU 1500U /* max MTU size of Ethernet frame */ +#define XEMACPS_MTU_JUMBO 10240U /* max MTU size of jumbo frame */ +#define XEMACPS_HDR_SIZE 14U /* size of Ethernet header */ +#define XEMACPS_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */ +#define XEMACPS_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */ +#define XEMACPS_MAX_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE (XEMACPS_MTU + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) +#define XEMACPS_MAX_VLAN_FRAME_SIZE_JUMBO (XEMACPS_MTU_JUMBO + XEMACPS_HDR_SIZE + \ + XEMACPS_HDR_VLAN_SIZE + XEMACPS_TRL_SIZE) + +/* DMACR Bust length hash defines */ + +#define XEMACPS_SINGLE_BURST 0x00000001 +#define XEMACPS_4BYTE_BURST 0x00000004 +#define XEMACPS_8BYTE_BURST 0x00000008 +#define XEMACPS_16BYTE_BURST 0x00000010 + + +/**************************** Type Definitions ******************************/ +/** @name Typedefs for callback functions + * + * These callbacks are invoked in interrupt context. + * @{ + */ +/** + * Callback invoked when frame(s) have been sent or received in interrupt + * driven DMA mode. To set the send callback, invoke XEmacPs_SetHandler(). + * + * @param CallBackRef is user data assigned when the callback was set. + * + * @note + * See xemacps_hw.h for bitmasks definitions and the device hardware spec for + * further information on their meaning. + * + */ +typedef void (*XEmacPs_Handler) (void *CallBackRef); + +/** + * Callback when an asynchronous error occurs. To set this callback, invoke + * XEmacPs_SetHandler() with XEMACPS_HANDLER_ERROR in the HandlerType + * paramter. + * + * @param CallBackRef is user data assigned when the callback was set. + * @param Direction defines either receive or transmit error(s) has occurred. + * @param ErrorWord definition varies with Direction + * + */ +typedef void (*XEmacPs_ErrHandler) (void *CallBackRef, u8 Direction, + u32 ErrorWord); + +/*@}*/ + +/** + * This typedef contains configuration information for a device. + */ +typedef struct { + u16 DeviceId; /**< Unique ID of device */ + UINTPTR BaseAddress;/**< Physical base address of IPIF registers */ +} XEmacPs_Config; + + +/** + * The XEmacPs driver instance data. The user is required to allocate a + * structure of this type for every XEmacPs device in the system. A pointer + * to a structure of this type is then passed to the driver API functions. + */ +typedef struct XEmacPs_Instance { + XEmacPs_Config Config; /* Hardware configuration */ + u32 IsStarted; /* Device is currently started */ + u32 IsReady; /* Device is initialized and ready */ + u32 Options; /* Current options word */ + + XEmacPs_BdRing TxBdRing; /* Transmit BD ring */ + XEmacPs_BdRing RxBdRing; /* Receive BD ring */ + + XEmacPs_Handler SendHandler; + XEmacPs_Handler RecvHandler; + void *SendRef; + void *RecvRef; + + XEmacPs_ErrHandler ErrorHandler; + void *ErrorRef; + u32 Version; + u32 RxBufMask; + u32 MaxMtuSize; + u32 MaxFrameSize; + u32 MaxVlanFrameSize; + +} XEmacPs; + + +/***************** Macros (Inline Functions) Definitions ********************/ + +/****************************************************************************/ +/** +* Retrieve the Tx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return TxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetTxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetTxRing(InstancePtr) ((InstancePtr)->TxBdRing) + +/****************************************************************************/ +/** +* Retrieve the Rx ring object. This object can be used in the various Ring +* API functions. +* +* @param InstancePtr is the DMA channel to operate on. +* +* @return RxBdRing attribute +* +* @note +* C-style signature: +* XEmacPs_BdRing XEmacPs_GetRxRing(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_GetRxRing(InstancePtr) ((InstancePtr)->RxBdRing) + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntEnable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntEnable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IER_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntDisable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_IDR_OFFSET, \ + ((Mask) & XEMACPS_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Enable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to enable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntQ1Enable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Enable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IER_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* Disable interrupts specified in Mask. The corresponding interrupt for +* each bit set to 1 in Mask, will be enabled. +* +* @param InstancePtr is a pointer to the instance to be worked on. +* @param Mask contains a bit mask of interrupts to disable. The mask can +* be formed using a set of bitwise or'd values. +* +* @note +* The state of the transmitter and receiver are not modified by this function. +* C-style signature +* void XEmacPs_IntDisable(XEmacPs *InstancePtr, u32 Mask) +* +*****************************************************************************/ +#define XEmacPs_IntQ1Disable(InstancePtr, Mask) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_INTQ1_IDR_OFFSET, \ + ((Mask) & XEMACPS_INTQ1_IXR_ALL_MASK)); + +/****************************************************************************/ +/** +* +* This macro triggers trasmit circuit to send data currently in TX buffer(s). +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* @note +* +* Signature: void XEmacPs_Transmit(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_Transmit(InstancePtr) \ + XEmacPs_WriteReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET, \ + (XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCTRL_OFFSET) | XEMACPS_NWCTRL_STARTTX_MASK)) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the receive channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsRxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsRxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_NWCFG_OFFSET) & XEMACPS_NWCFG_RXCHKSUMEN_MASK) != 0U \ + ? TRUE : FALSE) + +/****************************************************************************/ +/** +* +* This macro determines if the device is configured with checksum offloading +* on the transmit channel +* +* @param InstancePtr is a pointer to the XEmacPs instance to be worked on. +* +* @return +* +* Boolean TRUE if the device is configured with checksum offloading, or +* FALSE otherwise. +* +* @note +* +* Signature: u32 XEmacPs_IsTxCsum(XEmacPs *InstancePtr) +* +*****************************************************************************/ +#define XEmacPs_IsTxCsum(InstancePtr) \ + ((XEmacPs_ReadReg((InstancePtr)->Config.BaseAddress, \ + XEMACPS_DMACR_OFFSET) & XEMACPS_DMACR_TCPCKSUM_MASK) != 0U \ + ? TRUE : FALSE) + +/************************** Function Prototypes *****************************/ + +/* + * Initialization functions in xemacps.c + */ +LONG XEmacPs_CfgInitialize(XEmacPs *InstancePtr, XEmacPs_Config *CfgPtr, + UINTPTR EffectiveAddress); +void XEmacPs_Start(XEmacPs *InstancePtr); +void XEmacPs_Stop(XEmacPs *InstancePtr); +void XEmacPs_Reset(XEmacPs *InstancePtr); +void XEmacPs_SetQueuePtr(XEmacPs *InstancePtr, UINTPTR QPtr, u8 QueueNum, + u16 Direction); + +/* + * Lookup configuration in xemacps_sinit.c + */ +XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId); + +/* + * Interrupt-related functions in xemacps_intr.c + * DMA only and FIFO is not supported. This DMA does not support coalescing. + */ +LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType, + void *FuncPointer, void *CallBackRef); +void XEmacPs_IntrHandler(void *XEmacPsPtr); + +/* + * MAC configuration/control functions in XEmacPs_control.c + */ +LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options); +LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options); +u32 XEmacPs_GetOptions(XEmacPs *InstancePtr); + +LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); +LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index); + +LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr); +void XEmacPs_ClearHash(XEmacPs *InstancePtr); +void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr); + +void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, + XEmacPs_MdcDiv Divisor); +void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed); +u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr); +LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 *PhyDataPtr); +LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress, + u32 RegisterNum, u16 PhyData); +LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index); + +LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr); +void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength); + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bd.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bd.h new file mode 100644 index 000000000..52c5f7e7e --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bd.h @@ -0,0 +1,804 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** + * + * @file xemacps_bd.h +* @addtogroup emacps_v3_1 +* @{ + * + * This header provides operations to manage buffer descriptors in support + * of scatter-gather DMA. + * + * The API exported by this header defines abstracted macros that allow the + * user to read/write specific BD fields. + * + * Buffer Descriptors + * + * A buffer descriptor (BD) defines a DMA transaction. The macros defined by + * this header file allow access to most fields within a BD to tailor a DMA + * transaction according to user and hardware requirements. See the hardware + * IP DMA spec for more information on BD fields and how they affect transfers. + * + * The XEmacPs_Bd structure defines a BD. The organization of this structure + * is driven mainly by the hardware for use in scatter-gather DMA transfers. + * + * Performance + * + * Limiting I/O to BDs can improve overall performance of the DMA channel. + * + * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale MP GEM specification
+ *                     and 64-bit changes.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ *                     Disable extended mode. Perform all 64 bit changes under
+ *                     check for arch64.
+ * 3.2   hk   11/18/15 Change BD typedef and number of words.
+ *
+ *
+ * + * *************************************************************************** + */ + +#ifndef XEMACPS_BD_H /* prevent circular inclusions */ +#define XEMACPS_BD_H /* by using protection macros */ + +#ifdef __cplusplus +extern "C" { +#endif + +/***************************** Include Files *********************************/ + +#include +#include "xil_types.h" +#include "xil_assert.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ +#ifdef __aarch64__ +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 64U +#define XEMACPS_BD_NUM_WORDS 4U +#else +/* Minimum BD alignment */ +#define XEMACPS_DMABD_MINIMUM_ALIGNMENT 4U +#define XEMACPS_BD_NUM_WORDS 2U +#endif + +/** + * The XEmacPs_Bd is the type for buffer descriptors (BDs). + */ +typedef u32 XEmacPs_Bd[XEMACPS_BD_NUM_WORDS]; + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*****************************************************************************/ +/** + * Zero out BD fields + * + * @param BdPtr is the BD pointer to operate on + * + * @return Nothing + * + * @note + * C-style signature: + * void XEmacPs_BdClear(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClear(BdPtr) \ + memset((BdPtr), 0, sizeof(XEmacPs_Bd)) + +/****************************************************************************/ +/** +* +* Read the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to read +* @param Offset is the word offset to be read +* +* @return The 32-bit value of the field +* +* @note +* C-style signature: +* u32 XEmacPs_BdRead(UINTPTR BaseAddress, UINTPTR Offset) +* +*****************************************************************************/ +#define XEmacPs_BdRead(BaseAddress, Offset) \ + (*(u32 *)((UINTPTR)((void*)(BaseAddress)) + (u32)(Offset))) + +/****************************************************************************/ +/** +* +* Write the given Buffer Descriptor word. +* +* @param BaseAddress is the base address of the BD to write +* @param Offset is the word offset to be written +* @param Data is the 32-bit value to write to the field +* +* @return None. +* +* @note +* C-style signature: +* void XEmacPs_BdWrite(UINTPTR BaseAddress, UINTPTR Offset, UINTPTR Data) +* +*****************************************************************************/ +#define XEmacPs_BdWrite(BaseAddress, Offset, Data) \ + (*(u32 *)((UINTPTR)(void*)(BaseAddress) + (u32)(Offset)) = (u32)(Data)) + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : + * + * C-style signature: + * void XEmacPs_BdSetAddressTx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + (u32)((Addr) & ULONG64_LO_MASK)); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressTx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, (u32)(Addr)) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Address field (word 0). + * + * @param BdPtr is the BD pointer to operate on + * @param Addr is the value to write to BD's status field. + * + * @note : Due to some bits are mixed within recevie BD's address field, + * read-modify-write is performed. + * + * C-style signature: + * void XEmacPs_BdSetAddressRx(XEmacPs_Bd* BdPtr, UINTPTR Addr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | ((u32)((Addr) & ULONG64_LO_MASK)))); \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET, \ + (u32)(((Addr) & ULONG64_HI_MASK) >> 32U)); +#else +#define XEmacPs_BdSetAddressRx(BdPtr, Addr) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_ADD_MASK) | (UINTPTR)(Addr))) +#endif + +/*****************************************************************************/ +/** + * Set the BD's Status field (word 1). + * + * @param BdPtr is the BD pointer to operate on + * @param Data is the value to write to BD's status field. + * + * @note + * C-style signature: + * void XEmacPs_BdSetStatus(XEmacPs_Bd* BdPtr, UINTPTR Data) + * + *****************************************************************************/ +#define XEmacPs_BdSetStatus(BdPtr, Data) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | (Data)) + + +/*****************************************************************************/ +/** + * Retrieve the BD's Packet DMA transfer status word (word 1). + * + * @param BdPtr is the BD pointer to operate on + * + * @return Status word + * + * @note + * C-style signature: + * u32 XEmacPs_BdGetStatus(XEmacPs_Bd* BdPtr) + * + * Due to the BD bit layout differences in transmit and receive. User's + * caution is required. + *****************************************************************************/ +#define XEmacPs_BdGetStatus(BdPtr) \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) + + +/*****************************************************************************/ +/** + * Get the address (bits 0..31) of the BD's buffer address (word 0) + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetBufAddr(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#ifdef __aarch64__ +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_HI_OFFSET)) << 32U) +#else +#define XEmacPs_BdGetBufAddr(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET)) +#endif + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + + +/*****************************************************************************/ +/** + * Set transfer length in bytes for the given BD. The length must be set each + * time a BD is submitted to hardware. + * + * @param BdPtr is the BD pointer to operate on + * @param LenBytes is the number of bytes to transfer. + * + * @note + * C-style signature: + * void XEmacPs_BdSetLength(XEmacPs_Bd* BdPtr, u32 LenBytes) + * + *****************************************************************************/ +#define XEmacPs_BdSetLength(BdPtr, LenBytes) \ + XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LEN_MASK) | (LenBytes))) + + +/*****************************************************************************/ +/** + * Retrieve the BD length field. + * + * For Tx channels, the returned value is the same as that written with + * XEmacPs_BdSetLength(). + * + * For Rx channels, the returned value is the size of the received packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetLength(XEmacPs_Bd* BdPtr) + * XEAMCPS_RXBUF_LEN_MASK is same as XEMACPS_TXBUF_LEN_MASK. + * + *****************************************************************************/ +#define XEmacPs_BdGetLength(BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_LEN_MASK) + +/*****************************************************************************/ +/** + * Retrieve the RX frame size. + * + * The returned value is the size of the received packet. + * This API supports jumbo frame sizes if enabled. + * + * @param BdPtr is the BD pointer to operate on + * + * @return Length field processed by hardware or set by + * XEmacPs_BdSetLength(). + * + * @note + * C-style signature: + * UINTPTR XEmacPs_GetRxFrameSize(XEmacPs* InstancePtr, XEmacPs_Bd* BdPtr) + * RxBufMask is dependent on whether jumbo is enabled or not. + * + *****************************************************************************/ +#define XEmacPs_GetRxFrameSize(InstancePtr, BdPtr) \ + (XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + (InstancePtr)->RxBufMask) + +/*****************************************************************************/ +/** + * Test whether the given BD has been marked as the last BD of a packet. + * + * @param BdPtr is the BD pointer to operate on + * + * @return TRUE if BD represents the "Last" BD of a packet, FALSE otherwise + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsLast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the given transmit BD marks the end of the current + * packet to be processed. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Tell the DMA engine that the current packet does not end with the given + * BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearLast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearLast(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_LAST_MASK)) + + +/*****************************************************************************/ +/** + * Set this bit to mark the last descriptor in the receive buffer descriptor + * list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetRxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) | \ + XEMACPS_RXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the receive BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdIsRxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit to mark the last descriptor in the transmit buffer + * descriptor list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +/*#define XEmacPs_BdSetTxWrap(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_WRAP_MASK)) +*/ + +/*****************************************************************************/ +/** + * Determine the wrap bit of the transmit BD which indicates end of the + * BD list. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * u8 XEmacPs_BdGetTxWrap(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxWrap(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_WRAP_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/* + * Must clear this bit to enable the MAC to write data to the receive + * buffer. Hardware sets this bit once it has successfully written a frame to + * memory. Once set, software has to clear the bit before the buffer can be + * used again. This macro clear the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearRxNew(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_ADDR_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + ~XEMACPS_RXBUF_NEW_MASK)) + + +/*****************************************************************************/ +/** + * Determine the new bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxNew(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxNew(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_ADDR_OFFSET) & \ + XEMACPS_RXBUF_NEW_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Software sets this bit to disable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro sets this bit of transmit BD to avoid + * confusion. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdSetTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Software clears this bit to enable the buffer to be read by the hardware. + * Hardware sets this bit for the first buffer of a frame once it has been + * successfully transmitted. This macro clears this bit of transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * void XEmacPs_BdClearTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxUsed(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_USED_MASK)) + + +/*****************************************************************************/ +/** + * Determine the used bit of the transmit BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUsed(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUsed(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_USED_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to too many retries. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxRetry(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxRetry(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_RETRY_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to data can not be + * feteched in time or buffers are exhausted. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxUrun(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxUrun(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_URUN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if a frame fails to be transmitted due to buffer is exhausted + * mid-frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsTxExh(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsTxExh(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_TXBUF_EXH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Sets this bit, no CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdSetTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdSetTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) | \ + XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Clear this bit, CRC will be appended to the current frame. This control + * bit must be set for the first buffer in a frame and will be ignored for + * the subsequent buffers of a frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * This bit must be clear when using the transmit checksum generation offload, + * otherwise checksum generation and substitution will not occur. + * + * C-style signature: + * UINTPTR XEmacPs_BdClearTxNoCRC(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdClearTxNoCRC(BdPtr) \ + (XEmacPs_BdWrite((BdPtr), XEMACPS_BD_STAT_OFFSET, \ + XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + ~XEMACPS_TXBUF_NOCRC_MASK)) + + +/*****************************************************************************/ +/** + * Determine the broadcast bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxBcast(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxBcast(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_BCAST_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the multicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxMultiHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxMultiHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_MULTIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the unicast hash bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxUniHash(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxUniHash(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_UNIHASH_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame is a VLAN Tagged frame. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxVlan(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxVlan(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_VLAN_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame has Type ID of 8100h and null VLAN + * identifier(Priority tag). + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxPri(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxPri(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_PRI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine if the received frame's Concatenation Format Indicator (CFI) of + * the frames VLANTCI field was set. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdIsRxCFI(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxCFI(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_CFI_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the End Of Frame (EOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxEOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxEOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_EOF_MASK)!=0U ? TRUE : FALSE) + + +/*****************************************************************************/ +/** + * Determine the Start Of Frame (SOF) bit of the receive BD. + * + * @param BdPtr is the BD pointer to operate on + * + * @note + * C-style signature: + * UINTPTR XEmacPs_BdGetRxSOF(XEmacPs_Bd* BdPtr) + * + *****************************************************************************/ +#define XEmacPs_BdIsRxSOF(BdPtr) \ + ((XEmacPs_BdRead((BdPtr), XEMACPS_BD_STAT_OFFSET) & \ + XEMACPS_RXBUF_SOF_MASK)!=0U ? TRUE : FALSE) + + +/************************** Function Prototypes ******************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* end of protection macro */ +/** @} */ diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.c new file mode 100644 index 000000000..d837e1df1 --- /dev/null +++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.c @@ -0,0 +1,1075 @@ +/****************************************************************************** +* +* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* Use of the Software is limited solely to applications: +* (a) running on a Xilinx device, or +* (b) that interact with a Xilinx device through a bus or interconnect. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, +* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF +* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. +* +* Except as contained in this notice, the name of the Xilinx shall not be used +* in advertising or otherwise to promote the sale, use or other dealings in +* this Software without prior written authorization from Xilinx. +* +******************************************************************************/ +/*****************************************************************************/ +/** +* +* @file xemacps_bdring.c +* @addtogroup emacps_v3_1 +* @{ +* +* This file implements buffer descriptor ring related functions. +* +* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.00a asa  11/21/11 The function XEmacPs_BdRingFromHwTx is modified.
+*		      Earlier it used to search in "BdLimit" number of BDs to
+*		      know which BDs are processed. Now one more check is
+*		      added. It looks for BDs till the current BD pointer
+*		      reaches HwTail. By doing this processing time is saved.
+* 1.00a asa  01/24/12 The function XEmacPs_BdRingFromHwTx in file
+*		      xemacps_bdring.c is modified. Now start of packet is
+*		      searched for returning the number of BDs processed.
+* 1.05a asa  09/23/13 Cache operations on BDs are not required and hence
+*		      removed. It is expected that all BDs are allocated in
+*		      from uncached area. Fix for CR #663885.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+*
+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xstatus.h" +#include "xil_cache.h" +#include "xemacps_hw.h" +#include "xemacps_bd.h" +#include "xemacps_bdring.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + +/**************************************************************************** + * Compute the virtual address of a descriptor from its physical address + * + * @param BdPtr is the physical address of the BD + * + * @returns Virtual address of BdPtr + * + * @note Assume BdPtr is always a valid BD in the ring + ****************************************************************************/ +#define XEMACPS_PHYS_TO_VIRT(BdPtr) \ + ((UINTPTR)(BdPtr) + (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) + +/**************************************************************************** + * Compute the physical address of a descriptor from its virtual address + * + * @param BdPtr is the physical address of the BD + * + * @returns Physical address of BdPtr + * + * @note Assume BdPtr is always a valid BD in the ring + ****************************************************************************/ +#define XEMACPS_VIRT_TO_PHYS(BdPtr) \ + ((UINTPTR)(BdPtr) - (RingPtr->BaseBdAddr - RingPtr->PhysBaseAddr)) + +/**************************************************************************** + * Move the BdPtr argument ahead an arbitrary number of BDs wrapping around + * to the beginning of the ring if needed. + * + * We know if a wrapaound should occur if the new BdPtr is greater than + * the high address in the ring OR if the new BdPtr crosses over the + * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not + * allow a BD space to span this boundary. + * + * @param RingPtr is the ring BdPtr appears in + * @param BdPtr on input is the starting BD position and on output is the + * final BD position + * @param NumBd is the number of BD spaces to increment + * + ****************************************************************************/ +#define XEMACPS_RING_SEEKAHEAD(RingPtr, BdPtr, NumBd) \ + { \ + UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \ + \ + Addr += ((RingPtr)->Separation * (NumBd)); \ + if ((Addr > (RingPtr)->HighBdAddr) || ((UINTPTR)(void *)(BdPtr) > Addr)) \ + { \ + Addr -= (RingPtr)->Length; \ + } \ + \ + (BdPtr) = (XEmacPs_Bd*)(void *)Addr; \ + } + +/**************************************************************************** + * Move the BdPtr argument backwards an arbitrary number of BDs wrapping + * around to the end of the ring if needed. + * + * We know if a wrapaound should occur if the new BdPtr is less than + * the base address in the ring OR if the new BdPtr crosses over the + * 0xFFFFFFFF to 0 boundary. The latter test is a valid one since we do not + * allow a BD space to span this boundary. + * + * @param RingPtr is the ring BdPtr appears in + * @param BdPtr on input is the starting BD position and on output is the + * final BD position + * @param NumBd is the number of BD spaces to increment + * + ****************************************************************************/ +#define XEMACPS_RING_SEEKBACK(RingPtr, BdPtr, NumBd) \ + { \ + UINTPTR Addr = (UINTPTR)(void *)(BdPtr); \ + \ + Addr -= ((RingPtr)->Separation * (NumBd)); \ + if ((Addr < (RingPtr)->BaseBdAddr) || ((UINTPTR)(void*)(BdPtr) < Addr)) \ + { \ + Addr += (RingPtr)->Length; \ + } \ + \ + (BdPtr) = (XEmacPs_Bd*)(void*)Addr; \ + } + + +/************************** Function Prototypes ******************************/ + +static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr); +static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr); + +/************************** Variable Definitions *****************************/ + +/*****************************************************************************/ +/** + * Using a memory segment allocated by the caller, create and setup the BD list + * for the given DMA channel. + * + * @param RingPtr is the instance to be worked on. + * @param PhysAddr is the physical base address of user memory region. + * @param VirtAddr is the virtual base address of the user memory region. If + * address translation is not being utilized, then VirtAddr should be + * equivalent to PhysAddr. + * @param Alignment governs the byte alignment of individual BDs. This function + * will enforce a minimum alignment of 4 bytes with no maximum as long + * as it is specified as a power of 2. + * @param BdCount is the number of BDs to setup in the user memory region. It + * is assumed the region is large enough to contain the BDs. + * + * @return + * + * - XST_SUCCESS if initialization was successful + * - XST_NO_FEATURE if the provided instance is a non DMA type + * channel. + * - XST_INVALID_PARAM under any of the following conditions: + * 1) PhysAddr and/or VirtAddr are not aligned to the given Alignment + * parameter. + * 2) Alignment parameter does not meet minimum requirements or is not a + * power of 2 value. + * 3) BdCount is 0. + * - XST_DMA_SG_LIST_ERROR if the memory segment containing the list spans + * over address 0x00000000 in virtual address space. + * + * @note + * Make sure to pass in the right alignment value. + *****************************************************************************/ +LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr, + UINTPTR VirtAddr, u32 Alignment, u32 BdCount) +{ + u32 i; + UINTPTR BdVirtAddr; + UINTPTR BdPhyAddr; + UINTPTR VirtAddrLoc = VirtAddr; + + /* In case there is a failure prior to creating list, make sure the + * following attributes are 0 to prevent calls to other functions + * from doing anything. + */ + RingPtr->AllCnt = 0U; + RingPtr->FreeCnt = 0U; + RingPtr->HwCnt = 0U; + RingPtr->PreCnt = 0U; + RingPtr->PostCnt = 0U; + + /* Make sure Alignment parameter meets minimum requirements */ + if (Alignment < (u32)XEMACPS_DMABD_MINIMUM_ALIGNMENT) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Make sure Alignment is a power of 2 */ + if (((Alignment - 0x00000001U) & Alignment)!=0x00000000U) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Make sure PhysAddr and VirtAddr are on same Alignment */ + if (((PhysAddr % Alignment)!=(u32)0) || ((VirtAddrLoc % Alignment)!=(u32)0)) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Is BdCount reasonable? */ + if (BdCount == 0x00000000U) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Figure out how many bytes will be between the start of adjacent BDs */ + RingPtr->Separation = ((u32)sizeof(XEmacPs_Bd)); + + /* Must make sure the ring doesn't span address 0x00000000. If it does, + * then the next/prev BD traversal macros will fail. + */ + if (VirtAddrLoc > ((VirtAddrLoc + (RingPtr->Separation * BdCount)) - (u32)1)) { + return (LONG)(XST_DMA_SG_LIST_ERROR); + } + + /* Initial ring setup: + * - Clear the entire space + * - Setup each BD's BDA field with the physical address of the next BD + */ + (void)memset((void *) VirtAddrLoc, 0, (RingPtr->Separation * BdCount)); + + BdVirtAddr = VirtAddrLoc; + BdPhyAddr = PhysAddr + RingPtr->Separation; + for (i = 1U; i < BdCount; i++) { + BdVirtAddr += RingPtr->Separation; + BdPhyAddr += RingPtr->Separation; + } + + /* Setup and initialize pointers and counters */ + RingPtr->RunState = (u32)(XST_DMA_SG_IS_STOPPED); + RingPtr->BaseBdAddr = VirtAddrLoc; + RingPtr->PhysBaseAddr = PhysAddr; + RingPtr->HighBdAddr = BdVirtAddr; + RingPtr->Length = + ((RingPtr->HighBdAddr - RingPtr->BaseBdAddr) + RingPtr->Separation); + RingPtr->AllCnt = (u32)BdCount; + RingPtr->FreeCnt = (u32)BdCount; + RingPtr->FreeHead = (XEmacPs_Bd *)(void *)VirtAddrLoc; + RingPtr->PreHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->HwHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->HwTail = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->PostHead = (XEmacPs_Bd *)VirtAddrLoc; + RingPtr->BdaRestart = (XEmacPs_Bd *)(void *)PhysAddr; + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** + * Clone the given BD into every BD in the list. + * every field of the source BD is replicated in every BD of the list. + * + * This function can be called only when all BDs are in the free group such as + * they are immediately after initialization with XEmacPs_BdRingCreate(). + * This prevents modification of BDs while they are in use by hardware or the + * user. + * + * @param RingPtr is the pointer of BD ring instance to be worked on. + * @param SrcBdPtr is the source BD template to be cloned into the list. This + * BD will be modified. + * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates + * which direction. + * + * @return + * - XST_SUCCESS if the list was modified. + * - XST_DMA_SG_NO_LIST if a list has not been created. + * - XST_DMA_SG_LIST_ERROR if some of the BDs in this channel are under + * hardware or user control. + * - XST_DEVICE_IS_STARTED if the DMA channel has not been stopped. + * + *****************************************************************************/ +LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr, + u8 Direction) +{ + u32 i; + UINTPTR CurBd; + + /* Can't do this function if there isn't a ring */ + if (RingPtr->AllCnt == 0x00000000U) { + return (LONG)(XST_DMA_SG_NO_LIST); + } + + /* Can't do this function with the channel running */ + if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) { + return (LONG)(XST_DEVICE_IS_STARTED); + } + + /* Can't do this function with some of the BDs in use */ + if (RingPtr->FreeCnt != RingPtr->AllCnt) { + return (LONG)(XST_DMA_SG_LIST_ERROR); + } + + if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) { + return (LONG)(XST_INVALID_PARAM); + } + + /* Starting from the top of the ring, save BD.Next, overwrite the entire + * BD with the template, then restore BD.Next + */ + CurBd = RingPtr->BaseBdAddr; + for (i = 0U; i < RingPtr->AllCnt; i++) { + memcpy((void *)CurBd, SrcBdPtr, sizeof(XEmacPs_Bd)); + CurBd += RingPtr->Separation; + } + + CurBd -= RingPtr->Separation; + + if (Direction == XEMACPS_RECV) { + XEmacPs_BdSetRxWrap(CurBd); + } + else { + XEmacPs_BdSetTxWrap(CurBd); + } + + return (LONG)(XST_SUCCESS); +} + + +/*****************************************************************************/ +/** + * Reserve locations in the BD list. The set of returned BDs may be modified + * in preparation for future DMA transaction(s). Once the BDs are ready to be + * submitted to hardware, the user must call XEmacPs_BdRingToHw() in the same + * order which they were allocated here. Example: + * + * 
+ *        NumBd = 2,
+ *        Status = XEmacPs_BdRingAlloc(MyRingPtr, NumBd, &MyBdSet),
+ *
+ *        if (Status != XST_SUCCESS)
+ *        {
+ *            *Not enough BDs available for the request*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be allocated and given to hardware in the correct sequence:
+ * 
+ *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingAlloc(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingToHw(MyRingPtr, NumBd1, MySet1),
+ * 

+ *
+ * Use the API defined in xemacps_bd.h to modify individual BDs. Traversal
+ * of the BD set can be done using XEmacPs_BdRingNext() and
+ * XEmacPs_BdRingPrev().
+ *
+ * @param RingPtr is a pointer to the BD ring instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the requested number of BDs was returned in the BdSetPtr
+ *     parameter.
+ *   - XST_FAILURE if there were not enough free BDs to satisfy the request.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ * @note Do not modify more BDs than the number requested with the NumBd
+ *       parameter. Doing so will lead to data corruption and system
+ *       instability.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr)
+{
+	LONG Status;
+	/* Enough free BDs available for the request? */
+	if (RingPtr->FreeCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead forward */
+	*BdSetPtr = RingPtr->FreeHead;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->FreeHead, NumBd);
+	RingPtr->FreeCnt -= NumBd;
+	RingPtr->PreCnt += NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Fully or partially undo an XEmacPs_BdRingAlloc() operation. Use this
+ * function if all the BDs allocated by XEmacPs_BdRingAlloc() could not be
+ * transferred to hardware with XEmacPs_BdRingToHw().
+ *
+ * This function helps out in situations when an unrelated error occurs after
+ * BDs have been allocated but before they have been given to hardware.
+ * An example of this type of error would be an OS running out of resources.
+ *
+ * This function is not the same as XEmacPs_BdRingFree(). The Free function
+ * returns BDs to the free list after they have been processed by hardware,
+ * while UnAlloc returns them before being processed by hardware.
+ *
+ * There are two scenarios where this function can be used. Full UnAlloc or
+ * Partial UnAlloc. A Full UnAlloc means all the BDs Alloc'd will be returned:
+ *
+ * 
+ *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *        ...
+ *    if (Error)
+ *    {
+ *        Status = XEmacPs_BdRingUnAlloc(MyRingPtr, 10, &BdPtr),
+ *    }
+ * 

+ *
+ * A partial UnAlloc means some of the BDs Alloc'd will be returned:
+ *
+ * 
+ *    Status = XEmacPs_BdRingAlloc(MyRingPtr, 10, &BdPtr),
+ *    BdsLeft = 10,
+ *    CurBdPtr = BdPtr,
+ *
+ *    while (BdsLeft)
+ *    {
+ *       if (Error)
+ *       {
+ *          Status = XEmacPs_BdRingUnAlloc(MyRingPtr, BdsLeft, CurBdPtr),
+ *       }
+ *
+ *       CurBdPtr = XEmacPs_BdRingNext(MyRingPtr, CurBdPtr),
+ *       BdsLeft--,
+ *    }
+ * 

+ *
+ * A partial UnAlloc must include the last BD in the list that was Alloc'd.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to allocate
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for modification.
+ *
+ * @return
+ *   - XST_SUCCESS if the BDs were unallocated.
+ *   - XST_FAILURE if NumBd parameter was greater that the number of BDs in
+ *     the preprocessing state.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	(void *)BdSetPtr;
+	Xil_AssertNonvoid(RingPtr != NULL);
+	Xil_AssertNonvoid(BdSetPtr != NULL);
+
+	/* Enough BDs in the free state for the request? */
+	if (RingPtr->PreCnt < NumBd) {
+		Status = (LONG)(XST_FAILURE);
+	} else {
+	/* Set the return argument and move FreeHead backward */
+		XEMACPS_RING_SEEKBACK(RingPtr, (RingPtr->FreeHead), NumBd);
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PreCnt -= NumBd;
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Enqueue a set of BDs to hardware that were previously allocated by
+ * XEmacPs_BdRingAlloc(). Once this function returns, the argument BD set goes
+ * under hardware control. Any changes made to these BDs after this point will
+ * corrupt the BD list leading to data corruption and system instability.
+ *
+ * The set will be rejected if the last BD of the set does not mark the end of
+ * a packet (see XEmacPs_BdSetLast()).
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs in the set.
+ * @param BdSetPtr is the first BD of the set to commit to hardware.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was accepted and enqueued to hardware.
+ *   - XST_FAILURE if the set of BDs was rejected because the last BD of the set
+ *     did not have its "last" bit set.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingAlloc().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 i;
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingAlloc() */
+	if ((RingPtr->PreCnt < NumBd) || (RingPtr->PreHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	CurBdPtr = BdSetPtr;
+			for (i = 0U; i < NumBd; i++) {
+				CurBdPtr = (XEmacPs_Bd *)((void *)XEmacPs_BdRingNext(RingPtr, CurBdPtr));
+	}
+	/* Adjust ring pointers & counters */
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PreHead, NumBd);
+	RingPtr->PreCnt -= NumBd;
+	RingPtr->HwTail = CurBdPtr;
+	RingPtr->HwCnt += NumBd;
+
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * 
+ *        NumBd = XEmacPs_BdRingFromHwTx(MyRingPtr, MaxBd, &MyBdSet),
+ *        if (NumBd == 0)
+ *        {
+ *           * hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * 
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwTx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * 

+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Sop = 0U;
+	u32 Status;
+	u32 BdLimitLoc = BdLimit;
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+		if (BdLimitLoc > RingPtr->HwCnt){
+			BdLimitLoc = RingPtr->HwCnt;
+	}
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has not completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+		while (BdCount < BdLimitLoc) {
+		/* Read the status */
+			if(CurBdPtr != NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+
+			if ((Sop == 0x00000000U) && ((BdStr & XEMACPS_TXBUF_USED_MASK)!=0x00000000U)){
+				Sop = 1U;
+			}
+			if (Sop == 0x00000001U) {
+			BdCount++;
+			BdPartialCount++;
+		}
+
+		/* hardware has processed this BD so check the "last" bit.
+		 * If it is clear, then there are more BDs for the current
+		 * packet. Keep a count of these partial packet BDs.
+		 */
+			if ((Sop == 0x00000001U) && ((BdStr & XEMACPS_TXBUF_LAST_MASK)!=0x00000000U)) {
+				Sop = 0U;
+				BdPartialCount = 0U;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+        BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+		} else {
+			*BdSetPtr = NULL;
+			Status = 0U;
+	}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Returns a set of BD(s) that have been processed by hardware. The returned
+ * BDs may be examined to determine the outcome of the DMA transaction(s).
+ * Once the BDs have been examined, the user must call XEmacPs_BdRingFree()
+ * in the same order which they were retrieved here. Example:
+ *
+ * 
+ *        NumBd = XEmacPs_BdRingFromHwRx(MyRingPtr, MaxBd, &MyBdSet),
+ *
+ *        if (NumBd == 0)
+ *        {
+ *           *hardware has nothing ready for us yet*
+ *        }
+ *
+ *        CurBd = MyBdSet,
+ *        for (i=0; i
+ *
+ * A more advanced use of this function may allocate multiple sets of BDs.
+ * They must be retrieved from hardware and freed in the correct sequence:
+ * 
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *
+ *        * Legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *
+ *        * Not legal *
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd1, &MySet1),
+ *        XEmacPs_BdRingFromHwRx(MyRingPtr, NumBd2, &MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd2, MySet2),
+ *        XEmacPs_BdRingFree(MyRingPtr, NumBd1, MySet1),
+ * 

+ *
+ * If hardware has only partially completed a packet spanning multiple BDs,
+ * then none of the BDs for that packet will be included in the results.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param BdLimit is the maximum number of BDs to return in the set.
+ * @param BdSetPtr is an output parameter, it points to the first BD available
+ *        for examination.
+ *
+ * @return
+ *   The number of BDs processed by hardware. A value of 0 indicates that no
+ *   data is available. No more than BdLimit BDs will be returned.
+ *
+ * @note Treat BDs returned by this function as read-only.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr)
+{
+	XEmacPs_Bd *CurBdPtr;
+	u32 BdStr = 0U;
+	u32 BdCount;
+	u32 BdPartialCount;
+	u32 Status;
+
+	CurBdPtr = RingPtr->HwHead;
+	BdCount = 0U;
+	BdPartialCount = 0U;
+
+	/* If no BDs in work group, then there's nothing to search */
+	if (RingPtr->HwCnt == 0x00000000U) {
+		*BdSetPtr = NULL;
+		Status = 0U;
+	} else {
+
+	/* Starting at HwHead, keep moving forward in the list until:
+	 *  - A BD is encountered with its new/used bit set which means
+	 *    hardware has completed processing of that BD.
+	 *  - RingPtr->HwTail is reached and RingPtr->HwCnt is reached.
+	 *  - The number of requested BDs has been processed
+	 */
+	while (BdCount < BdLimit) {
+
+		/* Read the status */
+			if(CurBdPtr!=NULL){
+		BdStr = XEmacPs_BdRead(CurBdPtr, XEMACPS_BD_STAT_OFFSET);
+			}
+			if ((!(XEmacPs_BdIsRxNew(CurBdPtr)))==TRUE) {
+			break;
+		}
+
+		BdCount++;
+
+		/* hardware has processed this BD so check the "last" bit. If
+                 * it is clear, then there are more BDs for the current packet.
+                 * Keep a count of these partial packet BDs.
+		 */
+			if ((BdStr & XEMACPS_RXBUF_EOF_MASK)!=0x00000000U) {
+				BdPartialCount = 0U;
+			} else {
+			BdPartialCount++;
+		}
+
+		/* Move on to next BD in work group */
+		CurBdPtr = XEmacPs_BdRingNext(RingPtr, CurBdPtr);
+	}
+
+	/* Subtract off any partial packet BDs found */
+	BdCount -= BdPartialCount;
+
+	/* If BdCount is non-zero then BDs were found to return. Set return
+	 * parameters, update pointers and counters, return success
+	 */
+		if (BdCount > 0x00000000U) {
+		*BdSetPtr = RingPtr->HwHead;
+		RingPtr->HwCnt -= BdCount;
+		RingPtr->PostCnt += BdCount;
+		XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->HwHead, BdCount);
+			Status = (BdCount);
+	}
+	else {
+		*BdSetPtr = NULL;
+			Status = 0U;
+	}
+}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Frees a set of BDs that had been previously retrieved with
+ * XEmacPs_BdRingFromHw().
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param NumBd is the number of BDs to free.
+ * @param BdSetPtr is the head of a list of BDs returned by
+ * XEmacPs_BdRingFromHw().
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_LIST_ERROR if this function was called out of sequence with
+ *     XEmacPs_BdRingFromHw().
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr)
+{
+	LONG Status;
+	/* if no bds to process, simply return. */
+	if (0x00000000U == NumBd){
+		Status = (LONG)(XST_SUCCESS);
+	} else {
+	/* Make sure we are in sync with XEmacPs_BdRingFromHw() */
+	if ((RingPtr->PostCnt < NumBd) || (RingPtr->PostHead != BdSetPtr)) {
+			Status = (LONG)(XST_DMA_SG_LIST_ERROR);
+		} else {
+	/* Update pointers and counters */
+	RingPtr->FreeCnt += NumBd;
+	RingPtr->PostCnt -= NumBd;
+	XEMACPS_RING_SEEKAHEAD(RingPtr, RingPtr->PostHead, NumBd);
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Check the internal data structures of the BD ring for the provided channel.
+ * The following checks are made:
+ *
+ *   - Is the BD ring linked correctly in physical address space.
+ *   - Do the internal pointers point to BDs in the ring.
+ *   - Do the internal counters add up.
+ *
+ * The channel should be stopped prior to calling this function.
+ *
+ * @param RingPtr is a pointer to the instance to be worked on.
+ * @param Direction is either XEMACPS_SEND or XEMACPS_RECV that indicates
+ *        which direction.
+ *
+ * @return
+ *   - XST_SUCCESS if the set of BDs was freed.
+ *   - XST_DMA_SG_NO_LIST if the list has not been created.
+ *   - XST_IS_STARTED if the channel is not stopped.
+ *   - XST_DMA_SG_LIST_ERROR if a problem is found with the internal data
+ *     structures. If this value is returned, the channel should be reset to
+ *     avoid data corruption or system instability.
+ *
+ * @note This function should not be preempted by another XEmacPs_Bd function
+ *       call that modifies the BD space. It is the caller's responsibility to
+ *       provide a mutual exclusion mechanism.
+ *
+ *****************************************************************************/
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction)
+{
+	UINTPTR AddrV, AddrP;
+	u32 i;
+
+	if ((Direction != (u8)XEMACPS_SEND) && (Direction != (u8)XEMACPS_RECV)) {
+		return (LONG)(XST_INVALID_PARAM);
+	}
+
+	/* Is the list created */
+	if (RingPtr->AllCnt == 0x00000000U) {
+		return (LONG)(XST_DMA_SG_NO_LIST);
+	}
+
+	/* Can't check if channel is running */
+	if (RingPtr->RunState == (u32)XST_DMA_SG_IS_STARTED) {
+		return (LONG)(XST_IS_STARTED);
+	}
+
+	/* RunState doesn't make sense */
+	if (RingPtr->RunState != (u32)XST_DMA_SG_IS_STOPPED) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal pointers point to correct memory space */
+	AddrV = (UINTPTR) RingPtr->FreeHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PreHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->HwTail;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	AddrV = (UINTPTR) RingPtr->PostHead;
+	if ((AddrV < RingPtr->BaseBdAddr) || (AddrV > RingPtr->HighBdAddr)) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify internal counters add up */
+	if ((RingPtr->HwCnt + RingPtr->PreCnt + RingPtr->FreeCnt +
+	     RingPtr->PostCnt) != RingPtr->AllCnt) {
+		return (LONG)(XST_DMA_SG_LIST_ERROR);
+	}
+
+	/* Verify BDs are linked correctly */
+	AddrV = RingPtr->BaseBdAddr;
+	AddrP = RingPtr->PhysBaseAddr + RingPtr->Separation;
+
+	for (i = 1U; i < RingPtr->AllCnt; i++) {
+		/* Check BDA for this BD. It should point to next physical addr */
+		if (XEmacPs_BdRead(AddrV, XEMACPS_BD_ADDR_OFFSET) != AddrP) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+
+		/* Move on to next BD */
+		AddrV += RingPtr->Separation;
+		AddrP += RingPtr->Separation;
+	}
+
+	/* Last BD should have wrap bit set */
+	if (XEMACPS_SEND == Direction) {
+		if ((!XEmacPs_BdIsTxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+	else {			/* XEMACPS_RECV */
+		if ((!XEmacPs_BdIsRxWrap(AddrV))==TRUE) {
+			return (LONG)(XST_DMA_SG_LIST_ERROR);
+		}
+	}
+
+	/* No problems found */
+	return (LONG)(XST_SUCCESS);
+}
+
+/*****************************************************************************/
+/**
+ * Set this bit to mark the last descriptor in the receive buffer descriptor
+ * list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetRxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetRxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueRx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_ADDR_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueRx = *TempPtr;
+		DataValueRx |= XEMACPS_RXBUF_WRAP_MASK;
+		*TempPtr = DataValueRx;
+	}
+}
+
+/*****************************************************************************/
+/**
+ * Sets this bit to mark the last descriptor in the transmit buffer
+ * descriptor list.
+ *
+ * @param  BdPtr is the BD pointer to operate on
+ *
+ * @note
+ * C-style signature:
+ *    void XEmacPs_BdSetTxWrap(XEmacPs_Bd* BdPtr)
+ *
+ *****************************************************************************/
+static void XEmacPs_BdSetTxWrap(UINTPTR BdPtr)
+{
+    u32 DataValueTx;
+	u32 *TempPtr;
+
+	BdPtr += (u32)(XEMACPS_BD_STAT_OFFSET);
+	TempPtr = (u32 *)BdPtr;
+	if(TempPtr != NULL) {
+		DataValueTx = *TempPtr;
+		DataValueTx |= XEMACPS_TXBUF_WRAP_MASK;
+		*TempPtr = DataValueTx;
+	}
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.h
new file mode 100644
index 000000000..de78cf28f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_bdring.h
@@ -0,0 +1,238 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_bdring.h
+* @addtogroup emacps_v3_1
+* @{
+*
+* The Xiline EmacPs Buffer Descriptor ring driver. This is part of EmacPs
+* DMA functionalities.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XEMACPS_BDRING_H	/* prevent curcular inclusions */
+#define XEMACPS_BDRING_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**************************** Type Definitions *******************************/
+
+/** This is an internal structure used to maintain the DMA list */
+typedef struct {
+	UINTPTR PhysBaseAddr;/**< Physical address of 1st BD in list */
+	UINTPTR BaseBdAddr;	 /**< Virtual address of 1st BD in list */
+	UINTPTR HighBdAddr;	 /**< Virtual address of last BD in the list */
+	u32 Length;	 /**< Total size of ring in bytes */
+	u32 RunState;	 /**< Flag to indicate DMA is started */
+	u32 Separation;	 /**< Number of bytes between the starting address
+                                  of adjacent BDs */
+	XEmacPs_Bd *FreeHead;
+			     /**< First BD in the free group */
+	XEmacPs_Bd *PreHead;/**< First BD in the pre-work group */
+	XEmacPs_Bd *HwHead; /**< First BD in the work group */
+	XEmacPs_Bd *HwTail; /**< Last BD in the work group */
+	XEmacPs_Bd *PostHead;
+			     /**< First BD in the post-work group */
+	XEmacPs_Bd *BdaRestart;
+			     /**< BDA to load when channel is started */
+
+	u32 HwCnt;	     /**< Number of BDs in work group */
+	u32 PreCnt;     /**< Number of BDs in pre-work group */
+	u32 FreeCnt;    /**< Number of allocatable BDs in the free group */
+	u32 PostCnt;    /**< Number of BDs in post-work group */
+	u32 AllCnt;     /**< Total Number of BDs for channel */
+} XEmacPs_BdRing;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many BDs will fit
+* in a BD list within the given memory constraints.
+*
+* The results of this macro can be provided to XEmacPs_BdRingCreate().
+*
+* @param Alignment specifies what byte alignment the BDs must fall on and
+*        must be a power of 2 to get an accurate calculation (32, 64, 128,...)
+* @param Bytes is the number of bytes to be used to store BDs.
+*
+* @return Number of BDs that can fit in the given memory area
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingCntCalc(u32 Alignment, u32 Bytes)
+*
+******************************************************************************/
+#define XEmacPs_BdRingCntCalc(Alignment, Bytes)                    \
+    (u32)((Bytes) / (sizeof(XEmacPs_Bd)))
+
+/*****************************************************************************/
+/**
+* Use this macro at initialization time to determine how many bytes of memory
+* is required to contain a given number of BDs at a given alignment.
+*
+* @param Alignment specifies what byte alignment the BDs must fall on. This
+*        parameter must be a power of 2 to get an accurate calculation (32, 64,
+*        128,...)
+* @param NumBd is the number of BDs to calculate memory size requirements for
+*
+* @return The number of bytes of memory required to create a BD list with the
+*         given memory constraints.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingMemCalc(u32 Alignment, u32 NumBd)
+*
+******************************************************************************/
+#define XEmacPs_BdRingMemCalc(Alignment, NumBd)                    \
+    (u32)(sizeof(XEmacPs_Bd) * (NumBd))
+
+/****************************************************************************/
+/**
+* Return the total number of BDs allocated by this channel with
+* XEmacPs_BdRingCreate().
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The total number of BDs allocated for this channel.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetCnt(RingPtr) ((RingPtr)->AllCnt)
+
+/****************************************************************************/
+/**
+* Return the number of BDs allocatable with XEmacPs_BdRingAlloc() for pre-
+* processing.
+*
+* @param  RingPtr is the DMA channel to operate on.
+*
+* @return The number of BDs currently allocatable.
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_BdRingGetFreeCnt(XEmacPs_BdRing* RingPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingGetFreeCnt(RingPtr)   ((RingPtr)->FreeCnt)
+
+/****************************************************************************/
+/**
+* Return the next BD from BdPtr in a list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on.
+*
+* @return The next BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingNext(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingNext(RingPtr, BdPtr)                           \
+    (((UINTPTR)((void *)(BdPtr)) >= (RingPtr)->HighBdAddr) ?                     \
+    (XEmacPs_Bd*)((void*)(RingPtr)->BaseBdAddr) :                              \
+    (XEmacPs_Bd*)((UINTPTR)((void *)(BdPtr)) + (RingPtr)->Separation))
+
+/****************************************************************************/
+/**
+* Return the previous BD from BdPtr in the list.
+*
+* @param  RingPtr is the DMA channel to operate on.
+* @param  BdPtr is the BD to operate on
+*
+* @return The previous BD in the list relative to the BdPtr parameter.
+*
+* @note
+* C-style signature:
+*    XEmacPs_Bd *XEmacPs_BdRingPrev(XEmacPs_BdRing* RingPtr,
+*                                      XEmacPs_Bd *BdPtr)
+*
+*****************************************************************************/
+#define XEmacPs_BdRingPrev(RingPtr, BdPtr)                           \
+    (((UINTPTR)(BdPtr) <= (RingPtr)->BaseBdAddr) ?                     \
+    (XEmacPs_Bd*)(RingPtr)->HighBdAddr :                              \
+    (XEmacPs_Bd*)((UINTPTR)(BdPtr) - (RingPtr)->Separation))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Scatter gather DMA related functions in xemacps_bdring.c
+ */
+LONG XEmacPs_BdRingCreate(XEmacPs_BdRing * RingPtr, UINTPTR PhysAddr,
+			  UINTPTR VirtAddr, u32 Alignment, u32 BdCount);
+LONG XEmacPs_BdRingClone(XEmacPs_BdRing * RingPtr, XEmacPs_Bd * SrcBdPtr,
+			 u8 Direction);
+LONG XEmacPs_BdRingAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingUnAlloc(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			   XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingToHw(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+LONG XEmacPs_BdRingFree(XEmacPs_BdRing * RingPtr, u32 NumBd,
+			XEmacPs_Bd * BdSetPtr);
+u32 XEmacPs_BdRingFromHwTx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+u32 XEmacPs_BdRingFromHwRx(XEmacPs_BdRing * RingPtr, u32 BdLimit,
+				 XEmacPs_Bd ** BdSetPtr);
+LONG XEmacPs_BdRingCheck(XEmacPs_BdRing * RingPtr, u8 Direction);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* end of protection macros */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_control.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_control.c
new file mode 100644
index 000000000..f52451a8c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_control.c
@@ -0,0 +1,1174 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * @file xemacps_control.c
+* @addtogroup emacps_v3_1
+* @{
+ *
+ * Functions in this file implement general purpose command and control related
+ * functionality. See xemacps.h for a detailed description of the driver.
+ *
+ * 
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- -------------------------------------------------------
+ * 1.00a wsy  01/10/10 First release
+ * 1.02a asa  11/05/12 Added a new API for deleting an entry from the HASH
+ *					   register. Added a new API for setting the BURST length
+ *					   in DMACR register.
+ * 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp architecture.
+ * 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+ * 3.0   hk   02/20/15 Added support for jumbo frames.
+ * 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+ * 

+ *****************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Set the MAC address for this driver/device.  The address is a 48-bit value.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	}
+	else{
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the MAC bits [31:0] in BOT */
+		MacAddr = *(Aptr);
+		MacAddr |= ((u32)(*(Aptr+1)) << 8U);
+		MacAddr |= ((u32)(*(Aptr+2)) << 16U);
+		MacAddr |= ((u32)(*(Aptr+3)) << 24U);
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+	/* There are reserved bits in TOP so don't affect them */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+
+		MacAddr &= (u32)(~XEMACPS_LADDR_MACH_MASK);
+
+	/* Set MAC bits [47:32] in TOP */
+		MacAddr |= (u32)(*(Aptr+4));
+		MacAddr |= (u32)(*(Aptr+5)) << 8U;
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)), MacAddr);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the MAC address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current MAC address will be copied.
+ * @param Index is a index to which MAC (1-4) address.
+ *
+ *****************************************************************************/
+void XEmacPs_GetMacAddress(XEmacPs *InstancePtr, void *AddressPtr, u8 Index)
+{
+	u32 MacAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 IndexLoc = Index;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Aptr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IndexLoc <= (u8)XEMACPS_MAX_MAC_ADDR) && (IndexLoc > 0x00U));
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+	IndexLoc--;
+
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1L_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*Aptr = (u8) MacAddr;
+	*(Aptr+1) = (u8) (MacAddr >> 8U);
+	*(Aptr+2) = (u8) (MacAddr >> 16U);
+	*(Aptr+3) = (u8) (MacAddr >> 24U);
+
+	/* Read MAC bits [47:32] in TOP */
+	MacAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    ((u32)XEMACPS_LADDR1H_OFFSET + ((u32)IndexLoc * (u32)8)));
+	*(Aptr+4) = (u8) MacAddr;
+	*(Aptr+5) = (u8) (MacAddr >> 8U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * The hash address register is 64 bits long and takes up two locations in
+ * the memory map. The least significant bits are stored in hash register
+ * bottom and the most significant bits in hash register top.
+ *
+ * The unicast hash enable and the multicast hash enable bits in the network
+ * configuration register enable the reception of hash matched frames. The
+ * destination address is reduced to a 6 bit index into the 64 bit hash
+ * register using the following hash function. The hash function is an XOR
+ * of every sixth bit of the destination address.
+ *
+ * 
+ * hash_index[05] = da[05]^da[11]^da[17]^da[23]^da[29]^da[35]^da[41]^da[47]
+ * hash_index[04] = da[04]^da[10]^da[16]^da[22]^da[28]^da[34]^da[40]^da[46]
+ * hash_index[03] = da[03]^da[09]^da[15]^da[21]^da[27]^da[33]^da[39]^da[45]
+ * hash_index[02] = da[02]^da[08]^da[14]^da[20]^da[26]^da[32]^da[38]^da[44]
+ * hash_index[01] = da[01]^da[07]^da[13]^da[19]^da[25]^da[31]^da[37]^da[43]
+ * hash_index[00] = da[00]^da[06]^da[12]^da[18]^da[24]^da[30]^da[36]^da[42]
+ * 

+ *
+ * da[0] represents the least significant bit of the first byte received,
+ * that is, the multicast/unicast indicator, and da[47] represents the most
+ * significant bit of the last byte received.
+ *
+ * If the hash index points to a bit that is set in the hash register then
+ * the frame will be matched according to whether the frame is multicast
+ * or unicast.
+ *
+ * A multicast match will be signaled if the multicast hash enable bit is
+ * set, da[0] is logic 1 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * A unicast match will be signaled if the unicast hash enable bit is set,
+ * da[0] is logic 0 and the hash index points to a bit set in the hash
+ * register.
+ *
+ * To receive all multicast frames, the hash register should be set with
+ * all ones and the multicast hash enable bit should be set in the network
+ * configuration register.
+ *
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_SetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(AddressPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x3U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+				(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)XEMACPS_MAX_HASH_BITS) {
+			Status = (LONG)(XST_INVALID_PARAM);
+		} else {
+
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr |= (u32)(0x00000001U << Result);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr |= (u32)(0x00000001U << (u32)(Result - (u32)32));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Delete 48-bit MAC addresses in hash table.
+ * The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is a pointer to a 6-byte MAC address.
+ *
+ * @return
+ * - XST_SUCCESS if the HASH MAC address was deleted successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ * - XST_INVALID_PARAM if the HASH MAC address passed in does not meet
+ *   requirement after calculation
+ *
+ * @note
+ * Having Aptr be unsigned type prevents the following operations from sign
+ * extending.
+ *****************************************************************************/
+LONG XEmacPs_DeleteHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 HashAddr;
+	u8 *Aptr = (u8 *)(void *)AddressPtr;
+	u8 Temp1, Temp2, Temp3, Temp4, Temp5, Temp6, Temp7, Temp8;
+	u32 Result;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Aptr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+		Temp1 = (*(Aptr+0)) & 0x3FU;
+		Temp2 = ((*(Aptr+0) >> 6U) & 0x03U) | ((*(Aptr+1) & 0x0FU) << 2U);
+		Temp3 = ((*(Aptr+1) >> 4U) & 0x0FU) | ((*(Aptr+2) & 0x03U) << 4U);
+		Temp4 = ((*(Aptr+2) >> 2U) & 0x3FU);
+		Temp5 =   (*(Aptr+3)) & 0x3FU;
+		Temp6 = ((*(Aptr+3) >> 6U) & 0x03U) | ((*(Aptr+4) & 0x0FU) << 2U);
+		Temp7 = ((*(Aptr+4) >> 4U) & 0x0FU) | ((*(Aptr+5) & 0x03U) << 4U);
+		Temp8 = ((*(Aptr+5) >> 2U) & 0x3FU);
+
+		Result = (u32)((u32)Temp1 ^ (u32)Temp2 ^ (u32)Temp3 ^ (u32)Temp4 ^
+					(u32)Temp5 ^ (u32)Temp6 ^ (u32)Temp7 ^ (u32)Temp8);
+
+		if (Result >= (u32)(XEMACPS_MAX_HASH_BITS)) {
+			Status =  (LONG)(XST_INVALID_PARAM);
+		} else {
+			if (Result < (u32)32) {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << Result));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHL_OFFSET, HashAddr);
+	} else {
+		HashAddr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_HASHH_OFFSET);
+				HashAddr &= (u32)(~(0x00000001U << (u32)(Result - (u32)32)));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_HASHH_OFFSET, HashAddr);
+	}
+			Status = (LONG)(XST_SUCCESS);
+		}
+	}
+	return Status;
+}
+/*****************************************************************************/
+/**
+ * Clear the Hash registers for the mac address pointed by AddressPtr.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ *****************************************************************************/
+void XEmacPs_ClearHash(XEmacPs *InstancePtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET, 0x0U);
+
+	/* write bits [63:32] in TOP */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET, 0x0U);
+}
+
+
+/*****************************************************************************/
+/**
+ * Get the Hash address for this driver/device.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param AddressPtr is an output parameter, and is a pointer to a buffer into
+ *        which the current HASH MAC address will be copied.
+ *
+ *****************************************************************************/
+void XEmacPs_GetHash(XEmacPs *InstancePtr, void *AddressPtr)
+{
+	u32 *Aptr = (u32 *)(void *)AddressPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(AddressPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	*(Aptr+0) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHL_OFFSET);
+
+	/* Read Hash bits [63:32] in TOP */
+	*(Aptr+1) = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XEMACPS_HASHH_OFFSET);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the Type ID match for this driver/device.  The register is a 32-bit
+ * value. The device must be stopped before calling this function.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Id_Check is type ID to be configured.
+ * @param Index is a index to which Type ID (1-4).
+ *
+ * @return
+ * - XST_SUCCESS if the MAC address was set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetTypeIdCheck(XEmacPs *InstancePtr, u32 Id_Check, u8 Index)
+{
+	u8 IndexLoc = Index;
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((IndexLoc <= (u8)XEMACPS_MAX_TYPE_ID) && (IndexLoc > 0x00U));
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Index ranges 1 to 4, for offset calculation is 0 to 3. */
+		IndexLoc--;
+
+	/* Set the ID bits in MATCHx register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   ((u32)XEMACPS_MATCH1_OFFSET + ((u32)IndexLoc * (u32)4)), Id_Check);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * Set options for the driver/device. The driver should be stopped with
+ * XEmacPs_Stop() before changing options.
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to set. Multiple options can be set by OR'ing
+ *        XTE_*_OPTIONS constants together. Options not specified are not
+ *        affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic register contents */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/*
+	 * It is configured to max 1536.
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn on VLAN packet only, only VLAN tagged will be accepted */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_NVLANDISC_MASK;
+	}
+
+	/* Turn on FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_FCSREM_MASK;
+	}
+
+	/* Turn on length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg |= XEMACPS_NWCFG_LENERRDSCRD_MASK;
+	}
+
+	/* Turn on flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_PAUSEEN_MASK;
+	}
+
+	/* Turn on promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_COPYALLEN_MASK;
+	}
+
+	/* Allow broadcast address reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_BCASTDI_MASK);
+	}
+
+	/* Allow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_MCASTHASHEN_MASK;
+	}
+
+	/* enable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_RXCHKSUMEN_MASK;
+	}
+
+	/* Enable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg |= XEMACPS_NWCFG_JUMBO_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_JUMBOMAXLEN_OFFSET, XEMACPS_RX_BUF_SIZE_JUMBO);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE_JUMBO / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE_JUMBO %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU_JUMBO;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU_JUMBO +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_JUMBO_MASK;
+	}
+
+	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg |= (XEMACPS_NWCFG_SGMIIEN_MASK |
+						XEMACPS_NWCFG_PCSSEL_MASK);
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Enable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+		Reg |= XEMACPS_DMACR_TCPCKSUM_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Enable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_TXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Enable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+		Reg |= XEMACPS_NWCTRL_RXEN_MASK;
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * the option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options |= Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Clear options for the driver/device
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Options are the options to clear. Multiple options can be cleared by
+ *        OR'ing XEMACPS_*_OPTIONS constants together. Options not specified
+ *        are not affected.
+ *
+ * @return
+ * - XST_SUCCESS if the options were set successfully
+ * - XST_DEVICE_IS_STARTED if the device has not yet been stopped
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+LONG XEmacPs_ClearOptions(XEmacPs *InstancePtr, u32 Options)
+{
+	u32 Reg;		/* Generic */
+	u32 RegNetCfg;		/* Reflects original contents of NET_CONFIG */
+	u32 RegNewNetCfg;	/* Reflects new contents of NET_CONFIG */
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Be sure device has been stopped */
+	if (InstancePtr->IsStarted == (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STARTED);
+	} else {
+
+	/* Many of these options will change the NET_CONFIG registers.
+	 * To reduce the amount of IO to the device, group these options here
+	 * and change them all at once.
+	 */
+
+	/* Grab current register contents */
+	RegNetCfg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_NWCFG_OFFSET);
+	RegNewNetCfg = RegNetCfg;
+
+	/* There is only RX configuration!?
+	 * It is configured in two different length, upto 1536 and 10240 bytes
+	 */
+		if ((Options & XEMACPS_FRAME1536_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_1536RXEN_MASK);
+	}
+
+	/* Turn off VLAN packet only */
+		if ((Options & XEMACPS_VLAN_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_NVLANDISC_MASK);
+	}
+
+	/* Turn off FCS stripping on receive packets */
+		if ((Options & XEMACPS_FCS_STRIP_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_FCSREM_MASK);
+	}
+
+	/* Turn off length/type field checking on receive packets */
+		if ((Options & XEMACPS_LENTYPE_ERR_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_LENERRDSCRD_MASK);
+	}
+
+	/* Turn off flow control */
+		if ((Options & XEMACPS_FLOW_CONTROL_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_PAUSEEN_MASK);
+	}
+
+	/* Turn off promiscuous frame filtering (all frames are received) */
+		if ((Options & XEMACPS_PROMISC_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_COPYALLEN_MASK);
+	}
+
+	/* Disallow broadcast address filtering => broadcast reception */
+		if ((Options & XEMACPS_BROADCAST_OPTION) != 0x00000000U) {
+		RegNewNetCfg |= XEMACPS_NWCFG_BCASTDI_MASK;
+	}
+
+	/* Disallow multicast address filtering */
+		if ((Options & XEMACPS_MULTICAST_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_MCASTHASHEN_MASK);
+	}
+
+	/* Disable RX checksum offload */
+		if ((Options & XEMACPS_RX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+			RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_RXCHKSUMEN_MASK);
+	}
+
+	/* Disable jumbo frames */
+	if (((Options & XEMACPS_JUMBO_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg &= (u32)(~XEMACPS_NWCFG_JUMBO_MASK);
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XEMACPS_DMACR_OFFSET);
+		Reg &= ~XEMACPS_DMACR_RXBUF_MASK;
+		Reg |= (((((u32)XEMACPS_RX_BUF_SIZE / (u32)XEMACPS_RX_BUF_UNIT) +
+			(((((u32)XEMACPS_RX_BUF_SIZE %
+			(u32)XEMACPS_RX_BUF_UNIT))!=(u32)0) ? 1U : 0U)) <<
+			(u32)(XEMACPS_DMACR_RXBUF_SHIFT)) &
+			(u32)(XEMACPS_DMACR_RXBUF_MASK));
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_DMACR_OFFSET, Reg);
+		InstancePtr->MaxMtuSize = XEMACPS_MTU;
+		InstancePtr->MaxFrameSize = XEMACPS_MTU +
+					XEMACPS_HDR_SIZE + XEMACPS_TRL_SIZE;
+		InstancePtr->MaxVlanFrameSize = InstancePtr->MaxFrameSize +
+					XEMACPS_HDR_VLAN_SIZE;
+		InstancePtr->RxBufMask = XEMACPS_RXBUF_LEN_MASK;
+	}
+
+	if (((Options & XEMACPS_SGMII_ENABLE_OPTION) != 0x00000000U) &&
+		(InstancePtr->Version > 2)) {
+		RegNewNetCfg &= (u32)(~(XEMACPS_NWCFG_SGMIIEN_MASK |
+						XEMACPS_NWCFG_PCSSEL_MASK));
+	}
+
+	/* Officially change the NET_CONFIG registers if it needs to be
+	 * modified.
+	 */
+	if (RegNetCfg != RegNewNetCfg) {
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCFG_OFFSET, RegNewNetCfg);
+	}
+
+	/* Disable TX checksum offload */
+		if ((Options & XEMACPS_TX_CHKSUM_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_DMACR_OFFSET);
+			Reg &= (u32)(~XEMACPS_DMACR_TCPCKSUM_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					 XEMACPS_DMACR_OFFSET, Reg);
+	}
+
+	/* Disable transmitter */
+		if ((Options & XEMACPS_TRANSMITTER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_TXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* Disable receiver */
+		if ((Options & XEMACPS_RECEIVER_ENABLE_OPTION) != 0x00000000U) {
+		Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET);
+			Reg &= (u32)(~XEMACPS_NWCTRL_RXEN_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_NWCTRL_OFFSET, Reg);
+	}
+
+	/* The remaining options not handled here are managed elsewhere in the
+	 * driver. No register modifications are needed at this time. Reflecting
+	 * option in InstancePtr->Options is good enough for now.
+	 */
+
+	/* Set options word to its new value */
+	InstancePtr->Options &= ~Options;
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * Get current option settings
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * A bitmask of XTE_*_OPTION constants. Any bit set to 1 is to be interpreted
+ * as a set opion.
+ *
+ * @note
+ * See xemacps.h for a description of the available options.
+ *
+ *****************************************************************************/
+u32 XEmacPs_GetOptions(XEmacPs *InstancePtr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	return (InstancePtr->Options);
+}
+
+
+/*****************************************************************************/
+/**
+ * Send a pause packet
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ *
+ * @return
+ * - XST_SUCCESS if pause frame transmission was initiated
+ * - XST_DEVICE_IS_STOPPED if the device has not been started.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SendPausePacket(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* Make sure device is ready for this operation */
+	if (InstancePtr->IsStarted != (u32)XIL_COMPONENT_IS_STARTED) {
+		Status = (LONG)(XST_DEVICE_IS_STOPPED);
+	} else {
+	/* Send flow control frame */
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCTRL_OFFSET);
+	Reg |= XEMACPS_NWCTRL_PAUSETX_MASK;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCTRL_OFFSET, Reg);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+ * XEmacPs_GetOperatingSpeed gets the current operating link speed. This may
+ * be the value set by XEmacPs_SetOperatingSpeed() or a hardware default.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ *
+ * @return XEmacPs_GetOperatingSpeed returns the link speed in units of
+ *         megabits per second.
+ *
+ * @note
+ *
+ *****************************************************************************/
+u16 XEmacPs_GetOperatingSpeed(XEmacPs *InstancePtr)
+{
+	u32 Reg;
+	u16 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+
+	if ((Reg & XEMACPS_NWCFG_1000_MASK) != 0x00000000U) {
+		Status = (u16)(1000);
+	} else {
+		if ((Reg & XEMACPS_NWCFG_100_MASK) != 0x00000000U) {
+			Status = (u16)(100);
+		} else {
+			Status = (u16)(10);
+		}
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+ * XEmacPs_SetOperatingSpeed sets the current operating link speed. For any
+ * traffic to be passed, this speed must match the current MII/GMII/SGMII/RGMII
+ * link speed.
+ *
+ * @param InstancePtr references the TEMAC channel on which to operate.
+ * @param Speed is the speed to set in units of Mbps. Valid values are 10, 100,
+ *        or 1000. XEmacPs_SetOperatingSpeed ignores invalid values.
+ *
+ * @note
+ *
+ *****************************************************************************/
+void XEmacPs_SetOperatingSpeed(XEmacPs *InstancePtr, u16 Speed)
+{
+        u32 Reg;
+	u16 Status;
+        Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+    Xil_AssertVoid((Speed == (u16)10) || (Speed == (u16)100) || (Speed == (u16)1000));
+
+        Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XEMACPS_NWCFG_OFFSET);
+	Reg &= (u32)(~(XEMACPS_NWCFG_1000_MASK | XEMACPS_NWCFG_100_MASK));
+
+	switch (Speed) {
+		case (u16)10:
+				Status = 0U;
+                break;
+
+        case (u16)100:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_100_MASK;
+                break;
+
+        case (u16)1000:
+			Status = 0U;
+                Reg |= XEMACPS_NWCFG_1000_MASK;
+                break;
+
+        default:
+			Status = 1U;
+                break;
+    }
+	if(Status == (u16)1){
+                return;
+        }
+
+        /* Set register and return */
+        XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+                XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+ * Set the MDIO clock divisor.
+ *
+ * Calculating the divisor:
+ *
+ * 
+ *              f[HOSTCLK]
+ *   f[MDC] = -----------------
+ *            (1 + Divisor) * 2
+ * 

+ *
+ * where f[HOSTCLK] is the bus clock frequency in MHz, and f[MDC] is the
+ * MDIO clock frequency in MHz to the PHY. Typically, f[MDC] should not
+ * exceed 2.5 MHz. Some PHYs can tolerate faster speeds which means faster
+ * access. Here is the table to show values to generate MDC,
+ *
+ * 
+ * 000 : divide pclk by   8 (pclk up to  20 MHz)
+ * 001 : divide pclk by  16 (pclk up to  40 MHz)
+ * 010 : divide pclk by  32 (pclk up to  80 MHz)
+ * 011 : divide pclk by  48 (pclk up to 120 MHz)
+ * 100 : divide pclk by  64 (pclk up to 160 MHz)
+ * 101 : divide pclk by  96 (pclk up to 240 MHz)
+ * 110 : divide pclk by 128 (pclk up to 320 MHz)
+ * 111 : divide pclk by 224 (pclk up to 540 MHz)
+ * 

+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param Divisor is the divisor to set. Range is 0b000 to 0b111.
+ *
+ *****************************************************************************/
+void XEmacPs_SetMdioDivisor(XEmacPs *InstancePtr, XEmacPs_MdcDiv Divisor)
+{
+	u32 Reg;
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Divisor <= (XEmacPs_MdcDiv)0x7); /* only last three bits are valid */
+
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWCFG_OFFSET);
+	/* clear these three bits, could be done with mask */
+	Reg &= (u32)(~XEMACPS_NWCFG_MDCCLKDIV_MASK);
+
+	Reg |= ((u32)Divisor << XEMACPS_NWCFG_MDC_SHIFT_MASK);
+
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_NWCFG_OFFSET, Reg);
+}
+
+
+/*****************************************************************************/
+/**
+* Read the current value of the PHY register indicated by the PhyAddress and
+* the RegisterNum parameters. The MAC provides the driver with the ability to
+* talk to a PHY that adheres to the Media Independent Interface (MII) as
+* defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be read (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to read
+* @param PhyDataPtr is an output parameter, and points to a 16-bit buffer into
+*        which the current value of the register will be copied.
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was read from successfully
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the read is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyRead(XEmacPs *InstancePtr, u32 PhyAddress,
+		     u32 RegisterNum, u16 *PhyDataPtr)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpReadTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK);
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+			IpReadTemp = Ipisr;
+		} while ((IpReadTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+	/* Read data */
+		*PhyDataPtr = (u16)XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_PHYMNTNC_OFFSET);
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+* Write data to the specified PHY register. The Ethernet driver does not
+* require the device to be stopped before writing to the PHY.  Although it is
+* probably a good idea to stop the device, it is the responsibility of the
+* application to deem this necessary. The MAC provides the driver with the
+* ability to talk to a PHY that adheres to the Media Independent Interface
+* (MII) as defined in the IEEE 802.3 standard.
+*
+* Prior to PHY access with this function, the user should have setup the MDIO
+* clock with XEmacPs_SetMdioDivisor().
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param PhyAddress is the address of the PHY to be written (supports multiple
+*        PHYs)
+* @param RegisterNum is the register number, 0-31, of the specific PHY register
+*        to write
+* @param PhyData is the 16-bit value that will be written to the register
+*
+* @return
+*
+* - XST_SUCCESS if the PHY was written to successfully. Since there is no error
+*   status from the MAC on a write, the user should read the PHY to verify the
+*   write was successful.
+* - XST_EMAC_MII_BUSY if there is another PHY operation in progress
+*
+* @note
+*
+* This function is not thread-safe. The user must provide mutually exclusive
+* access to this function if there are to be multiple threads that can call it.
+*
+* There is the possibility that this function will not return if the hardware
+* is broken (i.e., it never sets the status bit indicating that the write is
+* done). If this is of concern to the user, the user should provide a mechanism
+* suitable to their needs for recovery.
+*
+* For the duration of this function, all host interface reads and writes are
+* blocked to the current XEmacPs instance.
+*
+******************************************************************************/
+LONG XEmacPs_PhyWrite(XEmacPs *InstancePtr, u32 PhyAddress,
+		      u32 RegisterNum, u16 PhyData)
+{
+	u32 Mgtcr;
+	volatile u32 Ipisr;
+	u32 IpWriteTemp;
+	LONG Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Make sure no other PHY operation is currently in progress */
+	if ((!(XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XEMACPS_NWSR_OFFSET) &
+	      XEMACPS_NWSR_MDIOIDLE_MASK))==TRUE) {
+		Status = (LONG)(XST_EMAC_MII_BUSY);
+	} else {
+	/* Construct Mgtcr mask for the operation */
+	Mgtcr = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK |
+			(PhyAddress << XEMACPS_PHYMNTNC_PHAD_SHFT_MSK) |
+			(RegisterNum << XEMACPS_PHYMNTNC_PREG_SHFT_MSK) | (u32)PhyData;
+
+	/* Write Mgtcr and wait for completion */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XEMACPS_PHYMNTNC_OFFSET, Mgtcr);
+
+	do {
+		Ipisr = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_NWSR_OFFSET);
+				IpWriteTemp = Ipisr;
+		} while ((IpWriteTemp & XEMACPS_NWSR_MDIOIDLE_MASK) == 0x00000000U);
+
+		Status = (LONG)(XST_SUCCESS);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* API to update the Burst length in the DMACR register.
+*
+* @param InstancePtr is a pointer to the XEmacPs instance to be worked on.
+* @param BLength is the length in bytes for the dma burst.
+*
+* @return None
+*
+******************************************************************************/
+void XEmacPs_DMABLengthUpdate(XEmacPs *InstancePtr, s32 BLength)
+{
+	u32 Reg;
+	u32 RegUpdateVal;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid((BLength == XEMACPS_SINGLE_BURST) ||
+					(BLength == XEMACPS_4BYTE_BURST) ||
+					(BLength == XEMACPS_8BYTE_BURST) ||
+					(BLength == XEMACPS_16BYTE_BURST));
+
+	switch (BLength) {
+		case XEMACPS_SINGLE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_SINGLE_AHB_BURST;
+			break;
+
+		case XEMACPS_4BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR4_AHB_BURST;
+			break;
+
+		case XEMACPS_8BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR8_AHB_BURST;
+			break;
+
+		case XEMACPS_16BYTE_BURST:
+			RegUpdateVal = XEMACPS_DMACR_INCR16_AHB_BURST;
+			break;
+
+		default:
+			RegUpdateVal = 0x00000000U;
+			break;
+	}
+	Reg = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_DMACR_OFFSET);
+
+	Reg &= (u32)(~XEMACPS_DMACR_BLENGTH_MASK);
+	Reg |= RegUpdateVal;
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_DMACR_OFFSET,
+																	Reg);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_g.c
new file mode 100644
index 000000000..6a7cc7866
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xemacps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XEmacPs_Config XEmacPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_ETHERNET_3_DEVICE_ID,
+		XPAR_PSU_ETHERNET_3_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.c
new file mode 100644
index 000000000..daba38397
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.c
@@ -0,0 +1,123 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* This file contains the implementation of the ethernet interface reset sequence
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.05a kpc  28/06/13 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps_hw.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given emacps interface by
+* configuring the appropriate control bits in the emacps specifc registers.
+* the emacps reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status registers
+*	Disable Rx and Tx engines
+*	Update the Tx and Rx descriptor queue registers with reset values
+*	Update the other relevant control registers with reset value
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* emacps controller
+******************************************************************************/
+void XEmacPs_ResetHw(u32 BaseAddr)
+{
+	u32 RegVal;
+
+	/* Disable the interrupts  */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_IDR_OFFSET,0x0U);
+
+	/* Stop transmission,disable loopback and Stop tx and Rx engines */
+	RegVal = XEmacPs_ReadReg(BaseAddr,XEMACPS_NWCTRL_OFFSET);
+	RegVal &= ~((u32)XEMACPS_NWCTRL_TXEN_MASK|
+				(u32)XEMACPS_NWCTRL_RXEN_MASK|
+				(u32)XEMACPS_NWCTRL_HALTTX_MASK|
+				(u32)XEMACPS_NWCTRL_LOOPEN_MASK);
+	/* Clear the statistic registers, flush the packets in DPRAM*/
+	RegVal |= (XEMACPS_NWCTRL_STATCLR_MASK|
+				XEMACPS_NWCTRL_FLUSH_DPRAM_MASK);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCTRL_OFFSET,RegVal);
+	/* Clear the interrupt status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_ISR_OFFSET,XEMACPS_IXR_ALL_MASK);
+	/* Clear the tx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXSR_OFFSET,(XEMACPS_TXSR_ERROR_MASK|
+									(u32)XEMACPS_TXSR_TXCOMPL_MASK|
+									(u32)XEMACPS_TXSR_TXGO_MASK));
+	/* Clear the rx status */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXSR_OFFSET,
+								XEMACPS_RXSR_FRAMERX_MASK);
+	/* Clear the tx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_TXQBASE_OFFSET,0x0U);
+	/* Clear the rx base address */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_RXQBASE_OFFSET,0x0U);
+	/* Update the network config register with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_NWCFG_OFFSET,XEMACPS_NWCFG_RESET_MASK);
+	/* Update the hash address registers with reset value */
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHL_OFFSET,0x0U);
+	XEmacPs_WriteReg(BaseAddr,XEMACPS_HASHH_OFFSET,0x0U);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.h
new file mode 100644
index 000000000..953cc6265
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_hw.h
@@ -0,0 +1,656 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_hw.h
+* @addtogroup emacps_v3_1
+* @{
+*
+* This header file contains identifiers and low-level driver functions (or
+* macros) that can be used to access the PS Ethernet MAC (XEmacPs) device.
+* High-level driver functions are defined in xemacps.h.
+*
+* @note
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release.
+* 1.02a asa  11/05/12 Added hash defines for DMACR burst length configuration.
+* 1.05a kpc  28/06/13 Added XEmacPs_ResetHw function prototype
+* 1.06a asa  11/02/13 Changed the value for XEMACPS_RXBUF_LEN_MASK from 0x3fff
+*					  to 0x1fff. This fixes the CR#744902.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification.
+* 3.0   kvn  12/16/14 Changed name of XEMACPS_NWCFG_LENGTHERRDSCRD_MASK to
+*					  XEMACPS_NWCFG_LENERRDSCRD_MASK as it exceeds 31 characters.
+* 3.0  kpc   1/23/15  Corrected the extended descriptor macro values.
+* 3.0  kvn   02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.0  hk   03/18/15 Added support for jumbo frames.
+*                    Remove "used bit set" from TX error interrupt masks.
+* 3.1  hk   08/10/15 Update upper 32 bit tx and rx queue ptr register offsets.
+* 3.2   hk   02/22/16 Added SGMII support for Zynq Ultrascale+ MPSoC.
+* 

+*
+******************************************************************************/
+
+#ifndef XEMACPS_HW_H		/* prevent circular inclusions */
+#define XEMACPS_HW_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+#define XEMACPS_MAX_MAC_ADDR     4U   /**< Maxmum number of mac address
+                                           supported */
+#define XEMACPS_MAX_TYPE_ID      4U   /**< Maxmum number of type id supported */
+
+#ifdef __aarch64__
+#define XEMACPS_BD_ALIGNMENT     64U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#else
+
+#define XEMACPS_BD_ALIGNMENT     4U   /**< Minimum buffer descriptor alignment
+                                           on the local bus */
+#endif
+#define XEMACPS_RX_BUF_ALIGNMENT 4U   /**< Minimum buffer alignment when using
+                                           options that impose alignment
+                                           restrictions on the buffer data on
+                                           the local bus */
+
+/** @name Direction identifiers
+ *
+ *  These are used by several functions and callbacks that need
+ *  to specify whether an operation specifies a send or receive channel.
+ * @{
+ */
+#define XEMACPS_SEND        1U	      /**< send direction */
+#define XEMACPS_RECV        2U	      /**< receive direction */
+/*@}*/
+
+/**  @name MDC clock division
+ *  currently supporting 8, 16, 32, 48, 64, 96, 128, 224.
+ * @{
+ */
+typedef enum { MDC_DIV_8 = 0U, MDC_DIV_16, MDC_DIV_32, MDC_DIV_48,
+	MDC_DIV_64, MDC_DIV_96, MDC_DIV_128, MDC_DIV_224
+} XEmacPs_MdcDiv;
+
+/*@}*/
+
+#define XEMACPS_RX_BUF_SIZE 1536U /**< Specify the receive buffer size in
+                                       bytes, 64, 128, ... 10240 */
+#define XEMACPS_RX_BUF_SIZE_JUMBO 10240U
+
+#define XEMACPS_RX_BUF_UNIT   64U /**< Number of receive buffer bytes as a
+                                       unit, this is HW setup */
+
+#define XEMACPS_MAX_RXBD     128U /**< Size of RX buffer descriptor queues */
+#define XEMACPS_MAX_TXBD     128U /**< Size of TX buffer descriptor queues */
+
+#define XEMACPS_MAX_HASH_BITS 64U /**< Maximum value for hash bits. 2**6 */
+
+/* Register offset definitions. Unless otherwise noted, register access is
+ * 32 bit. Names are self explained here.
+ */
+
+#define XEMACPS_NWCTRL_OFFSET        0x00000000U /**< Network Control reg */
+#define XEMACPS_NWCFG_OFFSET         0x00000004U /**< Network Config reg */
+#define XEMACPS_NWSR_OFFSET          0x00000008U /**< Network Status reg */
+
+#define XEMACPS_DMACR_OFFSET         0x00000010U /**< DMA Control reg */
+#define XEMACPS_TXSR_OFFSET          0x00000014U /**< TX Status reg */
+#define XEMACPS_RXQBASE_OFFSET       0x00000018U /**< RX Q Base address reg */
+#define XEMACPS_TXQBASE_OFFSET       0x0000001CU /**< TX Q Base address reg */
+#define XEMACPS_RXSR_OFFSET          0x00000020U /**< RX Status reg */
+
+#define XEMACPS_ISR_OFFSET           0x00000024U /**< Interrupt Status reg */
+#define XEMACPS_IER_OFFSET           0x00000028U /**< Interrupt Enable reg */
+#define XEMACPS_IDR_OFFSET           0x0000002CU /**< Interrupt Disable reg */
+#define XEMACPS_IMR_OFFSET           0x00000030U /**< Interrupt Mask reg */
+
+#define XEMACPS_PHYMNTNC_OFFSET      0x00000034U /**< Phy Maintaince reg */
+#define XEMACPS_RXPAUSE_OFFSET       0x00000038U /**< RX Pause Time reg */
+#define XEMACPS_TXPAUSE_OFFSET       0x0000003CU /**< TX Pause Time reg */
+
+#define XEMACPS_JUMBOMAXLEN_OFFSET   0x00000048U /**< Jumbo max length reg */
+
+#define XEMACPS_HASHL_OFFSET         0x00000080U /**< Hash Low address reg */
+#define XEMACPS_HASHH_OFFSET         0x00000084U /**< Hash High address reg */
+
+#define XEMACPS_LADDR1L_OFFSET       0x00000088U /**< Specific1 addr low reg */
+#define XEMACPS_LADDR1H_OFFSET       0x0000008CU /**< Specific1 addr high reg */
+#define XEMACPS_LADDR2L_OFFSET       0x00000090U /**< Specific2 addr low reg */
+#define XEMACPS_LADDR2H_OFFSET       0x00000094U /**< Specific2 addr high reg */
+#define XEMACPS_LADDR3L_OFFSET       0x00000098U /**< Specific3 addr low reg */
+#define XEMACPS_LADDR3H_OFFSET       0x0000009CU /**< Specific3 addr high reg */
+#define XEMACPS_LADDR4L_OFFSET       0x000000A0U /**< Specific4 addr low reg */
+#define XEMACPS_LADDR4H_OFFSET       0x000000A4U /**< Specific4 addr high reg */
+
+#define XEMACPS_MATCH1_OFFSET        0x000000A8U /**< Type ID1 Match reg */
+#define XEMACPS_MATCH2_OFFSET        0x000000ACU /**< Type ID2 Match reg */
+#define XEMACPS_MATCH3_OFFSET        0x000000B0U /**< Type ID3 Match reg */
+#define XEMACPS_MATCH4_OFFSET        0x000000B4U /**< Type ID4 Match reg */
+
+#define XEMACPS_STRETCH_OFFSET       0x000000BCU /**< IPG Stretch reg */
+
+#define XEMACPS_OCTTXL_OFFSET        0x00000100U /**< Octects transmitted Low
+                                                      reg */
+#define XEMACPS_OCTTXH_OFFSET        0x00000104U /**< Octects transmitted High
+                                                      reg */
+
+#define XEMACPS_TXCNT_OFFSET         0x00000108U /**< Error-free Frmaes
+                                                      transmitted counter */
+#define XEMACPS_TXBCCNT_OFFSET       0x0000010CU /**< Error-free Broadcast
+                                                      Frames counter*/
+#define XEMACPS_TXMCCNT_OFFSET       0x00000110U /**< Error-free Multicast
+                                                      Frame counter */
+#define XEMACPS_TXPAUSECNT_OFFSET    0x00000114U /**< Pause Frames Transmitted
+                                                      Counter */
+#define XEMACPS_TX64CNT_OFFSET       0x00000118U /**< Error-free 64 byte Frames
+                                                      Transmitted counter */
+#define XEMACPS_TX65CNT_OFFSET       0x0000011CU /**< Error-free 65-127 byte
+                                                      Frames Transmitted
+                                                      counter */
+#define XEMACPS_TX128CNT_OFFSET      0x00000120U /**< Error-free 128-255 byte
+                                                      Frames Transmitted
+                                                      counter*/
+#define XEMACPS_TX256CNT_OFFSET      0x00000124U /**< Error-free 256-511 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX512CNT_OFFSET      0x00000128U /**< Error-free 512-1023 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1024CNT_OFFSET     0x0000012CU /**< Error-free 1024-1518 byte
+                                                      Frames transmitted
+                                                      counter */
+#define XEMACPS_TX1519CNT_OFFSET     0x00000130U /**< Error-free larger than
+                                                      1519 byte Frames
+                                                      transmitted counter */
+#define XEMACPS_TXURUNCNT_OFFSET     0x00000134U /**< TX under run error
+                                                      counter */
+
+#define XEMACPS_SNGLCOLLCNT_OFFSET   0x00000138U /**< Single Collision Frame
+                                                      Counter */
+#define XEMACPS_MULTICOLLCNT_OFFSET  0x0000013CU /**< Multiple Collision Frame
+                                                      Counter */
+#define XEMACPS_EXCESSCOLLCNT_OFFSET 0x00000140U /**< Excessive Collision Frame
+                                                      Counter */
+#define XEMACPS_LATECOLLCNT_OFFSET   0x00000144U /**< Late Collision Frame
+                                                      Counter */
+#define XEMACPS_TXDEFERCNT_OFFSET    0x00000148U /**< Deferred Transmission
+                                                      Frame Counter */
+#define XEMACPS_TXCSENSECNT_OFFSET   0x0000014CU /**< Transmit Carrier Sense
+                                                      Error Counter */
+
+#define XEMACPS_OCTRXL_OFFSET        0x00000150U /**< Octects Received register
+                                                      Low */
+#define XEMACPS_OCTRXH_OFFSET        0x00000154U /**< Octects Received register
+                                                      High */
+
+#define XEMACPS_RXCNT_OFFSET         0x00000158U /**< Error-free Frames
+                                                      Received Counter */
+#define XEMACPS_RXBROADCNT_OFFSET    0x0000015CU /**< Error-free Broadcast
+                                                      Frames Received Counter */
+#define XEMACPS_RXMULTICNT_OFFSET    0x00000160U /**< Error-free Multicast
+                                                      Frames Received Counter */
+#define XEMACPS_RXPAUSECNT_OFFSET    0x00000164U /**< Pause Frames
+                                                      Received Counter */
+#define XEMACPS_RX64CNT_OFFSET       0x00000168U /**< Error-free 64 byte Frames
+                                                      Received Counter */
+#define XEMACPS_RX65CNT_OFFSET       0x0000016CU /**< Error-free 65-127 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX128CNT_OFFSET      0x00000170U /**< Error-free 128-255 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX256CNT_OFFSET      0x00000174U /**< Error-free 256-512 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX512CNT_OFFSET      0x00000178U /**< Error-free 512-1023 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1024CNT_OFFSET     0x0000017CU /**< Error-free 1024-1518 byte
+                                                      Frames Received Counter */
+#define XEMACPS_RX1519CNT_OFFSET     0x00000180U /**< Error-free 1519-max byte
+                                                      Frames Received Counter */
+#define XEMACPS_RXUNDRCNT_OFFSET     0x00000184U /**< Undersize Frames Received
+                                                      Counter */
+#define XEMACPS_RXOVRCNT_OFFSET      0x00000188U /**< Oversize Frames Received
+                                                      Counter */
+#define XEMACPS_RXJABCNT_OFFSET      0x0000018CU /**< Jabbers Received
+                                                      Counter */
+#define XEMACPS_RXFCSCNT_OFFSET      0x00000190U /**< Frame Check Sequence
+                                                      Error Counter */
+#define XEMACPS_RXLENGTHCNT_OFFSET   0x00000194U /**< Length Field Error
+                                                      Counter */
+#define XEMACPS_RXSYMBCNT_OFFSET     0x00000198U /**< Symbol Error Counter */
+#define XEMACPS_RXALIGNCNT_OFFSET    0x0000019CU /**< Alignment Error Counter */
+#define XEMACPS_RXRESERRCNT_OFFSET   0x000001A0U /**< Receive Resource Error
+                                                      Counter */
+#define XEMACPS_RXORCNT_OFFSET       0x000001A4U /**< Receive Overrun Counter */
+#define XEMACPS_RXIPCCNT_OFFSET      0x000001A8U /**< IP header Checksum Error
+                                                      Counter */
+#define XEMACPS_RXTCPCCNT_OFFSET     0x000001ACU /**< TCP Checksum Error
+                                                      Counter */
+#define XEMACPS_RXUDPCCNT_OFFSET     0x000001B0U /**< UDP Checksum Error
+                                                      Counter */
+#define XEMACPS_LAST_OFFSET          0x000001B4U /**< Last statistic counter
+						      offset, for clearing */
+
+#define XEMACPS_1588_SEC_OFFSET      0x000001D0U /**< 1588 second counter */
+#define XEMACPS_1588_NANOSEC_OFFSET  0x000001D4U /**< 1588 nanosecond counter */
+#define XEMACPS_1588_ADJ_OFFSET      0x000001D8U /**< 1588 nanosecond
+						      adjustment counter */
+#define XEMACPS_1588_INC_OFFSET      0x000001DCU /**< 1588 nanosecond
+						      increment counter */
+#define XEMACPS_PTP_TXSEC_OFFSET     0x000001E0U /**< 1588 PTP transmit second
+						      counter */
+#define XEMACPS_PTP_TXNANOSEC_OFFSET 0x000001E4U /**< 1588 PTP transmit
+						      nanosecond counter */
+#define XEMACPS_PTP_RXSEC_OFFSET     0x000001E8U /**< 1588 PTP receive second
+						      counter */
+#define XEMACPS_PTP_RXNANOSEC_OFFSET 0x000001ECU /**< 1588 PTP receive
+						      nanosecond counter */
+#define XEMACPS_PTPP_TXSEC_OFFSET    0x000001F0U /**< 1588 PTP peer transmit
+						      second counter */
+#define XEMACPS_PTPP_TXNANOSEC_OFFSET 0x000001F4U /**< 1588 PTP peer transmit
+						      nanosecond counter */
+#define XEMACPS_PTPP_RXSEC_OFFSET    0x000001F8U /**< 1588 PTP peer receive
+						      second counter */
+#define XEMACPS_PTPP_RXNANOSEC_OFFSET 0x000001FCU /**< 1588 PTP peer receive
+						      nanosecond counter */
+
+#define XEMACPS_INTQ1_STS_OFFSET     0x00000400U /**< Interrupt Q1 Status
+							reg */
+#define XEMACPS_TXQ1BASE_OFFSET	     0x00000440U /**< TX Q1 Base address
+							reg */
+#define XEMACPS_RXQ1BASE_OFFSET	     0x00000480U /**< RX Q1 Base address
+							reg */
+#define XEMACPS_MSBBUF_TXQBASE_OFFSET  0x000004C8U /**< MSB Buffer TX Q Base
+							reg */
+#define XEMACPS_MSBBUF_RXQBASE_OFFSET  0x000004D4U /**< MSB Buffer RX Q Base
+							reg */
+#define XEMACPS_INTQ1_IER_OFFSET     0x00000600U /**< Interrupt Q1 Enable
+							reg */
+#define XEMACPS_INTQ1_IDR_OFFSET     0x00000620U /**< Interrupt Q1 Disable
+							reg */
+#define XEMACPS_INTQ1_IMR_OFFSET     0x00000640U /**< Interrupt Q1 Mask
+							reg */
+
+/* Define some bit positions for registers. */
+
+/** @name network control register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCTRL_FLUSH_DPRAM_MASK	0x00040000U /**< Flush a packet from
+							Rx SRAM */
+#define XEMACPS_NWCTRL_ZEROPAUSETX_MASK 0x00000800U /**< Transmit zero quantum
+                                                         pause frame */
+#define XEMACPS_NWCTRL_PAUSETX_MASK     0x00000800U /**< Transmit pause frame */
+#define XEMACPS_NWCTRL_HALTTX_MASK      0x00000400U /**< Halt transmission
+                                                         after current frame */
+#define XEMACPS_NWCTRL_STARTTX_MASK     0x00000200U /**< Start tx (tx_go) */
+
+#define XEMACPS_NWCTRL_STATWEN_MASK     0x00000080U /**< Enable writing to
+                                                         stat counters */
+#define XEMACPS_NWCTRL_STATINC_MASK     0x00000040U /**< Increment statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_STATCLR_MASK     0x00000020U /**< Clear statistic
+                                                         registers */
+#define XEMACPS_NWCTRL_MDEN_MASK        0x00000010U /**< Enable MDIO port */
+#define XEMACPS_NWCTRL_TXEN_MASK        0x00000008U /**< Enable transmit */
+#define XEMACPS_NWCTRL_RXEN_MASK        0x00000004U /**< Enable receive */
+#define XEMACPS_NWCTRL_LOOPEN_MASK      0x00000002U /**< local loopback */
+/*@}*/
+
+/** @name network configuration register bit definitions
+ * @{
+ */
+#define XEMACPS_NWCFG_BADPREAMBEN_MASK 0x20000000U /**< disable rejection of
+                                                        non-standard preamble */
+#define XEMACPS_NWCFG_IPDSTRETCH_MASK  0x10000000U /**< enable transmit IPG */
+#define XEMACPS_NWCFG_SGMIIEN_MASK     0x08000000U /**< SGMII Enable */
+#define XEMACPS_NWCFG_FCSIGNORE_MASK   0x04000000U /**< disable rejection of
+                                                        FCS error */
+#define XEMACPS_NWCFG_HDRXEN_MASK      0x02000000U /**< RX half duplex */
+#define XEMACPS_NWCFG_RXCHKSUMEN_MASK  0x01000000U /**< enable RX checksum
+                                                        offload */
+#define XEMACPS_NWCFG_PAUSECOPYDI_MASK 0x00800000U /**< Do not copy pause
+                                                        Frames to memory */
+#define XEMACPS_NWCFG_DWIDTH_64_MASK   0x00200000U /**< 64 bit Data bus width */
+#define XEMACPS_NWCFG_MDC_SHIFT_MASK   18U	   /**< shift bits for MDC */
+#define XEMACPS_NWCFG_MDCCLKDIV_MASK   0x001C0000U /**< MDC Mask PCLK divisor */
+#define XEMACPS_NWCFG_FCSREM_MASK      0x00020000U /**< Discard FCS from
+                                                        received frames */
+#define XEMACPS_NWCFG_LENERRDSCRD_MASK 0x00010000U
+/**< RX length error discard */
+#define XEMACPS_NWCFG_RXOFFS_MASK      0x0000C000U /**< RX buffer offset */
+#define XEMACPS_NWCFG_PAUSEEN_MASK     0x00002000U /**< Enable pause RX */
+#define XEMACPS_NWCFG_RETRYTESTEN_MASK 0x00001000U /**< Retry test */
+#define XEMACPS_NWCFG_XTADDMACHEN_MASK 0x00000200U
+/**< External address match enable */
+#define XEMACPS_NWCFG_PCSSEL_MASK      0x00000800U /**< PCS Select */
+#define XEMACPS_NWCFG_1000_MASK        0x00000400U /**< 1000 Mbps */
+#define XEMACPS_NWCFG_1536RXEN_MASK    0x00000100U /**< Enable 1536 byte
+                                                        frames reception */
+#define XEMACPS_NWCFG_UCASTHASHEN_MASK 0x00000080U /**< Receive unicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_MCASTHASHEN_MASK 0x00000040U /**< Receive multicast hash
+                                                        frames */
+#define XEMACPS_NWCFG_BCASTDI_MASK     0x00000020U /**< Do not receive
+                                                        broadcast frames */
+#define XEMACPS_NWCFG_COPYALLEN_MASK   0x00000010U /**< Copy all frames */
+#define XEMACPS_NWCFG_JUMBO_MASK       0x00000008U /**< Jumbo frames */
+#define XEMACPS_NWCFG_NVLANDISC_MASK   0x00000004U /**< Receive only VLAN
+                                                        frames */
+#define XEMACPS_NWCFG_FDEN_MASK        0x00000002U/**< full duplex */
+#define XEMACPS_NWCFG_100_MASK         0x00000001U /**< 100 Mbps */
+#define XEMACPS_NWCFG_RESET_MASK       0x00080000U/**< reset value */
+/*@}*/
+
+/** @name network status register bit definitaions
+ * @{
+ */
+#define XEMACPS_NWSR_MDIOIDLE_MASK     0x00000004U /**< PHY management idle */
+#define XEMACPS_NWSR_MDIO_MASK         0x00000002U /**< Status of mdio_in */
+/*@}*/
+
+
+/** @name MAC address register word 1 mask
+ * @{
+ */
+#define XEMACPS_LADDR_MACH_MASK        0x0000FFFFU /**< Address bits[47:32]
+                                                      bit[31:0] are in BOTTOM */
+/*@}*/
+
+
+/** @name DMA control register bit definitions
+ * @{
+ */
+#define XEMACPS_DMACR_ADDR_WIDTH_64		0x40000000U /**< 64 bit address bus */
+#define XEMACPS_DMACR_TXEXTEND_MASK		0x20000000U /**< Tx Extended desc mode */
+#define XEMACPS_DMACR_RXEXTEND_MASK		0x10000000U /**< Rx Extended desc mode */
+#define XEMACPS_DMACR_RXBUF_MASK		0x00FF0000U /**< Mask bit for RX buffer
+													size */
+#define XEMACPS_DMACR_RXBUF_SHIFT 		16U	/**< Shift bit for RX buffer
+												size */
+#define XEMACPS_DMACR_TCPCKSUM_MASK		0x00000800U /**< enable/disable TX
+													    checksum offload */
+#define XEMACPS_DMACR_TXSIZE_MASK		0x00000400U /**< TX buffer memory size */
+#define XEMACPS_DMACR_RXSIZE_MASK		0x00000300U /**< RX buffer memory size */
+#define XEMACPS_DMACR_ENDIAN_MASK		0x00000080U /**< endian configuration */
+#define XEMACPS_DMACR_BLENGTH_MASK		0x0000001FU /**< buffer burst length */
+#define XEMACPS_DMACR_SINGLE_AHB_BURST	0x00000001U /**< single AHB bursts */
+#define XEMACPS_DMACR_INCR4_AHB_BURST	0x00000004U /**< 4 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR8_AHB_BURST	0x00000008U /**< 8 bytes AHB bursts */
+#define XEMACPS_DMACR_INCR16_AHB_BURST	0x00000010U /**< 16 bytes AHB bursts */
+/*@}*/
+
+/** @name transmit status register bit definitions
+ * @{
+ */
+#define XEMACPS_TXSR_HRESPNOK_MASK    0x00000100U /**< Transmit hresp not OK */
+#define XEMACPS_TXSR_URUN_MASK        0x00000040U /**< Transmit underrun */
+#define XEMACPS_TXSR_TXCOMPL_MASK     0x00000020U /**< Transmit completed OK */
+#define XEMACPS_TXSR_BUFEXH_MASK      0x00000010U /**< Transmit buffs exhausted
+                                                       mid frame */
+#define XEMACPS_TXSR_TXGO_MASK        0x00000008U /**< Status of go flag */
+#define XEMACPS_TXSR_RXOVR_MASK       0x00000004U /**< Retry limit exceeded */
+#define XEMACPS_TXSR_FRAMERX_MASK     0x00000002U /**< Collision tx frame */
+#define XEMACPS_TXSR_USEDREAD_MASK    0x00000001U /**< TX buffer used bit set */
+
+#define XEMACPS_TXSR_ERROR_MASK      ((u32)XEMACPS_TXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_TXSR_URUN_MASK | \
+                                       (u32)XEMACPS_TXSR_BUFEXH_MASK | \
+                                       (u32)XEMACPS_TXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_TXSR_FRAMERX_MASK | \
+                                       (u32)XEMACPS_TXSR_USEDREAD_MASK)
+/*@}*/
+
+/**
+ * @name receive status register bit definitions
+ * @{
+ */
+#define XEMACPS_RXSR_HRESPNOK_MASK    0x00000008U /**< Receive hresp not OK */
+#define XEMACPS_RXSR_RXOVR_MASK       0x00000004U /**< Receive overrun */
+#define XEMACPS_RXSR_FRAMERX_MASK     0x00000002U /**< Frame received OK */
+#define XEMACPS_RXSR_BUFFNA_MASK      0x00000001U /**< RX buffer used bit set */
+
+#define XEMACPS_RXSR_ERROR_MASK      ((u32)XEMACPS_RXSR_HRESPNOK_MASK | \
+                                       (u32)XEMACPS_RXSR_RXOVR_MASK | \
+                                       (u32)XEMACPS_RXSR_BUFFNA_MASK)
+/*@}*/
+
+/**
+ * @name Interrupt Q1 status register bit definitions
+ * @{
+ */
+#define XEMACPS_INTQ1SR_TXCOMPL_MASK	0x00000080U /**< Transmit completed OK */
+#define XEMACPS_INTQ1SR_TXERR_MASK	0x00000040U /**< Transmit AMBA Error */
+
+#define XEMACPS_INTQ1_IXR_ALL_MASK	((u32)XEMACPS_INTQ1SR_TXCOMPL_MASK | \
+					 (u32)XEMACPS_INTQ1SR_TXERR_MASK)
+
+/*@}*/
+
+/**
+ * @name interrupts bit definitions
+ * Bits definitions are same in XEMACPS_ISR_OFFSET,
+ * XEMACPS_IER_OFFSET, XEMACPS_IDR_OFFSET, and XEMACPS_IMR_OFFSET
+ * @{
+ */
+#define XEMACPS_IXR_PTPPSTX_MASK    0x02000000U /**< PTP Psync transmitted */
+#define XEMACPS_IXR_PTPPDRTX_MASK   0x01000000U /**< PTP Pdelay_req
+						     transmitted */
+#define XEMACPS_IXR_PTPSTX_MASK     0x00800000U /**< PTP Sync transmitted */
+#define XEMACPS_IXR_PTPDRTX_MASK    0x00400000U /**< PTP Delay_req transmitted
+						*/
+#define XEMACPS_IXR_PTPPSRX_MASK    0x00200000U /**< PTP Psync received */
+#define XEMACPS_IXR_PTPPDRRX_MASK   0x00100000U /**< PTP Pdelay_req received */
+#define XEMACPS_IXR_PTPSRX_MASK     0x00080000U /**< PTP Sync received */
+#define XEMACPS_IXR_PTPDRRX_MASK    0x00040000U /**< PTP Delay_req received */
+#define XEMACPS_IXR_PAUSETX_MASK    0x00004000U	/**< Pause frame transmitted */
+#define XEMACPS_IXR_PAUSEZERO_MASK  0x00002000U	/**< Pause time has reached
+                                                     zero */
+#define XEMACPS_IXR_PAUSENZERO_MASK 0x00001000U	/**< Pause frame received */
+#define XEMACPS_IXR_HRESPNOK_MASK   0x00000800U	/**< hresp not ok */
+#define XEMACPS_IXR_RXOVR_MASK      0x00000400U	/**< Receive overrun occurred */
+#define XEMACPS_IXR_TXCOMPL_MASK    0x00000080U	/**< Frame transmitted ok */
+#define XEMACPS_IXR_TXEXH_MASK      0x00000040U	/**< Transmit err occurred or
+                                                     no buffers*/
+#define XEMACPS_IXR_RETRY_MASK      0x00000020U	/**< Retry limit exceeded */
+#define XEMACPS_IXR_URUN_MASK       0x00000010U	/**< Transmit underrun */
+#define XEMACPS_IXR_TXUSED_MASK     0x00000008U	/**< Tx buffer used bit read */
+#define XEMACPS_IXR_RXUSED_MASK     0x00000004U	/**< Rx buffer used bit read */
+#define XEMACPS_IXR_FRAMERX_MASK    0x00000002U	/**< Frame received ok */
+#define XEMACPS_IXR_MGMNT_MASK      0x00000001U	/**< PHY management complete */
+#define XEMACPS_IXR_ALL_MASK        0x00007FFFU	/**< Everything! */
+
+#define XEMACPS_IXR_TX_ERR_MASK    ((u32)XEMACPS_IXR_TXEXH_MASK |         \
+                                     (u32)XEMACPS_IXR_RETRY_MASK |         \
+                                     (u32)XEMACPS_IXR_URUN_MASK)
+
+
+#define XEMACPS_IXR_RX_ERR_MASK    ((u32)XEMACPS_IXR_HRESPNOK_MASK |      \
+                                     (u32)XEMACPS_IXR_RXUSED_MASK |        \
+                                     (u32)XEMACPS_IXR_RXOVR_MASK)
+
+/*@}*/
+
+/** @name PHY Maintenance bit definitions
+ * @{
+ */
+#define XEMACPS_PHYMNTNC_OP_MASK    0x40020000U	/**< operation mask bits */
+#define XEMACPS_PHYMNTNC_OP_R_MASK  0x20000000U	/**< read operation */
+#define XEMACPS_PHYMNTNC_OP_W_MASK  0x10000000U	/**< write operation */
+#define XEMACPS_PHYMNTNC_ADDR_MASK  0x0F800000U	/**< Address bits */
+#define XEMACPS_PHYMNTNC_REG_MASK   0x007C0000U	/**< register bits */
+#define XEMACPS_PHYMNTNC_DATA_MASK  0x00000FFFU	/**< data bits */
+#define XEMACPS_PHYMNTNC_PHAD_SHFT_MSK   23U	/**< Shift bits for PHYAD */
+#define XEMACPS_PHYMNTNC_PREG_SHFT_MSK   18U	/**< Shift bits for PHREG */
+/*@}*/
+
+/* Transmit buffer descriptor status words offset
+ * @{
+ */
+#define XEMACPS_BD_ADDR_OFFSET  0x00000000U /**< word 0/addr of BDs */
+#define XEMACPS_BD_STAT_OFFSET  0x00000004U /**< word 1/status of BDs */
+#define XEMACPS_BD_ADDR_HI_OFFSET  0x00000008U /**< word 2/addr of BDs */
+
+/*
+ * @}
+ */
+
+/* Transmit buffer descriptor status words bit positions.
+ * Transmit buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit address pointing to the location of
+ * the transmit data.
+ * The following register - word1, consists of various information to control
+ * the XEmacPs transmit process.  After transmit, this is updated with status
+ * information, whether the frame was transmitted OK or why it had failed.
+ * @{
+ */
+#define XEMACPS_TXBUF_USED_MASK  0x80000000U /**< Used bit. */
+#define XEMACPS_TXBUF_WRAP_MASK  0x40000000U /**< Wrap bit, last descriptor */
+#define XEMACPS_TXBUF_RETRY_MASK 0x20000000U /**< Retry limit exceeded */
+#define XEMACPS_TXBUF_URUN_MASK  0x10000000U /**< Transmit underrun occurred */
+#define XEMACPS_TXBUF_EXH_MASK   0x08000000U /**< Buffers exhausted */
+#define XEMACPS_TXBUF_TCP_MASK   0x04000000U /**< Late collision. */
+#define XEMACPS_TXBUF_NOCRC_MASK 0x00010000U /**< No CRC */
+#define XEMACPS_TXBUF_LAST_MASK  0x00008000U /**< Last buffer */
+#define XEMACPS_TXBUF_LEN_MASK   0x00003FFFU /**< Mask for length field */
+/*
+ * @}
+ */
+
+/* Receive buffer descriptor status words bit positions.
+ * Receive buffer descriptor consists of two 32-bit registers,
+ * the first - word0 contains a 32-bit word aligned address pointing to the
+ * address of the buffer. The lower two bits make up the wrap bit indicating
+ * the last descriptor and the ownership bit to indicate it has been used by
+ * the XEmacPs.
+ * The following register - word1, contains status information regarding why
+ * the frame was received (the filter match condition) as well as other
+ * useful info.
+ * @{
+ */
+#define XEMACPS_RXBUF_BCAST_MASK     0x80000000U /**< Broadcast frame */
+#define XEMACPS_RXBUF_MULTIHASH_MASK 0x40000000U /**< Multicast hashed frame */
+#define XEMACPS_RXBUF_UNIHASH_MASK   0x20000000U /**< Unicast hashed frame */
+#define XEMACPS_RXBUF_EXH_MASK       0x08000000U /**< buffer exhausted */
+#define XEMACPS_RXBUF_AMATCH_MASK    0x06000000U /**< Specific address
+                                                      matched */
+#define XEMACPS_RXBUF_IDFOUND_MASK   0x01000000U /**< Type ID matched */
+#define XEMACPS_RXBUF_IDMATCH_MASK   0x00C00000U /**< ID matched mask */
+#define XEMACPS_RXBUF_VLAN_MASK      0x00200000U /**< VLAN tagged */
+#define XEMACPS_RXBUF_PRI_MASK       0x00100000U /**< Priority tagged */
+#define XEMACPS_RXBUF_VPRI_MASK      0x000E0000U /**< Vlan priority */
+#define XEMACPS_RXBUF_CFI_MASK       0x00010000U /**< CFI frame */
+#define XEMACPS_RXBUF_EOF_MASK       0x00008000U /**< End of frame. */
+#define XEMACPS_RXBUF_SOF_MASK       0x00004000U /**< Start of frame. */
+#define XEMACPS_RXBUF_LEN_MASK       0x00001FFFU /**< Mask for length field */
+#define XEMACPS_RXBUF_LEN_JUMBO_MASK 0x00003FFFU /**< Mask for jumbo length */
+
+#define XEMACPS_RXBUF_WRAP_MASK      0x00000002U /**< Wrap bit, last BD */
+#define XEMACPS_RXBUF_NEW_MASK       0x00000001U /**< Used bit.. */
+#define XEMACPS_RXBUF_ADD_MASK       0xFFFFFFFCU /**< Mask for address */
+/*
+ * @}
+ */
+
+/*
+ * Define appropriate I/O access method to memory mapped I/O or other
+ * interface if necessary.
+ */
+
+#define XEmacPs_In32  Xil_In32
+#define XEmacPs_Out32 Xil_Out32
+
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XEmacPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XEmacPs_ReadReg(BaseAddress, RegOffset) \
+    XEmacPs_In32((BaseAddress) + (u32)(RegOffset))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param    BaseAddress is the base address of the device
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XEmacPs_WriteReg(u32 BaseAddress, u32 RegOffset,
+*         u32 Data)
+*
+*****************************************************************************/
+#define XEmacPs_WriteReg(BaseAddress, RegOffset, Data) \
+    XEmacPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes *****************************/
+/*
+ * Perform reset operation to the emacps interface
+ */
+void XEmacPs_ResetHw(u32 BaseAddr);
+
+#ifdef __cplusplus
+  }
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_intr.c
new file mode 100644
index 000000000..59636c4ef
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_intr.c
@@ -0,0 +1,268 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_intr.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* Functions in this file implement general purpose interrupt processing related
+* functionality. See xemacps.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 First release
+* 1.03a asa  01/24/13 Fix for CR #692702 which updates error handling for
+*		      Rx errors. Under heavy Rx traffic, there will be a large
+*		      number of errors related to receive buffer not available.
+*		      Because of a HW bug (SI #692601), under such heavy errors,
+*		      the Rx data path can become unresponsive. To reduce the
+*		      probabilities for hitting this HW bug, the SW writes to
+*		      bit 18 to flush a packet from Rx DPRAM immediately. The
+*		      changes for it are done in the function
+*		      XEmacPs_IntrHandler.
+* 2.1   srt  07/15/14 Add support for Zynq Ultrascale Mp GEM specification
+*		       and 64-bit changes.
+* 3.0   kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1   hk   07/27/15 Do not call error handler with '0' error code when
+*                     there is no error. CR# 869403
+* 

+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+ * Install an asynchronious handler function for the given HandlerType:
+ *
+ * @param InstancePtr is a pointer to the instance to be worked on.
+ * @param HandlerType indicates what interrupt handler type is.
+ *        XEMACPS_HANDLER_DMASEND, XEMACPS_HANDLER_DMARECV and
+ *        XEMACPS_HANDLER_ERROR.
+ * @param FuncPointer is the pointer to the callback function
+ * @param CallBackRef is the upper layer callback reference passed back when
+ *        when the callback function is invoked.
+ *
+ * @return
+ *
+ * None.
+ *
+ * @note
+ * There is no assert on the CallBackRef since the driver doesn't know what
+ * it is.
+ *
+ *****************************************************************************/
+LONG XEmacPs_SetHandler(XEmacPs *InstancePtr, u32 HandlerType,
+			void *FuncPointer, void *CallBackRef)
+{
+	LONG Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FuncPointer != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	switch (HandlerType) {
+	case XEMACPS_HANDLER_DMASEND:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->SendHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->SendRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_DMARECV:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->RecvHandler = ((XEmacPs_Handler)(void *)FuncPointer);
+		InstancePtr->RecvRef = CallBackRef;
+		break;
+	case XEMACPS_HANDLER_ERROR:
+		Status = (LONG)(XST_SUCCESS);
+		InstancePtr->ErrorHandler = ((XEmacPs_ErrHandler)(void *)FuncPointer);
+		InstancePtr->ErrorRef = CallBackRef;
+		break;
+	default:
+		Status = (LONG)(XST_INVALID_PARAM);
+		break;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* Master interrupt handler for EMAC driver. This routine will query the
+* status of the device, bump statistics, and invoke user callbacks.
+*
+* This routine must be connected to an interrupt controller using OS/BSP
+* specific methods.
+*
+* @param XEmacPsPtr is a pointer to the XEMACPS instance that has caused the
+*        interrupt.
+*
+******************************************************************************/
+void XEmacPs_IntrHandler(void *XEmacPsPtr)
+{
+	u32 RegISR;
+	u32 RegSR;
+	u32 RegCtrl;
+	u32 RegQ1ISR = 0U;
+	XEmacPs *InstancePtr = (XEmacPs *) XEmacPsPtr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/* This ISR will try to handle as many interrupts as it can in a single
+	 * call. However, in most of the places where the user's error handler
+         * is called, this ISR exits because it is expected that the user will
+         * reset the device in nearly all instances.
+	 */
+	RegISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_ISR_OFFSET);
+
+	/* Read Transmit Q1 ISR */
+
+	if (InstancePtr->Version > 2)
+		RegQ1ISR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET);
+
+	/* Clear the interrupt status register */
+	XEmacPs_WriteReg(InstancePtr->Config.BaseAddress, XEMACPS_ISR_OFFSET,
+			   RegISR);
+
+	/* Receive complete interrupt */
+	if ((RegISR & XEMACPS_IXR_FRAMERX_MASK) != 0x00000000U) {
+		/* Clear RX status register RX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET,
+				   ((u32)XEMACPS_RXSR_FRAMERX_MASK |
+				   (u32)XEMACPS_RXSR_BUFFNA_MASK));
+		InstancePtr->RecvHandler(InstancePtr->RecvRef);
+	}
+
+	/* Transmit Q1 complete interrupt */
+	if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET,
+				   XEMACPS_INTQ1SR_TXCOMPL_MASK);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Transmit complete interrupt */
+	if ((RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U) {
+		/* Clear TX status register TX complete indication but preserve
+		 * error bits if there is any */
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET,
+				   ((u32)XEMACPS_TXSR_TXCOMPL_MASK |
+				   (u32)XEMACPS_TXSR_USEDREAD_MASK));
+		InstancePtr->SendHandler(InstancePtr->SendRef);
+	}
+
+	/* Receive error conditions interrupt */
+	if ((RegISR & XEMACPS_IXR_RX_ERR_MASK) != 0x00000000U) {
+		/* Clear RX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_RXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_RXSR_OFFSET, RegSR);
+
+		/* Fix for CR # 692702. Write to bit 18 of net_ctrl
+		 * register to flush a packet out of Rx SRAM upon
+		 * an error for receive buffer not available. */
+		if ((RegISR & XEMACPS_IXR_RXUSED_MASK) != 0x00000000U) {
+			RegCtrl =
+			XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XEMACPS_NWCTRL_OFFSET);
+			RegCtrl |= (u32)XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+					XEMACPS_NWCTRL_OFFSET, RegCtrl);
+		}
+
+		if(RegSR != 0) {
+			InstancePtr->ErrorHandler(InstancePtr->ErrorRef,
+						XEMACPS_RECV, RegSR);
+		}
+	}
+
+        /* When XEMACPS_IXR_TXCOMPL_MASK is flaged, XEMACPS_IXR_TXUSED_MASK
+         * will be asserted the same time.
+         * Have to distinguish this bit to handle the real error condition.
+         */
+	/* Transmit Q1 error conditions interrupt */
+        if ((InstancePtr->Version > 2) &&
+			((RegQ1ISR & XEMACPS_INTQ1SR_TXERR_MASK) != 0x00000000U) &&
+            ((RegQ1ISR & XEMACPS_INTQ1SR_TXCOMPL_MASK) != 0x00000000U)) {
+			/* Clear Interrupt Q1 status register */
+			XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_INTQ1_STS_OFFSET, RegQ1ISR);
+			InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegQ1ISR);
+	   }
+
+	/* Transmit error conditions interrupt */
+        if (((RegISR & XEMACPS_IXR_TX_ERR_MASK) != 0x00000000U) &&
+            (!(RegISR & XEMACPS_IXR_TXCOMPL_MASK) != 0x00000000U)) {
+		/* Clear TX status register */
+		RegSR = XEmacPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XEMACPS_TXSR_OFFSET);
+		XEmacPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XEMACPS_TXSR_OFFSET, RegSR);
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, XEMACPS_SEND,
+					  RegSR);
+	}
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_sinit.c
new file mode 100644
index 000000000..1bc5b3b19
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/emacps_v3_2/src/xemacps_sinit.c
@@ -0,0 +1,97 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xemacps_sinit.c
+* @addtogroup emacps_v3_1
+* @{
+*
+* This file contains lookup method by device ID when success, it returns
+* pointer to config table to be used to initialize the device.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a wsy  01/10/10 New
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xemacps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/*************************** Variable Definitions *****************************/
+extern XEmacPs_Config XEmacPs_ConfigTable[XPAR_XEMACPS_NUM_INSTANCES];
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID.  The table
+* contains the configuration info for each device in the system.
+*
+* @param DeviceId is the unique device ID of the device being looked up.
+*
+* @return
+* A pointer to the configuration table entry corresponding to the given
+* device ID, or NULL if no match is found.
+*
+******************************************************************************/
+XEmacPs_Config *XEmacPs_LookupConfig(u16 DeviceId)
+{
+	XEmacPs_Config *CfgPtr = NULL;
+	u32 i;
+
+	for (i = 0U; i < (u32)XPAR_XEMACPS_NUM_INSTANCES; i++) {
+		if (XEmacPs_ConfigTable[i].DeviceId == DeviceId) {
+			CfgPtr = &XEmacPs_ConfigTable[i];
+			break;
+		}
+	}
+
+	return (XEmacPs_Config *)(CfgPtr);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/Makefile
new file mode 100644
index 000000000..8601ce4c7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xgpiops_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling gpiops"
+
+xgpiops_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xgpiops_includes
+
+xgpiops_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.c
new file mode 100644
index 000000000..90eedb87d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.c
@@ -0,0 +1,628 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.c
+* @addtogroup gpiops_v3_1
+* @{
+*
+* The XGpioPs driver. Functions in this file are the minimum required functions
+* for this driver. See xgpiops.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device. The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XGpioPs instance/driver.
+* All members of the XGpioPs instance structure are initialized and
+* StubHandlers are assigned to the Bank Status Handlers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	ConfigPtr points to the XGpioPs device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address should be passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return	XST_SUCCESS always.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status = XST_SUCCESS;
+	u8 i;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddr != (u32)0);
+	/*
+	 * Set some default values for instance data, don't indicate the device
+	 * is ready to use until everything has been initialized successfully.
+	 */
+	InstancePtr->IsReady = 0U;
+	InstancePtr->GpioConfig.BaseAddr = EffectiveAddr;
+	InstancePtr->GpioConfig.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Handler = StubHandler;
+	InstancePtr->Platform = XGetPlatform_Info();
+
+	/* Initialize the Bank data based on platform */
+	if (InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/*
+		 *	Max pins in the ZynqMP GPIO device
+		 *	0 - 25,  Bank 0
+		 *	26 - 51, Bank 1
+		 *	52 - 77, Bank 2
+		 *	78 - 109, Bank 3
+		 *	110 - 141, Bank 4
+		 *	142 - 173, Bank 5
+		 */
+		InstancePtr->MaxPinNum = (u32)174;
+		InstancePtr->MaxBanks = (u8)6;
+	} else {
+		/*
+		 *	Max pins in the GPIO device
+		 *	0 - 31,  Bank 0
+		 *	32 - 53, Bank 1
+		 *	54 - 85, Bank 2
+		 *	86 - 117, Bank 3
+		 */
+		InstancePtr->MaxPinNum = (u32)118;
+		InstancePtr->MaxBanks = (u8)4;
+	}
+
+	/*
+	 * By default, interrupts are not masked in GPIO. Disable
+	 * interrupts for all pins in all the 4 banks.
+	 */
+	for (i=0;iMaxBanks;i++) {
+		XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+					  ((u32)(i) * XGPIOPS_REG_MASK_OFFSET) +
+					  XGPIOPS_INTDIS_OFFSET, 0xFFFFFFFFU);
+	}
+
+	/* Indicate the component is now ready to use. */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Read the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	Current value of the Data register.
+*
+* @note		This function is used for reading the state of all the GPIO pins
+*		of specified bank.
+*
+*****************************************************************************/
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Read Data from the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the data has to be read.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*		See xgpiops.h for the mapping of the pin numbers in the banks.
+*
+* @return	Current value of the Pin (0 or 1).
+*
+* @note		This function is used for reading the state of the specified
+*		GPIO pin.
+*
+*****************************************************************************/
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_RO_OFFSET) >> (u32)PinNumber) & (u32)1;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Write to the Data register of the specified GPIO bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Data is the value to be written to the Data register.
+*
+* @return	None.
+*
+* @note		This function is used for writing to all the GPIO pins of
+*		the bank. The previous state of the pins is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_DATA_BANK_OFFSET) +
+			  XGPIOPS_DATA_OFFSET, Data);
+}
+
+/****************************************************************************/
+/**
+*
+* Write data to the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	Data is the data to be written to the specified pin (0 or 1).
+*
+* @return	None.
+*
+* @note		This function does a masked write to the specified pin of
+*		the specified GPIO bank. The previous state of other pins
+*		is maintained.
+*
+*****************************************************************************/
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data)
+{
+	u32 RegOffset;
+	u32 Value;
+	u8 Bank;
+	u8 PinNumber;
+	u32 DataVar = Data;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	if (PinNumber > 15U) {
+		/* There are only 16 data bits in bit maskable register. */
+		PinNumber -= (u8)16;
+		RegOffset = XGPIOPS_DATA_MSW_OFFSET;
+	} else {
+		RegOffset = XGPIOPS_DATA_LSW_OFFSET;
+	}
+
+	/*
+	 * Get the 32 bit value to be written to the Mask/Data register where
+	 * the upper 16 bits is the mask and lower 16 bits is the data.
+	 */
+	DataVar &= (u32)0x01;
+	Value = ~((u32)1 << (PinNumber + 16U)) & ((DataVar << PinNumber) | 0xFFFF0000U);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_DATA_MASK_OFFSET) +
+			  RegOffset, Value);
+}
+
+
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Direction is the 32 bit mask of the Pin direction to be set for
+*		all the pins in the Bank. Bits with 0 are set to Input mode,
+*		bits with 1 are	set to Output Mode.
+*
+* @return	None.
+*
+* @note		This function is used for setting the direction of all the pins
+*		in the specified bank. The previous state of the pins is
+*		not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_DIRM_OFFSET, Direction);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	Direction is the direction to be set for the specified pin.
+*		Valid values are 0 for Input Direction, 1 for Output Direction.
+*
+* @return	None.
+*
+*****************************************************************************/
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 DirModeReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(Direction <= (u32)1);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	DirModeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_DIRM_OFFSET);
+
+	if (Direction!=(u32)0) { /*  Output Direction */
+		DirModeReg |= ((u32)1 << (u32)PinNumber);
+	} else { /* Input Direction */
+		DirModeReg &= ~ ((u32)1 << (u32)PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			 XGPIOPS_DIRM_OFFSET, DirModeReg);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* return	Returns a 32 bit mask of the Direction register. Bits with 0 are
+*		in Input mode, bits with 1 are in Output Mode.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_DIRM_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Direction of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Direction is to be
+*		retrieved.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	Direction of the specified pin.
+*		- 0 for Input Direction
+*		- 1 for Output Direction
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	OpEnable is the 32 bit mask of the Output Enables to be set for
+*		all the pins in the Bank. The Output Enable of bits with 0 are
+*		disabled, the Output Enable of bits with 1 are enabled.
+*
+* @return	None.
+*
+* @note		This function is used for setting the Output Enables of all the
+*		pins in the specified bank. The previous state of the Output
+*		Enables is not maintained.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnable);
+}
+
+/****************************************************************************/
+/**
+*
+* Set the Output Enable of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number to which the Data is to be written.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	OpEnable specifies whether the Output Enable for the specified
+*		pin should be enabled.
+*		Valid values are 0 for Disabling Output Enable,
+*		1 for Enabling Output Enable.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 OpEnableReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(OpEnable <= (u32)1);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	OpEnableReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_OUTEN_OFFSET);
+
+	if (OpEnable != (u32)0) { /*  Enable Output Enable */
+		OpEnableReg |= ((u32)1 << (u32)PinNumber);
+	} else { /* Disable Output Enable */
+		OpEnableReg &= ~ ((u32)1 << (u32)PinNumber);
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_OUTEN_OFFSET, OpEnableReg);
+}
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the pins of the specified GPIO Bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* return	Returns a a 32 bit mask of the Output Enable register.
+*		Bits with 0 are in Disabled state, bits with 1 are in
+*		Enabled State.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_OUTEN_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* Get the Output Enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the Output Enable status is to
+*		be retrieved.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	Output Enable of the specified pin.
+*		- 0 if Output Enable is disabled for this pin
+*		- 1 if Output Enable is enabled for this pin
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	return (XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET) >> (u32)PinNumber) & (u32)1;
+}
+
+/****************************************************************************/
+/*
+*
+* Get the Bank number and the Pin number in the Bank, for the given PinNumber
+* in the GPIO device.
+*
+* @param	PinNumber is the Pin number in the GPIO device.
+* @param	BankNumber returns the Bank in which this GPIO pin is present.
+*		Valid values are 0 to XGPIOPS_MAX_BANKS - 1.
+* @param	PinNumberInBank returns the Pin Number within the Bank.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetBankPin(u8 PinNumber, u8 *BankNumber, u8 *PinNumberInBank)
+{
+	u32 XGpioPsPinTable[6] = {0};
+	u32 Platform = XGetPlatform_Info();
+
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/*
+		 * This structure defines the mapping of the pin numbers to the banks when
+		 * the driver APIs are used for working on the individual pins.
+		 */
+
+		XGpioPsPinTable[0] = (u32)25; /* 0 - 25, Bank 0 */
+		XGpioPsPinTable[1] = (u32)51; /* 26 - 51, Bank 1 */
+		XGpioPsPinTable[2] = (u32)77; /* 52 - 77, Bank 2 */
+		XGpioPsPinTable[3] = (u32)109; /* 78 - 109, Bank 3 */
+		XGpioPsPinTable[4] = (u32)141; /* 110 - 141, Bank 4 */
+		XGpioPsPinTable[5] = (u32)173; /* 142 - 173 Bank 5 */
+
+		*BankNumber = 0U;
+		while (*BankNumber < 6U) {
+			if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+				break;
+			}
+			(*BankNumber)++;
+		}
+	} else {
+		XGpioPsPinTable[0] = (u32)31; /* 0 - 31, Bank 0 */
+		XGpioPsPinTable[1] = (u32)53; /* 32 - 53, Bank 1 */
+		XGpioPsPinTable[2] = (u32)85; /* 54 - 85, Bank 2 */
+		XGpioPsPinTable[3] = (u32)117; /* 86 - 117 Bank 3 */
+
+		*BankNumber = 0U;
+		while (*BankNumber < 4U) {
+			if (PinNumber <= XGpioPsPinTable[*BankNumber]) {
+				break;
+			}
+			(*BankNumber)++;
+		}
+	}
+	if (*BankNumber == (u8)0) {
+		*PinNumberInBank = PinNumber;
+	} else {
+		*PinNumberInBank = (u8)((u32)PinNumber %
+					(XGpioPsPinTable[*BankNumber - (u8)1] + (u32)1));
+	}
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.h
new file mode 100644
index 000000000..102615572
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops.h
@@ -0,0 +1,268 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops.h
+* @addtogroup gpiops_v3_1
+* @{
+* @details
+*
+* The Xilinx PS GPIO driver. This driver supports the Xilinx PS GPIO
+* Controller.
+*
+* The GPIO Controller supports the following features:
+*	- 4 banks
+*	- Masked writes (There are no masked reads)
+*	- Bypass mode
+*	- Configurable Interrupts (Level/Edge)
+*
+* This driver is intended to be RTOS and processor independent. Any needs for
+* dynamic memory management, threads or thread mutual exclusion, virtual
+* memory, or cache control must be satisfied by the layer above this driver.
+
+* This driver supports all the features listed above, if applicable.
+*
+* Driver Description
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the GPIO.
+*
+* Interrupts
+*
+* The driver provides interrupt management functions and an interrupt handler.
+* Users of this driver need to provide callback functions. An interrupt handler
+* example is available with the driver.
+*
+* Threads
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+* Asserts
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+* Building the driver
+*
+* The XGpioPs driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+* 


+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.01a sv   04/15/12 Removed the APIs XGpioPs_SetMode, XGpioPs_SetModePin
+*                     XGpioPs_GetMode, XGpioPs_GetModePin as they are not
+*		      relevant to Zynq device.The interrupts are disabled
+*		      for output pins on all banks during initialization.
+* 1.02a hk   08/22/13 Added low level reset API
+* 2.1   hk   04/29/14 Use Input data register DATA_RO for read. CR# 771667.
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to APIs. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+* 

+*
+******************************************************************************/
+#ifndef XGPIOPS_H		/* prevent circular inclusions */
+#define XGPIOPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xgpiops_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Interrupt types
+ *  @{
+ * The following constants define the interrupt types that can be set for each
+ * GPIO pin.
+ */
+#define XGPIOPS_IRQ_TYPE_EDGE_RISING	0x00U  /**< Interrupt on Rising edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_FALLING	0x01U  /**< Interrupt Falling edge */
+#define XGPIOPS_IRQ_TYPE_EDGE_BOTH	0x02U  /**< Interrupt on both edges */
+#define XGPIOPS_IRQ_TYPE_LEVEL_HIGH	0x03U  /**< Interrupt on high level */
+#define XGPIOPS_IRQ_TYPE_LEVEL_LOW	0x04U  /**< Interrupt on low level */
+/*@}*/
+
+#define XGPIOPS_BANK_MAX_PINS		(u32)32 /**< Max pins in a GPIO bank */
+#define XGPIOPS_BANK0			0x00U  /**< GPIO Bank 0 */
+#define XGPIOPS_BANK1			0x01U  /**< GPIO Bank 1 */
+#define XGPIOPS_BANK2			0x02U  /**< GPIO Bank 2 */
+#define XGPIOPS_BANK3			0x03U  /**< GPIO Bank 3 */
+
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_BANK4			0x04U  /**< GPIO Bank 4 */
+#define XGPIOPS_BANK5			0x05U  /**< GPIO Bank 5 */
+#endif
+
+#define XGPIOPS_MAX_BANKS_ZYNQMP		0x06U  /**< Max banks in a
+										*	Zynq Ultrascale+ MP GPIO device
+										*/
+#define XGPIOPS_MAX_BANKS		0x04U  /**< Max banks in a Zynq GPIO device */
+
+#define XGPIOPS_DEVICE_MAX_PIN_NUM_ZYNQMP	(u32)174 /**< Max pins in the
+						  *	Zynq Ultrascale+ MP GPIO device
+					      * 0 - 25,  Bank 0
+					      * 26 - 51, Bank 1
+					      *	52 - 77, Bank 2
+					      *	78 - 109, Bank 3
+					      *	110 - 141, Bank 4
+					      *	142 - 173, Bank 5
+					      */
+#define XGPIOPS_DEVICE_MAX_PIN_NUM	(u32)118 /**< Max pins in the Zynq GPIO device
+					      * 0 - 31,  Bank 0
+					      * 32 - 53, Bank 1
+					      *	54 - 85, Bank 2
+					      *	86 - 117, Bank 3
+					      */
+
+/**************************** Type Definitions *******************************/
+
+/****************************************************************************/
+/**
+ * This handler data type allows the user to define a callback function to
+ * handle the interrupts for the GPIO device. The application using this
+ * driver is expected to define a handler of this type, to support interrupt
+ * driven mode. The handler executes in an interrupt context such that minimal
+ * processing should be performed.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the callback functions for a GPIO bank. It is
+ *		passed back to the upper layer when the callback is invoked. Its
+ *		type is not important to the driver component, so it is a void
+ *		pointer.
+ * @param	Bank is the bank for which the interrupt status has changed.
+ * @param	Status is the Interrupt status of the GPIO bank.
+ *
+ *****************************************************************************/
+typedef void (*XGpioPs_Handler) (void *CallBackRef, u32 Bank, u32 Status);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Register base address */
+} XGpioPs_Config;
+
+/**
+ * The XGpioPs driver instance data. The user is required to allocate a
+ * variable of this type for the GPIO device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XGpioPs_Config GpioConfig;	/**< Device configuration */
+	u32 IsReady;			/**< Device is initialized and ready */
+	XGpioPs_Handler Handler;	/**< Status handlers for all banks */
+	void *CallBackRef; 		/**< Callback ref for bank handlers */
+	u32 Platform;			/**< Platform data */
+	u32 MaxPinNum;			/**< Max pins in the GPIO device */
+	u8 MaxBanks;			/**< Max banks in a GPIO device */
+} XGpioPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xgpiops.c */
+s32 XGpioPs_CfgInitialize(XGpioPs *InstancePtr, XGpioPs_Config *ConfigPtr,
+			   u32 EffectiveAddr);
+
+/* Bank APIs in xgpiops.c */
+u32 XGpioPs_Read(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_Write(XGpioPs *InstancePtr, u8 Bank, u32 Data);
+void XGpioPs_SetDirection(XGpioPs *InstancePtr, u8 Bank, u32 Direction);
+u32 XGpioPs_GetDirection(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_SetOutputEnable(XGpioPs *InstancePtr, u8 Bank, u32 OpEnable);
+u32 XGpioPs_GetOutputEnable(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_GetBankPin(u8 PinNumber,	u8 *BankNumber, u8 *PinNumberInBank);
+
+/* Pin APIs in xgpiops.c */
+u32 XGpioPs_ReadPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_WritePin(XGpioPs *InstancePtr, u32 Pin, u32 Data);
+void XGpioPs_SetDirectionPin(XGpioPs *InstancePtr, u32 Pin, u32 Direction);
+u32 XGpioPs_GetDirectionPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_SetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin, u32 OpEnable);
+u32 XGpioPs_GetOutputEnablePin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Diagnostic functions in xgpiops_selftest.c */
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr);
+
+/* Functions in xgpiops_intr.c */
+/* Bank APIs in xgpiops_intr.c */
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank);
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank);
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask);
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny);
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny);
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+			     XGpioPs_Handler FuncPointer);
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr);
+
+/* Pin APIs in xgpiops_intr.c */
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType);
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin);
+
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin);
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin);
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin);
+
+/* Functions in xgpiops_sinit.c */
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
new file mode 100644
index 000000000..597b38a12
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xgpiops.h"
+
+/*
+* The configuration table for devices
+*/
+
+XGpioPs_Config XGpioPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_GPIO_0_DEVICE_ID,
+		XPAR_PSU_GPIO_0_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c
new file mode 100644
index 000000000..d7a5e00f0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.c
@@ -0,0 +1,169 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.c
+* @addtogroup gpiops_v3_1
+* @{
+*
+* This file contains low level GPIO functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.02a hk   08/22/13 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops_hw.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+
+/*****************************************************************************/
+/*
+*
+* This function resets the GPIO module by writing reset values to
+* all registers
+*
+* @param	Base address of GPIO module
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XGpioPs_ResetHw(u32 BaseAddress)
+{
+	u32 BankCount;
+	u32 Platform,MaxBanks;
+
+	Platform = XGetPlatform_Info();
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		MaxBanks = (u32)6;
+	} else {
+		MaxBanks = (u32)4;
+	}
+	/* Write reset values to all mask data registers */
+	for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_LSW_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_MASK_OFFSET) +
+				 XGPIOPS_DATA_MSW_OFFSET), 0x0U);
+	}
+	/* Write reset values to all output data registers */
+	for(BankCount = 2U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_DATA_BANK_OFFSET) +
+				 XGPIOPS_DATA_OFFSET), 0x0U);
+	}
+
+	/* Reset all registers of all GPIO banks */
+	for(BankCount = 0U; BankCount < (u32)MaxBanks; BankCount++) {
+
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_DIRM_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_OUTEN_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTMASK_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTEN_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTDIS_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTSTS_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTPOL_OFFSET), 0x0U);
+		XGpioPs_WriteReg(BaseAddress,
+				((BankCount * XGPIOPS_REG_MASK_OFFSET) +
+				 XGPIOPS_INTANY_OFFSET), 0x0U);
+	}
+
+	/* Bank 0 Int type */
+	XGpioPs_WriteReg(BaseAddress, XGPIOPS_INTTYPE_OFFSET,
+			XGPIOPS_INTTYPE_BANK0_RESET);
+	/* Bank 1 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			((u32)XGPIOPS_REG_MASK_OFFSET + (u32)XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK1_RESET);
+	/* Bank 2 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)2 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK2_RESET);
+	/* Bank 3 Int type */
+	XGpioPs_WriteReg(BaseAddress,
+			(((u32)3 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+			XGPIOPS_INTTYPE_BANK3_RESET);
+
+	if (Platform == XPLAT_ZYNQ_ULTRA_MP) {
+		/* Bank 4 Int type */
+		XGpioPs_WriteReg(BaseAddress,
+				(((u32)4 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+				XGPIOPS_INTTYPE_BANK4_RESET);
+		/* Bank 5 Int type */
+		XGpioPs_WriteReg(BaseAddress,
+				(((u32)5 * XGPIOPS_REG_MASK_OFFSET) + XGPIOPS_INTTYPE_OFFSET),
+				XGPIOPS_INTTYPE_BANK5_RESET);
+	}
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h
new file mode 100644
index 000000000..81e8d6a9f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_hw.h
@@ -0,0 +1,164 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_hw.h
+* @addtogroup gpiops_v3_1
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xgpiops.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 1.02a hk   08/22/13 Added low level reset API function prototype and
+*                     related constant definitions
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Corrected reset values of banks.
+* 

+*
+******************************************************************************/
+#ifndef XGPIOPS_HW_H		/* prevent circular inclusions */
+#define XGPIOPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register offsets for the GPIO. Each register is 32 bits.
+ *  @{
+ */
+#define XGPIOPS_DATA_LSW_OFFSET  0x00000000U  /* Mask and Data Register LSW, WO */
+#define XGPIOPS_DATA_MSW_OFFSET  0x00000004U  /* Mask and Data Register MSW, WO */
+#define XGPIOPS_DATA_OFFSET	 0x00000040U  /* Data Register, RW */
+#define XGPIOPS_DATA_RO_OFFSET	 0x00000060U  /* Data Register - Input, RO */
+#define XGPIOPS_DIRM_OFFSET	 0x00000204U  /* Direction Mode Register, RW */
+#define XGPIOPS_OUTEN_OFFSET	 0x00000208U  /* Output Enable Register, RW */
+#define XGPIOPS_INTMASK_OFFSET	 0x0000020CU  /* Interrupt Mask Register, RO */
+#define XGPIOPS_INTEN_OFFSET	 0x00000210U  /* Interrupt Enable Register, WO */
+#define XGPIOPS_INTDIS_OFFSET	 0x00000214U  /* Interrupt Disable Register, WO*/
+#define XGPIOPS_INTSTS_OFFSET	 0x00000218U  /* Interrupt Status Register, RO */
+#define XGPIOPS_INTTYPE_OFFSET	 0x0000021CU  /* Interrupt Type Register, RW */
+#define XGPIOPS_INTPOL_OFFSET	 0x00000220U  /* Interrupt Polarity Register, RW */
+#define XGPIOPS_INTANY_OFFSET	 0x00000224U  /* Interrupt On Any Register, RW */
+/* @} */
+
+/** @name Register offsets for each Bank.
+ *  @{
+ */
+#define XGPIOPS_DATA_MASK_OFFSET 0x00000008U  /* Data/Mask Registers offset */
+#define XGPIOPS_DATA_BANK_OFFSET 0x00000004U  /* Data Registers offset */
+#define XGPIOPS_REG_MASK_OFFSET  0x00000040U  /* Registers offset */
+/* @} */
+
+/* For backwards compatibility */
+#define XGPIOPS_BYPM_MASK_OFFSET	(u32)0x40
+
+/** @name Interrupt type reset values for each bank
+ *  @{
+ */
+#ifdef XPAR_PSU_GPIO_0_BASEADDR
+#define XGPIOPS_INTTYPE_BANK0_RESET  0x03FFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x03FFFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0x03FFFFFFU
+#else
+#define XGPIOPS_INTTYPE_BANK0_RESET  0xFFFFFFFFU  /* Resets specific to Zynq */
+#define XGPIOPS_INTTYPE_BANK1_RESET  0x003FFFFFU
+#define XGPIOPS_INTTYPE_BANK2_RESET  0xFFFFFFFFU
+#endif
+
+#define XGPIOPS_INTTYPE_BANK3_RESET  0xFFFFFFFFU  /* Reset common to both platforms */
+#define XGPIOPS_INTTYPE_BANK4_RESET  0xFFFFFFFFU  /* Resets specific to Zynq Ultrascale+ MP */
+#define XGPIOPS_INTTYPE_BANK5_RESET  0xFFFFFFFFU
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the register offset to be read.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_ReadReg(BaseAddr, RegOffset)		\
+		Xil_In32((BaseAddr) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* This macro writes to the given register.
+*
+* @param	BaseAddr is the base address of the device.
+* @param	RegOffset is the offset of the register to be written.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XGpioPs_WriteReg(BaseAddr, RegOffset, Data)	\
+		Xil_Out32((BaseAddr) + (u32)(RegOffset), (u32)(Data))
+
+/************************** Function Prototypes ******************************/
+
+void XGpioPs_ResetHw(u32 BaseAddress);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XGPIOPS_HW_H */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c
new file mode 100644
index 000000000..c07381be6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_intr.c
@@ -0,0 +1,731 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_intr.c
+* @addtogroup gpiops_v3_1
+* @{
+*
+* This file contains functions related to GPIO interrupt handling.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 2.2	sk	 10/13/14 Used Pin number in Bank instead of pin number
+* 					  passed to API's. CR# 822636
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn  04/13/15 Add support for Zynq Ultrascale+ MP. CR# 856980.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status);
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the bit mask of the pins for which interrupts are to
+*		be enabled. Bit positions of 1 will be enabled. Bit positions
+*		of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the interrupt for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be enabled.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrEnablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0U;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg = ((u32)1 << (u32)PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTEN_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pins in the specified
+* bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the bit mask of the pins for which interrupts are
+*		to be disabled. Bit positions of 1 will be disabled. Bit
+*		positions of 0 will keep the previous setting.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisable(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the interrupts for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt is to be disabled.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrDisablePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg = 0U;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg =  ((u32)1 << (u32)PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTDIS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt enable status for a bank.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	Enabled interrupt(s) in a 32-bit format. Bit positions with 1
+*		indicate that the interrupt for that pin is enabled, bit
+*		positions with 0 indicate that the interrupt for that pin is
+*		disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabled(XGpioPs *InstancePtr, u8 Bank)
+{
+	u32 IntrMask;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	IntrMask = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+	return (~IntrMask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns whether interrupts are enabled for the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+*		- TRUE if the interrupt is enabled.
+*		- FALSE if the interrupt is disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetEnabledPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg  = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTMASK_OFFSET);
+
+	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? FALSE : TRUE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+*
+* @return	The value read from Interrupt Status Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatus(XGpioPs *InstancePtr, u8 Bank)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Bank < InstancePtr->MaxBanks);
+
+	return XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				XGPIOPS_INTSTS_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns interrupt enable status of the specified pin.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt enable status
+*		is to be known.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return
+*		- TRUE if the interrupt has occurred.
+*		- FALSE if the interrupt has not occurred.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XGpioPs_IntrGetStatusPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	return (((IntrReg & ((u32)1 << PinNumber)) != (u32)0)? TRUE : FALSE);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears pending interrupt(s) with the provided mask. This
+* function should be called after the software has serviced the interrupts
+* that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	Mask is the mask of the interrupts to be cleared. Bit positions
+*		of 1 will be cleared. Bit positions of 0 will not change the
+*		previous interrupt status.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClear(XGpioPs *InstancePtr, u8 Bank, u32 Mask)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	/* Clear the currently pending interrupts. */
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, Mask);
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified pending interrupt. This function should be
+* called after the software has serviced the interrupts that are pending.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	Pin is the pin number for which the interrupt status is to be
+*		cleared. Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_IntrClearPin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u8 Bank;
+	u8 PinNumber;
+	u32 IntrReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	/* Clear the specified pending interrupts. */
+	IntrReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTSTS_OFFSET);
+
+	IntrReg &= ((u32)1 << PinNumber);
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTSTS_OFFSET, IntrReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	IntrType is the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity is the 32 bit mask of the interrupt polarity.
+*		0 means Active Low or Falling Edge and 1 means Active High or
+*		Rising Edge.
+* @param	IntrOnAny is the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means  trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		This function is used for setting the interrupt related
+*		properties of all the pins in the specified bank. The previous
+*		state of the pins is not maintained.
+*		To change the Interrupt properties of a single GPIO pin, use the
+*		function XGpioPs_SetPinIntrType().
+*
+*****************************************************************************/
+void XGpioPs_SetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 IntrType,
+			  u32 IntrPolarity, u32 IntrOnAny)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrType);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolarity);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAny);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for getting the Interrupt Type, Interrupt Polarity and
+* Interrupt On Any for the specified GPIO Bank pins.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Bank is the bank number of the GPIO to operate on.
+*		Valid values are 0-3 in Zynq and 0-5 in Zynq Ultrascale+ MP.
+* @param	IntrType returns the 32 bit mask of the interrupt type.
+*		0 means Level Sensitive and 1 means Edge Sensitive.
+* @param	IntrPolarity returns the 32 bit mask of the interrupt
+*		polarity. 0 means Active Low or Falling Edge and 1 means
+*		Active High or Rising Edge.
+* @param	IntrOnAny returns the 32 bit mask of the interrupt trigger for
+*		edge triggered interrupts. 0 means trigger on single edge using
+*		the configured interrupt polarity and 1 means trigger on both
+*		edges.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_GetIntrType(XGpioPs *InstancePtr, u8 Bank, u32 *IntrType,
+			  u32 *IntrPolarity, u32 *IntrOnAny)
+
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Bank < InstancePtr->MaxBanks);
+
+	*IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTTYPE_OFFSET);
+
+	*IntrPolarity = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					 ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					 XGPIOPS_INTPOL_OFFSET);
+
+	*IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTANY_OFFSET);
+}
+
+/****************************************************************************/
+/**
+*
+* This function is used for setting the IRQ Type of a single GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be set.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+* @param	IrqType is the IRQ type for GPIO Pin. Use XGPIOPS_IRQ_TYPE_*
+*		defined in xgpiops.h to specify the IRQ type.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XGpioPs_SetIntrTypePin(XGpioPs *InstancePtr, u32 Pin, u8 IrqType)
+{
+	u32 IntrTypeReg;
+	u32 IntrPolReg;
+	u32 IntrOnAnyReg;
+	u8 Bank;
+	u8 PinNumber;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Pin < InstancePtr->MaxPinNum);
+	Xil_AssertVoid(IrqType <= XGPIOPS_IRQ_TYPE_LEVEL_LOW);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrTypeReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				       ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				       XGPIOPS_INTTYPE_OFFSET);
+
+	IntrPolReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				      ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				      XGPIOPS_INTPOL_OFFSET);
+
+	IntrOnAnyReg = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+					((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+					XGPIOPS_INTANY_OFFSET);
+
+	switch (IrqType) {
+		case XGPIOPS_IRQ_TYPE_EDGE_RISING:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrPolReg |= ((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_FALLING:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_EDGE_BOTH:
+			IntrTypeReg |= ((u32)1 << (u32)PinNumber);
+			IntrOnAnyReg |= ((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_HIGH:
+			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+			IntrPolReg |= ((u32)1 << (u32)PinNumber);
+			break;
+		case XGPIOPS_IRQ_TYPE_LEVEL_LOW:
+			IntrTypeReg &= ~((u32)1 << (u32)PinNumber);
+			IntrPolReg &= ~((u32)1 << (u32)PinNumber);
+			break;
+		default:
+			/**< Default statement is added for MISRA C compliance. */
+			break;
+	}
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTTYPE_OFFSET, IntrTypeReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTPOL_OFFSET, IntrPolReg);
+
+	XGpioPs_WriteReg(InstancePtr->GpioConfig.BaseAddr,
+			  ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+			  XGPIOPS_INTANY_OFFSET, IntrOnAnyReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the IRQ Type of a given GPIO pin.
+*
+* @param	InstancePtr is a pointer to an XGpioPs instance.
+* @param	Pin is the pin number whose IRQ type is to be obtained.
+*		Valid values are 0-117 in Zynq and 0-173 in Zynq Ultrascale+ MP.
+*
+* @return	None.
+*
+* @note		Use XGPIOPS_IRQ_TYPE_* defined in xgpiops.h for the IRQ type
+*		returned by this function.
+*
+*****************************************************************************/
+u8 XGpioPs_GetIntrTypePin(XGpioPs *InstancePtr, u32 Pin)
+{
+	u32 IntrType;
+	u32 IntrPol;
+	u32 IntrOnAny;
+	u8 Bank;
+	u8 PinNumber;
+	u8 IrqType;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Pin < InstancePtr->MaxPinNum);
+
+	/* Get the Bank number and Pin number within the bank. */
+	XGpioPs_GetBankPin((u8)Pin, &Bank, &PinNumber);
+
+	IntrType = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				    ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				    XGPIOPS_INTTYPE_OFFSET) & ((u32)1 << PinNumber);
+
+	if (IntrType == ((u32)1 << PinNumber)) {
+
+		IntrOnAny = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				     ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				     XGPIOPS_INTANY_OFFSET) & ((u32)1 << PinNumber);
+
+		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+
+		if (IntrOnAny == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_BOTH;
+		} else if (IntrPol == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_RISING;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_EDGE_FALLING;
+		}
+	} else {
+
+		IntrPol = XGpioPs_ReadReg(InstancePtr->GpioConfig.BaseAddr,
+				   ((u32)(Bank) * XGPIOPS_REG_MASK_OFFSET) +
+				   XGPIOPS_INTPOL_OFFSET) & ((u32)1 << PinNumber);
+
+		if (IntrPol == ((u32)1 << PinNumber)) {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_HIGH;
+		} else {
+			IrqType = XGPIOPS_IRQ_TYPE_LEVEL_LOW;
+		}
+	}
+
+	return IrqType;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function. The callback function is
+* called by the  XGpioPs_IntrHandler when an interrupt occurs.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPtr is the pointer to the callback function.
+*
+*
+* @return	None.
+*
+* @note		The handler is called within interrupt context, so it should do
+*		its work quickly and queue potentially time-consuming work to a
+*		task-level thread.
+*
+******************************************************************************/
+void XGpioPs_SetCallbackHandler(XGpioPs *InstancePtr, void *CallBackRef,
+				 XGpioPs_Handler FuncPointer)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPointer != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPointer;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for GPIO interrupts.It checks the
+* interrupt status registers of all the banks to determine the actual bank in
+* which an interrupt has been triggered. It then calls the upper layer callback
+* handler set by the function XGpioPs_SetBankHandler(). The callback is called
+* when an interrupt
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return	None.
+*
+* @note		This function does not save and restore the processor context
+*		such that the user must provide this processing.
+*
+******************************************************************************/
+void XGpioPs_IntrHandler(XGpioPs *InstancePtr)
+{
+	u8 Bank;
+	u32 IntrStatus;
+	u32 IntrEnabled;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (Bank = 0U; Bank < InstancePtr->MaxBanks; Bank++) {
+		IntrStatus = XGpioPs_IntrGetStatus(InstancePtr, Bank);
+		if (IntrStatus != (u32)0) {
+			IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr,
+							      Bank);
+			XGpioPs_IntrClear((XGpioPs *)InstancePtr, Bank,
+							(IntrStatus & IntrEnabled));
+			InstancePtr->Handler(InstancePtr->
+					     CallBackRef, Bank,
+					     (IntrStatus & IntrEnabled));
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers do not set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	Bank is the GPIO Bank in which an interrupt occurred.
+* @param	Status is the Interrupt status of the GPIO bank.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void StubHandler(void *CallBackRef, u32 Bank, u32 Status)
+{
+	(void*) CallBackRef;
+	(void) Bank;
+	(void) Status;
+
+	Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c
new file mode 100644
index 000000000..da1973a2d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_selftest.c
@@ -0,0 +1,133 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_selftest.c
+* @addtogroup gpiops_v3_1
+* @{
+*
+* This file contains a diagnostic self-test function for the XGpioPs driver.
+*
+* Read xgpiops.h file for more information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/18/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xgpiops.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function runs a self-test on the GPIO driver/device. This function
+* does a register read/write test on some of the Interrupt Registers.
+*
+* @param	InstancePtr is a pointer to the XGpioPs instance.
+*
+* @return
+*		- XST_SUCCESS if the self-test passed.
+* 		- XST_FAILURE otherwise.
+*
+*
+******************************************************************************/
+s32 XGpioPs_SelfTest(XGpioPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrEnabled;
+	u32 CurrentIntrType = 0U;
+	u32 CurrentIntrPolarity = 0U;
+	u32 CurrentIntrOnAny = 0U;
+	u32 IntrType = 0U;
+	u32 IntrPolarity = 0U;
+	u32 IntrOnAny = 0U;
+	u32 IntrTestValue = 0x22U;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable the Interrupts for Bank 0 . */
+	IntrEnabled = XGpioPs_IntrGetEnabled(InstancePtr, XGPIOPS_BANK0);
+	XGpioPs_IntrDisable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	/*
+	 * Get the Current Interrupt properties for Bank 0.
+	 * Set them to a known value, read it back and compare.
+	 */
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &CurrentIntrType,
+			     &CurrentIntrPolarity, &CurrentIntrOnAny);
+
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, IntrTestValue,
+			     IntrTestValue, IntrTestValue);
+
+	XGpioPs_GetIntrType(InstancePtr, XGPIOPS_BANK0, &IntrType,
+			     &IntrPolarity, &IntrOnAny);
+
+	if ((IntrType != IntrTestValue) && (IntrPolarity != IntrTestValue) &&
+	    (IntrOnAny != IntrTestValue)) {
+
+		Status = XST_FAILURE;
+	}
+
+	/*
+	 * Restore the contents of all the interrupt registers modified in this
+	 * test.
+	 */
+	XGpioPs_SetIntrType(InstancePtr, XGPIOPS_BANK0, CurrentIntrType,
+			     CurrentIntrPolarity, CurrentIntrOnAny);
+
+	XGpioPs_IntrEnable(InstancePtr, XGPIOPS_BANK0, IntrEnabled);
+
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c
new file mode 100644
index 000000000..2ca008373
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/gpiops_v3_1/src/xgpiops_sinit.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xgpiops_sinit.c
+* @addtogroup gpiops_v3_1
+* @{
+*
+* This file contains the implementation of the XGpioPs driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a sv   01/15/10 First Release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xgpiops.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XGpioPs_Config XGpioPs_ConfigTable[XPAR_XGPIOPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XGpioPs_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XGpioPs_Config *XGpioPs_LookupConfig(u16 DeviceId)
+{
+	XGpioPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XGPIOPS_NUM_INSTANCES; Index++) {
+		if (XGpioPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XGpioPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XGpioPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/Makefile
new file mode 100644
index 000000000..8c16c35ae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xiicps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling iicps"
+
+xiicps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xiicps_includes
+
+xiicps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.c
new file mode 100644
index 000000000..812c2ecdc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.c
@@ -0,0 +1,332 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains implementation of required functions for the XIicPs driver.
+* See xiicps.h for detailed description of the device and driver.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.00a sdm     09/21/11 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+* 2.1   hk      04/25/14 Explicitly reset CR and clear FIFO in Abort function
+*                        and state the same in the comments. CR# 784254.
+*                        Fix for CR# 761060 - provision for repeated start.
+* 2.3	sk		10/07/14 Repeated start feature removed.
+* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
+* 						 in XIicPs_Reset.
+*				12/06/14 Implemented Repeated start feature.
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef, u32 StatusEvent);
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XIicPs instance such that the driver is ready to use.
+*
+* The state of the device after initialization is:
+*   - Device is disabled
+*   - Slave mode
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific IIC device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return	The return value is XST_SUCCESS if successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config *ConfigPtr,
+				  u32 EffectiveAddr)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values.
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->StatusHandler = StubHandler;
+	InstancePtr->CallBackRef = NULL;
+
+	InstancePtr->IsReady = (u32)XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Reset the IIC device to get it into its initial state. It is expected
+	 * that device configuration will take place after this initialization
+	 * is done, but before the device is started.
+	 */
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	/* Initialize repeated start flag to 0 */
+	InstancePtr->IsRepeatedStart = 0;
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* Check whether the I2C bus is busy
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+* 		- TRUE if the bus is busy.
+*		- FALSE if the bus is not busy.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr)
+{
+	u32 StatusReg;
+	s32	Status;
+
+	StatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_SR_OFFSET);
+	if ((StatusReg & XIICPS_SR_BA_MASK) != 0x0U) {
+		Status = (s32)TRUE;
+	}else {
+		Status = (s32)FALSE;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference.
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef, u32 StatusEvent)
+{
+	(void) ((void *)CallBackRef);
+	(void) StatusEvent;
+	Xil_AssertVoidAlways();
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by resetting the FIFOs. The byte counts are
+* cleared.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Abort(XIicPs *InstancePtr)
+{
+	u32 IntrMaskReg;
+	u32 IntrStatusReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Enter a critical section, so disable the interrupts while we clear
+	 * the FIFO and the status register.
+	 */
+	IntrMaskReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_IMR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+
+	/*
+	 * Reset the settings in config register and clear the FIFOs.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  XIICPS_CR_RESET_VALUE | XIICPS_CR_CLR_FIFO_MASK);
+
+	/*
+	 * Read, then write the interrupt status to make sure there are no
+	 * pending interrupts.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Restore the interrupt state.
+	 */
+	IntrMaskReg = XIICPS_IXR_ALL_INTR_MASK & (~IntrMaskReg);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_IER_OFFSET, IntrMaskReg);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the IIC device. Reset must only be called after the driver has been
+* initialized. The configuration of the device after reset is the same as its
+* configuration after initialization.  Any data transfer that is in progress is
+* aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and reenabling interrupts for the IIC device after the reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XIicPs_Reset(XIicPs *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Abort any transfer that is in progress.
+	 */
+	XIicPs_Abort(InstancePtr);
+
+	/*
+	 * Reset any values so the software state matches the hardware device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  XIICPS_CR_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_IDR_OFFSET,
+			  XIICPS_IXR_ALL_INTR_MASK);
+
+}
+/*****************************************************************************/
+/**
+* Put more data into the transmit FIFO, number of bytes is ether expected
+* number of bytes for this transfer or available space in FIFO, which ever
+* is less.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes left for this instance.
+*
+* @note		This is function is shared by master and slave.
+*
+******************************************************************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr)
+{
+	u8 AvailBytes;
+	s32 LoopCnt;
+	s32 NumBytesToSend;
+
+	/*
+	 * Determine number of bytes to write to FIFO.
+	 */
+	AvailBytes = (u8)XIICPS_FIFO_DEPTH -
+		(u8)XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					   XIICPS_TRANS_SIZE_OFFSET);
+
+	if (InstancePtr->SendByteCount > (s32)AvailBytes) {
+		NumBytesToSend = (s32)AvailBytes;
+	} else {
+		NumBytesToSend = InstancePtr->SendByteCount;
+	}
+
+	/*
+	 * Fill FIFO with amount determined above.
+	 */
+	for (LoopCnt = 0; LoopCnt < NumBytesToSend; LoopCnt++) {
+		XIicPs_SendByte(InstancePtr);
+	}
+
+	return InstancePtr->SendByteCount;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.h
new file mode 100644
index 000000000..73ad5dc64
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps.h
@@ -0,0 +1,420 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps.h
+* @addtogroup iicps_v3_0
+* @{
+* @details
+*
+* This is an implementation of IIC driver in the PS block. The device can
+* be either a master or a slave on the IIC bus. This implementation supports
+* both interrupt mode transfer and polled mode transfer. Only 7-bit address
+* is used in the driver, although the hardware also supports 10-bit address.
+*
+* IIC is a 2-wire serial interface.  The master controls the clock, so it can
+* regulate when it wants to send or receive data. The slave is under control of
+* the master, it must respond quickly since it has no control of the clock and
+* must send/receive data as fast or as slow as the master does.
+*
+* The higher level software must implement a higher layer protocol to inform
+* the slave what to send to the master.
+*
+* Initialization & Configuration
+*
+* The XIicPs_Config structure is used by the driver to configure itself. This
+* configuration structure is typically created by the tool-chain based on HW
+* build properties.
+*
+* To support multiple runtime loading and initialization strategies employed by
+* various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*    - XIicPs_LookupConfig(DeviceId) - Use the device identifier to find
+*      the static configuration structure defined in xiicps_g.c. This is
+*      setup by the tools. For some operating systems the config structure
+*      will be initialized by the software and this call is not needed.
+*
+*   - XIicPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*     configuration structure provided by the caller. If running in a
+*     system with address translation, the provided virtual memory base
+*     address replaces the physical address in the configuration
+*     structure.
+*
+* Multiple Masters
+*
+* More than one master can exist, bus arbitration is defined in the IIC
+* standard. Lost of arbitration causes arbitration loss interrupt on the device.
+*
+* Multiple Slaves
+*
+* Multiple slaves are supported by selecting them with unique addresses. It is
+* up to the system designer to be sure all devices on the IIC bus have
+* unique addresses.
+*
+* Addressing
+*
+* The IIC hardware can use 7 or 10 bit addresses.  The driver provides the
+* ability to control which address size is sent in messages as a master to a
+* slave device.
+*
+* FIFO Size 
+* The hardware FIFO is 32 bytes deep. The user must know the limitations of
+* other IIC devices on the bus. Some are only able to receive a limited number
+* of bytes in a single transfer.
+*
+* Data Rates
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+*
+* When the device is configured as a slave, the slck setting controls the
+* sample rate and so must be set to be at least as fast as the fastest scl
+* expected to be seen in the system.
+*
+* Polled Mode Operation
+*
+* This driver supports polled mode transfers.
+*
+* Interrupts
+*
+* The user must connect the interrupt handler of the driver,
+* XIicPs_InterruptHandler to an interrupt system such that it will be called
+* when an interrupt occurs. This function does not save and restore the
+* processor context such that the user must provide this processing.
+*
+* The driver handles the following interrupts:
+* - Transfer complete
+* - More Data
+* - Transfer not Acknowledged
+* - Transfer Time out
+* - Monitored slave ready - master mode only
+* - Receive Overflow
+* - Transmit FIFO overflow
+* - Receive FIFO underflow
+* - Arbitration lost
+*
+* Bus Busy
+*
+* Bus busy is checked before the setup of a master mode device, to avoid
+* unnecessary arbitration loss interrupt.
+*
+* RTOS Independence
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads or
+* thread mutual exclusion, virtual memory, or cache control must be satisfied by
+* the layer above this driver.
+*
+*Repeated Start
+*
+* The I2C controller does not indicate completion of a receive transfer if HOLD
+* bit is set. Due to this errata, repeated start cannot be used if a receive
+* transfer is followed by any other transfer.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/08 First release
+* 1.00a sdm     09/21/11 Fixed an issue in the XIicPs_SetOptions and
+*			 XIicPs_ClearOptions where the InstancePtr->Options
+*			 was not updated correctly.
+* 			 Updated the InstancePtr->Options in the
+*			 XIicPs_CfgInitialize by calling XIicPs_GetOptions.
+*			 Updated the XIicPs_SetupMaster to not check for
+*			 Bus Busy condition when the Hold Bit is set.
+*			 Removed some unused variables.
+* 1.01a sg      03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*			 check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error for
+*			 CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Added check for error status in the while loop that
+*                    checks for completion.
+*                    (XIicPs_MasterSendPolled function). CR# 762244, 764875.
+*                    Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                    Explicitly reset CR and clear FIFO in Abort function
+*                    and state the same in the comments. CR# 784254.
+*                    Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk  08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                    read mode and clear transfer size register.
+*                    Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	10/07/14 Repeated start feature deleted.
+* 3.0	sk	11/03/14 Modified TimeOut Register value to 0xFF
+* 					 in XIicPs_Reset.
+* 			12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XIICPS_H       /* prevent circular inclusions */
+#define XIICPS_H       /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xiicps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * The following options may be specified or retrieved for the device and
+ * enable/disable additional features of the IIC.  Each of the options
+ * are bit fields, so more than one may be specified.
+ *
+ * @{
+ */
+#define XIICPS_7_BIT_ADDR_OPTION	0x01U  /**< 7-bit address mode */
+#define XIICPS_10_BIT_ADDR_OPTION	0x02U  /**< 10-bit address mode */
+#define XIICPS_SLAVE_MON_OPTION		0x04U  /**< Slave monitor mode */
+#define XIICPS_REP_START_OPTION		0x08U  /**< Repeated Start */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that are passed to an application
+ * event handler from the driver.  These constants are bit masks such that
+ * more than one event can be passed to the handler.
+ *
+ * @{
+ */
+#define XIICPS_EVENT_COMPLETE_SEND	0x0001U  /**< Transmit Complete Event*/
+#define XIICPS_EVENT_COMPLETE_RECV	0x0002U  /**< Receive Complete Event*/
+#define XIICPS_EVENT_TIME_OUT		0x0004U  /**< Transfer timed out */
+#define XIICPS_EVENT_ERROR			0x0008U  /**< Receive error */
+#define XIICPS_EVENT_ARB_LOST		0x0010U  /**< Arbitration lost */
+#define XIICPS_EVENT_NACK			0x0020U  /**< NACK Received */
+#define XIICPS_EVENT_SLAVE_RDY		0x0040U  /**< Slave ready */
+#define XIICPS_EVENT_RX_OVR			0x0080U  /**< RX overflow */
+#define XIICPS_EVENT_TX_OVR			0x0100U  /**< TX overflow */
+#define XIICPS_EVENT_RX_UNF			0x0200U  /**< RX underflow */
+/*@}*/
+
+/** @name Role constants
+ *
+ * These constants are used to pass into the device setup routines to
+ * set up the device according to transfer direction.
+ */
+#define SENDING_ROLE		1  /**< Transfer direction is sending */
+#define RECVING_ROLE		0  /**< Transfer direction is receiving */
+
+/* Maximum transfer size */
+#define XIICPS_MAX_TRANSFER_SIZE	(u32)(255U - 3U)
+
+/**************************** Type Definitions *******************************/
+
+/**
+* The handler data type allows the user to define a callback function to
+* respond to interrupt events in the system. This function is executed
+* in interrupt context, so amount of processing should be minimized.
+*
+* @param	CallBackRef is the callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked. Its type is
+*		not important to the driver, so it is a void pointer.
+* @param	StatusEvent indicates one or more status events that occurred.
+*/
+typedef void (*XIicPs_IntrHandler) (void *CallBackRef, u32 StatusEvent);
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;     /**< Unique ID  of device */
+	u32 BaseAddress;  /**< Base address of the device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XIicPs_Config;
+
+/**
+ * The XIicPs driver instance data. The user is required to allocate a
+ * variable of this type for each IIC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XIicPs_Config Config;	/* Configuration structure */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 Options;		/* Options set in the device */
+
+	u8 *SendBufferPtr;	/* Pointer to send buffer */
+	u8 *RecvBufferPtr;	/* Pointer to recv buffer */
+	s32 SendByteCount;	/* Number of bytes still expected to send */
+	s32 RecvByteCount;	/* Number of bytes still expected to receive */
+	s32 CurrByteCount;	/* No. of bytes expected in current transfer */
+
+	s32 UpdateTxSize;	/* If tx size register has to be updated */
+	s32 IsSend;		/* Whether master is sending or receiving */
+	s32 IsRepeatedStart;	/* Indicates if user set repeated start */
+
+	XIicPs_IntrHandler StatusHandler;  /* Event handler function */
+	void *CallBackRef;	/* Callback reference for event handler */
+} XIicPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/*
+*
+* Place one byte into the transmit FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_SendByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_SendByte(InstancePtr)					\
+{									\
+	u8 Data;							\
+	Data = *((InstancePtr)->SendBufferPtr);				\
+	 XIicPs_Out32((InstancePtr)->Config.BaseAddress			\
+			 + (u32)(XIICPS_DATA_OFFSET), 			\
+					(u32)(Data));			\
+	(InstancePtr)->SendBufferPtr += 1;				\
+	(InstancePtr)->SendByteCount -= 1;\
+}
+
+/****************************************************************************/
+/*
+*
+* Receive one byte from FIFO.
+*
+* @param	InstancePtr is the instance of IIC
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		u8 XIicPs_RecvByte(XIicPs *InstancePtr)
+*
+*****************************************************************************/
+#define XIicPs_RecvByte(InstancePtr)					\
+{									\
+	u8 *Data, Value;						\
+	Value = (u8)(XIicPs_In32((InstancePtr)->Config.BaseAddress	\
+		  + (u32)XIICPS_DATA_OFFSET));  			\
+	Data = &Value;							\
+	*(InstancePtr)->RecvBufferPtr = *Data;				\
+	(InstancePtr)->RecvBufferPtr += 1;				\
+	 (InstancePtr)->RecvByteCount --; 				\
+}
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Function for configuration lookup, in xiicps_sinit.c
+ */
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Functions for general setup, in xiicps.c
+ */
+s32 XIicPs_CfgInitialize(XIicPs *InstancePtr, XIicPs_Config * ConfigPtr,
+				  u32 EffectiveAddr);
+
+void XIicPs_Abort(XIicPs *InstancePtr);
+void XIicPs_Reset(XIicPs *InstancePtr);
+
+s32 XIicPs_BusIsBusy(XIicPs *InstancePtr);
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+/*
+ * Functions for interrupts, in xiicps_intr.c
+ */
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FunctionPtr);
+
+/*
+ * Functions for device as master, in xiicps_master.c
+ */
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		u16 SlaveAddr);
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr);
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for device as slave, in xiicps_slave.c
+ */
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr);
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount);
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr);
+
+/*
+ * Functions for selftest, in xiicps_selftest.c
+ */
+s32 XIicPs_SelfTest(XIicPs *InstancePtr);
+
+/*
+ * Functions for setting and getting data rate, in xiicps_options.c
+ */
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options);
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options);
+u32 XIicPs_GetOptions(XIicPs *InstancePtr);
+
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz);
+u32 XIicPs_GetSClk(XIicPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_g.c
new file mode 100644
index 000000000..50f1c1413
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_g.c
@@ -0,0 +1,61 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xiicps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XIicPs_Config XIicPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_I2C_0_DEVICE_ID,
+		XPAR_PSU_I2C_0_BASEADDR,
+		XPAR_PSU_I2C_0_I2C_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_I2C_1_DEVICE_ID,
+		XPAR_PSU_I2C_1_BASEADDR,
+		XPAR_PSU_I2C_1_I2C_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.c
new file mode 100644
index 000000000..8b7a58fc6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.c
@@ -0,0 +1,111 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains implementation of required functions for providing the reset sequence
+* to the i2c interface
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- --------------------------------------------
+* 1.04a kpc     11/07/13 First release
+* 3.0	sk		11/03/14 Modified TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps_hw.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+/*****************************************************************************/
+/**
+* This function perform the reset sequence to the given I2c interface by
+* configuring the appropriate control bits in the I2c specifc registers
+* the i2cps reset squence involves the following steps
+*	Disable all the interuupts
+*	Clear the status
+*	Clear FIFO's and disable hold bit
+*	Clear the line status
+*	Update relevant config registers with reset values
+*
+* @param   BaseAddress of the interface
+*
+* @return N/A
+*
+* @note
+* This function will not modify the slcr registers that are relavant for
+* I2c controller
+******************************************************************************/
+void XIicPs_ResetHw(u32 BaseAddress)
+{
+	u32 RegVal;
+
+	/* Disable all the interrupts */
+	XIicPs_WriteReg(BaseAddress, XIICPS_IDR_OFFSET, XIICPS_IXR_ALL_INTR_MASK);
+	/* Clear the interrupt status */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_ISR_OFFSET, RegVal);
+	/* Clear the hold bit,master enable bit and ack bit */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_CR_OFFSET);
+	RegVal &= ~(XIICPS_CR_HOLD_MASK|XIICPS_CR_MS_MASK|XIICPS_CR_ACKEN_MASK);
+	/* Clear the fifos */
+	RegVal |= XIICPS_CR_CLR_FIFO_MASK;
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, RegVal);
+	/* Clear the timeout register */
+	XIicPs_WriteReg(BaseAddress, XIICPS_TIME_OUT_OFFSET, XIICPS_TO_RESET_VALUE);
+	/* Clear the transfer size register */
+	XIicPs_WriteReg(BaseAddress, XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+	/* Clear the status register */
+	RegVal = XIicPs_ReadReg(BaseAddress,XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddress, XIICPS_SR_OFFSET, RegVal);
+	/* Update the configuraqtion register with reset value */
+	XIicPs_WriteReg(BaseAddress, XIICPS_CR_OFFSET, 0x0U);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.h
new file mode 100644
index 000000000..cec349928
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_hw.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_hw.h
+* @addtogroup iicps_v3_0
+* @{
+*
+* This header file contains the hardware definition for an IIC device.
+* It includes register definitions and interface functions to read/write
+* the registers.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who 	Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.04a kpc		11/07/13 Added function prototype.
+* 3.0	sk		11/03/14 Modified the TimeOut Register value to 0xFF
+*				01/31/15 Modified the code according to MISRAC 2012 Compliant.
+* 

+*
+******************************************************************************/
+#ifndef XIICPS_HW_H		/* prevent circular inclusions */
+#define XIICPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the IIC.
+ * @{
+ */
+#define XIICPS_CR_OFFSET			0x00U  /**< 32-bit Control */
+#define XIICPS_SR_OFFSET			0x04U  /**< Status */
+#define XIICPS_ADDR_OFFSET			0x08U  /**< IIC Address */
+#define XIICPS_DATA_OFFSET			0x0CU  /**< IIC FIFO Data */
+#define XIICPS_ISR_OFFSET			0x10U  /**< Interrupt Status */
+#define XIICPS_TRANS_SIZE_OFFSET	0x14U  /**< Transfer Size */
+#define XIICPS_SLV_PAUSE_OFFSET		0x18U  /**< Slave monitor pause */
+#define XIICPS_TIME_OUT_OFFSET		0x1CU  /**< Time Out */
+#define XIICPS_IMR_OFFSET			0x20U  /**< Interrupt Enabled Mask */
+#define XIICPS_IER_OFFSET			0x24U  /**< Interrupt Enable */
+#define XIICPS_IDR_OFFSET			0x28U  /**< Interrupt Disable */
+/* @} */
+
+/** @name Control Register
+ *
+ * This register contains various control bits that
+ * affects the operation of the IIC controller. Read/Write.
+ * @{
+ */
+
+#define XIICPS_CR_DIV_A_MASK	0x0000C000U /**< Clock Divisor A */
+#define XIICPS_CR_DIV_A_SHIFT			14U /**< Clock Divisor A shift */
+#define XIICPS_DIV_A_MAX				 4U /**< Maximum value of Divisor A */
+#define XIICPS_CR_DIV_B_MASK	0x00003F00U /**< Clock Divisor B */
+#define XIICPS_CR_DIV_B_SHIFT			 8U /**< Clock Divisor B shift */
+#define XIICPS_CR_CLR_FIFO_MASK	0x00000040U /**< Clear FIFO, auto clears*/
+#define XIICPS_CR_SLVMON_MASK	0x00000020U /**< Slave monitor mode */
+#define XIICPS_CR_HOLD_MASK		0x00000010U /**<  Hold bus 1=Hold scl,
+												0=terminate transfer */
+#define XIICPS_CR_ACKEN_MASK	0x00000008U /**< Enable TX of ACK when
+												Master receiver*/
+#define XIICPS_CR_NEA_MASK		0x00000004U /**< Addressing Mode 1=7 bit,
+												0=10 bit */
+#define XIICPS_CR_MS_MASK		0x00000002U /**< Master mode bit 1=Master,
+												0=Slave */
+#define XIICPS_CR_RD_WR_MASK	0x00000001U /**< Read or Write Master
+												transfer  0=Transmitter,
+												1=Receiver*/
+#define XIICPS_CR_RESET_VALUE			 0U /**< Reset value of the Control
+												register */
+/* @} */
+
+/** @name IIC Status Register
+ *
+ * This register is used to indicate status of the IIC controller. Read only
+ * @{
+ */
+#define XIICPS_SR_BA_MASK		0x00000100U  /**< Bus Active Mask */
+#define XIICPS_SR_RXOVF_MASK	0x00000080U  /**< Receiver Overflow Mask */
+#define XIICPS_SR_TXDV_MASK		0x00000040U  /**< Transmit Data Valid Mask */
+#define XIICPS_SR_RXDV_MASK		0x00000020U  /**< Receiver Data Valid Mask */
+#define XIICPS_SR_RXRW_MASK		0x00000008U  /**< Receive read/write Mask */
+/* @} */
+
+/** @name IIC Address Register
+ *
+ * Normal addressing mode uses add[6:0]. Extended addressing mode uses add[9:0].
+ * A write access to this register always initiates a transfer if the IIC is in
+ * master mode. Read/Write
+ * @{
+ */
+#define XIICPS_ADDR_MASK	0x000003FF  /**< IIC Address Mask */
+/* @} */
+
+/** @name IIC Data Register
+ *
+ * When written to, the data register sets data to transmit. When read from, the
+ * data register reads the last received byte of data. Read/Write
+ * @{
+ */
+#define XIICPS_DATA_MASK	0x000000FF  /**< IIC Data Mask */
+/* @} */
+
+/** @name IIC Interrupt Registers
+ *
+ * IIC Interrupt Status Register
+ *
+ * This register holds the interrupt status flags for the IIC controller. Some
+ * of the flags are level triggered
+ * - i.e. are set as long as the interrupt condition exists.  Other flags are
+ *   edge triggered, which means they are set one the interrupt condition occurs
+ *   then remain set until they are cleared by software.
+ *   The interrupts are cleared by writing a one to the interrupt bit position
+ *   in the Interrupt Status Register. Read/Write.
+ *
+ * IIC Interrupt Enable Register
+ *
+ * This register is used to enable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register clears the corresponding bit in the
+ * IIC Interrupt Mask register.  Write only.
+ *
+ * IIC Interrupt Disable Register 
+ *
+ * This register is used to disable interrupt sources for the IIC controller.
+ * Writing a '1' to a bit in this register sets the corresponding bit in the
+ * IIC Interrupt Mask register. Write only.
+ *
+ * IIC Interrupt Mask Register
+ *
+ * This register shows the enabled/disabled status of each IIC controller
+ * interrupt source. A bit set to 1 will ignore the corresponding interrupt in
+ * the status register. A bit set to 0 means the interrupt is enabled.
+ * All mask bits are set and all interrupts are disabled after reset. Read only.
+ *
+ * All four registers have the same bit definitions. They are only defined once
+ * for each of the Interrupt Enable Register, Interrupt Disable Register,
+ * Interrupt Mask Register, and Interrupt Status Register
+ * @{
+ */
+
+#define XIICPS_IXR_ARB_LOST_MASK  0x00000200U	 /**< Arbitration Lost Interrupt
+													mask */
+#define XIICPS_IXR_RX_UNF_MASK    0x00000080U	 /**< FIFO Recieve Underflow
+													Interrupt mask */
+#define XIICPS_IXR_TX_OVR_MASK    0x00000040U	 /**< Transmit Overflow
+													Interrupt mask */
+#define XIICPS_IXR_RX_OVR_MASK    0x00000020U	 /**< Receive Overflow Interrupt
+													mask */
+#define XIICPS_IXR_SLV_RDY_MASK   0x00000010U	 /**< Monitored Slave Ready
+													Interrupt mask */
+#define XIICPS_IXR_TO_MASK        0x00000008U	 /**< Transfer Time Out
+													Interrupt mask */
+#define XIICPS_IXR_NACK_MASK      0x00000004U	 /**< NACK Interrupt mask */
+#define XIICPS_IXR_DATA_MASK      0x00000002U	 /**< Data Interrupt mask */
+#define XIICPS_IXR_COMP_MASK      0x00000001U	 /**< Transfer Complete
+													Interrupt mask */
+#define XIICPS_IXR_DEFAULT_MASK   0x000002FFU	 /**< Default ISR Mask */
+#define XIICPS_IXR_ALL_INTR_MASK  0x000002FFU	 /**< All ISR Mask */
+/* @} */
+
+
+/** @name IIC Transfer Size Register
+*
+* The register's meaning varies according to the operating mode as follows:
+*   - Master transmitter mode: number of data bytes still not transmitted minus
+*     one
+*   - Master receiver mode: number of data bytes that are still expected to be
+*     received
+*   - Slave transmitter mode: number of bytes remaining in the FIFO after the
+*     master terminates the transfer
+*   - Slave receiver mode: number of valid data bytes in the FIFO
+*
+* This register is cleared if CLR_FIFO bit in the control register is set.
+* Read/Write
+* @{
+*/
+#define XIICPS_TRANS_SIZE_MASK  0x0000003F /**< IIC Transfer Size Mask */
+#define XIICPS_FIFO_DEPTH          16	  /**< Number of bytes in the FIFO */
+#define XIICPS_DATA_INTR_DEPTH     14    /**< Number of bytes at DATA intr */
+/* @} */
+
+
+/** @name IIC Slave Monitor Pause Register
+*
+* This register is associated with the slave monitor mode of the I2C interface.
+* It is meaningful only when the module is in master mode and bit SLVMON in the
+* control register is set.
+*
+* This register defines the pause interval between consecutive attempts to
+* address the slave once a write to an I2C address register is done by the
+* host. It represents the number of sclk cycles minus one between two attempts.
+*
+* The reset value of the register is 0, which results in the master repeatedly
+* trying to access the slave immediately after unsuccessful attempt.
+* Read/Write
+* @{
+*/
+#define XIICPS_SLV_PAUSE_MASK    0x0000000F  /**< Slave monitor pause mask */
+/* @} */
+
+
+/** @name IIC Time Out Register
+*
+* The value of time out register represents the time out interval in number of
+* sclk cycles minus one.
+*
+* When the accessed slave holds the sclk line low for longer than the time out
+* period, thus prohibiting the I2C interface in master mode to complete the
+* current transfer, an interrupt is generated and TO interrupt flag is set.
+*
+* The reset value of the register is 0x1f.
+* Read/Write
+* @{
+ */
+#define XIICPS_TIME_OUT_MASK    0x000000FFU    /**< IIC Time Out mask */
+#define XIICPS_TO_RESET_VALUE   0x000000FFU    /**< IIC Time Out reset value */
+/* @} */
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XIicPs_In32 Xil_In32
+#define XIicPs_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XIicPs_ReadReg(BaseAddress, RegOffset) \
+	XIicPs_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write an IIC register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to select the specific register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_WriteReg(u32 BaseAddress, int RegOffset, u32 RegisterValue)
+*
+******************************************************************************/
+#define XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/***************************************************************************/
+/**
+* Read the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	Current bit mask that represents currently enabled interrupts.
+*
+* @note		C-Style signature:
+*		u32 XIicPs_ReadIER(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_ReadIER(BaseAddress) \
+	XIicPs_ReadReg((BaseAddress),  XIICPS_IER_OFFSET)
+
+/***************************************************************************/
+/**
+* Write to the interrupt enable register.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be enabled.
+*
+* @return	None.
+*
+* @note	C-Style signature:
+*	void XIicPs_EnabledInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_EnableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
+
+/***************************************************************************/
+/**
+* Disable all interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableAllInterrupts(u32 BaseAddress)
+*
+******************************************************************************/
+#define XIicPs_DisableAllInterrupts(BaseAddress) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		XIICPS_IXR_ALL_INTR_MASK)
+
+/***************************************************************************/
+/**
+* Disable selected interrupts.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @param	IntrMask is the interrupts to be disabled.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XIicPs_DisableInterrupts(u32 BaseAddress, u32 IntrMask)
+*
+******************************************************************************/
+#define XIicPs_DisableInterrupts(BaseAddress, IntrMask) \
+	XIicPs_WriteReg((BaseAddress), XIICPS_IDR_OFFSET, \
+		(IntrMask))
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+/*
+ * Perform reset operation to the I2c interface
+ */
+void XIicPs_ResetHw(u32 BaseAddress);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_intr.c
new file mode 100644
index 000000000..de05b93b6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_intr.c
@@ -0,0 +1,101 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_intr.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains functions of the XIicPs driver for interrupt-driven transfers.
+* See xiicps.h for a detailed description of the device and driver.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 3.00	sk		01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function sets the status callback function, the status handler, which the
+* driver calls when it encounters conditions that should be reported to the
+* higher layer software. The handler executes in an interrupt context, so
+* the amount of processing should be minimized
+*
+* Refer to the xiicps.h file for a list of the Callback events. The events are
+* defined to start with XIICPS_EVENT_*.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FunctionPtr is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should finish its
+* work quickly.
+*
+******************************************************************************/
+void XIicPs_SetStatusHandler(XIicPs *InstancePtr, void *CallBackRef,
+				  XIicPs_IntrHandler FunctionPtr)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FunctionPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FunctionPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_master.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_master.c
new file mode 100644
index 000000000..d49feecdf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_master.c
@@ -0,0 +1,987 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_master.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Handles master mode transfers.
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---  -------- ---------------------------------------------
+* 1.00a jz   01/30/10 First release
+* 1.00a sdm  09/21/11 Updated the XIicPs_SetupMaster to not check for
+*		      Bus Busy condition when the Hold Bit is set.
+* 1.01a sg   03/30/12 Fixed an issue in XIicPs_MasterSendPolled where a
+*		      check for transfer completion is added, which indicates
+*			 the completion of current transfer.
+* 2.0   hk   03/07/14 Added check for error status in the while loop that
+*                     checks for completion. CR# 762244, 764875.
+* 2.1   hk   04/24/14 Fix for CR# 789821 to handle >14 byte transfers.
+*                     Fix for CR# 761060 - provision for repeated start.
+* 2.2   hk   08/23/14 Slave monitor mode changes - clear FIFO, enable
+*                     read mode and clear transfer size register.
+*                     Disable NACK to avoid interrupts on each retry.
+* 2.3	sk	 10/06/14 Fill transmit fifo before address register when sending.
+* 					  Replaced XIICPS_DATA_INTR_DEPTH with XIICPS_FIFO_DEPTH.
+* 					  Repeated start feature removed.
+* 3.0	sk	 12/06/14 Implemented Repeated start feature.
+*			 01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*			 02/18/15 Implemented larger data transfer using repeated start
+*					  in Zynq UltraScale MP.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role);
+static void MasterSendData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven send in master mode.
+*
+* It tries to send the first FIFO-full of data, then lets the interrupt
+* handler to handle the rest of the data if there is any.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+ ****************************************************************************/
+void XIicPs_MasterSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+	InstancePtr->IsSend = 1;
+
+	/*
+	 * Set repeated start if sending more than FIFO of data.
+	 */
+	if (((InstancePtr->IsRepeatedStart) != 0)||
+		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+		XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET,
+			XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+				(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Setup as a master sending role.
+	 */
+	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	(void)TransmitFifoFill(InstancePtr);
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_ARB_LOST_MASK);
+	/*
+	 * Do the address transfer to notify the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+}
+
+/*****************************************************************************/
+/**
+* This function initiates an interrupt-driven receive in master mode.
+*
+* It sets the transfer size register so the slave can send data to us.
+* The rest of the work is managed by interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note		This receive routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_MasterRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount,
+		 u16 SlaveAddr)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->CurrByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+	InstancePtr->IsSend = 0;
+	InstancePtr->UpdateTxSize = 0;
+
+	if ((ByteCount > XIICPS_FIFO_DEPTH) ||
+		((InstancePtr->IsRepeatedStart) !=0))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	/*
+	 * Initialize for a master receiving role.
+	 */
+	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+	/*
+	 * Setup the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCount > XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		InstancePtr->CurrByteCount = (s32)XIICPS_MAX_TRANSFER_SIZE;
+		InstancePtr->UpdateTxSize = 1;
+	}else {
+		XIicPs_WriteReg(BaseAddr, (u32)(XIICPS_TRANS_SIZE_OFFSET),
+			 (u32)ByteCount);
+	}
+
+	XIicPs_EnableInterrupts(BaseAddr,
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_ARB_LOST_MASK);
+	/*
+	 * Do the address transfer to signal the slave.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode send in master mode.
+*
+* It sends data to the FIFO and waits for the slave to pick them up.
+* If slave fails to remove data from FIFO, the send fails with
+* time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+* @param	SlaveAddr is the address of the slave we are sending to.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterSendPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+		 s32 ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	u32 Intrs;
+	u32 Value;
+	s32 Status;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	if (((InstancePtr->IsRepeatedStart) != 0) ||
+		((ByteCount > XIICPS_FIFO_DEPTH) != 0U)) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+	}
+
+	(void)XIicPs_SetupMaster(InstancePtr, SENDING_ROLE);
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_TX_OVR_MASK |
+		(u32)XIICPS_IXR_NACK_MASK;
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Transmit first FIFO full of data.
+	 */
+	(void)TransmitFifoFill(InstancePtr);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Continue sending as long as there is more data and
+	 * there are no errors.
+	 */
+	Value = ((InstancePtr->SendByteCount > (s32)0) &&
+		((IntrStatusReg & Intrs) == (u32)0U));
+	while (Value != (u32)0x00U) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+		/*
+		 * Wait until transmit FIFO is empty.
+		 */
+		if ((StatusReg & XIICPS_SR_TXDV_MASK) != 0U) {
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					XIICPS_ISR_OFFSET);
+			Value = ((InstancePtr->SendByteCount > (s32)0) &&
+				((IntrStatusReg & Intrs) == (u32)0U));
+			continue;
+		}
+
+		/*
+		 * Send more data out through transmit FIFO.
+		 */
+		(void)TransmitFifoFill(InstancePtr);
+		Value = ((InstancePtr->SendByteCount > (s32)0) &&
+			((IntrStatusReg & Intrs) == (u32)0U));
+	}
+
+	/*
+	 * Check for completion of transfer.
+	 */
+	while ((IntrStatusReg & XIICPS_IXR_COMP_MASK) != XIICPS_IXR_COMP_MASK){
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		/*
+		 * If there is an error, tell the caller.
+		 */
+		if ((IntrStatusReg & Intrs) != 0U) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function initiates a polled mode receive in master mode.
+*
+* It repeatedly sets the transfer size register so the slave can
+* send data to us. It polls the data register for data to come in.
+* If slave fails to send us data, it fails with time out.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_MasterRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr,
+				s32 ByteCount, u16 SlaveAddr)
+{
+	u32 IntrStatusReg;
+	u32 Intrs;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 BytesToRecv;
+	s32 BytesToRead;
+	s32 TransSize;
+	s32 Tmp = 0;
+	u32 Status_Rcv;
+	u32 Status;
+	s32 Result;
+	s32 IsHold = 0;
+	s32 UpdateTxSize = 0;
+	s32 ByteCountVar = ByteCount;
+	u32 Platform;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCountVar;
+
+	Platform = XGetPlatform_Info();
+
+	if((ByteCountVar > XIICPS_FIFO_DEPTH) ||
+		((InstancePtr->IsRepeatedStart) !=0))
+	{
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) |
+						(u32)XIICPS_CR_HOLD_MASK);
+		IsHold = 1;
+	}
+
+	(void)XIicPs_SetupMaster(InstancePtr, RECVING_ROLE);
+
+	/*
+	 * Clear the interrupt status register before use it to monitor.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+	/*
+	 * Set up the transfer size register so the slave knows how much
+	 * to send to us.
+	 */
+	if (ByteCountVar > XIICPS_MAX_TRANSFER_SIZE) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+				XIICPS_MAX_TRANSFER_SIZE);
+		ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+		UpdateTxSize = 1;
+	}else {
+		XIicPs_WriteReg(BaseAddr, XIICPS_TRANS_SIZE_OFFSET,
+			 ByteCountVar);
+	}
+
+	/*
+	 * Intrs keeps all the error-related interrupts.
+	 */
+	Intrs = (u32)XIICPS_IXR_ARB_LOST_MASK | (u32)XIICPS_IXR_RX_OVR_MASK |
+			(u32)XIICPS_IXR_RX_UNF_MASK | (u32)XIICPS_IXR_NACK_MASK;
+	/*
+	 * Poll the interrupt status register to find the errors.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	while ((InstancePtr->RecvByteCount > 0) &&
+			((IntrStatusReg & Intrs) == 0U)) {
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	    while ((StatusReg & XIICPS_SR_RXDV_MASK) != 0U) {
+		    if (((InstancePtr->RecvByteCount <
+			    XIICPS_DATA_INTR_DEPTH) != 0U) && (IsHold != 0) &&
+			    ((!InstancePtr->IsRepeatedStart) != 0) &&
+			    (UpdateTxSize == 0)) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+		    ByteCountVar --;
+
+			if (Platform == XPLAT_ZYNQ) {
+			    if ((UpdateTxSize != 0) &&
+				    ((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+				    break;
+				}
+			}
+
+			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+		}
+		if (Platform == XPLAT_ZYNQ) {
+			if ((UpdateTxSize != 0) &&
+				((ByteCountVar == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+			    /*  wait while fifo is full */
+			    while (XIicPs_ReadReg(BaseAddr,
+				    XIICPS_TRANS_SIZE_OFFSET) !=
+				    (u32)(ByteCountVar - XIICPS_FIFO_DEPTH)) { ;
+				}
+
+				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+					XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE +
+							XIICPS_FIFO_DEPTH;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount -
+						XIICPS_FIFO_DEPTH);
+					UpdateTxSize = 0;
+				    ByteCountVar = InstancePtr->RecvByteCount;
+				}
+			}
+		} else {
+		    if ((InstancePtr->RecvByteCount > 0) && (ByteCountVar == 0)) {
+				/*
+				 * Clear the interrupt status register before use it to
+				 * monitor.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+				if ((InstancePtr->RecvByteCount) >
+					XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+				    ByteCountVar = (s32)XIICPS_MAX_TRANSFER_SIZE;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount);
+					UpdateTxSize = 0;
+				    ByteCountVar = InstancePtr->RecvByteCount;
+				}
+			}
+		}
+
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	}
+
+	if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+		XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+				XIicPs_ReadReg(BaseAddr,XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+	}
+	if ((IntrStatusReg & Intrs) != 0x0U) {
+		Result = (s32)XST_FAILURE;
+	}
+	else {
+		Result =  (s32)XST_SUCCESS;
+	}
+
+	return Result;
+}
+
+/*****************************************************************************/
+/**
+* This function enables the slave monitor mode.
+*
+* It enables slave monitor in the control register and enables
+* slave ready interrupt. It then does an address transfer to slave.
+* Interrupt handler will signal the caller if slave responds to
+* the address transfer.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we want to contact.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_EnableSlaveMonitor(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	u32 BaseAddr;
+	u32 ConfigReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/* Clear transfer size register */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_TRANS_SIZE_OFFSET, 0x0U);
+
+	/*
+	 * Enable slave monitor mode in control register.
+	 */
+	ConfigReg = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET);
+	ConfigReg |= (u32)XIICPS_CR_MS_MASK | (u32)XIICPS_CR_NEA_MASK |
+			(u32)XIICPS_CR_CLR_FIFO_MASK | (u32)XIICPS_CR_SLVMON_MASK;
+	ConfigReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_CR_OFFSET, ConfigReg);
+
+	/*
+	 * Set up interrupt flag for slave monitor interrupt.
+	 * Dont enable NACK.
+	 */
+	XIicPs_EnableInterrupts(BaseAddr, (u32)XIICPS_IXR_SLV_RDY_MASK);
+
+	/*
+	 * Initialize the slave monitor register.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_SLV_PAUSE_OFFSET, 0xFU);
+
+	/*
+	 * Set the slave address to start the slave address transmission.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function disables slave monitor mode.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XIicPs_DisableSlaveMonitor(XIicPs *InstancePtr)
+{
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Clear slave monitor control bit.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+		XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET)
+			& (~XIICPS_CR_SLVMON_MASK));
+
+	/*
+	 * Clear interrupt flag for slave monitor interrupt.
+	 */
+	XIicPs_DisableInterrupts(BaseAddr, XIICPS_IXR_SLV_RDY_MASK);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for the master mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper handling.
+*
+* 
+* The interrupts that are handled are:
+* - DATA
+*	This case is handled only for master receive data.
+*	The master has to request for more data (if there is more data to
+*	receive) and read the data from the FIFO .
+*
+* - COMP
+*	If the Master is transmitting data and there is more data to be
+*	sent then the data is written to the FIFO. If there is no more data to
+*	be transmitted then a completion event is signalled to the upper layer
+*	by calling the callback handler.
+*
+*	If the Master is receiving data then the data is read from the FIFO and
+*	the Master has to request for more data (if there is more data to
+*	receive). If all the data has been received then a completion event
+*	is signalled to the upper layer by calling the callback handler.
+*	It is an error if the amount of received data is more than expected.
+*
+* - NAK and SLAVE_RDY
+*	This is signalled to the upper layer by calling the callback handler.
+*
+* - All Other interrupts
+*	These interrupts are marked as error. This is signalled to the upper
+*	layer by calling the callback handler.
+*
+* 

+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_MasterInterruptHandler(XIicPs *InstancePtr)
+{
+	u32 IntrStatusReg;
+	u32 StatusEvent = 0U;
+	u32 BaseAddr;
+	u16 SlaveAddr;
+	s32 ByteCnt;
+	s32 IsHold;
+	u32 Platform;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	Platform = XGetPlatform_Info();
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+					 (u32)XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are
+	 * missed while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, (u32)XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, (u32)XIICPS_IMR_OFFSET));
+
+	ByteCnt = InstancePtr->CurrByteCount;
+
+	IsHold = 0;
+	if ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_CR_OFFSET) & (u32)XIICPS_CR_HOLD_MASK) != 0U) {
+		IsHold = 1;
+	}
+
+	/*
+	 * Send
+	 */
+	if (((InstancePtr->IsSend) != 0) &&
+		((u32)0U != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK))) {
+		if (InstancePtr->SendByteCount > 0) {
+			MasterSendData(InstancePtr);
+		} else {
+			StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+		}
+	}
+
+
+	/*
+	 * Receive
+	 */
+	if (((!(InstancePtr->IsSend))!= 0) &&
+		((0 != (IntrStatusReg & (u32)XIICPS_IXR_DATA_MASK)) ||
+		(0 != (IntrStatusReg & (u32)XIICPS_IXR_COMP_MASK)))){
+
+		while ((XIicPs_ReadReg(BaseAddr, (u32)XIICPS_SR_OFFSET) &
+				XIICPS_SR_RXDV_MASK) != 0U) {
+			if (((InstancePtr->RecvByteCount <
+				XIICPS_DATA_INTR_DEPTH)!= 0U)  && (IsHold != 0)  &&
+				((!InstancePtr->IsRepeatedStart)!= 0) &&
+				(InstancePtr->UpdateTxSize == 0)) {
+				IsHold = 0;
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			XIicPs_RecvByte(InstancePtr);
+			ByteCnt--;
+
+			if (Platform == XPLAT_ZYNQ) {
+			    if ((InstancePtr->UpdateTxSize != 0) &&
+				    ((ByteCnt == (XIICPS_FIFO_DEPTH + 1)) != 0U)) {
+				    break;
+				}
+			}
+		}
+
+		if (Platform == XPLAT_ZYNQ) {
+			if ((InstancePtr->UpdateTxSize != 0) &&
+				((ByteCnt == (XIICPS_FIFO_DEPTH + 1))!= 0U)) {
+				/* wait while fifo is full */
+				while (XIicPs_ReadReg(BaseAddr,
+					XIICPS_TRANS_SIZE_OFFSET) !=
+					(u32)(ByteCnt - XIICPS_FIFO_DEPTH)) {
+				}
+
+				if ((InstancePtr->RecvByteCount - XIICPS_FIFO_DEPTH) >
+					XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE +
+							XIICPS_FIFO_DEPTH;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount -
+						XIICPS_FIFO_DEPTH);
+					InstancePtr->UpdateTxSize = 0;
+					ByteCnt = InstancePtr->RecvByteCount;
+				}
+			}
+		} else {
+			if ((InstancePtr->RecvByteCount > 0) && (ByteCnt == 0)) {
+				/*
+				 * Clear the interrupt status register before use it to
+				 * monitor.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+				SlaveAddr = XIicPs_ReadReg(BaseAddr, (u32)XIICPS_ADDR_OFFSET);
+				XIicPs_WriteReg(BaseAddr, XIICPS_ADDR_OFFSET, SlaveAddr);
+
+				if ((InstancePtr->RecvByteCount) >
+					XIICPS_MAX_TRANSFER_SIZE) {
+
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						XIICPS_MAX_TRANSFER_SIZE);
+					ByteCnt = (s32)XIICPS_MAX_TRANSFER_SIZE;
+				} else {
+					XIicPs_WriteReg(BaseAddr,
+						XIICPS_TRANS_SIZE_OFFSET,
+						InstancePtr->RecvByteCount);
+					InstancePtr->UpdateTxSize = 0;
+					ByteCnt = InstancePtr->RecvByteCount;
+				}
+				XIicPs_EnableInterrupts(BaseAddr,
+					(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_DATA_MASK |
+					(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_COMP_MASK |
+					(u32)XIICPS_IXR_ARB_LOST_MASK);
+			}
+		}
+		InstancePtr->CurrByteCount = ByteCnt;
+	}
+
+	if (((!(InstancePtr->IsSend)) != 0) &&
+		(0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK))) {
+		/*
+		 * If all done, tell the application.
+		 */
+		if (InstancePtr->RecvByteCount == 0){
+			if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+				XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+						XIicPs_ReadReg(BaseAddr,
+						XIICPS_CR_OFFSET) &
+						(~XIICPS_CR_HOLD_MASK));
+			}
+			StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+		}
+	}
+
+
+	/*
+	 * Slave ready interrupt, it is only meaningful for master mode.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_SLV_RDY_MASK)) {
+		StatusEvent |= XIICPS_EVENT_SLAVE_RDY;
+	}
+
+	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		if ((!(InstancePtr->IsRepeatedStart)) != 0 ) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * Arbitration lost interrupt
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_ARB_LOST_MASK)) {
+		StatusEvent |= XIICPS_EVENT_ARB_LOST;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0U != (IntrStatusReg & (XIICPS_IXR_NACK_MASK |
+			XIICPS_IXR_RX_UNF_MASK | XIICPS_IXR_TX_OVR_MASK |
+			XIICPS_IXR_RX_OVR_MASK))) {
+		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+			XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+					XIicPs_ReadReg(BaseAddr,
+					XIICPS_CR_OFFSET) &
+					(~XIICPS_CR_HOLD_MASK));
+		}
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if (StatusEvent != 0U) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+
+}
+
+/*****************************************************************************/
+/*
+* This function prepares a device to transfers as a master.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @param	Role specifies whether the device is sending or receiving.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if bus is busy.
+*
+* @note		Interrupts are always disabled, device which needs to use
+*		interrupts needs to setup interrupts after this call.
+*
+****************************************************************************/
+static s32 XIicPs_SetupMaster(XIicPs *InstancePtr, s32 Role)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+	u32 EnabledIntr = 0x0U;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	ControlReg = XIicPs_ReadReg(BaseAddr, XIICPS_CR_OFFSET);
+
+
+	/*
+	 * Only check if bus is busy when repeated start option is not set.
+	 */
+	if ((ControlReg & XIICPS_CR_HOLD_MASK) == 0U) {
+		if (XIicPs_BusIsBusy(InstancePtr) == (s32)1) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK |
+			(u32)XIICPS_CR_NEA_MASK | (u32)XIICPS_CR_MS_MASK;
+
+	if (Role == RECVING_ROLE) {
+		ControlReg |= (u32)XIICPS_CR_RD_WR_MASK;
+		EnabledIntr = (u32)XIICPS_IXR_DATA_MASK |(u32)XIICPS_IXR_RX_OVR_MASK;
+	}else {
+		ControlReg &= (u32)(~XIICPS_CR_RD_WR_MASK);
+	}
+	EnabledIntr |= (u32)XIICPS_IXR_COMP_MASK | (u32)XIICPS_IXR_ARB_LOST_MASK;
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET, ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/*
+* This function handles continuation of sending data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+static void MasterSendData(XIicPs *InstancePtr)
+{
+	(void)TransmitFifoFill(InstancePtr);
+
+	/*
+	 * Clear hold bit if done, so stop can be sent out.
+	 */
+	if (InstancePtr->SendByteCount == 0) {
+
+		/*
+		 * If user has enabled repeated start as an option,
+		 * do not disable it.
+		 */
+		if ((!(InstancePtr->IsRepeatedStart)) != 0) {
+
+			XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			(u32)XIICPS_CR_OFFSET,
+			XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+			(u32)XIICPS_CR_OFFSET) & (u32)(~ XIICPS_CR_HOLD_MASK));
+		}
+	}
+
+	return;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_options.c
new file mode 100644
index 000000000..5d7427a48
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_options.c
@@ -0,0 +1,496 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_options.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Contains functions for the configuration of the XIccPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- -----------------------------------------------
+* 1.00a drg/jz  01/30/10 First release
+* 1.02a sg	08/29/12 Updated the logic to arrive at the best divisors
+*			 to achieve I2C clock with minimum error.
+*			 This is a fix for CR #674195
+* 1.03a hk  05/04/13 Initialized BestDivA and BestDivB to 0.
+*			 This is fix for CR#704398 to remove warning.
+* 2.0   hk  03/07/14 Limited frequency set when 100KHz or 400KHz is
+*                    selected. This is a hardware limitation. CR#779290.
+* 2.1   hk  04/24/14 Fix for CR# 761060 - provision for repeated start.
+* 2.3	sk	10/07/14 Repeated start feature removed.
+* 3.0	sk	12/06/14 Implemented Repeated start feature.
+*			01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+		u32 Option;
+		u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+		{XIICPS_7_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_10_BIT_ADDR_OPTION, XIICPS_CR_NEA_MASK},
+		{XIICPS_SLAVE_MON_OPTION, XIICPS_CR_SLVMON_MASK},
+		{XIICPS_REP_START_OPTION, XIICPS_CR_HOLD_MASK},
+};
+
+#define XIICPS_NUM_OPTIONS      (sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the IIC device driver. The options control
+* how the device behaves relative to the IIC bus. The device must be idle
+* rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_SetOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	u32 Index;
+	u32 OptionsVar = Options;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is requested, set the flag.
+	 * The hold bit in CR will be written by driver when the next transfer
+	 * is initiated.
+	 */
+	if ((OptionsVar & XIICPS_REP_START_OPTION) != 0U ) {
+		InstancePtr->IsRepeatedStart = 1;
+		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table, turning the option on.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so turning it on means
+			 * turning 7-bit option off.
+			 */
+			if ((OptionsTable[Index].Option &
+				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+			} else {
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+	/*
+	 * Now write to the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function clears the options for the IIC device driver. The options
+* control how the device behaves relative to the IIC bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	Options contains the specified options to be cleared. This is a
+*		bit mask where a 1 means to turn the option off. One or more bit
+*		values may be contained in the mask. See the bit definitions
+*		named XIICPS_*_OPTION in xiicps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XIicPs_ClearOptions(XIicPs *InstancePtr, u32 Options)
+{
+	u32 ControlReg;
+	u32 Index;
+	u32 OptionsVar = Options;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XIICPS_CR_OFFSET);
+
+	/*
+	 * If repeated start option is cleared, set the flag.
+	 * The hold bit in CR will be cleared by driver when the
+	 * following transfer ends.
+	 */
+	if ((OptionsVar & XIICPS_REP_START_OPTION) != (u32)0x0U ) {
+		InstancePtr->IsRepeatedStart = 0;
+		OptionsVar = OptionsVar & (~XIICPS_REP_START_OPTION);
+	}
+
+	/*
+	 * Loop through the options table and clear the specified options.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((OptionsVar & OptionsTable[Index].Option) != (u32)0x0U) {
+
+			/*
+			 * 10-bit option is specially treated, because it is
+			 * using the 7-bit option, so clearing it means turning
+			 * 7-bit option on.
+			 */
+			if ((OptionsTable[Index].Option &
+				XIICPS_10_BIT_ADDR_OPTION) != (u32)0x0U) {
+
+				/* Turn 7-bit on */
+				ControlReg |= OptionsTable[Index].Mask;
+			} else {
+
+				/* Turn 7-bit off */
+				ControlReg &= ~OptionsTable[Index].Mask;
+			}
+		}
+	}
+
+
+	/*
+	 * Now write the control register. Leave it to the upper layers
+	 * to restart the device.
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	/*
+	 * Keep a copy of what options this instance has.
+	 */
+	InstancePtr->Options = XIicPs_GetOptions(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the IIC device. The options control how
+* the device behaves relative to the IIC bus.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	32 bit mask of the options, where a 1 means the option is on,
+*		and a 0 means to the option is off. One or more bit values may
+*		be contained in the mask. See the bit definitions named
+* 		XIICPS_*_OPTION in the file xiicps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetOptions(XIicPs *InstancePtr)
+{
+	u32 OptionsFlag = 0U;
+	u32 ControlReg;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read control register to find which options are currently set.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				      XIICPS_CR_OFFSET);
+
+	/*
+	 * Loop through the options table to determine which options are set.
+	 */
+	for (Index = 0U; Index < XIICPS_NUM_OPTIONS; Index++) {
+		if ((ControlReg & OptionsTable[Index].Mask) != (u32)0x0U) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+		if ((ControlReg & XIICPS_CR_NEA_MASK) == (u32)0x0U) {
+			OptionsFlag |= XIICPS_10_BIT_ADDR_OPTION;
+		}
+	}
+
+	if (InstancePtr->IsRepeatedStart != 0 ) {
+		OptionsFlag |= XIICPS_REP_START_OPTION;
+	}
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* The data rate is set by values in the control register. The formula for
+* determining the correct register values is:
+* Fscl = Fpclk/(22 x (divisor_a+1) x (divisor_b+1))
+* See the hardware data sheet for a full explanation of setting the serial
+* clock rate.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	FsclHz is the clock frequency in Hz. The two most common clock
+*		rates are 100KHz and 400KHz.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_IS_STARTED if the device is currently transferring
+*		data. The transfer must complete or be aborted before setting
+*		options.
+*		- XST_FAILURE if the Fscl frequency can not be set.
+*
+* @note		The clock can not be faster than the input clock divide by 22.
+*
+******************************************************************************/
+s32 XIicPs_SetSClk(XIicPs *InstancePtr, u32 FsclHz)
+{
+	u32 Div_a;
+	u32 Div_b;
+	u32 ActualFscl;
+	u32 Temp;
+	u32 TempLimit;
+	u32 LastError;
+	u32 BestError;
+	u32 CurrentError;
+	u32 ControlReg;
+	u32 CalcDivA;
+	u32 CalcDivB;
+	u32 BestDivA = 0;
+	u32 BestDivB = 0;
+	u32 FsclHzVar = FsclHz;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(FsclHzVar > 0U);
+
+	if (0U != XIicPs_In32((InstancePtr->Config.BaseAddress) +
+					XIICPS_TRANS_SIZE_OFFSET)) {
+		return (s32)XST_DEVICE_IS_STARTED;
+	}
+
+	/*
+	 * Assume Div_a is 0 and calculate (divisor_a+1) x (divisor_b+1).
+	 */
+	Temp = (InstancePtr->Config.InputClockHz) / ((u32)22U * FsclHzVar);
+
+	/*
+	 * If the answer is negative or 0, the Fscl input is out of range.
+	 */
+	if ((u32)(0U) == Temp) {
+		return (s32)XST_FAILURE;
+	}
+
+	/*
+	 * If frequency 400KHz is selected, 384.6KHz should be set.
+	 * If frequency 100KHz is selected, 90KHz should be set.
+	 * This is due to a hardware limitation.
+	 */
+	if(FsclHzVar > 384600U) {
+		FsclHzVar = 384600U;
+	}
+
+	if((FsclHzVar <= 100000U) && (FsclHzVar > 90000U)) {
+		FsclHzVar = 90000U;
+	}
+
+	/*
+	 * TempLimit helps in iterating over the consecutive value of Temp to
+	 * find the closest clock rate achievable with divisors.
+	 * Iterate over the next value only if fractional part is involved.
+	 */
+	TempLimit = (((InstancePtr->Config.InputClockHz) %
+			((u32)22 * FsclHzVar)) != 	(u32)0x0U) ?
+						Temp + (u32)1U : Temp;
+	BestError = FsclHzVar;
+
+	BestDivA = 0U;
+	BestDivB = 0U;
+	for ( ; Temp <= TempLimit ; Temp++)
+	{
+		LastError = FsclHzVar;
+		CalcDivA = 0U;
+		CalcDivB = 0U;
+
+		for (Div_b = 0U; Div_b < 64U; Div_b++) {
+
+			Div_a = Temp / (Div_b + 1U);
+
+			if (Div_a != 0U){
+				Div_a = Div_a - (u32)1U;
+			}
+			if (Div_a > 3U){
+				continue;
+			}
+			ActualFscl = (InstancePtr->Config.InputClockHz) /
+						(22U * (Div_a + 1U) * (Div_b + 1U));
+
+			if (ActualFscl > FsclHzVar){
+				CurrentError = (ActualFscl - FsclHzVar);}
+			else{
+				CurrentError = (FsclHzVar - ActualFscl);}
+
+			if (LastError > CurrentError) {
+				CalcDivA = Div_a;
+				CalcDivB = Div_b;
+				LastError = CurrentError;
+			}
+		}
+
+		/*
+		 * Used to capture the best divisors.
+		 */
+		if (LastError < BestError) {
+			BestError = LastError;
+			BestDivA = CalcDivA;
+			BestDivB = CalcDivB;
+		}
+	}
+
+
+	/*
+	 * Read the control register and mask the Divisors.
+	 */
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  (u32)XIICPS_CR_OFFSET);
+	ControlReg &= ~((u32)XIICPS_CR_DIV_A_MASK | (u32)XIICPS_CR_DIV_B_MASK);
+	ControlReg |= (BestDivA << XIICPS_CR_DIV_A_SHIFT) |
+		(BestDivB << XIICPS_CR_DIV_B_SHIFT);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress, (u32)XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the serial clock rate for the IIC device. The device
+* must be idle rather than busy transferring data before setting these device
+* options.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	The value of the IIC clock to the nearest Hz based on the
+*		control register settings. The actual value may not be exact to
+*		to integer math rounding errors.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XIicPs_GetSClk(XIicPs *InstancePtr)
+{
+	u32 ControlReg;
+	u32 ActualFscl;
+	u32 Div_a;
+	u32 Div_b;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	ControlReg = XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XIICPS_CR_OFFSET);
+
+	Div_a = (ControlReg & XIICPS_CR_DIV_A_MASK) >> XIICPS_CR_DIV_A_SHIFT;
+	Div_b = (ControlReg & XIICPS_CR_DIV_B_MASK) >> XIICPS_CR_DIV_B_SHIFT;
+
+	ActualFscl = (InstancePtr->Config.InputClockHz) /
+		(22U * (Div_a + 1U) * (Div_b + 1U));
+
+	return ActualFscl;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_selftest.c
new file mode 100644
index 000000000..2d9e0e35e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_selftest.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_selftest.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* This component contains the implementation of selftest functions for the
+* XIicPs driver component.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 1.00a sdm    09/22/11 Removed unused code
+* 3.0	sk	   11/03/14 Removed TimeOut Register value check
+*			   01/31/15	Modified the code according to MISRAC 2012 Compliant.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+#define REG_TEST_VALUE    0x00000005U
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device. The self-test is destructive in that
+* a reset of the device is performed in order to check the reset values of
+* the registers and to get the device into a known state.
+*
+* Upon successful return from the self-test, the device is reset.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_REGISTER_ERROR indicates a register did not read or write
+*		correctly
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XIicPs_SelfTest(XIicPs *InstancePtr)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the IIC registers should be in their default state right now.
+	 */
+	if ((XIICPS_CR_RESET_VALUE !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_CR_OFFSET)) ||
+		(XIICPS_IXR_ALL_INTR_MASK !=
+		 XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XIICPS_IMR_OFFSET))) {
+		return (s32)XST_FAILURE;
+	}
+
+	XIicPs_Reset(InstancePtr);
+
+	/*
+	 * Write, Read then write a register
+	 */
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, REG_TEST_VALUE);
+
+	if (REG_TEST_VALUE != XIicPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XIICPS_SLV_PAUSE_OFFSET)) {
+		return (s32)XST_FAILURE;
+	}
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_SLV_PAUSE_OFFSET, 0U);
+
+	XIicPs_Reset(InstancePtr);
+
+	return (s32)XST_SUCCESS;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_sinit.c
new file mode 100644
index 000000000..40ee7733e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_sinit.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xiicps_sinit.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* The implementation of the XIicPs component's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- --------------------------------------------
+* 1.00a drg/jz 01/30/10 First release
+* 3.00	sk	   01/31/15	Modified the code according to MISRAC 2012 Compliant.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XIicPs_Config XIicPs_ConfigTable[XPAR_XIICPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return	A pointer to the configuration found or NULL if the specified
+*		device ID was not found. See xiicps.h for the definition of
+*		XIicPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XIicPs_Config *XIicPs_LookupConfig(u16 DeviceId)
+{
+	XIicPs_Config *CfgPtr = NULL;
+	s32 Index;
+
+	for (Index = 0; Index < XPAR_XIICPS_NUM_INSTANCES; Index++) {
+		if (XIicPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XIicPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XIicPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_slave.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_slave.c
new file mode 100644
index 000000000..074b5ea2e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/iicps_v3_1/src/xiicps_slave.c
@@ -0,0 +1,590 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xiicps_slave.c
+* @addtogroup iicps_v3_0
+* @{
+*
+* Handles slave transfers
+*
+* 
 MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --  -------- ---------------------------------------------
+* 1.00a jz  01/30/10 First release
+* 1.04a kpc 08/30/13 Avoid buffer overwrite in SlaveRecvData function
+* 3.00	sk	01/31/15 Modified the code according to MISRAC 2012 Compliant.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xiicps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+extern s32 TransmitFifoFill(XIicPs *InstancePtr);
+
+static s32 SlaveRecvData(XIicPs *InstancePtr);
+
+/************************* Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function sets up the device to be a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	SlaveAddr is the address of the slave we are receiving from.
+*
+* @return	None.
+*
+* @note
+*	Interrupt is always enabled no matter the tranfer is interrupt-
+*	driven or polled mode. Whether device will be interrupted or not
+*	depends on whether the device is connected to an interrupt
+*	controller and interrupt for the device is enabled.
+*
+****************************************************************************/
+void XIicPs_SetupSlave(XIicPs *InstancePtr, u16 SlaveAddr)
+{
+	u32 ControlReg;
+	u32 BaseAddr;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(XIICPS_ADDR_MASK >= SlaveAddr);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	ControlReg = XIicPs_In32(BaseAddr + XIICPS_CR_OFFSET);
+
+	/*
+	 * Set up master, AckEn, nea and also clear fifo.
+	 */
+	ControlReg |= (u32)XIICPS_CR_ACKEN_MASK | (u32)XIICPS_CR_CLR_FIFO_MASK;
+	ControlReg |= (u32)XIICPS_CR_NEA_MASK;
+	ControlReg &= (u32)(~XIICPS_CR_MS_MASK);
+
+	XIicPs_WriteReg(BaseAddr, XIICPS_CR_OFFSET,
+			  ControlReg);
+
+	XIicPs_DisableAllInterrupts(BaseAddr);
+
+	XIicPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XIICPS_ADDR_OFFSET, (u32)SlaveAddr);
+
+	return;
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven send. It set the repeated
+* start for the device is the tranfer size is larger than FIFO depth.
+* Data processing for the send is initiated by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return	None.
+*
+* @note		This send routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveSend(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+	InstancePtr->RecvBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(BaseAddr,
+			(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+			(u32)XIICPS_IXR_TO_MASK | (u32)XIICPS_IXR_NACK_MASK |
+			(u32)XIICPS_IXR_TX_OVR_MASK);
+}
+
+/*****************************************************************************/
+/**
+* This function setup a slave interrupt-driven receive.
+* Data processing for the receive is handled by the interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return	None.
+*
+* @note		This routine is for interrupt-driven transfer only.
+*
+****************************************************************************/
+void XIicPs_SlaveRecv(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(MsgPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+	InstancePtr->SendBufferPtr = NULL;
+
+	XIicPs_EnableInterrupts(InstancePtr->Config.BaseAddress,
+		(u32)XIICPS_IXR_DATA_MASK | (u32)XIICPS_IXR_COMP_MASK |
+		(u32)XIICPS_IXR_NACK_MASK | (u32)XIICPS_IXR_TO_MASK |
+		(u32)XIICPS_IXR_RX_OVR_MASK | (u32)XIICPS_IXR_RX_UNF_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+* This function sends  a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the send buffer.
+* @param	ByteCount is the number of bytes to be sent.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if master sends us data or master terminates the
+*		transfer before all data has sent out.
+*
+* @note		This send routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveSendPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Tmp;
+	s32 BytesToSend;
+	s32 Error = 0;
+	s32 Status = (s32)XST_SUCCESS;
+	u32 Value;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->SendBufferPtr = MsgPtr;
+	InstancePtr->SendByteCount = ByteCount;
+
+	/*
+	 * Use RXRW bit in status register to wait master to start a read.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	while (((StatusReg & XIICPS_SR_RXRW_MASK) == 0U) &&
+				((!Error) != 0)) {
+
+		/*
+		 * If master tries to send us data, it is an error.
+		 */
+		if ((StatusReg & XIICPS_SR_RXDV_MASK) != 0x0U) {
+			Error = 1;
+		}
+
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	}
+
+	if (Error != 0) {
+		Status = (s32)XST_FAILURE;
+	} else {
+
+		/*
+		 * Clear the interrupt status register.
+		 */
+		IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+		XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+		/*
+		 * Send data as long as there is more data to send and
+		 * there are no errors.
+		 */
+		Value = (InstancePtr->SendByteCount > (s32)0) &&
+						((!Error) != 0);
+		while (Value != (u32)0x00U) {
+
+			/*
+			 * Find out how many can be sent.
+			 */
+			BytesToSend = InstancePtr->SendByteCount;
+			if (BytesToSend > (s32)(XIICPS_FIFO_DEPTH)) {
+				BytesToSend = (s32)(XIICPS_FIFO_DEPTH);
+			}
+
+			for(Tmp = 0; Tmp < BytesToSend; Tmp ++) {
+				XIicPs_SendByte(InstancePtr);
+			}
+
+			StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+			/*
+			 * Wait for master to read the data out of fifo.
+			 */
+			while (((StatusReg & XIICPS_SR_TXDV_MASK) != (u32)0x00U) &&
+							((!Error) != 0)) {
+
+				/*
+				 * If master terminates the transfer before all data is
+				 * sent, it is an error.
+				 */
+				IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+				XIICPS_ISR_OFFSET);
+				if ((IntrStatusReg & XIICPS_IXR_NACK_MASK) != 0x0U) {
+					Error = 1;
+				}
+
+				/* Clear ISR.
+				 */
+				XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+							IntrStatusReg);
+
+				StatusReg = XIicPs_ReadReg(BaseAddr,
+						XIICPS_SR_OFFSET);
+			}
+			Value = (InstancePtr->SendByteCount > (s32)0U) &&
+							((!Error) != 0);
+		}
+	}
+	if (Error != 0) {
+	Status = (s32)XST_FAILURE;
+	}
+
+	return Status;
+}
+/*****************************************************************************/
+/**
+* This function receives a buffer in polled mode as a slave.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+* @param	MsgPtr is the pointer to the receive buffer.
+* @param	ByteCount is the number of bytes to be received.
+*
+* @return
+*		- XST_SUCCESS if everything went well.
+*		- XST_FAILURE if timed out.
+*
+* @note		This receive routine is for polled mode transfer only.
+*
+****************************************************************************/
+s32 XIicPs_SlaveRecvPolled(XIicPs *InstancePtr, u8 *MsgPtr, s32 ByteCount)
+{
+	u32 IntrStatusReg;
+	u32 StatusReg;
+	u32 BaseAddr;
+	s32 Count;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+	InstancePtr->RecvBufferPtr = MsgPtr;
+	InstancePtr->RecvByteCount = ByteCount;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	/*
+	 * Clear the interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Clear the status register.
+	 */
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	XIicPs_WriteReg(BaseAddr, XIICPS_SR_OFFSET, StatusReg);
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	Count = InstancePtr->RecvByteCount;
+	while (Count > (s32)0) {
+
+		/* Wait for master to put data */
+		while ((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) {
+		    StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+			/*
+			 * If master terminates the transfer before we get all
+			 * the data or the master tries to read from us,
+			 * it is an error.
+			 */
+			IntrStatusReg = XIicPs_ReadReg(BaseAddr,
+						XIICPS_ISR_OFFSET);
+			if (((IntrStatusReg & (XIICPS_IXR_DATA_MASK |
+					XIICPS_IXR_COMP_MASK))!=0x0U) &&
+				((StatusReg & XIICPS_SR_RXDV_MASK) == 0U) &&
+				((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+
+				return (s32)XST_FAILURE;
+			}
+
+			/*
+			 * Clear the interrupt status register.
+			 */
+			XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET,
+			IntrStatusReg);
+		}
+
+		/*
+		 * Read all data from FIFO.
+		 */
+		while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+			 ((InstancePtr->RecvByteCount > 0) != 0x0U)){
+
+			XIicPs_RecvByte(InstancePtr);
+
+			StatusReg = XIicPs_ReadReg(BaseAddr,
+				XIICPS_SR_OFFSET);
+		}
+		Count = InstancePtr->RecvByteCount;
+	}
+
+	return (s32)XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* The interrupt handler for slave mode. It does the protocol handling for
+* the interrupt-driven transfers.
+*
+* Completion events and errors are signaled to upper layer for proper
+* handling.
+*
+* 
+*
+* The interrupts that are handled are:
+* - DATA
+*	If the instance is sending, it means that the master wants to read more
+*	data from us. Send more data, and check whether we are done with this
+*	send.
+*
+*	If the instance is receiving, it means that the master has writen
+* 	more data to us. Receive more data, and check whether we are done with
+*	with this receive.
+*
+* - COMP
+*	This marks that stop sequence has been sent from the master, transfer
+*	is about to terminate. However, for receiving, the master may have
+*	written us some data, so receive that first.
+*
+*	It is an error if the amount of transfered data is less than expected.
+*
+* - NAK
+*	This marks that master does not want our data. It is for send only.
+*
+* - Other interrupts
+*	These interrupts are marked as error.
+*
+* 

+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	None.
+*
+* @note 	None.
+*
+****************************************************************************/
+void XIicPs_SlaveInterruptHandler(XIicPs *InstancePtr)
+{
+	u32 IntrStatusReg;
+	u32 IsSend = 0U;
+	u32 StatusEvent = 0U;
+	s32 LeftOver;
+	u32 BaseAddr;
+
+	/*
+	 * Assert validates the input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == (u32)XIL_COMPONENT_IS_READY);
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	/*
+	 * Read the Interrupt status register.
+	 */
+	IntrStatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_ISR_OFFSET);
+
+	/*
+	 * Write the status back to clear the interrupts so no events are missed
+	 * while processing this interrupt.
+	 */
+	XIicPs_WriteReg(BaseAddr, XIICPS_ISR_OFFSET, IntrStatusReg);
+
+	/*
+	 * Use the Mask register AND with the Interrupt Status register so
+	 * disabled interrupts are not processed.
+	 */
+	IntrStatusReg &= ~(XIicPs_ReadReg(BaseAddr, XIICPS_IMR_OFFSET));
+
+	/*
+	 * Determine whether the device is sending.
+	 */
+	if (InstancePtr->RecvBufferPtr == NULL) {
+		IsSend = 1U;
+	}
+
+	/* Data interrupt
+	 *
+	 * This means master wants to do more data transfers.
+	 * Also check for completion of transfer, signal upper layer if done.
+	 */
+	if ((u32)0U != (IntrStatusReg & XIICPS_IXR_DATA_MASK)) {
+		if (IsSend != 0x0U) {
+			LeftOver = TransmitFifoFill(InstancePtr);
+				/*
+				 * We may finish send here
+				 */
+				if (LeftOver == 0) {
+					StatusEvent |=
+						XIICPS_EVENT_COMPLETE_SEND;
+				}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+
+			/* We may finish the receive here */
+			if (LeftOver == 0) {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Complete interrupt.
+	 *
+	 * In slave mode, it means the master has done with this transfer, so
+	 * we signal the application using completion event.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_COMP_MASK)) {
+		if (IsSend != 0x0U) {
+			if (InstancePtr->SendByteCount > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			}else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_SEND;
+			}
+		} else {
+			LeftOver = SlaveRecvData(InstancePtr);
+			if (LeftOver > 0) {
+				StatusEvent |= XIICPS_EVENT_ERROR;
+			} else {
+				StatusEvent |= XIICPS_EVENT_COMPLETE_RECV;
+			}
+		}
+	}
+
+	/*
+	 * Nack interrupt, pass this information to application.
+	 */
+	if (0U != (IntrStatusReg & XIICPS_IXR_NACK_MASK)) {
+		StatusEvent |= XIICPS_EVENT_NACK;
+	}
+
+	/*
+	 * All other interrupts are treated as error.
+	 */
+	if (0U != (IntrStatusReg & (XIICPS_IXR_TO_MASK |
+				XIICPS_IXR_RX_UNF_MASK |
+				XIICPS_IXR_TX_OVR_MASK |
+				XIICPS_IXR_RX_OVR_MASK))){
+
+		StatusEvent |= XIICPS_EVENT_ERROR;
+	}
+
+	/*
+	 * Signal application if there are any events.
+	 */
+	if (0U != StatusEvent) {
+		InstancePtr->StatusHandler(InstancePtr->CallBackRef,
+					   StatusEvent);
+	}
+}
+
+/*****************************************************************************/
+/*
+*
+* This function handles continuation of receiving data. It is invoked
+* from interrupt handler.
+*
+* @param	InstancePtr is a pointer to the XIicPs instance.
+*
+* @return	Number of bytes still expected by the instance.
+*
+* @note		None.
+*
+****************************************************************************/
+static s32 SlaveRecvData(XIicPs *InstancePtr)
+{
+	u32 StatusReg;
+	u32 BaseAddr;
+
+	BaseAddr = InstancePtr->Config.BaseAddress;
+
+	StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+
+	while (((StatusReg & XIICPS_SR_RXDV_MASK)!=0x0U) &&
+			((InstancePtr->RecvByteCount > 0) != 0x0U)) {
+		XIicPs_RecvByte(InstancePtr);
+		StatusReg = XIicPs_ReadReg(BaseAddr, XIICPS_SR_OFFSET);
+	}
+
+	return InstancePtr->RecvByteCount;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/Makefile
new file mode 100644
index 000000000..3e1fc71f7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xipipsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ipipsu"
+
+xipipsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xipipsu_includes
+
+xipipsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.c
new file mode 100644
index 000000000..f8f902330
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.c
@@ -0,0 +1,352 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xipipsu.c
+* @addtogroup ipipsu_v1_0
+* @{
+*
+* This file contains the implementation of the interface functions for XIpiPsu
+* driver. Refer to the header file xipipsu.h for more detailed information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver	Who	Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	mjr	03/15/15	First Release
+* 2.0	mjr	01/22/16	Fixed response buffer address
+*                               calculation. CR# 932582.
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xipipsu.h"
+#include "xipipsu_hw.h"
+
+/****************************************************************************/
+/**
+ * Initialize the Instance pointer based on a given Config Pointer
+ *
+ * @param	InstancePtr is a pointer to the instance to be worked on
+ * @param	CfgPtr is the device configuration structure containing required
+ *		  	hardware build data
+ * @param	EffectiveAddress is the base address of the device. If address
+ *        	translation is not utilized, this parameter can be passed in using
+ *        	CfgPtr->Config.BaseAddress to specify the physical base address.
+ * @return	XST_SUCCESS if initialization was successful
+ * 			XST_FAILURE in case of failure
+ *
+ */
+
+XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
+		UINTPTR EffectiveAddress)
+{
+	u32 Index;
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr != NULL);
+	/* Set device base address and ID */
+	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddress;
+	InstancePtr->Config.BitMask = CfgPtr->BitMask;
+	InstancePtr->Config.IntId = CfgPtr->IntId;
+
+	InstancePtr->Config.TargetCount = CfgPtr->TargetCount;
+
+	for (Index = 0; Index < CfgPtr->TargetCount; Index++) {
+		InstancePtr->Config.TargetList[Index].Mask =
+				CfgPtr->TargetList[Index].Mask;
+		InstancePtr->Config.TargetList[Index].BufferIndex =
+				CfgPtr->TargetList[Index].BufferIndex;
+	}
+
+	/* Mark the component as Ready */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	return (XST_SUCCESS);
+}
+
+/**
+ * @brief	Reset the given IPI register set.
+ *        	This function can be called to disable the IPIs from all
+ *        	the sources and clear any pending IPIs in status register
+ *
+ * @param 	InstancePtr is the pointer to current IPI instance
+ *
+ */
+
+void XIpiPsu_Reset(XIpiPsu *InstancePtr)
+{
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/**************Disable***************/
+
+	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_IDR_OFFSET,
+			XIPIPSU_ALL_MASK);
+
+	/**************Clear***************/
+	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_ISR_OFFSET,
+			XIPIPSU_ALL_MASK);
+
+}
+
+/**
+ * @brief	Trigger an IPI to a Destination CPU
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	DestCpuMask is the Mask of the CPU to which IPI is to be triggered
+ *
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if an error occurred
+ */
+
+XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask)
+{
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Trigger an IPI to the Target */
+	XIpiPsu_WriteReg(InstancePtr->Config.BaseAddress, XIPIPSU_TRIG_OFFSET,
+			DestCpuMask);
+	return XST_SUCCESS;
+
+}
+
+/**
+ * @brief Poll for an acknowledgement using Observation Register
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	DestCpuMask is the Mask of the destination CPU from which ACK is expected
+ * @param	TimeOutCount is the Count after which the routines returns failure
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if a timeout occurred
+ */
+
+XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
+		u32 TimeOutCount)
+{
+	u32 Flag, PollCount;
+	XStatus Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	PollCount = 0;
+	/* Poll the OBS register until the corresponding DestCpu bit is cleared */
+	do {
+		Flag = (XIpiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XIPIPSU_OBS_OFFSET)) & (DestCpuMask);
+		PollCount++;
+		/* Check if the IPI was Acknowledged by the Target or we Timed Out*/
+	} while ((0x00000000U != Flag) && (PollCount < TimeOutCount));
+
+	if (PollCount >= TimeOutCount) {
+		Status = XST_FAILURE;
+	} else {
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/**
+ * @brief	Get the Buffer Index for a CPU specified by Mask
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	CpuMask is the Mask of the CPU form which Index is required
+ *
+ * @return	Buffer Index value if CPU Mask is valid
+ * 			XIPIPSU_MAX_BUFF_INDEX+1 if not valid
+ *
+ * @note	Static function used only by XIpiPsu_GetBufferAddress
+ *
+ */
+static u32 XIpiPsu_GetBufferIndex(XIpiPsu *InstancePtr, u32 CpuMask)
+{
+	u32 BufferIndex;
+	u32 Index;
+	/* Init Index with an invalid value */
+	BufferIndex = XIPIPSU_MAX_BUFF_INDEX + 1;
+
+	/*Search for CPU in the List */
+	for (Index = 0; Index < InstancePtr->Config.TargetCount; Index++) {
+		/*If we find the CPU , then set the Index and break the loop*/
+		if (InstancePtr->Config.TargetList[Index].Mask == CpuMask) {
+			BufferIndex = InstancePtr->Config.TargetList[Index].BufferIndex;
+			break;
+		}
+	}
+
+	/* Return the Index */
+	return BufferIndex;
+}
+
+/**
+ * @brief	Get the Buffer Address for a given pair of CPUs
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	SrcCpuMask is the Mask for Source CPU
+ * @param	DestCpuMask is the Mask for Destination CPU
+ * @param	BufferType is either XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP
+ *
+ * @return	Valid Buffer Address if no error
+ * 			NULL if an error occurred in calculating Address
+ *
+ */
+
+static u32* XIpiPsu_GetBufferAddress(XIpiPsu *InstancePtr, u32 SrcCpuMask,
+		u32 DestCpuMask, u32 BufferType)
+{
+#ifdef __aarch64__
+	u64 BufferAddr;
+#else
+	u32 BufferAddr;
+#endif
+
+	u32 SrcIndex;
+	u32 DestIndex;
+	/* Get the buffer indices */
+	SrcIndex = XIpiPsu_GetBufferIndex(InstancePtr, SrcCpuMask);
+	DestIndex = XIpiPsu_GetBufferIndex(InstancePtr, DestCpuMask);
+
+	/* If we got an invalid buffer index, then return NULL pointer, else valid address */
+	if ((SrcIndex > XIPIPSU_MAX_BUFF_INDEX)
+			|| (DestIndex > XIPIPSU_MAX_BUFF_INDEX)) {
+		BufferAddr = 0U;
+	} else {
+
+		if (XIPIPSU_BUF_TYPE_MSG == BufferType) {
+			BufferAddr = XIPIPSU_MSG_RAM_BASE
+					+ (SrcIndex * XIPIPSU_BUFFER_OFFSET_GROUP)
+					+ (DestIndex * XIPIPSU_BUFFER_OFFSET_TARGET);
+		} else if (XIPIPSU_BUF_TYPE_RESP == BufferType) {
+			BufferAddr = XIPIPSU_MSG_RAM_BASE
+					+ (DestIndex * XIPIPSU_BUFFER_OFFSET_GROUP)
+					+ (SrcIndex * XIPIPSU_BUFFER_OFFSET_TARGET)
+					+ (XIPIPSU_BUFFER_OFFSET_RESPONSE);
+		} else {
+			BufferAddr = 0U;
+		}
+
+	}
+
+	return (u32 *) BufferAddr;
+}
+
+/**
+ * @brief	Read an Incoming Message from a Source
+ *
+ * @param 	InstancePtr is the pointer to current IPI instance
+ * @param 	SrcCpuMask is the Device Mask for the CPU which has sent the message
+ * @param 	MsgPtr is the pointer to Buffer to which the read message needs to be stored
+ * @param 	MsgLength is the length of the buffer/message
+ * @param 	BufType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if an error occurred
+ */
+
+XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufferType)
+{
+	u32 *BufferPtr;
+	u32 Index;
+	u32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
+
+	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr, TargetMask,
+			InstancePtr->Config.BitMask, BufferType);
+	if (BufferPtr != NULL) {
+		/* Copy the IPI Buffer contents into Users's Buffer*/
+		for (Index = 0; Index < MsgLength; Index++) {
+			MsgPtr[Index] = BufferPtr[Index];
+		}
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	return Status;
+}
+
+
+/**
+ * @brief	Send a Message to Destination
+ *
+ * @param	InstancePtr is the pointer to current IPI instance
+ * @param	DestCpuMask is the Device Mask for the destination CPU
+ * @param	MsgPtr is the pointer to Buffer which contains the message to be sent
+ * @param	MsgLength is the length of the buffer/message
+ * @param	BufType is the type of buffer (XIPIPSU_BUF_TYPE_MSG or XIPIPSU_BUF_TYPE_RESP)
+ *
+ * @return	XST_SUCCESS if successful
+ * 			XST_FAILURE if an error occurred
+ */
+
+XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 TargetMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufferType)
+{
+	u32 *BufferPtr;
+	u32 Index;
+	u32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MsgPtr != NULL);
+	Xil_AssertNonvoid(MsgLength <= XIPIPSU_MAX_MSG_LEN);
+
+	BufferPtr = XIpiPsu_GetBufferAddress(InstancePtr,
+			InstancePtr->Config.BitMask, TargetMask, BufferType);
+	if (BufferPtr != NULL) {
+		/* Copy the Message to IPI Buffer */
+		for (Index = 0; Index < MsgLength; Index++) {
+			BufferPtr[Index] = MsgPtr[Index];
+		}
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.h
new file mode 100644
index 000000000..7eb8e5469
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu.h
@@ -0,0 +1,281 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+ * @file xipipsu.h
+* @addtogroup ipipsu_v1_0
+* @{
+* @details
+ *
+ * This is the header file for implementation of IPIPSU driver.
+ * Inter Processor Interrupt (IPI) is used for communication between
+ * different processors on ZynqMP SoC. Each IPI register set has Trigger, Status
+ * and Observation registers for communication between processors. Each IPI path
+ * has a 32 byte buffer associated with it and these buffers are located in the
+ * XPPU RAM. This driver supports the following operations:
+ *
+ * - Trigger IPIs to CPUs on the SoC
+ * - Write and Read Message buffers
+ * - Read the status of Observation Register to get status of Triggered IPI
+ * - Enable/Disable IPIs from selected Masters
+ * - Read the Status register to get the source of an incoming IPI
+ *
+ * Initialization
+ * The config data for the driver is loaded and is based on the HW build. The
+ * XIpiPsu_Config data structure contains all the data related to the
+ * IPI driver instance and also teh available Target CPUs.
+ *
+ * Sending an IPI
+ * The following steps can be followed to send an IPI:
+ * - Write the Message into Message Buffer using XIpiPsu_WriteMessage()
+ * - Trigger IPI using XIpiPsu_TriggerIpi()
+ * - Wait for Ack using XIpiPsu_PollForAck()
+ * - Read response using XIpiPsu_ReadMessage()
+ *
+ * @note	XIpiPsu_GetObsStatus() before sending an IPI to ensure that the
+ * previous IPI was serviced by the target
+ *
+ * Receiving an IPI
+ * To receive an IPI, the following sequence can be followed:
+ * - Register an interrupt handler for the IPIs interrupt ID
+ * - Enable the required sources using XIpiPsu_InterruptEnable()
+ * - In the interrupt handler, Check for source using XIpiPsu_GetInterruptStatus
+ * - Read the message form source using XIpiPsu_ReadMessage()
+ * - Write the response using XIpiPsu_WriteMessage()
+ * - Ack the IPI using XIpiPsu_ClearInterruptStatus()
+ *
+ * @note	XIpiPsu_Reset can be used at startup to clear the status and
+ * disable all sources
+ *
+ */
+/*****************************************************************************/
+#ifndef XIPIPSU_H_
+#define XIPIPSU_H_
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xstatus.h"
+#include "xipipsu_hw.h"
+
+/************************** Constant Definitions *****************************/
+#define XIPIPSU_BUF_TYPE_MSG	(0x00000001U)
+#define XIPIPSU_BUF_TYPE_RESP	(0x00000002U)
+#define XIPIPSU_MAX_MSG_LEN		XIPIPSU_MSG_BUF_SIZE
+/**************************** Type Definitions *******************************/
+/**
+ * Data structure used to refer IPI Targets
+ */
+typedef struct {
+	u32 Mask; /**< Bit Mask for the target */
+	u32 BufferIndex; /**< Buffer Index used for calculating buffer address */
+} XIpiPsu_Target;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u32 DeviceId; /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of the device */
+	u32 BitMask; /**< BitMask to be used to identify this CPU */
+	u32 BufferIndex; /**< Index of the IPI Message Buffer */
+	u32 IntId; /**< Interrupt ID on GIC **/
+	u32 TargetCount; /**< Number of available IPI Targets */
+	XIpiPsu_Target TargetList[XIPIPSU_MAX_TARGETS] ; /** < List of IPI Targets */
+} XIpiPsu_Config;
+
+/**
+ * The XIpiPsu driver instance data. The user is required to allocate a
+ * variable of this type for each IPI device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XIpiPsu_Config Config; /**< Configuration structure */
+	u32 IsReady; /**< Device is initialized and ready */
+	u32 Options; /**< Options set in the device */
+} XIpiPsu;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/**
+*
+* Read the register specified by the base address and offset
+*
+* @param	BaseAddress is the base address of the IPI instance
+* @param	RegOffset is the offset of the register relative to base
+*
+* @return	Value of the specified register
+* @note
+* C-style signature
+*	u32 XIpiPsu_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+
+#define XIpiPsu_ReadReg(BaseAddress, RegOffset) \
+		Xil_In32((BaseAddress) + (RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write a value into a register specified by base address and offset
+*
+* @param BaseAddress is the base address of the IPI instance
+* @param RegOffset is the offset of the register relative to base
+* @param Data is a 32-bit value that is to be written into the specified register
+*
+* @note
+* C-style signature
+*	void XIpiPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+
+#define XIpiPsu_WriteReg(BaseAddress, RegOffset, Data) \
+		Xil_Out32(((BaseAddress) + (RegOffset)), (Data))
+
+/****************************************************************************/
+/**
+*
+* Enable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be enabled.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Mask contains a bit mask of interrupts to enable. The mask can
+*			be formed using a set of bitwise or'd values of individual CPU masks
+*
+* @note
+* C-style signature
+*	void XIpiPsu_InterruptEnable(XIpiPsu *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XIpiPsu_InterruptEnable(InstancePtr, Mask) \
+	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_IER_OFFSET, \
+		((Mask) & XIPIPSU_ALL_MASK));
+
+/****************************************************************************/
+/**
+*
+* Disable interrupts specified in Mask. The corresponding interrupt for
+* each bit set to 1 in Mask, will be disabled.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Mask contains a bit mask of interrupts to disable. The mask can
+*			be formed using a set of bitwise or'd values of individual CPU masks
+*
+* @note
+* C-style signature
+*	void XIpiPsu_InterruptDisable(XIpiPsu *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+#define XIpiPsu_InterruptDisable(InstancePtr, Mask)  \
+	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_IDR_OFFSET, \
+		((Mask) & XIPIPSU_ALL_MASK));
+/****************************************************************************/
+/**
+*
+* Get the STATUS REGISTER of the current IPI instance.
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @return Returns the Interrupt Status register(ISR) contents
+* @note User needs to parse this 32-bit value to check the source CPU
+* C-style signature
+*	u32 XIpiPsu_GetInterruptStatus(XIpiPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XIpiPsu_GetInterruptStatus(InstancePtr)  \
+	XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_ISR_OFFSET)
+/****************************************************************************/
+/**
+*
+* Clear the STATUS REGISTER of the current IPI instance.
+* The corresponding interrupt status for
+* each bit set to 1 in Mask, will be cleared
+*
+* @param InstancePtr is a pointer to the instance to be worked on.
+* @param Mask corresponding to the source CPU*
+*
+* @note This function should be used after handling the IPI.
+* Clearing the status will automatically clear the corresponding bit in
+* OBSERVATION register of Source CPU
+* C-style signature
+*	void XIpiPsu_ClearInterruptStatus(XIpiPsu *InstancePtr, u32 Mask)
+*
+*****************************************************************************/
+
+#define XIpiPsu_ClearInterruptStatus(InstancePtr, Mask)  \
+	XIpiPsu_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_ISR_OFFSET, \
+		((Mask) & XIPIPSU_ALL_MASK));
+/****************************************************************************/
+/**
+*
+* Get the OBSERVATION REGISTER of the current IPI instance.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @return	Returns the Observation register(OBS) contents
+* @note		User needs to parse this 32-bit value to check the status of
+*			individual CPUs
+* C-style signature
+*	u32 XIpiPsu_GetObsStatus(XIpiPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XIpiPsu_GetObsStatus(InstancePtr)  \
+	XIpiPsu_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XIPIPSU_OBS_OFFSET)
+/****************************************************************************/
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xipipsu_sinit.c */
+
+XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId);
+
+/* Interface Functions implemented in xipipsu.c */
+
+XStatus XIpiPsu_CfgInitialize(XIpiPsu *InstancePtr, XIpiPsu_Config * CfgPtr,
+		UINTPTR EffectiveAddress);
+
+void XIpiPsu_Reset(XIpiPsu *InstancePtr);
+
+XStatus XIpiPsu_TriggerIpi(XIpiPsu *InstancePtr, u32 DestCpuMask);
+
+XStatus XIpiPsu_PollForAck(XIpiPsu *InstancePtr, u32 DestCpuMask,
+		u32 TimeOutCount);
+
+XStatus XIpiPsu_ReadMessage(XIpiPsu *InstancePtr, u32 SrcCpuMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufType);
+
+XStatus XIpiPsu_WriteMessage(XIpiPsu *InstancePtr, u32 DestCpuMask, u32 *MsgPtr,
+		u32 MsgLength, u8 BufType);
+
+#endif /* XIPIPSU_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
new file mode 100644
index 000000000..f5728c502
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_g.c
@@ -0,0 +1,161 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xipipsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XIpiPsu_Config XIpiPsu_ConfigTable[] =
+{
+
+	{
+		XPAR_PSU_IPI_1_DEVICE_ID,
+		XPAR_PSU_IPI_1_BASE_ADDRESS,
+		XPAR_PSU_IPI_1_BIT_MASK,
+		XPAR_PSU_IPI_1_BUFFER_INDEX,
+		XPAR_PSU_IPI_1_INT_ID,
+		XPAR_XIPIPSU_NUM_TARGETS,
+		{
+
+			{
+				XPAR_PSU_IPI_0_BIT_MASK,
+				XPAR_PSU_IPI_0_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_1_BIT_MASK,
+				XPAR_PSU_IPI_1_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_2_BIT_MASK,
+				XPAR_PSU_IPI_2_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_3_BIT_MASK,
+				XPAR_PSU_IPI_3_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_4_BIT_MASK,
+				XPAR_PSU_IPI_4_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_5_BIT_MASK,
+				XPAR_PSU_IPI_5_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_6_BIT_MASK,
+				XPAR_PSU_IPI_6_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_7_BIT_MASK,
+				XPAR_PSU_IPI_7_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_8_BIT_MASK,
+				XPAR_PSU_IPI_8_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_9_BIT_MASK,
+				XPAR_PSU_IPI_9_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_10_BIT_MASK,
+				XPAR_PSU_IPI_10_BUFFER_INDEX
+			}
+		}
+	},
+
+	{
+		XPAR_PSU_IPI_2_DEVICE_ID,
+		XPAR_PSU_IPI_2_BASE_ADDRESS,
+		XPAR_PSU_IPI_2_BIT_MASK,
+		XPAR_PSU_IPI_2_BUFFER_INDEX,
+		XPAR_PSU_IPI_2_INT_ID,
+		XPAR_XIPIPSU_NUM_TARGETS,
+		{
+
+			{
+				XPAR_PSU_IPI_0_BIT_MASK,
+				XPAR_PSU_IPI_0_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_1_BIT_MASK,
+				XPAR_PSU_IPI_1_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_2_BIT_MASK,
+				XPAR_PSU_IPI_2_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_3_BIT_MASK,
+				XPAR_PSU_IPI_3_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_4_BIT_MASK,
+				XPAR_PSU_IPI_4_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_5_BIT_MASK,
+				XPAR_PSU_IPI_5_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_6_BIT_MASK,
+				XPAR_PSU_IPI_6_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_7_BIT_MASK,
+				XPAR_PSU_IPI_7_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_8_BIT_MASK,
+				XPAR_PSU_IPI_8_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_9_BIT_MASK,
+				XPAR_PSU_IPI_9_BUFFER_INDEX
+			},
+			{
+				XPAR_PSU_IPI_10_BIT_MASK,
+				XPAR_PSU_IPI_10_BUFFER_INDEX
+			}
+		}
+	}
+};
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_hw.h
new file mode 100644
index 000000000..d24a8ea0a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_hw.h
@@ -0,0 +1,79 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/**
+*
+* @file xipipsu_hw.h
+* @addtogroup ipipsu_v1_0
+* @{
+*
+* This file contains macro definitions for low level HW related params
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   mjr  03/15/15 First release
+*
+* 

+*
+******************************************************************************/
+#ifndef XIPIPSU_HW_H_	/* prevent circular inclusions */
+#define XIPIPSU_HW_H_	/* by using protection macros */
+
+/************************** Constant Definitions *****************************/
+/* Message RAM related params */
+#define XIPIPSU_MSG_RAM_BASE 0xFF990000U
+#define XIPIPSU_MSG_BUF_SIZE 8U	/* Size in Words */
+#define XIPIPSU_MAX_BUFF_INDEX	7
+
+/* EIGHT pairs of TWO buffers(msg+resp) of THIRTY TWO bytes each */
+#define XIPIPSU_BUFFER_OFFSET_GROUP	(8U * 2U * 32U)
+#define XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U)
+#define XIPIPSU_BUFFER_OFFSET_RESPONSE		(32U)
+
+/* Max Number of IPI slots on the device */
+#define XIPIPSU_MAX_TARGETS	11
+
+/* Register Offsets for each member  of IPI Register Set */
+#define XIPIPSU_TRIG_OFFSET 0x00U
+#define XIPIPSU_OBS_OFFSET 0x04U
+#define XIPIPSU_ISR_OFFSET 0x10U
+#define XIPIPSU_IMR_OFFSET 0x14U
+#define XIPIPSU_IER_OFFSET 0x18U
+#define XIPIPSU_IDR_OFFSET 0x1CU
+
+/* MASK of all valid IPI bits in above registers */
+#define XIPIPSU_ALL_MASK	0x0F0F0301U
+
+#endif /* XIPIPSU_HW_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_sinit.c
new file mode 100644
index 000000000..26495c8dd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ipipsu_v2_0/src/xipipsu_sinit.c
@@ -0,0 +1,90 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/**
+*
+* @file xipipsu_sinit.c
+* @addtogroup ipipsu_v1_0
+* @{
+*
+* The implementation of the XIpiPsu component's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   mjr  03/15/15 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xparameters.h"
+#include "xipipsu.h"
+
+/************************** Variable Definitions *****************************/
+extern XIpiPsu_Config XIpiPsu_ConfigTable[];
+
+/*****************************************************************************/
+
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*			configuration for.
+*
+* @return	A pointer to the configuration found or NULL if the specified
+*			device ID was not found. See xipipsu.h for the definition of
+*			XIpiPsu_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XIpiPsu_Config *XIpiPsu_LookupConfig(u32 DeviceId)
+{
+	XIpiPsu_Config *CfgPtr = NULL;
+	int Index;
+
+	for (Index = 0; Index < XPAR_XIPIPSU_NUM_INSTANCES; Index++) {
+		if (XIpiPsu_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XIpiPsu_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/Makefile
new file mode 100644
index 000000000..88a66dd93
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xqspipsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling qspipsu"
+
+xqspipsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xqspipsu_includes
+
+xqspipsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.c
new file mode 100644
index 000000000..cd415ae07
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.c
@@ -0,0 +1,1290 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu.c
+* @addtogroup qspipsu_v1_0
+* @{
+*
+* This file implements the functions required to use the QSPIPSU hardware to
+* perform a transfer. These are accessible to the user via xqspipsu.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   hk  08/21/14 First release
+*       sk  03/13/15 Added IO mode support.
+*       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
+*                    Clear and disbale DMA interrupts/status in abort.
+*                    Use DMA DONE bit instead of BUSY as recommended.
+*       sk  04/24/15 Modified the code according to MISRAC-2012.
+*       sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
+*                    writing/reading from 0x0 location is permitted.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspipsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+			u32 ByteCount);
+static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode);
+static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+			u32 *GenFifoEntry);
+static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg, s32 Size);
+static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg);
+static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr);
+static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg, s32 Index);
+static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr);
+static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
+			XQspiPsu_Msg *Msg, s32 Size);
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XQspiPsu instance such that the driver is ready to use.
+*
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific QSPIPSU device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+	s32 Status;
+
+	/*
+	 * If the device is busy, disallow the initialize and return a status
+	 * indicating it is already started. This allows the user to stop the
+	 * device and re-initialize, but prevents a user from inadvertently
+	 * initializing. This assumes the busy flag is cleared at startup.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_IS_STARTED;
+	} else {
+
+		/* Set some default values. */
+		InstancePtr->IsBusy = FALSE;
+
+		InstancePtr->Config.BaseAddress = EffectiveAddr + XQSPIPSU_OFFSET;
+		InstancePtr->Config.ConnectionMode = ConfigPtr->ConnectionMode;
+		InstancePtr->StatusHandler = StubStatusHandler;
+		InstancePtr->Config.BusWidth = ConfigPtr->BusWidth;
+
+		/* Other instance variable initializations */
+		InstancePtr->SendBufferPtr = NULL;
+		InstancePtr->RecvBufferPtr = NULL;
+		InstancePtr->GenFifoBufferPtr = NULL;
+		InstancePtr->TxBytes = 0;
+		InstancePtr->RxBytes = 0;
+		InstancePtr->GenFifoEntries = 0;
+		InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
+		InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
+		InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
+		InstancePtr->IsUnaligned = 0;
+		InstancePtr->IsManualstart = TRUE;
+
+		/* Select QSPIPSU */
+		XQspiPsu_Select(InstancePtr);
+
+		/*
+		 * Reset the QSPIPSU device to get it into its initial state. It is
+		 * expected that device configuration will take place after this
+		 * initialization is done, but before the device is started.
+		 */
+		XQspiPsu_Reset(InstancePtr);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Resets the QSPIPSU device. Reset must only be called after the driver has
+* been initialized. Any data transfer that is in progress is aborted.
+*
+* The upper layer software is responsible for re-configuring (if necessary)
+* and restarting the QSPIPSU device after the reset.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XQspiPsu_Reset(XQspiPsu *InstancePtr)
+{
+	u32 ConfigReg;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Abort any transfer that is in progress */
+	XQspiPsu_Abort(InstancePtr);
+
+	/* Default value to config register */
+	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_CFG_OFFSET);
+
+	/* DMA mode */
+	ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+	ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
+	/* Manual start */
+	ConfigReg |= XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK;
+	/* Little endain by default */
+	ConfigReg &= ~XQSPIPSU_CFG_ENDIAN_MASK;
+	/* Disable poll timeout */
+	ConfigReg &= ~XQSPIPSU_CFG_EN_POLL_TO_MASK;
+	/* Set hold bit */
+	ConfigReg |= XQSPIPSU_CFG_WP_HOLD_MASK;
+	/* Clear prescalar by default */
+	ConfigReg &= (u32)(~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK);
+	/* CPOL CPHA 00 */
+	ConfigReg &= (u32)(~XQSPIPSU_CFG_CLK_PHA_MASK);
+	ConfigReg &= (u32)(~XQSPIPSU_CFG_CLK_POL_MASK);
+
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_CFG_OFFSET, ConfigReg);
+
+	/* Set by default to allow for high frequencies */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_LPBK_DLY_ADJ_OFFSET,
+		XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_LPBK_DLY_ADJ_OFFSET) |
+			XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK);
+
+	/* Reset thresholds */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_TX_THRESHOLD_OFFSET,
+		XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_RX_THRESHOLD_OFFSET,
+		XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_GF_THRESHOLD_OFFSET,
+		XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL);
+
+	/* DMA init */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET,
+			XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Aborts a transfer in progress by
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None.
+*
+* @note
+*
+******************************************************************************/
+void XQspiPsu_Abort(XQspiPsu *InstancePtr)
+{
+
+	u32 IntrStatus, ConfigReg;
+
+	IntrStatus = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					XQSPIPSU_ISR_OFFSET);
+
+	/* Clear and disable interrupts */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_ISR_OFFSET, IntrStatus | XQSPIPSU_ISR_WR_TO_CLR_MASK);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
+		XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET));
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_STS_OFFSET,
+			XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_QSPIDMA_DST_STS_OFFSET) |
+				XQSPIPSU_QSPIDMA_DST_STS_WTC);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_IDR_OFFSET, XQSPIPSU_IDR_ALL_MASK);
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
+			XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK);
+
+	/* Clear FIFO */
+	if((XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_ISR_OFFSET) & XQSPIPSU_ISR_RXEMPTY_MASK) != FALSE) {
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_FIFO_CTRL_OFFSET,
+			XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK |
+			XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK);
+	}
+
+	/*
+	 * Switch to IO mode to Clear RX FIFO. This is becuase of DMA behaviour
+	 * where it waits on RX empty and goes busy assuming there is data
+	 * to be transfered even if there is no request.
+	 */
+	if ((IntrStatus & XQSPIPSU_ISR_RXEMPTY_MASK) != 0U) {
+		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					XQSPIPSU_CFG_OFFSET);
+		ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_CFG_OFFSET, ConfigReg);
+
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_FIFO_CTRL_OFFSET,
+				XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK);
+
+		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+			ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
+			XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+					XQSPIPSU_CFG_OFFSET, ConfigReg);
+		}
+	}
+
+	/* Disable QSPIPSU */
+	XQspiPsu_Disable(InstancePtr);
+
+	InstancePtr->TxBytes = 0;
+	InstancePtr->RxBytes = 0;
+	InstancePtr->GenFifoEntries = 0;
+	InstancePtr->IsBusy = FALSE;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function performs a transfer on the bus in polled mode. The messages
+* passed are all transferred on the bus between one CS assert and de-assert.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	NumMsg is the number of messages to be transferred.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*		- XST_DEVICE_BUSY if a transfer is already in progress.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				u32 NumMsg)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	s32 Index;
+	u32 QspiPsuStatusReg, DmaStatusReg;
+	u32 BaseAddress;
+	s32 Status;
+	s32 RxThr;
+	u32 IOPending = (u32)FALSE;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	for (Index = 0; Index < (s32)NumMsg; Index++) {
+		Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
+	}
+
+	/* Check whether there is another transfer in progress. Not thread-safe */
+	if (InstancePtr->IsBusy == TRUE) {
+		return (s32)XST_DEVICE_BUSY;
+	}
+
+	/* Check for ByteCount upper limit - 2^28 for DMA */
+	for (Index = 0; Index < (s32)NumMsg; Index++) {
+		if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
+				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared when the transfer is
+	 * entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+
+	/* Enable */
+	XQspiPsu_Enable(InstancePtr);
+
+	/* Select slave */
+	XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
+
+	/* list */
+	Index = 0;
+	while (Index < (s32)NumMsg) {
+		XQspiPsu_GenFifoEntryData(InstancePtr, Msg, Index);
+
+		if (InstancePtr->IsManualstart == TRUE) {
+			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
+				XQspiPsu_ReadReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET) |
+					XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+		}
+
+		/* Use thresholds here */
+		/* If there is more data to be transmitted */
+		do {
+			QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_ISR_OFFSET);
+
+			/* Transmit more data if left */
+			if (((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) != FALSE) &&
+				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
+				(InstancePtr->TxBytes > 0)) {
+				XQspiPsu_FillTxFifo(InstancePtr, &Msg[Index],
+						XQSPIPSU_TXD_DEPTH);
+			}
+
+			/* Check if DMA RX is complete and update RxBytes */
+			if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) &&
+				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+				u32 DmaIntrSts;
+				DmaIntrSts = XQspiPsu_ReadReg(BaseAddress,
+								XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
+				if ((DmaIntrSts & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) != FALSE) {
+					XQspiPsu_WriteReg(BaseAddress,
+						XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET,
+						DmaIntrSts);
+					/* Read remaining bytes using IO mode */
+					if((InstancePtr->RxBytes % 4) != 0 ) {
+						XQspiPsu_WriteReg(BaseAddress,
+							XQSPIPSU_CFG_OFFSET,
+							(XQspiPsu_ReadReg(BaseAddress,
+							XQSPIPSU_CFG_OFFSET) &
+							~XQSPIPSU_CFG_MODE_EN_MASK));
+						InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
+						Msg[Index].ByteCount =
+							(InstancePtr->RxBytes % 4);
+						Msg[Index].RxBfrPtr += (InstancePtr->RxBytes -
+								(InstancePtr->RxBytes % 4));
+						InstancePtr->IsUnaligned = 1;
+						IOPending = (u32)TRUE;
+						break;
+					}
+					InstancePtr->RxBytes = 0;
+				}
+			} else {
+				if ((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE) {
+					/* Check if PIO RX is complete and update RxBytes */
+					RxThr = (s32)XQspiPsu_ReadReg(BaseAddress,
+							XQSPIPSU_RX_THRESHOLD_OFFSET);
+					if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
+									!= 0U) {
+						XQspiPsu_ReadRxFifo(InstancePtr,
+								&Msg[Index], RxThr*4);
+
+					} else {
+						if ((QspiPsuStatusReg &
+							XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != 0U) {
+								XQspiPsu_ReadRxFifo(InstancePtr,
+									&Msg[Index], InstancePtr->RxBytes);
+						}
+					}
+				}
+			}
+		} while (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE) ||
+			(InstancePtr->TxBytes != 0) ||
+			((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) == FALSE) ||
+			(InstancePtr->RxBytes != 0));
+
+		if((InstancePtr->IsUnaligned != 0) && (IOPending == (u32)FALSE)) {
+			InstancePtr->IsUnaligned = 0;
+			XQspiPsu_WriteReg(BaseAddress,
+				XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
+				BaseAddress,
+				XQSPIPSU_CFG_OFFSET) |
+				XQSPIPSU_CFG_MODE_EN_DMA_MASK));
+			InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
+		}
+
+		if (IOPending == (u32)TRUE) {
+			IOPending = (u32)FALSE;
+		} else {
+			Index++;
+		}
+	}
+
+	/* De-select slave */
+	XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
+
+	if (InstancePtr->IsManualstart == TRUE) {
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
+			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
+				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+	}
+
+	QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_ISR_OFFSET);
+	while ((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) == FALSE) {
+		QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_ISR_OFFSET);
+	}
+
+	/* Clear the busy flag. */
+	InstancePtr->IsBusy = FALSE;
+
+	/* Disable the device. */
+	XQspiPsu_Disable(InstancePtr);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function initiates a transfer on the bus and enables interrupts.
+* The transfer is completed by the interrupt handler. The messages passed are
+* all transferred on the bus between one CS assert and de-assert.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	NumMsg is the number of messages to be transferred.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*		- XST_DEVICE_BUSY if a transfer is already in progress.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				u32 NumMsg)
+{
+	u32 StatusReg;
+	u32 ConfigReg;
+	s32 Index;
+	u32 BaseAddress;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	for (Index = 0; Index < (s32)NumMsg; Index++) {
+		Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
+	}
+
+	/* Check whether there is another transfer in progress. Not thread-safe */
+	if (InstancePtr->IsBusy == TRUE) {
+		return (s32)XST_DEVICE_BUSY;
+	}
+
+	/* Check for ByteCount upper limit - 2^28 for DMA */
+	for (Index = 0; Index < (s32)NumMsg; Index++) {
+		if ((Msg[Index].ByteCount > XQSPIPSU_DMA_BYTES_MAX) &&
+				((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+			return (s32)XST_FAILURE;
+		}
+	}
+
+	/*
+	 * Set the busy flag, which will be cleared when the transfer is
+	 * entirely done.
+	 */
+	InstancePtr->IsBusy = TRUE;
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+
+	InstancePtr->Msg = Msg;
+	InstancePtr->NumMsg = (s32)NumMsg;
+	InstancePtr->MsgCnt = 0;
+
+	/* Enable */
+	XQspiPsu_Enable(InstancePtr);
+
+	/* Select slave */
+	XQspiPsu_GenFifoEntryCSAssert(InstancePtr);
+
+	/* This might not work if not manual start */
+	/* Put first message in FIFO along with the above slave select */
+	XQspiPsu_GenFifoEntryData(InstancePtr, Msg, 0);
+
+	if (InstancePtr->IsManualstart == TRUE) {
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
+			XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) |
+				XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+	}
+
+	/* Enable interrupts */
+	XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IER_OFFSET,
+		(u32)XQSPIPSU_IER_TXNOT_FULL_MASK | (u32)XQSPIPSU_IER_TXEMPTY_MASK |
+		(u32)XQSPIPSU_IER_RXNEMPTY_MASK | (u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
+		(u32)XQSPIPSU_IER_RXEMPTY_MASK);
+
+	if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET,
+				XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr)
+{
+	u32 QspiPsuStatusReg, DmaIntrStatusReg = 0;
+	u32 BaseAddress;
+	XQspiPsu_Msg *Msg;
+	s32 NumMsg;
+	s32 MsgCnt;
+	u8 DeltaMsgCnt = 0;
+	s32 RxThr;
+	u32 TxRxFlag;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+	Msg = InstancePtr->Msg;
+	NumMsg = InstancePtr->NumMsg;
+	MsgCnt = InstancePtr->MsgCnt;
+	TxRxFlag = Msg[MsgCnt].Flags;
+
+	/* QSPIPSU Intr cleared on read */
+	QspiPsuStatusReg = XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_ISR_OFFSET);
+	if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+		/* DMA Intr write to clear */
+		DmaIntrStatusReg = XQspiPsu_ReadReg(BaseAddress,
+					XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET);
+
+		XQspiPsu_WriteReg(BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET, DmaIntrStatusReg);
+	}
+	if (((QspiPsuStatusReg & XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK) != FALSE) ||
+		((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK) != FALSE)) {
+		/* Call status handler to indicate error */
+		InstancePtr->StatusHandler(InstancePtr->StatusRef,
+					XST_SPI_COMMAND_ERROR, 0);
+	}
+
+	/* Fill more data to be txed if required */
+	if ((MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
+		((QspiPsuStatusReg & XQSPIPSU_ISR_TXNOT_FULL_MASK) != FALSE) &&
+		(InstancePtr->TxBytes > 0)) {
+		XQspiPsu_FillTxFifo(InstancePtr, &Msg[MsgCnt],
+				XQSPIPSU_TXD_DEPTH);
+	}
+
+	/*
+	 * Check if the entry is ONLY TX and increase MsgCnt.
+	 * This is to allow TX and RX together in one entry - corner case.
+	 */
+	if ((MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
+		((QspiPsuStatusReg & XQSPIPSU_ISR_TXEMPTY_MASK) != FALSE) &&
+		((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
+		(InstancePtr->TxBytes == 0) &&
+		((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) == FALSE)) {
+		MsgCnt += 1;
+		DeltaMsgCnt = 1U;
+	}
+
+	if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) &&
+		(MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+		if ((DmaIntrStatusReg & XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK) != FALSE) {
+				/* Read remaining bytes using IO mode */
+			if((InstancePtr->RxBytes % 4) != 0 ) {
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET, (XQspiPsu_ReadReg(
+					BaseAddress, XQSPIPSU_CFG_OFFSET) &
+					~XQSPIPSU_CFG_MODE_EN_MASK));
+				InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
+				Msg[MsgCnt].ByteCount = (InstancePtr->RxBytes % 4);
+				Msg[MsgCnt].RxBfrPtr += (InstancePtr->RxBytes -
+						(InstancePtr->RxBytes % 4));
+				InstancePtr->IsUnaligned = 1;
+				XQspiPsu_GenFifoEntryData(InstancePtr, Msg,
+						MsgCnt);
+				if(InstancePtr->IsManualstart == TRUE) {
+					XQspiPsu_WriteReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET,
+						XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET) |
+						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+				}
+			}
+			else {
+				InstancePtr->RxBytes = 0;
+				MsgCnt += 1;
+				DeltaMsgCnt = 1U;
+			}
+		}
+	} else {
+		if ((MsgCnt < NumMsg) && ((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+			if (InstancePtr->RxBytes != 0) {
+				if ((QspiPsuStatusReg & XQSPIPSU_ISR_RXNEMPTY_MASK)
+								!= FALSE) {
+					RxThr = (s32)XQspiPsu_ReadReg(BaseAddress,
+								XQSPIPSU_RX_THRESHOLD_OFFSET);
+					XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
+						RxThr*4);
+				} else {
+					if (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
+						((QspiPsuStatusReg & XQSPIPSU_ISR_RXEMPTY_MASK) == FALSE)) {
+						XQspiPsu_ReadRxFifo(InstancePtr, &Msg[MsgCnt],
+							InstancePtr->RxBytes);
+					}
+				}
+				if (InstancePtr->RxBytes == 0) {
+					MsgCnt += 1;
+					DeltaMsgCnt = 1U;
+				}
+			}
+		}
+	}
+
+	/*
+	 * Dummy byte transfer
+	 * MsgCnt < NumMsg check is to ensure is it a valid dummy cycle message
+	 * If one of the above conditions increased MsgCnt, then
+	 * the new message is yet to be placed in the FIFO; hence !DeltaMsgCnt.
+	 */
+	if ((MsgCnt < NumMsg) && (DeltaMsgCnt == FALSE) &&
+		((TxRxFlag & XQSPIPSU_MSG_FLAG_RX) == FALSE) &&
+		((TxRxFlag & XQSPIPSU_MSG_FLAG_TX) == FALSE) &&
+		((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE)) {
+		MsgCnt += 1;
+		DeltaMsgCnt = 1U;
+	}
+	InstancePtr->MsgCnt = MsgCnt;
+
+	/*
+	 * DeltaMsgCnt is to handle conditions where genfifo empty can be set
+	 * while tx is still not empty or rx dma is not yet done.
+	 * MsgCnt > NumMsg indicates CS de-assert entry was also executed.
+	 */
+	if (((QspiPsuStatusReg & XQSPIPSU_ISR_GENFIFOEMPTY_MASK) != FALSE) &&
+		((DeltaMsgCnt != FALSE) || (MsgCnt > NumMsg))) {
+		if (MsgCnt < NumMsg) {
+			if(InstancePtr->IsUnaligned != 0) {
+				InstancePtr->IsUnaligned = 0;
+				XQspiPsu_WriteReg(InstancePtr->Config.
+					BaseAddress, XQSPIPSU_CFG_OFFSET,
+					(XQspiPsu_ReadReg(InstancePtr->Config.
+					BaseAddress, XQSPIPSU_CFG_OFFSET) |
+					XQSPIPSU_CFG_MODE_EN_DMA_MASK));
+				InstancePtr->ReadMode = XQSPIPSU_READMODE_DMA;
+			}
+			/* This might not work if not manual start */
+			XQspiPsu_GenFifoEntryData(InstancePtr, Msg, MsgCnt);
+
+			if (InstancePtr->IsManualstart == TRUE) {
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET,
+					XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET) |
+						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+			}
+		} else if (MsgCnt == NumMsg) {
+			/* This is just to keep track of the de-assert entry */
+			MsgCnt += 1;
+			InstancePtr->MsgCnt = MsgCnt;
+
+			/* De-select slave */
+			XQspiPsu_GenFifoEntryCSDeAssert(InstancePtr);
+
+			if (InstancePtr->IsManualstart == TRUE) {
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_CFG_OFFSET,
+					XQspiPsu_ReadReg(BaseAddress,
+						XQSPIPSU_CFG_OFFSET) |
+						XQSPIPSU_CFG_START_GEN_FIFO_MASK);
+			}
+		} else {
+			/* Disable interrupts */
+			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_IDR_OFFSET,
+					(u32)XQSPIPSU_IER_TXNOT_FULL_MASK |
+					(u32)XQSPIPSU_IER_TXEMPTY_MASK |
+					(u32)XQSPIPSU_IER_RXNEMPTY_MASK |
+					(u32)XQSPIPSU_IER_GENFIFOEMPTY_MASK |
+					(u32)XQSPIPSU_IER_RXEMPTY_MASK);
+			if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET,
+					XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK);
+			}
+
+			/* Clear the busy flag. */
+			InstancePtr->IsBusy = FALSE;
+
+			/* Disable the device. */
+			XQspiPsu_Disable(InstancePtr);
+
+			/* Call status handler to indicate completion */
+			InstancePtr->StatusHandler(InstancePtr->StatusRef,
+						XST_SPI_TRANSFER_DONE, 0);
+		}
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the status callback function, the status handler, which the driver
+* calls when it encounters conditions that should be reported to upper
+* layer software. The handler executes in an interrupt context, so it must
+* minimize the amount of processing performed. One of the following status
+* events is passed to the status handler.
+*
+* 
+*
+* XST_SPI_TRANSFER_DONE		The requested data transfer is done
+*
+* XST_SPI_TRANSMIT_UNDERRUN	As a slave device, the master clocked data
+*				but there were none available in the transmit
+*				register/FIFO. This typically means the slave
+*				application did not issue a transfer request
+*				fast enough, or the processor/driver could not
+*				fill the transmit register/FIFO fast enough.
+*
+* XST_SPI_RECEIVE_OVERRUN	The QSPIPSU device lost data. Data was received
+*				but the receive data register/FIFO was full.
+*
+* 

+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+* @param	FuncPointer is the pointer to the callback function.
+*
+* @return	None.
+*
+* @note
+*
+* The handler is called within interrupt context, so it should do its work
+* quickly and queue potentially time-consuming work to a task-level thread.
+*
+******************************************************************************/
+void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
+				XQspiPsu_StatusHandler FuncPointer)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPointer != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->StatusHandler = FuncPointer;
+	InstancePtr->StatusRef = CallBackRef;
+}
+
+/*****************************************************************************/
+/**
+*
+* This is a stub for the status callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+* @param	StatusEvent is the event that just occurred.
+* @param	ByteCount is the number of bytes transferred up until the event
+*		occurred.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubStatusHandler(void *CallBackRef, u32 StatusEvent,
+				u32 ByteCount)
+{
+	(void *) CallBackRef;
+	(void) StatusEvent;
+	(void) ByteCount;
+
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects SPI mode - x1 or x2 or x4.
+*
+* @param	SpiMode - spi or dual or quad.
+* @return	Mask to set desired SPI mode in GENFIFO entry.
+*
+* @note		None.
+*
+******************************************************************************/
+static inline u32 XQspiPsu_SelectSpiMode(u8 SpiMode)
+{
+	u32 Mask;
+	switch (SpiMode) {
+		case XQSPIPSU_SELECT_MODE_DUALSPI:
+			Mask = XQSPIPSU_GENFIFO_MODE_DUALSPI;
+			break;
+		case XQSPIPSU_SELECT_MODE_QUADSPI:
+			Mask = XQSPIPSU_GENFIFO_MODE_QUADSPI;
+			break;
+		case XQSPIPSU_SELECT_MODE_SPI:
+			Mask = XQSPIPSU_GENFIFO_MODE_SPI;
+			break;
+		default:
+			Mask = XQSPIPSU_GENFIFO_MODE_SPI;
+			break;
+	}
+
+	return Mask;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function checks the TX/RX buffers in the message and setups up the
+* GENFIFO entries, TX FIFO or RX DMA as required.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	GenFifoEntry is pointer to the variable in which GENFIFO mask
+*		is returned to calling function
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_TXRXSetup(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+					u32 *GenFifoEntry)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Transmit */
+	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
+			((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) == FALSE)) {
+		/* Setup data to be TXed */
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_TX;
+		InstancePtr->TxBytes = (s32)Msg->ByteCount;
+		InstancePtr->SendBufferPtr = Msg->TxBfrPtr;
+		InstancePtr->RecvBufferPtr = NULL;
+		XQspiPsu_FillTxFifo(InstancePtr, Msg, XQSPIPSU_TXD_DEPTH);
+		/* Discard RX data */
+		*GenFifoEntry &= ~XQSPIPSU_GENFIFO_RX;
+		InstancePtr->RxBytes = 0;
+	}
+
+	/* Receive */
+	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE) &&
+			((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) == FALSE)) {
+		/* TX auto fill */
+		*GenFifoEntry &= ~XQSPIPSU_GENFIFO_TX;
+		InstancePtr->TxBytes = 0;
+		/* Setup RX */
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_RX;
+		InstancePtr->RxBytes = (s32)Msg->ByteCount;
+		InstancePtr->SendBufferPtr = NULL;
+		InstancePtr->RecvBufferPtr = Msg->RxBfrPtr;
+		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+			XQspiPsu_SetupRxDma(InstancePtr, Msg);
+		}
+	}
+
+	/* If only dummy is requested as a separate entry */
+	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) == FALSE) &&
+			(Msg->Flags & XQSPIPSU_MSG_FLAG_RX) == FALSE) {
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
+		InstancePtr->TxBytes = 0;
+		InstancePtr->RxBytes = 0;
+		InstancePtr->SendBufferPtr = NULL;
+		InstancePtr->RecvBufferPtr = NULL;
+	}
+
+	/* Dummy and cmd sent by upper layer to received data */
+	if (((Msg->Flags & XQSPIPSU_MSG_FLAG_TX) != FALSE) &&
+			((Msg->Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+		*GenFifoEntry |= XQSPIPSU_GENFIFO_DATA_XFER;
+		*GenFifoEntry |= (XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX);
+		InstancePtr->TxBytes = (s32)Msg->ByteCount;
+		InstancePtr->RxBytes = (s32)Msg->ByteCount;
+		InstancePtr->SendBufferPtr = Msg->TxBfrPtr;
+		InstancePtr->RecvBufferPtr = Msg->RxBfrPtr;
+		XQspiPsu_FillTxFifo(InstancePtr, Msg, XQSPIPSU_TXD_DEPTH);
+		/* Add check for DMA or PIO here */
+		if (InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA) {
+			XQspiPsu_SetupRxDma(InstancePtr, Msg);
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Fills the TX FIFO as long as there is room in the FIFO or the bytes required
+* to be transmitted.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	Size is the number of bytes to be transmitted.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_FillTxFifo(XQspiPsu *InstancePtr,
+					XQspiPsu_Msg *Msg, s32 Size)
+{
+	s32 Count = 0;
+	u32 Data;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	while ((InstancePtr->TxBytes > 0) && (Count < Size)) {
+		if (InstancePtr->TxBytes >= 4) {
+			(void)memcpy(&Data, Msg->TxBfrPtr, 4);
+			Msg->TxBfrPtr += 4;
+			InstancePtr->TxBytes -= 4;
+			Count += 4;
+		} else {
+			(void)memcpy(&Data, Msg->TxBfrPtr, InstancePtr->TxBytes);
+			Msg->TxBfrPtr += InstancePtr->TxBytes;
+			Count += InstancePtr->TxBytes;
+			InstancePtr->TxBytes = 0;
+		}
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_TXD_OFFSET, Data);
+
+	}
+	if (InstancePtr->TxBytes < 0) {
+		InstancePtr->TxBytes = 0;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets up the RX DMA operation.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_SetupRxDma(XQspiPsu *InstancePtr,
+					XQspiPsu_Msg *Msg)
+{
+	s32 Remainder;
+	s32 DmaRxBytes;
+	u64 AddrTemp;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	AddrTemp = (u64)((INTPTR)(Msg->RxBfrPtr) &
+				XQSPIPSU_QSPIDMA_DST_ADDR_MASK);
+	/* Check for RXBfrPtr to be word aligned */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET,
+			(u32)AddrTemp);
+
+	AddrTemp = AddrTemp >> 32;
+	if ((AddrTemp & 0xFFFU) != FALSE) {
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET,
+				(u32)AddrTemp &
+				XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK);
+	}
+
+	Remainder = InstancePtr->RxBytes % 4;
+	DmaRxBytes = InstancePtr->RxBytes;
+	if (Remainder != 0) {
+		/* This is done to make Dma bytes aligned */
+		DmaRxBytes = InstancePtr->RxBytes - Remainder;
+		Msg->ByteCount = (u32)DmaRxBytes;
+	}
+
+	Xil_DCacheInvalidateRange((INTPTR)InstancePtr->RecvBufferPtr, Msg->ByteCount);
+
+	/* Write no. of words to DMA DST SIZE */
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+			XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET, (u32)DmaRxBytes);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function writes the GENFIFO entry to assert CS.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_GenFifoEntryCSAssert(XQspiPsu *InstancePtr)
+{
+	u32 GenFifoEntry;
+
+	GenFifoEntry = 0x0U;
+	GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
+	GenFifoEntry |= XQSPIPSU_GENFIFO_MODE_SPI;
+	GenFifoEntry |= InstancePtr->GenFifoCS;
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
+	GenFifoEntry |= InstancePtr->GenFifoBus;
+	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
+			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
+	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_SETUP;
+
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function writes the GENFIFO entries to transmit the messages requested.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	Index of the current message to be handled.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if transfer fails.
+*		- XST_DEVICE_BUSY if a transfer is already in progress.
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_GenFifoEntryData(XQspiPsu *InstancePtr,
+						XQspiPsu_Msg *Msg, s32 Index)
+{
+	u32 GenFifoEntry;
+	u32 BaseAddress;
+	u32 TempCount;
+	u32 ImmData;
+
+	BaseAddress = InstancePtr->Config.BaseAddress;
+
+	GenFifoEntry = 0x0U;
+	/* Bus width */
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
+	GenFifoEntry |= XQspiPsu_SelectSpiMode((u8)Msg[Index].BusWidth);
+
+	GenFifoEntry |= InstancePtr->GenFifoCS;
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
+	GenFifoEntry |= InstancePtr->GenFifoBus;
+
+	/* Data */
+	if (((Msg[Index].Flags) & XQSPIPSU_MSG_FLAG_STRIPE) != FALSE) {
+		GenFifoEntry |= XQSPIPSU_GENFIFO_STRIPE;
+	} else {
+		GenFifoEntry &= ~XQSPIPSU_GENFIFO_STRIPE;
+	}
+
+	/* If Byte Count is less than 8 bytes do the transfer in IO mode */
+	if ((Msg[Index].ByteCount < 8U) &&
+		(InstancePtr->ReadMode == XQSPIPSU_READMODE_DMA)) {
+			InstancePtr->ReadMode = XQSPIPSU_READMODE_IO;
+			XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_CFG_OFFSET,
+				(XQspiPsu_ReadReg(BaseAddress, XQSPIPSU_CFG_OFFSET) &
+						~XQSPIPSU_CFG_MODE_EN_MASK));
+			InstancePtr->IsUnaligned = 1;
+	}
+
+	XQspiPsu_TXRXSetup(InstancePtr, &Msg[Index], &GenFifoEntry);
+
+	if (Msg[Index].ByteCount < XQSPIPSU_GENFIFO_IMM_DATA_MASK) {
+		GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
+		GenFifoEntry |= Msg[Index].ByteCount;
+		XQspiPsu_WriteReg(BaseAddress, XQSPIPSU_GEN_FIFO_OFFSET,
+				GenFifoEntry);
+	} else {
+		TempCount = Msg[Index].ByteCount;
+		u32 Exponent = 8;	/* 2^8 = 256 */
+
+		ImmData = TempCount & 0xFFU;
+		/* Exponent entries */
+		GenFifoEntry |= XQSPIPSU_GENFIFO_EXP;
+		while (TempCount != 0U) {
+			if ((TempCount & XQSPIPSU_GENFIFO_EXP_START) != FALSE) {
+				GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
+				GenFifoEntry |= Exponent;
+				XQspiPsu_WriteReg(BaseAddress,
+					XQSPIPSU_GEN_FIFO_OFFSET,
+					GenFifoEntry);
+			}
+			TempCount = TempCount >> 1;
+			Exponent++;
+		}
+
+		/* Immediate entry */
+		GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_EXP);
+		if ((ImmData & 0xFFU) != FALSE) {
+			GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_IMM_DATA_MASK);
+			GenFifoEntry |= ImmData & 0xFFU;
+			XQspiPsu_WriteReg(BaseAddress,
+				XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+		}
+	}
+
+	/* One dummy GenFifo entry in case of IO mode */
+	if ((InstancePtr->ReadMode == XQSPIPSU_READMODE_IO) &&
+			((Msg[Index].Flags & XQSPIPSU_MSG_FLAG_RX) != FALSE)) {
+		GenFifoEntry = 0x0U;
+		XQspiPsu_WriteReg(BaseAddress,
+				XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function writes the GENFIFO entry to de-assert CS.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_GenFifoEntryCSDeAssert(XQspiPsu *InstancePtr)
+{
+	u32 GenFifoEntry;
+
+	GenFifoEntry = 0x0U;
+	GenFifoEntry &= ~((u32)XQSPIPSU_GENFIFO_DATA_XFER | (u32)XQSPIPSU_GENFIFO_EXP);
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_MODE_MASK);
+	GenFifoEntry |= XQSPIPSU_GENFIFO_MODE_SPI;
+	GenFifoEntry &= (u32)(~XQSPIPSU_GENFIFO_BUS_MASK);
+	GenFifoEntry |= InstancePtr->GenFifoBus;
+	GenFifoEntry &= ~(XQSPIPSU_GENFIFO_TX | XQSPIPSU_GENFIFO_RX |
+			XQSPIPSU_GENFIFO_STRIPE | XQSPIPSU_GENFIFO_POLL);
+	GenFifoEntry |= XQSPIPSU_GENFIFO_CS_HOLD;
+
+	XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+		XQSPIPSU_GEN_FIFO_OFFSET, GenFifoEntry);
+}
+
+/*****************************************************************************/
+/**
+*
+* Read the specified number of bytes from RX FIFO
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Msg is a pointer to the structure containing transfer data.
+* @param	Size is the number of bytes to be read.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static inline void XQspiPsu_ReadRxFifo(XQspiPsu *InstancePtr,
+					XQspiPsu_Msg *Msg, s32 Size)
+{
+	s32 Count = 0;
+	u32 Data;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Msg != NULL);
+
+	while ((InstancePtr->RxBytes != 0) && (Count < Size)) {
+		Data = XQspiPsu_ReadReg(InstancePtr->
+				Config.BaseAddress, XQSPIPSU_RXD_OFFSET);
+		if (InstancePtr->RxBytes >= 4) {
+			(void)memcpy(Msg->RxBfrPtr, &Data, 4);
+			InstancePtr->RxBytes -= 4;
+			Msg->RxBfrPtr += 4;
+			Count += 4;
+		} else {
+			/* Read unaligned bytes (< 4 bytes) */
+			(void)memcpy(Msg->RxBfrPtr, &Data, InstancePtr->RxBytes);
+			Msg->RxBfrPtr += InstancePtr->RxBytes;
+			Count += InstancePtr->RxBytes;
+			InstancePtr->RxBytes = 0;
+		}
+	}
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.h
new file mode 100644
index 000000000..d34438df6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu.h
@@ -0,0 +1,272 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu.h
+* @addtogroup qspipsu_v1_0
+* @{
+* @details
+*
+* This is the header file for the implementation of QSPIPSU driver.
+* Generic QSPI interface allows for communication to any QSPI slave device.
+* GQSPI contains a GENFIFO into which the bus transfers required are to be
+* pushed with appropriate configuration. The controller provides TX and RX
+* FIFO's and a DMA to be used for RX transfers. The controller executes each
+* GENFIFO entry noting the configuration and places data on the bus as required
+*
+* The different options in GENFIFO are as follows:
+* IMM_DATA : Can be one byte of data to be transmitted, number of clocks or
+*            number of bytes in transfer.
+* DATA_XFER : Indicates that data/clocks need to be transmitted or received.
+* EXPONENT : e when 2^e bytes are involved in transfer.
+* SPI_MODE : SPI/Dual SPI/Quad SPI
+* CS : Lower or Upper CS or Both
+* Bus : Lower or Upper Bus or Both
+* TX : When selected, controller transmits data in IMM or fetches number of
+*      bytes mentioned form TX FIFO. If not selected, dummies are pumped.
+* RX : When selected, controller receives and fills the RX FIFO/allows RX DMA
+*      of requested number of bytes. If not selected, RX data is discarded.
+* Stripe : Byte stripe over lower and upper bus or not.
+* Poll : Polls response to match for to a set value (used along with POLL_CFG
+*        registers) and then proceeds to next GENFIFO entry.
+*        This feature is not currently used in the driver.
+*
+* GENFIFO has manual and auto start options.
+* All DMA requests need a 4-byte aligned destination address buffer and
+* size of transfer should also be a multiple of 4.
+* This driver supports DMA RX and IO RX.
+*
+* Initialization:
+* This driver uses the GQSPI controller with RX DMA. It supports both
+* interrupt and polled transfers. Manual start of GENFIFO is used.
+* XQspiPsu_CfgInitialize() initializes the instance variables.
+* Additional setting can be done using SetOptions/ClearOptions functions
+* and SelectSlave function.
+*
+* Transfer:
+* Polled or Interrupt transfers can be done. The transfer function needs the
+* message(s) to be transmitted in the form of an array of type XQspiPsu_Msg.
+* This is supposed to contain the byte count and any TX/RX buffers as required.
+* Flags can be used indicate further information such as whether the message
+* should be striped. The transfer functions form and write GENFIFO entries,
+* check the status of the transfer and report back to the application
+* when done.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   hk  08/21/14 First release
+*       sk  03/13/15 Added IO mode support.
+*       hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
+*                    Clear and disbale DMA interrupts/status in abort.
+*                    Use DMA DONE bit instead of BUSY as recommended.
+*       sk  04/24/15 Modified the code according to MISRAC-2012.
+*       sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
+*                    writing/reading from 0x0 location is permitted.
+*
+* 

+*
+******************************************************************************/
+#ifndef XQSPIPSU_H_		/* prevent circular inclusions */
+#define XQSPIPSU_H_		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspipsu_hw.h"
+#include "xil_cache.h"
+
+/**************************** Type Definitions *******************************/
+/**
+ * The handler data type allows the user to define a callback function to
+ * handle the asynchronous processing for the QSPIPSU device.  The application
+ * using this driver is expected to define a handler of this type to support
+ * interrupt driven mode.  The handler executes in an interrupt context, so
+ * only minimal processing should be performed.
+ *
+ * @param	CallBackRef is the callback reference passed in by the upper
+ *		layer when setting the callback functions, and passed back to
+ *		the upper layer when the callback is invoked. Its type is
+ *		not important to the driver, so it is a void pointer.
+ * @param 	StatusEvent holds one or more status events that have occurred.
+ *		See the XQspiPsu_SetStatusHandler() for details on the status
+ *		events that can be passed in the callback.
+ * @param	ByteCount indicates how many bytes of data were successfully
+ *		transferred.  This may be less than the number of bytes
+ *		requested if the status event indicates an error.
+ */
+typedef void (*XQspiPsu_StatusHandler) (void *CallBackRef, u32 StatusEvent,
+					u32 ByteCount);
+
+/**
+ * This typedef contains configuration information for a flash message.
+ */
+typedef struct {
+	u8 *TxBfrPtr;
+	u8 *RxBfrPtr;
+	u32 ByteCount;
+	u32 BusWidth;
+	u32 Flags;
+} XQspiPsu_Msg;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 BaseAddress;	/**< Base address of the device */
+	u32 InputClockHz;	/**< Input clock frequency */
+	u8  ConnectionMode; /**< Single, Stacked and Parallel mode */
+	u8  BusWidth; 	/**< Bus width available on board */
+} XQspiPsu_Config;
+
+/**
+ * The XQspiPsu driver instance data. The user is required to allocate a
+ * variable of this type for every QSPIPSU device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XQspiPsu_Config Config;	 /**< Configuration structure */
+	u32 IsReady;		 /**< Device is initialized and ready */
+
+	u8 *SendBufferPtr;	 /**< Buffer to send (state) */
+	u8 *RecvBufferPtr;	 /**< Buffer to receive (state) */
+	u8 *GenFifoBufferPtr;	 /**< Gen FIFO entries */
+	s32 TxBytes;	 /**< Number of bytes to transfer (state) */
+	s32 RxBytes;	 /**< Number of bytes left to transfer(state) */
+	s32 GenFifoEntries;	 /**< Number of Gen FIFO entries remaining */
+	u32 IsBusy;		 /**< A transfer is in progress (state) */
+	u32 ReadMode;		 /**< DMA or IO mode */
+	u32 GenFifoCS;
+	u32 GenFifoBus;
+	s32 NumMsg;
+	s32 MsgCnt;
+	s32 IsUnaligned;
+	u8 IsManualstart;
+	XQspiPsu_Msg *Msg;
+	XQspiPsu_StatusHandler StatusHandler;
+	void *StatusRef;  	 /**< Callback reference for status handler */
+} XQspiPsu;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQSPIPSU_READMODE_DMA	0x0U
+#define XQSPIPSU_READMODE_IO	0x1U
+
+#define XQSPIPSU_SELECT_FLASH_CS_LOWER	0x1U
+#define XQSPIPSU_SELECT_FLASH_CS_UPPER	0x2U
+#define XQSPIPSU_SELECT_FLASH_CS_BOTH	0x3U
+
+#define XQSPIPSU_SELECT_FLASH_BUS_LOWER	0x1U
+#define XQSPIPSU_SELECT_FLASH_BUS_UPPER	0x2U
+#define XQSPIPSU_SELECT_FLASH_BUS_BOTH	0x3U
+
+#define XQSPIPSU_SELECT_MODE_SPI	0x1U
+#define XQSPIPSU_SELECT_MODE_DUALSPI	0x2U
+#define XQSPIPSU_SELECT_MODE_QUADSPI	0x4U
+
+#define XQSPIPSU_GENFIFO_CS_SETUP	0x05U
+#define XQSPIPSU_GENFIFO_CS_HOLD	0x04U
+
+#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION	0x2U
+#define XQSPIPSU_CLK_PHASE_1_OPTION	0x4U
+#define XQSPIPSU_MANUAL_START_OPTION	0x8U
+
+#define XQSPIPSU_GENFIFO_EXP_START	0x100U
+
+#define XQSPIPSU_DMA_BYTES_MAX		0x10000000U
+
+#define XQSPIPSU_CLK_PRESCALE_2		0x00U
+#define XQSPIPSU_CLK_PRESCALE_4		0x01U
+#define XQSPIPSU_CLK_PRESCALE_8		0x02U
+#define XQSPIPSU_CLK_PRESCALE_16		0x03U
+#define XQSPIPSU_CLK_PRESCALE_32		0x04U
+#define XQSPIPSU_CLK_PRESCALE_64		0x05U
+#define XQSPIPSU_CLK_PRESCALE_128	0x06U
+#define XQSPIPSU_CLK_PRESCALE_256	0x07U
+#define XQSPIPSU_CR_PRESC_MAXIMUM	7U
+
+#define XQSPIPSU_CONNECTION_MODE_SINGLE		0U
+#define XQSPIPSU_CONNECTION_MODE_STACKED	1U
+#define XQSPIPSU_CONNECTION_MODE_PARALLEL	2U
+
+/* Add more flags as required */
+#define XQSPIPSU_MSG_FLAG_STRIPE	0x1U
+#define XQSPIPSU_MSG_FLAG_RX		0x2U
+#define XQSPIPSU_MSG_FLAG_TX		0x4U
+
+#define XQspiPsu_Select(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_SEL_OFFSET, XQSPIPSU_SEL_MASK)
+
+#define XQspiPsu_Enable(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)
+
+#define XQspiPsu_Disable(InstancePtr)	XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + XQSPIPSU_EN_OFFSET, 0x0U)
+
+/************************** Function Prototypes ******************************/
+
+/* Initialization and reset */
+XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId);
+s32 XQspiPsu_CfgInitialize(XQspiPsu *InstancePtr, XQspiPsu_Config *ConfigPtr,
+				u32 EffectiveAddr);
+void XQspiPsu_Reset(XQspiPsu *InstancePtr);
+void XQspiPsu_Abort(XQspiPsu *InstancePtr);
+
+/* Transfer functions and handlers */
+s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				u32 NumMsg);
+s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
+				u32 NumMsg);
+s32 XQspiPsu_InterruptHandler(XQspiPsu *InstancePtr);
+void XQspiPsu_SetStatusHandler(XQspiPsu *InstancePtr, void *CallBackRef,
+				XQspiPsu_StatusHandler FuncPointer);
+
+/* Configuration functions */
+s32 XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler);
+void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus);
+s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options);
+s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options);
+u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr);
+s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* XQSPIPSU_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
new file mode 100644
index 000000000..daa5bde27
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_g.c
@@ -0,0 +1,58 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xqspipsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XQspiPsu_Config XQspiPsu_ConfigTable[] =
+{
+	{
+		XPAR_PSU_QSPI_0_DEVICE_ID,
+		XPAR_PSU_QSPI_0_BASEADDR,
+		XPAR_PSU_QSPI_0_QSPI_CLK_FREQ_HZ,
+		XPAR_PSU_QSPI_0_QSPI_MODE,
+		XPAR_PSU_QSPI_0_QSPI_BUS_WIDTH
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h
new file mode 100644
index 000000000..508109019
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_hw.h
@@ -0,0 +1,841 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu_hw.h
+* @addtogroup qspipsu_v1_0
+* @{
+*
+* This file contains low level access funcitons using the base address
+* directly without an instance.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------.
+* 1.0   hk  08/21/14 First release
+*       hk  03/18/15 Add DMA status register masks required.
+*       sk  04/24/15 Modified the code according to MISRAC-2012.
+*
+* 

+*
+******************************************************************************/
+#ifndef _XQSPIPSU_HW_H_		/* prevent circular inclusions */
+#define _XQSPIPSU_HW_H_		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * QSPI Base Address
+ */
+#define XQSPIPS_BASEADDR      0XFF0F0000U
+
+/**
+ * GQSPI Base Address
+ */
+#define XQSPIPSU_BASEADDR     0xFF0F0100U
+#define XQSPIPSU_OFFSET     0x100U
+
+/**
+ * Register: XQSPIPS_EN_REG
+ */
+#define XQSPIPS_EN_REG    ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
+
+#define XQSPIPS_EN_SHIFT   0
+#define XQSPIPS_EN_WIDTH   1
+#define XQSPIPS_EN_MASK    0X00000001U
+
+/**
+ * Register: XQSPIPSU_CFG
+ */
+#define XQSPIPSU_CFG_OFFSET    0X00000000U
+
+#define XQSPIPSU_CFG_MODE_EN_SHIFT   30
+#define XQSPIPSU_CFG_MODE_EN_WIDTH   2
+#define XQSPIPSU_CFG_MODE_EN_MASK    0XC0000000U
+#define XQSPIPSU_CFG_MODE_EN_DMA_MASK	0X80000000U
+
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT   29
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH   1
+#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK    0X20000000U
+
+#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT   28
+#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH   1
+#define XQSPIPSU_CFG_START_GEN_FIFO_MASK    0X10000000U
+
+#define XQSPIPSU_CFG_ENDIAN_SHIFT   26
+#define XQSPIPSU_CFG_ENDIAN_WIDTH   1
+#define XQSPIPSU_CFG_ENDIAN_MASK    0X04000000U
+
+#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT   20
+#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH   1
+#define XQSPIPSU_CFG_EN_POLL_TO_MASK    0X00100000U
+
+#define XQSPIPSU_CFG_WP_HOLD_SHIFT   19
+#define XQSPIPSU_CFG_WP_HOLD_WIDTH   1
+#define XQSPIPSU_CFG_WP_HOLD_MASK    0X00080000U
+
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT   3
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH   3
+#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK    0X00000038U
+
+#define XQSPIPSU_CFG_CLK_PHA_SHIFT   2
+#define XQSPIPSU_CFG_CLK_PHA_WIDTH   1
+#define XQSPIPSU_CFG_CLK_PHA_MASK    0X00000004U
+
+#define XQSPIPSU_CFG_CLK_POL_SHIFT   1
+#define XQSPIPSU_CFG_CLK_POL_WIDTH   1
+#define XQSPIPSU_CFG_CLK_POL_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_ISR
+ */
+#define XQSPIPSU_ISR_OFFSET	0X00000004U
+
+#define XQSPIPSU_ISR_RXEMPTY_SHIFT   11
+#define XQSPIPSU_ISR_RXEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_ISR_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_ISR_TXEMPTY_SHIFT   8
+#define XQSPIPSU_ISR_TXEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_ISR_RXFULL_SHIFT   5
+#define XQSPIPSU_ISR_RXFULL_WIDTH   1
+#define XQSPIPSU_ISR_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_ISR_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_ISR_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_ISR_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_ISR_TXFULL_SHIFT   3
+#define XQSPIPSU_ISR_TXFULL_WIDTH   1
+#define XQSPIPSU_ISR_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_ISR_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK    0X00000002U
+
+#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U
+
+/**
+ * Register: XQSPIPSU_IER
+ */
+#define XQSPIPSU_IER_OFFSET    0X00000008U
+
+#define XQSPIPSU_IER_RXEMPTY_SHIFT   11
+#define XQSPIPSU_IER_RXEMPTY_WIDTH   1
+#define XQSPIPSU_IER_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_IER_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_IER_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_IER_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_IER_TXEMPTY_SHIFT   8
+#define XQSPIPSU_IER_TXEMPTY_WIDTH   1
+#define XQSPIPSU_IER_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_IER_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_IER_RXFULL_SHIFT   5
+#define XQSPIPSU_IER_RXFULL_WIDTH   1
+#define XQSPIPSU_IER_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_IER_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_IER_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_IER_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_IER_TXFULL_SHIFT   3
+#define XQSPIPSU_IER_TXFULL_WIDTH   1
+#define XQSPIPSU_IER_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_IER_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_IER_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_IER_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_IDR
+ */
+#define XQSPIPSU_IDR_OFFSET    0X0000000CU
+
+#define XQSPIPSU_IDR_RXEMPTY_SHIFT   11
+#define XQSPIPSU_IDR_RXEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_IDR_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_IDR_TXEMPTY_SHIFT   8
+#define XQSPIPSU_IDR_TXEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_IDR_RXFULL_SHIFT   5
+#define XQSPIPSU_IDR_RXFULL_WIDTH   1
+#define XQSPIPSU_IDR_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_IDR_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_IDR_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_IDR_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_IDR_TXFULL_SHIFT   3
+#define XQSPIPSU_IDR_TXFULL_WIDTH   1
+#define XQSPIPSU_IDR_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_IDR_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK    0X00000002U
+
+#define XQSPIPSU_IDR_ALL_MASK    0X0FBEU
+
+/**
+ * Register: XQSPIPSU_IMR
+ */
+#define XQSPIPSU_IMR_OFFSET    0X00000010U
+
+#define XQSPIPSU_IMR_RXEMPTY_SHIFT   11
+#define XQSPIPSU_IMR_RXEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_RXEMPTY_MASK    0X00000800U
+
+#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT   10
+#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH   1
+#define XQSPIPSU_IMR_GENFIFOFULL_MASK    0X00000400U
+
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT   9
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH   1
+#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK    0X00000200U
+
+#define XQSPIPSU_IMR_TXEMPTY_SHIFT   8
+#define XQSPIPSU_IMR_TXEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_TXEMPTY_MASK    0X00000100U
+
+#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT   7
+#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK    0X00000080U
+
+#define XQSPIPSU_IMR_RXFULL_SHIFT   5
+#define XQSPIPSU_IMR_RXFULL_WIDTH   1
+#define XQSPIPSU_IMR_RXFULL_MASK    0X00000020U
+
+#define XQSPIPSU_IMR_RXNEMPTY_SHIFT   4
+#define XQSPIPSU_IMR_RXNEMPTY_WIDTH   1
+#define XQSPIPSU_IMR_RXNEMPTY_MASK    0X00000010U
+
+#define XQSPIPSU_IMR_TXFULL_SHIFT   3
+#define XQSPIPSU_IMR_TXFULL_WIDTH   1
+#define XQSPIPSU_IMR_TXFULL_MASK    0X00000008U
+
+#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT   2
+#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH   1
+#define XQSPIPSU_IMR_TXNOT_FULL_MASK    0X00000004U
+
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT   1
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH   1
+#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_EN_REG
+ */
+#define XQSPIPSU_EN_OFFSET    0X00000014U
+
+#define XQSPIPSU_EN_SHIFT   0
+#define XQSPIPSU_EN_WIDTH   1
+#define XQSPIPSU_EN_MASK    0X00000001U
+
+/**
+ * Register: XQSPIPSU_TXD
+ */
+#define XQSPIPSU_TXD_OFFSET    0X0000001CU
+
+#define XQSPIPSU_TXD_SHIFT   0
+#define XQSPIPSU_TXD_WIDTH   32
+#define XQSPIPSU_TXD_MASK    0XFFFFFFFFU
+
+#define XQSPIPSU_TXD_DEPTH    64
+
+/**
+ * Register: XQSPIPSU_RXD
+ */
+#define XQSPIPSU_RXD_OFFSET    0X00000020U
+
+#define XQSPIPSU_RXD_SHIFT   0
+#define XQSPIPSU_RXD_WIDTH   32
+#define XQSPIPSU_RXD_MASK    0XFFFFFFFFU
+
+/**
+ * Register: XQSPIPSU_TX_THRESHOLD
+ */
+#define XQSPIPSU_TX_THRESHOLD_OFFSET    0X00000028U
+
+#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT   0
+#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH   6
+#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK    0X0000003FU
+#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL    0X01U
+
+/**
+ * Register: XQSPIPSU_RX_THRESHOLD
+ */
+#define XQSPIPSU_RX_THRESHOLD_OFFSET    0X0000002CU
+
+#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT   0
+#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH   6
+#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK    0X0000003FU
+#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL    0X01U
+
+#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U
+
+/**
+ * Register: XQSPIPSU_GPIO
+ */
+#define XQSPIPSU_GPIO_OFFSET    0X00000030U
+
+#define XQSPIPSU_GPIO_WP_N_SHIFT   0
+#define XQSPIPSU_GPIO_WP_N_WIDTH   1
+#define XQSPIPSU_GPIO_WP_N_MASK    0X00000001U
+
+/**
+ * Register: XQSPIPSU_LPBK_DLY_ADJ
+ */
+#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET    0X00000038U
+
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT   5
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH   1
+#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK    0X00000020U
+
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT   3
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH   2
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK    0X00000018U
+
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT   0
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH   3
+#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK    0X00000007U
+
+/**
+ * Register: XQSPIPSU_GEN_FIFO
+ */
+#define XQSPIPSU_GEN_FIFO_OFFSET    0X00000040U
+
+#define XQSPIPSU_GEN_FIFO_DATA_SHIFT   0
+#define XQSPIPSU_GEN_FIFO_DATA_WIDTH   20
+#define XQSPIPSU_GEN_FIFO_DATA_MASK    0X000FFFFFU
+
+/**
+ * Register: XQSPIPSU_SEL
+ */
+#define XQSPIPSU_SEL_OFFSET    0X00000044U
+
+#define XQSPIPSU_SEL_SHIFT   0
+#define XQSPIPSU_SEL_WIDTH   1
+#define XQSPIPSU_SEL_MASK    0X00000001U
+
+/**
+ * Register: XQSPIPSU_FIFO_CTRL
+ */
+#define XQSPIPSU_FIFO_CTRL_OFFSET    0X0000004CU
+
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT   2
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH   1
+#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK    0X00000004U
+
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT   1
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH   1
+#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK    0X00000002U
+
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT   0
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH   1
+#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK    0X00000001U
+
+/**
+ * Register: XQSPIPSU_GF_THRESHOLD
+ */
+#define XQSPIPSU_GF_THRESHOLD_OFFSET    0X00000050U
+
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT   0
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH   5
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK    0X0000001F
+#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL    0X10U
+
+/**
+ * Register: XQSPIPSU_POLL_CFG
+ */
+#define XQSPIPSU_POLL_CFG_OFFSET    0X00000054U
+
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT   31
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH   1
+#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK    0X80000000U
+
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT   30
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH   1
+#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK    0X40000000U
+
+#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT   8
+#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH   8
+#define XQSPIPSU_POLL_CFG_MASK_EN_MASK    0X0000FF00U
+
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT   0
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH   8
+#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK    0X000000FFU
+
+/**
+ * Register: XQSPIPSU_P_TIMEOUT
+ */
+#define XQSPIPSU_P_TO_OFFSET    0X00000058U
+
+#define XQSPIPSU_P_TO_VALUE_SHIFT   0
+#define XQSPIPSU_P_TO_VALUE_WIDTH   32
+#define XQSPIPSU_P_TO_VALUE_MASK    0XFFFFFFFFU
+
+/**
+ * Register: XQSPIPSU_XFER_STS
+ */
+#define XQSPIPSU_XFER_STS_OFFSET	0X0000005CU
+
+#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT   0
+#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH   32
+#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK    0XFFFFFFFFU
+
+/**
+ * Register: XQSPIPSU_GF_SNAPSHOT
+ */
+#define XQSPIPSU_GF_SNAPSHOT_OFFSET    0X00000060U
+
+#define XQSPIPSU_GF_SNAPSHOT_SHIFT   0
+#define XQSPIPSU_GF_SNAPSHOT_WIDTH   20
+#define XQSPIPSU_GF_SNAPSHOT_MASK    0X000FFFFFU
+
+/**
+ * Register: XQSPIPSU_RX_COPY
+ */
+#define XQSPIPSU_RX_COPY_OFFSET    0X00000064U
+
+#define XQSPIPSU_RX_COPY_UPPER_SHIFT   8
+#define XQSPIPSU_RX_COPY_UPPER_WIDTH   8
+#define XQSPIPSU_RX_COPY_UPPER_MASK    0X0000FF00U
+
+#define XQSPIPSU_RX_COPY_LOWER_SHIFT   0
+#define XQSPIPSU_RX_COPY_LOWER_WIDTH   8
+#define XQSPIPSU_RX_COPY_LOWER_MASK    0X000000FFU
+
+/**
+ * Register: XQSPIPSU_MOD_ID
+ */
+#define XQSPIPSU_MOD_ID_OFFSET    0X000000FCU
+
+#define XQSPIPSU_MOD_ID_SHIFT   0
+#define XQSPIPSU_MOD_ID_WIDTH   32
+#define XQSPIPSU_MOD_ID_MASK    0XFFFFFFFFU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_ADDR
+ */
+#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET    0X00000700U
+
+#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH   30
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK    0XFFFFFFFCU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_SIZE
+ */
+#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET    0X00000704U
+
+#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH   27
+#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK    0X1FFFFFFCU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_STS
+ */
+#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET    0X00000708U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT   13
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK    0X0000E000U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH   8
+#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK    0X00001FE0U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH   4
+#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK    0X0000001EU
+
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK    0X00000001U
+
+#define XQSPIPSU_QSPIDMA_DST_STS_WTC	0xE000U
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_CTRL
+ */
+#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET    0X0000070CU
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT   25
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH   7
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK    0XFE000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT   24
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK    0X01000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT   23
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK    0X00800000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT   22
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK    0X00400000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT   10
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH   12
+#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK    0X003FFC00U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH   8
+#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK    0X000003FCU
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK    0X00000002U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK    0X00000001U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL	0x403FFA00U
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_I_STS
+ */
+#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET    0X00000714U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK    0X00000002U
+
+#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK    0X000000FCU
+#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK    0X000000FEU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_I_EN
+ */
+#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET    0X00000718U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_I_DIS
+ */
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET    0X0000071CU
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_IMR
+ */
+#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET    0X00000720U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT   7
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK    0X00000080U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT   6
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK    0X00000040U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT   5
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK    0X00000020U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK    0X00000010U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT   3
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK    0X00000008U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT   2
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK    0X00000004U
+
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK    0X00000002U
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_CTRL2
+ */
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET    0X00000724U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT   27
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK    0X08000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT   24
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK    0X07000000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT   22
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH   1
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK    0X00400000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT   19
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK    0X00380000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT   16
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH   3
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK    0X00070000U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT   4
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH   12
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK    0X0000FFF0U
+
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH   4
+#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK    0X0000000FU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_DST_ADDR_MSB
+ */
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET    0X00000728U
+
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT   0
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH   12
+#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK    0X00000FFFU
+
+/**
+ * Register: XQSPIPSU_QSPIDMA_FUTURE_ECO
+ */
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET    0X00000EFCU
+
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT   0
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH   32
+#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK    0XFFFFFFFFU
+
+/*
+ * Generic FIFO masks
+ */
+#define XQSPIPSU_GENFIFO_IMM_DATA_MASK	0xFFU
+#define XQSPIPSU_GENFIFO_DATA_XFER	0x100U
+#define XQSPIPSU_GENFIFO_EXP		0x200U
+#define XQSPIPSU_GENFIFO_MODE_SPI	0x400U
+#define XQSPIPSU_GENFIFO_MODE_DUALSPI	0x800U
+#define XQSPIPSU_GENFIFO_MODE_QUADSPI	0xC00U
+#define XQSPIPSU_GENFIFO_MODE_MASK	0xC00U	/* And with ~MASK first */
+#define XQSPIPSU_GENFIFO_CS_LOWER	0x1000U
+#define XQSPIPSU_GENFIFO_CS_UPPER	0x2000U
+#define XQSPIPSU_GENFIFO_BUS_LOWER	0x4000U
+#define XQSPIPSU_GENFIFO_BUS_UPPER	0x8000U
+#define XQSPIPSU_GENFIFO_BUS_BOTH	0xC000U	/* inverse is no bus */
+#define XQSPIPSU_GENFIFO_BUS_MASK	0xC000U	/* And with ~MASK first */
+#define XQSPIPSU_GENFIFO_TX		0x10000U	/* inverse is zero pump */
+#define XQSPIPSU_GENFIFO_RX		0x20000U	/* inverse is RX discard */
+#define XQSPIPSU_GENFIFO_STRIPE		0x40000U
+#define XQSPIPSU_GENFIFO_POLL		0x80000U
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XQspiPsu_In32 Xil_In32
+#define XQspiPsu_Out32 Xil_Out32
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset)
+*
+******************************************************************************/
+#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* _XQSPIPSU_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c
new file mode 100644
index 000000000..97eee8cfd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_options.c
@@ -0,0 +1,449 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu_options.c
+* @addtogroup qspipsu_v1_0
+* @{
+*
+* This file implements funcitons to configure the QSPIPSU component,
+* specifically some optional settings, clock and flash related information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   hk  08/21/14 First release
+*       sk  03/13/15 Added IO mode support.
+*       sk  04/24/15 Modified the code according to MISRAC-2012.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xqspipsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+} OptionsMap;
+
+static OptionsMap OptionsTable[] = {
+	{XQSPIPSU_CLK_ACTIVE_LOW_OPTION, XQSPIPSU_CFG_CLK_POL_MASK},
+	{XQSPIPSU_CLK_PHASE_1_OPTION, XQSPIPSU_CFG_CLK_PHA_MASK},
+	{XQSPIPSU_MANUAL_START_OPTION, XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK},
+};
+
+#define XQSPIPSU_NUM_OPTIONS	(sizeof(OptionsTable) / sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the QSPIPSU device driver.The options
+* control how the device behaves relative to the QSPIPSU bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 indicates the option should be turned ON and
+*		a 0 indicates no action. One or more bit values may be
+*		contained in the mask. See the bit definitions named
+*		XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPsu_SetOptions(XQspiPsu *InstancePtr, u32 Options)
+{
+	u32 ConfigReg;
+	u32 Index;
+	u32 QspiPsuOptions;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					      XQSPIPSU_CFG_OFFSET);
+
+		/*
+		 * Loop through the options table, turning the option on
+		 * depending on whether the bit is set in the incoming options flag.
+		 */
+		for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
+			if ((Options & OptionsTable[Index].Option) != FALSE) {
+				/* Turn it on */
+				ConfigReg |= OptionsTable[Index].Mask;
+			}
+		}
+
+		/*
+		 * Now write the control register. Leave it to the upper layers
+		 * to restart the device.
+		 */
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+				 ConfigReg);
+
+		if ((Options & XQSPIPSU_MANUAL_START_OPTION) != FALSE) {
+			InstancePtr->IsManualstart = TRUE;
+		}
+
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets the options for the QSPIPSU device driver.The options
+* control how the device behaves relative to the QSPIPSU bus. The device must be
+* idle rather than busy transferring data before setting these device options.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 indicates the option should be turned OFF and
+*		a 0 indicates no action. One or more bit values may be
+*		contained in the mask. See the bit definitions named
+*		XQSPIPSU_*_OPTIONS in the file xqspipsu.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting options.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPsu_ClearOptions(XQspiPsu *InstancePtr, u32 Options)
+{
+	u32 ConfigReg;
+	u32 Index;
+	u32 QspiPsuOptions;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					      XQSPIPSU_CFG_OFFSET);
+
+		/*
+		 * Loop through the options table, turning the option on
+		 * depending on whether the bit is set in the incoming options flag.
+		 */
+		for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
+			if ((Options & OptionsTable[Index].Option) != FALSE) {
+				/* Turn it off */
+				ConfigReg &= ~OptionsTable[Index].Mask;
+			}
+		}
+
+		/*
+		 * Now write the control register. Leave it to the upper layers
+		 * to restart the device.
+		 */
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+				 ConfigReg);
+
+		if ((Options & XQSPIPSU_MANUAL_START_OPTION) != FALSE) {
+			InstancePtr->IsManualstart = FALSE;
+		}
+
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the options for the QSPIPSU device. The options control how
+* the device behaves relative to the QSPIPSU bus.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+*
+* @return
+*
+* Options contains the specified options currently set. This is a bit value
+* where a 1 means the option is on, and a 0 means the option is off.
+* See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XQspiPsu_GetOptions(XQspiPsu *InstancePtr)
+{
+	u32 OptionsFlag = 0;
+	u32 ConfigReg;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the current options from QSPIPSU configuration register.
+	 */
+	ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+				      XQSPIPSU_CFG_OFFSET);
+
+	/* Loop through the options table to grab options */
+	for (Index = 0U; Index < XQSPIPSU_NUM_OPTIONS; Index++) {
+		if ((ConfigReg & OptionsTable[Index].Mask) != FALSE) {
+			OptionsFlag |= OptionsTable[Index].Option;
+		}
+	}
+
+	return OptionsFlag;
+}
+
+/*****************************************************************************/
+/**
+*
+* Configures the clock according to the prescaler passed.
+*
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Prescaler - clock prescaler to be set.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XQspiPsu_SetClkPrescaler(XQspiPsu *InstancePtr, u8 Prescaler)
+{
+	u32 ConfigReg;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Prescaler <= XQSPIPSU_CR_PRESC_MAXIMUM);
+
+	/*
+	 * Do not allow the slave select to change while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		/*
+		 * Read the configuration register, mask out the relevant bits, and set
+		 * them with the shifted value passed into the function. Write the
+		 * results back to the configuration register.
+		 */
+		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					      XQSPIPSU_CFG_OFFSET);
+
+		ConfigReg &= (u32)(~XQSPIPSU_CFG_BAUD_RATE_DIV_MASK);
+		ConfigReg |= (u32) ((u32)Prescaler & (u32)XQSPIPSU_CR_PRESC_MAXIMUM) <<
+				    XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT;
+
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress,
+				  XQSPIPSU_CFG_OFFSET, ConfigReg);
+
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This funciton should be used to tell the QSPIPSU driver the HW flash
+* configuration being used. This API should be called atleast once in the
+* application. If desired, it can be called multiple times when switching
+* between communicating to different flahs devices/using different configs.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	FlashCS - Flash Chip Select.
+* @param	FlashBus - Flash Bus (Upper, Lower or Both).
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		If this funciton is not called atleast once in the application,
+*		the driver assumes there is a single flash connected to the
+*		lower bus and CS line.
+*
+******************************************************************************/
+void XQspiPsu_SelectFlash(XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/*
+	 * Bus and CS lines selected here will be updated in the instance and
+	 * used for subsequent GENFIFO entries during transfer.
+	 */
+
+	/* Choose slave select line */
+	switch (FlashCS) {
+		case XQSPIPSU_SELECT_FLASH_CS_BOTH:
+			InstancePtr->GenFifoCS = (u32)XQSPIPSU_GENFIFO_CS_LOWER |
+						(u32)XQSPIPSU_GENFIFO_CS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_CS_UPPER:
+			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_CS_LOWER:
+			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
+			break;
+		default:
+			InstancePtr->GenFifoCS = XQSPIPSU_GENFIFO_CS_LOWER;
+			break;
+	}
+
+	/* Choose bus */
+	switch (FlashBus) {
+		case XQSPIPSU_SELECT_FLASH_BUS_BOTH:
+			InstancePtr->GenFifoBus = (u32)XQSPIPSU_GENFIFO_BUS_LOWER |
+						(u32)XQSPIPSU_GENFIFO_BUS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_BUS_UPPER:
+			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_UPPER;
+			break;
+		case XQSPIPSU_SELECT_FLASH_BUS_LOWER:
+			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
+			break;
+		default:
+			InstancePtr->GenFifoBus = XQSPIPSU_GENFIFO_BUS_LOWER;
+			break;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the Read mode for the QSPIPSU device driver.The device
+* must be idle rather than busy transferring data before setting Read mode
+* options.
+*
+* @param	InstancePtr is a pointer to the XQspiPsu instance.
+* @param	Mode contains the specified Mode to be set. See the
+* 		bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_DEVICE_BUSY if the device is currently transferring data.
+*		The transfer must complete or be aborted before setting Mode.
+*
+* @note
+* This function is not thread-safe.
+*
+******************************************************************************/
+s32 XQspiPsu_SetReadMode(XQspiPsu *InstancePtr, u32 Mode)
+{
+	u32 ConfigReg;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Do not allow to modify the Control Register while a transfer is in
+	 * progress. Not thread-safe.
+	 */
+	if (InstancePtr->IsBusy == TRUE) {
+		Status = (s32)XST_DEVICE_BUSY;
+	} else {
+
+		InstancePtr->ReadMode = Mode;
+
+		ConfigReg = XQspiPsu_ReadReg(InstancePtr->Config.BaseAddress,
+					      XQSPIPSU_CFG_OFFSET);
+
+		if (Mode == XQSPIPSU_READMODE_DMA) {
+			ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+			ConfigReg |= XQSPIPSU_CFG_MODE_EN_DMA_MASK;
+		} else {
+			ConfigReg &= ~XQSPIPSU_CFG_MODE_EN_MASK;
+		}
+
+		XQspiPsu_WriteReg(InstancePtr->Config.BaseAddress, XQSPIPSU_CFG_OFFSET,
+				 ConfigReg);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c
new file mode 100644
index 000000000..63aaed0bb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/qspipsu_v1_0/src/xqspipsu_sinit.c
@@ -0,0 +1,100 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xqspipsu_sinit.c
+* @addtogroup qspipsu_v1_0
+* @{
+*
+* The implementation of the XQspiPsu component's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who Date     Changes
+* ----- --- -------- -----------------------------------------------
+* 1.0   hk  08/21/14 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xqspipsu.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xqspipsu.h for the definition of XQspiPsu_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XQspiPsu_Config *XQspiPsu_LookupConfig(u16 DeviceId)
+{
+	XQspiPsu_Config *CfgPtr = NULL;
+	s32 Index;
+
+	for (Index = 0; Index < XPAR_XQSPIPSU_NUM_INSTANCES; Index++) {
+		if (XQspiPsu_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XQspiPsu_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XQspiPsu_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/Makefile
new file mode 100644
index 000000000..dc8cbdf6b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xrtcpsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling rtcpsu"
+
+xrtcpsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xrtcpsu_includes
+
+xrtcpsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.c
new file mode 100644
index 000000000..58163eb34
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.c
@@ -0,0 +1,422 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xrtcpsu.c
+* @addtogroup rtcpsu_v1_0
+* @{
+*
+* Functions in this file are the minimum required functions for the XRtcPsu
+* driver. See xrtcpsu.h for a detailed description of the driver.
+*
+* @note 	None.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    04/21/15 First release
+* 1.1   kvn    09/25/15 Modify control register to enable battery
+*                       switching when vcc_psaux is not available.
+* 1.2          02/15/16 Corrected Calibration mask and Fractional
+*                       mask in CalculateCalibration API.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xrtcpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+static const u32 DaysInMonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
+
+/************************** Function Prototypes ******************************/
+
+static void XRtcPsu_StubHandler(void *CallBackRef, u32 Event);
+
+/*****************************************************************************/
+/*
+*
+* This function initializes a XRtcPsu instance/driver.
+*
+* The initialization entails:
+* - Initialize all members of the XRtcPsu structure.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	ConfigPtr points to the XRtcPsu device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return	XST_SUCCESS always.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XRtcPsu_CfgInitialize(XRtcPsu *InstancePtr, XRtcPsu_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 ControlRegister;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values for instance data, don't indicate the device
+	 * is ready to use until everything has been initialized successfully.
+	 */
+	InstancePtr->IsReady = 0U;
+	InstancePtr->RtcConfig.BaseAddr = EffectiveAddr;
+	InstancePtr->RtcConfig.DeviceId = ConfigPtr->DeviceId;
+
+	if(InstancePtr->OscillatorFreq == 0U) {
+		InstancePtr->CalibrationValue = XRTC_CALIBRATION_VALUE;
+		InstancePtr->OscillatorFreq = XRTC_TYPICAL_OSC_FREQ;
+	}
+
+	/* Set all handlers to stub values, let user configure this data later. */
+	InstancePtr->Handler = XRtcPsu_StubHandler;
+
+	InstancePtr->IsPeriodicAlarm = 0U;
+
+	/* Set the calibration value in calibration register. */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CALIB_WR_OFFSET,
+				InstancePtr->CalibrationValue);
+
+	/* Set the Oscillator crystal and Battery switch enable in control register. */
+	ControlRegister = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CTL_OFFSET);
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_CTL_OFFSET,
+			(ControlRegister | (u32)XRTCPSU_CRYSTAL_OSC_EN | (u32)XRTC_CTL_BATTERY_EN_MASK));
+
+	/* Clear the Interrupt Status and Disable the interrupts. */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET,
+			((u32)XRTC_INT_STS_ALRM_MASK | (u32)XRTC_INT_STS_SECS_MASK));
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_DIS_OFFSET,
+			((u32)XRTC_INT_DIS_ALRM_MASK | (u32)XRTC_INT_DIS_SECS_MASK));
+
+	/* Indicate the component is now ready to use. */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	Status = XST_SUCCESS;
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param	CallBackRef is unused by this function.
+* @param	Event is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XRtcPsu_StubHandler(void *CallBackRef, u32 Event)
+{
+	(void *) CallBackRef;
+	(void) Event;
+	/* Assert occurs always since this is a stub and should never be called */
+	Xil_AssertVoidAlways();
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the alarm value of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance
+* @param	Alarm is the desired alarm time for RTC.
+* @param	Periodic says whether the alarm need to set at periodic
+* 			Intervals or a one-time alarm.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XRtcPsu_SetAlarm(XRtcPsu *InstancePtr, u32 Alarm, u32 Periodic)
+{
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Alarm != 0U);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Alarm - XRtcPsu_GetCurrentTime(InstancePtr)) > (u32)0);
+
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr+XRTC_ALRM_OFFSET, Alarm);
+	if(Periodic != 0U) {
+		InstancePtr->IsPeriodicAlarm = 1U;
+		InstancePtr->PeriodicAlarmTime =
+				Alarm - XRtcPsu_GetCurrentTime(InstancePtr);
+	}
+}
+
+
+/****************************************************************************/
+/**
+*
+* This function translates time in seconds to a YEAR:MON:DAY HR:MIN:SEC
+* format and saves it in the DT structure variable. It also reports the weekday.
+*
+* @param	Seconds is the time value that has to be shown in DateTime
+* 			format.
+* @param	dt is the DateTime format variable that stores the translated
+* 			time.
+*
+* @return	None.
+*
+* @note		This API supports this century i.e., 2000 - 2099 years only.
+*
+*****************************************************************************/
+void XRtcPsu_SecToDateTime(u32 Seconds, XRtcPsu_DT *dt)
+{
+	u32 CurrentTime, TempDays, Leap, DaysPerMonth;
+
+	CurrentTime = Seconds;
+	dt->Sec = CurrentTime % 60U;
+	CurrentTime /= 60U;
+	dt->Min = CurrentTime % 60U;
+	CurrentTime /= 60U;
+	dt->Hour = CurrentTime % 24U;
+	TempDays = CurrentTime / 24U;
+
+	if (TempDays == 0U) {
+		TempDays = 1U;
+	}
+	dt->WeekDay = TempDays % 7U;
+
+	for (dt->Year = 0U; dt->Year <= 99U; ++(dt->Year)) {
+		if ((dt->Year % 4U) == 0U ) {
+			Leap = 1U;
+		}
+		else {
+			Leap = 0U;
+		}
+		if (TempDays < (365U + Leap)) {
+			break;
+		}
+		TempDays -= (365U + Leap);
+	}
+
+	for (dt->Month = 1U; dt->Month >= 1U; ++(dt->Month)) {
+		DaysPerMonth = DaysInMonth[dt->Month - 1];
+		if ((Leap == 1U) && (dt->Month == 2U)) {
+			DaysPerMonth++;
+		}
+		if (TempDays < DaysPerMonth) {
+			break;
+		}
+		TempDays -= DaysPerMonth;
+	}
+
+	dt->Day = TempDays;
+	dt->Year += 2000U;
+}
+
+/****************************************************************************/
+/**
+*
+* This function translates time in YEAR:MON:DAY HR:MIN:SEC format to
+* seconds.
+*
+* @param	dt is a pointer to a DatetTime format structure variable
+* 			of time that has to be shown in seconds.
+*
+* @return	Seconds value of provided in dt time.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XRtcPsu_DateTimeToSec(XRtcPsu_DT *dt)
+{
+	u32 i, Days;
+	u32 Seconds;
+	Xil_AssertNonvoid(dt != NULL);
+
+	if (dt->Year >= 2000U) {
+		dt->Year -= 2000U;
+	}
+
+	for (i = 1U; i < dt->Month; i++) {
+		dt->Day += (u32)DaysInMonth[i-1];
+	}
+
+	if ((dt->Month > 2U) && ((dt->Year % 4U) == 0U)) {
+		dt->Day++;
+	}
+	Days = dt->Day + (365U * dt->Year) + ((dt->Year + 3U) / 4U);
+	Seconds = (((((Days * 24U) + dt->Hour) * 60U) + dt->Min) * 60U) + dt->Sec;
+	return Seconds;
+}
+
+/****************************************************************************/
+/**
+*
+* This function calculates the calibration value depending on the actual
+* realworld time and also helps in deriving new calibration value if
+* the user wishes to change his oscillator frequency.TimeReal is generally the
+* internet time with EPOCH time as reference i.e.,1/1/1970 1st second.
+* But this RTC driver assumes start time from 1/1/2000 1st second. Hence,if
+* the user maps the internet time InternetTimeInSecs, then he has to use
+* 	XRtcPsu_SecToDateTime(InternetTimeInSecs,&InternetTime),
+* 	TimeReal = XRtcPsu_DateTimeToSec(InternetTime)
+* 	consecutively to arrive at TimeReal value.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	TimeReal is the actual realworld time generally an
+* 		network time / Internet time in seconds.
+*
+* @param	CrystalOscFreq is the Oscillator new frequency. Say, If the user
+* 		is going with the typical 32768Hz, then he inputs the same
+* 		frequency value.
+*
+* @return	None.
+*
+* @note		After Calculating the calibration register, user / application has to
+* 			call again CfgInitialize API to bring the new calibration into effect.
+*
+*****************************************************************************/
+void XRtcPsu_CalculateCalibration(XRtcPsu *InstancePtr,u32 TimeReal,
+		u32 CrystalOscFreq)
+{
+	u32 ReadTime, SetTime;
+	u32 Cprev,Fprev,Cnew,Fnew,Xf,Calibration;
+	Xil_AssertVoid(TimeReal != 0U);
+	Xil_AssertVoid(CrystalOscFreq != 0U);
+
+	ReadTime = XRtcPsu_GetCurrentTime(InstancePtr);
+	SetTime = XRtcPsu_GetLastSetTime(InstancePtr);
+	Calibration = XRtcPsu_GetCalibration(InstancePtr);
+	/*
+	 * When board gets reseted, Calibration value is zero
+	 * and Last setTime will be marked as 1st  second. This implies
+	 * CurrentTime to be in few seconds say something in tens. TimeReal will
+	 * be huge, say something in thousands. So to prevent such reset case, Cnew
+	 * and Fnew will not be calculated.
+	 */
+	if((Calibration == 0U) || (CrystalOscFreq != InstancePtr->OscillatorFreq)) {
+		Cnew = CrystalOscFreq - (u32)1;
+		Fnew = 0U;
+	} else {
+		Cprev = Calibration & XRTC_CALIB_RD_MAX_TCK_MASK;
+		Fprev = Calibration & XRTC_CALIB_RD_FRACTN_DATA_MASK;
+
+		Xf = ((ReadTime - SetTime) * ((Cprev+1U) + ((Fprev+1U)/16U))) / (TimeReal - SetTime);
+		Cnew = (u32)(Xf) - (u32)1;
+		Fnew = XRtcPsu_RoundOff((Xf - Cnew) * 16U) - (u32)1;
+	}
+
+	Calibration = (Fnew << XRTC_CALIB_RD_FRACTN_DATA_SHIFT) + Cnew;
+	Calibration |= XRTC_CALIB_RD_FRACTN_EN_MASK;
+
+	InstancePtr->CalibrationValue = Calibration;
+	InstancePtr->OscillatorFreq = CrystalOscFreq;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the seconds event status by reading
+* interrupt status register.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	Returns 1 if a new second event is generated.Else 0..
+*
+* @note		This API is used in polled mode operation of RTC.
+* 			This also clears interrupt status seconds bit.
+*
+*****************************************************************************/
+u32 XRtcPsu_IsSecondsEventGenerated(XRtcPsu *InstancePtr)
+{
+	u32 Status;
+
+	/* Loop the interrupt status register for Seconds Event */
+	if ((XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_INT_STS_OFFSET) & (XRTC_INT_STS_SECS_MASK)) == 0U) {
+		Status = 0U;
+	} else {
+		/* Clear the interrupt status register */
+		XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr +
+				XRTC_INT_STS_OFFSET, XRTC_INT_STS_SECS_MASK);
+		Status = 1U;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the alarm event status by reading
+* interrupt status register.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	Returns 1 if the alarm event is generated.Else 0.
+*
+* @note		This API is used in polled mode operation of RTC.
+* 			This also clears interrupt status alarm bit.
+*
+*****************************************************************************/
+u32 XRtcPsu_IsAlarmEventGenerated(XRtcPsu *InstancePtr)
+{
+	u32 Status;
+
+	/* Loop the interrupt status register for Alarm Event */
+	if ((XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_INT_STS_OFFSET) & (XRTC_INT_STS_ALRM_MASK)) == 0U) {
+		Status = 0U;
+	} else {
+		/* Clear the interrupt status register */
+		XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr +
+				XRTC_INT_STS_OFFSET, XRTC_INT_STS_ALRM_MASK);
+		Status = 1U;
+	}
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.h
new file mode 100644
index 000000000..98e668911
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu.h
@@ -0,0 +1,387 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xrtcpsu.h
+* @addtogroup rtcpsu_v1_0
+* @{
+* @details
+*
+* The Xilinx RTC driver component.  This component supports the Xilinx
+* RTC Controller. RTC Core and RTC controller are the two main important sub-
+* components for this RTC module. RTC core can run even in the battery powered
+* domain when the power from auxiliary source is down. Because of this, RTC core
+* latches the calibration,programmed time. This core interfaces with the crystal
+* oscillator and maintains current time in seconds.Calibration circuitry
+* calculates a second with maximum 1 PPM inaccuracy using a crystal oscillator
+* with arbitrary static inaccuracy. Core also responsible to maintain control
+* value used by the oscillator and power switching circuitry.
+*
+* RTC controller includes an APB interface responsible for register access with
+* in controller and core. It contains alarm generation logic including the alarm
+* register to hold alarm time in seconds.Interrupt management using Interrupt
+* status, Interrupt mask, Interrupt enable, Interrupt disable registers are
+* included to manage alarm and seconds interrupts. Address Slave error interrupts
+* are not being handled by this driver component.
+*
+* This driver supports the following features:
+* - Setting the RTC time.
+* - Setting the Alarm value that can be one-time alarm or a periodic alarm.
+* - Modifying the calibration value.
+*
+* Initialization & Configuration
+*
+* The XRtcPsu_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XRtcPsu based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*   - XRtcPsu_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	 configuration structure provided by the caller. If running in a system
+*	 with address translation, the parameter EffectiveAddr should be the
+* 	  virtual address.
+*
+* Interrupts
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - Alarm is generated.
+* - A new second is generated.
+*
+* The application can control which interrupts are enabled using the
+* XRtcPsu_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XRtcPsu_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XRtcPsu_SetHandler() function.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    04/21/15 First release
+* 1.1   kvn    09/25/15 Modify control register to enable battery
+*                       switching when vcc_psaux is not available.
+* 

+*
+******************************************************************************/
+
+
+#ifndef XRTC_H_			/* prevent circular inclusions */
+#define XRTC_H_			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xrtcpsu_hw.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XRTCPSU_EVENT_ALARM_GEN		1U /**< Alarm generated event */
+#define XRTCPSU_EVENT_SECS_GEN		2U /**< A new second generated event */
+/*@}*/
+
+#define XRTCPSU_CRYSTAL_OSC_EN		(u32)1 << XRTC_CTL_OSC_SHIFT
+/**< Separate Mask for Crystal oscillator bit Enable */
+
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ * @param	Event contains one of the event constants indicating events that
+ *		have occurred.
+ * @param	EventData contains the number of bytes sent or received at the
+ *		time of the call for send and receive events and contains the
+ *		modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XRtcPsu_Handler) (void *CallBackRef, u32 Event);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddr;		/**< Register base address */
+} XRtcPsu_Config;
+
+/**
+ * The XRtcPsu driver instance data. The user is required to allocate a
+ * variable of this type for the RTC device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XRtcPsu_Config RtcConfig; 	/**< Device configuration */
+	u32 IsReady;				/**< Device is initialized and ready */
+	u32 PeriodicAlarmTime;
+	u8 IsPeriodicAlarm;
+	u32 OscillatorFreq;
+	u32 CalibrationValue;
+	XRtcPsu_Handler Handler;
+	void *CallBackRef;			/**< Callback reference for event handler */
+} XRtcPsu;
+
+/**
+ * This typedef contains DateTime format structure.
+ */
+typedef struct {
+	u32 Year;
+	u32 Month;
+	u32 Day;
+	u32 Hour;
+	u32 Min;
+	u32 Sec;
+	u32 WeekDay;
+} XRtcPsu_DT;
+
+
+/************************* Variable Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XRTC_CALIBRATION_VALUE 0x00198231U
+#define XRTC_TYPICAL_OSC_FREQ 33330U
+
+/****************************************************************************/
+/**
+*
+* This macro updates the current time of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	Time is the desired time for RTC in seconds.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XRtcPsu_SetTime(XRtcPsu *InstancePtr, u32 Time)
+*
+*****************************************************************************/
+#define XRtcPsu_SetTime(InstancePtr,Time) \
+	XRtcPsu_WriteReg(((InstancePtr)->RtcConfig.BaseAddr + \
+				XRTC_SET_TIME_WR_OFFSET),(Time))
+
+/****************************************************************************/
+/**
+*
+* This macro returns the last set time of RTC device. Whenever a reset
+* happens, the last set time will be zeroth day first sec.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	The last set time in seconds.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_GetLastSetTime(XRtcPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XRtcPsu_GetLastSetTime(InstancePtr) \
+	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr + XRTC_SET_TIME_RD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* This macro returns the calibration value of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	Calibration value for RTC.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_GetCalibration(XRtcPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XRtcPsu_GetCalibration(InstancePtr) \
+	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr+XRTC_CALIB_RD_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* This macro returns the current time of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	Current Time. This current time will be in seconds.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_GetCurrentTime(XRtcPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XRtcPsu_GetCurrentTime(InstancePtr) \
+	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr+XRTC_CUR_TIME_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* This macro sets the control register value of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	Value is the desired control register value for RTC.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XRtcPsu_SetControlRegister(XRtcPsu *InstancePtr, u32 Value)
+*
+*****************************************************************************/
+#define XRtcPsu_SetControlRegister(InstancePtr, Value) \
+	XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr + \
+			XRTC_CTL_OFFSET,(Value))
+
+/****************************************************************************/
+/**
+*
+* This macro returns the safety check register value of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	Safety check register value.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_GetSafetyCheck(XRtcPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XRtcPsu_GetSafetyCheck(InstancePtr)	\
+	XRtcPsu_ReadReg((InstancePtr)->RtcConfig.BaseAddr+XRTC_SFTY_CHK_OFFSET)
+
+/****************************************************************************/
+/**
+*
+* This macro sets the safety check register value of RTC device.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+* @param	Value is a safety check value to be written in register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		void XRtcPsu_SetSafetyCheck(XRtcPsu *InstancePtr, u32 Value)
+*
+*****************************************************************************/
+#define XRtcPsu_SetSafetyCheck(InstancePtr, Value)	\
+	XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr + \
+			XRTC_SFTY_CHK_OFFSET,(Value))
+
+/****************************************************************************/
+/**
+*
+* This macro resets the alarm register
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_ResetAlarm(XRtcPsu *InstancePtr)
+*
+*****************************************************************************/
+#define XRtcPsu_ResetAlarm(InstancePtr) \
+		XRtcPsu_WriteReg((InstancePtr)->RtcConfig.BaseAddr + \
+				XRTC_ALRM_OFFSET,XRTC_ALRM_RSTVAL)
+
+/****************************************************************************/
+/**
+*
+* This macro rounds off the given number
+*
+* @param	Number is the one that needs to be rounded off..
+*
+* @return	The rounded off value of the input number.
+*
+* @note		C-Style signature:
+* 		u32 XRtcPsu_RoundOff(float Number)
+*
+*****************************************************************************/
+#define XRtcPsu_RoundOff(Number) \
+	(u32)(((Number) < (u32)0) ? ((Number) - (u32)0.5) : ((Number) + (u32)0.5))
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xrtcpsu.c */
+s32 XRtcPsu_CfgInitialize(XRtcPsu *InstancePtr, XRtcPsu_Config *ConfigPtr,
+				u32 EffectiveAddr);
+
+void XRtcPsu_SetAlarm(XRtcPsu *InstancePtr, u32 Alarm, u32 Periodic);
+void XRtcPsu_SecToDateTime(u32 Seconds, XRtcPsu_DT *dt);
+u32 XRtcPsu_DateTimeToSec(XRtcPsu_DT *dt);
+void XRtcPsu_CalculateCalibration(XRtcPsu *InstancePtr,u32 TimeReal,
+		u32 CrystalOscFreq);
+u32 XRtcPsu_IsSecondsEventGenerated(XRtcPsu *InstancePtr);
+u32 XRtcPsu_IsAlarmEventGenerated(XRtcPsu *InstancePtr);
+
+/* interrupt functions in xrtcpsu_intr.c */
+void XRtcPsu_SetInterruptMask(XRtcPsu *InstancePtr, u32 Mask);
+void XRtcPsu_ClearInterruptMask(XRtcPsu *InstancePtr, u32 Mask);
+void XRtcPsu_InterruptHandler(XRtcPsu *InstancePtr);
+void XRtcPsu_SetHandler(XRtcPsu *InstancePtr, XRtcPsu_Handler FuncPtr,
+			 void *CallBackRef);
+
+/* Functions in xrtcpsu_selftest.c */
+s32 XRtcPsu_SelfTest(XRtcPsu *InstancePtr);
+
+/* Functions in xrtcpsu_sinit.c */
+XRtcPsu_Config *XRtcPsu_LookupConfig(u16 DeviceId);
+
+
+#endif /* XRTC_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
new file mode 100644
index 000000000..8dc37775a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xrtcpsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XRtcPsu_Config XRtcPsu_ConfigTable[] =
+{
+	{
+		XPAR_PSU_RTC_DEVICE_ID,
+		XPAR_PSU_RTC_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_hw.h
new file mode 100644
index 000000000..532ef7e3c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_hw.h
@@ -0,0 +1,362 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xrtcpsu_hw.h
+* @addtogroup rtcpsu_v1_0
+* @{
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xrtcpsu.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00a kvn	  04/21/15 First release
+* 1.1   kvn   09/25/15 Modify control register to enable battery
+*                      switching when vcc_psaux is not available.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XRTC_HW_H_		/* prevent circular inclusions */
+#define XRTC_HW_H_		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * Xrtc Base Address
+ */
+#define XRTC_BASEADDR      0xFFA60000U
+
+/**
+ * Register: XrtcSetTimeWr
+ */
+#define XRTC_SET_TIME_WR_OFFSET    0x00000000U
+#define XRTC_SET_TIME_WR_RSTVAL   0x00000000U
+
+#define XRTC_SET_TIME_WR_VAL_SHIFT   0U
+#define XRTC_SET_TIME_WR_VAL_WIDTH   32U
+#define XRTC_SET_TIME_WR_VAL_MASK    0xffffffffU
+#define XRTC_SET_TIME_WR_VAL_DEFVAL  0x0U
+
+/**
+ * Register: XrtcSetTimeRd
+ */
+#define XRTC_SET_TIME_RD_OFFSET    0x00000004U
+#define XRTC_SET_TIME_RD_RSTVAL   0x00000000U
+
+#define XRTC_SET_TIME_RD_VAL_SHIFT   0U
+#define XRTC_SET_TIME_RD_VAL_WIDTH   32U
+#define XRTC_SET_TIME_RD_VAL_MASK    0xffffffffU
+#define XRTC_SET_TIME_RD_VAL_DEFVAL  0x0U
+
+/**
+ * Register: XrtcCalibWr
+ */
+#define XRTC_CALIB_WR_OFFSET    0x00000008U
+#define XRTC_CALIB_WR_RSTVAL   0x00000000U
+
+#define XRTC_CALIB_WR_FRACTN_EN_SHIFT   20U
+#define XRTC_CALIB_WR_FRACTN_EN_WIDTH   1U
+#define XRTC_CALIB_WR_FRACTN_EN_MASK    0x00100000U
+#define XRTC_CALIB_WR_FRACTN_EN_DEFVAL  0x0U
+
+#define XRTC_CALIB_WR_FRACTN_DATA_SHIFT   16U
+#define XRTC_CALIB_WR_FRACTN_DATA_WIDTH   4U
+#define XRTC_CALIB_WR_FRACTN_DATA_MASK    0x000f0000U
+#define XRTC_CALIB_WR_FRACTN_DATA_DEFVAL  0x0U
+
+#define XRTC_CALIB_WR_MAX_TCK_SHIFT   0U
+#define XRTC_CALIB_WR_MAX_TCK_WIDTH   16U
+#define XRTC_CALIB_WR_MAX_TCK_MASK    0x0000ffffU
+#define XRTC_CALIB_WR_MAX_TCK_DEFVAL  0x0U
+
+/**
+ * Register: XrtcCalibRd
+ */
+#define XRTC_CALIB_RD_OFFSET    0x0000000CU
+#define XRTC_CALIB_RD_RSTVAL   0x00000000U
+
+#define XRTC_CALIB_RD_FRACTN_EN_SHIFT   20U
+#define XRTC_CALIB_RD_FRACTN_EN_WIDTH   1U
+#define XRTC_CALIB_RD_FRACTN_EN_MASK    0x00100000U
+#define XRTC_CALIB_RD_FRACTN_EN_DEFVAL  0x0U
+
+#define XRTC_CALIB_RD_FRACTN_DATA_SHIFT   16U
+#define XRTC_CALIB_RD_FRACTN_DATA_WIDTH   4U
+#define XRTC_CALIB_RD_FRACTN_DATA_MASK    0x000f0000U
+#define XRTC_CALIB_RD_FRACTN_DATA_DEFVAL  0x0U
+
+#define XRTC_CALIB_RD_MAX_TCK_SHIFT   0U
+#define XRTC_CALIB_RD_MAX_TCK_WIDTH   16U
+#define XRTC_CALIB_RD_MAX_TCK_MASK    0x0000ffffU
+#define XRTC_CALIB_RD_MAX_TCK_DEFVAL  0x0U
+
+/**
+ * Register: XrtcCurTime
+ */
+#define XRTC_CUR_TIME_OFFSET    0x00000010U
+#define XRTC_CUR_TIME_RSTVAL   0x00000000U
+
+#define XRTC_CUR_TIME_VAL_SHIFT   0U
+#define XRTC_CUR_TIME_VAL_WIDTH   32U
+#define XRTC_CUR_TIME_VAL_MASK    0xffffffffU
+#define XRTC_CUR_TIME_VAL_DEFVAL  0x0U
+
+/**
+ * Register: XrtcCurTck
+ */
+#define XRTC_CUR_TCK_OFFSET    0x00000014U
+#define XRTC_CUR_TCK_RSTVAL   0x00000000U
+
+#define XRTC_CUR_TCK_VAL_SHIFT   0U
+#define XRTC_CUR_TCK_VAL_WIDTH   16U
+#define XRTC_CUR_TCK_VAL_MASK    0x0000ffffU
+#define XRTC_CUR_TCK_VAL_DEFVAL  0x0U
+
+/**
+ * Register: XrtcAlrm
+ */
+#define XRTC_ALRM_OFFSET    0x00000018U
+#define XRTC_ALRM_RSTVAL   0x00000000U
+
+#define XRTC_ALRM_VAL_SHIFT   0U
+#define XRTC_ALRM_VAL_WIDTH   32U
+#define XRTC_ALRM_VAL_MASK    0xffffffffU
+#define XRTC_ALRM_VAL_DEFVAL  0x0U
+
+/**
+ * Register: XrtcIntSts
+ */
+#define XRTC_INT_STS_OFFSET    0x00000020U
+#define XRTC_INT_STS_RSTVAL   0x00000000U
+
+#define XRTC_INT_STS_ALRM_SHIFT   1U
+#define XRTC_INT_STS_ALRM_WIDTH   1U
+#define XRTC_INT_STS_ALRM_MASK    0x00000002U
+#define XRTC_INT_STS_ALRM_DEFVAL  0x0U
+
+#define XRTC_INT_STS_SECS_SHIFT   0U
+#define XRTC_INT_STS_SECS_WIDTH   1U
+#define XRTC_INT_STS_SECS_MASK    0x00000001U
+#define XRTC_INT_STS_SECS_DEFVAL  0x0U
+
+/**
+ * Register: XrtcIntMsk
+ */
+#define XRTC_INT_MSK_OFFSET    0x00000024U
+#define XRTC_INT_MSK_RSTVAL   0x00000003U
+
+#define XRTC_INT_MSK_ALRM_SHIFT   1U
+#define XRTC_INT_MSK_ALRM_WIDTH   1U
+#define XRTC_INT_MSK_ALRM_MASK    0x00000002U
+#define XRTC_INT_MSK_ALRM_DEFVAL  0x1U
+
+#define XRTC_INT_MSK_SECS_SHIFT   0U
+#define XRTC_INT_MSK_SECS_WIDTH   1U
+#define XRTC_INT_MSK_SECS_MASK    0x00000001U
+#define XRTC_INT_MSK_SECS_DEFVAL  0x1U
+
+/**
+ * Register: XrtcIntEn
+ */
+#define XRTC_INT_EN_OFFSET    0x00000028U
+#define XRTC_INT_EN_RSTVAL   0x00000000U
+
+#define XRTC_INT_EN_ALRM_SHIFT   1U
+#define XRTC_INT_EN_ALRM_WIDTH   1U
+#define XRTC_INT_EN_ALRM_MASK    0x00000002U
+#define XRTC_INT_EN_ALRM_DEFVAL  0x0U
+
+#define XRTC_INT_EN_SECS_SHIFT   0U
+#define XRTC_INT_EN_SECS_WIDTH   1U
+#define XRTC_INT_EN_SECS_MASK    0x00000001U
+#define XRTC_INT_EN_SECS_DEFVAL  0x0U
+
+/**
+ * Register: XrtcIntDis
+ */
+#define XRTC_INT_DIS_OFFSET    0x0000002CU
+#define XRTC_INT_DIS_RSTVAL   0x00000000U
+
+#define XRTC_INT_DIS_ALRM_SHIFT   1U
+#define XRTC_INT_DIS_ALRM_WIDTH   1U
+#define XRTC_INT_DIS_ALRM_MASK    0x00000002U
+#define XRTC_INT_DIS_ALRM_DEFVAL  0x0U
+
+#define XRTC_INT_DIS_SECS_SHIFT   0U
+#define XRTC_INT_DIS_SECS_WIDTH   1U
+#define XRTC_INT_DIS_SECS_MASK    0x00000001U
+#define XRTC_INT_DIS_SECS_DEFVAL  0x0U
+
+/**
+ * Register: XrtcAddErr
+ */
+#define XRTC_ADD_ERR_OFFSET    0x00000030U
+#define XRTC_ADD_ERR_RSTVAL   0x00000000U
+
+#define XRTC_ADD_ERR_STS_SHIFT   0U
+#define XRTC_ADD_ERR_STS_WIDTH   1U
+#define XRTC_ADD_ERR_STS_MASK    0x00000001U
+#define XRTC_ADD_ERR_STS_DEFVAL  0x0U
+
+/**
+ * Register: XrtcAddErrIntMsk
+ */
+#define XRTC_ADD_ERR_INT_MSK_OFFSET    0x00000034U
+#define XRTC_ADD_ERR_INT_MSK_RSTVAL   0x00000001U
+
+#define XRTC_ADD_ERR_INT_MSK_SHIFT   0U
+#define XRTC_ADD_ERR_INT_MSK_WIDTH   1U
+#define XRTC_ADD_ERR_INT_MSK_MASK    0x00000001U
+#define XRTC_ADD_ERR_INT_MSK_DEFVAL  0x1U
+
+/**
+ * Register: XrtcAddErrIntEn
+ */
+#define XRTC_ADD_ERR_INT_EN_OFFSET    0x00000038U
+#define XRTC_ADD_ERR_INT_EN_RSTVAL   0x00000000U
+
+#define XRTC_ADD_ERR_INT_EN_MSK_SHIFT   0U
+#define XRTC_ADD_ERR_INT_EN_MSK_WIDTH   1U
+#define XRTC_ADD_ERR_INT_EN_MSK_MASK    0x00000001U
+#define XRTC_ADD_ERR_INT_EN_MSK_DEFVAL  0x0U
+
+/**
+ * Register: XrtcAddErrIntDis
+ */
+#define XRTC_ADD_ERR_INT_DIS_OFFSET    0x0000003CU
+#define XRTC_ADD_ERR_INT_DIS_RSTVAL   0x00000000U
+
+#define XRTC_ADD_ERR_INT_DIS_MSK_SHIFT   0U
+#define XRTC_ADD_ERR_INT_DIS_MSK_WIDTH   1U
+#define XRTC_ADD_ERR_INT_DIS_MSK_MASK    0x00000001U
+#define XRTC_ADD_ERR_INT_DIS_MSK_DEFVAL  0x0U
+
+/**
+ * Register: XrtcCtl
+ */
+#define XRTC_CTL_OFFSET    0x00000040U
+#define XRTC_CTL_RSTVAL   0x01000000U
+
+#define XRTC_CTL_BATTERY_EN_SHIFT   31U
+#define XRTC_CTL_BATTERY_EN_WIDTH   1U
+#define XRTC_CTL_BATTERY_EN_MASK    0x80000000U
+#define XRTC_CTL_BATTERY_EN_DEFVAL  0x0U
+
+#define XRTC_CTL_OSC_SHIFT   24U
+#define XRTC_CTL_OSC_WIDTH   4U
+#define XRTC_CTL_OSC_MASK    0x0f000000U
+#define XRTC_CTL_OSC_DEFVAL  0x1U
+
+#define XRTC_CTL_SLVERR_EN_SHIFT   0U
+#define XRTC_CTL_SLVERR_EN_WIDTH   1U
+#define XRTC_CTL_SLVERR_EN_MASK    0x00000001U
+#define XRTC_CTL_SLVERR_EN_DEFVAL  0x0U
+
+/**
+ * Register: XrtcSftyChk
+ */
+#define XRTC_SFTY_CHK_OFFSET    0x00000050U
+#define XRTC_SFTY_CHK_RSTVAL   0x00000000U
+
+#define XRTC_SFTY_CHK_REG_SHIFT   0U
+#define XRTC_SFTY_CHK_REG_WIDTH   32U
+#define XRTC_SFTY_CHK_REG_MASK    0xffffffffU
+#define XRTC_SFTY_CHK_REG_DEFVAL  0x0U
+
+/**
+ * Register: XrtcEco
+ */
+#define XRTC_ECO_OFFSET    0x00000060U
+#define XRTC_ECO_RSTVAL   0x00000000U
+
+#define XRTC_ECO_REG_SHIFT   0U
+#define XRTC_ECO_REG_WIDTH   32U
+#define XRTC_ECO_REG_MASK    0xffffffffU
+#define XRTC_ECO_REG_DEFVAL  0x0U
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	RegisterAddr is the register address in the address
+* 			space of the RTC device.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XRtcPsu_ReadReg(RegisterAddr) Xil_In32(RegisterAddr)
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	RegisterAddr is the register address in the address
+* 			space of the RTC device.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XRtcPsu_WriteReg(RegisterAddr, Data) Xil_Out32(RegisterAddr, (u32)(Data))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XRTC_HW_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_intr.c
new file mode 100644
index 000000000..bca20af12
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_intr.c
@@ -0,0 +1,232 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xrtcpsu_intr.c
+* @addtogroup rtcpsu_v1_0
+* @{
+*
+* This file contains functions related to RTC interrupt handling.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    04/21/15 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xrtcpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance
+* @param	Mask contains the interrupts to be enabled.
+*		A '1' enables an interupt, and a '0' disables.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XRtcPsu_SetInterruptMask(XRtcPsu *InstancePtr, u32 Mask)
+{
+	/*
+	 * Clear the Status register to be sure of no pending interrupts.
+	 * Writing mask values to interrupt bits as it is a WTC register.
+	 */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_INT_STS_OFFSET,
+			((u32)XRTC_INT_STS_ALRM_MASK | (u32)XRTC_INT_STS_SECS_MASK));
+
+	/*
+	 * XRTC_INT_MSK_RSTVAL contains the valid interrupts
+	 * for the RTC device. The AND operation on Mask makes sure one
+	 * of the valid bits are only set.
+	 */
+
+	/* Write the mask to the IER Register */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr+XRTC_INT_EN_OFFSET,
+					(Mask & (u32)XRTC_INT_MSK_RSTVAL));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the interrupt mask.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance
+* @param	Mask contains the interrupts to be disabled.
+*		A '1' enables an interrupt, and a '0' disables.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XRtcPsu_ClearInterruptMask(XRtcPsu *InstancePtr, u32 Mask)
+{
+	/*
+	 * XRTC_INT_MSK_RSTVAL contains the valid interrupts
+	 * for the RTC device. The AND operation on mask makes sure one
+	 * of the valid bits are only cleared.
+	 */
+
+	/* Write the Mask to the IDR register */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr+XRTC_INT_DIS_OFFSET,
+					(Mask & (u32)XRTC_INT_MSK_RSTVAL));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance
+* @param	FuncPtr is the pointer to the callback function.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+*
+* @return	None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XRtcPsu_SetHandler(XRtcPsu *InstancePtr, XRtcPsu_Handler FuncPtr,
+		 void *CallBackRef)
+{
+	/*
+	 * Asserts validate the input arguments
+	 * CallBackRef not checked, no way to know what is valid
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param	InstancePtr contains a pointer to the driver instance
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XRtcPsu_InterruptHandler(XRtcPsu *InstancePtr)
+{
+	u32 IsrStatus;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the interrupt ID register to determine which
+	 * interrupt is active.
+	 */
+	IsrStatus = ~(XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_INT_MSK_OFFSET));
+
+	IsrStatus &= XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_INT_STS_OFFSET);
+
+	/*
+	 * Clear the interrupt status to allow future
+	 * interrupts before this generated interrupt is serviced.
+	 */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_INT_STS_OFFSET, IsrStatus);
+
+	/* Handle the generated interrupts appropriately. */
+
+	/* Alarm interrupt */
+	if((IsrStatus & XRTC_INT_STS_ALRM_MASK) != (u32)0) {
+
+		if(InstancePtr->IsPeriodicAlarm != 0U) {
+			XRtcPsu_SetAlarm(InstancePtr,
+					(XRtcPsu_GetCurrentTime(InstancePtr)+InstancePtr->PeriodicAlarmTime),1U);
+		}
+
+		/*
+		 * Call the application handler to indicate that there is an
+		 * alarm interrupt. If the application cares about this alarm,
+		 * it will act accordingly through its own handler.
+		 */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					XRTCPSU_EVENT_ALARM_GEN);
+	}
+
+	/* Seconds interrupt */
+	if((IsrStatus & XRTC_INT_STS_SECS_MASK) != (u32)0) {
+		/*
+		 * Call the application handler to indicate that there is an
+		 * seconds interrupt. If the application cares about this seconds
+		 * interrupt, it will act accordingly through its own handler.
+		 */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					XRTCPSU_EVENT_SECS_GEN);
+	}
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_selftest.c
new file mode 100644
index 000000000..67c562c64
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_selftest.c
@@ -0,0 +1,112 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xrtcpsu_selftest.c
+* @addtogroup rtcpsu_v1_0
+* @{
+*
+* This file contains the self-test functions for the XRtcPsu driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  kvn    04/21/15 First release.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xrtcpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test writes reset value into safety check register and read backs the same.
+* If mismatch offers, returns the failure.
+*
+* @param	InstancePtr is a pointer to the XRtcPsu instance
+*
+* @return
+*		 - XST_SUCCESS if the test was successful
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+s32 XRtcPsu_SelfTest(XRtcPsu *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 SafetyCheck;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Write the reset value in safety check register and
+	 * try reading back. If mismatch happens, return failure.
+	 */
+	XRtcPsu_WriteReg(InstancePtr->RtcConfig.BaseAddr + XRTC_SFTY_CHK_OFFSET,
+			XRTC_SFTY_CHK_RSTVAL);
+	SafetyCheck = XRtcPsu_ReadReg(InstancePtr->RtcConfig.BaseAddr +
+			XRTC_SFTY_CHK_OFFSET);
+
+	if (SafetyCheck != XRTC_SFTY_CHK_RSTVAL) {
+		Status = XST_FAILURE;
+	}
+
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_sinit.c
new file mode 100644
index 000000000..d3a8b7dfc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/rtcpsu_v1_2/src/xrtcpsu_sinit.c
@@ -0,0 +1,102 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xrtcpsu_sinit.c
+* @addtogroup rtcpsu_v1_0
+* @{
+*
+* This file contains the implementation of the XRtcPsu driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    04/21/15 First release.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xrtcpsu.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XRtcPsu_Config XRtcPsu_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XRtcPsu_ConfigTable[] contains the configuration information for
+* each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XRtcPsu_Config *XRtcPsu_LookupConfig(u16 DeviceId)
+{
+	XRtcPsu_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XRTCPSU_NUM_INSTANCES; Index++) {
+		if (XRtcPsu_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XRtcPsu_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XRtcPsu_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/Makefile
new file mode 100644
index 000000000..04867a484
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner scugic_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling scugic"
+
+scugic_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: scugic_includes
+
+scugic_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.c
new file mode 100644
index 000000000..1806274c7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.c
@@ -0,0 +1,769 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* Contains required functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 Changes are made in function XScuGic_CfgInitialize. Since
+*		      "Config" entry is now made as pointer in the XScuGic
+*		      structure, necessary changes are made.
+*		      The HandlerTable can now be populated through the low
+*		      level routine XScuGic_RegisterHandler added in this
+*		      release. Hence necessary checks are added not to
+*		      overwrite the HandlerTable entriesin function
+*		      XScuGic_CfgInitialize.
+* 1.03a srt  02/27/13 Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+* 		      Removed Offset calculation macros, defined in _hw.h
+*		      (CR 702687)
+*			  Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+*
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.06a asa  16/11/13 Fix for CR#749178. Assignment for EffectiveAddr
+*			  in function XScuGic_CfgInitialize is removed as it was
+*		      a bug.
+* 3.00  kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.01	pkp	 06/19/15 Added XScuGic_InterruptMaptoCpu API for an interrupt
+*			  target CPU mapping
+* 3.02	pkp	 11/09/15 Modified DistributorInit function for AMP case to add
+*					  the current cpu to interrupt processor targets registers
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  distributor is left uninitialized for Zynq AMP. It is assumed
+*             that the distributor will be initialized by Linux master. However
+*             for CortexR5 case, the earlier code is left unchanged where the
+*             the interrupt processor target registers in the distributor is
+*             initialized with the corresponding CPU ID on which the application
+*             built over the scugic driver runs.
+*             These changes fix CR#937243.
+*
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+static void StubHandler(void *CallBackRef);
+
+/*****************************************************************************/
+/**
+*
+* DistributorInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistributorInit(XScuGic *InstancePtr, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+#if USE_AMP==1
+	#warning "Building GIC for AMP"
+#ifdef ARMR5
+    u32 RegValue;
+
+	/*
+	 * The overall distributor should not be initialized in AMP case where
+	 * another CPU is taking care of it.
+	 */
+	LocalCpuID |= LocalCpuID << 8U;
+	LocalCpuID |= LocalCpuID << 16U;
+	for (Int_Id = 32U; Int_IdBaseAddress for this parameters, passing the physical
+*		address instead.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr,
+				XScuGic_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	u32 Int_Id;
+	u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
+	(void) EffectiveAddr;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	if(InstancePtr->IsReady != XIL_COMPONENT_IS_READY) {
+
+		InstancePtr->IsReady = 0;
+		InstancePtr->Config = ConfigPtr;
+
+
+		for (Int_Id = 0U; Int_IdConfig->HandlerTable[Int_Id].Handler == NULL)) {
+				InstancePtr->Config->HandlerTable[Int_Id].Handler =
+									StubHandler;
+			}
+			InstancePtr->Config->HandlerTable[Int_Id].CallBackRef =
+								InstancePtr;
+		}
+
+		DistributorInit(InstancePtr, Cpu_Id);
+		CPUInitialize(InstancePtr);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	}
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Int_Id of the interrupt source and the
+* associated handler that is to run when the interrupt is recognized. The
+* argument provided in this call as the Callbackref is used as the argument
+* for the handler when it is called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+* @param	Handler to the handler for that interrupt.
+* @param	CallBackRef is the callback reference, usually the instance
+*		pointer of the connecting driver.
+*
+* @return
+*
+*		- XST_SUCCESS if the handler was connected correctly.
+*
+* @note
+*
+* WARNING: The handler provided as an argument will overwrite any handler
+* that was previously connected.
+*
+****************************************************************************/
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+                      Xil_InterruptHandler Handler, void *CallBackRef)
+{
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertNonvoid(Handler != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used as an index into the table to select the proper
+	 * handler
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = Handler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = CallBackRef;
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* Updates the interrupt table with the Null Handler and NULL arguments at the
+* location pointed at by the Int_Id. This effectively disconnects that interrupt
+* source from any handler. The interrupt is disabled also.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param	Int_Id contains the ID of the interrupt source and should
+*		be in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the interrupt such that it won't occur while disconnecting
+	 * the handler, only disable the specified interrupt id without modifying
+	 * the other interrupt ids
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+
+	/*
+	 * Disconnect the handler and connect a stub, the callback reference
+	 * must be set to this instance to allow unhandled interrupts to be
+	 * tracked
+	 */
+	InstancePtr->Config->HandlerTable[Int_Id].Handler = StubHandler;
+	InstancePtr->Config->HandlerTable[Int_Id].CallBackRef = InstancePtr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Enables the interrupt source provided as the argument Int_Id. Any pending
+* interrupt condition for the specified Int_Id will occur after this function is
+* called.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Enable the selected interrupt source by setting the
+	 * corresponding bit in the Enable Set register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_ENABLE_SET_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Disables the interrupt source provided as the argument Int_Id such that the
+* interrupt controller will not cause interrupts for the specified Int_Id. The
+* interrupt controller will continue to hold an interrupt condition for the
+* Int_Id, but will not cause an interrupt.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id contains the ID of the interrupt source and should be
+*		in the range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired bit position. Int_Id currently limited to 0 - 31
+	 */
+	Mask = 0x00000001U << (Int_Id % 32U);
+
+	/*
+	 * Disable the selected interrupt source by setting the
+	 * corresponding bit in the IDR.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, (u32)XSCUGIC_DISABLE_OFFSET +
+						((Int_Id / 32U) * 4U), Mask);
+}
+
+/*****************************************************************************/
+/**
+*
+* Allows software to simulate an interrupt in the interrupt controller.  This
+* function will only be successful when the interrupt controller has been
+* started in simulation mode.  A simulated interrupt allows the interrupt
+* controller to be tested without any device to drive an interrupt input
+* signal into it.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	Int_Id is the software interrupt ID to simulate an interrupt.
+* @param	Cpu_Id is the list of CPUs to send the interrupt.
+*
+* @return
+*
+* XST_SUCCESS if successful, or XST_FAILURE if the interrupt could not be
+* simulated
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id)
+{
+	u32 Mask;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(Int_Id <= 15U) ;
+	Xil_AssertNonvoid(Cpu_Id <= 255U) ;
+
+
+	/*
+	 * The Int_Id is used to create the appropriate mask for the
+	 * desired interrupt. Int_Id currently limited to 0 - 15
+	 * Use the target list for the Cpu ID.
+	 */
+	Mask = ((Cpu_Id << 16U) | Int_Id) &
+		(XSCUGIC_SFI_TRIG_CPU_MASK | XSCUGIC_SFI_TRIG_INTID_MASK);
+
+	/*
+	 * Write to the Software interrupt trigger register. Use the appropriate
+	 * CPU Int_Id.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_SFI_TRIG_OFFSET, Mask);
+
+	/* Indicate the interrupt was successfully simulated */
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+*
+* A stub for the asynchronous callback. The stub is here in case the upper
+* layers forget to set the handler.
+*
+* @param	CallBackRef is a pointer to the upper layer callback reference
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubHandler(void *CallBackRef) {
+	/*
+	 * verify that the inputs are valid
+	 */
+	Xil_AssertVoid(CallBackRef != NULL);
+
+	/*
+	 * Indicate another unhandled interrupt for stats
+	 */
+	((XScuGic *)((void *)CallBackRef))->UnhandledInterrupts++;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority;
+	LocalPriority = Priority;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= (u8)XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= (u8)XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & (u8)XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				RegValue);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_DistWriteReg(InstancePtr, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+	XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/****************************************************************************/
+/**
+* Sets the target CPU for the interrupt of a peripheral
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cpu_Id is a CPU number for which the interrupt has to be targeted
+* @param	Int_Id is the IRQ source number to modify
+*
+* @return	None.
+*
+* @note		None
+*
+*****************************************************************************/
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id)
+{
+	u32 RegValue, Offset;
+	RegValue = XScuGic_DistReadReg(InstancePtr,
+			XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id));
+
+	Offset =  (Int_Id & 0x3);
+
+	RegValue = (RegValue | (~(0xFF << (Offset*8))) );
+	RegValue |= ((Cpu_Id) << (Offset*8));
+
+	XScuGic_DistWriteReg(InstancePtr,
+						 XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id),
+						 RegValue);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.h
new file mode 100644
index 000000000..d8efce92e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic.h
@@ -0,0 +1,327 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic.h
+* @addtogroup scugic_v3_1
+* @{
+* @details
+*
+* The generic interrupt controller driver component.
+*
+* The interrupt controller driver uses the idea of priority for the various
+* handlers. Priority is an integer within the range of 1 and 31 inclusive with
+* default of 1 being the highest priority interrupt source. The priorities
+* of the various sources can be dynamically altered as needed through
+* hardware configuration.
+*
+* The generic interrupt controller supports the following
+* features:
+*
+*   - specific individual interrupt enabling/disabling
+*   - specific individual interrupt acknowledging
+*   - attaching specific callback function to handle interrupt source
+*   - assigning desired priority to interrupt source if default is not
+*     acceptable.
+*
+* Details about connecting the interrupt handler of the driver are contained
+* in the source file specific to interrupt processing, xscugic_intr.c.
+*
+* This driver is intended to be RTOS and processor independent.  It works with
+* physical addresses only.  Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* Interrupt Vector Tables
+*
+* The device ID of the interrupt controller device is used by the driver as a
+* direct index into the configuration data table. The user should populate the
+* vector table with handlers and callbacks at run-time using the
+* XScuGic_Connect() and XScuGic_Disconnect() functions.
+*
+* Each vector table entry corresponds to a device that can generate an
+* interrupt. Each entry contains an interrupt handler function and an
+* argument to be passed to the handler when an interrupt occurs.  The
+* user must use XScuGic_Connect() when the interrupt handler takes an
+* argument other than the base address.
+*
+* Nested Interrupts Processing
+*
+* Nested interrupts are not supported by this driver.
+*
+* NOTE:
+* The generic interrupt controller is not a part of the snoop control unit
+* as indicated by the prefix "scu" in the name of the driver.
+* It is an independent module in APU.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/00 First release
+* 1.01a sdm  11/09/11 The XScuGic and XScuGic_Config structures have changed.
+*		      The HandlerTable (of type XScuGic_VectorTableEntry) is
+*		      moved to XScuGic_Config structure from XScuGic structure.
+*
+*		      The "Config" entry in XScuGic structure is made as
+*		      pointer for better efficiency.
+*
+*		      A new file named as xscugic_hw.c is now added. It is
+*		      to implement low level driver routines without using
+*		      any xscugic instance pointer. They are useful when the
+*		      user wants to use xscugic through device id or
+*		      base address. The driver routines provided are explained
+*		      below.
+*		      XScuGic_DeviceInitialize that takes device id as
+*		      argument and initializes the device (without calling
+*		      XScuGic_CfgInitialize).
+*		      XScuGic_DeviceInterruptHandler that takes device id
+*		      as argument and calls appropriate handlers from the
+*		      HandlerTable.
+*		      XScuGic_RegisterHandler that registers a new handler
+*		      by taking xscugic hardware base address as argument.
+*		      LookupConfigByBaseAddress is used to return the
+*		      corresponding config structure from XScuGic_ConfigTable
+*		      based on the scugic base address passed.
+* 1.02a sdm  12/20/11 Removed AckBeforeService from the XScuGic_Config
+*		      structure.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *.c and *_hw.c to
+*		      *_hw.h
+*		      Added APIs
+*			- XScuGic_SetPriTrigTypeByDistAddr()
+*			- XScuGic_GetPriTrigTypeByDistAddr()
+*		      (CR 702687)
+*			Added support to direct interrupts to the appropriate CPU. Earlier
+*			  interrupts were directed to CPU1 (hard coded). Now depending
+*			  upon the CPU selected by the user (xparameters.h), interrupts
+*			  will be directed to the relevant CPU. This fixes CR 699688.
+* 1.04a hk   05/04/13 Assigned EffectiveAddr to CpuBaseAddress in
+*			  XScuGic_CfgInitialize. Fix for CR#704400 to remove warnings.
+*			  Moved functions XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr to xscugic_hw.c.
+*			  This is fix for CR#705621.
+* 1.05a hk   06/26/13 Modified tcl to export external interrupts correctly to
+*                     xparameters.h. Fix for CR's 690505, 708928 & 719359.
+* 2.0   adk  12/10/13 Updated as per the New Tcl API's
+* 2.1   adk  25/04/14 Fixed the CR:789373 changes are made in the driver tcl file.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.2   asa  02/29/16 Modified DistributorInit function for Zynq AMP case. The
+*			  distributor is left uninitialized for Zynq AMP. It is assumed
+*             that the distributor will be initialized by Linux master. However
+*             for CortexR5 case, the earlier code is left unchanged where the
+*             the interrupt processor target registers in the distributor is
+*             initialized with the corresponding CPU ID on which the application
+*             built over the scugic driver runs.
+*             These changes fix CR#937243.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XSCUGIC_H /* prevent circular inclusions */
+#define XSCUGIC_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_io.h"
+#include "xscugic_hw.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* The following data type defines each entry in an interrupt vector table.
+ * The callback reference is the base address of the interrupting device
+ * for the low level driver and an instance pointer for the high level driver.
+ */
+typedef struct
+{
+	Xil_InterruptHandler Handler;
+	void *CallBackRef;
+} XScuGic_VectorTableEntry;
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct
+{
+	u16 DeviceId;		/**< Unique ID  of device */
+	u32 CpuBaseAddress;	/**< CPU Interface Register base address */
+	u32 DistBaseAddress;	/**< Distributor Register base address */
+	XScuGic_VectorTableEntry HandlerTable[XSCUGIC_MAX_NUM_INTR_INPUTS];/**<
+				 Vector table of interrupt handlers */
+} XScuGic_Config;
+
+/**
+ * The XScuGic driver instance data. The user is required to allocate a
+ * variable of this type for every intc device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct
+{
+	XScuGic_Config *Config;  /**< Configuration table entry */
+	u32 IsReady;		 /**< Device is initialized and ready */
+	u32 UnhandledInterrupts; /**< Intc Statistics */
+} XScuGic;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Write the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_CPUWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_CPUWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given CPU Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_CPUReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_CPUReadReg(InstancePtr, RegOffset) \
+	(XScuGic_ReadReg(((InstancePtr)->Config->CpuBaseAddress), (RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be written
+* @param    Data is the 32-bit value to write to the register
+*
+* @return   None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_DistWriteReg(XScuGic *InstancePtr, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_DistWriteReg(InstancePtr, RegOffset, Data) \
+(XScuGic_WriteReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset), \
+					((u32)(Data))))
+
+/****************************************************************************/
+/**
+*
+* Read the given Distributor Interface register
+*
+* @param    InstancePtr is a pointer to the instance to be worked on.
+* @param    RegOffset is the register offset to be read
+*
+* @return   The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_DistReadReg(XScuGic *InstancePtr, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_DistReadReg(InstancePtr, RegOffset) \
+(XScuGic_ReadReg(((InstancePtr)->Config->DistBaseAddress), (RegOffset)))
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Required functions in xscugic.c
+ */
+
+s32  XScuGic_Connect(XScuGic *InstancePtr, u32 Int_Id,
+			Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_Disconnect(XScuGic *InstancePtr, u32 Int_Id);
+
+void XScuGic_Enable(XScuGic *InstancePtr, u32 Int_Id);
+void XScuGic_Disable(XScuGic *InstancePtr, u32 Int_Id);
+
+s32  XScuGic_CfgInitialize(XScuGic *InstancePtr, XScuGic_Config *ConfigPtr,
+							u32 EffectiveAddr);
+
+s32  XScuGic_SoftwareIntr(XScuGic *InstancePtr, u32 Int_Id, u32 Cpu_Id);
+
+void XScuGic_GetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+void XScuGic_SetPriorityTriggerType(XScuGic *InstancePtr, u32 Int_Id,
+					u8 Priority, u8 Trigger);
+void XScuGic_InterruptMaptoCpu(XScuGic *InstancePtr, u8 Cpu_Id, u32 Int_Id);
+/*
+ * Initialization functions in xscugic_sinit.c
+ */
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId);
+
+/*
+ * Interrupt functions in xscugic_intr.c
+ */
+void XScuGic_InterruptHandler(XScuGic *InstancePtr);
+
+/*
+ * Self-test functions in xscugic_selftest.c
+ */
+s32  XScuGic_SelfTest(XScuGic *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_g.c
new file mode 100644
index 000000000..2457f6b23
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_g.c
@@ -0,0 +1,56 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xscugic.h"
+
+/*
+* The configuration table for devices
+*/
+
+XScuGic_Config XScuGic_ConfigTable[] =
+{
+	{
+		XPAR_PSU_RCPU_GIC_DEVICE_ID,
+		XPAR_PSU_RCPU_GIC_BASEADDR,
+		XPAR_PSU_RCPU_GIC_DIST_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.c
new file mode 100644
index 000000000..626779720
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.c
@@ -0,0 +1,570 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* This file contains low-level driver functions that can be used to access the
+* device.  The user should refer to the hardware device specification for more
+* details of the device operation.
+* These routines are used when the user does not want to create an instance of
+* XScuGic structure but still wants to use the ScuGic device. Hence the
+* routines provided here take device id or scugic base address as arguments.
+* Separate static versions of DistInit and CPUInit are provided to implement
+* the low level driver routines.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.01a sdm  07/18/11 First release
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+*					  Added support to direct interrupts to the appropriate CPU.
+*			  Earlier interrupts were directed to CPU1 (hard coded). Now
+*			  depending upon the CPU selected by the user (xparameters.h),
+*			  interrupts will be directed to the relevant CPU.
+*			  This fixes CR 699688.
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved functions
+*			  XScuGic_SetPriTrigTypeByDistAddr and
+*             XScuGic_GetPriTrigTypeByDistAddr here from xscugic.c
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+static void DistInit(XScuGic_Config *Config, u32 CpuID);
+static void CPUInit(XScuGic_Config *Config);
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_XSCUGIC_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* DistInit initializes the distributor of the GIC. The
+* initialization entails:
+*
+* - Write the trigger mode, priority and target CPU
+* - All interrupt sources are disabled
+* - Enable the distributor
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+* @param	CpuID is the Cpu ID to be initialized.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void DistInit(XScuGic_Config *Config, u32 CpuID)
+{
+	u32 Int_Id;
+	u32 LocalCpuID = CpuID;
+
+#if USE_AMP==1
+	#warning "Building GIC for AMP"
+
+	/*
+	 * The distrubutor should not be initialized by FreeRTOS in the case of
+	 * AMP -- it is assumed that Linux is the master of this device in that
+	 * case.
+	 */
+	return;
+#endif
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET, 0U);
+
+	/*
+	 * Set the security domains in the int_security registers for non-secure
+	 * interrupts. All are secure, so leave at the default. Set to 1 for
+	 * non-secure interrupts.
+	 */
+
+
+	/*
+	 * For the Shared Peripheral Interrupts INT_ID[MAX..32], set:
+	 */
+
+	/*
+	 * 1. The trigger mode in the int_config register
+	 * Only write to the SPI interrupts, so start at 32
+	 */
+	for (Int_Id = 32U; Int_IdDistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id), 0U);
+	}
+
+
+#define DEFAULT_PRIORITY	0xa0a0a0a0U
+	for (Int_Id = 0U; Int_IdDistBaseAddress,
+				XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+				DEFAULT_PRIORITY);
+	}
+
+	for (Int_Id = 32U; Int_IdDistBaseAddress,
+				XSCUGIC_SPI_TARGET_OFFSET_CALC(Int_Id), LocalCpuID);
+	}
+
+	for (Int_Id = 0U; Int_IdDistBaseAddress,
+		XSCUGIC_EN_DIS_OFFSET_CALC(XSCUGIC_DISABLE_OFFSET,
+		Int_Id),
+		0xFFFFFFFFU);
+
+	}
+
+	XScuGic_WriteReg(Config->DistBaseAddress, XSCUGIC_DIST_EN_OFFSET,
+						XSCUGIC_EN_INT_MASK);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CPUInit initializes the CPU Interface of the GIC. The initialization entails:
+*
+* - Set the priority of the CPU.
+* - Enable the CPU interface
+*
+* @param	ConfigPtr is a pointer to a config table for the particular
+*		device this driver is associated with.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+static void CPUInit(XScuGic_Config *Config)
+{
+	/*
+	 * Program the priority mask of the CPU using the Priority mask
+	 * register
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CPU_PRIOR_OFFSET,
+									0xF0U);
+
+	/*
+	 * If the CPU operates in both security domains, set parameters in the
+	 * control_s register.
+	 * 1. Set FIQen=1 to use FIQ for secure interrupts,
+	 * 2. Program the AckCtl bit
+	 * 3. Program the SBPR bit to select the binary pointer behavior
+	 * 4. Set EnableS = 1 to enable secure interrupts
+	 * 5. Set EnbleNS = 1 to enable non secure interrupts
+	 */
+
+	/*
+	 * If the CPU operates only in the secure domain, setup the
+	 * control_s register.
+	 * 1. Set FIQen=1,
+	 * 2. Set EnableS=1, to enable the CPU interface to signal secure .
+	 * interrupts Only enable the IRQ output unless secure interrupts
+	 * are needed.
+	 */
+	XScuGic_WriteReg(Config->CpuBaseAddress, XSCUGIC_CONTROL_OFFSET, 0x07U);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* CfgInitialize a specific interrupt controller instance/driver. The
+* initialization entails:
+*
+* - Initialize fields of the XScuGic structure
+* - Initial vector table with stub function calls
+* - All interrupt sources are disabled
+*
+* @param InstancePtr is a pointer to the XScuGic instance to be worked on.
+* @param ConfigPtr is a pointer to a config table for the particular device
+*        this driver is associated with.
+* @param EffectiveAddr is the device base address in the virtual memory address
+*        space. The caller is responsible for keeping the address mapping
+*        from EffectiveAddr to the device physical base address unchanged
+*        once this function is invoked. Unexpected errors may occur if the
+*        address mapping changes after this function is called. If address
+*        translation is not used, use Config->BaseAddress for this parameters,
+*        passing the physical address instead.
+*
+* @return
+*
+* - XST_SUCCESS if initialization was successful
+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+s32 XScuGic_DeviceInitialize(u32 DeviceId)
+{
+	XScuGic_Config *Config;
+	u32 Cpu_Id = (u32)XPAR_CPU_ID + (u32)1;
+
+	Config = &XScuGic_ConfigTable[(u32 )DeviceId];
+
+	DistInit(Config, Cpu_Id);
+
+	CPUInit(Config);
+
+	return XST_SUCCESS;
+}
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the
+* interrupt.Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+* @param	DeviceId is the unique identifier for the ScuGic device.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_DeviceInterruptHandler(void *DeviceId)
+{
+
+	u32 InterruptID;
+	u32 IntIDFull;
+	XScuGic_VectorTableEntry *TablePtr;
+	XScuGic_Config *CfgPtr;
+
+	CfgPtr = &XScuGic_ConfigTable[(INTPTR )DeviceId];
+
+	/*
+	 * Read the int_ack register to identify the highest priority
+	 * interrupt ID and make sure it is valid. Reading Int_Ack will
+	 * clear the interrupt in the GIC.
+	 */
+	IntIDFull = XScuGic_ReadReg(CfgPtr->CpuBaseAddress, XSCUGIC_INT_ACK_OFFSET);
+	InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+	if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	}
+
+	/*
+	 * If the interrupt is shared, do some locking here if there are
+	 * multiple processors.
+	 */
+	/*
+	 * If pre-eption is required:
+	 * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	 * interrupts or the F bit for secure interrupts
+	 */
+
+	/*
+	 * If we need to change security domains, issue a SMC instruction here.
+	 */
+
+	/*
+	 * Execute the ISR. Jump into the Interrupt service routine based on
+	 * the IRQSource. A software trigger is cleared by the ACK.
+	 */
+	TablePtr = &(CfgPtr->HandlerTable[InterruptID]);
+	if(TablePtr != NULL) {
+		TablePtr->Handler(TablePtr->CallBackRef);
+	}
+
+IntrExit:
+	/*
+	 * Write to the EOI register, we are all done here.
+	 * Let this function return, the boot code will restore the stack.
+	 */
+	XScuGic_WriteReg(CfgPtr->CpuBaseAddress, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	/*
+	 * Return from the interrupt. Change security domains could happen
+	 * here.
+	 */
+}
+
+/*****************************************************************************/
+/**
+*
+* Register a handler function for a specific interrupt ID.  The vector table
+* of the interrupt controller is updated, overwriting any previous handler.
+* The handler function will be called when an interrupt occurs for the given
+* interrupt ID.
+*
+* @param	BaseAddress is the CPU Interface Register base address of the
+*		interrupt controller whose vector table will be modified.
+* @param	InterruptId is the interrupt ID to be associated with the input
+*		handler.
+* @param	Handler is the function pointer that will be added to
+*		the vector table for the given interrupt ID.
+* @param	CallBackRef is the argument that will be passed to the new
+*		handler function when it is called. This is user-specific.
+*
+* @return	None.
+*
+* @note
+*
+* Note that this function has no effect if the input base address is invalid.
+*
+******************************************************************************/
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler IntrHandler, void *CallBackRef)
+{
+	XScuGic_Config *CfgPtr;
+	CfgPtr = LookupConfigByBaseAddress(BaseAddress);
+
+	if(CfgPtr != NULL) {
+		if( IntrHandler != NULL) {
+			CfgPtr->HandlerTable[InterruptID].Handler = IntrHandler;
+		}
+		if( CallBackRef != NULL) {
+			CfgPtr->HandlerTable[InterruptID].CallBackRef = CallBackRef;
+		}
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the CPU interface base address of
+* the device. A table contains the configuration info for each device in the
+* system.
+*
+* @param	CpuBaseAddress is the CPU Interface Register base address.
+*
+* @return 	A pointer to the configuration structure for the specified
+*		device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+static XScuGic_Config *LookupConfigByBaseAddress(u32 CpuBaseAddress)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].CpuBaseAddress ==
+				CpuBaseAddress) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
+
+/****************************************************************************/
+/**
+* Sets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is the new priority for the IRQ source. 0 is highest
+* 			priority, 0xF8 (248) is lowest. There are 32 priority levels
+*			supported with a step of 8. Hence the supported priorities are
+*			0, 8, 16, 32, 40 ..., 248.
+* @param	Trigger is the new trigger type for the IRQ source.
+* Each bit pair describes the configuration for an INT_ID.
+* SFI    Read Only    b10 always
+* PPI    Read Only    depending on how the PPIs are configured.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive
+* SPI                LSB is read only.
+*                    b01    Active HIGH level sensitive
+*                    b11 Rising edge sensitive/
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_SetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 Priority, u8 Trigger)
+{
+	u32 RegValue;
+	u8 LocalPriority = Priority;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Trigger <= XSCUGIC_INT_CFG_MASK);
+	Xil_AssertVoid(LocalPriority <= XSCUGIC_MAX_INTR_PRIO_VAL);
+
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * The priority bits are Bits 7 to 3 in GIC Priority Register. This
+	 * means the number of priority levels supported are 32 and they are
+	 * in steps of 8. The priorities can be 0, 8, 16, 32, 48, ... etc.
+	 * The lower order 3 bits are masked before putting it in the register.
+	 */
+	LocalPriority = LocalPriority & XSCUGIC_INTR_PRIO_MASK;
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_PRIORITY_MASK << ((Int_Id%4U)*8U));
+	RegValue |= (u32)LocalPriority << ((Int_Id%4U)*8U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id),
+					RegValue);
+	/*
+	 * Determine the register to write to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+			XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue &= ~(XSCUGIC_INT_CFG_MASK << ((Int_Id%16U)*2U));
+	RegValue |= (u32)Trigger << ((Int_Id%16U)*2U);
+
+	/*
+	 * Write the value back to the register.
+	 */
+	XScuGic_WriteReg(DistBaseAddress, XSCUGIC_INT_CFG_OFFSET_CALC(Int_Id),
+				RegValue);
+}
+
+/****************************************************************************/
+/**
+* Gets the interrupt priority and trigger type for the specificd IRQ source.
+*
+* @param	BaseAddr is the device base address
+* @param	Int_Id is the IRQ source number to modify
+* @param	Priority is a pointer to the value of the priority of the IRQ
+*		source. This is a return value.
+* @param	Trigger is pointer to the value of the trigger of the IRQ
+*		source. This is a return value.
+*
+* @return	None.
+*
+* @note		This API has the similar functionality of XScuGic_GetPriority
+*	        TriggerType() and should be used when there is no InstancePtr.
+*
+*****************************************************************************/
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger)
+{
+	u32 RegValue;
+
+	Xil_AssertVoid(Int_Id < XSCUGIC_MAX_NUM_INTR_INPUTS);
+	Xil_AssertVoid(Priority != NULL);
+	Xil_AssertVoid(Trigger != NULL);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_PRIORITY_OFFSET_CALC(Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%4U)*8U);
+	*Priority = (u8)(RegValue & XSCUGIC_PRIORITY_MASK);
+
+	/*
+	 * Determine the register to read to using the Int_Id.
+	 */
+	RegValue = XScuGic_ReadReg(DistBaseAddress,
+	    XSCUGIC_INT_CFG_OFFSET_CALC (Int_Id));
+
+	/*
+	 * Shift and Mask the correct bits for the priority and trigger in the
+	 * register
+	 */
+	RegValue = RegValue >> ((Int_Id%16U)*2U);
+
+	*Trigger = (u8)(RegValue & XSCUGIC_INT_CFG_MASK);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.h
new file mode 100644
index 000000000..5eaa633e3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_hw.h
@@ -0,0 +1,642 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_hw.h
+* @addtogroup scugic_v3_1
+* @{
+*
+* This header file contains identifiers and HW access functions (or
+* macros) that can be used to access the device.  The user should refer to the
+* hardware device specification for more details of the device operation.
+* The driver functions/APIs are defined in xscugic.h.
+*
+* This GIC device has two parts, a distributor and CPU interface(s). Each part
+* has separate register definition sections.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 "xil_exception.h" added as include.
+*		      Macros XScuGic_EnableIntr and XScuGic_DisableIntr are
+*		      added to enable or disable interrupts based on
+*		      Distributor Register base address. Normally users use
+*		      XScuGic instance and call XScuGic_Enable or
+*		      XScuGic_Disable to enable/disable interrupts. These
+*		      new macros are provided when user does not want to
+*		      use an instance pointer but still wants to enable or
+*		      disable interrupts.
+*		      Function prototypes for functions (present in newly
+*		      added file xscugic_hw.c) are added.
+* 1.03a srt  02/27/13 Moved Offset calculation macros from *_hw.c (CR
+*		      702687).
+* 1.04a hk   05/04/13 Fix for CR#705621. Moved function prototypes
+*		      XScuGic_SetPriTrigTypeByDistAddr and
+*         	      XScuGic_GetPriTrigTypeByDistAddr here from xscugic.h
+* 3.0	pkp  12/09/14 changed XSCUGIC_MAX_NUM_INTR_INPUTS for
+*		      Zynq Ultrascale Mp
+* 3.0   kvn  02/13/14 Modified code for MISRA-C:2012 compliance.
+* 3.2	pkp  11/09/15 Corrected the interrupt processsor target mask value
+*					  for CPU interface 2 i.e. XSCUGIC_SPI_CPU2_MASK
+* 

+*
+******************************************************************************/
+
+#ifndef XSCUGIC_HW_H /* prevent circular inclusions */
+#define XSCUGIC_HW_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xil_exception.h"
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * The maximum number of interrupts supported by the hardware.
+ */
+#ifdef __ARM_NEON__
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	95U /* Maximum number of interrupt defined by Zynq */
+#else
+#define XSCUGIC_MAX_NUM_INTR_INPUTS    	195U /* Maximum number of interrupt defined by Zynq Ultrascale Mp */
+#endif
+
+/*
+ * The maximum priority value that can be used in the GIC.
+ */
+#define XSCUGIC_MAX_INTR_PRIO_VAL    	248U
+#define XSCUGIC_INTR_PRIO_MASK			0x000000F8U
+
+/** @name Distributor Interface Register Map
+ *
+ * Define the offsets from the base address for all Distributor registers of
+ * the interrupt controller, some registers may be reserved in the hardware
+ * device.
+ * @{
+ */
+#define XSCUGIC_DIST_EN_OFFSET		0x00000000U /**< Distributor Enable
+							Register */
+#define XSCUGIC_IC_TYPE_OFFSET		0x00000004U /**< Interrupt Controller
+							Type Register */
+#define XSCUGIC_DIST_IDENT_OFFSET	0x00000008U /**< Implementor ID
+							Register */
+#define XSCUGIC_SECURITY_OFFSET		0x00000080U /**< Interrupt Security
+							Register */
+#define XSCUGIC_ENABLE_SET_OFFSET	0x00000100U /**< Enable Set
+							Register */
+#define XSCUGIC_DISABLE_OFFSET		0x00000180U /**< Enable Clear Register */
+#define XSCUGIC_PENDING_SET_OFFSET	0x00000200U /**< Pending Set
+							Register */
+#define XSCUGIC_PENDING_CLR_OFFSET	0x00000280U /**< Pending Clear
+							Register */
+#define XSCUGIC_ACTIVE_OFFSET		0x00000300U /**< Active Status Register */
+#define XSCUGIC_PRIORITY_OFFSET		0x00000400U /**< Priority Level Register */
+#define XSCUGIC_SPI_TARGET_OFFSET	0x00000800U /**< SPI Target
+							Register 0x800-0x8FB */
+#define XSCUGIC_INT_CFG_OFFSET		0x00000C00U /**< Interrupt Configuration
+							Register 0xC00-0xCFC */
+#define XSCUGIC_PPI_STAT_OFFSET		0x00000D00U /**< PPI Status Register */
+#define XSCUGIC_SPI_STAT_OFFSET		0x00000D04U /**< SPI Status Register
+							0xd04-0xd7C */
+#define XSCUGIC_AHB_CONFIG_OFFSET	0x00000D80U /**< AHB Configuration
+							Register */
+#define XSCUGIC_SFI_TRIG_OFFSET		0x00000F00U /**< Software Triggered
+							Interrupt Register */
+#define XSCUGIC_PERPHID_OFFSET		0x00000FD0U /**< Peripheral ID Reg */
+#define XSCUGIC_PCELLID_OFFSET		0x00000FF0U /**< Pcell ID Register */
+/* @} */
+
+/** @name  Distributor Enable Register
+ * Controls if the distributor response to external interrupt inputs.
+ * @{
+ */
+#define XSCUGIC_EN_INT_MASK		0x00000001U /**< Interrupt In Enable */
+/* @} */
+
+/** @name  Interrupt Controller Type Register
+ * @{
+ */
+#define XSCUGIC_LSPI_MASK	0x0000F800U /**< Number of Lockable
+						Shared Peripheral
+						Interrupts*/
+#define XSCUGIC_DOMAIN_MASK	0x00000400U /**< Number os Security domains*/
+#define XSCUGIC_CPU_NUM_MASK	0x000000E0U /**< Number of CPU Interfaces */
+#define XSCUGIC_NUM_INT_MASK	0x0000001FU /**< Number of Interrupt IDs */
+/* @} */
+
+/** @name  Implementor ID Register
+ * Implementor and revision information.
+ * @{
+ */
+#define XSCUGIC_REV_MASK	0x00FFF000U /**< Revision Number */
+#define XSCUGIC_IMPL_MASK	0x00000FFFU /**< Implementor */
+/* @} */
+
+/** @name  Interrupt Security Registers
+ * Each bit controls the security level of an interrupt, either secure or non
+ * secure. These registers can only be accessed using secure read and write.
+ * There are registers for each of the CPU interfaces at offset 0x080.  A
+ * register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x084.
+ * @{
+ */
+#define XSCUGIC_INT_NS_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Set Register
+ * Each bit controls the enabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Use the ENABLE_CLR register to set a
+ * bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x100. With up
+ * to 8 registers aliased to the same address. A register set for the SPI
+ * interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x104.
+ * @{
+ */
+#define XSCUGIC_INT_EN_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Enable Clear Register
+ * Each bit controls the disabling of an interrupt, a 0 is disabled, a 1 is
+ * enabled. Writing a 0 has no effect. Writing a 1 disables an interrupt and
+ * sets the corresponding bit to 0.
+ * There are registers for each of the CPU interfaces at offset 0x180. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x184.
+ * @{
+ */
+#define XSCUGIC_INT_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Set Register
+ * Each bit controls the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1 sets
+ * an interrupt to the pending state.
+ * There are registers for each of the CPU interfaces at offset 0x200. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x204.
+ * @{
+ */
+#define XSCUGIC_PEND_SET_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Pending Clear Register
+ * Each bit can clear the Pending or Active and Pending state of an interrupt, a
+ * 0 is not pending, a 1 is pending. Writing a 0 has no effect. Writing a 1
+ * clears the pending state of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x280. With up
+ * to 8 registers aliased to the same address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x284.
+ * @{
+ */
+#define XSCUGIC_PEND_CLR_MASK	0x00000001U /**< Each bit corresponds to an
+						INT_ID */
+/* @} */
+
+/** @name  Active Status Register
+ * Each bit provides the Active status of an interrupt, a
+ * 0 is not Active, a 1 is Active. This is a read only register.
+ * There are registers for each of the CPU interfaces at offset 0x300. With up
+ * to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 32 of these registers staring at location 0x380.
+ * @{
+ */
+#define XSCUGIC_ACTIVE_MASK	0x00000001U /**< Each bit corresponds to an
+					      INT_ID */
+/* @} */
+
+/** @name  Priority Level Register
+ * Each byte in a Priority Level Register sets the priority level of an
+ * interrupt. Reading the register provides the priority level of an interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x400 through
+ * 0x41C. With up to 8 registers aliased to each address.
+ * 0 is highest priority, 0xFF is lowest.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x420.
+ * @{
+ */
+#define XSCUGIC_PRIORITY_MASK	0x000000FFU /**< Each Byte corresponds to an
+						INT_ID */
+#define XSCUGIC_PRIORITY_MAX	0x000000FFU /**< Highest value of a priority
+						actually the lowest priority*/
+/* @} */
+
+/** @name  SPI Target Register 0x800-0x8FB
+ * Each byte references a separate SPI and programs which of the up to 8 CPU
+ * interfaces are sent a Pending interrupt.
+ * There are registers for each of the CPU interfaces at offset 0x800 through
+ * 0x81C. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0x820.
+ *
+ * This driver does not support multiple CPU interfaces. These are included
+ * for complete documentation.
+ * @{
+ */
+#define XSCUGIC_SPI_CPU7_MASK	0x00000080U /**< CPU 7 Mask*/
+#define XSCUGIC_SPI_CPU6_MASK	0x00000040U /**< CPU 6 Mask*/
+#define XSCUGIC_SPI_CPU5_MASK	0x00000020U /**< CPU 5 Mask*/
+#define XSCUGIC_SPI_CPU4_MASK	0x00000010U /**< CPU 4 Mask*/
+#define XSCUGIC_SPI_CPU3_MASK	0x00000008U /**< CPU 3 Mask*/
+#define XSCUGIC_SPI_CPU2_MASK	0x00000004U /**< CPU 2 Mask*/
+#define XSCUGIC_SPI_CPU1_MASK	0x00000002U /**< CPU 1 Mask*/
+#define XSCUGIC_SPI_CPU0_MASK	0x00000001U /**< CPU 0 Mask*/
+/* @} */
+
+/** @name  Interrupt Configuration Register 0xC00-0xCFC
+ * The interrupt configuration registers program an SFI to be active HIGH level
+ * sensitive or rising edge sensitive.
+ * Each bit pair describes the configuration for an INT_ID.
+ * SFI    Read Only    b10 always
+ * PPI    Read Only    depending on how the PPIs are configured.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive
+ * SPI                LSB is read only.
+ *                    b01    Active HIGH level sensitive
+ *                    b11 Rising edge sensitive/
+ * There are registers for each of the CPU interfaces at offset 0xC00 through
+ * 0xC04. With up to 8 registers aliased to each address.
+ * A register set for the SPI interrupts is available to all CPU interfaces.
+ * There are up to 255 of these registers staring at location 0xC08.
+ * @{
+ */
+#define XSCUGIC_INT_CFG_MASK    0x00000003U    /**< */
+/* @} */
+
+/** @name  PPI Status Register
+ * Enables an external AMBA master to access the status of the PPI inputs.
+ * A CPU can only read the status of its local PPI signals and cannot read the
+ * status for other CPUs.
+ * This register is aliased for each CPU interface.
+ * @{
+ */
+#define XSCUGIC_PPI_C15_MASK	0x00008000U    /**< PPI Status */
+#define XSCUGIC_PPI_C14_MASK	0x00004000U    /**< PPI Status */
+#define XSCUGIC_PPI_C13_MASK	0x00002000U    /**< PPI Status */
+#define XSCUGIC_PPI_C12_MASK	0x00001000U    /**< PPI Status */
+#define XSCUGIC_PPI_C11_MASK	0x00000800U    /**< PPI Status */
+#define XSCUGIC_PPI_C10_MASK	0x00000400U    /**< PPI Status */
+#define XSCUGIC_PPI_C09_MASK	0x00000200U    /**< PPI Status */
+#define XSCUGIC_PPI_C08_MASK	0x00000100U    /**< PPI Status */
+#define XSCUGIC_PPI_C07_MASK	0x00000080U    /**< PPI Status */
+#define XSCUGIC_PPI_C06_MASK	0x00000040U    /**< PPI Status */
+#define XSCUGIC_PPI_C05_MASK	0x00000020U    /**< PPI Status */
+#define XSCUGIC_PPI_C04_MASK	0x00000010U    /**< PPI Status */
+#define XSCUGIC_PPI_C03_MASK	0x00000008U    /**< PPI Status */
+#define XSCUGIC_PPI_C02_MASK	0x00000004U    /**< PPI Status */
+#define XSCUGIC_PPI_C01_MASK	0x00000002U    /**< PPI Status */
+#define XSCUGIC_PPI_C00_MASK	0x00000001U    /**< PPI Status */
+/* @} */
+
+/** @name  SPI Status Register 0xd04-0xd7C
+ * Enables an external AMBA master to access the status of the SPI inputs.
+ * There are up to 63 registers if the maximum number of SPI inputs are
+ * configured.
+ * @{
+ */
+#define XSCUGIC_SPI_N_MASK    0x00000001U    /**< Each bit corresponds to an SPI
+					     input */
+/* @} */
+
+/** @name  AHB Configuration Register
+ * Provides the status of the CFGBIGEND input signal and allows the endianess
+ * of the GIC to be set.
+ * @{
+ */
+#define XSCUGIC_AHB_END_MASK       0x00000004U    /**< 0-GIC uses little Endian,
+                                                  1-GIC uses Big Endian */
+#define XSCUGIC_AHB_ENDOVR_MASK    0x00000002U    /**< 0-Uses CFGBIGEND control,
+                                                  1-use the AHB_END bit */
+#define XSCUGIC_AHB_TIE_OFF_MASK   0x00000001U    /**< State of CFGBIGEND */
+
+/* @} */
+
+/** @name  Software Triggered Interrupt Register
+ * Controls issueing of software interrupts.
+ * @{
+ */
+#define XSCUGIC_SFI_SELFTRIG_MASK	0x02010000U
+#define XSCUGIC_SFI_TRIG_TRGFILT_MASK    0x03000000U    /**< Target List filter
+                                                            b00-Use the target List
+                                                            b01-All CPUs except requester
+                                                            b10-To Requester
+                                                            b11-reserved */
+#define XSCUGIC_SFI_TRIG_CPU_MASK	0x00FF0000U    /**< CPU Target list */
+#define XSCUGIC_SFI_TRIG_SATT_MASK	0x00008000U    /**< 0= Use a secure interrupt */
+#define XSCUGIC_SFI_TRIG_INTID_MASK	0x0000000FU    /**< Set to the INTID
+                                                        signaled to the CPU*/
+/* @} */
+
+/** @name CPU Interface Register Map
+ *
+ * Define the offsets from the base address for all CPU registers of the
+ * interrupt controller, some registers may be reserved in the hardware device.
+ * @{
+ */
+#define XSCUGIC_CONTROL_OFFSET		0x00000000U /**< CPU Interface Control
+							Register */
+#define XSCUGIC_CPU_PRIOR_OFFSET	0x00000004U /**< Priority Mask Reg */
+#define XSCUGIC_BIN_PT_OFFSET		0x00000008U /**< Binary Point Register */
+#define XSCUGIC_INT_ACK_OFFSET		0x0000000CU /**< Interrupt ACK Reg */
+#define XSCUGIC_EOI_OFFSET		0x00000010U /**< End of Interrupt Reg */
+#define XSCUGIC_RUN_PRIOR_OFFSET	0x00000014U /**< Running Priority Reg */
+#define XSCUGIC_HI_PEND_OFFSET		0x00000018U /**< Highest Pending Interrupt
+							Register */
+#define XSCUGIC_ALIAS_BIN_PT_OFFSET	0x0000001CU /**< Aliased non-Secure
+						        Binary Point Register */
+
+/**<  0x00000020 to 0x00000FBC are reserved and should not be read or written
+ * to. */
+/* @} */
+
+
+/** @name Control Register
+ * CPU Interface Control register definitions
+ * All bits are defined here although some are not available in the non-secure
+ * mode.
+ * @{
+ */
+#define XSCUGIC_CNTR_SBPR_MASK	0x00000010U    /**< Secure Binary Pointer,
+                                                 0=separate registers,
+                                                 1=both use bin_pt_s */
+#define XSCUGIC_CNTR_FIQEN_MASK	0x00000008U    /**< Use nFIQ_C for secure
+                                                  interrupts,
+                                                  0= use IRQ for both,
+                                                  1=Use FIQ for secure, IRQ for non*/
+#define XSCUGIC_CNTR_ACKCTL_MASK	0x00000004U    /**< Ack control for secure or non secure */
+#define XSCUGIC_CNTR_EN_NS_MASK		0x00000002U    /**< Non Secure enable */
+#define XSCUGIC_CNTR_EN_S_MASK		0x00000001U    /**< Secure enable, 0=Disabled, 1=Enabled */
+/* @} */
+
+/** @name Priority Mask Register
+ * Priority Mask register definitions
+ * The CPU interface does not send interrupt if the level of the interrupt is
+ * lower than the level of the register.
+ * @{
+ */
+/*#define XSCUGIC_PRIORITY_MASK		0x000000FFU*/   /**< All interrupts */
+/* @} */
+
+/** @name Binary Point Register
+ * Binary Point register definitions
+ * @{
+ */
+
+#define XSCUGIC_BIN_PT_MASK	0x00000007U  /**< Binary point mask value
+						Value  Secure  Non-secure
+						b000    0xFE    0xFF
+						b001    0xFC    0xFE
+						b010    0xF8    0xFC
+						b011    0xF0    0xF8
+						b100    0xE0    0xF0
+						b101    0xC0    0xE0
+						b110    0x80    0xC0
+						b111    0x00    0x80
+						*/
+/*@}*/
+
+/** @name Interrupt Acknowledge Register
+ * Interrupt Acknowledge register definitions
+ * Identifies the current Pending interrupt, and the CPU ID for software
+ * interrupts.
+ */
+#define XSCUGIC_ACK_INTID_MASK		0x000003FFU /**< Interrupt ID */
+#define XSCUGIC_CPUID_MASK		0x00000C00U /**< CPU ID */
+/* @} */
+
+/** @name End of Interrupt Register
+ * End of Interrupt register definitions
+ * Allows the CPU to signal the GIC when it completes an interrupt service
+ * routine.
+ */
+#define XSCUGIC_EOI_INTID_MASK		0x000003FFU /**< Interrupt ID */
+
+/* @} */
+
+/** @name Running Priority Register
+ * Running Priority register definitions
+ * Identifies the interrupt priority level of the highest priority active
+ * interrupt.
+ */
+#define XSCUGIC_RUN_PRIORITY_MASK	0x000000FFU    /**< Interrupt Priority */
+/* @} */
+
+/*
+ * Highest Pending Interrupt register definitions
+ * Identifies the interrupt priority of the highest priority pending interupt
+ */
+#define XSCUGIC_PEND_INTID_MASK		0x000003FFU /**< Pending Interrupt ID */
+/*#define XSCUGIC_CPUID_MASK		0x00000C00U */	 /**< CPU ID */
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Configuration Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_INT_CFG_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_INT_CFG_OFFSET + (((InterruptID)/16U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Priority Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_PRIORITY_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_PRIORITY_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the SPI Target Register offset for an interrupt id.
+*
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_SPI_TARGET_OFFSET_CALC(InterruptID) \
+	((u32)XSCUGIC_SPI_TARGET_OFFSET + (((InterruptID)/4U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the Interrupt Clear-Enable Register offset for an interrupt ID
+*
+* @param	Register is the register offset for the clear/enable bank.
+* @param	InterruptID is the interrupt number.
+*
+* @return	The 32-bit value of the offset
+*
+* @note
+*
+*****************************************************************************/
+#define XSCUGIC_EN_DIS_OFFSET_CALC(Register, InterruptID) \
+		((Register) + (((InterruptID)/32U) * 4U))
+
+/****************************************************************************/
+/**
+*
+* Read the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note
+* C-style signature:
+*    u32 XScuGic_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XScuGic_ReadReg(BaseAddress, RegOffset) \
+	(Xil_In32((BaseAddress) + (RegOffset)))
+
+
+/****************************************************************************/
+/**
+*
+* Write the given Intc register.
+*
+* @param	BaseAddress is the base address of the device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*    void XScuGic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XScuGic_WriteReg(BaseAddress, RegOffset, Data) \
+	(Xil_Out32(((BaseAddress) + (RegOffset)), ((u32)(Data))))
+
+
+/****************************************************************************/
+/**
+*
+* Enable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_EnableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_EnableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_ENABLE_SET_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+/****************************************************************************/
+/**
+*
+* Disable specific interrupt(s) in the interrupt controller.
+*
+* @param	DistBaseAddress is the Distributor Register base address of the
+*		device
+* @param	Int_Id is the ID of the interrupt source and should be in the
+*		range of 0 to XSCUGIC_MAX_NUM_INTR_INPUTS - 1
+*
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XScuGic_DisableIntr(u32 DistBaseAddress, u32 Int_Id)
+*
+*****************************************************************************/
+#define XScuGic_DisableIntr(DistBaseAddress, Int_Id) \
+	XScuGic_WriteReg((DistBaseAddress), \
+			 XSCUGIC_DISABLE_OFFSET + (((Int_Id) / 32U) * 4U), \
+			 (0x00000001U << ((Int_Id) % 32U)))
+
+
+/************************** Function Prototypes ******************************/
+
+void XScuGic_DeviceInterruptHandler(void *DeviceId);
+s32  XScuGic_DeviceInitialize(u32 DeviceId);
+void XScuGic_RegisterHandler(u32 BaseAddress, s32 InterruptID,
+			     Xil_InterruptHandler Handler, void *CallBackRef);
+void XScuGic_SetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+                                        u8 Priority, u8 Trigger);
+void XScuGic_GetPriTrigTypeByDistAddr(u32 DistBaseAddress, u32 Int_Id,
+					u8 *Priority, u8 *Trigger);
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_intr.c
new file mode 100644
index 000000000..d05a51c5e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_intr.c
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_intr.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* This file contains the interrupt processing for the driver for the Xilinx
+* Interrupt Controller.  The interrupt processing is partitioned separately such
+* that users are not required to use the provided interrupt processing.  This
+* file requires other files of the driver to be linked in also.
+*
+* The interrupt handler, XScuGic_InterruptHandler, uses an input argument which
+* is an instance pointer to an interrupt controller driver such that multiple
+* interrupt controllers can be supported.  This handler requires the calling
+* function to pass it the appropriate argument, so another level of indirection
+* may be required.
+*
+* The interrupt processing may be used by connecting the interrupt handler to
+* the interrupt system.  The handler does not save and restore the processor
+* context but only handles the processing of the Interrupt Controller. The user
+* is encouraged to supply their own interrupt handler when performance tuning is
+* deemed necessary.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 1.01a sdm  11/09/11 XScuGic_InterruptHandler has changed correspondingly
+*		      since the HandlerTable has now moved to XScuGic_Config.
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+* @internal
+*
+* This driver assumes that the context of the processor has been saved prior to
+* the calling of the Interrupt Controller interrupt handler and then restored
+* after the handler returns. This requires either the running RTOS to save the
+* state of the machine or that a wrapper be used as the destination of the
+* interrupt vector to save the state of the processor and restore the state
+* after the interrupt handler returns.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+* This function is the primary interrupt handler for the driver.  It must be
+* connected to the interrupt source such that it is called when an interrupt of
+* the interrupt controller is active. It will resolve which interrupts are
+* active and enabled and call the appropriate interrupt handler. It uses
+* the Interrupt Type information to determine when to acknowledge the interrupt.
+* Highest priority interrupts are serviced first.
+*
+* This function assumes that an interrupt vector table has been previously
+* initialized.  It does not verify that entries in the table are valid before
+* calling an interrupt handler.
+*
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XScuGic_InterruptHandler(XScuGic *InstancePtr)
+{
+
+	u32 InterruptID;
+	    u32 IntIDFull;
+	    XScuGic_VectorTableEntry *TablePtr;
+
+	    /* Assert that the pointer to the instance is valid
+	     */
+	    Xil_AssertVoid(InstancePtr != NULL);
+
+	    /*
+	     * Read the int_ack register to identify the highest priority interrupt ID
+	     * and make sure it is valid. Reading Int_Ack will clear the interrupt
+	     * in the GIC.
+	     */
+	    IntIDFull = XScuGic_CPUReadReg(InstancePtr, XSCUGIC_INT_ACK_OFFSET);
+	    InterruptID = IntIDFull & XSCUGIC_ACK_INTID_MASK;
+
+	    if(XSCUGIC_MAX_NUM_INTR_INPUTS < InterruptID){
+		goto IntrExit;
+	    }
+
+	    /*
+	     * If the interrupt is shared, do some locking here if there are multiple
+	     * processors.
+	     */
+	    /*
+	     * If pre-eption is required:
+	     * Re-enable pre-emption by setting the CPSR I bit for non-secure ,
+	     * interrupts or the F bit for secure interrupts
+	     */
+
+	    /*
+	     * If we need to change security domains, issue a SMC instruction here.
+	     */
+
+	    /*
+	     * Execute the ISR. Jump into the Interrupt service routine based on the
+	     * IRQSource. A software trigger is cleared by the ACK.
+	     */
+	    TablePtr = &(InstancePtr->Config->HandlerTable[InterruptID]);
+		if(TablePtr != NULL) {
+	        TablePtr->Handler(TablePtr->CallBackRef);
+		}
+
+	IntrExit:
+	    /*
+	     * Write to the EOI register, we are all done here.
+	     * Let this function return, the boot code will restore the stack.
+	     */
+	    XScuGic_CPUWriteReg(InstancePtr, XSCUGIC_EOI_OFFSET, IntIDFull);
+
+	    /*
+	     * Return from the interrupt. Change security domains could happen here.
+     */
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_selftest.c
new file mode 100644
index 000000000..47620d644
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_selftest.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_selftest.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* Contains diagnostic self-test functions for the XScuGic driver.
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+#define	XSCUGIC_PCELL_ID	0xB105F00DU
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. This test reads the ID registers and
+* compares them.
+*
+* @param	InstancePtr is a pointer to the XScuGic instance.
+*
+* @return
+*
+* 		- XST_SUCCESS if self-test is successful.
+* 		- XST_FAILURE if the self-test is not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32  XScuGic_SelfTest(XScuGic *InstancePtr)
+{
+	u32 RegValue1 = 0U;
+	u32 Index;
+	s32 Status;
+
+	/*
+	 * Assert the arguments
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the ID registers.
+	 */
+	for(Index=0U; Index<=3U; Index++) {
+		RegValue1 |= XScuGic_DistReadReg(InstancePtr,
+			((u32)XSCUGIC_PCELLID_OFFSET + (Index * 4U))) << (Index * 8U);
+	}
+
+	if(XSCUGIC_PCELL_ID != RegValue1){
+		Status = XST_FAILURE;
+	} else {
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_sinit.c
new file mode 100644
index 000000000..d30390ab8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/scugic_v3_2/src/xscugic_sinit.c
@@ -0,0 +1,103 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xscugic_sinit.c
+* @addtogroup scugic_v3_1
+* @{
+*
+* Contains static init functions for the XScuGic driver for the Interrupt
+* Controller. See xscugic.h for a detailed description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- --------------------------------------------------------
+* 1.00a drg  01/19/10 First release
+* 3.00  kvn  02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xparameters.h"
+#include "xscugic.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XScuGic_Config XScuGic_ConfigTable[XPAR_SCUGIC_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique identifier for a device.
+*
+* @return	A pointer to the XScuGic configuration structure for the
+*		specified device, or NULL if the device was not found.
+*
+* @note		None.
+*
+******************************************************************************/
+XScuGic_Config *XScuGic_LookupConfig(u16 DeviceId)
+{
+	XScuGic_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index=0U; Index < (u32)XPAR_SCUGIC_NUM_INSTANCES; Index++) {
+		if (XScuGic_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XScuGic_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XScuGic_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/Makefile
new file mode 100644
index 000000000..f57081af6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xsdps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling sdps"
+
+xsdps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xsdps_includes
+
+xsdps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.c
new file mode 100644
index 000000000..6425a791b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.c
@@ -0,0 +1,1507 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.c
+* @addtogroup sdps_v2_5
+* @{
+*
+* Contains the interface functions of the XSdPs driver.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk     12/13/13 Added check for arm to use sleep.h and its API's
+* 2.1   hk     04/18/14 Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+/*
+ * The header sleep.h and API usleep() can only be used with an arm design.
+ * MB_Sleep() is used for microblaze design.
+ */
+#if defined (__arm__) || defined (__aarch64__)
+
+#include "sleep.h"
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+#include "microblaze_sleep.h"
+
+#endif
+
+/************************** Constant Definitions *****************************/
+#define XSDPS_CMD8_VOL_PATTERN	0x1AAU
+#define XSDPS_RESPOCR_READY	0x80000000U
+#define XSDPS_ACMD41_HCS	0x40000000U
+#define XSDPS_ACMD41_3V3	0x00300000U
+#define XSDPS_CMD1_HIGH_VOL	0x00FF8000U
+#define XSDPS_CMD1_DUAL_VOL	0x00FF8010U
+#define HIGH_SPEED_SUPPORT	0x2U
+#define WIDTH_4_BIT_SUPPORT	0x4U
+#define SD_CLK_25_MHZ		25000000U
+#define SD_CLK_26_MHZ		26000000U
+#define EXT_CSD_DEVICE_TYPE_BYTE	196U
+#define EXT_CSD_DEVICE_TYPE_HIGH_SPEED			0x2U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED	0x4U
+#define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED	0x8U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200		0x10U
+#define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200		0x20U
+#define CSD_SPEC_VER_3		0x3U
+
+/* Note: Remove this once fixed */
+#define UHS_BROKEN
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd);
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+extern s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr);
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr);
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XSdPs instance such that the driver is ready to use.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific SD device. This function initializes an
+*		InstancePtr object for a specific device specified by the
+*		contents of Config.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, use
+*		ConfigPtr->Config.BaseAddress for this device.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_DEVICE_IS_STARTED if the device is already started.
+*		It must be stopped to re-initialize.
+*
+* @note		This function initializes the host controller.
+*		Initial clock of 400KHz is set.
+*		Voltage of 3.3V is selected as that is supported by host.
+*		Interrupts status is enabled and signal disabled by default.
+*		Default data direction is card to host and
+*		32 bit ADMA2 is selected. Defualt Block size is 512 bytes.
+*
+******************************************************************************/
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr)
+{
+	s32 Status;
+	u8 PowerLevel;
+	u8 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/* Set some default values. */
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+	InstancePtr->Config.CardDetect =  ConfigPtr->CardDetect;
+	InstancePtr->Config.WriteProtect =  ConfigPtr->WriteProtect;
+
+	/* Disable bus power */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_POWER_CTRL_OFFSET, 0U);
+
+	/* Delay to poweroff card */
+#if defined (__arm__) || defined (__aarch64__)
+
+    (void)sleep(1U);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+    MB_Sleep(1000U);
+
+#endif
+
+	/* "Software reset for all" is initiated */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_ALL_MASK);
+
+	/* Proceed with initialization only after reset is complete */
+	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_SW_RST_OFFSET);
+	while ((ReadReg & XSDPS_SWRST_ALL_MASK) != 0U) {
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+				XSDPS_SW_RST_OFFSET);
+	}
+	/* Host Controller version is read. */
+	 InstancePtr->HC_Version =
+			(u8)(XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL_VER_OFFSET) & XSDPS_HC_SPEC_VER_MASK);
+
+	/*
+	 * Read capabilities register and update it in Instance pointer.
+	 * It is sufficient to read this once on power on.
+	 */
+	InstancePtr->Host_Caps = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_CAPS_OFFSET);
+
+	/* Select voltage and enable bus power. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_POWER_CTRL_OFFSET,
+			XSDPS_PC_BUS_VSEL_3V3_MASK | XSDPS_PC_BUS_PWR_MASK);
+
+	/* Change the clock frequency to 400 KHz */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH ;
+	}
+
+    if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V3_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_3V3_MASK;
+	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_3V0_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_3V0_MASK;
+	} else if ((InstancePtr->Host_Caps & XSDPS_CAP_VOLT_1V8_MASK) != 0U) {
+		PowerLevel = XSDPS_PC_BUS_VSEL_1V8_MASK;
+	} else {
+		PowerLevel = 0U;
+	}
+
+	/* Select voltage based on capability and enable bus power. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_POWER_CTRL_OFFSET,
+			PowerLevel | XSDPS_PC_BUS_PWR_MASK);
+	/* Enable ADMA2 in 64bit mode. */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			XSDPS_HC_DMA_ADMA2_32_MASK);
+
+	/* Enable all interrupt status except card interrupt initially */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_EN_OFFSET,
+			XSDPS_NORM_INTR_ALL_MASK & (~XSDPS_INTR_CARD_MASK));
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_EN_OFFSET,
+			XSDPS_ERROR_INTR_ALL_MASK);
+
+	/* Disable all interrupt signals by default. */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_SIG_EN_OFFSET, 0x0U);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_SIG_EN_OFFSET, 0x0U);
+
+	/*
+	 * Transfer mode register - default value
+	 * DMA enabled, block count enabled, data direction card to host(read)
+	 */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_DAT_DIR_SEL_MASK);
+
+	/* Set block size to 512 by default */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, XSDPS_BLK_SIZE_512_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* SD initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+			   initialization cycle failed
+*
+* @note		This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD8 and ACDM41 are sent to identify voltage and
+*		high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	s32 Status;
+	u32 RespOCR;
+	u32 CSD[4];
+	u32 Arg;
+	u8 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/*
+			 * Check the present state register to make sure
+			 * card is inserted and detected by host controller
+			 */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, (u32)CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * CMD8; response expected
+	 * 0x1AA - Supply Voltage 2.7 - 3.6V and AA is pattern
+	 */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8,
+			XSDPS_CMD8_VOL_PATTERN, 0U);
+	if ((Status != XST_SUCCESS) && (Status != XSDPS_CT_ERROR)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (Status == XSDPS_CT_ERROR) {
+		 /* "Software reset for all" is initiated */
+		XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+				XSDPS_SWRST_CMD_LINE_MASK);
+
+		/* Proceed with initialization only after reset is complete */
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+						XSDPS_SW_RST_OFFSET);
+		while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+			ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+						XSDPS_SW_RST_OFFSET);
+		}
+	}
+
+	RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XSDPS_RESP0_OFFSET);
+	if (RespOCR != XSDPS_CMD8_VOL_PATTERN) {
+		InstancePtr->Card_Version = XSDPS_SD_VER_1_0;
+	}
+	else {
+		InstancePtr->Card_Version = XSDPS_SD_VER_2_0;
+	}
+
+	RespOCR = 0U;
+	/* Send ACMD41 while card is still busy with power up */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, 0U, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+        Arg = XSDPS_ACMD41_HCS | XSDPS_ACMD41_3V3 | (0x1FFU << 15U);
+		if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+		    Arg |= XSDPS_OCR_S18;
+		}
+
+		/* 0x40300000 - Host High Capacity support & 3.3V window */
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD41,
+				Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Response with card capacity */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/* Update HCS support flag based on card capacity response */
+	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+		InstancePtr->HCS = 1U;
+	}
+
+	/* There is no support to switch to 1.8V and use UHS mode on 1.0 silicon */
+#ifndef UHS_BROKEN
+    if ((RespOCR & XSDPS_OCR_S18) != 0U) {
+		InstancePtr->Switch1v8 = 1U;
+		Status = XSdPs_Switch_Voltage(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	}
+#endif
+
+	/* CMD2 for Card ID */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+	do {
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD3, 0U, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Relative card address is stored as the upper 16 bits
+		 * This is to avoid shifting when sending commands
+		 */
+		InstancePtr->RelCardAddr =
+				XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_RESP0_OFFSET) & 0xFFFF0000U;
+	} while (InstancePtr->RelCardAddr == 0U);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Initialize Card with Identification mode sequence
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) SD is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the
+*			   initialization cycle failed
+*
+*
+******************************************************************************/
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr) {
+	u8 Tmp;
+	u32 Cnt;
+	u32 PresentStateReg;
+	u32 CtrlReg;
+	u32 CSD[4];
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+static u8 ExtCsd[512];
+#pragma data_alignment = 4
+#else
+static u8 ExtCsd[512] __attribute__ ((aligned(32)));
+#endif
+	u8 SCR[8] = { 0U };
+	u8 ReadBuff[64] = { 0U };
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Default settings */
+	InstancePtr->BusWidth = XSDPS_1_BIT_WIDTH;
+	InstancePtr->CardType = XSDPS_CARD_SD;
+	InstancePtr->Switch1v8 = 0U;
+	InstancePtr->BusSpeed = XSDPS_CLK_400_KHZ;
+
+	if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) &&
+			((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+			== XSDPS_CAPS_EMB_SLOT)) {
+		InstancePtr->CardType = XSDPS_CHIP_EMMC;
+	} else {
+		Status = XSdPs_IdentifyCard(InstancePtr);
+		if (Status == XST_FAILURE) {
+			goto RETURN_PATH;
+		}
+	}
+
+	if ((InstancePtr->CardType != XSDPS_CARD_SD) &&
+		(InstancePtr->CardType != XSDPS_CARD_MMC) &&
+		(InstancePtr->CardType != XSDPS_CHIP_EMMC)) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+		Status = XSdPs_SdCardInitialize(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Change clock to default clock 25MHz */
+		InstancePtr->BusSpeed = SD_CLK_25_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	} else if ((InstancePtr->CardType == XSDPS_CARD_MMC)
+			|| (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
+		Status = XSdPs_MmcCardInitialize(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+		/* Change clock to default clock 26MHz */
+		InstancePtr->BusSpeed = SD_CLK_26_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_Select_Card(InstancePtr);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+		/* Pull-up disconnected during data transfer */
+		Status = XSdPs_Pullup(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Status = XSdPs_Get_BusWidth(InstancePtr, SCR);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((SCR[1] & WIDTH_4_BIT_SUPPORT) != 0U) {
+			Status = XSdPs_Change_BusWidth(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+
+		if ((InstancePtr->Switch1v8 != 0U) &&
+				(InstancePtr->BusWidth == XSDPS_4_BIT_WIDTH)) {
+			/* Set UHS-I SDR104 mode */
+			Status = XSdPs_Uhs_ModeInit(InstancePtr,
+					XSDPS_UHS_SPEED_MODE_SDR104);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+		} else {
+
+			/*
+			 * card supports CMD6 when SD_SPEC field in SCR register
+			 * indicates that the Physical Layer Specification Version
+			 * is 1.10 or later. So for SD v1.0 cmd6 is not supported.
+			 */
+			if (SCR[0] != 0U) {
+				/* Get speed supported by device */
+				Status = XSdPs_Get_BusSpeed(InstancePtr, ReadBuff);
+				if (Status != XST_SUCCESS) {
+					Status = XST_FAILURE;
+					goto RETURN_PATH;
+				}
+
+				/* Check for high speed support */
+				if ((ReadBuff[13] & HIGH_SPEED_SUPPORT) != 0U) {
+					Status = XSdPs_Change_BusSpeed(InstancePtr);
+					if (Status != XST_SUCCESS) {
+						Status = XST_FAILURE;
+						goto RETURN_PATH;
+					}
+				}
+			}
+		}
+
+	} else if (((InstancePtr->CardType == XSDPS_CARD_MMC) &&
+				(InstancePtr->Card_Version > CSD_SPEC_VER_3)) &&
+				(InstancePtr->HC_Version == XSDPS_HC_SPEC_V2)) {
+
+		Status = XSdPs_Change_BusWidth(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				EXT_CSD_DEVICE_TYPE_HIGH_SPEED) != 0U) {
+			Status = XSdPs_Change_BusSpeed(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HIGH) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	} else if (InstancePtr->CardType == XSDPS_CHIP_EMMC){
+		/* Change bus width to 8-bit */
+		Status = XSdPs_Change_BusWidth(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Get Extended CSD */
+		Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((ExtCsd[EXT_CSD_DEVICE_TYPE_BYTE] &
+				(EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 |
+				EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200)) != 0U) {
+			Status = XSdPs_Change_BusSpeed(InstancePtr);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			Status = XSdPs_Get_Mmc_ExtCsd(InstancePtr, ExtCsd);
+			if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+
+			if (ExtCsd[EXT_CSD_HS_TIMING_BYTE] != EXT_CSD_HS_TIMING_HS200) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	Status = XSdPs_SetBlkSize(InstancePtr, XSDPS_BLK_SIZE_512_MASK);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Identify type of card using CMD0 + CMD1 sequence
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_IdentifyCard(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 OperCondReg;
+	u8 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* 74 CLK delay after card is powered up, before the first command. */
+#if defined (__arm__) || defined (__aarch64__)
+
+	usleep(XSDPS_INIT_DELAY);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	/* 2 msec delay */
+	MB_Sleep(2);
+
+#endif
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Host High Capacity support & High voltage window */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+			XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+	if (Status != XST_SUCCESS) {
+		InstancePtr->CardType = XSDPS_CARD_SD;
+	} else {
+		InstancePtr->CardType = XSDPS_CARD_MMC;
+	}
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+
+	/* "Software reset for all" is initiated */
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress, XSDPS_SW_RST_OFFSET,
+			XSDPS_SWRST_CMD_LINE_MASK);
+
+	/* Proceed with initialization only after reset is complete */
+	ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_SW_RST_OFFSET);
+	while ((ReadReg & XSDPS_SWRST_CMD_LINE_MASK) != 0U) {
+		ReadReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_SW_RST_OFFSET);
+	}
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Switches the SD card voltage from 3v3 to 1v8
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+******************************************************************************/
+static s32 XSdPs_Switch_Voltage(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u16 CtrlReg;
+	u32 ReadReg;
+
+	/* Send switch voltage command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD11, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+	}
+
+	/* Wait for CMD and DATA line to go low */
+	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK |
+					XSDPS_PSR_DAT30_SG_LVL_MASK)) != 0U) {
+		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+	}
+
+	/* Stop the clock */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	CtrlReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+			CtrlReg);
+
+	/* Wait minimum 5mSec */
+#if defined (__arm__) || defined (__aarch64__)
+
+	(void)usleep(5000U);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	MB_Sleep(5U);
+
+#endif
+
+	/* Enabling 1.8V in controller */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg |= XSDPS_HC2_1V8_EN_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_HOST_CTRL2_OFFSET,
+			CtrlReg);
+
+	/* Start clock */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_400_KHZ);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Wait for CMD and DATA line to go high */
+	ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+	while ((ReadReg & (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK))
+			!= (XSDPS_PSR_CMD_SG_LVL_MASK | XSDPS_PSR_DAT30_SG_LVL_MASK)) {
+		ReadReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+	}
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+
+* This function does SD command generation.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Cmd is the command to be sent.
+* @param	Arg is the argument to be sent along with the command.
+* 		This could be address or any other information
+* @param	BlkCnt - Block count passed by the user.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 			is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt)
+{
+	u32 PresentStateReg;
+	u32 CommandReg;
+	u32 StatusReg;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Check the command inhibit to make sure no other
+	 * command transfer is in progress
+	 */
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+	if ((PresentStateReg & XSDPS_PSR_INHIBIT_CMD_MASK) != 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Write block count register */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_CNT_OFFSET, (u16)BlkCnt);
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_TIMEOUT_CTRL_OFFSET, 0xEU);
+
+	/* Write argument register */
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress,
+			XSDPS_ARGMT_OFFSET, Arg);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_NORM_INTR_ALL_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+	/* Command register is set to trigger transfer of command */
+	CommandReg = XSdPs_FrameCmd(InstancePtr, Cmd);
+
+	/*
+	 * Mask to avoid writing to reserved bits 31-30
+	 * This is necessary because 0x80000000 is used  by this software to
+	 * distinguish between ACMD and CMD of same number
+	 */
+	CommandReg = CommandReg & 0x3FFFU;
+
+	/*
+	 * Check for data inhibit in case of command using DAT lines.
+	 * For Tuning Commands DAT lines check can be ignored.
+	 */
+	if ((Cmd != CMD21) && (Cmd != CMD19)) {
+		PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_PRES_STATE_OFFSET);
+		if (((PresentStateReg & (XSDPS_PSR_INHIBIT_DAT_MASK |
+									XSDPS_PSR_INHIBIT_DAT_MASK)) != 0U) &&
+				((CommandReg & XSDPS_DAT_PRESENT_SEL_MASK) != 0U)) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CMD_OFFSET,
+			(u16)CommandReg);
+
+	/* Polling for response for now */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((Cmd == CMD21) || (Cmd == CMD19)) {
+			if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET) & XSDPS_INTR_BRR_MASK) != 0U){
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_BRR_MASK);
+				break;
+			}
+		}
+
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			Status = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+									XSDPS_ERR_INTR_STS_OFFSET);
+			if ((Status & ~XSDPS_INTR_ERR_CT_MASK) == 0) {
+				Status = XSDPS_CT_ERROR;
+			}
+			 /* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_CC_MASK) == 0U);
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET,
+			XSDPS_INTR_CC_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+* This function frames the Command register for a particular command.
+* Note that this generates only the command register value i.e.
+* the upper 16 bits of the transfer mode and command register.
+* This value is already shifted to be upper 16 bits and can be directly
+* OR'ed with transfer mode register value.
+*
+* @param	Command to be sent.
+*
+* @return	Command register value complete with response type and
+* 		data, CRC and index related flags.
+*
+******************************************************************************/
+u32 XSdPs_FrameCmd(XSdPs *InstancePtr, u32 Cmd)
+{
+		u32 RetVal;
+
+		RetVal = Cmd;
+
+		switch(Cmd) {
+		case CMD0:
+			RetVal |= RESP_NONE;
+		break;
+		case CMD1:
+			RetVal |= RESP_R3;
+		break;
+		case CMD2:
+			RetVal |= RESP_R2;
+		break;
+		case CMD3:
+			RetVal |= RESP_R6;
+		break;
+		case CMD4:
+			RetVal |= RESP_NONE;
+			break;
+		case CMD5:
+			RetVal |= RESP_R1B;
+		break;
+		case CMD6:
+			if (InstancePtr->CardType == XSDPS_CARD_SD) {
+				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+			} else {
+				RetVal |= RESP_R1B;
+			}
+			break;
+		case ACMD6:
+			RetVal |= RESP_R1;
+		break;
+		case CMD7:
+			RetVal |= RESP_R1;
+		break;
+		case CMD8:
+			if (InstancePtr->CardType == XSDPS_CARD_SD) {
+				RetVal |= RESP_R1;
+			} else {
+				RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+			}
+			break;
+		case CMD9:
+			RetVal |= RESP_R2;
+		break;
+		case CMD11:
+		case CMD10:
+		case CMD12:
+		case ACMD13:
+		case CMD16:
+			RetVal |= RESP_R1;
+		break;
+		case CMD17:
+		case CMD18:
+		case CMD19:
+		case CMD21:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD23:
+		case ACMD23:
+		case CMD24:
+		case CMD25:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		case ACMD41:
+			RetVal |= RESP_R3;
+		break;
+		case ACMD42:
+			RetVal |= RESP_R1;
+		break;
+		case ACMD51:
+			RetVal |= RESP_R1 | (u32)XSDPS_DAT_PRESENT_SEL_MASK;
+		break;
+		case CMD52:
+		case CMD55:
+			RetVal |= RESP_R1;
+		break;
+		case CMD58:
+		break;
+		default :
+			RetVal |= Cmd;
+		break;
+		}
+
+		return RetVal;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD read in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff)
+{
+	s32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/* Check status to ensure card is initialized */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* Set block size to 512 if not already set */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK | XSDPS_TM_DAT_DIR_SEL_MASK |
+			XSDPS_TM_DMA_EN_MASK | XSDPS_TM_MUL_SIN_BLK_SEL_MASK);
+
+	Xil_DCacheInvalidateRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+
+	/* Send block read command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD18, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/* Check for transfer complete */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+* This function performs SD write in polled mode.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	Arg is the address passed by the user that is to be sent as
+* 		argument along with the command.
+* @param	BlkCnt - Block count passed by the user.
+* @param	Buff - Pointer to the data buffer for a DMA transfer.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because another transfer
+* 		is in progress or command or data inhibit is set
+*
+******************************************************************************/
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff)
+{
+	s32 Status;
+	u32 PresentStateReg;
+	u32 StatusReg;
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/* Check status to ensure card is initialized */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0x0U) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* Set block size to 512 if not already set */
+	if( XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET) != XSDPS_BLK_SIZE_512_MASK ) {
+		Status = XSdPs_SetBlkSize(InstancePtr,
+			XSDPS_BLK_SIZE_512_MASK);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+	}
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, Buff);
+	Xil_DCacheFlushRange((INTPTR)Buff, BlkCnt * XSDPS_BLK_SIZE_512_MASK);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_AUTO_CMD12_EN_MASK |
+			XSDPS_TM_BLK_CNT_EN_MASK |
+			XSDPS_TM_MUL_SIN_BLK_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD25, Arg, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Selects card and sets default block size
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Select_Card (XSdPs *InstancePtr)
+{
+	s32 Status = 0;
+
+	/* Send CMD7 - Select card */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD7,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to setup ADMA2 descriptor table
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	BlkCnt - block count.
+* @param	Buff pointer to data buffer.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff)
+{
+	u32 TotalDescLines = 0U;
+	u32 DescNum = 0U;
+	u32 BlkSize = 0U;
+
+	/* Setup ADMA2 - Write descriptor table and point ADMA SAR to it */
+	BlkSize = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_BLK_SIZE_OFFSET);
+	BlkSize = BlkSize & XSDPS_BLK_SIZE_MASK;
+
+	if((BlkCnt*BlkSize) < XSDPS_DESC_MAX_LENGTH) {
+
+		TotalDescLines = 1U;
+
+	}else {
+
+		TotalDescLines = ((BlkCnt*BlkSize) / XSDPS_DESC_MAX_LENGTH);
+		if (((BlkCnt * BlkSize) % XSDPS_DESC_MAX_LENGTH) != 0U) {
+			TotalDescLines += 1U;
+		}
+
+	}
+
+	for (DescNum = 0U; DescNum < (TotalDescLines-1); DescNum++) {
+		InstancePtr->Adma2_DescrTbl[DescNum].Address =
+				(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+		InstancePtr->Adma2_DescrTbl[DescNum].Attribute =
+				XSDPS_DESC_TRAN | XSDPS_DESC_VALID;
+		/* This will write '0' to length field which indicates 65536 */
+		InstancePtr->Adma2_DescrTbl[DescNum].Length =
+				(u16)XSDPS_DESC_MAX_LENGTH;
+	}
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Address =
+			(u32)((UINTPTR)Buff + (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Attribute =
+			XSDPS_DESC_TRAN | XSDPS_DESC_END | XSDPS_DESC_VALID;
+
+	InstancePtr->Adma2_DescrTbl[TotalDescLines-1].Length =
+			(u16)((BlkCnt*BlkSize) - (DescNum*XSDPS_DESC_MAX_LENGTH));
+
+
+	XSdPs_WriteReg(InstancePtr->Config.BaseAddress, XSDPS_ADMA_SAR_OFFSET,
+			(u32)(UINTPTR)&(InstancePtr->Adma2_DescrTbl[0]));
+
+	Xil_DCacheFlushRange((INTPTR)&(InstancePtr->Adma2_DescrTbl[0]),
+			sizeof(XSdPs_Adma2Descriptor) * 32U);
+
+}
+
+/*****************************************************************************/
+/**
+* Mmc initialization is done in this function
+*
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+*
+* @return
+* 		- XST_SUCCESS if initialization was successful
+* 		- XST_FAILURE if failure - could be because
+* 			a) MMC is already initialized
+* 			b) There is no card inserted
+* 			c) One of the steps (commands) in the initialization
+*			   cycle failed
+* @note 	This function initializes the SD card by following its
+*		initialization and identification state diagram.
+*		CMD0 is sent to reset card.
+*		CMD1 sent to identify voltage and high capacity support
+*		CMD2 and CMD3 are sent to obtain Card ID and
+*		Relative card address respectively.
+*		CMD9 is sent to read the card specific data.
+*
+******************************************************************************/
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr)
+{
+	u32 PresentStateReg;
+	s32 Status;
+	u32 RespOCR;
+	u32 CSD[4];
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if ((InstancePtr->HC_Version != XSDPS_HC_SPEC_V3) ||
+				((InstancePtr->Host_Caps & XSDPS_CAPS_SLOT_TYPE_MASK)
+				!= XSDPS_CAPS_EMB_SLOT)) {
+		if(InstancePtr->Config.CardDetect != 0U) {
+			/*
+			 * Check the present state register to make sure
+			 * card is inserted and detected by host controller
+			 */
+			PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XSDPS_PRES_STATE_OFFSET);
+			if ((PresentStateReg & XSDPS_PSR_CARD_INSRT_MASK) == 0U)	{
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		}
+	}
+
+	/* CMD0 no response expected */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD0, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	RespOCR = 0U;
+	/* Send CMD1 while card is still busy with power up */
+	while ((RespOCR & XSDPS_RESPOCR_READY) == 0U) {
+
+		/* Host High Capacity support & High volage window */
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD1,
+				XSDPS_ACMD41_HCS | XSDPS_CMD1_HIGH_VOL, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Response with card capacity */
+		RespOCR = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XSDPS_RESP0_OFFSET);
+
+	}
+
+	/* Update HCS support flag based on card capacity response */
+	if ((RespOCR & XSDPS_ACMD41_HCS) != 0U) {
+		InstancePtr->HCS = 1U;
+	}
+
+	/* CMD2 for Card ID */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD2, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	InstancePtr->CardID[0] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	InstancePtr->CardID[1] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	InstancePtr->CardID[2] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	InstancePtr->CardID[3] =
+			XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	/* Set relative card address */
+	InstancePtr->RelCardAddr = 0x12340000U;
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD3, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD9, (InstancePtr->RelCardAddr), 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Card specific data is read.
+	 * Currently not used for any operation.
+	 */
+	CSD[0] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+	CSD[1] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP1_OFFSET);
+	CSD[2] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP2_OFFSET);
+	CSD[3] = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP3_OFFSET);
+
+	InstancePtr->Card_Version =  (CSD[3] & CSD_SPEC_VER_MASK) >>18U;
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+	return Status;
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.h
new file mode 100644
index 000000000..409653891
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps.h
@@ -0,0 +1,228 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps.h
+* @addtogroup sdps_v2_5
+* @{
+* @details
+*
+* This file contains the implementation of XSdPs driver.
+* This driver is used initialize read from and write to the SD card.
+* Features such as switching bus width to 4-bit and switching to high speed,
+* changing clock frequency, block size etc. are supported.
+* SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however
+* is done using 1-bit bus width and 400KHz clock frequency.
+* SD commands are classified as broadcast and addressed. Commands can be
+* those with response only (using only command line) or
+* response + data (using command and data lines).
+* Only one command can be sent at a time. During a data transfer however,
+* when dsta lines are in use, certain commands (which use only the command
+* line) can be sent, most often to obtain status.
+* This driver does not support multi card slots at present.
+*
+* Intialization:
+* This includes initialization on the host controller side to select
+* clock frequency, bus power and default transfer related parameters.
+* The default voltage is 3.3V.
+* On the SD card side, the initialization and identification state diagram is
+* implemented. This resets the card, gives it a unique address/ID and
+* identifies key card related specifications.
+*
+* Data transfer:
+* The SD card is put in tranfer state to read from or write to it.
+* The default block size is 512 bytes and if supported,
+* default bus width is 4-bit and bus speed is High speed.
+* The read and write functions are implemented in polled mode using ADMA2.
+*
+* At any point, when key parameters such as block size or
+* clock/speed or bus width are modified, this driver takes care of
+* maintaining the same selection on host and card.
+* All error bits in host controller are monitored by the driver and in the
+* event one of them is set, driver will clear the interrupt status and
+* communicate failure to the upper layer.
+*
+* File system use:
+* This driver can be used with xilffs library to read and write files to SD.
+* (Please refer to procedure in diskio.c). The file system read/write example
+* in polled mode can used for reference.
+*
+* There is no example for using SD driver without file system at present.
+* However, the driver can be used without the file system. The glue layer
+* in filesytem can be used as reference for the same. The block count
+* passed to the read/write function in one call is limited by the ADMA2
+* descriptor table and hence care will have to be taken to call read/write
+* API's in a loop for large file sizes.
+*
+* Interrupt mode is not supported because it offers no improvement when used
+* with file system.
+*
+* eMMC support:
+* SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK.
+* The features of eMMC supported by the driver will depend on those supported
+* by the host controller. The current driver supports read/write on eMMC card
+* using 4-bit and high speed mode currently.
+*
+* Features not supported include - card write protect, password setting,
+* lock/unlock, interrupts, SDMA mode, programmed I/O mode and
+* 64-bit addressed ADMA2, erase/pre-erase commands.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.2   hk     07/28/14 Make changes to enable use of data cache.
+* 2.3   sk     09/23/14 Send command for relative card address
+*                       when re-initialization is done.CR# 819614.
+*						Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.4	sk	   12/04/14 Added support for micro SD without
+* 						WP/CD. CR# 810655.
+*						Checked for DAT Inhibit mask instead of CMD
+* 						Inhibit mask in Cmd Transfer API.
+*						Added Support for SD Card v1.0
+* 2.5 	sg		07/09/15 Added SD 3.0 features
+*       kvn     07/15/15 Modified the code according to MISRAC-2012.
+* 2.6   sk     10/12/15 Added support for SD card v1.0 CR# 840601.
+* 2.7   sk     11/24/15 Considered the slot type befoe checking CD/WP pins.
+*       sk     12/10/15 Added support for MMC cards.
+*              01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/01/16 Removed Bus Width check for eMMC. CR# 938311.
+*
+* 

+*
+******************************************************************************/
+
+
+#ifndef SDPS_H_
+#define SDPS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_printf.h"
+#include "xil_cache.h"
+#include "xstatus.h"
+#include "xsdps_hw.h"
+#include 
+
+/************************** Constant Definitions *****************************/
+
+#define XSDPS_CT_ERROR	0x2U	/**< Command timeout flag */
+#define MAX_TUNING_COUNT	40U		/**< Maximum Tuning count */
+
+/**************************** Type Definitions *******************************/
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;			/**< Unique ID  of device */
+	u32 BaseAddress;		/**< Base address of the device */
+	u32 InputClockHz;		/**< Input clock frequency */
+	u32 CardDetect;			/**< Card Detect */
+	u32 WriteProtect;			/**< Write Protect */
+} XSdPs_Config;
+
+/* ADMA2 descriptor table */
+typedef struct {
+	u16 Attribute;		/**< Attributes of descriptor */
+	u16 Length;		/**< Length of current dma transfer */
+	u32 Address;		/**< Address of current dma transfer */
+} XSdPs_Adma2Descriptor;
+
+/**
+ * The XSdPs driver instance data. The user is required to allocate a
+ * variable of this type for every SD device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XSdPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 Host_Caps;		/**< Capabilities of host controller */
+	u32 Host_CapsExt;	/**< Extended Capabilities */
+	u32 HCS;		/**< High capacity support in card */
+	u8  CardType;		/**< Type of card - SD/MMC/eMMC */
+	u8  Card_Version;	/**< Card version */
+	u8  HC_Version;		/**< Host controller version */
+	u8  BusWidth;		/**< Current operating bus width */
+	u32 BusSpeed;		/**< Current operating bus speed */
+	u8  Switch1v8;		/**< 1.8V Switch support */
+	u32 CardID[4];		/**< Card ID Register */
+	u32 RelCardAddr;	/**< Relative Card Address */
+	u32 CardSpecData[4];	/**< Card Specific Data Register */
+	u32 SdCardConfig;	/**< Sd Card Configuration Register */
+	/**< ADMA Descriptors */
+#ifdef __ICCARM__
+#pragma data_alignment = 32
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32];
+#pragma data_alignment = 4
+#else
+	XSdPs_Adma2Descriptor Adma2_DescrTbl[32] __attribute__ ((aligned(32)));
+#endif
+} XSdPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId);
+s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr,
+				u32 EffectiveAddr);
+s32 XSdPs_SdCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff);
+s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize);
+s32 XSdPs_Select_Card (XSdPs *InstancePtr);
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq);
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr);
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr);
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR);
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff);
+s32 XSdPs_Pullup(XSdPs *InstancePtr);
+s32 XSdPs_MmcCardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_CardInitialize(XSdPs *InstancePtr);
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_g.c
new file mode 100644
index 000000000..b5d2e4be8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_g.c
@@ -0,0 +1,58 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsdps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSdPs_Config XSdPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_SD_1_DEVICE_ID,
+		XPAR_PSU_SD_1_BASEADDR,
+		XPAR_PSU_SD_1_SDIO_CLK_FREQ_HZ,
+		XPAR_PSU_SD_1_HAS_CD,
+		XPAR_PSU_SD_1_HAS_WP
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_hw.h
new file mode 100644
index 000000000..c797e8216
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_hw.h
@@ -0,0 +1,1186 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_hw.h
+* @addtogroup sdps_v2_5
+* @{
+*
+* This header file contains the identifiers and basic HW access driver
+* functions (or  macros) that can be used to access the device. Other driver
+* functions are defined in xsdps.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     12/10/15 Added support for MMC cards.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+* 

+*
+******************************************************************************/
+
+#ifndef SD_HW_H_
+#define SD_HW_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of an SD device.
+ * @{
+ */
+
+#define XSDPS_SDMA_SYS_ADDR_OFFSET	0x00U	/**< SDMA System Address
+							Register */
+#define XSDPS_SDMA_SYS_ADDR_LO_OFFSET	XSDPS_SDMA_SYS_ADDR_OFFSET
+						/**< SDMA System Address
+							Low Register */
+#define XSDPS_ARGMT2_LO_OFFSET		0x00U	/**< Argument2 Low Register */
+#define XSDPS_SDMA_SYS_ADDR_HI_OFFSET	0x02U	/**< SDMA System Address
+							High Register */
+#define XSDPS_ARGMT2_HI_OFFSET		0x02U	/**< Argument2 High Register */
+
+#define XSDPS_BLK_SIZE_OFFSET		0x04U	/**< Block Size Register */
+#define XSDPS_BLK_CNT_OFFSET		0x06U	/**< Block Count Register */
+#define XSDPS_ARGMT_OFFSET		0x08U	/**< Argument Register */
+#define XSDPS_ARGMT1_LO_OFFSET		XSDPS_ARGMT_OFFSET
+						/**< Argument1 Register */
+#define XSDPS_ARGMT1_HI_OFFSET		0x0AU	/**< Argument1 Register */
+
+#define XSDPS_XFER_MODE_OFFSET		0x0CU	/**< Transfer Mode Register */
+#define XSDPS_CMD_OFFSET		0x0EU	/**< Command Register */
+#define XSDPS_RESP0_OFFSET		0x10U	/**< Response0 Register */
+#define XSDPS_RESP1_OFFSET		0x14U	/**< Response1 Register */
+#define XSDPS_RESP2_OFFSET		0x18U	/**< Response2 Register */
+#define XSDPS_RESP3_OFFSET		0x1CU	/**< Response3 Register */
+#define XSDPS_BUF_DAT_PORT_OFFSET	0x20U	/**< Buffer Data Port */
+#define XSDPS_PRES_STATE_OFFSET		0x24U	/**< Present State */
+#define XSDPS_HOST_CTRL1_OFFSET		0x28U	/**< Host Control 1 */
+#define XSDPS_POWER_CTRL_OFFSET		0x29U	/**< Power Control */
+#define XSDPS_BLK_GAP_CTRL_OFFSET	0x2AU	/**< Block Gap Control */
+#define XSDPS_WAKE_UP_CTRL_OFFSET	0x2BU	/**< Wake Up Control */
+#define XSDPS_CLK_CTRL_OFFSET		0x2CU	/**< Clock Control */
+#define XSDPS_TIMEOUT_CTRL_OFFSET	0x2EU	/**< Timeout Control */
+#define XSDPS_SW_RST_OFFSET		0x2FU	/**< Software Reset */
+#define XSDPS_NORM_INTR_STS_OFFSET 	0x30U	/**< Normal Interrupt
+							Status Register */
+#define XSDPS_ERR_INTR_STS_OFFSET 	0x32U	/**< Error Interrupt
+							Status Register */
+#define XSDPS_NORM_INTR_STS_EN_OFFSET	0x34U	/**< Normal Interrupt
+						Status Enable Register */
+#define XSDPS_ERR_INTR_STS_EN_OFFSET	0x36U	/**< Error Interrupt
+						Status Enable Register */
+#define XSDPS_NORM_INTR_SIG_EN_OFFSET	0x38U	/**< Normal Interrupt
+						Signal Enable Register */
+#define XSDPS_ERR_INTR_SIG_EN_OFFSET	0x3AU	/**< Error Interrupt
+						Signal Enable Register */
+
+#define XSDPS_AUTO_CMD12_ERR_STS_OFFSET	0x3CU	/**< Auto CMD12 Error Status
+							Register */
+#define XSDPS_HOST_CTRL2_OFFSET		0x3EU	/**< Host Control2 Register */
+#define XSDPS_CAPS_OFFSET 		0x40U	/**< Capabilities Register */
+#define XSDPS_CAPS_EXT_OFFSET 		0x44U	/**< Capabilities Extended */
+#define XSDPS_MAX_CURR_CAPS_OFFSET	0x48U	/**< Maximum Current
+						Capabilities Register */
+#define XSDPS_MAX_CURR_CAPS_EXT_OFFSET	0x4CU	/**< Maximum Current
+						Capabilities Ext Register */
+#define XSDPS_FE_ERR_INT_STS_OFFSET	0x52U	/**< Force Event for
+						Error Interrupt Status */
+#define XSDPS_FE_AUTO_CMD12_EIS_OFFSET	0x50U	/**< Auto CM12 Error Interrupt
+							Status Register */
+#define XSDPS_ADMA_ERR_STS_OFFSET	0x54U	/**< ADMA Error Status
+							Register */
+#define XSDPS_ADMA_SAR_OFFSET		0x58U	/**< ADMA System Address
+							Register */
+#define XSDPS_ADMA_SAR_EXT_OFFSET	0x5CU	/**< ADMA System Address
+							Extended Register */
+#define XSDPS_PRE_VAL_1_OFFSET		0x60U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_2_OFFSET		0x64U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_3_OFFSET		0x68U	/**< Preset Value Register */
+#define XSDPS_PRE_VAL_4_OFFSET		0x6CU	/**< Preset Value Register */
+#define XSDPS_BOOT_TOUT_CTRL_OFFSET	0x70U	/**< Boot timeout control
+							register */
+
+#define XSDPS_SHARED_BUS_CTRL_OFFSET	0xE0U	/**< Shared Bus Control
+							Register */
+#define XSDPS_SLOT_INTR_STS_OFFSET	0xFCU	/**< Slot Interrupt Status
+							Register */
+#define XSDPS_HOST_CTRL_VER_OFFSET	0xFEU	/**< Host Controller Version
+							Register */
+
+/* @} */
+
+/** @name Control Register - Host control, Power control,
+ * 			Block Gap control and Wakeup control
+ *
+ * This register contains bits for various configuration options of
+ * the SD host controller. Read/Write apart from the reserved bits.
+ * @{
+ */
+
+#define XSDPS_HC_LED_MASK		0x00000001U /**< LED Control */
+#define XSDPS_HC_WIDTH_MASK		0x00000002U /**< Bus width */
+#define XSDPS_HC_BUS_WIDTH_4		0x00000002U
+#define XSDPS_HC_SPEED_MASK		0x00000004U /**< High Speed */
+#define XSDPS_HC_DMA_MASK		0x00000018U /**< DMA Mode Select */
+#define XSDPS_HC_DMA_SDMA_MASK		0x00000000U /**< SDMA Mode */
+#define XSDPS_HC_DMA_ADMA1_MASK		0x00000008U /**< ADMA1 Mode */
+#define XSDPS_HC_DMA_ADMA2_32_MASK	0x00000010U /**< ADMA2 Mode - 32 bit */
+#define XSDPS_HC_DMA_ADMA2_64_MASK	0x00000018U /**< ADMA2 Mode - 64 bit */
+#define XSDPS_HC_EXT_BUS_WIDTH		0x00000020U /**< Bus width - 8 bit */
+#define XSDPS_HC_CARD_DET_TL_MASK	0x00000040U /**< Card Detect Tst Lvl */
+#define XSDPS_HC_CARD_DET_SD_MASK	0x00000080U /**< Card Detect Sig Det */
+
+#define XSDPS_PC_BUS_PWR_MASK		0x00000001U /**< Bus Power Control */
+#define XSDPS_PC_BUS_VSEL_MASK		0x0000000EU /**< Bus Voltage Select */
+#define XSDPS_PC_BUS_VSEL_3V3_MASK	0x0000000EU /**< Bus Voltage 3.3V */
+#define XSDPS_PC_BUS_VSEL_3V0_MASK	0x0000000CU /**< Bus Voltage 3.0V */
+#define XSDPS_PC_BUS_VSEL_1V8_MASK	0x0000000AU /**< Bus Voltage 1.8V */
+#define XSDPS_PC_EMMC_HW_RST_MASK	0x00000010U /**< HW reset for eMMC */
+
+#define XSDPS_BGC_STP_REQ_MASK		0x00000001U /**< Block Gap Stop Req */
+#define XSDPS_BGC_CNT_REQ_MASK		0x00000002U /**< Block Gap Cont Req */
+#define XSDPS_BGC_RWC_MASK		0x00000004U /**< Block Gap Rd Wait */
+#define XSDPS_BGC_INTR_MASK		0x00000008U /**< Block Gap Intr */
+#define XSDPS_BGC_SPI_MODE_MASK		0x00000010U /**< Block Gap SPI Mode */
+#define XSDPS_BGC_BOOT_EN_MASK		0x00000020U /**< Block Gap Boot Enb */
+#define XSDPS_BGC_ALT_BOOT_EN_MASK	0x00000040U /**< Block Gap Alt BootEn */
+#define XSDPS_BGC_BOOT_ACK_MASK		0x00000080U /**< Block Gap Boot Ack */
+
+#define XSDPS_WC_WUP_ON_INTR_MASK	0x00000001U /**< Wakeup Card Intr */
+#define XSDPS_WC_WUP_ON_INSRT_MASK	0x00000002U /**< Wakeup Card Insert */
+#define XSDPS_WC_WUP_ON_REM_MASK	0x00000004U /**< Wakeup Card Removal */
+
+/* @} */
+
+/** @name Control Register - Clock control, Timeout control & Software reset
+ *
+ * This register contains bits for configuration options of clock, timeout and
+ * software reset.
+ * Read/Write except for Inter_Clock_Stable bit (read only) and reserved bits.
+ * @{
+ */
+
+#define XSDPS_CC_INT_CLK_EN_MASK		0x00000001U
+#define XSDPS_CC_INT_CLK_STABLE_MASK	0x00000002U
+#define XSDPS_CC_SD_CLK_EN_MASK			0x00000004U
+#define XSDPS_CC_SD_CLK_GEN_SEL_MASK		0x00000020U
+#define XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK	0x000000C0U
+#define XSDPS_CC_SDCLK_FREQ_SEL_MASK		0x0000FF00U
+#define XSDPS_CC_SDCLK_FREQ_D256_MASK		0x00008000U
+#define XSDPS_CC_SDCLK_FREQ_D128_MASK		0x00004000U
+#define XSDPS_CC_SDCLK_FREQ_D64_MASK		0x00002000U
+#define XSDPS_CC_SDCLK_FREQ_D32_MASK		0x00001000U
+#define XSDPS_CC_SDCLK_FREQ_D16_MASK		0x00000800U
+#define XSDPS_CC_SDCLK_FREQ_D8_MASK		0x00000400U
+#define XSDPS_CC_SDCLK_FREQ_D4_MASK		0x00000200U
+#define XSDPS_CC_SDCLK_FREQ_D2_MASK		0x00000100U
+#define XSDPS_CC_SDCLK_FREQ_BASE_MASK	0x00000000U
+#define XSDPS_CC_MAX_DIV_CNT			256U
+#define XSDPS_CC_EXT_MAX_DIV_CNT		2046U
+#define XSDPS_CC_EXT_DIV_SHIFT			6U
+
+#define XSDPS_TC_CNTR_VAL_MASK			0x0000000FU
+
+#define XSDPS_SWRST_ALL_MASK			0x00000001U
+#define XSDPS_SWRST_CMD_LINE_MASK		0x00000002U
+#define XSDPS_SWRST_DAT_LINE_MASK		0x00000004U
+
+#define XSDPS_CC_MAX_NUM_OF_DIV		9U
+#define XSDPS_CC_DIV_SHIFT		8U
+
+/* @} */
+
+/** @name SD Interrupt Registers
+ *
+ *  Normal and Error Interrupt Status Register 
+ * This register shows the normal and error interrupt status.
+ * Status enable register affects reads of this register.
+ * If Signal enable register is set and the corresponding status bit is set,
+ * interrupt is generated.
+ * Write to clear except
+ * Error_interrupt and Card_Interrupt bits - Read only
+ *
+ *  Normal and Error Interrupt Status Enable Register 
+ * Setting this register bits enables Interrupt status.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ *  Normal and Error Interrupt Signal Enable Register 
+ * This register is used to select which interrupt status is
+ * indicated to the Host System as the interrupt.
+ * Read/Write except Fixed_to_0 bit (Read only)
+ *
+ * All three registers have same bit definitions
+ * @{
+ */
+
+#define XSDPS_INTR_CC_MASK		0x00000001U /**< Command Complete */
+#define XSDPS_INTR_TC_MASK		0x00000002U /**< Transfer Complete */
+#define XSDPS_INTR_BGE_MASK		0x00000004U /**< Block Gap Event */
+#define XSDPS_INTR_DMA_MASK		0x00000008U /**< DMA Interrupt */
+#define XSDPS_INTR_BWR_MASK		0x00000010U /**< Buffer Write Ready */
+#define XSDPS_INTR_BRR_MASK		0x00000020U /**< Buffer Read Ready */
+#define XSDPS_INTR_CARD_INSRT_MASK	0x00000040U /**< Card Insert */
+#define XSDPS_INTR_CARD_REM_MASK	0x00000080U /**< Card Remove */
+#define XSDPS_INTR_CARD_MASK		0x00000100U /**< Card Interrupt */
+#define XSDPS_INTR_INT_A_MASK		0x00000200U /**< INT A Interrupt */
+#define XSDPS_INTR_INT_B_MASK		0x00000400U /**< INT B Interrupt */
+#define XSDPS_INTR_INT_C_MASK		0x00000800U /**< INT C Interrupt */
+#define XSDPS_INTR_RE_TUNING_MASK	0x00001000U /**< Re-Tuning Interrupt */
+#define XSDPS_INTR_BOOT_ACK_RECV_MASK	0x00002000U /**< Boot Ack Recv
+							Interrupt */
+#define XSDPS_INTR_BOOT_TERM_MASK	0x00004000U /**< Boot Terminate
+							Interrupt */
+#define XSDPS_INTR_ERR_MASK		0x00008000U /**< Error Interrupt */
+#define XSDPS_NORM_INTR_ALL_MASK	0x0000FFFFU
+
+#define XSDPS_INTR_ERR_CT_MASK		0x00000001U /**< Command Timeout
+							Error */
+#define XSDPS_INTR_ERR_CCRC_MASK	0x00000002U /**< Command CRC Error */
+#define XSDPS_INTR_ERR_CEB_MASK		0x00000004U /**< Command End Bit
+							Error */
+#define XSDPS_INTR_ERR_CI_MASK		0x00000008U /**< Command Index Error */
+#define XSDPS_INTR_ERR_DT_MASK		0x00000010U /**< Data Timeout Error */
+#define XSDPS_INTR_ERR_DCRC_MASK	0x00000020U /**< Data CRC Error */
+#define XSDPS_INTR_ERR_DEB_MASK		0x00000040U /**< Data End Bit Error */
+#define XSDPS_INTR_ERR_CUR_LMT_MASK	0x00000080U /**< Current Limit Error */
+#define XSDPS_INTR_ERR_AUTO_CMD12_MASK	0x00000100U /**< Auto CMD12 Error */
+#define XSDPS_INTR_ERR_ADMA_MASK	0x00000200U /**< ADMA Error */
+#define XSDPS_INTR_ERR_TR_MASK		0x00001000U /**< Tuning Error */
+#define XSDPS_INTR_VEND_SPF_ERR_MASK	0x0000E000U /**< Vendor Specific
+							Error */
+#define XSDPS_ERROR_INTR_ALL_MASK	0x0000F3FFU /**< Mask for error bits */
+/* @} */
+
+/** @name Block Size and Block Count Register
+ *
+ * This register contains the block count for current transfer,
+ * block size and SDMA buffer size.
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_MASK		0x00000FFFU /**< Transfer Block Size */
+#define XSDPS_SDMA_BUFF_SIZE_MASK	0x00007000U /**< Host SDMA Buffer Size */
+#define XSDPS_BLK_SIZE_1024		0x400U
+#define XSDPS_BLK_SIZE_2048		0x800U
+#define XSDPS_BLK_CNT_MASK		0x0000FFFFU /**< Block Count for
+								Current Transfer */
+
+/* @} */
+
+/** @name Transfer Mode and Command Register
+ *
+ * The Transfer Mode register is used to control the data transfers and
+ * Command register is used for command generation
+ * Read/Write except for reserved bits.
+ * @{
+ */
+
+#define XSDPS_TM_DMA_EN_MASK		0x00000001U /**< DMA Enable */
+#define XSDPS_TM_BLK_CNT_EN_MASK	0x00000002U /**< Block Count Enable */
+#define XSDPS_TM_AUTO_CMD12_EN_MASK	0x00000004U /**< Auto CMD12 Enable */
+#define XSDPS_TM_DAT_DIR_SEL_MASK	0x00000010U /**< Data Transfer
+							Direction Select */
+#define XSDPS_TM_MUL_SIN_BLK_SEL_MASK	0x00000020U /**< Multi/Single
+							Block Select */
+
+#define XSDPS_CMD_RESP_SEL_MASK		0x00000003U /**< Response Type
+							Select */
+#define XSDPS_CMD_RESP_NONE_MASK	0x00000000U /**< No Response */
+#define XSDPS_CMD_RESP_L136_MASK	0x00000001U /**< Response length 138 */
+#define XSDPS_CMD_RESP_L48_MASK		0x00000002U /**< Response length 48 */
+#define XSDPS_CMD_RESP_L48_BSY_CHK_MASK	0x00000003U /**< Response length 48 &
+							check busy after
+							response */
+#define XSDPS_CMD_CRC_CHK_EN_MASK	0x00000008U /**< Command CRC Check
+							Enable */
+#define XSDPS_CMD_INX_CHK_EN_MASK	0x00000010U /**< Command Index Check
+							Enable */
+#define XSDPS_DAT_PRESENT_SEL_MASK	0x00000020U /**< Data Present Select */
+#define XSDPS_CMD_TYPE_MASK		0x000000C0U /**< Command Type */
+#define XSDPS_CMD_TYPE_NORM_MASK	0x00000000U /**< CMD Type - Normal */
+#define XSDPS_CMD_TYPE_SUSPEND_MASK	0x00000040U /**< CMD Type - Suspend */
+#define XSDPS_CMD_TYPE_RESUME_MASK	0x00000080U /**< CMD Type - Resume */
+#define XSDPS_CMD_TYPE_ABORT_MASK	0x000000C0U /**< CMD Type - Abort */
+#define XSDPS_CMD_MASK			0x00003F00U /**< Command Index Mask -
+							Set to CMD0-63,
+							AMCD0-63 */
+
+/* @} */
+
+/** @name Auto CMD Error Status Register
+ *
+ * This register is read only register which contains
+ * information about the error status of Auto CMD 12 and 23.
+ * Read Only
+ * @{
+ */
+#define XSDPS_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_AUTO_CMD_CRC_MASK		0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_AUTO_CMD_EB_MASK		0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_AUTO_CMD_IND_MASK		0x0010U /**< Auto CMD Index Error */
+#define XSDPS_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+/** @name Host Control2 Register
+ *
+ * This register contains extended configuration bits.
+ * Read Write
+ * @{
+ */
+#define XSDPS_HC2_UHS_MODE_MASK		0x0007U /**< UHS Mode select bits */
+#define XSDPS_HC2_UHS_MODE_SDR12_MASK	0x0000U /**< SDR12 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR25_MASK	0x0001U /**< SDR25 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR50_MASK	0x0002U /**< SDR50 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_SDR104_MASK	0x0003U /**< SDR104 UHS Mode */
+#define XSDPS_HC2_UHS_MODE_DDR50_MASK	0x0004U /**< DDR50 UHS Mode */
+#define XSDPS_HC2_1V8_EN_MASK		0x0008U /**< 1.8V Signal Enable */
+#define XSDPS_HC2_DRV_STR_SEL_MASK	0x0030U /**< Driver Strength
+							Selection */
+#define XSDPS_HC2_DRV_STR_B_MASK	0x0000U /**< Driver Strength B */
+#define XSDPS_HC2_DRV_STR_A_MASK	0x0010U /**< Driver Strength A */
+#define XSDPS_HC2_DRV_STR_C_MASK	0x0020U /**< Driver Strength C */
+#define XSDPS_HC2_DRV_STR_D_MASK	0x0030U /**< Driver Strength D */
+#define XSDPS_HC2_EXEC_TNG_MASK		0x0040U /**< Execute Tuning */
+#define XSDPS_HC2_SAMP_CLK_SEL_MASK	0x0080U /**< Sampling Clock
+							Selection */
+#define XSDPS_HC2_ASYNC_INTR_EN_MASK	0x4000U /**< Asynchronous Interrupt
+							Enable */
+#define XSDPS_HC2_PRE_VAL_EN_MASK	0x8000U /**< Preset Value Enable */
+
+/* @} */
+
+/** @name Capabilities Register
+ *
+ * Capabilities register is a read only register which contains
+ * information about the host controller.
+ * Sufficient if read once after power on.
+ * Read Only
+ * @{
+ */
+#define XSDPS_CAP_TOUT_CLK_FREQ_MASK	0x0000003FU /**< Timeout clock freq
+							select */
+#define XSDPS_CAP_TOUT_CLK_UNIT_MASK	0x00000080U /**< Timeout clock unit -
+							MHz/KHz */
+#define XSDPS_CAP_MAX_BLK_LEN_MASK	0x00030000U /**< Max block length */
+#define XSDPS_CAP_MAX_BLK_LEN_512B_MASK	0x00000000U /**< Max block 512 bytes */
+#define XSDPS_CAP_MAX_BL_LN_1024_MASK	0x00010000U /**< Max block 1024 bytes */
+#define XSDPS_CAP_MAX_BL_LN_2048_MASK	0x00020000U /**< Max block 2048 bytes */
+#define XSDPS_CAP_MAX_BL_LN_4096_MASK	0x00030000U /**< Max block 4096 bytes */
+
+#define XSDPS_CAP_EXT_MEDIA_BUS_MASK	0x00040000U /**< Extended media bus */
+#define XSDPS_CAP_ADMA2_MASK		0x00080000U /**< ADMA2 support */
+#define XSDPS_CAP_HIGH_SPEED_MASK	0x00200000U /**< High speed support */
+#define XSDPS_CAP_SDMA_MASK		0x00400000U /**< SDMA support */
+#define XSDPS_CAP_SUSP_RESUME_MASK	0x00800000U /**< Suspend/Resume
+							support */
+#define XSDPS_CAP_VOLT_3V3_MASK		0x01000000U /**< 3.3V support */
+#define XSDPS_CAP_VOLT_3V0_MASK		0x02000000U /**< 3.0V support */
+#define XSDPS_CAP_VOLT_1V8_MASK		0x04000000U /**< 1.8V support */
+
+#define XSDPS_CAP_SYS_BUS_64_MASK	0x10000000U /**< 64 bit system bus
+							support */
+/* Spec 2.0 */
+#define XSDPS_CAP_INTR_MODE_MASK	0x08000000U /**< Interrupt mode
+							support */
+#define XSDPS_CAP_SPI_MODE_MASK		0x20000000U /**< SPI mode */
+#define XSDPS_CAP_SPI_BLOCK_MODE_MASK	0x40000000U /**< SPI block mode */
+
+
+/* Spec 3.0 */
+#define XSDPS_CAPS_ASYNC_INTR_MASK	0x20000000U /**< Async Interrupt
+							support */
+#define XSDPS_CAPS_SLOT_TYPE_MASK	0xC0000000U /**< Slot Type */
+#define XSDPS_CAPS_REM_CARD			0x00000000U /**< Removable Slot */
+#define XSDPS_CAPS_EMB_SLOT			0x40000000U /**< Embedded Slot */
+#define XSDPS_CAPS_SHR_BUS			0x80000000U /**< Shared Bus Slot */
+
+#define XSDPS_ECAPS_SDR50_MASK		0x00000001U /**< SDR50 Mode support */
+#define XSDPS_ECAPS_SDR104_MASK		0x00000002U /**< SDR104 Mode support */
+#define XSDPS_ECAPS_DDR50_MASK		0x00000004U /**< DDR50 Mode support */
+#define XSDPS_ECAPS_DRV_TYPE_A_MASK	0x00000010U /**< DriverType A support */
+#define XSDPS_ECAPS_DRV_TYPE_C_MASK	0x00000020U /**< DriverType C support */
+#define XSDPS_ECAPS_DRV_TYPE_D_MASK	0x00000040U /**< DriverType D support */
+#define XSDPS_ECAPS_TMR_CNT_MASK	0x00000F00U /**< Timer Count for
+							Re-tuning */
+#define XSDPS_ECAPS_USE_TNG_SDR50_MASK	0x00002000U /**< SDR50 Mode needs
+							tuning */
+#define XSDPS_ECAPS_RE_TNG_MODES_MASK	0x0000C000U /**< Re-tuning modes
+							support */
+#define XSDPS_ECAPS_RE_TNG_MODE1_MASK	0x00000000U /**< Re-tuning mode 1 */
+#define XSDPS_ECAPS_RE_TNG_MODE2_MASK	0x00004000U /**< Re-tuning mode 2 */
+#define XSDPS_ECAPS_RE_TNG_MODE3_MASK	0x00008000U /**< Re-tuning mode 3 */
+#define XSDPS_ECAPS_CLK_MULT_MASK	0x00FF0000U /**< Clock Multiplier value
+							for Programmable clock
+							mode */
+#define XSDPS_ECAPS_SPI_MODE_MASK	0x01000000U /**< SPI mode */
+#define XSDPS_ECAPS_SPI_BLK_MODE_MASK	0x02000000U /**< SPI block mode */
+
+/* @} */
+
+/** @name Present State Register
+ *
+ * Gives the current status of the host controller
+ * Read Only
+ * @{
+ */
+
+#define XSDPS_PSR_INHIBIT_CMD_MASK	0x00000001U /**< Command inhibit - CMD */
+#define XSDPS_PSR_INHIBIT_DAT_MASK	0x00000002U /**< Command Inhibit - DAT */
+#define XSDPS_PSR_DAT_ACTIVE_MASK	0x00000004U /**< DAT line active */
+#define XSDPS_PSR_RE_TUNING_REQ_MASK	0x00000008U /**< Re-tuning request */
+#define XSDPS_PSR_WR_ACTIVE_MASK	0x00000100U /**< Write transfer active */
+#define XSDPS_PSR_RD_ACTIVE_MASK	0x00000200U /**< Read transfer active */
+#define XSDPS_PSR_BUFF_WR_EN_MASK	0x00000400U /**< Buffer write enable */
+#define XSDPS_PSR_BUFF_RD_EN_MASK	0x00000800U /**< Buffer read enable */
+#define XSDPS_PSR_CARD_INSRT_MASK	0x00010000U /**< Card inserted */
+#define XSDPS_PSR_CARD_STABLE_MASK	0x00020000U /**< Card state stable */
+#define XSDPS_PSR_CARD_DPL_MASK		0x00040000U /**< Card detect pin level */
+#define XSDPS_PSR_WPS_PL_MASK		0x00080000U /**< Write protect switch
+								pin level */
+#define XSDPS_PSR_DAT30_SG_LVL_MASK	0x00F00000U /**< Data 3:0 signal lvl */
+#define XSDPS_PSR_CMD_SG_LVL_MASK	0x01000000U /**< Cmd Line signal lvl */
+#define XSDPS_PSR_DAT74_SG_LVL_MASK	0x1E000000U /**< Data 7:4 signal lvl */
+
+/* @} */
+
+/** @name Maximum Current Capablities Register
+ *
+ * This register is read only register which contains
+ * information about current capabilities at each voltage levels.
+ * Read Only
+ * @{
+ */
+#define XSDPS_MAX_CUR_CAPS_1V8_MASK	0x00000F00U /**< Maximum Current
+							Capability at 1.8V */
+#define XSDPS_MAX_CUR_CAPS_3V0_MASK	0x000000F0U /**< Maximum Current
+							Capability at 3.0V */
+#define XSDPS_MAX_CUR_CAPS_3V3_MASK	0x0000000FU /**< Maximum Current
+							Capability at 3.3V */
+/* @} */
+
+
+/** @name Force Event for Auto CMD Error Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events for Auto CMD error status.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_AUTO_CMD12_NT_EX_MASK	0x0001U /**< Auto CMD12 Not
+							executed */
+#define XSDPS_FE_AUTO_CMD_TOUT_MASK	0x0002U /**< Auto CMD Timeout
+							Error */
+#define XSDPS_FE_AUTO_CMD_CRC_MASK	0x0004U /**< Auto CMD CRC Error */
+#define XSDPS_FE_AUTO_CMD_EB_MASK	0x0008U /**< Auto CMD End Bit
+							Error */
+#define XSDPS_FE_AUTO_CMD_IND_MASK	0x0010U /**< Auto CMD Index Error */
+#define XSDPS_FE_AUTO_CMD_CNI_ERR_MASK	0x0080U /**< Command not issued by
+							Auto CMD12 Error */
+/* @} */
+
+
+
+/** @name Force Event for Error Interrupt Status Register
+ *
+ * This register is write only register which contains
+ * control bits to generate events of error interrupt status register.
+ * Write Only
+ * @{
+ */
+#define XSDPS_FE_INTR_ERR_CT_MASK	0x0001U /**< Command Timeout
+							Error */
+#define XSDPS_FE_INTR_ERR_CCRC_MASK	0x0002U /**< Command CRC Error */
+#define XSDPS_FE_INTR_ERR_CEB_MASK	0x0004U /**< Command End Bit
+							Error */
+#define XSDPS_FE_INTR_ERR_CI_MASK	0x0008U /**< Command Index Error */
+#define XSDPS_FE_INTR_ERR_DT_MASK	0x0010U /**< Data Timeout Error */
+#define XSDPS_FE_INTR_ERR_DCRC_MASK	0x0020U /**< Data CRC Error */
+#define XSDPS_FE_INTR_ERR_DEB_MASK	0x0040U /**< Data End Bit Error */
+#define XSDPS_FE_INTR_ERR_CUR_LMT_MASK	0x0080U /**< Current Limit Error */
+#define XSDPS_FE_INTR_ERR_AUTO_CMD_MASK	0x0100U /**< Auto CMD Error */
+#define XSDPS_FE_INTR_ERR_ADMA_MASK	0x0200U /**< ADMA Error */
+#define XSDPS_FE_INTR_ERR_TR_MASK	0x1000U /**< Target Reponse */
+#define XSDPS_FE_INTR_VEND_SPF_ERR_MASK	0xE000U /**< Vendor Specific
+							Error */
+
+/* @} */
+
+/** @name ADMA Error Status Register
+ *
+ * This register is read only register which contains
+ * status information about ADMA errors.
+ * Read Only
+ * @{
+ */
+#define XSDPS_ADMA_ERR_MM_LEN_MASK	0x04U /**< ADMA Length Mismatch
+							Error */
+#define XSDPS_ADMA_ERR_STATE_MASK	0x03U /**< ADMA Error State */
+#define XSDPS_ADMA_ERR_STATE_STOP_MASK	0x00U /**< ADMA Error State
+							STOP */
+#define XSDPS_ADMA_ERR_STATE_FDS_MASK	0x01U /**< ADMA Error State
+							FDS */
+#define XSDPS_ADMA_ERR_STATE_TFR_MASK	0x03U /**< ADMA Error State
+							TFR */
+/* @} */
+
+/** @name Preset Values Register
+ *
+ * This register is read only register which contains
+ * preset values for each of speed modes.
+ * Read Only
+ * @{
+ */
+#define XSDPS_PRE_VAL_SDCLK_FSEL_MASK	0x03FFU /**< SDCLK Frequency
+							Select Value */
+#define XSDPS_PRE_VAL_CLK_GEN_SEL_MASK	0x0400U /**< Clock Generator
+							Mode Select */
+#define XSDPS_PRE_VAL_DRV_STR_SEL_MASK	0xC000U /**< Driver Strength
+							Select Value */
+
+/* @} */
+
+/** @name Slot Interrupt Status Register
+ *
+ * This register is read only register which contains
+ * interrupt slot signal for each slot.
+ * Read Only
+ * @{
+ */
+#define XSDPS_SLOT_INTR_STS_INT_MASK	0x0007U /**< Interrupt Signal
+							mask */
+
+/* @} */
+
+/** @name Host Controller Version Register
+ *
+ * This register is read only register which contains
+ * Host Controller and Vendor Specific version.
+ * Read Only
+ * @{
+ */
+#define XSDPS_HC_VENDOR_VER		0xFF00U /**< Vendor
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_VER_MASK		0x00FFU /**< Host
+							Specification
+							version mask */
+#define XSDPS_HC_SPEC_V3		0x0002U
+#define XSDPS_HC_SPEC_V2		0x0001U
+#define XSDPS_HC_SPEC_V1		0x0000U
+
+/** @name Block size mask for 512 bytes
+ *
+ * Block size mask for 512 bytes - This is the default block size.
+ * @{
+ */
+
+#define XSDPS_BLK_SIZE_512_MASK	0x200U
+
+/* @} */
+
+/** @name Commands
+ *
+ * Constant definitions for commands and response related to SD
+ * @{
+ */
+
+#define XSDPS_APP_CMD_PREFIX	 0x8000U
+#define CMD0	 0x0000U
+#define CMD1	 0x0100U
+#define CMD2	 0x0200U
+#define CMD3	 0x0300U
+#define CMD4	 0x0400U
+#define CMD5	 0x0500U
+#define CMD6	 0x0600U
+#define ACMD6	(XSDPS_APP_CMD_PREFIX + 0x0600U)
+#define CMD7	 0x0700U
+#define CMD8	 0x0800U
+#define CMD9	 0x0900U
+#define CMD10	 0x0A00U
+#define CMD11	 0x0B00U
+#define CMD12	 0x0C00U
+#define ACMD13	 (XSDPS_APP_CMD_PREFIX + 0x0D00U)
+#define CMD16	 0x1000U
+#define CMD17	 0x1100U
+#define CMD18	 0x1200U
+#define CMD19	 0x1300U
+#define CMD21	 0x1500U
+#define CMD23	 0x1700U
+#define ACMD23	 (XSDPS_APP_CMD_PREFIX + 0x1700U)
+#define CMD24	 0x1800U
+#define CMD25	 0x1900U
+#define CMD41	 0x2900U
+#define ACMD41	 (XSDPS_APP_CMD_PREFIX + 0x2900U)
+#define ACMD42	 (XSDPS_APP_CMD_PREFIX + 0x2A00U)
+#define ACMD51	 (XSDPS_APP_CMD_PREFIX + 0x3300U)
+#define CMD52	 0x3400U
+#define CMD55	 0x3700U
+#define CMD58	 0x3A00U
+
+#define RESP_NONE	(u32)XSDPS_CMD_RESP_NONE_MASK
+#define RESP_R1		(u32)XSDPS_CMD_RESP_L48_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK | \
+			(u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R1B	(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+#define RESP_R2		(u32)XSDPS_CMD_RESP_L136_MASK | (u32)XSDPS_CMD_CRC_CHK_EN_MASK
+#define RESP_R3		(u32)XSDPS_CMD_RESP_L48_MASK
+
+#define RESP_R6		(u32)XSDPS_CMD_RESP_L48_BSY_CHK_MASK | \
+			(u32)XSDPS_CMD_CRC_CHK_EN_MASK | (u32)XSDPS_CMD_INX_CHK_EN_MASK
+
+/* @} */
+
+/* Card Interface Conditions Definitions */
+#define XSDPS_CIC_CHK_PATTERN	0xAAU
+#define XSDPS_CIC_VOLT_MASK	(0xFU<<8)
+#define XSDPS_CIC_VOLT_2V7_3V6	(1U<<8)
+#define XSDPS_CIC_VOLT_LOW	(1U<<9)
+
+/* Operation Conditions Register Definitions */
+#define XSDPS_OCR_PWRUP_STS	(1U<<31)
+#define XSDPS_OCR_CC_STS	(1U<<30)
+#define XSDPS_OCR_S18		(1U<<24)
+#define XSDPS_OCR_3V5_3V6	(1U<<23)
+#define XSDPS_OCR_3V4_3V5	(1U<<22)
+#define XSDPS_OCR_3V3_3V4	(1U<<21)
+#define XSDPS_OCR_3V2_3V3	(1U<<20)
+#define XSDPS_OCR_3V1_3V2	(1U<<19)
+#define XSDPS_OCR_3V0_3V1	(1U<<18)
+#define XSDPS_OCR_2V9_3V0	(1U<<17)
+#define XSDPS_OCR_2V8_2V9	(1U<<16)
+#define XSDPS_OCR_2V7_2V8	(1U<<15)
+#define XSDPS_OCR_1V7_1V95	(1U<<7)
+#define XSDPS_OCR_HIGH_VOL	0x00FF8000U
+#define XSDPS_OCR_LOW_VOL	0x00000080U
+
+/* SD Card Configuration Register Definitions */
+#define XSDPS_SCR_REG_LEN		8U
+#define XSDPS_SCR_STRUCT_MASK		(0xFU<<28)
+#define XSDPS_SCR_SPEC_MASK		(0xFU<<24)
+#define XSDPS_SCR_SPEC_1V0		0U
+#define XSDPS_SCR_SPEC_1V1		(1U<<24)
+#define XSDPS_SCR_SPEC_2V0_3V0		(2U<<24)
+#define XSDPS_SCR_MEM_VAL_AF_ERASE	(1U<<23)
+#define XSDPS_SCR_SEC_SUPP_MASK		(7U<<20)
+#define XSDPS_SCR_SEC_SUPP_NONE		0U
+#define XSDPS_SCR_SEC_SUPP_1V1		(2U<<20)
+#define XSDPS_SCR_SEC_SUPP_2V0		(3U<<20)
+#define XSDPS_SCR_SEC_SUPP_3V0		(4U<<20)
+#define XSDPS_SCR_BUS_WIDTH_MASK	(0xFU<<16)
+#define XSDPS_SCR_BUS_WIDTH_1		(1U<<16)
+#define XSDPS_SCR_BUS_WIDTH_4		(4U<<16)
+#define XSDPS_SCR_SPEC3_MASK		(1U<<12)
+#define XSDPS_SCR_SPEC3_2V0		0U
+#define XSDPS_SCR_SPEC3_3V0		(1U<<12)
+#define XSDPS_SCR_CMD_SUPP_MASK		0x3U
+#define XSDPS_SCR_CMD23_SUPP		(1U<<1)
+#define XSDPS_SCR_CMD20_SUPP		(1U<<0)
+
+/* Card Status Register Definitions */
+#define XSDPS_CD_STS_OUT_OF_RANGE	(1U<<31)
+#define XSDPS_CD_STS_ADDR_ERR		(1U<<30)
+#define XSDPS_CD_STS_BLK_LEN_ERR	(1U<<29)
+#define XSDPS_CD_STS_ER_SEQ_ERR		(1U<<28)
+#define XSDPS_CD_STS_ER_PRM_ERR		(1U<<27)
+#define XSDPS_CD_STS_WP_VIO		(1U<<26)
+#define XSDPS_CD_STS_IS_LOCKED		(1U<<25)
+#define XSDPS_CD_STS_LOCK_UNLOCK_FAIL	(1U<<24)
+#define XSDPS_CD_STS_CMD_CRC_ERR	(1U<<23)
+#define XSDPS_CD_STS_ILGL_CMD		(1U<<22)
+#define XSDPS_CD_STS_CARD_ECC_FAIL	(1U<<21)
+#define XSDPS_CD_STS_CC_ERR		(1U<<20)
+#define XSDPS_CD_STS_ERR		(1U<<19)
+#define XSDPS_CD_STS_CSD_OVRWR		(1U<<16)
+#define XSDPS_CD_STS_WP_ER_SKIP		(1U<<15)
+#define XSDPS_CD_STS_CARD_ECC_DIS	(1U<<14)
+#define XSDPS_CD_STS_ER_RST		(1U<<13)
+#define XSDPS_CD_STS_CUR_STATE		(0xFU<<9)
+#define XSDPS_CD_STS_RDY_FOR_DATA	(1U<<8)
+#define XSDPS_CD_STS_APP_CMD		(1U<<5)
+#define XSDPS_CD_STS_AKE_SEQ_ERR	(1U<<2)
+
+/* Switch Function Definitions CMD6 */
+#define XSDPS_SWITCH_SD_RESP_LEN	64U
+
+#define XSDPS_SWITCH_FUNC_SWITCH	(1U<<31)
+#define XSDPS_SWITCH_FUNC_CHECK		0U
+
+#define XSDPS_MODE_FUNC_GRP1		1U
+#define XSDPS_MODE_FUNC_GRP2		2U
+#define XSDPS_MODE_FUNC_GRP3		3U
+#define XSDPS_MODE_FUNC_GRP4		4U
+#define XSDPS_MODE_FUNC_GRP5		5U
+#define XSDPS_MODE_FUNC_GRP6		6U
+
+#define XSDPS_FUNC_GRP_DEF_VAL		0xFU
+#define XSDPS_FUNC_ALL_GRP_DEF_VAL	0xFFFFFFU
+
+#define XSDPS_ACC_MODE_DEF_SDR12	0U
+#define XSDPS_ACC_MODE_HS_SDR25		1U
+#define XSDPS_ACC_MODE_SDR50		2U
+#define XSDPS_ACC_MODE_SDR104		3U
+#define XSDPS_ACC_MODE_DDR50		4U
+
+#define XSDPS_CMD_SYS_ARG_SHIFT		4U
+#define XSDPS_CMD_SYS_DEF		0U
+#define XSDPS_CMD_SYS_eC		1U
+#define XSDPS_CMD_SYS_OTP		3U
+#define XSDPS_CMD_SYS_ASSD		4U
+#define XSDPS_CMD_SYS_VEND		5U
+
+#define XSDPS_DRV_TYPE_ARG_SHIFT	8U
+#define XSDPS_DRV_TYPE_B		0U
+#define XSDPS_DRV_TYPE_A		1U
+#define XSDPS_DRV_TYPE_C		2U
+#define XSDPS_DRV_TYPE_D		3U
+
+#define XSDPS_CUR_LIM_ARG_SHIFT		12U
+#define XSDPS_CUR_LIM_200		0U
+#define XSDPS_CUR_LIM_400		1U
+#define XSDPS_CUR_LIM_600		2U
+#define XSDPS_CUR_LIM_800		3U
+
+#define CSD_SPEC_VER_MASK		0x3C0000U
+
+/* EXT_CSD field definitions */
+#define XSDPS_EXT_CSD_SIZE		512U
+
+#define EXT_CSD_WR_REL_PARAM_EN		(1U<<2)
+
+#define EXT_CSD_BOOT_WP_B_PWR_WP_DIS    (0x40U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_DIS   (0x10U)
+#define EXT_CSD_BOOT_WP_B_PERM_WP_EN    (0x04U)
+#define EXT_CSD_BOOT_WP_B_PWR_WP_EN     (0x01U)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK    (0x7U)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0   (0x1U)
+#define EXT_CSD_PART_CONFIG_ACC_RPMB    (0x3U)
+#define EXT_CSD_PART_CONFIG_ACC_GP0     (0x4U)
+
+#define EXT_CSD_PART_SUPPORT_PART_EN    (0x1U)
+
+#define EXT_CSD_CMD_SET_NORMAL          (1U<<0)
+#define EXT_CSD_CMD_SET_SECURE          (1U<<1)
+#define EXT_CSD_CMD_SET_CPSECURE        (1U<<2)
+
+#define EXT_CSD_CARD_TYPE_26    	(1U<<0)  /* Card can run at 26MHz */
+#define EXT_CSD_CARD_TYPE_52    	(1U<<1)  /* Card can run at 52MHz */
+#define EXT_CSD_CARD_TYPE_MASK  	0x3FU    /* Mask out reserved bits */
+#define EXT_CSD_CARD_TYPE_DDR_1_8V	(1U<<2)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.8V or 3V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_1_2V	(1U<<3)   /* Card can run at 52MHz */
+                                             /* DDR mode @1.2V I/O */
+#define EXT_CSD_CARD_TYPE_DDR_52	(EXT_CSD_CARD_TYPE_DDR_1_8V  \
+                                        | EXT_CSD_CARD_TYPE_DDR_1_2V)
+#define EXT_CSD_CARD_TYPE_SDR_1_8V      (1U<<4)  /* Card can run at 200MHz */
+#define EXT_CSD_CARD_TYPE_SDR_1_2V      (1U<<5)  /* Card can run at 200MHz */
+                                                /* SDR mode @1.2V I/O */
+#define EXT_CSD_BUS_WIDTH_BYTE			183U
+#define EXT_CSD_BUS_WIDTH_1_BIT			0U	/* Card is in 1 bit mode */
+#define EXT_CSD_BUS_WIDTH_4_BIT			1U	/* Card is in 4 bit mode */
+#define EXT_CSD_BUS_WIDTH_8_BIT			2U	/* Card is in 8 bit mode */
+#define EXT_CSD_BUS_WIDTH_DDR_4_BIT		5U	/* Card is in 4 bit DDR mode */
+#define EXT_CSD_BUS_WIDTH_DDR_8_BIT		6U	/* Card is in 8 bit DDR mode */
+
+#define EXT_CSD_HS_TIMING_BYTE		185U
+#define EXT_CSD_HS_TIMING_DEF		0U
+#define EXT_CSD_HS_TIMING_HIGH		1U	/* Card is in high speed mode */
+#define EXT_CSD_HS_TIMING_HS200		2U	/* Card is in HS200 mode */
+
+
+#define XSDPS_EXT_CSD_CMD_SET		0U
+#define XSDPS_EXT_CSD_SET_BITS		1U
+#define XSDPS_EXT_CSD_CLR_BITS		2U
+#define XSDPS_EXT_CSD_WRITE_BYTE	3U
+
+#define XSDPS_MMC_DEF_SPEED_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					| ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					| ((u32)EXT_CSD_HS_TIMING_DEF << 8))
+
+#define XSDPS_MMC_HIGH_SPEED_ARG	(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HIGH << 8))
+
+#define XSDPS_MMC_HS200_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_HS_TIMING_BYTE << 16) \
+					 | ((u32)EXT_CSD_HS_TIMING_HS200 << 8))
+
+#define XSDPS_MMC_1_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WITH_1_BIT << 8))
+
+#define XSDPS_MMC_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_4_BIT << 8))
+
+#define XSDPS_MMC_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_8_BIT << 8))
+
+#define XSDPS_MMC_DDR_4_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_4_BIT << 8))
+
+#define XSDPS_MMC_DDR_8_BIT_BUS_ARG		(((u32)XSDPS_EXT_CSD_WRITE_BYTE << 24) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_BYTE << 16) \
+					 | ((u32)EXT_CSD_BUS_WIDTH_DDR_8_BIT << 8))
+
+#define XSDPS_MMC_DELAY_FOR_SWITCH	1000U
+
+/* @} */
+
+/* @400KHz, in usec */
+#define XSDPS_74CLK_DELAY	2960U
+#define XSDPS_100CLK_DELAY	4000U
+#define XSDPS_INIT_DELAY	10000U
+
+#define XSDPS_DEF_VOLT_LVL	XSDPS_PC_BUS_VSEL_3V0_MASK
+#define XSDPS_CARD_DEF_ADDR	0x1234U
+
+#define XSDPS_CARD_SD		1U
+#define XSDPS_CARD_MMC		2U
+#define XSDPS_CARD_SDIO		3U
+#define XSDPS_CARD_SDCOMBO	4U
+#define XSDPS_CHIP_EMMC		5U
+
+
+/** @name ADMA2 Descriptor related definitions
+ *
+ * ADMA2 Descriptor related definitions
+ * @{
+ */
+
+#define XSDPS_DESC_MAX_LENGTH 65536U
+
+#define XSDPS_DESC_VALID     	(0x1U << 0)
+#define XSDPS_DESC_END       	(0x1U << 1)
+#define XSDPS_DESC_INT       	(0x1U << 2)
+#define XSDPS_DESC_TRAN  	(0x2U << 4)
+
+/* @} */
+
+/* For changing clock frequencies */
+#define XSDPS_CLK_400_KHZ		400000U		/**< 400 KHZ */
+#define XSDPS_CLK_50_MHZ		50000000U	/**< 50 MHZ */
+#define XSDPS_CLK_52_MHZ		52000000U	/**< 52 MHZ */
+#define XSDPS_SD_VER_1_0		0x1U		/**< SD ver 1 */
+#define XSDPS_SD_VER_2_0		0x2U		/**< SD ver 2 */
+#define XSDPS_SCR_BLKCNT	1U
+#define XSDPS_SCR_BLKSIZE	8U
+#define XSDPS_1_BIT_WIDTH	0x1U
+#define XSDPS_4_BIT_WIDTH	0x2U
+#define XSDPS_8_BIT_WIDTH	0x3U
+#define XSDPS_UHS_SPEED_MODE_SDR12	0x0U
+#define XSDPS_UHS_SPEED_MODE_SDR25	0x1U
+#define XSDPS_UHS_SPEED_MODE_SDR50	0x2U
+#define XSDPS_UHS_SPEED_MODE_SDR104	0x3U
+#define XSDPS_UHS_SPEED_MODE_DDR50	0x4U
+#define XSDPS_SWITCH_CMD_BLKCNT		1U
+#define XSDPS_SWITCH_CMD_BLKSIZE	64U
+#define XSDPS_SWITCH_CMD_HS_GET		0x00FFFFF0U
+#define XSDPS_SWITCH_CMD_HS_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR12_SET		0x80FFFFF0U
+#define XSDPS_SWITCH_CMD_SDR25_SET		0x80FFFFF1U
+#define XSDPS_SWITCH_CMD_SDR50_SET		0x80FFFFF2U
+#define XSDPS_SWITCH_CMD_SDR104_SET		0x80FFFFF3U
+#define XSDPS_SWITCH_CMD_DDR50_SET		0x80FFFFF4U
+#define XSDPS_EXT_CSD_CMD_BLKCNT	1U
+#define XSDPS_EXT_CSD_CMD_BLKSIZE	512U
+#define XSDPS_TUNING_CMD_BLKCNT		1U
+#define XSDPS_TUNING_CMD_BLKSIZE	64U
+
+#define XSDPS_HIGH_SPEED_MAX_CLK	50000000U
+#define XSDPS_UHS_SDR104_MAX_CLK	208000000U
+#define XSDPS_UHS_SDR50_MAX_CLK		100000000U
+#define XSDPS_UHS_DDR50_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR25_MAX_CLK		50000000U
+#define XSDPS_UHS_SDR12_MAX_CLK		25000000U
+
+#define SD_DRIVER_TYPE_B	0x01U
+#define SD_DRIVER_TYPE_A	0x02U
+#define SD_DRIVER_TYPE_C	0x04U
+#define SD_DRIVER_TYPE_D	0x08U
+#define SD_SET_CURRENT_LIMIT_200	0U
+#define SD_SET_CURRENT_LIMIT_400	1U
+#define SD_SET_CURRENT_LIMIT_600	2U
+#define SD_SET_CURRENT_LIMIT_800	3U
+
+#define SD_MAX_CURRENT_200	(1U << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400	(1U << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600	(1U << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800	(1U << SD_SET_CURRENT_LIMIT_800)
+
+#define XSDPS_SD_SDR12_MAX_CLK	25000000U
+#define XSDPS_SD_SDR25_MAX_CLK	50000000U
+#define XSDPS_SD_SDR50_MAX_CLK	100000000U
+#define XSDPS_SD_DDR50_MAX_CLK	50000000U
+#define XSDPS_SD_SDR104_MAX_CLK	208000000U
+#define XSDPS_MMC_HS200_MAX_CLK	200000000U
+
+#define XSDPS_CARD_STATE_IDLE		0U
+#define XSDPS_CARD_STATE_RDY		1U
+#define XSDPS_CARD_STATE_IDEN		2U
+#define XSDPS_CARD_STATE_STBY		3U
+#define XSDPS_CARD_STATE_TRAN		4U
+#define XSDPS_CARD_STATE_DATA		5U
+#define XSDPS_CARD_STATE_RCV		6U
+#define XSDPS_CARD_STATE_PROG		7U
+#define XSDPS_CARD_STATE_DIS		8U
+#define XSDPS_CARD_STATE_BTST		9U
+#define XSDPS_CARD_STATE_SLP		10U
+
+#define XSDPS_SLOT_REM			0U
+#define XSDPS_SLOT_EMB			1U
+
+#if defined (__arm__) || defined (__aarch64__)
+#define SD_DLL_CTRL 			0x00000358U
+#define SD_ITAPDLY				0x00000314U
+#define SD_OTAPDLYSEL			0x00000318U
+#define SD0_DLL_RST				0x00000004U
+#define SD0_ITAPCHGWIN			0x00000200U
+#define SD0_ITAPDLYENA			0x00000100U
+#define SD0_OTAPDLYENA			0x00000040U
+#define SD0_OTAPDLYSEL_HS200	0x00000003U
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+#define XSdPs_In64 Xil_In64
+#define XSdPs_Out64 Xil_Out64
+
+#define XSdPs_In32 Xil_In32
+#define XSdPs_Out32 Xil_Out32
+
+#define XSdPs_In16 Xil_In16
+#define XSdPs_Out16 Xil_Out16
+
+#define XSdPs_In8 Xil_In8
+#define XSdPs_Out8 Xil_Out8
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(XSdPs *InstancePtr. s32 RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg64(InstancePtr, RegOffset) \
+	XSdPs_In64((InstancePtr->Config.BaseAddress) + RegOffset)
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(XSdPs *InstancePtr, s32 RegOffset,
+*		u64 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg64(InstancePtr, RegOffset, RegisterValue) \
+	XSdPs_Out64((InstancePtr->Config.BaseAddress) + (RegOffset), \
+		(RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg(BaseAddress, RegOffset) \
+	XSdPs_In32((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u32 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out32((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg16(BaseAddress, RegOffset) \
+	XSdPs_In16((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u16 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg16(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out16((BaseAddress) + (RegOffset), (RegisterValue))
+
+/****************************************************************************/
+/**
+* Read a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to the target register.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u8 XSdPs_ReadReg(u32 BaseAddress. int RegOffset)
+*
+******************************************************************************/
+#define XSdPs_ReadReg8(BaseAddress, RegOffset) \
+	XSdPs_In8((BaseAddress) + (RegOffset))
+
+/***************************************************************************/
+/**
+* Write to a register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the 1st register of the
+*		device to target register.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_WriteReg8(BaseAddress, RegOffset, RegisterValue) \
+	XSdPs_Out8((BaseAddress) + (RegOffset), (RegisterValue))
+
+/***************************************************************************/
+/**
+* Macro to get present status register
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XSdPs_WriteReg(u32 BaseAddress, int RegOffset,
+*		u8 RegisterValue)
+*
+******************************************************************************/
+#define XSdPs_GetPresentStatusReg(BaseAddress) \
+		XSdPs_In32((BaseAddress) + (XSDPS_PRES_STATE_OFFSET))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SD_HW_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_options.c
new file mode 100644
index 000000000..8151eef1b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_options.c
@@ -0,0 +1,1152 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_options.c
+* @addtogroup sdps_v2_5
+* @{
+*
+* Contains API's for changing the various options in host and card.
+* See xsdps.h for a detailed description of the device and driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+* 2.1   hk     04/18/14 Increase sleep for eMMC switch command.
+*                       Add sleep for microblaze designs. CR# 781117.
+* 2.3   sk     09/23/14 Use XSdPs_Change_ClkFreq API whenever changing
+*						clock.CR# 816586.
+* 2.5 	sg	   07/09/15 Added SD 3.0 features
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+* 2.7   sk     01/08/16 Added workaround for issue in auto tuning mode
+*                       of SDR50, SDR104 and HS200.
+*       sk     02/16/16 Corrected the Tuning logic.
+*       sk     03/02/16 Configured the Tap Delay values for eMMC HS200 mode.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xsdps.h"
+/*
+ * The header sleep.h and API usleep() can only be used with an arm design.
+ * MB_Sleep() is used for microblaze design.
+ */
+#if defined (__arm__) || defined (__aarch64__)
+
+#include "sleep.h"
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+#include "microblaze_sleep.h"
+
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+s32 XSdPs_CmdTransfer(XSdPs *InstancePtr, u32 Cmd, u32 Arg, u32 BlkCnt);
+void XSdPs_SetupADMA2DescTbl(XSdPs *InstancePtr, u32 BlkCnt, const u8 *Buff);
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr);
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode);
+#if defined (__arm__) || defined (__aarch64__)
+void XSdPs_SetTapDelay(XSdPs *InstancePtr);
+#endif
+
+/*****************************************************************************/
+/**
+* Update Block size for read/write operations.
+*
+* @param	InstancePtr is a pointer to the instance to be worked on.
+* @param	BlkSize - Block size passed by the user.
+*
+* @return	None
+*
+******************************************************************************/
+s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize)
+{
+	s32 Status;
+	u32 PresentStateReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	PresentStateReg = XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_PRES_STATE_OFFSET);
+
+	if ((PresentStateReg & ((u32)XSDPS_PSR_INHIBIT_CMD_MASK |
+			(u32)XSDPS_PSR_INHIBIT_DAT_MASK |
+			(u32)XSDPS_PSR_WR_ACTIVE_MASK | (u32)XSDPS_PSR_RD_ACTIVE_MASK)) != 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD16, BlkSize, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	/* Set block size to the value passed */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			 BlkSize & XSDPS_BLK_SIZE_MASK);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus width support by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SCR - buffer to store SCR register returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *SCR)
+{
+	s32 Status;
+	u32 StatusReg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 8; LoopCnt++) {
+		SCR[LoopCnt] = 0U;
+	}
+
+	/* Send block write command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	BlkCnt = XSDPS_SCR_BLKCNT;
+	BlkSize = XSDPS_SCR_BLKSIZE;
+
+	/* Set block size to the value passed */
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, SCR);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Xil_DCacheInvalidateRange((INTPTR)SCR, 8);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD51, 0U, BlkCnt);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set bus width to 4-bit in card and host
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD55, InstancePtr->RelCardAddr,
+				0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+
+		Arg = ((u32)InstancePtr->BusWidth);
+
+		Status = XSdPs_CmdTransfer(InstancePtr, ACMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+
+		if ((InstancePtr->HC_Version == XSDPS_HC_SPEC_V3)
+				&& (InstancePtr->CardType == XSDPS_CHIP_EMMC)) {
+			/* in case of eMMC data width 8-bit */
+			InstancePtr->BusWidth = XSDPS_8_BIT_WIDTH;
+		} else {
+			InstancePtr->BusWidth = XSDPS_4_BIT_WIDTH;
+		}
+
+		if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+			Arg = XSDPS_MMC_8_BIT_BUS_ARG;
+		} else {
+			Arg = XSDPS_MMC_4_BIT_BUS_ARG;
+		}
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/* Check for transfer complete */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/* Write to clear error bits */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/* Write to clear bit */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+	}
+
+#if defined (__arm__) || defined (__aarch64__)
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	/* 2 msec delay */
+	MB_Sleep(2);
+
+#endif
+
+	StatusReg = XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+
+	/* Width setting in controller */
+	if (InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH) {
+		StatusReg |= XSDPS_HC_EXT_BUS_WIDTH;
+	} else {
+		StatusReg |= XSDPS_HC_WIDTH_MASK;
+	}
+
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET,
+			(u8)StatusReg);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get bus speed supported by card.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store function group support data
+*		returned by card.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 64; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0U;
+	}
+
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	Arg = XSDPS_SWITCH_CMD_HS_GET;
+
+	Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 64);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to set high speed in card and host. Changes clock in host accordingly.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+	u32 ClockReg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	u8 ReadBuff[64];
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	if (InstancePtr->CardType == XSDPS_CARD_SD) {
+
+		BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+		BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+		BlkSize &= XSDPS_BLK_SIZE_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+		XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+		Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_XFER_MODE_OFFSET,
+				XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+		Arg = XSDPS_SWITCH_CMD_HS_SET;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 * Polling for response for now
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/* Write to clear error bits */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/* Write to clear bit */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 50 MHz */
+		InstancePtr->BusSpeed = XSDPS_CLK_50_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+		}
+
+	} else if (InstancePtr->CardType == XSDPS_CARD_MMC) {
+		Arg = XSDPS_MMC_HIGH_SPEED_ARG;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/*
+				 * Write to clear error bits
+				 */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/*
+		 * Write to clear bit
+		 */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 52 MHz */
+		InstancePtr->BusSpeed = XSDPS_CLK_52_MHZ;
+		Status = XSdPs_Change_ClkFreq(InstancePtr, XSDPS_CLK_52_MHZ);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		Arg = XSDPS_MMC_HS200_ARG;
+
+		Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 0U);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		/*
+		 * Check for transfer complete
+		 */
+		do {
+			StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_NORM_INTR_STS_OFFSET);
+			if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+				/*
+				 * Write to clear error bits
+				 */
+				XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+						XSDPS_ERR_INTR_STS_OFFSET,
+						XSDPS_ERROR_INTR_ALL_MASK);
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+			}
+		} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+		/*
+		 * Write to clear bit
+		 */
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+		/* Change the clock frequency to 200 MHz */
+		InstancePtr->BusSpeed = XSDPS_MMC_HS200_MAX_CLK;
+
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+		Status = XSdPs_Execute_Tuning(InstancePtr);
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+#if defined (__arm__) || defined (__aarch64__)
+		/* Program the Tap delays */
+		XSdPs_SetTapDelay(InstancePtr);
+#endif
+	}
+
+#if defined (__arm__) || defined (__aarch64__)
+
+	usleep(XSDPS_MMC_DELAY_FOR_SWITCH);
+
+#endif
+
+#ifdef __MICROBLAZE__
+
+	/* 2 msec delay */
+	MB_Sleep(2);
+
+#endif
+
+	StatusReg = (s32)XSdPs_ReadReg8(InstancePtr->Config.BaseAddress,
+					XSDPS_HOST_CTRL1_OFFSET);
+	StatusReg |= XSDPS_HC_SPEED_MASK;
+	XSdPs_WriteReg8(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL1_OFFSET, (u8)StatusReg);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to change clock freq to given value.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	SelFreq - Clock frequency in Hz.
+*
+* @return	None
+*
+* @note		This API will change clock frequency to the value less than
+*		or equal to the given value using the permissible dividors.
+*
+******************************************************************************/
+s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq)
+{
+	u16 ClockReg;
+	u16 DivCnt;
+	u16 Divisor = 0U;
+	u16 ExtDivisor;
+	u16 ClkLoopCnt;
+	s32 Status;
+	u16 ReadReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	ClockReg &= ~(XSDPS_CC_SD_CLK_EN_MASK | XSDPS_CC_INT_CLK_EN_MASK);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET, ClockReg);
+
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+		/* Calculate divisor */
+		for (DivCnt = 0x1U; DivCnt <= XSDPS_CC_EXT_MAX_DIV_CNT;DivCnt++) {
+			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+				Divisor = DivCnt >> 1;
+				break;
+			}
+		}
+
+		if (DivCnt > XSDPS_CC_EXT_MAX_DIV_CNT) {
+			/* No valid divisor found for given frequency */
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} else {
+		/* Calculate divisor */
+		DivCnt = 0x1U;
+		while (DivCnt <= XSDPS_CC_MAX_DIV_CNT) {
+			if (((InstancePtr->Config.InputClockHz) / DivCnt) <= SelFreq) {
+				Divisor = DivCnt / 2U;
+				break;
+			}
+			DivCnt = DivCnt << 1U;
+		}
+
+		if (DivCnt > XSDPS_CC_MAX_DIV_CNT) {
+			/* No valid divisor found for given frequency */
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	}
+
+	/* Set clock divisor */
+	if (InstancePtr->HC_Version == XSDPS_HC_SPEC_V3) {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+		ClockReg &= ~(XSDPS_CC_SDCLK_FREQ_SEL_MASK |
+		XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK);
+
+		ExtDivisor = Divisor >> 8;
+		ExtDivisor <<= XSDPS_CC_EXT_DIV_SHIFT;
+		ExtDivisor &= XSDPS_CC_SDCLK_FREQ_SEL_EXT_MASK;
+
+		Divisor <<= XSDPS_CC_DIV_SHIFT;
+		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+		ClockReg |= Divisor | ExtDivisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+				ClockReg);
+	} else {
+		ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+		ClockReg &= (~XSDPS_CC_SDCLK_FREQ_SEL_MASK);
+
+		Divisor <<= XSDPS_CC_DIV_SHIFT;
+		Divisor &= XSDPS_CC_SDCLK_FREQ_SEL_MASK;
+		ClockReg |= Divisor | (u16)XSDPS_CC_INT_CLK_EN_MASK;
+		XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_CLK_CTRL_OFFSET,
+				ClockReg);
+	}
+
+	/* Wait for internal clock to stabilize */
+	ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_CLK_CTRL_OFFSET);
+	while((ReadReg & XSDPS_CC_INT_CLK_STABLE_MASK) == 0U) {
+		ReadReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_CLK_CTRL_OFFSET);;
+	}
+
+	/* Enable SD clock */
+	ClockReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET);
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_CLK_CTRL_OFFSET,
+			ClockReg | XSDPS_CC_SD_CLK_EN_MASK);
+
+	Status = XST_SUCCESS;
+
+RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to send pullup command to card before using DAT line 3(using 4-bit bus)
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Pullup(XSdPs *InstancePtr)
+{
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD55,
+			InstancePtr->RelCardAddr, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, ACMD42, 0U, 0U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* API to get EXT_CSD register of eMMC.
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	ReadBuff - buffer to store EXT_CSD
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg = 0U;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	for (LoopCnt = 0; LoopCnt < 512; LoopCnt++) {
+		ReadBuff[LoopCnt] = 0U;
+	}
+
+	BlkCnt = XSDPS_EXT_CSD_CMD_BLKCNT;
+	BlkSize = XSDPS_EXT_CSD_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_BLK_SIZE_OFFSET, BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	Xil_DCacheInvalidateRange((INTPTR)ReadBuff, 512U);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+
+	/* Send SEND_EXT_CSD command */
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD8, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET,
+					XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+	Status = (s32)XSdPs_ReadReg(InstancePtr->Config.BaseAddress,
+			XSDPS_RESP0_OFFSET);
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+
+}
+
+
+/*****************************************************************************/
+/**
+*
+* API to UHS-I mode initialization
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+* @param	Mode UHS-I mode
+*
+* @return
+*		- XST_SUCCESS if successful.
+*		- XST_FAILURE if fail.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XSdPs_Uhs_ModeInit(XSdPs *InstancePtr, u8 Mode)
+{
+	s32 Status;
+	u16 StatusReg;
+	u16 CtrlReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	u8 ReadBuff[64];
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Drive strength */
+
+	/* Bus speed mode selection */
+	BlkCnt = XSDPS_SWITCH_CMD_BLKCNT;
+	BlkSize = XSDPS_SWITCH_CMD_BLKSIZE;
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			BlkSize);
+
+	XSdPs_SetupADMA2DescTbl(InstancePtr, BlkCnt, ReadBuff);
+
+	Xil_DCacheFlushRange((INTPTR)ReadBuff, 64);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK | XSDPS_TM_DMA_EN_MASK);
+
+	switch (Mode) {
+	case 0U:
+		Arg = XSDPS_SWITCH_CMD_SDR12_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR12_MAX_CLK;
+		break;
+	case 1U:
+		Arg = XSDPS_SWITCH_CMD_SDR25_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR25_MAX_CLK;
+		break;
+	case 2U:
+		Arg = XSDPS_SWITCH_CMD_SDR50_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR50_MAX_CLK;
+		break;
+	case 3U:
+		Arg = XSDPS_SWITCH_CMD_SDR104_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_SDR104_MAX_CLK;
+		break;
+	case 4U:
+		Arg = XSDPS_SWITCH_CMD_DDR50_SET;
+		InstancePtr->BusSpeed = XSDPS_SD_DDR50_MAX_CLK;
+		break;
+	default:
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+		break;
+	}
+
+	Status = XSdPs_CmdTransfer(InstancePtr, CMD6, Arg, 1U);
+	if (Status != XST_SUCCESS) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * Check for transfer complete
+	 * Polling for response for now
+	 */
+	do {
+		StatusReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_NORM_INTR_STS_OFFSET);
+		if ((StatusReg & XSDPS_INTR_ERR_MASK) != 0U) {
+			/* Write to clear error bits */
+			XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+					XSDPS_ERR_INTR_STS_OFFSET, XSDPS_ERROR_INTR_ALL_MASK);
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+	} while ((StatusReg & XSDPS_INTR_TC_MASK) == 0U);
+
+	/* Write to clear bit */
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_NORM_INTR_STS_OFFSET, XSDPS_INTR_TC_MASK);
+
+
+	/* Current limit */
+
+	/* Set UHS mode in controller */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg &= (u16)(~XSDPS_HC2_UHS_MODE_MASK);
+	CtrlReg |= Mode;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+	/* Change the clock frequency */
+	Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+	if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+	}
+
+	if((Mode == XSDPS_UHS_SPEED_MODE_SDR104) ||
+			(Mode == XSDPS_UHS_SPEED_MODE_DDR50)) {
+		/* Send tuning pattern */
+		Status = XSdPs_Execute_Tuning(InstancePtr);
+		if (Status != XST_SUCCESS) {
+				Status = XST_FAILURE;
+				goto RETURN_PATH;
+		}
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH:
+		return Status;
+}
+
+static s32 XSdPs_Execute_Tuning(XSdPs *InstancePtr)
+{
+	s32 Status;
+	u32 StatusReg;
+	u32 Arg;
+	u16 BlkCnt;
+	u16 BlkSize;
+	s32 LoopCnt;
+	u16 CtrlReg;
+	u8 TuningCount;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	BlkCnt = XSDPS_TUNING_CMD_BLKCNT;
+	BlkSize = XSDPS_TUNING_CMD_BLKSIZE;
+	if(InstancePtr->BusWidth == XSDPS_8_BIT_WIDTH)
+	{
+		BlkSize = BlkSize*2U;
+	}
+	BlkSize &= XSDPS_BLK_SIZE_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_BLK_SIZE_OFFSET,
+			BlkSize);
+
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress, XSDPS_XFER_MODE_OFFSET,
+			XSDPS_TM_DAT_DIR_SEL_MASK);
+
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET);
+	CtrlReg |= XSDPS_HC2_EXEC_TNG_MASK;
+	XSdPs_WriteReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET, CtrlReg);
+
+	for (TuningCount = 0U; TuningCount < MAX_TUNING_COUNT; TuningCount++) {
+
+		if (InstancePtr->CardType == XSDPS_CARD_SD) {
+			Status = XSdPs_CmdTransfer(InstancePtr, CMD19, 0U, 1U);
+		} else {
+			Status = XSdPs_CmdTransfer(InstancePtr, CMD21, 0U, 1U);
+		}
+
+		if (Status != XST_SUCCESS) {
+			Status = XST_FAILURE;
+			goto RETURN_PATH;
+		}
+
+		if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_EXEC_TNG_MASK) == 0U) {
+			break;
+		}
+	}
+
+	if ((XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+			XSDPS_HOST_CTRL2_OFFSET) & XSDPS_HC2_SAMP_CLK_SEL_MASK) == 0U) {
+		Status = XST_FAILURE;
+		goto RETURN_PATH;
+	}
+
+	/*
+	 * As per controller erratum, program the "SDCLK Frequency
+	 * Select" of clock control register with a value, say
+	 * clock/2. Wait for the Internal clock stable and program
+	 * the desired frequency.
+	 */
+	CtrlReg = XSdPs_ReadReg16(InstancePtr->Config.BaseAddress,
+				XSDPS_HOST_CTRL2_OFFSET);
+	if ((CtrlReg & XSDPS_HC2_SAMP_CLK_SEL_MASK) != 0U) {
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed/2);
+		if (Status != XST_SUCCESS) {
+			goto RETURN_PATH ;
+		}
+		Status = XSdPs_Change_ClkFreq(InstancePtr, InstancePtr->BusSpeed);
+		if (Status != XST_SUCCESS) {
+			goto RETURN_PATH ;
+		}
+
+	}
+
+	Status = XST_SUCCESS;
+
+	RETURN_PATH: return Status;
+
+}
+
+#if defined (__arm__) || defined (__aarch64__)
+/*****************************************************************************/
+/**
+*
+* API to set Tap Delay w.r.t speed modes
+*
+*
+* @param	InstancePtr is a pointer to the XSdPs instance.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XSdPs_SetTapDelay(XSdPs *InstancePtr)
+{
+	u32 DllCtrl, TapDelay;
+	if (InstancePtr->Config.DeviceId == XPAR_XSDPS_0_DEVICE_ID) {
+		DllCtrl = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL);
+		DllCtrl |= SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+		if(InstancePtr->BusSpeed == XSDPS_MMC_HS200_MAX_CLK) {
+			/* Program the ITAPDLY */
+			TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY);
+			TapDelay |= SD0_ITAPCHGWIN;
+			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+			TapDelay |= SD0_ITAPDLYENA;
+			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+			TapDelay &= ~SD0_ITAPCHGWIN;
+			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_ITAPDLY, TapDelay);
+			/* Program the OTAPDLY */
+			TapDelay = XSdPs_ReadReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL);
+			TapDelay |= SD0_OTAPDLYENA;
+			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL, TapDelay);
+			TapDelay |= SD0_OTAPDLYSEL_HS200;
+			XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_OTAPDLYSEL, TapDelay);
+		}
+		DllCtrl &= ~SD0_DLL_RST;
+		XSdPs_WriteReg(XPS_SYS_CTRL_BASEADDR, SD_DLL_CTRL, DllCtrl);
+	}
+}
+#endif
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_sinit.c
new file mode 100644
index 000000000..59657a7b3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sdps_v2_7/src/xsdps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2013 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsdps_sinit.c
+* @addtogroup sdps_v2_5
+* @{
+*
+* The implementation of the XSdPs component's static initialization
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ---    -------- -----------------------------------------------
+* 1.00a hk/sg  10/17/13 Initial release
+*       kvn    07/15/15 Modified the code according to MISRAC-2012.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+#include "xstatus.h"
+#include "xsdps.h"
+#include "xparameters.h"
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XSdPs_Config XSdPs_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device to look up the
+*		configuration for.
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xsdps.h for the definition of XSdPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId)
+{
+	XSdPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XSDPS_NUM_INSTANCES; Index++) {
+		if (XSdPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XSdPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XSdPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/Makefile
new file mode 100644
index 000000000..ca8621a76
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/Makefile
@@ -0,0 +1,74 @@
+###############################################################################
+#
+# Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# Use of the Software is limited solely to applications:
+# (a) running on a Xilinx device, or
+# (b) that interact with a Xilinx device through a bus or interconnect.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+# XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+# WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+# OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+#
+# Except as contained in this notice, the name of the Xilinx shall not be used
+# in advertising or otherwise to promote the sale, use or other dealings in
+# this Software without prior written authorization from Xilinx.
+#
+###############################################################################
+
+include config.make
+CC=$(COMPILER)
+AR=$(ARCHIVER)
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(subst -pg, -DPROFILING, $(COMPILER_FLAGS))
+ECC_FLAGS = $(subst -pg, -DPROFILING, $(EXTRA_COMPILER_FLAGS))
+
+ifeq ($(notdir $(CC)), armr5-none-eabi-gcc)
+ECC_FLAGS	+= -nostartfiles\
+		  -mfloat-abi=soft\
+		  -mfpu=vfpv3-d16
+endif
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+INCLUDEFILES=*.h
+INCLUDEFILES+=includes_ps/*.h
+
+libs: $(LIBS)
+
+standalone_libs: $(LIBSOURCES)
+	echo "Compiling standalone R5"
+	$(CC) $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) $^
+	$(AR) -r ${RELEASEDIR}/${LIB} ${OUTS}
+
+.PHONY: include
+include: standalone_includes
+
+standalone_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OUTS}
+	$(MAKE) -C COMPILER_FLAGS="$(COMPILER_FLAGS)" EXTRA_COMPILER_FLAGS="$(EXTRA_COMPILER_FLAGS)" COMPILER="$(CC)" ARCHIVER="$(AR)" clean
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_exit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_exit.c
new file mode 100644
index 000000000..0086c59b0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_exit.c
@@ -0,0 +1,87 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+/*
+ * _exit - Does not return.
+ *
+ * If R5 application runs in lock-step mode, the comparators are enabled by
+ * boot code after resetting the debug logic. The debugger does not have access
+ * while the R5 application is being run to avoid any intervention. After the
+ * application runs, the debug logic need to be taken out of reset for the
+ * debugger to gain access. Therefore the debug logic is enabled and
+ * comparators are disabled in case of R5 running in lock-step mode with
+ * debug logic reset in JTAG boot mode.
+ */
+
+#define RPU_GLBL_CNTL_REG	0xFF9A0000U
+#define RPU_ERR_INJ_REG		0xFF9A0020U
+#define RST_LPD_DBG_REG		0xFF5E0240U
+#define BOOT_MODE_USER_REG	0xFF5E0200U
+
+#define lock_step 			0x00000008U
+#define fault_log_enable	0x00000101U
+#define debug_reset 		0x00000032U
+#define jtag_boot			0x0000000FU
+__attribute__((weak)) void _exit (sint32 status)
+{
+
+	/*
+	 * Enables the debug logic and disable the comparators
+	 * when in JTAG boot mode and R5 is in lock-step mode
+	 * if the fault log is enabled
+	 */
+	u32 debug_reg, err_inj_reg;
+	if((Xil_In32(BOOT_MODE_USER_REG) & jtag_boot) == 0){
+		if((Xil_In32(RPU_GLBL_CNTL_REG) & lock_step) == 0){
+			if((Xil_In32(RPU_ERR_INJ_REG) & fault_log_enable) != 0) {
+				if((Xil_In32(RST_LPD_DBG_REG) & debug_reset) != 0) {
+					err_inj_reg = Xil_In32(RPU_ERR_INJ_REG);
+					err_inj_reg = err_inj_reg & (~fault_log_enable);
+					Xil_Out32(RPU_ERR_INJ_REG, err_inj_reg);
+
+					debug_reg = Xil_In32(RST_LPD_DBG_REG);
+					debug_reg = debug_reg & (~debug_reset);
+					Xil_Out32(RST_LPD_DBG_REG, debug_reg);
+				}
+			}
+		}
+	}
+
+  (void)status;
+  while (1)
+  {
+     __asm__("wfi");
+  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_open.c
new file mode 100644
index 000000000..b2809c5d0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_open.c
@@ -0,0 +1,53 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode);
+}
+#endif
+
+/*
+ * _open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 _open(const char8 *buf, s32 flags, s32 mode)
+{
+  (void *)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_sbrk.c
new file mode 100644
index 000000000..bcec069c8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/_sbrk.c
@@ -0,0 +1,70 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) caddr_t _sbrk ( s32 incr );
+}
+#endif
+
+__attribute__((weak)) caddr_t _sbrk ( s32 incr )
+{
+  static u8 *heap = NULL;
+  u8 *prev_heap;
+  static u8 *HeapEndPtr = (u8 *)&_heap_end;
+  caddr_t Status;
+
+  if (heap == NULL) {
+    heap = (u8 *)&_heap_start;
+  }
+  prev_heap = heap;
+
+  heap += incr;
+
+  if (heap > HeapEndPtr){
+	  Status = (caddr_t) -1;
+  }
+  else if (prev_heap != NULL) {
+	  Status = (caddr_t) ((void *)prev_heap);
+  }
+  else {
+	  Status = (caddr_t) -1;
+  }
+
+  return Status;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/abort.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/abort.c
new file mode 100644
index 000000000..122c25bbd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/abort.c
@@ -0,0 +1,42 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include 
+
+/*
+ * abort -- go out via exit...
+ */
+__attribute__((weak)) void abort(void)
+{
+  _exit(1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/asm_vectors.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/asm_vectors.S
new file mode 100644
index 000000000..138c22e89
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/asm_vectors.S
@@ -0,0 +1,121 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file asm_vectors.s
+*
+* This file contains the initial vector table for the Cortex R5 processor
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	02/10/14 Initial version
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+.org 0
+.text
+
+.globl _boot
+.globl _vector_table
+
+.globl FIQInterrupt
+.globl IRQInterrupt
+.globl SWInterrupt
+.globl DataAbortInterrupt
+.globl PrefetchAbortInterrupt
+
+.globl IRQHandler
+.globl prof_pc
+
+.section .vectors, "a"
+_vector_table:
+	ldr	pc,=_boot
+	ldr	pc,=Undefined
+	ldr	pc,=SVCHandler
+	ldr	pc,=PrefetchAbortHandler
+	ldr	pc,=DataAbortHandler
+	NOP	/* Placeholder for address exception vector*/
+	ldr	pc,=IRQHandler
+	ldr	pc,=FIQHandler
+
+.text
+IRQHandler:					/* IRQ vector handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code*/
+	bl	IRQInterrupt			/* IRQ vector */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	subs	pc, lr, #4			/* adjust return */
+
+FIQHandler:					/* FIQ vector handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+FIQLoop:
+	bl	FIQInterrupt			/* FIQ vector */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	subs	pc, lr, #4			/* adjust return */
+
+Undefined:					/* Undefined handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	b	_prestart
+	movs	pc, lr
+
+SVCHandler:					/* SWI handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	tst	r0, #0x20			/* check the T bit */
+	ldrneh	r0, [lr,#-2]			/* Thumb mode */
+	bicne	r0, r0, #0xff00			/* Thumb mode */
+	ldreq	r0, [lr,#-4]			/* ARM mode */
+	biceq	r0, r0, #0xff000000		/* ARM mode */
+	bl	SWInterrupt			/* SWInterrupt: call C function here */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	movs	pc, lr				/* adjust return */
+
+DataAbortHandler:				/* Data Abort handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	bl	DataAbortInterrupt		/*DataAbortInterrupt :call C function here */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	subs	pc, lr, #8			/* adjust return */
+
+PrefetchAbortHandler:				/* Prefetch Abort handler */
+	stmdb	sp!,{r0-r3,r12,lr}		/* state save from compiled code */
+	bl	PrefetchAbortInterrupt		/* PrefetchAbortInterrupt: call C function here */
+	ldmia	sp!,{r0-r3,r12,lr}		/* state restore from compiled code */
+	subs	pc, lr, #4			/* adjust return */
+
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/boot.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/boot.S
new file mode 100644
index 000000000..724f9616f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/boot.S
@@ -0,0 +1,300 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file boot.S
+*
+* This file contains the initial startup code for the Cortex R5 processor
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 5.04	pkp  09/11/15 Disabled ACTLR.DBWR bit to avoid potential R5 deadlock
+*		      for errata 780125
+* 5.04 pkp   02/04/16 Enabled the fault log for lock-step mode
+* 5.04 pkp   02/25/16 Initialized the banked registers for various modes,
+*		      initialized floating point registers and enabled the
+*		      cache ECC check before enabling the fault log for
+*		      lock step mode
+* 5.04 pkp   03/24/16 Reset the dbg_lpd_reset before enabling the fault log
+*		      to avoid intervention for lock-step mode
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xparameters.h"
+
+
+.global _prestart
+.global _boot
+.global __stack
+.global __irq_stack
+.global __supervisor_stack
+.global __abort_stack
+.global __fiq_stack
+.global __undef_stack
+.global _vector_table
+
+
+/* Stack Pointer locations for boot code */
+.set Undef_stack,	__undef_stack
+.set FIQ_stack,		__fiq_stack
+.set Abort_stack,	__abort_stack
+.set SPV_stack,		__supervisor_stack
+.set IRQ_stack,		__irq_stack
+.set SYS_stack,		__stack
+
+.set vector_base,	_vector_table
+
+.set RPU_GLBL_CNTL,	0xFF9A0000
+.set RPU_ERR_INJ,	0xFF9A0020
+.set RST_LPD_DBG,	0xFF5E0240
+.set fault_log_enable,	0x101
+
+.section .boot,"axS"
+
+
+/* this initializes the various processor modes */
+
+_prestart:
+_boot:
+
+OKToRun:
+
+/* Initialize processor registers to 0 */
+	mov	r0,#0
+	mov	r1,#0
+	mov	r2,#0
+	mov	r3,#0
+	mov	r4,#0
+	mov	r5,#0
+	mov	r6,#0
+	mov	r7,#0
+	mov	r8,#0
+	mov	r9,#0
+	mov	r10,#0
+	mov	r11,#0
+	mov	r12,#0
+
+/* Initialize stack pointer and banked registers for various mode */
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the irq stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x12			/* IRQ mode */
+	msr	cpsr, r2
+	ldr	r13,=IRQ_stack			/* IRQ stack pointer */
+	mov 	r14,#0
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the supervisor stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x13			/* supervisor mode */
+	msr	cpsr, r2
+	ldr	r13,=SPV_stack			/* Supervisor stack pointer */
+	mov 	r14,#0
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the Abort  stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x17			/* Abort mode */
+	msr	cpsr, r2
+	ldr	r13,=Abort_stack		/* Abort stack pointer */
+	mov 	r14,#0
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the FIQ stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x11			/* FIQ mode */
+	msr	cpsr, r2
+	mov 	r8, #0
+	mov 	r9, #0
+	mov 	r10, #0
+	mov 	r11, #0
+	mov 	r12, #0
+	ldr	r13,=FIQ_stack			/* FIQ stack pointer */
+	mov 	r14,#0
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the Undefine stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x1b			/* Undefine mode */
+	msr	cpsr, r2
+	ldr	r13,=Undef_stack		/* Undefine stack pointer */
+	mov 	r14,#0
+
+	mrs	r0, cpsr			/* get the current PSR */
+	mvn	r1, #0x1f			/* set up the system stack pointer */
+	and	r2, r1, r0
+	orr	r2, r2, #0x1F			/* SYS mode */
+	msr	cpsr, r2
+	ldr	r13,=SYS_stack			/* SYS stack pointer */
+	mov 	r14,#0
+
+/*
+ * Enable access to VFP by enabling access to Coprocessors 10 and 11.
+ * Enables Full Access i.e. in both privileged and non privileged modes
+ */
+	mrc     p15, 0, r0, c1, c0, 2      	/* Read Coprocessor Access Control Register (CPACR) */
+        orr     r0, r0, #(0xF << 20)       	/* Enable access to CP 10 & 11 */
+        mcr     p15, 0, r0, c1, c0, 2      	/* Write Coprocessor Access Control Register (CPACR) */
+        isb
+
+/* enable fpu access  */
+	vmrs	r3, FPEXC
+	orr	r1, r3, #(1<<30)
+	vmsr	FPEXC, r1
+
+/* clear the floating point register*/
+	mov	r1,#0
+	vmov	d0,r1,r1
+	vmov	d1,r1,r1
+	vmov	d2,r1,r1
+	vmov	d3,r1,r1
+	vmov	d4,r1,r1
+	vmov	d5,r1,r1
+	vmov	d6,r1,r1
+	vmov	d7,r1,r1
+	vmov	d8,r1,r1
+	vmov	d9,r1,r1
+	vmov	d10,r1,r1
+	vmov	d11,r1,r1
+	vmov	d12,r1,r1
+	vmov	d13,r1,r1
+	vmov	d14,r1,r1
+	vmov	d15,r1,r1
+
+/* restore previous value for fpu access */
+	vmsr	FPEXC,r3
+
+/* Disable MPU and caches */
+        mrc     p15, 0, r0, c1, c0, 0       	/* Read CP15 Control Register*/
+        bic     r0, r0, #0x05               	/* Disable MPU (M bit) and data cache (C bit) */
+        bic     r0, r0, #0x1000             	/* Disable instruction cache (I bit) */
+        dsb                                 	/* Ensure all previous loads/stores have completed */
+        mcr     p15, 0, r0, c1, c0, 0       	/* Write CP15 Control Register */
+        isb                                 	/* Ensure subsequent insts execute wrt new MPU settings */
+
+/* Disable Branch prediction, TCM ECC checks */
+        mrc     p15, 0, r0, c1, c0, 1       	/* Read ACTLR */
+        orr     r0, r0, #(0x1 << 17)        	/* Enable RSDIS bit 17 to disable the return stack */
+        orr     r0, r0, #(0x1 << 16)        	/* Clear BP bit 15 and set BP bit 16:*/
+        bic     r0, r0, #(0x1 << 15)        	/* Branch always not taken and history table updates disabled*/
+        bic     r0, r0, #(0x1 << 27)		/* Disable B1TCM ECC check */
+        bic     r0, r0, #(0x1 << 26)		/* Disable B0TCM ECC check */
+        bic     r0, r0, #(0x1 << 25)		/* Disable ATCM ECC check */
+	orr	r0, r0, #(0x1 << 5)		/* Enable ECC with no forced write through with [5:3]=b'101*/
+	bic 	r0, r0, #(0x1 << 4)
+	orr	r0, r0, #(0x1 << 3)
+        mcr     p15, 0, r0, c1, c0, 1       	/* Write ACTLR*/
+	dsb				    	/* Complete all outstanding explicit memory operations*/
+
+/* Invalidate caches */
+	mov	r0,#0				/* r0 = 0  */
+	dsb
+	mcr	p15, 0, r0, c7, c5, 0		/* invalidate icache */
+	mcr 	p15, 0, r0, c15, c5, 0      	/* Invalidate entire data cache*/
+	isb
+
+/* enable fault log for lock step */
+	ldr	r0,=RPU_GLBL_CNTL
+	ldr	r1, [r0]
+	ands	r1, r1, #0x8
+/* branch to initialization if split mode*/
+	bne 	init
+/* reset the debug logic */
+	ldr	r0,=RST_LPD_DBG
+	ldr	r1, [r0]
+	orr	r1, r1, #(0x1 << 1)
+	orr	r1, r1, #(0x1 << 4)
+	orr	r1, r1, #(0x1 << 5)
+	str	r1, [r0]
+/* enable fault log */
+	ldr	r0,=RPU_ERR_INJ
+	ldr	r1,=fault_log_enable
+	ldr	r2, [r0]
+	orr	r2, r2, r1
+	str	r2, [r0]
+	nop
+	nop
+
+init:
+	bl 	Init_MPU		/* Initialize MPU */
+
+/* Enable Branch prediction */
+	mrc     p15, 0, r0, c1, c0, 1       /* Read ACTLR*/
+        bic     r0, r0, #(0x1 << 17)        /* Clear RSDIS bit 17 to enable return stack*/
+        bic     r0, r0, #(0x1 << 16)        /* Clear BP bit 15 and BP bit 16:*/
+        bic     r0, r0, #(0x1 << 15)        /* Normal operation, BP is taken from the global history table.*/
+        orr	r0, r0, #(0x1 << 14)	    /* Disable DBWR for errata 780125 */
+	mcr     p15, 0, r0, c1, c0, 1       /* Write ACTLR*/
+
+/* Enable icahce and dcache */
+	mrc 	p15,0,r1,c1,c0,0
+	ldr	r0, =0x1005
+	orr 	r1,r1,r0
+	dsb
+	mcr	p15,0,r1,c1,c0,0		/* Enable cache  */
+	isb					/* isb	flush prefetch buffer */
+
+/* Warning message to be removed after 2016.1 */
+/* USEAMP was introduced in 2015.4 with ZynqMP and caused confusion with USE_AMP */
+#ifdef USEAMP
+#warning "-DUSEAMP=1 is deprecated, use -DVEC_TABLE_IN_OCM instead to set vector table in OCM"
+#endif
+
+/* Set vector table in TCM/LOVEC */
+#ifndef VEC_TABLE_IN_OCM
+	mrc	p15, 0, r0, c1, c0, 0
+	mvn	r1, #0x2000
+	and	r0, r0, r1
+	mcr	p15, 0, r0, c1, c0, 0
+#endif
+
+/* enable asynchronous abort exception */
+	mrs	r0, cpsr
+	bic	r0, r0, #0x100
+	msr	cpsr_xsf, r0
+
+        b 	_startup                       /* jump to C startup code */
+
+
+.Ldone:	b	.Ldone				/* Paranoia: we should never get here */
+
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/bspconfig.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/bspconfig.h
new file mode 100644
index 000000000..4dd178f04
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/bspconfig.h
@@ -0,0 +1,40 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Configurations for Standalone BSP
+*
+*******************************************************************/
+
+#define MICROBLAZE_PVR_NONE
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/changelog.txt b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/changelog.txt
new file mode 100644
index 000000000..ad9c771e1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/changelog.txt
@@ -0,0 +1,324 @@
+/*****************************************************************************
+ * MODIFICATION HISTORY:
+ *
+ * Ver   Who  Date     Changes
+ * ----- ---- -------- ---------------------------------------------------
+  * 3.02a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+ * 3.02a sdm  06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
+ * 3.02a sdm  07/07/11 Updated ppc440 boot.S to set guarded bit for all but
+ *                     cacheable regions
+ *                     Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
+ *                     generated by the cpu driver, for enabling caches
+ * 3.02a sdm  07/08/11 Updated microblaze cache flush APIs based on write-back/
+ *                     write-thru caches
+ * 3.03a sdm  08/20/11 Updated the tag/data RAM latency values for L2CC
+ *		       Updated the MMU table to mark OCM in high address space
+ *		       as inner cacheable and reserved space as Invalid
+ * 3.03a sdm  08/20/11 Changes to support FreeRTOS
+ *		       Updated the MMU table to mark upper half of the DDR as
+ *		       non-cacheable
+ *		       Setup supervisor and abort mode stacks
+ *		       Do not initialize/enable L2CC in case of AMP
+ *		       Initialize UART1 for 9600bps in case of AMP
+ * 3.03a sdm  08/27/11 Setup abort and supervisor mode stacks and don't init SMC
+ *		       in case of AMP
+ * 3.03a sdm  09/14/11 Added code for performance monitor and L2CC event
+ *		       counters
+ * 3.03a sdm  11/08/11 Updated microblaze xil_cache.h file to include
+ *		       xparameters.h file for CR630532 -  Xil_DCacheFlush()/
+ *		       Xil_DCacheFlushRange() functions in standalone BSP v3_02a
+ *		       for MicroBlaze will invalidate data in the cache instead
+ *		       of flushing it for writeback caches
+ * 3.04a sdm  11/21/11 Updated to initialize stdio device for 115200bps, for PS7
+ * 3.04a sdm  01/02/12 Updated to clear cp15 regs with unknown reset values
+ *		       Remove redundant dsb/dmb instructions in cache maintenance
+ *		       APIs
+ *		       Remove redundant dsb in mcr instruction
+ * 3.04a sdm  01/13/12 Updated MMU table to mark DDR memory as Shareable
+ * 3.05a sdm  02/02/12 Removed some of the defines as they are being generated through
+ *                     driver tcl in xparameters.h. Update the gcc/translationtable.s
+ *                     for the QSPI complete address range - DT644567
+ *                     Removed profile directory for armcc compiler and changed
+ *                     profiling setting to false in standalone_v2_1_0.tcl file
+ *                     Deleting boot.S file after preprocessing for armcc compiler
+ * 3.05a asa  03/11/12 Updated the function Xil_EnableMMU in file xil_mmu.c to
+ *		       invalidate the caches before enabling back the MMU and
+ *		       D cache.
+ * 3.05a asa  04/15/12 Updated the function Xil_SetTlbAttributes in file
+ *		       xil_mmu.c. Now we invalidate UTLB, Branch predictor
+ *		       array, flush the D-cache before changing the attributes
+ *		       in translation table. The user need not call Xil_DisableMMU
+ *		       before calling Xil_SetTlbAttributes.
+ * 3.06a asa/ 06/17/12 Removed the UART initialization for Zynq. For PEEP, the UART
+ *	 sgd	       initialization is present. Changes for this were done in
+ *		       uart.c and xil-crt0.s.
+ *		       Made changes in xil_io.c to use volatile pointers.
+ *		       Made changes in xil_mmu.c to correct the function
+ *		       Xil_SetTlbAttributes.
+ *		       Changes are made xil-crt0.s to initialize the static
+ *		       C++ constructors.
+ *		       Changes are made in boot.s, to fix the TTBR settings,
+ *		       correct the L2 Cache Auxiliary register settings, L2 cache
+ *		       latency settings.
+ * 3.07a asa/ 07/16/12 Made changes in cortexa9/xtime_l.c, xtime_l.h, sleep.c
+ *	 sgd	       usleep.c to use global timer intstead of CP15.
+ *		       Made changes in cortexa9/gcc/translation_table.s to map
+ *		       the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/xil-crt0.s to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/boot.S to initialize
+ *		       the global timer.
+ *		       Made changes in cortexa9/armcc/translation_table.s to
+ *		       map the peripheral devices as shareable device memory.
+ *		       Made changes in cortexa9/gcc/boot.S to optimize the
+ *		       L2 cache settings. Changes the section properties for
+ *		       ".mmu_tbl" and ".boot" sections in cortexa9/gcc/boot.S
+ *			and cortexa9/gcc/translation_table.S.
+ *		       Made changes in cortexa9/xil_cache.c to change the
+ *		       cache invalidation order.
+ * 3.07a asa  08/17/12 Made changes across files for Cortexa9 to remove
+ *		       compilation/linking issues for C++ compiler.
+ *		       Made changes in mb_interface.h to remove compilation/
+ *		       linking issues for C++ compiler.
+ *		       Added macros for swapb and swaph microblaze instructions
+ *		       mb_interface.h
+ *		       Remove barrier usage (SYNCHRONIZE_IO) from xil_io.c
+ *		       for CortexA9.
+ * 3.07a asa  08/30/12 Updated for CR 675636 to provide the L2 Base Address
+ * 3.07a asa  08/31/12 Added xil_printf.h include
+ * 3.07a sgd  09/18/12 Corrected the L2 cache enable settings
+ *				Corrected L2 cache sequence disable sequence
+ * 3.07a sgd  10/19/12 SMC NOR and SRAM initialization with compiler option
+ * 3.09a asa  01/25/13 Updated to push and pop neon registers into stack for
+ *		       irq/fiq handling.
+ *		       Relocated COUNTS_PER_SECOND from sleep.c to xtime_l.h. This
+ *		       fixes the CR #692094.
+ * 3.09a sgd  02/14/13 Fix for CRs 697094 (SI#687034) and 675552.
+ * 3.10a srt  04/18/13 Implemented ARM Erratas.
+ *		       Cortex A9 Errata - 742230, 743622, 775420, 794073
+ *		       L2Cache PL310 Errata - 588369, 727915, 759370
+ *		       Please refer to file 'xil_errata.h' for errata
+ *		       description.
+ * 3.10a asa  05/04/13 Added support for L2 cache in MicroBlaze BSP. The older
+ *		       cache APIs were corresponding to only Layer 1 cache
+ *		       memories. New APIs were now added and the existing cache
+ *		       related APIs were changed to provide a uniform interface
+ *		       to flush/invalidate/enable/disable the complete cache
+ *		       system which includes both L1 and L2 caches. The changes
+ *		       for these were done in:
+ *		       src/microblaze/xil_cache.c and src/microblaze/xil_cache.h
+ *		       files.
+ *		       Four new files were added for supporting L2 cache. They are:
+ *		       microblaze_flush_cache_ext.S-> Flushes L2 cache
+ *		       microblaze_flush_cache_ext_range.S -> Flushes a range of
+ *		       memory in L2 cache.
+ *		       microblaze_invalidate_cache_ext.S-> Invalidates L2 cache
+ *		       microblaze_invalidate_cache_ext_range -> Invalidates a
+ *		       range of memory in L2 cache.
+ *		       These changes are done to implement PR #697214.
+ * 3.10a  asa 05/13/13 Modified cache disable APIs at src/cortexa9/xil_cache.c to
+ *		       fix the CR #706464. L2 cache disabling happens independent
+ *		       of L1 data cache disable operation. Changes are done in the
+ *		       same file in cache handling APIs to do a L2 cache sync
+ *		       (poll reg7_?cache_?sync). This fixes CR #700542.
+ * 3.10a asa  05/20/13 Added API/Macros for enabling and disabling nested
+ *		       interrupts for ARM. These are done to fix the CR#699680.
+ * 3.10a srt  05/20/13 Made changes in cache maintenance APIs to do a proper cach
+ *		       sync operation. This fixes the CR# 716781.
+ * 3.11a asa  09/07/13 Updated armcc specific BSP files to have proper support
+ *		       for armcc toolchain.
+ *		       Modified asm_vectors.S (gcc) and asm_vectors.s (armcc) to
+ *		       fix issues related to NEON context saving. The assembly
+ *		       routines for IRQ and FIQ handling are modified.
+ *		       Deprecated the older BSP (3.10a).
+ * 3.11a asa  09/22/13 Fix for CR#732704. Cache APIs are modified to avoid
+ *		       various potential issues. Made changes in the function
+ *		       Xil_SetAttributes in file xil_mmu.c.
+ * 3.11a asa  09/23/13 Added files xil_misc_psreset_api.c and xil_misc_psreset_api.h
+ *		       in src\cortexa9 and src\microblaze folders.
+ * 3.11a asa  09/28/13 Modified the cache APIs (src\cortexa9) to fix handling of
+ *		       L2 cache sync operation and to fix issues around complete
+ *		       L2 cache flush/invalidation by ways.
+ * 3.12a asa  10/22/13 Modified the files xpseudo_asm_rvct.c and xpseudo_asm_rvct.h
+ *		       to fix linking issues with armcc/DS-5. Modified the armcc
+ *		       makefile to fix issues.
+ * 3.12a asa  11/15/13 Fix for CR#754800. It fixes issues around profiling for MB.
+ * 4.0   hk   12/13/13 Added check for STDOUT_BASEADDRESS where outbyte is used.
+ * 4.0 	 pkp  22/01/14 Modified return addresses for interrupt handlers (DataAbortHandler
+ *		       and SWIHandler) in asm_vector.S (src\cortexa9\gcc\ and
+ *		       src\cortexa9\armcc\) to fix CR#767251
+ * 4.0	 pkp  24/01/14 Modified cache APIs (Xil_DCacheInvalidateRange and
+ *		       Xil_L1DCacheInvalidate) in xil_cache.c (src\cortexa9) to fix the bugs.
+ *		       Few cache lines were missed to invalidate when unaligned address
+ *		       invalidation was accommodated in Xil_DCacheInvalidateRange.
+ *		       In Xil_L1DCacheInvalidate, while invalidating all L1D cache
+ *		       stack memory (which contains return address) was invalidated. So
+ *		       stack memory is flushed first and then L1D cache is invalidated.
+ *		       This is done to fix CR #763829
+ * 4.0 adk   22/02/2014 Fixed the CR:775379 removed unnecessay _t(unit32_t etc) from
+ *			mblaze_nt_types.h file and replace uint32_t with u32 in the
+ *			profile_hist.c to fix the above CR.
+ * 4.1 bss   04/14/14  Updated driver tcl to remove _interrupt_handler.o from libgloss.a
+ * 		       instead of libxil.a and added prototypes for
+ *		       microblaze_invalidate_cache_ext and microblaze_flush_cache_ext in
+ *		       mb_interface.h
+ * 4.1 hk    04/18/14  Add sleep function.
+ * 4.1 asa   04/21/14  Fix for CR#764881. Added support for msrset and msrclr. Renamed
+ *		       some of the *.s files inMB BSP source to *.S.
+ * 4.1 asa   04/28/14  Fix for CR#772280. Made changes in file cortexa9/gcc/read.c.
+ * 4.1 bss   04/29/14  Modified driver tcl to use libxil.a if libgloss.a does not exist
+ *			CR#794205
+ * 4.1 asa   05/09/14  Fix for CR#798230. Made changes in cortexa9/xil_cache.c and
+ *		       common/xil_testcache.c
+ *	               Fix for CR#764881.
+ * 4.1 srt   06/27/14  Remove '#undef DEBUG' from src/common/xdebug.h, which allows to
+ *                     output the DEBUG logs when -DDEBUG flag is enabled in BSP.
+ * 4.2 pkp   06/27/14  Added support for IAR compiler in src/cortexa9/iccarm.
+ *		       Also added explanatory notes in cortexa9/xil_cache.c for CR#785243.
+ * 4.2 pkp   06/19/14  Asynchronous abort has been enabled into cortexa9/gcc/boot.s and
+ *		       cortexa9/armcc/boot.s. Added default exception handlers for data
+ *		       abort and prefetch abort using handlers called
+ *		       DataAbortHandler and PrefetchAbortHandler respectively in
+ *		       cortexa9/xil_exception.c to fix CR#802862.
+ * 4.2 pkp   06/30/14  MakeFile for cortexa9/armcc has been changed to fixes the
+ *		       issue of improper linking of translation_table.s
+ * 4.2 pkp   07/04/14  added weak attribute for the function in BSP which are also present
+ *		       in tool chain to avoid conflicts into some special cases
+ * 4.2 pkp   07/21/14  Corrected reset value of event counter in function
+ *		       Xpm_ResetEventCounters in src/cortexa9/xpm_counter.c to fix CR#796275
+ * 4.2 pkp   07/21/14  Included xil_types.h file in xil_mmu.h which had contained a function
+ * 		       containing type def u32 defined in xil_types.g to resolve issue of
+ *		       CR#805869
+ * 4.2 pkp   08/04/14  Removed unimplemented nanosleep routine from cortexa9/usleep.c as
+ *		       it is not possible to generate timer in nanosecond due to limited
+ *		       cpu frequency
+ * 4.2 pkp   08/04/14  Removed PEEP board related code which contained initialization of
+ *		       uart, smc nor and sram from cortexa9/gcc/xil-crt0.s and armcc/boot.s
+ *		       and iccarm/boot.s. Also uart.c and smc.c have been removed. Also
+ *		       removed function definition of XSmc_NorInit and XSmc_NorInit from
+ *		       cortexa9/smc.h
+ * 4.2 bss   08/11/14  Added microblaze_flush_cache_ext_range and microblaze_invalidate_
+ *		       cache_ext_range declarations in mb_interface.h CR#783821.
+ *		       Modified profile_mcount_mb.S to fix CR#808412.
+ * 4.2 pkp   08/21/14  modified makefile of iccarm for proper linking of objectfiles in
+ *		       cortexa9/iccarm to fix CR#816701
+ * 4.2 pkp   09/02/14  modified translation table entries in cortexa9/gcc/translation_table.s,
+ *		       armcc/translation_table.s and iccarm/translation_table.s
+ *		       to properly defined reserved entries according to address map for
+ *		       fixing CR#820146
+ * 4.2 pkp   09/11/14  modified translation table entries in cortexa9/iccarm/translation_table.s
+ *		       and  cortexa9/armcc/translation_table.s to resolve compilation
+ *		       error for solving CR#822897
+ * 5.0 kvn   12/9/14   Support for Zync Ultrascale Mp.Also modified code for
+ *                     MISRA-C:2012 compliance.
+ * 5.0 pkp   12/15/14  Added APIs to get information about the platforms running the code by
+ *		       adding src/common/xplatform_info.*s
+ * 5.0 pkp   16/12/14  Modified boot code to enable scu after MMU is enabled and
+ *		       removed incorrect initialization of TLB lockdown register to fix
+ *		       CR#830580 in cortexa9/gcc/boot.S & cpu_init.S, armcc/boot.S
+ *		       and iccarm/boot.s
+ * 5.0 pkp   25/02/15  Modified floating point flag to vfpv3 from vfpv3_d16 in BSP MakeFile
+ *		       for iccarm and armcc compiler of cortexA9
+ * 5.1 pkp   05/13/15  Changed the initialization order in cortexa9/gcc/boot.S, iccarm/boot.s
+ *		       and armcc/boot.s so to first invalidate caches and TLB, enable MMU and
+ *		       caches, then enable SMP bit in ACTLR. L2Cache invalidation and enabling
+ *		       of L2Cache is done later.
+ * 5.1 pkp   12/05/15  Modified cortexa9/xil_cache.c to modify Xil_DCacheInvalidateRange and
+ *		       Xil_DCacheFlushRange to remove unnecessary dsb which is unnecessarily
+ *		       taking long time to fix CR#853097. L2CacheSync is added into
+ *		       Xil_L2CacheInvalidateRange API. Xil_L1DCacheInvalidate and
+ *		       Xil_L2CacheInvalidate APIs are modified to flush the complete stack
+ *		       instead of just System Stack
+ * 5.1 pkp   14/05/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ *		       to update ECC_FLAGS and also take the compiler and archiver as specified
+ *		       in settings instead of hardcoding it.
+ * 5.2 pkp   06/08/15  Modified cortexa9/gcc/translation_table.S to put a check for
+ *		       XPAR_PS7_DDR_0_S_AXI_BASEADDR to confirm if DDR is present or not and
+ *		       accordingly generate the	translation table
+ * 5.2 pkp   23/07/15  Modified cortexa9/gcc/Makefile to keep a correct check of a compiler
+ *		       to update ECC_FLAGS to fix a bug introduced during new version creation
+ *		       of BSP.
+ * 5.3 pkp   10/07/15  Modified cortexa9/xil_cache.c file to change cache API so that L2 Cache
+ *		       functionalities are avoided for the OpenAMP slave application(when
+ *		       USE_AMP flag is defined for BSP) as master CPU would be utilizing L2
+ *		       cache for its operation. Also file operations such as read, write,
+ *		       close, open are also avoided for OpenAMP support(when USE_AMP flag is
+ *		       defined for BSP) because XilOpenAMP library contains own file operation.
+ *		       The xil-crt0.S file is modified for not initializing global timer for
+ *		       OpenAMP application as it might be already in use by master CPU
+ * 5.3 pkp   10/09/15  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to change function
+ *		       definition for dsb, isb and dmb to fix the compilation error when used
+ *     kvn   16/10/15  Encapsulated assembly code into macros for R5 xil_cache file.
+ * 5.4 pkp   09/11/15  Modified cortexr5/gcc/boot.S to disable ACTLR.DBWR bit to avoid potential
+ *		       R5 deadlock for errata 780125
+ * 5.4 pkp   09/11/15  Modified cortexa53/32bit/gcc/boot.S to enable I-Cache and D-Cache for a53
+ *		       32 bit BSP in the initialization
+ * 5.4 pkp   09/11/15  Modified cortexa9/xil_misc_psreset_api.c file to change the description
+ *		       for XOcm_Remap function
+ * 5.4 pkp   16/11/15  Modified microblaze/xil_misc_psreset_api.c file to change the description
+ *		       for XOcm_Remap function
+ *     kvn   21/11/15  Added volatile keyword for ADDR varibles in Xil_Out API
+ *     kvn   21/11/15  Changed ADDR variable type from u32 to UINTPTR. This is
+ *                     required for MISRA-C:2012 Compliance.
+ * 5.4 pkp   23/11/15  Added attribute definitions for Xil_SetTlbAttributes API of Cortex-A9
+ *		       in cortexa9/xil_mmu.h
+ * 5.4 pkp   23/11/15  Added default undefined exception handler for Cortex-A9
+ * 5.4 pkp   11/12/15  Modified common/xplatform_info.h to add #defines for silicon for
+ *		       checking the current executing platform
+ * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/xil-crt0.S and 64bit/gcc/xil-crt0.S
+ *		       to initialize global constructor for C++ applications
+ * 5.4 pkp   18/12/15  Modified cortexr5/gcc/xil-crt0.S to initialize global constructor for
+ *		       C++ applications
+ * 5.4 pkp   18/12/15  Modified cortexa53/32bit/gcc/translation_table.S and 64bit/gcc/
+ *		       translation_table.S to update the translation table according to proper
+ *		       address map
+ * 5.4 pkp   18/12/15  Modified cortexar5/mpu.c to initialize the MPU according to proper
+ *		       address map
+ * 5.4	pkp  05/01/16  Modified cortexa53/64bit/boot.S to set the reset vector register RVBAR
+ *		       equivalent to vector table base address
+ * 5.4 pkp   08/01/16  Modified cortexa9/gcc/Makefile to update the extra compiler flag
+ *		       as per the toolchain update
+ * 5.4 pkp   12/01/16  Changed common/xplatform_info.* to add platform information support
+ *		       for Cortex-A53 32bit mode
+ * 5.4 pkp   28/01/16  Modified cortexa53/32bit/sleep.c and usleep.c & cortexa53/64bit/sleep.c
+ *		       and usleep.c to correct routines to avoid hardcoding the timer frequency,
+ *		       instead take it from xparameters.h to properly configure the timestamp
+ *		       clock frequency
+ * 5.4 asa   29/01/16  Modified microblaze/mb_interface.h to add macros that support the
+ *		       new instructions for MB address extension feature
+ * 5.4 kvn   30/01/16  Modified xparameters_ps.h file to add interrupt ID number for
+ *		       system monitor.
+ * 5.4 pkp   04/02/16  Modified cortexr5/gcc/boot.S to enable fault log for lock-step mode
+ * 5.4 pkp   19/02/16  Modified cortexr5/xtime_l.c to add an API XTime_StartTimer and updated
+ *		       cortexr5/xil-crt0.S to configure the TTC3 timer when present. Modified
+ *		       cortexr5/sleep.c, cortexr5/usleep.c to use TTC3 when present otherwise
+ *		       use set of assembly instructions to provide required delay to fix
+ *		       CR#913249.
+ * 5.4 asa   25/02/16  Made changes in xil-crt0.S for R5, A53 64 and 32 bit BSPs, to replace
+ *		       _exit with exit. We should not be directly calling _exit and should
+ *		       always use the library exit. This fixes the CR#937036.
+ * 5.4 pkp   25/02/16  Made change to cortexr5/gcc/boot.S to initialize the floating point
+ *		       registers, banked registers for various modes and enabled
+ *		       the cache ECC check before enabling the fault log for lock step mode
+ *		       Also modified the cortexr5/gcc/Makefile to support floating point
+ *		       registers initialization in boot code.
+ * 5.4 pkp   03/01/16  Updated the exit function in cortexr5/gcc/_exit.c to enable the debug
+ *		       logic in case of lock-step mode when fault log is enabled to fix
+ *		       CR#938281
+ * 5.4 pkp   03/02/16  Modified cortexa9/iccarm/xpseudo_asm_iccarm.h file to include
+ *		       header file instrinsics.h which contains assembly instructions
+ *		       definitions which can be used by C
+ * 5.4 asa   03/02/16  Added print.c in MB BSP. Made other cosmetic changes to have uniform
+ *                     proto for all print.c across the BSPs. This patch fixes CR#938738.
+ * 5.4 pkp   03/09/16  Modified cortexr5/sleep.c and usleep.c to avoid disabling the
+ *		       interrupts when sleep/usleep is being executed using assembly
+ *		       instructions to fix CR#913249.
+ * 5.4 pkp   03/11/16  Modified cortexr5/xtime_l.c to avoid enabling overflow interrupt,
+ *		       instead modified cortexr5/sleep.c and usleep.c to poll the counter
+ *		       value and compare it with previous value to detect the overflow
+ *		       to fix CR#940209.
+ * 5.4 pkp   03/24/16  Modified cortexr5/boot.S to reset the dbg_lpd_reset before enabling
+ *		       the fault log to avoid intervention for lock-step mode and cortexr5/
+ *		       _exit.c to enable the dbg_lpd_reset once the fault log is disabled
+ *		       to fix CR#947335
+ *****************************************************************************************/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/close.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/close.c
new file mode 100644
index 000000000..e42a1ff36
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/close.c
@@ -0,0 +1,47 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _close(s32 fd);
+}
+#endif
+
+/*
+ * close -- We don't need to do anything, but pretend we did.
+ */
+
+__attribute__((weak)) s32 _close(s32 fd)
+{
+  (void)fd;
+  return (0);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/config.make b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/config.make
new file mode 100644
index 000000000..2b7dbb6f7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/config.make
@@ -0,0 +1,2 @@
+LIBSOURCES = *.c *.S
+LIBS = standalone_libs
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/cpu_init.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/cpu_init.S
new file mode 100644
index 000000000..40bbc2c7a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/cpu_init.S
@@ -0,0 +1,79 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file cpu_init.s
+*
+* This file contains CPU specific initialization. Invoked from main CRT
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp	02/10/14 Initial version
+*
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+	.text
+	.global __cpu_init
+	.align 2
+__cpu_init:
+
+/* Clear cp15 regs with unknown reset values */
+	mov	r0, #0x0
+	mcr	p15, 0, r0, c5, c0, 0	/* DFSR */
+	mcr	p15, 0, r0, c5, c0, 1	/* IFSR */
+	mcr	p15, 0, r0, c6, c0, 0	/* DFAR */
+	mcr	p15, 0, r0, c6, c0, 2	/* IFAR */
+	mcr	p15, 0, r0, c9, c13, 2	/* PMXEVCNTR */
+	mcr	p15, 0, r0, c13, c0, 2	/* TPIDRURW */
+	mcr	p15, 0, r0, c13, c0, 3	/* TPIDRURO */
+
+
+/* Reset and start Cycle Counter */
+	mov	r2, #0x80000000		/* clear overflow */
+	mcr	p15, 0, r2, c9, c12, 3
+	mov	r2, #0xd		/* D, C, E */
+	mcr	p15, 0, r2, c9, c12, 0
+	mov	r2, #0x80000000		/* enable cycle counter */
+	mcr	p15, 0, r2, c9, c12, 1
+
+	bx	lr
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/errno.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/errno.c
new file mode 100644
index 000000000..daaa1212d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/errno.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* The errno variable is stored in the reentrancy structure.  This
+   function returns its address for use by the macro errno defined in
+   errno.h.  */
+
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 * __errno (void);
+}
+#endif
+
+__attribute__((weak)) sint32 *
+__errno (void)
+{
+  return &_REENT->_errno;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fcntl.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fcntl.c
new file mode 100644
index 000000000..4c5de40fd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fcntl.c
@@ -0,0 +1,46 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+/*
+ * fcntl -- Manipulate a file descriptor.
+ *          We don't have a filesystem, so we do nothing.
+ */
+__attribute__((weak)) s32 fcntl (s32 fd, s32 cmd, s32 arg)
+{
+  (void)fd;
+  (void)cmd;
+  (void)arg;
+  return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fstat.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fstat.c
new file mode 100644
index 000000000..6271cfa84
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/fstat.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf);
+}
+#endif
+/*
+ * fstat -- Since we have no file system, we just return an error.
+ */
+__attribute__((weak)) s32 _fstat(s32 fd, struct stat *buf)
+{
+  (void)fd;
+  buf->st_mode = S_IFCHR; /* Always pretend to be a tty */
+
+  return (0);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/getpid.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/getpid.c
new file mode 100644
index 000000000..c2a84cb7f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/getpid.c
@@ -0,0 +1,51 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+/*
+ * getpid -- only one process, so just return 1.
+ */
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _getpid(void);
+}
+#endif
+
+__attribute__((weak)) s32 getpid(void)
+{
+  return 1;
+}
+
+__attribute__((weak)) s32 _getpid(void)
+{
+  return 1;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/inbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/inbyte.c
new file mode 100644
index 000000000..a5a6448d4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/inbyte.c
@@ -0,0 +1,14 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+char inbyte(void);
+#ifdef __cplusplus
+}
+#endif 
+
+char inbyte(void) {
+	 return XUartPs_RecvByte(STDIN_BASEADDRESS);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu0_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu0_cfg.h
new file mode 100644
index 000000000..9029bead8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu0_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU0_CFG_H__
+#define __XDDR_XMPU0_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu0Cfg Base Address
+ */
+#define XDDR_XMPU0_CFG_BASEADDR      0xFD000000UL
+
+/**
+ * Register: XddrXmpu0CfgCtrl
+ */
+#define XDDR_XMPU0_CFG_CTRL    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU0_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu0CfgErrSts1
+ */
+#define XDDR_XMPU0_CFG_ERR_STS1    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU0_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU0_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgErrSts2
+ */
+#define XDDR_XMPU0_CFG_ERR_STS2    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU0_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgPoison
+ */
+#define XDDR_XMPU0_CFG_POISON    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU0_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU0_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU0_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU0_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU0_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgIsr
+ */
+#define XDDR_XMPU0_CFG_ISR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU0_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgImr
+ */
+#define XDDR_XMPU0_CFG_IMR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU0_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu0CfgIen
+ */
+#define XDDR_XMPU0_CFG_IEN    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU0_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgIds
+ */
+#define XDDR_XMPU0_CFG_IDS    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU0_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU0_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU0_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgLock
+ */
+#define XDDR_XMPU0_CFG_LOCK    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU0_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00Strt
+ */
+#define XDDR_XMPU0_CFG_R00_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU0_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00End
+ */
+#define XDDR_XMPU0_CFG_R00_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU0_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00Mstr
+ */
+#define XDDR_XMPU0_CFG_R00_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU0_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR00
+ */
+#define XDDR_XMPU0_CFG_R00    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU0_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01Strt
+ */
+#define XDDR_XMPU0_CFG_R01_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU0_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01End
+ */
+#define XDDR_XMPU0_CFG_R01_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU0_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01Mstr
+ */
+#define XDDR_XMPU0_CFG_R01_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU0_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR01
+ */
+#define XDDR_XMPU0_CFG_R01    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU0_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02Strt
+ */
+#define XDDR_XMPU0_CFG_R02_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU0_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02End
+ */
+#define XDDR_XMPU0_CFG_R02_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU0_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02Mstr
+ */
+#define XDDR_XMPU0_CFG_R02_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU0_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR02
+ */
+#define XDDR_XMPU0_CFG_R02    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU0_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03Strt
+ */
+#define XDDR_XMPU0_CFG_R03_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU0_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03End
+ */
+#define XDDR_XMPU0_CFG_R03_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU0_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03Mstr
+ */
+#define XDDR_XMPU0_CFG_R03_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU0_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR03
+ */
+#define XDDR_XMPU0_CFG_R03    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU0_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04Strt
+ */
+#define XDDR_XMPU0_CFG_R04_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU0_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04End
+ */
+#define XDDR_XMPU0_CFG_R04_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU0_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04Mstr
+ */
+#define XDDR_XMPU0_CFG_R04_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU0_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR04
+ */
+#define XDDR_XMPU0_CFG_R04    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU0_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05Strt
+ */
+#define XDDR_XMPU0_CFG_R05_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU0_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05End
+ */
+#define XDDR_XMPU0_CFG_R05_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU0_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05Mstr
+ */
+#define XDDR_XMPU0_CFG_R05_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU0_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR05
+ */
+#define XDDR_XMPU0_CFG_R05    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU0_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06Strt
+ */
+#define XDDR_XMPU0_CFG_R06_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU0_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06End
+ */
+#define XDDR_XMPU0_CFG_R06_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU0_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06Mstr
+ */
+#define XDDR_XMPU0_CFG_R06_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU0_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR06
+ */
+#define XDDR_XMPU0_CFG_R06    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU0_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07Strt
+ */
+#define XDDR_XMPU0_CFG_R07_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU0_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07End
+ */
+#define XDDR_XMPU0_CFG_R07_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU0_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07Mstr
+ */
+#define XDDR_XMPU0_CFG_R07_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU0_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR07
+ */
+#define XDDR_XMPU0_CFG_R07    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU0_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08Strt
+ */
+#define XDDR_XMPU0_CFG_R08_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU0_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08End
+ */
+#define XDDR_XMPU0_CFG_R08_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU0_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08Mstr
+ */
+#define XDDR_XMPU0_CFG_R08_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU0_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR08
+ */
+#define XDDR_XMPU0_CFG_R08    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU0_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09Strt
+ */
+#define XDDR_XMPU0_CFG_R09_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU0_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09End
+ */
+#define XDDR_XMPU0_CFG_R09_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU0_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09Mstr
+ */
+#define XDDR_XMPU0_CFG_R09_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU0_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR09
+ */
+#define XDDR_XMPU0_CFG_R09    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU0_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10Strt
+ */
+#define XDDR_XMPU0_CFG_R10_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU0_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10End
+ */
+#define XDDR_XMPU0_CFG_R10_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU0_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10Mstr
+ */
+#define XDDR_XMPU0_CFG_R10_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU0_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR10
+ */
+#define XDDR_XMPU0_CFG_R10    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU0_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11Strt
+ */
+#define XDDR_XMPU0_CFG_R11_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU0_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11End
+ */
+#define XDDR_XMPU0_CFG_R11_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU0_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11Mstr
+ */
+#define XDDR_XMPU0_CFG_R11_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU0_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR11
+ */
+#define XDDR_XMPU0_CFG_R11    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU0_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12Strt
+ */
+#define XDDR_XMPU0_CFG_R12_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU0_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12End
+ */
+#define XDDR_XMPU0_CFG_R12_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU0_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12Mstr
+ */
+#define XDDR_XMPU0_CFG_R12_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU0_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR12
+ */
+#define XDDR_XMPU0_CFG_R12    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU0_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13Strt
+ */
+#define XDDR_XMPU0_CFG_R13_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU0_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13End
+ */
+#define XDDR_XMPU0_CFG_R13_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU0_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13Mstr
+ */
+#define XDDR_XMPU0_CFG_R13_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU0_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR13
+ */
+#define XDDR_XMPU0_CFG_R13    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU0_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14Strt
+ */
+#define XDDR_XMPU0_CFG_R14_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU0_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14End
+ */
+#define XDDR_XMPU0_CFG_R14_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU0_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14Mstr
+ */
+#define XDDR_XMPU0_CFG_R14_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU0_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR14
+ */
+#define XDDR_XMPU0_CFG_R14    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU0_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15Strt
+ */
+#define XDDR_XMPU0_CFG_R15_STRT    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU0_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15End
+ */
+#define XDDR_XMPU0_CFG_R15_END    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU0_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU0_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU0_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15Mstr
+ */
+#define XDDR_XMPU0_CFG_R15_MSTR    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU0_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU0_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU0_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu0CfgR15
+ */
+#define XDDR_XMPU0_CFG_R15    ( ( XDDR_XMPU0_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU0_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU0_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU0_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU0_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU0_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU0_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU0_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU0_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU0_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU0_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU0_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU0_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU0_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU0_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu1_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu1_cfg.h
new file mode 100644
index 000000000..e2fa6d4aa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu1_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU1_CFG_H__
+#define __XDDR_XMPU1_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu1Cfg Base Address
+ */
+#define XDDR_XMPU1_CFG_BASEADDR      0xFD010000UL
+
+/**
+ * Register: XddrXmpu1CfgCtrl
+ */
+#define XDDR_XMPU1_CFG_CTRL    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU1_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu1CfgErrSts1
+ */
+#define XDDR_XMPU1_CFG_ERR_STS1    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU1_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU1_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgErrSts2
+ */
+#define XDDR_XMPU1_CFG_ERR_STS2    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU1_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgPoison
+ */
+#define XDDR_XMPU1_CFG_POISON    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU1_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU1_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU1_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU1_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU1_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgIsr
+ */
+#define XDDR_XMPU1_CFG_ISR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU1_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgImr
+ */
+#define XDDR_XMPU1_CFG_IMR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU1_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu1CfgIen
+ */
+#define XDDR_XMPU1_CFG_IEN    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU1_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgIds
+ */
+#define XDDR_XMPU1_CFG_IDS    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU1_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU1_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU1_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgLock
+ */
+#define XDDR_XMPU1_CFG_LOCK    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU1_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00Strt
+ */
+#define XDDR_XMPU1_CFG_R00_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU1_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00End
+ */
+#define XDDR_XMPU1_CFG_R00_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU1_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00Mstr
+ */
+#define XDDR_XMPU1_CFG_R00_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU1_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR00
+ */
+#define XDDR_XMPU1_CFG_R00    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU1_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01Strt
+ */
+#define XDDR_XMPU1_CFG_R01_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU1_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01End
+ */
+#define XDDR_XMPU1_CFG_R01_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU1_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01Mstr
+ */
+#define XDDR_XMPU1_CFG_R01_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU1_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR01
+ */
+#define XDDR_XMPU1_CFG_R01    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU1_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02Strt
+ */
+#define XDDR_XMPU1_CFG_R02_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU1_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02End
+ */
+#define XDDR_XMPU1_CFG_R02_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU1_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02Mstr
+ */
+#define XDDR_XMPU1_CFG_R02_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU1_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR02
+ */
+#define XDDR_XMPU1_CFG_R02    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU1_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03Strt
+ */
+#define XDDR_XMPU1_CFG_R03_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU1_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03End
+ */
+#define XDDR_XMPU1_CFG_R03_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU1_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03Mstr
+ */
+#define XDDR_XMPU1_CFG_R03_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU1_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR03
+ */
+#define XDDR_XMPU1_CFG_R03    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU1_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04Strt
+ */
+#define XDDR_XMPU1_CFG_R04_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU1_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04End
+ */
+#define XDDR_XMPU1_CFG_R04_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU1_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04Mstr
+ */
+#define XDDR_XMPU1_CFG_R04_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU1_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR04
+ */
+#define XDDR_XMPU1_CFG_R04    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU1_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05Strt
+ */
+#define XDDR_XMPU1_CFG_R05_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU1_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05End
+ */
+#define XDDR_XMPU1_CFG_R05_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU1_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05Mstr
+ */
+#define XDDR_XMPU1_CFG_R05_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU1_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR05
+ */
+#define XDDR_XMPU1_CFG_R05    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU1_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06Strt
+ */
+#define XDDR_XMPU1_CFG_R06_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU1_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06End
+ */
+#define XDDR_XMPU1_CFG_R06_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU1_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06Mstr
+ */
+#define XDDR_XMPU1_CFG_R06_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU1_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR06
+ */
+#define XDDR_XMPU1_CFG_R06    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU1_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07Strt
+ */
+#define XDDR_XMPU1_CFG_R07_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU1_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07End
+ */
+#define XDDR_XMPU1_CFG_R07_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU1_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07Mstr
+ */
+#define XDDR_XMPU1_CFG_R07_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU1_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR07
+ */
+#define XDDR_XMPU1_CFG_R07    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU1_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08Strt
+ */
+#define XDDR_XMPU1_CFG_R08_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU1_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08End
+ */
+#define XDDR_XMPU1_CFG_R08_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU1_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08Mstr
+ */
+#define XDDR_XMPU1_CFG_R08_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU1_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR08
+ */
+#define XDDR_XMPU1_CFG_R08    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU1_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09Strt
+ */
+#define XDDR_XMPU1_CFG_R09_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU1_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09End
+ */
+#define XDDR_XMPU1_CFG_R09_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU1_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09Mstr
+ */
+#define XDDR_XMPU1_CFG_R09_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU1_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR09
+ */
+#define XDDR_XMPU1_CFG_R09    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU1_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10Strt
+ */
+#define XDDR_XMPU1_CFG_R10_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU1_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10End
+ */
+#define XDDR_XMPU1_CFG_R10_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU1_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10Mstr
+ */
+#define XDDR_XMPU1_CFG_R10_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU1_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR10
+ */
+#define XDDR_XMPU1_CFG_R10    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU1_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11Strt
+ */
+#define XDDR_XMPU1_CFG_R11_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU1_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11End
+ */
+#define XDDR_XMPU1_CFG_R11_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU1_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11Mstr
+ */
+#define XDDR_XMPU1_CFG_R11_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU1_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR11
+ */
+#define XDDR_XMPU1_CFG_R11    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU1_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12Strt
+ */
+#define XDDR_XMPU1_CFG_R12_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU1_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12End
+ */
+#define XDDR_XMPU1_CFG_R12_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU1_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12Mstr
+ */
+#define XDDR_XMPU1_CFG_R12_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU1_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR12
+ */
+#define XDDR_XMPU1_CFG_R12    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU1_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13Strt
+ */
+#define XDDR_XMPU1_CFG_R13_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU1_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13End
+ */
+#define XDDR_XMPU1_CFG_R13_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU1_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13Mstr
+ */
+#define XDDR_XMPU1_CFG_R13_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU1_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR13
+ */
+#define XDDR_XMPU1_CFG_R13    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU1_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14Strt
+ */
+#define XDDR_XMPU1_CFG_R14_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU1_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14End
+ */
+#define XDDR_XMPU1_CFG_R14_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU1_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14Mstr
+ */
+#define XDDR_XMPU1_CFG_R14_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU1_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR14
+ */
+#define XDDR_XMPU1_CFG_R14    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU1_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15Strt
+ */
+#define XDDR_XMPU1_CFG_R15_STRT    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU1_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15End
+ */
+#define XDDR_XMPU1_CFG_R15_END    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU1_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU1_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU1_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15Mstr
+ */
+#define XDDR_XMPU1_CFG_R15_MSTR    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU1_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU1_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU1_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu1CfgR15
+ */
+#define XDDR_XMPU1_CFG_R15    ( ( XDDR_XMPU1_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU1_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU1_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU1_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU1_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU1_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU1_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU1_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU1_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU1_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU1_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU1_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU1_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU1_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU1_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu2_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu2_cfg.h
new file mode 100644
index 000000000..55ea2a7d3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu2_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU2_CFG_H__
+#define __XDDR_XMPU2_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu2Cfg Base Address
+ */
+#define XDDR_XMPU2_CFG_BASEADDR      0xFD020000UL
+
+/**
+ * Register: XddrXmpu2CfgCtrl
+ */
+#define XDDR_XMPU2_CFG_CTRL    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU2_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu2CfgErrSts1
+ */
+#define XDDR_XMPU2_CFG_ERR_STS1    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU2_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU2_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgErrSts2
+ */
+#define XDDR_XMPU2_CFG_ERR_STS2    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU2_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgPoison
+ */
+#define XDDR_XMPU2_CFG_POISON    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU2_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU2_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU2_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU2_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU2_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgIsr
+ */
+#define XDDR_XMPU2_CFG_ISR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU2_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgImr
+ */
+#define XDDR_XMPU2_CFG_IMR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU2_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu2CfgIen
+ */
+#define XDDR_XMPU2_CFG_IEN    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU2_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgIds
+ */
+#define XDDR_XMPU2_CFG_IDS    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU2_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU2_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU2_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgLock
+ */
+#define XDDR_XMPU2_CFG_LOCK    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU2_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00Strt
+ */
+#define XDDR_XMPU2_CFG_R00_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU2_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00End
+ */
+#define XDDR_XMPU2_CFG_R00_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU2_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00Mstr
+ */
+#define XDDR_XMPU2_CFG_R00_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU2_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR00
+ */
+#define XDDR_XMPU2_CFG_R00    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU2_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01Strt
+ */
+#define XDDR_XMPU2_CFG_R01_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU2_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01End
+ */
+#define XDDR_XMPU2_CFG_R01_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU2_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01Mstr
+ */
+#define XDDR_XMPU2_CFG_R01_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU2_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR01
+ */
+#define XDDR_XMPU2_CFG_R01    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU2_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02Strt
+ */
+#define XDDR_XMPU2_CFG_R02_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU2_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02End
+ */
+#define XDDR_XMPU2_CFG_R02_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU2_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02Mstr
+ */
+#define XDDR_XMPU2_CFG_R02_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU2_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR02
+ */
+#define XDDR_XMPU2_CFG_R02    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU2_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03Strt
+ */
+#define XDDR_XMPU2_CFG_R03_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU2_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03End
+ */
+#define XDDR_XMPU2_CFG_R03_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU2_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03Mstr
+ */
+#define XDDR_XMPU2_CFG_R03_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU2_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR03
+ */
+#define XDDR_XMPU2_CFG_R03    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU2_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04Strt
+ */
+#define XDDR_XMPU2_CFG_R04_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU2_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04End
+ */
+#define XDDR_XMPU2_CFG_R04_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU2_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04Mstr
+ */
+#define XDDR_XMPU2_CFG_R04_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU2_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR04
+ */
+#define XDDR_XMPU2_CFG_R04    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU2_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05Strt
+ */
+#define XDDR_XMPU2_CFG_R05_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU2_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05End
+ */
+#define XDDR_XMPU2_CFG_R05_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU2_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05Mstr
+ */
+#define XDDR_XMPU2_CFG_R05_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU2_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR05
+ */
+#define XDDR_XMPU2_CFG_R05    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU2_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06Strt
+ */
+#define XDDR_XMPU2_CFG_R06_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU2_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06End
+ */
+#define XDDR_XMPU2_CFG_R06_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU2_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06Mstr
+ */
+#define XDDR_XMPU2_CFG_R06_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU2_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR06
+ */
+#define XDDR_XMPU2_CFG_R06    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU2_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07Strt
+ */
+#define XDDR_XMPU2_CFG_R07_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU2_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07End
+ */
+#define XDDR_XMPU2_CFG_R07_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU2_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07Mstr
+ */
+#define XDDR_XMPU2_CFG_R07_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU2_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR07
+ */
+#define XDDR_XMPU2_CFG_R07    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU2_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08Strt
+ */
+#define XDDR_XMPU2_CFG_R08_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU2_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08End
+ */
+#define XDDR_XMPU2_CFG_R08_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU2_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08Mstr
+ */
+#define XDDR_XMPU2_CFG_R08_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU2_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR08
+ */
+#define XDDR_XMPU2_CFG_R08    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU2_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09Strt
+ */
+#define XDDR_XMPU2_CFG_R09_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU2_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09End
+ */
+#define XDDR_XMPU2_CFG_R09_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU2_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09Mstr
+ */
+#define XDDR_XMPU2_CFG_R09_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU2_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR09
+ */
+#define XDDR_XMPU2_CFG_R09    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU2_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10Strt
+ */
+#define XDDR_XMPU2_CFG_R10_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU2_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10End
+ */
+#define XDDR_XMPU2_CFG_R10_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU2_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10Mstr
+ */
+#define XDDR_XMPU2_CFG_R10_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU2_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR10
+ */
+#define XDDR_XMPU2_CFG_R10    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU2_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11Strt
+ */
+#define XDDR_XMPU2_CFG_R11_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU2_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11End
+ */
+#define XDDR_XMPU2_CFG_R11_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU2_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11Mstr
+ */
+#define XDDR_XMPU2_CFG_R11_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU2_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR11
+ */
+#define XDDR_XMPU2_CFG_R11    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU2_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12Strt
+ */
+#define XDDR_XMPU2_CFG_R12_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU2_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12End
+ */
+#define XDDR_XMPU2_CFG_R12_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU2_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12Mstr
+ */
+#define XDDR_XMPU2_CFG_R12_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU2_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR12
+ */
+#define XDDR_XMPU2_CFG_R12    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU2_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13Strt
+ */
+#define XDDR_XMPU2_CFG_R13_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU2_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13End
+ */
+#define XDDR_XMPU2_CFG_R13_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU2_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13Mstr
+ */
+#define XDDR_XMPU2_CFG_R13_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU2_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR13
+ */
+#define XDDR_XMPU2_CFG_R13    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU2_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14Strt
+ */
+#define XDDR_XMPU2_CFG_R14_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU2_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14End
+ */
+#define XDDR_XMPU2_CFG_R14_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU2_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14Mstr
+ */
+#define XDDR_XMPU2_CFG_R14_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU2_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR14
+ */
+#define XDDR_XMPU2_CFG_R14    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU2_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15Strt
+ */
+#define XDDR_XMPU2_CFG_R15_STRT    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU2_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15End
+ */
+#define XDDR_XMPU2_CFG_R15_END    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU2_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU2_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU2_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15Mstr
+ */
+#define XDDR_XMPU2_CFG_R15_MSTR    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU2_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU2_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU2_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu2CfgR15
+ */
+#define XDDR_XMPU2_CFG_R15    ( ( XDDR_XMPU2_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU2_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU2_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU2_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU2_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU2_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU2_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU2_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU2_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU2_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU2_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU2_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU2_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU2_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU2_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu3_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu3_cfg.h
new file mode 100644
index 000000000..416314967
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu3_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU3_CFG_H__
+#define __XDDR_XMPU3_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu3Cfg Base Address
+ */
+#define XDDR_XMPU3_CFG_BASEADDR      0xFD030000UL
+
+/**
+ * Register: XddrXmpu3CfgCtrl
+ */
+#define XDDR_XMPU3_CFG_CTRL    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU3_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu3CfgErrSts1
+ */
+#define XDDR_XMPU3_CFG_ERR_STS1    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU3_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU3_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgErrSts2
+ */
+#define XDDR_XMPU3_CFG_ERR_STS2    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU3_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgPoison
+ */
+#define XDDR_XMPU3_CFG_POISON    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU3_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU3_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU3_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU3_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU3_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgIsr
+ */
+#define XDDR_XMPU3_CFG_ISR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU3_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgImr
+ */
+#define XDDR_XMPU3_CFG_IMR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU3_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu3CfgIen
+ */
+#define XDDR_XMPU3_CFG_IEN    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU3_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgIds
+ */
+#define XDDR_XMPU3_CFG_IDS    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU3_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU3_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU3_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgLock
+ */
+#define XDDR_XMPU3_CFG_LOCK    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU3_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00Strt
+ */
+#define XDDR_XMPU3_CFG_R00_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU3_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00End
+ */
+#define XDDR_XMPU3_CFG_R00_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU3_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00Mstr
+ */
+#define XDDR_XMPU3_CFG_R00_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU3_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR00
+ */
+#define XDDR_XMPU3_CFG_R00    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU3_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01Strt
+ */
+#define XDDR_XMPU3_CFG_R01_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU3_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01End
+ */
+#define XDDR_XMPU3_CFG_R01_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU3_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01Mstr
+ */
+#define XDDR_XMPU3_CFG_R01_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU3_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR01
+ */
+#define XDDR_XMPU3_CFG_R01    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU3_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02Strt
+ */
+#define XDDR_XMPU3_CFG_R02_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU3_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02End
+ */
+#define XDDR_XMPU3_CFG_R02_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU3_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02Mstr
+ */
+#define XDDR_XMPU3_CFG_R02_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU3_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR02
+ */
+#define XDDR_XMPU3_CFG_R02    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU3_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03Strt
+ */
+#define XDDR_XMPU3_CFG_R03_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU3_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03End
+ */
+#define XDDR_XMPU3_CFG_R03_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU3_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03Mstr
+ */
+#define XDDR_XMPU3_CFG_R03_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU3_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR03
+ */
+#define XDDR_XMPU3_CFG_R03    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU3_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04Strt
+ */
+#define XDDR_XMPU3_CFG_R04_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU3_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04End
+ */
+#define XDDR_XMPU3_CFG_R04_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU3_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04Mstr
+ */
+#define XDDR_XMPU3_CFG_R04_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU3_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR04
+ */
+#define XDDR_XMPU3_CFG_R04    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU3_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05Strt
+ */
+#define XDDR_XMPU3_CFG_R05_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU3_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05End
+ */
+#define XDDR_XMPU3_CFG_R05_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU3_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05Mstr
+ */
+#define XDDR_XMPU3_CFG_R05_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU3_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR05
+ */
+#define XDDR_XMPU3_CFG_R05    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU3_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06Strt
+ */
+#define XDDR_XMPU3_CFG_R06_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU3_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06End
+ */
+#define XDDR_XMPU3_CFG_R06_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU3_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06Mstr
+ */
+#define XDDR_XMPU3_CFG_R06_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU3_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR06
+ */
+#define XDDR_XMPU3_CFG_R06    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU3_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07Strt
+ */
+#define XDDR_XMPU3_CFG_R07_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU3_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07End
+ */
+#define XDDR_XMPU3_CFG_R07_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU3_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07Mstr
+ */
+#define XDDR_XMPU3_CFG_R07_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU3_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR07
+ */
+#define XDDR_XMPU3_CFG_R07    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU3_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08Strt
+ */
+#define XDDR_XMPU3_CFG_R08_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU3_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08End
+ */
+#define XDDR_XMPU3_CFG_R08_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU3_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08Mstr
+ */
+#define XDDR_XMPU3_CFG_R08_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU3_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR08
+ */
+#define XDDR_XMPU3_CFG_R08    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU3_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09Strt
+ */
+#define XDDR_XMPU3_CFG_R09_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU3_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09End
+ */
+#define XDDR_XMPU3_CFG_R09_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU3_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09Mstr
+ */
+#define XDDR_XMPU3_CFG_R09_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU3_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR09
+ */
+#define XDDR_XMPU3_CFG_R09    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU3_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10Strt
+ */
+#define XDDR_XMPU3_CFG_R10_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU3_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10End
+ */
+#define XDDR_XMPU3_CFG_R10_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU3_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10Mstr
+ */
+#define XDDR_XMPU3_CFG_R10_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU3_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR10
+ */
+#define XDDR_XMPU3_CFG_R10    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU3_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11Strt
+ */
+#define XDDR_XMPU3_CFG_R11_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU3_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11End
+ */
+#define XDDR_XMPU3_CFG_R11_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU3_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11Mstr
+ */
+#define XDDR_XMPU3_CFG_R11_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU3_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR11
+ */
+#define XDDR_XMPU3_CFG_R11    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU3_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12Strt
+ */
+#define XDDR_XMPU3_CFG_R12_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU3_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12End
+ */
+#define XDDR_XMPU3_CFG_R12_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU3_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12Mstr
+ */
+#define XDDR_XMPU3_CFG_R12_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU3_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR12
+ */
+#define XDDR_XMPU3_CFG_R12    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU3_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13Strt
+ */
+#define XDDR_XMPU3_CFG_R13_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU3_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13End
+ */
+#define XDDR_XMPU3_CFG_R13_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU3_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13Mstr
+ */
+#define XDDR_XMPU3_CFG_R13_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU3_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR13
+ */
+#define XDDR_XMPU3_CFG_R13    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU3_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14Strt
+ */
+#define XDDR_XMPU3_CFG_R14_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU3_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14End
+ */
+#define XDDR_XMPU3_CFG_R14_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU3_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14Mstr
+ */
+#define XDDR_XMPU3_CFG_R14_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU3_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR14
+ */
+#define XDDR_XMPU3_CFG_R14    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU3_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15Strt
+ */
+#define XDDR_XMPU3_CFG_R15_STRT    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU3_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15End
+ */
+#define XDDR_XMPU3_CFG_R15_END    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU3_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU3_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU3_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15Mstr
+ */
+#define XDDR_XMPU3_CFG_R15_MSTR    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU3_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU3_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU3_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu3CfgR15
+ */
+#define XDDR_XMPU3_CFG_R15    ( ( XDDR_XMPU3_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU3_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU3_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU3_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU3_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU3_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU3_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU3_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU3_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU3_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU3_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU3_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU3_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU3_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU3_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu4_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu4_cfg.h
new file mode 100644
index 000000000..2df814419
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu4_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU4_CFG_H__
+#define __XDDR_XMPU4_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu4Cfg Base Address
+ */
+#define XDDR_XMPU4_CFG_BASEADDR      0xFD040000UL
+
+/**
+ * Register: XddrXmpu4CfgCtrl
+ */
+#define XDDR_XMPU4_CFG_CTRL    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU4_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu4CfgErrSts1
+ */
+#define XDDR_XMPU4_CFG_ERR_STS1    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU4_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU4_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgErrSts2
+ */
+#define XDDR_XMPU4_CFG_ERR_STS2    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU4_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgPoison
+ */
+#define XDDR_XMPU4_CFG_POISON    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU4_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU4_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU4_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU4_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU4_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgIsr
+ */
+#define XDDR_XMPU4_CFG_ISR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU4_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgImr
+ */
+#define XDDR_XMPU4_CFG_IMR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU4_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu4CfgIen
+ */
+#define XDDR_XMPU4_CFG_IEN    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU4_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgIds
+ */
+#define XDDR_XMPU4_CFG_IDS    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU4_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU4_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU4_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgLock
+ */
+#define XDDR_XMPU4_CFG_LOCK    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU4_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00Strt
+ */
+#define XDDR_XMPU4_CFG_R00_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU4_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00End
+ */
+#define XDDR_XMPU4_CFG_R00_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU4_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00Mstr
+ */
+#define XDDR_XMPU4_CFG_R00_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU4_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR00
+ */
+#define XDDR_XMPU4_CFG_R00    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU4_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01Strt
+ */
+#define XDDR_XMPU4_CFG_R01_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU4_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01End
+ */
+#define XDDR_XMPU4_CFG_R01_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU4_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01Mstr
+ */
+#define XDDR_XMPU4_CFG_R01_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU4_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR01
+ */
+#define XDDR_XMPU4_CFG_R01    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU4_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02Strt
+ */
+#define XDDR_XMPU4_CFG_R02_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU4_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02End
+ */
+#define XDDR_XMPU4_CFG_R02_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU4_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02Mstr
+ */
+#define XDDR_XMPU4_CFG_R02_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU4_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR02
+ */
+#define XDDR_XMPU4_CFG_R02    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU4_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03Strt
+ */
+#define XDDR_XMPU4_CFG_R03_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU4_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03End
+ */
+#define XDDR_XMPU4_CFG_R03_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU4_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03Mstr
+ */
+#define XDDR_XMPU4_CFG_R03_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU4_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR03
+ */
+#define XDDR_XMPU4_CFG_R03    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU4_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04Strt
+ */
+#define XDDR_XMPU4_CFG_R04_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU4_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04End
+ */
+#define XDDR_XMPU4_CFG_R04_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU4_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04Mstr
+ */
+#define XDDR_XMPU4_CFG_R04_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU4_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR04
+ */
+#define XDDR_XMPU4_CFG_R04    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU4_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05Strt
+ */
+#define XDDR_XMPU4_CFG_R05_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU4_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05End
+ */
+#define XDDR_XMPU4_CFG_R05_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU4_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05Mstr
+ */
+#define XDDR_XMPU4_CFG_R05_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU4_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR05
+ */
+#define XDDR_XMPU4_CFG_R05    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU4_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06Strt
+ */
+#define XDDR_XMPU4_CFG_R06_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU4_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06End
+ */
+#define XDDR_XMPU4_CFG_R06_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU4_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06Mstr
+ */
+#define XDDR_XMPU4_CFG_R06_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU4_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR06
+ */
+#define XDDR_XMPU4_CFG_R06    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU4_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07Strt
+ */
+#define XDDR_XMPU4_CFG_R07_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU4_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07End
+ */
+#define XDDR_XMPU4_CFG_R07_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU4_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07Mstr
+ */
+#define XDDR_XMPU4_CFG_R07_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU4_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR07
+ */
+#define XDDR_XMPU4_CFG_R07    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU4_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08Strt
+ */
+#define XDDR_XMPU4_CFG_R08_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU4_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08End
+ */
+#define XDDR_XMPU4_CFG_R08_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU4_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08Mstr
+ */
+#define XDDR_XMPU4_CFG_R08_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU4_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR08
+ */
+#define XDDR_XMPU4_CFG_R08    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU4_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09Strt
+ */
+#define XDDR_XMPU4_CFG_R09_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU4_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09End
+ */
+#define XDDR_XMPU4_CFG_R09_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU4_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09Mstr
+ */
+#define XDDR_XMPU4_CFG_R09_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU4_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR09
+ */
+#define XDDR_XMPU4_CFG_R09    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU4_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10Strt
+ */
+#define XDDR_XMPU4_CFG_R10_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU4_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10End
+ */
+#define XDDR_XMPU4_CFG_R10_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU4_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10Mstr
+ */
+#define XDDR_XMPU4_CFG_R10_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU4_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR10
+ */
+#define XDDR_XMPU4_CFG_R10    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU4_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11Strt
+ */
+#define XDDR_XMPU4_CFG_R11_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU4_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11End
+ */
+#define XDDR_XMPU4_CFG_R11_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU4_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11Mstr
+ */
+#define XDDR_XMPU4_CFG_R11_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU4_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR11
+ */
+#define XDDR_XMPU4_CFG_R11    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU4_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12Strt
+ */
+#define XDDR_XMPU4_CFG_R12_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU4_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12End
+ */
+#define XDDR_XMPU4_CFG_R12_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU4_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12Mstr
+ */
+#define XDDR_XMPU4_CFG_R12_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU4_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR12
+ */
+#define XDDR_XMPU4_CFG_R12    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU4_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13Strt
+ */
+#define XDDR_XMPU4_CFG_R13_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU4_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13End
+ */
+#define XDDR_XMPU4_CFG_R13_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU4_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13Mstr
+ */
+#define XDDR_XMPU4_CFG_R13_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU4_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR13
+ */
+#define XDDR_XMPU4_CFG_R13    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU4_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14Strt
+ */
+#define XDDR_XMPU4_CFG_R14_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU4_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14End
+ */
+#define XDDR_XMPU4_CFG_R14_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU4_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14Mstr
+ */
+#define XDDR_XMPU4_CFG_R14_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU4_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR14
+ */
+#define XDDR_XMPU4_CFG_R14    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU4_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15Strt
+ */
+#define XDDR_XMPU4_CFG_R15_STRT    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU4_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15End
+ */
+#define XDDR_XMPU4_CFG_R15_END    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU4_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU4_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU4_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15Mstr
+ */
+#define XDDR_XMPU4_CFG_R15_MSTR    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU4_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU4_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU4_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu4CfgR15
+ */
+#define XDDR_XMPU4_CFG_R15    ( ( XDDR_XMPU4_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU4_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU4_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU4_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU4_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU4_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU4_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU4_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU4_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU4_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU4_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU4_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU4_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU4_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU4_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu5_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu5_cfg.h
new file mode 100644
index 000000000..60811718d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xddr_xmpu5_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XDDR_XMPU5_CFG_H__
+#define __XDDR_XMPU5_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XddrXmpu5Cfg Base Address
+ */
+#define XDDR_XMPU5_CFG_BASEADDR      0xFD050000UL
+
+/**
+ * Register: XddrXmpu5CfgCtrl
+ */
+#define XDDR_XMPU5_CFG_CTRL    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000000UL )
+#define XDDR_XMPU5_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu5CfgErrSts1
+ */
+#define XDDR_XMPU5_CFG_ERR_STS1    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000004UL )
+#define XDDR_XMPU5_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XDDR_XMPU5_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgErrSts2
+ */
+#define XDDR_XMPU5_CFG_ERR_STS2    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000008UL )
+#define XDDR_XMPU5_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgPoison
+ */
+#define XDDR_XMPU5_CFG_POISON    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000000CUL )
+#define XDDR_XMPU5_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XDDR_XMPU5_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_POISON_BASE_SHIFT   0UL
+#define XDDR_XMPU5_CFG_POISON_BASE_WIDTH   20UL
+#define XDDR_XMPU5_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XDDR_XMPU5_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgIsr
+ */
+#define XDDR_XMPU5_CFG_ISR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000010UL )
+#define XDDR_XMPU5_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_ISR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_ISR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgImr
+ */
+#define XDDR_XMPU5_CFG_IMR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000014UL )
+#define XDDR_XMPU5_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_IMR_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_IMR_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XddrXmpu5CfgIen
+ */
+#define XDDR_XMPU5_CFG_IEN    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000018UL )
+#define XDDR_XMPU5_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IEN_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_IEN_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgIds
+ */
+#define XDDR_XMPU5_CFG_IDS    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000001CUL )
+#define XDDR_XMPU5_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_IDS_INV_APB_SHIFT   0UL
+#define XDDR_XMPU5_CFG_IDS_INV_APB_WIDTH   1UL
+#define XDDR_XMPU5_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgLock
+ */
+#define XDDR_XMPU5_CFG_LOCK    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000020UL )
+#define XDDR_XMPU5_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00Strt
+ */
+#define XDDR_XMPU5_CFG_R00_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000100UL )
+#define XDDR_XMPU5_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00End
+ */
+#define XDDR_XMPU5_CFG_R00_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000104UL )
+#define XDDR_XMPU5_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R00_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00Mstr
+ */
+#define XDDR_XMPU5_CFG_R00_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000108UL )
+#define XDDR_XMPU5_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR00
+ */
+#define XDDR_XMPU5_CFG_R00    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000010CUL )
+#define XDDR_XMPU5_CFG_R00_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R00_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R00_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R00_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R00_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R00_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R00_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R00_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01Strt
+ */
+#define XDDR_XMPU5_CFG_R01_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000110UL )
+#define XDDR_XMPU5_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01End
+ */
+#define XDDR_XMPU5_CFG_R01_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000114UL )
+#define XDDR_XMPU5_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R01_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01Mstr
+ */
+#define XDDR_XMPU5_CFG_R01_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000118UL )
+#define XDDR_XMPU5_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR01
+ */
+#define XDDR_XMPU5_CFG_R01    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000011CUL )
+#define XDDR_XMPU5_CFG_R01_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R01_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R01_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R01_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R01_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R01_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R01_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R01_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02Strt
+ */
+#define XDDR_XMPU5_CFG_R02_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000120UL )
+#define XDDR_XMPU5_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02End
+ */
+#define XDDR_XMPU5_CFG_R02_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000124UL )
+#define XDDR_XMPU5_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R02_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02Mstr
+ */
+#define XDDR_XMPU5_CFG_R02_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000128UL )
+#define XDDR_XMPU5_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR02
+ */
+#define XDDR_XMPU5_CFG_R02    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000012CUL )
+#define XDDR_XMPU5_CFG_R02_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R02_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R02_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R02_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R02_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R02_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R02_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R02_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03Strt
+ */
+#define XDDR_XMPU5_CFG_R03_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000130UL )
+#define XDDR_XMPU5_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03End
+ */
+#define XDDR_XMPU5_CFG_R03_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000134UL )
+#define XDDR_XMPU5_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R03_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03Mstr
+ */
+#define XDDR_XMPU5_CFG_R03_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000138UL )
+#define XDDR_XMPU5_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR03
+ */
+#define XDDR_XMPU5_CFG_R03    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000013CUL )
+#define XDDR_XMPU5_CFG_R03_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R03_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R03_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R03_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R03_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R03_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R03_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R03_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04Strt
+ */
+#define XDDR_XMPU5_CFG_R04_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000140UL )
+#define XDDR_XMPU5_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04End
+ */
+#define XDDR_XMPU5_CFG_R04_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000144UL )
+#define XDDR_XMPU5_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R04_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04Mstr
+ */
+#define XDDR_XMPU5_CFG_R04_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000148UL )
+#define XDDR_XMPU5_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR04
+ */
+#define XDDR_XMPU5_CFG_R04    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000014CUL )
+#define XDDR_XMPU5_CFG_R04_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R04_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R04_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R04_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R04_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R04_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R04_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R04_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05Strt
+ */
+#define XDDR_XMPU5_CFG_R05_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000150UL )
+#define XDDR_XMPU5_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05End
+ */
+#define XDDR_XMPU5_CFG_R05_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000154UL )
+#define XDDR_XMPU5_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R05_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05Mstr
+ */
+#define XDDR_XMPU5_CFG_R05_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000158UL )
+#define XDDR_XMPU5_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR05
+ */
+#define XDDR_XMPU5_CFG_R05    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000015CUL )
+#define XDDR_XMPU5_CFG_R05_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R05_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R05_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R05_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R05_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R05_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R05_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R05_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06Strt
+ */
+#define XDDR_XMPU5_CFG_R06_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000160UL )
+#define XDDR_XMPU5_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06End
+ */
+#define XDDR_XMPU5_CFG_R06_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000164UL )
+#define XDDR_XMPU5_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R06_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06Mstr
+ */
+#define XDDR_XMPU5_CFG_R06_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000168UL )
+#define XDDR_XMPU5_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR06
+ */
+#define XDDR_XMPU5_CFG_R06    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000016CUL )
+#define XDDR_XMPU5_CFG_R06_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R06_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R06_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R06_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R06_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R06_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R06_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R06_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07Strt
+ */
+#define XDDR_XMPU5_CFG_R07_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000170UL )
+#define XDDR_XMPU5_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07End
+ */
+#define XDDR_XMPU5_CFG_R07_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000174UL )
+#define XDDR_XMPU5_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R07_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07Mstr
+ */
+#define XDDR_XMPU5_CFG_R07_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000178UL )
+#define XDDR_XMPU5_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR07
+ */
+#define XDDR_XMPU5_CFG_R07    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000017CUL )
+#define XDDR_XMPU5_CFG_R07_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R07_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R07_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R07_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R07_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R07_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R07_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R07_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08Strt
+ */
+#define XDDR_XMPU5_CFG_R08_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000180UL )
+#define XDDR_XMPU5_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08End
+ */
+#define XDDR_XMPU5_CFG_R08_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000184UL )
+#define XDDR_XMPU5_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R08_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08Mstr
+ */
+#define XDDR_XMPU5_CFG_R08_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000188UL )
+#define XDDR_XMPU5_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR08
+ */
+#define XDDR_XMPU5_CFG_R08    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000018CUL )
+#define XDDR_XMPU5_CFG_R08_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R08_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R08_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R08_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R08_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R08_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R08_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R08_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09Strt
+ */
+#define XDDR_XMPU5_CFG_R09_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000190UL )
+#define XDDR_XMPU5_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09End
+ */
+#define XDDR_XMPU5_CFG_R09_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000194UL )
+#define XDDR_XMPU5_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R09_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09Mstr
+ */
+#define XDDR_XMPU5_CFG_R09_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x00000198UL )
+#define XDDR_XMPU5_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR09
+ */
+#define XDDR_XMPU5_CFG_R09    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x0000019CUL )
+#define XDDR_XMPU5_CFG_R09_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R09_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R09_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R09_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R09_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R09_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R09_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R09_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10Strt
+ */
+#define XDDR_XMPU5_CFG_R10_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A0UL )
+#define XDDR_XMPU5_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10End
+ */
+#define XDDR_XMPU5_CFG_R10_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A4UL )
+#define XDDR_XMPU5_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R10_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10Mstr
+ */
+#define XDDR_XMPU5_CFG_R10_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001A8UL )
+#define XDDR_XMPU5_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR10
+ */
+#define XDDR_XMPU5_CFG_R10    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ACUL )
+#define XDDR_XMPU5_CFG_R10_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R10_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R10_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R10_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R10_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R10_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R10_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R10_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11Strt
+ */
+#define XDDR_XMPU5_CFG_R11_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B0UL )
+#define XDDR_XMPU5_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11End
+ */
+#define XDDR_XMPU5_CFG_R11_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B4UL )
+#define XDDR_XMPU5_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R11_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11Mstr
+ */
+#define XDDR_XMPU5_CFG_R11_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001B8UL )
+#define XDDR_XMPU5_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR11
+ */
+#define XDDR_XMPU5_CFG_R11    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001BCUL )
+#define XDDR_XMPU5_CFG_R11_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R11_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R11_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R11_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R11_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R11_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R11_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R11_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12Strt
+ */
+#define XDDR_XMPU5_CFG_R12_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C0UL )
+#define XDDR_XMPU5_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12End
+ */
+#define XDDR_XMPU5_CFG_R12_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C4UL )
+#define XDDR_XMPU5_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R12_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12Mstr
+ */
+#define XDDR_XMPU5_CFG_R12_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001C8UL )
+#define XDDR_XMPU5_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR12
+ */
+#define XDDR_XMPU5_CFG_R12    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001CCUL )
+#define XDDR_XMPU5_CFG_R12_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R12_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R12_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R12_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R12_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R12_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R12_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R12_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13Strt
+ */
+#define XDDR_XMPU5_CFG_R13_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D0UL )
+#define XDDR_XMPU5_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13End
+ */
+#define XDDR_XMPU5_CFG_R13_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D4UL )
+#define XDDR_XMPU5_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R13_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13Mstr
+ */
+#define XDDR_XMPU5_CFG_R13_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001D8UL )
+#define XDDR_XMPU5_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR13
+ */
+#define XDDR_XMPU5_CFG_R13    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001DCUL )
+#define XDDR_XMPU5_CFG_R13_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R13_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R13_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R13_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R13_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R13_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R13_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R13_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14Strt
+ */
+#define XDDR_XMPU5_CFG_R14_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E0UL )
+#define XDDR_XMPU5_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14End
+ */
+#define XDDR_XMPU5_CFG_R14_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E4UL )
+#define XDDR_XMPU5_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R14_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14Mstr
+ */
+#define XDDR_XMPU5_CFG_R14_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001E8UL )
+#define XDDR_XMPU5_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR14
+ */
+#define XDDR_XMPU5_CFG_R14    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001ECUL )
+#define XDDR_XMPU5_CFG_R14_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R14_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R14_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R14_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R14_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R14_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R14_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R14_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15Strt
+ */
+#define XDDR_XMPU5_CFG_R15_STRT    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F0UL )
+#define XDDR_XMPU5_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15End
+ */
+#define XDDR_XMPU5_CFG_R15_END    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F4UL )
+#define XDDR_XMPU5_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R15_END_ADDR_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_END_ADDR_WIDTH   28UL
+#define XDDR_XMPU5_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XDDR_XMPU5_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15Mstr
+ */
+#define XDDR_XMPU5_CFG_R15_MSTR    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001F8UL )
+#define XDDR_XMPU5_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XDDR_XMPU5_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XDDR_XMPU5_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XddrXmpu5CfgR15
+ */
+#define XDDR_XMPU5_CFG_R15    ( ( XDDR_XMPU5_CFG_BASEADDR ) + 0x000001FCUL )
+#define XDDR_XMPU5_CFG_R15_RSTVAL   0x00000008UL
+
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XDDR_XMPU5_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_REGNNS_SHIFT   3UL
+#define XDDR_XMPU5_CFG_R15_REGNNS_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XDDR_XMPU5_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XDDR_XMPU5_CFG_R15_WRALWD_SHIFT   2UL
+#define XDDR_XMPU5_CFG_R15_WRALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XDDR_XMPU5_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_RDALWD_SHIFT   1UL
+#define XDDR_XMPU5_CFG_R15_RDALWD_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XDDR_XMPU5_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XDDR_XMPU5_CFG_R15_EN_SHIFT   0UL
+#define XDDR_XMPU5_CFG_R15_EN_WIDTH   1UL
+#define XDDR_XMPU5_CFG_R15_EN_MASK    0x00000001UL
+#define XDDR_XMPU5_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XDDR_XMPU5_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr.h
new file mode 100644
index 000000000..b565b958a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr.h
@@ -0,0 +1,382 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_SLCR_H__
+#define __XFPD_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdSlcr Base Address
+ */
+#define XFPD_SLCR_BASEADDR      0xFD610000UL
+
+/**
+ * Register: XfpdSlcrWprot0
+ */
+#define XFPD_SLCR_WPROT0    ( ( XFPD_SLCR_BASEADDR ) + 0x00000000UL )
+#define XFPD_SLCR_WPROT0_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_WPROT0_ACT_SHIFT   0UL
+#define XFPD_SLCR_WPROT0_ACT_WIDTH   1UL
+#define XFPD_SLCR_WPROT0_ACT_MASK    0x00000001UL
+#define XFPD_SLCR_WPROT0_ACT_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrCtrl
+ */
+#define XFPD_SLCR_CTRL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000004UL )
+#define XFPD_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XFPD_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIsr
+ */
+#define XFPD_SLCR_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000008UL )
+#define XFPD_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrImr
+ */
+#define XFPD_SLCR_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000000CUL )
+#define XFPD_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrIer
+ */
+#define XFPD_SLCR_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00000010UL )
+#define XFPD_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIdr
+ */
+#define XFPD_SLCR_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000014UL )
+#define XFPD_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrItr
+ */
+#define XFPD_SLCR_ITR    ( ( XFPD_SLCR_BASEADDR ) + 0x00000018UL )
+#define XFPD_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrWdtClkSel
+ */
+#define XFPD_SLCR_WDT_CLK_SEL    ( ( XFPD_SLCR_BASEADDR ) + 0x00000100UL )
+#define XFPD_SLCR_WDT_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_WDT_CLK_SEL_SHIFT   0UL
+#define XFPD_SLCR_WDT_CLK_SEL_WIDTH   1UL
+#define XFPD_SLCR_WDT_CLK_SEL_MASK    0x00000001UL
+#define XFPD_SLCR_WDT_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrIntFpd
+ */
+#define XFPD_SLCR_INT_FPD    ( ( XFPD_SLCR_BASEADDR ) + 0x00000200UL )
+#define XFPD_SLCR_INT_FPD_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_INT_FPD_GFM_SEL_SHIFT   0UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_WIDTH   1UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_MASK    0x00000001UL
+#define XFPD_SLCR_INT_FPD_GFM_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrGpu
+ */
+#define XFPD_SLCR_GPU    ( ( XFPD_SLCR_BASEADDR ) + 0x0000100CUL )
+#define XFPD_SLCR_GPU_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_GPU_ARCACHE_SHIFT   7UL
+#define XFPD_SLCR_GPU_ARCACHE_WIDTH   4UL
+#define XFPD_SLCR_GPU_ARCACHE_MASK    0x00000780UL
+#define XFPD_SLCR_GPU_ARCACHE_DEFVAL  0x0UL
+
+#define XFPD_SLCR_GPU_AWCACHE_SHIFT   3UL
+#define XFPD_SLCR_GPU_AWCACHE_WIDTH   4UL
+#define XFPD_SLCR_GPU_AWCACHE_MASK    0x00000078UL
+#define XFPD_SLCR_GPU_AWCACHE_DEFVAL  0x0UL
+
+#define XFPD_SLCR_GPU_PP1_IDLE_SHIFT   2UL
+#define XFPD_SLCR_GPU_PP1_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_PP1_IDLE_MASK    0x00000004UL
+#define XFPD_SLCR_GPU_PP1_IDLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GPU_PP0_IDLE_SHIFT   1UL
+#define XFPD_SLCR_GPU_PP0_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_PP0_IDLE_MASK    0x00000002UL
+#define XFPD_SLCR_GPU_PP0_IDLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GPU_IDLE_SHIFT   0UL
+#define XFPD_SLCR_GPU_IDLE_WIDTH   1UL
+#define XFPD_SLCR_GPU_IDLE_MASK    0x00000001UL
+#define XFPD_SLCR_GPU_IDLE_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrGdmaCfg
+ */
+#define XFPD_SLCR_GDMA_CFG    ( ( XFPD_SLCR_BASEADDR ) + 0x00003000UL )
+#define XFPD_SLCR_GDMA_CFG_RSTVAL   0x00000048UL
+
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_SHIFT   5UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_WIDTH   2UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_MASK    0x00000060UL
+#define XFPD_SLCR_GDMA_CFG_BUS_WIDTH_DEFVAL  0x2UL
+
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_SHIFT   0UL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_WIDTH   5UL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_MASK    0x0000001fUL
+#define XFPD_SLCR_GDMA_CFG_NUM_CH_DEFVAL  0x8UL
+
+/**
+ * Register: XfpdSlcrGdma
+ */
+#define XFPD_SLCR_GDMA    ( ( XFPD_SLCR_BASEADDR ) + 0x00003010UL )
+#define XFPD_SLCR_GDMA_RSTVAL   0x00003b3bUL
+
+#define XFPD_SLCR_GDMA_RAM1_EMAB_SHIFT   12UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_MASK    0x00007000UL
+#define XFPD_SLCR_GDMA_RAM1_EMAB_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM1_EMASA_SHIFT   11UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_WIDTH   1UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_MASK    0x00000800UL
+#define XFPD_SLCR_GDMA_RAM1_EMASA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GDMA_RAM1_EMAA_SHIFT   8UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_MASK    0x00000700UL
+#define XFPD_SLCR_GDMA_RAM1_EMAA_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMAB_SHIFT   4UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_MASK    0x00000070UL
+#define XFPD_SLCR_GDMA_RAM0_EMAB_DEFVAL  0x3UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMASA_SHIFT   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_WIDTH   1UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_MASK    0x00000008UL
+#define XFPD_SLCR_GDMA_RAM0_EMASA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_GDMA_RAM0_EMAA_SHIFT   0UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_WIDTH   3UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_MASK    0x00000007UL
+#define XFPD_SLCR_GDMA_RAM0_EMAA_DEFVAL  0x3UL
+
+/**
+ * Register: XfpdSlcrAfiFs
+ */
+#define XFPD_SLCR_AFI_FS    ( ( XFPD_SLCR_BASEADDR ) + 0x00005000UL )
+#define XFPD_SLCR_AFI_FS_RSTVAL   0x00000a00UL
+
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_SHIFT   10UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_WIDTH   2UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_MASK    0x00000c00UL
+#define XFPD_SLCR_AFI_FS_DW_SS1_SEL_DEFVAL  0x2UL
+
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_SHIFT   8UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_WIDTH   2UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_MASK    0x00000300UL
+#define XFPD_SLCR_AFI_FS_DW_SS0_SEL_DEFVAL  0x2UL
+
+/**
+ * Register: XfpdSlcrErrAtbIsr
+ */
+#define XFPD_SLCR_ERR_ATB_ISR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006000UL )
+#define XFPD_SLCR_ERR_ATB_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_ISR_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_ISR_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrErrAtbImr
+ */
+#define XFPD_SLCR_ERR_ATB_IMR    ( ( XFPD_SLCR_BASEADDR ) + 0x00006004UL )
+#define XFPD_SLCR_ERR_ATB_IMR_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IMR_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IMR_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrErrAtbIer
+ */
+#define XFPD_SLCR_ERR_ATB_IER    ( ( XFPD_SLCR_BASEADDR ) + 0x00006008UL )
+#define XFPD_SLCR_ERR_ATB_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IER_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IER_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrErrAtbIdr
+ */
+#define XFPD_SLCR_ERR_ATB_IDR    ( ( XFPD_SLCR_BASEADDR ) + 0x0000600CUL )
+#define XFPD_SLCR_ERR_ATB_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ERR_ATB_IDR_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ERR_ATB_IDR_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrAtbCmdstore
+ */
+#define XFPD_SLCR_ATB_CMDSTORE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006010UL )
+#define XFPD_SLCR_ATB_CMDSTORE_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_CMDSTORE_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_CMDSTORE_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrAtbRespEn
+ */
+#define XFPD_SLCR_ATB_RESP_EN    ( ( XFPD_SLCR_BASEADDR ) + 0x00006014UL )
+#define XFPD_SLCR_ATB_RESP_EN_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS1_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_RESP_EN_AFIFS0_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_RESP_EN_FPDS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrAtbResptype
+ */
+#define XFPD_SLCR_ATB_RESPTYPE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006018UL )
+#define XFPD_SLCR_ATB_RESPTYPE_RSTVAL   0x00000007UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_SHIFT   2UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_MASK    0x00000004UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_SHIFT   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_MASK    0x00000002UL
+#define XFPD_SLCR_ATB_RESPTYPE_AFIFS0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_SHIFT   0UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_WIDTH   1UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_MASK    0x00000001UL
+#define XFPD_SLCR_ATB_RESPTYPE_FPDS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrAtbPrescale
+ */
+#define XFPD_SLCR_ATB_PRESCALE    ( ( XFPD_SLCR_BASEADDR ) + 0x00006020UL )
+#define XFPD_SLCR_ATB_PRESCALE_RSTVAL   0x0000ffffUL
+
+#define XFPD_SLCR_ATB_PRESCALE_EN_SHIFT   16UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_WIDTH   1UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_MASK    0x00010000UL
+#define XFPD_SLCR_ATB_PRESCALE_EN_DEFVAL  0x0UL
+
+#define XFPD_SLCR_ATB_PRESCALE_VAL_SHIFT   0UL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_WIDTH   16UL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_MASK    0x0000ffffUL
+#define XFPD_SLCR_ATB_PRESCALE_VAL_DEFVAL  0xffffUL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr_secure.h
new file mode 100644
index 000000000..6541a4f1d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_slcr_secure.h
@@ -0,0 +1,277 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_SLCR_SECURE_H__
+#define __XFPD_SLCR_SECURE_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdSlcrSecure Base Address
+ */
+#define XFPD_SLCR_SECURE_BASEADDR      0xFD690000UL
+
+/**
+ * Register: XfpdSlcrSecCtrl
+ */
+#define XFPD_SLCR_SEC_CTRL    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
+#define XFPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecIsr
+ */
+#define XFPD_SLCR_SEC_ISR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
+#define XFPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecImr
+ */
+#define XFPD_SLCR_SEC_IMR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
+#define XFPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecIer
+ */
+#define XFPD_SLCR_SEC_IER    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
+#define XFPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecIdr
+ */
+#define XFPD_SLCR_SEC_IDR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
+#define XFPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecItr
+ */
+#define XFPD_SLCR_SEC_ITR    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
+#define XFPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecSata
+ */
+#define XFPD_SLCR_SEC_SATA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
+#define XFPD_SLCR_SEC_SATA_RSTVAL   0x0000000eUL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_SHIFT   3UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_MASK    0x00000008UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_SHIFT   2UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_MASK    0x00000004UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIMDMA0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_SHIFT   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_MASK    0x00000002UL
+#define XFPD_SLCR_SEC_SATA_TZ_AXIS_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_SATA_TZ_EN_SHIFT   0UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_WIDTH   1UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_SATA_TZ_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdSlcrSecPcie
+ */
+#define XFPD_SLCR_SEC_PCIE    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
+#define XFPD_SLCR_SEC_PCIE_RSTVAL   0x01ffffffUL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_SHIFT   24UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_MASK    0x01000000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_SHIFT   23UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_MASK    0x00800000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_SHIFT   22UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_MASK    0x00400000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_SHIFT   21UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_MASK    0x00200000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_SHIFT   20UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_MASK    0x00100000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_7_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_SHIFT   19UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_MASK    0x00080000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_6_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_SHIFT   18UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_MASK    0x00040000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_5_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_SHIFT   17UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_MASK    0x00020000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_4_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_SHIFT   16UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_MASK    0x00010000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_SHIFT   15UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_MASK    0x00008000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_SHIFT   14UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_MASK    0x00004000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_SHIFT   13UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_MASK    0x00002000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_INGR_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_SHIFT   12UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_MASK    0x00001000UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_7_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_SHIFT   11UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_MASK    0x00000800UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_6_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_SHIFT   10UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_MASK    0x00000400UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_5_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_SHIFT   9UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_MASK    0x00000200UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_4_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_SHIFT   8UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_MASK    0x00000100UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_3_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_SHIFT   7UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_MASK    0x00000080UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_2_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_SHIFT   6UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_MASK    0x00000040UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_1_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_SHIFT   5UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_MASK    0x00000020UL
+#define XFPD_SLCR_SEC_PCIE_TZ_AT_EGR_0_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_SHIFT   4UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_MASK    0x00000010UL
+#define XFPD_SLCR_SEC_PCIE_TZ_DMA_REGS_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_SHIFT   3UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_MASK    0x00000008UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_PBA_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_SHIFT   2UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_MASK    0x00000004UL
+#define XFPD_SLCR_SEC_PCIE_TZ_MSIX_TABLE_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_SHIFT   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_MASK    0x00000002UL
+#define XFPD_SLCR_SEC_PCIE_TZ_ECAM_DEFVAL  0x1UL
+
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_SHIFT   0UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_WIDTH   1UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_PCIE_TZ_BRIDGE_REGS_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecDpdma
+ */
+#define XFPD_SLCR_SEC_DPDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000040UL )
+#define XFPD_SLCR_SEC_DPDMA_RSTVAL   0x00000001UL
+
+#define XFPD_SLCR_SEC_DPDMA_TZ_SHIFT   0UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_WIDTH   1UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_DPDMA_TZ_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdSlcrSecGdma
+ */
+#define XFPD_SLCR_SEC_GDMA    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000050UL )
+#define XFPD_SLCR_SEC_GDMA_RSTVAL   0x000000ffUL
+
+#define XFPD_SLCR_SEC_GDMA_TZ_SHIFT   0UL
+#define XFPD_SLCR_SEC_GDMA_TZ_WIDTH   8UL
+#define XFPD_SLCR_SEC_GDMA_TZ_MASK    0x000000ffUL
+#define XFPD_SLCR_SEC_GDMA_TZ_DEFVAL  0xffUL
+
+/**
+ * Register: XfpdSlcrSecGic
+ */
+#define XFPD_SLCR_SEC_GIC    ( ( XFPD_SLCR_SECURE_BASEADDR ) + 0x00000060UL )
+#define XFPD_SLCR_SEC_GIC_RSTVAL   0x00000000UL
+
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_SHIFT   0UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_WIDTH   1UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_MASK    0x00000001UL
+#define XFPD_SLCR_SEC_GIC_CFG_DIS_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_SLCR_SECURE_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_cfg.h
new file mode 100644
index 000000000..75aef19f9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_XMPU_CFG_H__
+#define __XFPD_XMPU_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdXmpuCfg Base Address
+ */
+#define XFPD_XMPU_CFG_BASEADDR      0xFD5D0000UL
+
+/**
+ * Register: XfpdXmpuCfgCtrl
+ */
+#define XFPD_XMPU_CFG_CTRL    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000000UL )
+#define XFPD_XMPU_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdXmpuCfgErrSts1
+ */
+#define XFPD_XMPU_CFG_ERR_STS1    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000004UL )
+#define XFPD_XMPU_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XFPD_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgErrSts2
+ */
+#define XFPD_XMPU_CFG_ERR_STS2    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000008UL )
+#define XFPD_XMPU_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgPoison
+ */
+#define XFPD_XMPU_CFG_POISON    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000000CUL )
+#define XFPD_XMPU_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XFPD_XMPU_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XFPD_XMPU_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XFPD_XMPU_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_POISON_BASE_SHIFT   0UL
+#define XFPD_XMPU_CFG_POISON_BASE_WIDTH   20UL
+#define XFPD_XMPU_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XFPD_XMPU_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgIsr
+ */
+#define XFPD_XMPU_CFG_ISR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000010UL )
+#define XFPD_XMPU_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_ISR_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_ISR_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgImr
+ */
+#define XFPD_XMPU_CFG_IMR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000014UL )
+#define XFPD_XMPU_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_IMR_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_IMR_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdXmpuCfgIen
+ */
+#define XFPD_XMPU_CFG_IEN    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000018UL )
+#define XFPD_XMPU_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IEN_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_IEN_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgIds
+ */
+#define XFPD_XMPU_CFG_IDS    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000001CUL )
+#define XFPD_XMPU_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_IDS_INV_APB_SHIFT   0UL
+#define XFPD_XMPU_CFG_IDS_INV_APB_WIDTH   1UL
+#define XFPD_XMPU_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgLock
+ */
+#define XFPD_XMPU_CFG_LOCK    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000020UL )
+#define XFPD_XMPU_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00Strt
+ */
+#define XFPD_XMPU_CFG_R00_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000100UL )
+#define XFPD_XMPU_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00End
+ */
+#define XFPD_XMPU_CFG_R00_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000104UL )
+#define XFPD_XMPU_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R00_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00Mstr
+ */
+#define XFPD_XMPU_CFG_R00_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000108UL )
+#define XFPD_XMPU_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR00
+ */
+#define XFPD_XMPU_CFG_R00    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000010CUL )
+#define XFPD_XMPU_CFG_R00_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R00_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R00_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R00_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R00_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R00_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R00_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R00_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01Strt
+ */
+#define XFPD_XMPU_CFG_R01_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000110UL )
+#define XFPD_XMPU_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01End
+ */
+#define XFPD_XMPU_CFG_R01_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000114UL )
+#define XFPD_XMPU_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R01_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01Mstr
+ */
+#define XFPD_XMPU_CFG_R01_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000118UL )
+#define XFPD_XMPU_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR01
+ */
+#define XFPD_XMPU_CFG_R01    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000011CUL )
+#define XFPD_XMPU_CFG_R01_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R01_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R01_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R01_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R01_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R01_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R01_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R01_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02Strt
+ */
+#define XFPD_XMPU_CFG_R02_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000120UL )
+#define XFPD_XMPU_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02End
+ */
+#define XFPD_XMPU_CFG_R02_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000124UL )
+#define XFPD_XMPU_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R02_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02Mstr
+ */
+#define XFPD_XMPU_CFG_R02_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000128UL )
+#define XFPD_XMPU_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR02
+ */
+#define XFPD_XMPU_CFG_R02    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000012CUL )
+#define XFPD_XMPU_CFG_R02_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R02_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R02_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R02_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R02_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R02_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R02_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R02_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03Strt
+ */
+#define XFPD_XMPU_CFG_R03_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000130UL )
+#define XFPD_XMPU_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03End
+ */
+#define XFPD_XMPU_CFG_R03_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000134UL )
+#define XFPD_XMPU_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R03_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03Mstr
+ */
+#define XFPD_XMPU_CFG_R03_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000138UL )
+#define XFPD_XMPU_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR03
+ */
+#define XFPD_XMPU_CFG_R03    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000013CUL )
+#define XFPD_XMPU_CFG_R03_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R03_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R03_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R03_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R03_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R03_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R03_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R03_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04Strt
+ */
+#define XFPD_XMPU_CFG_R04_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000140UL )
+#define XFPD_XMPU_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04End
+ */
+#define XFPD_XMPU_CFG_R04_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000144UL )
+#define XFPD_XMPU_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R04_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04Mstr
+ */
+#define XFPD_XMPU_CFG_R04_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000148UL )
+#define XFPD_XMPU_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR04
+ */
+#define XFPD_XMPU_CFG_R04    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000014CUL )
+#define XFPD_XMPU_CFG_R04_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R04_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R04_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R04_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R04_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R04_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R04_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R04_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05Strt
+ */
+#define XFPD_XMPU_CFG_R05_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000150UL )
+#define XFPD_XMPU_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05End
+ */
+#define XFPD_XMPU_CFG_R05_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000154UL )
+#define XFPD_XMPU_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R05_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05Mstr
+ */
+#define XFPD_XMPU_CFG_R05_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000158UL )
+#define XFPD_XMPU_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR05
+ */
+#define XFPD_XMPU_CFG_R05    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000015CUL )
+#define XFPD_XMPU_CFG_R05_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R05_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R05_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R05_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R05_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R05_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R05_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R05_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06Strt
+ */
+#define XFPD_XMPU_CFG_R06_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000160UL )
+#define XFPD_XMPU_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06End
+ */
+#define XFPD_XMPU_CFG_R06_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000164UL )
+#define XFPD_XMPU_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R06_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06Mstr
+ */
+#define XFPD_XMPU_CFG_R06_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000168UL )
+#define XFPD_XMPU_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR06
+ */
+#define XFPD_XMPU_CFG_R06    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000016CUL )
+#define XFPD_XMPU_CFG_R06_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R06_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R06_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R06_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R06_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R06_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R06_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R06_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07Strt
+ */
+#define XFPD_XMPU_CFG_R07_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000170UL )
+#define XFPD_XMPU_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07End
+ */
+#define XFPD_XMPU_CFG_R07_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000174UL )
+#define XFPD_XMPU_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R07_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07Mstr
+ */
+#define XFPD_XMPU_CFG_R07_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000178UL )
+#define XFPD_XMPU_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR07
+ */
+#define XFPD_XMPU_CFG_R07    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000017CUL )
+#define XFPD_XMPU_CFG_R07_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R07_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R07_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R07_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R07_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R07_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R07_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R07_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08Strt
+ */
+#define XFPD_XMPU_CFG_R08_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000180UL )
+#define XFPD_XMPU_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08End
+ */
+#define XFPD_XMPU_CFG_R08_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000184UL )
+#define XFPD_XMPU_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R08_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08Mstr
+ */
+#define XFPD_XMPU_CFG_R08_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000188UL )
+#define XFPD_XMPU_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR08
+ */
+#define XFPD_XMPU_CFG_R08    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000018CUL )
+#define XFPD_XMPU_CFG_R08_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R08_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R08_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R08_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R08_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R08_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R08_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R08_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09Strt
+ */
+#define XFPD_XMPU_CFG_R09_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000190UL )
+#define XFPD_XMPU_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09End
+ */
+#define XFPD_XMPU_CFG_R09_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000194UL )
+#define XFPD_XMPU_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R09_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09Mstr
+ */
+#define XFPD_XMPU_CFG_R09_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x00000198UL )
+#define XFPD_XMPU_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR09
+ */
+#define XFPD_XMPU_CFG_R09    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x0000019CUL )
+#define XFPD_XMPU_CFG_R09_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R09_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R09_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R09_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R09_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R09_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R09_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R09_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10Strt
+ */
+#define XFPD_XMPU_CFG_R10_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A0UL )
+#define XFPD_XMPU_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10End
+ */
+#define XFPD_XMPU_CFG_R10_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A4UL )
+#define XFPD_XMPU_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R10_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10Mstr
+ */
+#define XFPD_XMPU_CFG_R10_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001A8UL )
+#define XFPD_XMPU_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR10
+ */
+#define XFPD_XMPU_CFG_R10    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ACUL )
+#define XFPD_XMPU_CFG_R10_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R10_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R10_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R10_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R10_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R10_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R10_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R10_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11Strt
+ */
+#define XFPD_XMPU_CFG_R11_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B0UL )
+#define XFPD_XMPU_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11End
+ */
+#define XFPD_XMPU_CFG_R11_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B4UL )
+#define XFPD_XMPU_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R11_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11Mstr
+ */
+#define XFPD_XMPU_CFG_R11_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001B8UL )
+#define XFPD_XMPU_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR11
+ */
+#define XFPD_XMPU_CFG_R11    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001BCUL )
+#define XFPD_XMPU_CFG_R11_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R11_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R11_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R11_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R11_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R11_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R11_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R11_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12Strt
+ */
+#define XFPD_XMPU_CFG_R12_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C0UL )
+#define XFPD_XMPU_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12End
+ */
+#define XFPD_XMPU_CFG_R12_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C4UL )
+#define XFPD_XMPU_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R12_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12Mstr
+ */
+#define XFPD_XMPU_CFG_R12_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001C8UL )
+#define XFPD_XMPU_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR12
+ */
+#define XFPD_XMPU_CFG_R12    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001CCUL )
+#define XFPD_XMPU_CFG_R12_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R12_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R12_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R12_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R12_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R12_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R12_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R12_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13Strt
+ */
+#define XFPD_XMPU_CFG_R13_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D0UL )
+#define XFPD_XMPU_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13End
+ */
+#define XFPD_XMPU_CFG_R13_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D4UL )
+#define XFPD_XMPU_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R13_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13Mstr
+ */
+#define XFPD_XMPU_CFG_R13_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001D8UL )
+#define XFPD_XMPU_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR13
+ */
+#define XFPD_XMPU_CFG_R13    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001DCUL )
+#define XFPD_XMPU_CFG_R13_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R13_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R13_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R13_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R13_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R13_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R13_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R13_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14Strt
+ */
+#define XFPD_XMPU_CFG_R14_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E0UL )
+#define XFPD_XMPU_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14End
+ */
+#define XFPD_XMPU_CFG_R14_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E4UL )
+#define XFPD_XMPU_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R14_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14Mstr
+ */
+#define XFPD_XMPU_CFG_R14_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001E8UL )
+#define XFPD_XMPU_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR14
+ */
+#define XFPD_XMPU_CFG_R14    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001ECUL )
+#define XFPD_XMPU_CFG_R14_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R14_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R14_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R14_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R14_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R14_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R14_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R14_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15Strt
+ */
+#define XFPD_XMPU_CFG_R15_STRT    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F0UL )
+#define XFPD_XMPU_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15End
+ */
+#define XFPD_XMPU_CFG_R15_END    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F4UL )
+#define XFPD_XMPU_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R15_END_ADDR_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_END_ADDR_WIDTH   28UL
+#define XFPD_XMPU_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XFPD_XMPU_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15Mstr
+ */
+#define XFPD_XMPU_CFG_R15_MSTR    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001F8UL )
+#define XFPD_XMPU_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XFPD_XMPU_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XFPD_XMPU_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XFPD_XMPU_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuCfgR15
+ */
+#define XFPD_XMPU_CFG_R15    ( ( XFPD_XMPU_CFG_BASEADDR ) + 0x000001FCUL )
+#define XFPD_XMPU_CFG_R15_RSTVAL   0x00000008UL
+
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XFPD_XMPU_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_REGNNS_SHIFT   3UL
+#define XFPD_XMPU_CFG_R15_REGNNS_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XFPD_XMPU_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XFPD_XMPU_CFG_R15_WRALWD_SHIFT   2UL
+#define XFPD_XMPU_CFG_R15_WRALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XFPD_XMPU_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_RDALWD_SHIFT   1UL
+#define XFPD_XMPU_CFG_R15_RDALWD_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XFPD_XMPU_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XFPD_XMPU_CFG_R15_EN_SHIFT   0UL
+#define XFPD_XMPU_CFG_R15_EN_WIDTH   1UL
+#define XFPD_XMPU_CFG_R15_EN_MASK    0x00000001UL
+#define XFPD_XMPU_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_XMPU_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_sink.h
new file mode 100644
index 000000000..39172f1f4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xfpd_xmpu_sink.h
@@ -0,0 +1,81 @@
+/* ### HEADER ### */
+
+#ifndef __XFPD_XMPU_SINK_H__
+#define __XFPD_XMPU_SINK_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XfpdXmpuSink Base Address
+ */
+#define XFPD_XMPU_SINK_BASEADDR      0xFD4F0000UL
+
+/**
+ * Register: XfpdXmpuSinkErrSts
+ */
+#define XFPD_XMPU_SINK_ERR_STS    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF00UL )
+#define XFPD_XMPU_SINK_ERR_STS_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_SHIFT   31UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_WIDTH   1UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
+#define XFPD_XMPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
+
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_SHIFT   0UL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_WIDTH   12UL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
+#define XFPD_XMPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkIsr
+ */
+#define XFPD_XMPU_SINK_ISR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF10UL )
+#define XFPD_XMPU_SINK_ISR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkImr
+ */
+#define XFPD_XMPU_SINK_IMR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF14UL )
+#define XFPD_XMPU_SINK_IMR_RSTVAL   0x00000001UL
+
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
+
+/**
+ * Register: XfpdXmpuSinkIer
+ */
+#define XFPD_XMPU_SINK_IER    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF18UL )
+#define XFPD_XMPU_SINK_IER_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_IERADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XfpdXmpuSinkIdr
+ */
+#define XFPD_XMPU_SINK_IDR    ( ( XFPD_XMPU_SINK_BASEADDR ) + 0x0000FF1CUL )
+#define XFPD_XMPU_SINK_IDR_RSTVAL   0x00000000UL
+
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_SHIFT   0UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_WIDTH   1UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
+#define XFPD_XMPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XFPD_XMPU_SINK_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_secure_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_secure_slcr.h
new file mode 100644
index 000000000..cb4ad4903
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_secure_slcr.h
@@ -0,0 +1,174 @@
+/* ### HEADER ### */
+
+#ifndef __XIOU_SECURE_SLCR_H__
+#define __XIOU_SECURE_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XiouSecureSlcr Base Address
+ */
+#define XIOU_SECURE_SLCR_BASEADDR      0xFF240000UL
+
+/**
+ * Register: XiouSecSlcrAxiWprtcn
+ */
+#define XIOU_SEC_SLCR_AXI_WPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000000UL )
+#define XIOU_SEC_SLCR_AXI_WPRTCN_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_SHIFT   25UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_MASK    0x0e000000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XQSPIPSAXI_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_SHIFT   22UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_MASK    0x01c00000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XNANDPS8_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   19UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00380000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_SHIFT   16UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_MASK    0x00070000UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XSDPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   9UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000e00UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   6UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x000001c0UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000038UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_SHIFT   0UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_MASK    0x00000007UL
+#define XIOU_SEC_SLCR_AXI_WPRTCN_XEMACPS_AWPROT_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrAxiRprtcn
+ */
+#define XIOU_SEC_SLCR_AXI_RPRTCN    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000004UL )
+#define XIOU_SEC_SLCR_AXI_RPRTCN_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_SHIFT   22UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_MASK    0x01c00000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XNANDPS8_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   19UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00380000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_SHIFT   16UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_MASK    0x00070000UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XSDPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   9UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000e00UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   6UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x000001c0UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000038UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_SHIFT   0UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_WIDTH   3UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_MASK    0x00000007UL
+#define XIOU_SEC_SLCR_AXI_RPRTCN_XEMACPS_ARPROT_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrCtrl
+ */
+#define XIOU_SEC_SLCR_CTRL    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000040UL )
+#define XIOU_SEC_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrIsr
+ */
+#define XIOU_SEC_SLCR_ISR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000044UL )
+#define XIOU_SEC_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrImr
+ */
+#define XIOU_SEC_SLCR_IMR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000048UL )
+#define XIOU_SEC_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSecSlcrIer
+ */
+#define XIOU_SEC_SLCR_IER    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x0000004CUL )
+#define XIOU_SEC_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrIdr
+ */
+#define XIOU_SEC_SLCR_IDR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000050UL )
+#define XIOU_SEC_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSecSlcrItr
+ */
+#define XIOU_SEC_SLCR_ITR    ( ( XIOU_SECURE_SLCR_BASEADDR ) + 0x00000054UL )
+#define XIOU_SEC_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SEC_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XIOU_SECURE_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h
new file mode 100644
index 000000000..d81d178d3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xiou_slcr.h
@@ -0,0 +1,4029 @@
+/* ### HEADER ### */
+
+#ifndef __XIOU_SLCR_H__
+#define __XIOU_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XiouSlcr Base Address
+ */
+#define XIOU_SLCR_BASEADDR      0xFF180000UL
+
+/**
+ * Register: XiouSlcrMioPin0
+ */
+#define XIOU_SLCR_MIO_PIN_0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000000UL )
+#define XIOU_SLCR_MIO_PIN_0_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin1
+ */
+#define XIOU_SLCR_MIO_PIN_1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000004UL )
+#define XIOU_SLCR_MIO_PIN_1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin2
+ */
+#define XIOU_SLCR_MIO_PIN_2    ( ( XIOU_SLCR_BASEADDR ) + 0x00000008UL )
+#define XIOU_SLCR_MIO_PIN_2_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin3
+ */
+#define XIOU_SLCR_MIO_PIN_3    ( ( XIOU_SLCR_BASEADDR ) + 0x0000000CUL )
+#define XIOU_SLCR_MIO_PIN_3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin4
+ */
+#define XIOU_SLCR_MIO_PIN_4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000010UL )
+#define XIOU_SLCR_MIO_PIN_4_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin5
+ */
+#define XIOU_SLCR_MIO_PIN_5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000014UL )
+#define XIOU_SLCR_MIO_PIN_5_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin6
+ */
+#define XIOU_SLCR_MIO_PIN_6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000018UL )
+#define XIOU_SLCR_MIO_PIN_6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin7
+ */
+#define XIOU_SLCR_MIO_PIN_7    ( ( XIOU_SLCR_BASEADDR ) + 0x0000001CUL )
+#define XIOU_SLCR_MIO_PIN_7_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin8
+ */
+#define XIOU_SLCR_MIO_PIN_8    ( ( XIOU_SLCR_BASEADDR ) + 0x00000020UL )
+#define XIOU_SLCR_MIO_PIN_8_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin9
+ */
+#define XIOU_SLCR_MIO_PIN_9    ( ( XIOU_SLCR_BASEADDR ) + 0x00000024UL )
+#define XIOU_SLCR_MIO_PIN_9_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin10
+ */
+#define XIOU_SLCR_MIO_PIN_10    ( ( XIOU_SLCR_BASEADDR ) + 0x00000028UL )
+#define XIOU_SLCR_MIO_PIN_10_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin11
+ */
+#define XIOU_SLCR_MIO_PIN_11    ( ( XIOU_SLCR_BASEADDR ) + 0x0000002CUL )
+#define XIOU_SLCR_MIO_PIN_11_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin12
+ */
+#define XIOU_SLCR_MIO_PIN_12    ( ( XIOU_SLCR_BASEADDR ) + 0x00000030UL )
+#define XIOU_SLCR_MIO_PIN_12_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin13
+ */
+#define XIOU_SLCR_MIO_PIN_13    ( ( XIOU_SLCR_BASEADDR ) + 0x00000034UL )
+#define XIOU_SLCR_MIO_PIN_13_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin14
+ */
+#define XIOU_SLCR_MIO_PIN_14    ( ( XIOU_SLCR_BASEADDR ) + 0x00000038UL )
+#define XIOU_SLCR_MIO_PIN_14_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin15
+ */
+#define XIOU_SLCR_MIO_PIN_15    ( ( XIOU_SLCR_BASEADDR ) + 0x0000003CUL )
+#define XIOU_SLCR_MIO_PIN_15_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin16
+ */
+#define XIOU_SLCR_MIO_PIN_16    ( ( XIOU_SLCR_BASEADDR ) + 0x00000040UL )
+#define XIOU_SLCR_MIO_PIN_16_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin17
+ */
+#define XIOU_SLCR_MIO_PIN_17    ( ( XIOU_SLCR_BASEADDR ) + 0x00000044UL )
+#define XIOU_SLCR_MIO_PIN_17_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin18
+ */
+#define XIOU_SLCR_MIO_PIN_18    ( ( XIOU_SLCR_BASEADDR ) + 0x00000048UL )
+#define XIOU_SLCR_MIO_PIN_18_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin19
+ */
+#define XIOU_SLCR_MIO_PIN_19    ( ( XIOU_SLCR_BASEADDR ) + 0x0000004CUL )
+#define XIOU_SLCR_MIO_PIN_19_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin20
+ */
+#define XIOU_SLCR_MIO_PIN_20    ( ( XIOU_SLCR_BASEADDR ) + 0x00000050UL )
+#define XIOU_SLCR_MIO_PIN_20_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin21
+ */
+#define XIOU_SLCR_MIO_PIN_21    ( ( XIOU_SLCR_BASEADDR ) + 0x00000054UL )
+#define XIOU_SLCR_MIO_PIN_21_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin22
+ */
+#define XIOU_SLCR_MIO_PIN_22    ( ( XIOU_SLCR_BASEADDR ) + 0x00000058UL )
+#define XIOU_SLCR_MIO_PIN_22_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin23
+ */
+#define XIOU_SLCR_MIO_PIN_23    ( ( XIOU_SLCR_BASEADDR ) + 0x0000005CUL )
+#define XIOU_SLCR_MIO_PIN_23_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin24
+ */
+#define XIOU_SLCR_MIO_PIN_24    ( ( XIOU_SLCR_BASEADDR ) + 0x00000060UL )
+#define XIOU_SLCR_MIO_PIN_24_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin25
+ */
+#define XIOU_SLCR_MIO_PIN_25    ( ( XIOU_SLCR_BASEADDR ) + 0x00000064UL )
+#define XIOU_SLCR_MIO_PIN_25_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin26
+ */
+#define XIOU_SLCR_MIO_PIN_26    ( ( XIOU_SLCR_BASEADDR ) + 0x00000068UL )
+#define XIOU_SLCR_MIO_PIN_26_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin27
+ */
+#define XIOU_SLCR_MIO_PIN_27    ( ( XIOU_SLCR_BASEADDR ) + 0x0000006CUL )
+#define XIOU_SLCR_MIO_PIN_27_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin28
+ */
+#define XIOU_SLCR_MIO_PIN_28    ( ( XIOU_SLCR_BASEADDR ) + 0x00000070UL )
+#define XIOU_SLCR_MIO_PIN_28_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin29
+ */
+#define XIOU_SLCR_MIO_PIN_29    ( ( XIOU_SLCR_BASEADDR ) + 0x00000074UL )
+#define XIOU_SLCR_MIO_PIN_29_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin30
+ */
+#define XIOU_SLCR_MIO_PIN_30    ( ( XIOU_SLCR_BASEADDR ) + 0x00000078UL )
+#define XIOU_SLCR_MIO_PIN_30_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin31
+ */
+#define XIOU_SLCR_MIO_PIN_31    ( ( XIOU_SLCR_BASEADDR ) + 0x0000007CUL )
+#define XIOU_SLCR_MIO_PIN_31_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin32
+ */
+#define XIOU_SLCR_MIO_PIN_32    ( ( XIOU_SLCR_BASEADDR ) + 0x00000080UL )
+#define XIOU_SLCR_MIO_PIN_32_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin33
+ */
+#define XIOU_SLCR_MIO_PIN_33    ( ( XIOU_SLCR_BASEADDR ) + 0x00000084UL )
+#define XIOU_SLCR_MIO_PIN_33_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin34
+ */
+#define XIOU_SLCR_MIO_PIN_34    ( ( XIOU_SLCR_BASEADDR ) + 0x00000088UL )
+#define XIOU_SLCR_MIO_PIN_34_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin35
+ */
+#define XIOU_SLCR_MIO_PIN_35    ( ( XIOU_SLCR_BASEADDR ) + 0x0000008CUL )
+#define XIOU_SLCR_MIO_PIN_35_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin36
+ */
+#define XIOU_SLCR_MIO_PIN_36    ( ( XIOU_SLCR_BASEADDR ) + 0x00000090UL )
+#define XIOU_SLCR_MIO_PIN_36_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin37
+ */
+#define XIOU_SLCR_MIO_PIN_37    ( ( XIOU_SLCR_BASEADDR ) + 0x00000094UL )
+#define XIOU_SLCR_MIO_PIN_37_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin38
+ */
+#define XIOU_SLCR_MIO_PIN_38    ( ( XIOU_SLCR_BASEADDR ) + 0x00000098UL )
+#define XIOU_SLCR_MIO_PIN_38_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin39
+ */
+#define XIOU_SLCR_MIO_PIN_39    ( ( XIOU_SLCR_BASEADDR ) + 0x0000009CUL )
+#define XIOU_SLCR_MIO_PIN_39_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin40
+ */
+#define XIOU_SLCR_MIO_PIN_40    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A0UL )
+#define XIOU_SLCR_MIO_PIN_40_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin41
+ */
+#define XIOU_SLCR_MIO_PIN_41    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A4UL )
+#define XIOU_SLCR_MIO_PIN_41_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin42
+ */
+#define XIOU_SLCR_MIO_PIN_42    ( ( XIOU_SLCR_BASEADDR ) + 0x000000A8UL )
+#define XIOU_SLCR_MIO_PIN_42_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin43
+ */
+#define XIOU_SLCR_MIO_PIN_43    ( ( XIOU_SLCR_BASEADDR ) + 0x000000ACUL )
+#define XIOU_SLCR_MIO_PIN_43_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin44
+ */
+#define XIOU_SLCR_MIO_PIN_44    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B0UL )
+#define XIOU_SLCR_MIO_PIN_44_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin45
+ */
+#define XIOU_SLCR_MIO_PIN_45    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B4UL )
+#define XIOU_SLCR_MIO_PIN_45_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin46
+ */
+#define XIOU_SLCR_MIO_PIN_46    ( ( XIOU_SLCR_BASEADDR ) + 0x000000B8UL )
+#define XIOU_SLCR_MIO_PIN_46_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin47
+ */
+#define XIOU_SLCR_MIO_PIN_47    ( ( XIOU_SLCR_BASEADDR ) + 0x000000BCUL )
+#define XIOU_SLCR_MIO_PIN_47_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin48
+ */
+#define XIOU_SLCR_MIO_PIN_48    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C0UL )
+#define XIOU_SLCR_MIO_PIN_48_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin49
+ */
+#define XIOU_SLCR_MIO_PIN_49    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C4UL )
+#define XIOU_SLCR_MIO_PIN_49_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin50
+ */
+#define XIOU_SLCR_MIO_PIN_50    ( ( XIOU_SLCR_BASEADDR ) + 0x000000C8UL )
+#define XIOU_SLCR_MIO_PIN_50_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin51
+ */
+#define XIOU_SLCR_MIO_PIN_51    ( ( XIOU_SLCR_BASEADDR ) + 0x000000CCUL )
+#define XIOU_SLCR_MIO_PIN_51_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin52
+ */
+#define XIOU_SLCR_MIO_PIN_52    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D0UL )
+#define XIOU_SLCR_MIO_PIN_52_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin53
+ */
+#define XIOU_SLCR_MIO_PIN_53    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D4UL )
+#define XIOU_SLCR_MIO_PIN_53_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin54
+ */
+#define XIOU_SLCR_MIO_PIN_54    ( ( XIOU_SLCR_BASEADDR ) + 0x000000D8UL )
+#define XIOU_SLCR_MIO_PIN_54_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin55
+ */
+#define XIOU_SLCR_MIO_PIN_55    ( ( XIOU_SLCR_BASEADDR ) + 0x000000DCUL )
+#define XIOU_SLCR_MIO_PIN_55_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin56
+ */
+#define XIOU_SLCR_MIO_PIN_56    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E0UL )
+#define XIOU_SLCR_MIO_PIN_56_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin57
+ */
+#define XIOU_SLCR_MIO_PIN_57    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E4UL )
+#define XIOU_SLCR_MIO_PIN_57_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin58
+ */
+#define XIOU_SLCR_MIO_PIN_58    ( ( XIOU_SLCR_BASEADDR ) + 0x000000E8UL )
+#define XIOU_SLCR_MIO_PIN_58_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin59
+ */
+#define XIOU_SLCR_MIO_PIN_59    ( ( XIOU_SLCR_BASEADDR ) + 0x000000ECUL )
+#define XIOU_SLCR_MIO_PIN_59_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin60
+ */
+#define XIOU_SLCR_MIO_PIN_60    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F0UL )
+#define XIOU_SLCR_MIO_PIN_60_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin61
+ */
+#define XIOU_SLCR_MIO_PIN_61    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F4UL )
+#define XIOU_SLCR_MIO_PIN_61_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin62
+ */
+#define XIOU_SLCR_MIO_PIN_62    ( ( XIOU_SLCR_BASEADDR ) + 0x000000F8UL )
+#define XIOU_SLCR_MIO_PIN_62_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin63
+ */
+#define XIOU_SLCR_MIO_PIN_63    ( ( XIOU_SLCR_BASEADDR ) + 0x000000FCUL )
+#define XIOU_SLCR_MIO_PIN_63_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin64
+ */
+#define XIOU_SLCR_MIO_PIN_64    ( ( XIOU_SLCR_BASEADDR ) + 0x00000100UL )
+#define XIOU_SLCR_MIO_PIN_64_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin65
+ */
+#define XIOU_SLCR_MIO_PIN_65    ( ( XIOU_SLCR_BASEADDR ) + 0x00000104UL )
+#define XIOU_SLCR_MIO_PIN_65_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin66
+ */
+#define XIOU_SLCR_MIO_PIN_66    ( ( XIOU_SLCR_BASEADDR ) + 0x00000108UL )
+#define XIOU_SLCR_MIO_PIN_66_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin67
+ */
+#define XIOU_SLCR_MIO_PIN_67    ( ( XIOU_SLCR_BASEADDR ) + 0x0000010CUL )
+#define XIOU_SLCR_MIO_PIN_67_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin68
+ */
+#define XIOU_SLCR_MIO_PIN_68    ( ( XIOU_SLCR_BASEADDR ) + 0x00000110UL )
+#define XIOU_SLCR_MIO_PIN_68_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin69
+ */
+#define XIOU_SLCR_MIO_PIN_69    ( ( XIOU_SLCR_BASEADDR ) + 0x00000114UL )
+#define XIOU_SLCR_MIO_PIN_69_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin70
+ */
+#define XIOU_SLCR_MIO_PIN_70    ( ( XIOU_SLCR_BASEADDR ) + 0x00000118UL )
+#define XIOU_SLCR_MIO_PIN_70_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin71
+ */
+#define XIOU_SLCR_MIO_PIN_71    ( ( XIOU_SLCR_BASEADDR ) + 0x0000011CUL )
+#define XIOU_SLCR_MIO_PIN_71_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin72
+ */
+#define XIOU_SLCR_MIO_PIN_72    ( ( XIOU_SLCR_BASEADDR ) + 0x00000120UL )
+#define XIOU_SLCR_MIO_PIN_72_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin73
+ */
+#define XIOU_SLCR_MIO_PIN_73    ( ( XIOU_SLCR_BASEADDR ) + 0x00000124UL )
+#define XIOU_SLCR_MIO_PIN_73_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin74
+ */
+#define XIOU_SLCR_MIO_PIN_74    ( ( XIOU_SLCR_BASEADDR ) + 0x00000128UL )
+#define XIOU_SLCR_MIO_PIN_74_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin75
+ */
+#define XIOU_SLCR_MIO_PIN_75    ( ( XIOU_SLCR_BASEADDR ) + 0x0000012CUL )
+#define XIOU_SLCR_MIO_PIN_75_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin76
+ */
+#define XIOU_SLCR_MIO_PIN_76    ( ( XIOU_SLCR_BASEADDR ) + 0x00000130UL )
+#define XIOU_SLCR_MIO_PIN_76_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioPin77
+ */
+#define XIOU_SLCR_MIO_PIN_77    ( ( XIOU_SLCR_BASEADDR ) + 0x00000134UL )
+#define XIOU_SLCR_MIO_PIN_77_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT   5UL
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_WIDTH   3UL
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_MASK    0x000000e0UL
+#define XIOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT   3UL
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_WIDTH   2UL
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_MASK    0x00000018UL
+#define XIOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT   2UL
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT   1UL
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_WIDTH   1UL
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Ctrl0
+ */
+#define XIOU_SLCR_BANK0_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000138UL )
+#define XIOU_SLCR_BANK0_CTRL0_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank0Ctrl1
+ */
+#define XIOU_SLCR_BANK0_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000013CUL )
+#define XIOU_SLCR_BANK0_CTRL1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL1_DRIVE1_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Ctrl3
+ */
+#define XIOU_SLCR_BANK0_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000140UL )
+#define XIOU_SLCR_BANK0_CTRL3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Ctrl4
+ */
+#define XIOU_SLCR_BANK0_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000144UL )
+#define XIOU_SLCR_BANK0_CTRL4_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank0Ctrl5
+ */
+#define XIOU_SLCR_BANK0_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000148UL )
+#define XIOU_SLCR_BANK0_CTRL5_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank0Ctrl6
+ */
+#define XIOU_SLCR_BANK0_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x0000014CUL )
+#define XIOU_SLCR_BANK0_CTRL6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank0Sts
+ */
+#define XIOU_SLCR_BANK0_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000150UL )
+#define XIOU_SLCR_BANK0_STS_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_SHIFT   0UL
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_WIDTH   1UL
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_MASK    0x00000001UL
+#define XIOU_SLCR_BANK0_STS_VOLTAGE_MODE_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Ctrl0
+ */
+#define XIOU_SLCR_BANK1_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000154UL )
+#define XIOU_SLCR_BANK1_CTRL0_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank1Ctrl1
+ */
+#define XIOU_SLCR_BANK1_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000158UL )
+#define XIOU_SLCR_BANK1_CTRL1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL1_DRIVE1_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Ctrl3
+ */
+#define XIOU_SLCR_BANK1_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x0000015CUL )
+#define XIOU_SLCR_BANK1_CTRL3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Ctrl4
+ */
+#define XIOU_SLCR_BANK1_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x00000160UL )
+#define XIOU_SLCR_BANK1_CTRL4_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank1Ctrl5
+ */
+#define XIOU_SLCR_BANK1_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000164UL )
+#define XIOU_SLCR_BANK1_CTRL5_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank1Ctrl6
+ */
+#define XIOU_SLCR_BANK1_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000168UL )
+#define XIOU_SLCR_BANK1_CTRL6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank1Sts
+ */
+#define XIOU_SLCR_BANK1_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x0000016CUL )
+#define XIOU_SLCR_BANK1_STS_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_SHIFT   0UL
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_WIDTH   1UL
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_MASK    0x00000001UL
+#define XIOU_SLCR_BANK1_STS_VOLTAGE_MODE_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Ctrl0
+ */
+#define XIOU_SLCR_BANK2_CTRL0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000170UL )
+#define XIOU_SLCR_BANK2_CTRL0_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL0_DRIVE0_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank2Ctrl1
+ */
+#define XIOU_SLCR_BANK2_CTRL1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000174UL )
+#define XIOU_SLCR_BANK2_CTRL1_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL1_DRIVE1_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Ctrl3
+ */
+#define XIOU_SLCR_BANK2_CTRL3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000178UL )
+#define XIOU_SLCR_BANK2_CTRL3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Ctrl4
+ */
+#define XIOU_SLCR_BANK2_CTRL4    ( ( XIOU_SLCR_BASEADDR ) + 0x0000017CUL )
+#define XIOU_SLCR_BANK2_CTRL4_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL4_PULLHILO_N_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank2Ctrl5
+ */
+#define XIOU_SLCR_BANK2_CTRL5    ( ( XIOU_SLCR_BASEADDR ) + 0x00000180UL )
+#define XIOU_SLCR_BANK2_CTRL5_RSTVAL   0x03ffffffUL
+
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL5_PULL_EN_DEFVAL  0x3ffffffUL
+
+/**
+ * Register: XiouSlcrBank2Ctrl6
+ */
+#define XIOU_SLCR_BANK2_CTRL6    ( ( XIOU_SLCR_BASEADDR ) + 0x00000184UL )
+#define XIOU_SLCR_BANK2_CTRL6_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_SHIFT   0UL
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_WIDTH   26UL
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_MASK    0x03ffffffUL
+#define XIOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrBank2Sts
+ */
+#define XIOU_SLCR_BANK2_STS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000188UL )
+#define XIOU_SLCR_BANK2_STS_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_SHIFT   0UL
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_WIDTH   1UL
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_MASK    0x00000001UL
+#define XIOU_SLCR_BANK2_STS_VOLTAGE_MODE_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioLpbck
+ */
+#define XIOU_SLCR_MIO_LPBCK    ( ( XIOU_SLCR_BASEADDR ) + 0x00000200UL )
+#define XIOU_SLCR_MIO_LPBCK_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_SHIFT   3UL
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_LPBCK_XI2CPS_LOOP_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_SHIFT   2UL
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_LPBCK_CAN0_LOOP_CAN1_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_SHIFT   1UL
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_LPBCK_UA0_LOOP_UA1_DEFVAL  0x0UL
+
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_SHIFT   0UL
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_WIDTH   1UL
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_LPBCK_XSPIPS_LOOP_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrMioMstTri0
+ */
+#define XIOU_SLCR_MIO_MST_TRI0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000204UL )
+#define XIOU_SLCR_MIO_MST_TRI0_RSTVAL   0xffffffffUL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT   31UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK    0x80000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT   30UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK    0x40000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT   29UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK    0x20000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT   28UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK    0x10000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT   27UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK    0x08000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT   26UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK    0x04000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT   25UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK    0x02000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT   24UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK    0x01000000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT   23UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK    0x00800000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT   22UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK    0x00400000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT   21UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK    0x00200000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT   20UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK    0x00100000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT   19UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK    0x00080000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT   18UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK    0x00040000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT   17UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK    0x00020000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT   16UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK    0x00010000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT   15UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK    0x00008000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT   14UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK    0x00004000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT   13UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK    0x00002000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT   12UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK    0x00001000UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT   11UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK    0x00000800UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT   10UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK    0x00000400UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT   9UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK    0x00000200UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT   8UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK    0x00000100UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT   7UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK    0x00000080UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT   6UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK    0x00000040UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT   5UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK    0x00000020UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT   4UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK    0x00000010UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT   3UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT   2UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT   0UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrMioMstTri1
+ */
+#define XIOU_SLCR_MIO_MST_TRI1    ( ( XIOU_SLCR_BASEADDR ) + 0x00000208UL )
+#define XIOU_SLCR_MIO_MST_TRI1_RSTVAL   0xffffffffUL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT   31UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK    0x80000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT   30UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK    0x40000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT   29UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK    0x20000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT   28UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK    0x10000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT   27UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK    0x08000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT   26UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK    0x04000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT   25UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK    0x02000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT   24UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK    0x01000000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT   23UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK    0x00800000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT   22UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK    0x00400000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT   21UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK    0x00200000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT   20UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK    0x00100000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT   19UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK    0x00080000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT   18UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK    0x00040000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT   17UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK    0x00020000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT   16UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK    0x00010000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT   15UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK    0x00008000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT   14UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK    0x00004000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT   13UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK    0x00002000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT   12UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK    0x00001000UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT   11UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK    0x00000800UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT   10UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK    0x00000400UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT   9UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK    0x00000200UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT   8UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK    0x00000100UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT   7UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK    0x00000080UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT   6UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK    0x00000040UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT   5UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK    0x00000020UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT   4UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK    0x00000010UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT   3UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT   2UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT   0UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrMioMstTri2
+ */
+#define XIOU_SLCR_MIO_MST_TRI2    ( ( XIOU_SLCR_BASEADDR ) + 0x0000020CUL )
+#define XIOU_SLCR_MIO_MST_TRI2_RSTVAL   0x00003fffUL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT   13UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK    0x00002000UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT   12UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK    0x00001000UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT   11UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK    0x00000800UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT   10UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK    0x00000400UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT   9UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK    0x00000200UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT   8UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK    0x00000100UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT   7UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK    0x00000080UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT   6UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK    0x00000040UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT   5UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK    0x00000020UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT   4UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK    0x00000010UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT   3UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK    0x00000008UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT   2UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK    0x00000004UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK    0x00000002UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL  0x1UL
+
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT   0UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_WIDTH   1UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK    0x00000001UL
+#define XIOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrWdtClkSel
+ */
+#define XIOU_SLCR_WDT_CLK_SEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000300UL )
+#define XIOU_SLCR_WDT_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_WDT_CLK_SEL_SHIFT   0UL
+#define XIOU_SLCR_WDT_CLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_WDT_CLK_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_WDT_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrCanMioCtrl
+ */
+#define XIOU_SLCR_CAN_MIO_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000304UL )
+#define XIOU_SLCR_CAN_MIO_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_SHIFT   23UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_MASK    0x00800000UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_RXIN_REG_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_SHIFT   22UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_MASK    0x00400000UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_REF_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_SHIFT   15UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_WIDTH   7UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_MASK    0x003f8000UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN1_MUX_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_SHIFT   8UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_MASK    0x00000100UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_RXIN_REG_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_SHIFT   7UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_WIDTH   1UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_MASK    0x00000080UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_REF_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_SHIFT   0UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_WIDTH   7UL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_MASK    0x0000007fUL
+#define XIOU_SLCR_CAN_MIO_CTRL_CAN0_MUX_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrGemClkCtrl
+ */
+#define XIOU_SLCR_GEM_CLK_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000308UL )
+#define XIOU_SLCR_GEM_CLK_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_SHIFT   22UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_MASK    0x00400000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_LB_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_SHIFT   20UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_WIDTH   2UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_MASK    0x00300000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_TSU_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   18UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00040000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   17UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00020000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   16UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00010000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   15UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00008000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   13UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00002000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   12UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00001000UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   11UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000800UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   10UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000400UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   8UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000100UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   7UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000080UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   6UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000040UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   5UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000020UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_SHIFT   3UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_MASK    0x00000008UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_FIFO_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_SHIFT   2UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_MASK    0x00000004UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_SGMII_MODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_SHIFT   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_MASK    0x00000002UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_REF_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_SHIFT   0UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_GEM_CLK_CTRL_XEMACPS_RX_SRC_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdioClkCtrl
+ */
+#define XIOU_SLCR_SDIO_CLK_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x0000030CUL )
+#define XIOU_SLCR_SDIO_CLK_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_SHIFT   18UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_MASK    0x00040000UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_FBCLK_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT   17UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_WIDTH   1UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK    0x00020000UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_SHIFT   2UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_MASK    0x00000004UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_FBCLK_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_SHIFT   0UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_WIDTH   2UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_MASK    0x00000003UL
+#define XIOU_SLCR_SDIO_CLK_CTRL_SDIO0_RX_SRC_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrCtrlRegSd
+ */
+#define XIOU_SLCR_CTRL_REG_SD    ( ( XIOU_SLCR_BASEADDR ) + 0x00000310UL )
+#define XIOU_SLCR_CTRL_REG_SD_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT   15UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH   1UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK    0x00008000UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_SHIFT   0UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_WIDTH   1UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_CTRL_REG_SD_XSDPS_EMMC_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdItapdly
+ */
+#define XIOU_SLCR_SD_ITAPDLY    ( ( XIOU_SLCR_BASEADDR ) + 0x00000314UL )
+#define XIOU_SLCR_SD_ITAPDLY_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT   25UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x02000000UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   24UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x01000000UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   16UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_SHIFT   9UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_WIDTH   1UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_MASK    0x00000200UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPCHGWIN_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_SHIFT   8UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_MASK    0x00000100UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_SHIFT   0UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_WIDTH   8UL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_MASK    0x000000ffUL
+#define XIOU_SLCR_SD_ITAPDLY_XSDPS_ITAPDLYSEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdOtapdlysel
+ */
+#define XIOU_SLCR_SD_OTAPDLYSEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000318UL )
+#define XIOU_SLCR_SD_OTAPDLYSEL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT   22UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00400000UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH   6UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK    0x003f0000UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_SHIFT   6UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_WIDTH   1UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_MASK    0x00000040UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_OTAPDLYENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_WIDTH   6UL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_MASK    0x0000003fUL
+#define XIOU_SLCR_SD_OTAPDLYSEL_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCfgReg1
+ */
+#define XIOU_SLCR_SD_CFG_REG1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000031CUL )
+#define XIOU_SLCR_SD_CFG_REG1_RSTVAL   0x32403240UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT   23UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK    0x7f800000UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   17UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x007e0000UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   16UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00010000UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_SHIFT   7UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_WIDTH   8UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_MASK    0x00007f80UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_BASECLK_DEFVAL  0x64UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_SHIFT   1UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_WIDTH   6UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_MASK    0x0000007eUL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_TUNIGCOUNT_DEFVAL  0x20UL
+
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_SHIFT   0UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_MASK    0x00000001UL
+#define XIOU_SLCR_SD_CFG_REG1_XSDPS_ASYNCWKPENA_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCfgReg2
+ */
+#define XIOU_SLCR_SD_CFG_REG2    ( ( XIOU_SLCR_BASEADDR ) + 0x00000320UL )
+#define XIOU_SLCR_SD_CFG_REG2_RSTVAL   0x0ffc0ffcUL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   28UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x30000000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT   27UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK    0x08000000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT   26UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK    0x04000000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT   25UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK    0x02000000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT   24UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK    0x01000000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT   23UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK    0x00800000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT   22UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK    0x00400000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT   21UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK    0x00200000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   20UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00100000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT   19UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK    0x00080000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT   18UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK    0x00040000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT   16UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK    0x00030000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_SHIFT   12UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_WIDTH   2UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_MASK    0x00003000UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SLOTTYPE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_SHIFT   11UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_MASK    0x00000800UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ASYCINTR_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_SHIFT   10UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_MASK    0x00000400UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_64BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_SHIFT   9UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_MASK    0x00000200UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_1P8V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_SHIFT   8UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_MASK    0x00000100UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P0V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_SHIFT   7UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_MASK    0x00000080UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_3P3V_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_SHIFT   6UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_MASK    0x00000040UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SUSPRES_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_SHIFT   5UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_MASK    0x00000020UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_SDMA_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_SHIFT   4UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_MASK    0x00000010UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_HIGHSPEED_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_SHIFT   3UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_MASK    0x00000008UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_ADMA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_SHIFT   2UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_MASK    0x00000004UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_8BIT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_SHIFT   0UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_WIDTH   2UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_MASK    0x00000003UL
+#define XIOU_SLCR_SD_CFG_REG2_XSDPS_MAXBLK_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCfgReg3
+ */
+#define XIOU_SLCR_SD_CFG_REG3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000324UL )
+#define XIOU_SLCR_SD_CFG_REG3_RSTVAL   0x06070607UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   26UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x04000000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT   22UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK    0x03c00000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT   21UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK    0x00200000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT   20UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK    0x00100000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT   19UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK    0x00080000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT   18UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK    0x00040000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT   17UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK    0x00020000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT   16UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK    0x00010000UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_SHIFT   10UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_MASK    0x00000400UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_TUNINGSDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_SHIFT   6UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_WIDTH   4UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_MASK    0x000003c0UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_RETUNETMR_DEFVAL  0x8UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_SHIFT   5UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_MASK    0x00000020UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_SHIFT   4UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_MASK    0x00000010UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_CDRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_SHIFT   3UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_MASK    0x00000008UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_ADRIVER_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_SHIFT   2UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_MASK    0x00000004UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_DDR50_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_SHIFT   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_MASK    0x00000002UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR104_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_SHIFT   0UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_WIDTH   1UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_MASK    0x00000001UL
+#define XIOU_SLCR_SD_CFG_REG3_XSDPS_SDR50_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrSdInitpreset
+ */
+#define XIOU_SLCR_SD_INITPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000328UL )
+#define XIOU_SLCR_SD_INITPRESET_RSTVAL   0x01000100UL
+
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL  0x100UL
+
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_INITPRESET_XSDPS_DEFVAL  0x100UL
+
+/**
+ * Register: XiouSlcrSdDsppreset
+ */
+#define XIOU_SLCR_SD_DSPPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x0000032CUL )
+#define XIOU_SLCR_SD_DSPPRESET_RSTVAL   0x00040004UL
+
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL  0x4UL
+
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_DSPPRESET_XSDPS_DEFVAL  0x4UL
+
+/**
+ * Register: XiouSlcrSdHspdpreset
+ */
+#define XIOU_SLCR_SD_HSPDPRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000330UL )
+#define XIOU_SLCR_SD_HSPDPRESET_RSTVAL   0x00020002UL
+
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL  0x2UL
+
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_HSPDPRESET_XSDPS_DEFVAL  0x2UL
+
+/**
+ * Register: XiouSlcrSdSdr12preset
+ */
+#define XIOU_SLCR_SD_SDR12PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000334UL )
+#define XIOU_SLCR_SD_SDR12PRESET_RSTVAL   0x00040004UL
+
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL  0x4UL
+
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_SDR12PRESET_XSDPS_DEFVAL  0x4UL
+
+/**
+ * Register: XiouSlcrSdSdr25preset
+ */
+#define XIOU_SLCR_SD_SDR25PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000338UL )
+#define XIOU_SLCR_SD_SDR25PRESET_RSTVAL   0x00020002UL
+
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL  0x2UL
+
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_SDR25PRESET_XSDPS_DEFVAL  0x2UL
+
+/**
+ * Register: XiouSlcrSdSdr50prset
+ */
+#define XIOU_SLCR_SD_SDR50PRSET    ( ( XIOU_SLCR_BASEADDR ) + 0x0000033CUL )
+#define XIOU_SLCR_SD_SDR50PRSET_RSTVAL   0x00010001UL
+
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   16UL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
+
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_SHIFT   0UL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_SDR50PRSET_XSDPS_SDR50PRESET_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrSdSdr104prst
+ */
+#define XIOU_SLCR_SD_SDR104PRST    ( ( XIOU_SLCR_BASEADDR ) + 0x00000340UL )
+#define XIOU_SLCR_SD_SDR104PRST_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   16UL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_SHIFT   0UL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_WIDTH   13UL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_SDR104PRST_XSDPS_SDR104PRESET_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdDdr50preset
+ */
+#define XIOU_SLCR_SD_DDR50PRESET    ( ( XIOU_SLCR_BASEADDR ) + 0x00000344UL )
+#define XIOU_SLCR_SD_DDR50PRESET_RSTVAL   0x00020002UL
+
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK    0x1fff0000UL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL  0x2UL
+
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_WIDTH   13UL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_MASK    0x00001fffUL
+#define XIOU_SLCR_SD_DDR50PRESET_XSDPS_DEFVAL  0x2UL
+
+/**
+ * Register: XiouSlcrSdMaxcur1p8
+ */
+#define XIOU_SLCR_SD_MAXCUR1P8    ( ( XIOU_SLCR_BASEADDR ) + 0x0000034CUL )
+#define XIOU_SLCR_SD_MAXCUR1P8_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD_MAXCUR1P8_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdMaxcur3p0
+ */
+#define XIOU_SLCR_SD_MAXCUR3P0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000350UL )
+#define XIOU_SLCR_SD_MAXCUR3P0_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD_MAXCUR3P0_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdMaxcur3p3
+ */
+#define XIOU_SLCR_SD_MAXCUR3P3    ( ( XIOU_SLCR_BASEADDR ) + 0x00000354UL )
+#define XIOU_SLCR_SD_MAXCUR3P3_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK    0x00ff0000UL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_WIDTH   8UL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_MASK    0x000000ffUL
+#define XIOU_SLCR_SD_MAXCUR3P3_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdDllCtrl
+ */
+#define XIOU_SLCR_SD_DLL_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000358UL )
+#define XIOU_SLCR_SD_DLL_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT   18UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK    0x00040000UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT   17UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00020000UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT   16UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK    0x00010000UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_SHIFT   2UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_MASK    0x00000004UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_RST_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_SHIFT   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_MASK    0x00000002UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_TESTMODE_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_SHIFT   0UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_WIDTH   1UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_MASK    0x00000001UL
+#define XIOU_SLCR_SD_DLL_CTRL_XSDPS_LOCK_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrSdCdnCtrl
+ */
+#define XIOU_SLCR_SD_CDN_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x0000035CUL )
+#define XIOU_SLCR_SD_CDN_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT   16UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK    0x00010000UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_SHIFT   0UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_MASK    0x00000001UL
+#define XIOU_SLCR_SD_CDN_CTRL_XSDPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrGemCtrl
+ */
+#define XIOU_SLCR_GEM_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000360UL )
+#define XIOU_SLCR_GEM_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   6UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x000000c0UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   4UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x00000030UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   2UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x0000000cUL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_SHIFT   0UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_WIDTH   2UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_MASK    0x00000003UL
+#define XIOU_SLCR_GEM_CTRL_XEMACPS_SGMII_SD_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrTtcApbClk
+ */
+#define XIOU_SLCR_TTC_APB_CLK    ( ( XIOU_SLCR_BASEADDR ) + 0x00000380UL )
+#define XIOU_SLCR_TTC_APB_CLK_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_SHIFT   6UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_MASK    0x000000c0UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC3_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_SHIFT   4UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_MASK    0x00000030UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC2_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_SHIFT   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_MASK    0x0000000cUL
+#define XIOU_SLCR_TTC_APB_CLK_TTC1_SEL_DEFVAL  0x0UL
+
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_SHIFT   0UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_WIDTH   2UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_MASK    0x00000003UL
+#define XIOU_SLCR_TTC_APB_CLK_TTC0_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrTapdlyBypass
+ */
+#define XIOU_SLCR_TAPDLY_BYPASS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000390UL )
+#define XIOU_SLCR_TAPDLY_BYPASS_RSTVAL   0x00000007UL
+
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_SHIFT   2UL
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_WIDTH   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_MASK    0x00000004UL
+#define XIOU_SLCR_TAPDLY_BYPASS_LQSPI_RX_DEFVAL  0x1UL
+
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_SHIFT   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_WIDTH   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_MASK    0x00000002UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_OUT_DEFVAL  0x1UL
+
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_SHIFT   0UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_WIDTH   1UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_MASK    0x00000001UL
+#define XIOU_SLCR_TAPDLY_BYPASS_XNANDPS8_DQS_IN_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrCoherentCtrl
+ */
+#define XIOU_SLCR_COHERENT_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000400UL )
+#define XIOU_SLCR_COHERENT_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_SHIFT   28UL
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_MASK    0xf0000000UL
+#define XIOU_SLCR_COHERENT_CTRL_XQSPIPSAXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_SHIFT   24UL
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_MASK    0x0f000000UL
+#define XIOU_SLCR_COHERENT_CTRL_XNANDPS8_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT   20UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK    0x00f00000UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_SHIFT   16UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_MASK    0x000f0000UL
+#define XIOU_SLCR_COHERENT_CTRL_XSDPS_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   12UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x0000f000UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   8UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x00000f00UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x000000f0UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_SHIFT   0UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_WIDTH   4UL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_MASK    0x0000000fUL
+#define XIOU_SLCR_COHERENT_CTRL_XEMACPS_AXI_COH_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrVideoPssClkSel
+ */
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000404UL )
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_SHIFT   1UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_WIDTH   1UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_MASK    0x00000002UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_ALT_DEFVAL  0x0UL
+
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_SHIFT   0UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_WIDTH   1UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_MASK    0x00000001UL
+#define XIOU_SLCR_VIDEO_PSS_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrInterconnectRoute
+ */
+#define XIOU_SLCR_INTERCONNECT_ROUTE    ( ( XIOU_SLCR_BASEADDR ) + 0x00000408UL )
+#define XIOU_SLCR_INTERCONNECT_ROUTE_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_SHIFT   7UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_MASK    0x00000080UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XNANDPS8_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_SHIFT   6UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_MASK    0x00000040UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_QSPI_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT   5UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK    0x00000020UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_SHIFT   4UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_MASK    0x00000010UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XSDPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   3UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000008UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   2UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000004UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000002UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_SHIFT   0UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_WIDTH   1UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_MASK    0x00000001UL
+#define XIOU_SLCR_INTERCONNECT_ROUTE_XEMACPS_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrRamXemacps
+ */
+#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000500UL )
+#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXemacps
+ */
+#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000504UL )
+#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXemacps
+ */
+#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000508UL )
+#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXemacps
+ */
+#define XIOU_SLCR_RAM_XEMACPS    ( ( XIOU_SLCR_BASEADDR ) + 0x0000050CUL )
+#define XIOU_SLCR_RAM_XEMACPS_RSTVAL   0x00005b5bUL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XEMACPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XEMACPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXsdps
+ */
+#define XIOU_SLCR_RAM_XSDPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000510UL )
+#define XIOU_SLCR_RAM_XSDPS_RSTVAL   0x0000005bUL
+
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXsdps
+ */
+#define XIOU_SLCR_RAM_XSDPS    ( ( XIOU_SLCR_BASEADDR ) + 0x00000514UL )
+#define XIOU_SLCR_RAM_XSDPS_RSTVAL   0x0000005bUL
+
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XSDPS_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XSDPS_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XSDPS_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamCan0
+ */
+#define XIOU_SLCR_RAM_CAN0    ( ( XIOU_SLCR_BASEADDR ) + 0x00000518UL )
+#define XIOU_SLCR_RAM_CAN0_RSTVAL   0x005b5b5bUL
+
+#define XIOU_SLCR_RAM_CAN0_EMASA2_SHIFT   22UL
+#define XIOU_SLCR_RAM_CAN0_EMASA2_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN0_EMASA2_MASK    0x00400000UL
+#define XIOU_SLCR_RAM_CAN0_EMASA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAB2_SHIFT   19UL
+#define XIOU_SLCR_RAM_CAN0_EMAB2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB2_MASK    0x00380000UL
+#define XIOU_SLCR_RAM_CAN0_EMAB2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAA2_SHIFT   16UL
+#define XIOU_SLCR_RAM_CAN0_EMAA2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAA2_MASK    0x00070000UL
+#define XIOU_SLCR_RAM_CAN0_EMAA2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_CAN0_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN0_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_CAN0_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_CAN0_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_CAN0_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_CAN0_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_CAN0_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_CAN0_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN0_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_CAN0_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_CAN0_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN0_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_CAN0_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN0_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_CAN0_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamCan1
+ */
+#define XIOU_SLCR_RAM_CAN1    ( ( XIOU_SLCR_BASEADDR ) + 0x0000051CUL )
+#define XIOU_SLCR_RAM_CAN1_RSTVAL   0x005b5b5bUL
+
+#define XIOU_SLCR_RAM_CAN1_EMASA2_SHIFT   22UL
+#define XIOU_SLCR_RAM_CAN1_EMASA2_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN1_EMASA2_MASK    0x00400000UL
+#define XIOU_SLCR_RAM_CAN1_EMASA2_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAB2_SHIFT   19UL
+#define XIOU_SLCR_RAM_CAN1_EMAB2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB2_MASK    0x00380000UL
+#define XIOU_SLCR_RAM_CAN1_EMAB2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAA2_SHIFT   16UL
+#define XIOU_SLCR_RAM_CAN1_EMAA2_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAA2_MASK    0x00070000UL
+#define XIOU_SLCR_RAM_CAN1_EMAA2_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMASA1_SHIFT   14UL
+#define XIOU_SLCR_RAM_CAN1_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN1_EMASA1_MASK    0x00004000UL
+#define XIOU_SLCR_RAM_CAN1_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAB1_SHIFT   11UL
+#define XIOU_SLCR_RAM_CAN1_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB1_MASK    0x00003800UL
+#define XIOU_SLCR_RAM_CAN1_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAA1_SHIFT   8UL
+#define XIOU_SLCR_RAM_CAN1_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAA1_MASK    0x00000700UL
+#define XIOU_SLCR_RAM_CAN1_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_CAN1_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_CAN1_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_CAN1_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_CAN1_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_CAN1_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_CAN1_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_CAN1_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_CAN1_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamLqspi
+ */
+#define XIOU_SLCR_RAM_LQSPI    ( ( XIOU_SLCR_BASEADDR ) + 0x00000520UL )
+#define XIOU_SLCR_RAM_LQSPI_RSTVAL   0x00002ddbUL
+
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_SHIFT   13UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_WIDTH   1UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_MASK    0x00002000UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA1_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_SHIFT   10UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_MASK    0x00001c00UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_SHIFT   7UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_MASK    0x00000380UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA1_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_LQSPI_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_LQSPI_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_LQSPI_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrRamXnandps8
+ */
+#define XIOU_SLCR_RAM_XNANDPS8    ( ( XIOU_SLCR_BASEADDR ) + 0x00000524UL )
+#define XIOU_SLCR_RAM_XNANDPS8_RSTVAL   0x0000005bUL
+
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_SHIFT   6UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_WIDTH   1UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_MASK    0x00000040UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMASA0_DEFVAL  0x1UL
+
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_SHIFT   3UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_MASK    0x00000038UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAB0_DEFVAL  0x3UL
+
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_SHIFT   0UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_WIDTH   3UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_MASK    0x00000007UL
+#define XIOU_SLCR_RAM_XNANDPS8_EMAA0_DEFVAL  0x3UL
+
+/**
+ * Register: XiouSlcrCtrl
+ */
+#define XIOU_SLCR_CTRL    ( ( XIOU_SLCR_BASEADDR ) + 0x00000600UL )
+#define XIOU_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XIOU_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XIOU_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XIOU_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrIsr
+ */
+#define XIOU_SLCR_ISR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000700UL )
+#define XIOU_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrImr
+ */
+#define XIOU_SLCR_IMR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000704UL )
+#define XIOU_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XiouSlcrIer
+ */
+#define XIOU_SLCR_IER    ( ( XIOU_SLCR_BASEADDR ) + 0x00000708UL )
+#define XIOU_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrIdr
+ */
+#define XIOU_SLCR_IDR    ( ( XIOU_SLCR_BASEADDR ) + 0x0000070CUL )
+#define XIOU_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XiouSlcrItr
+ */
+#define XIOU_SLCR_ITR    ( ( XIOU_SLCR_BASEADDR ) + 0x00000710UL )
+#define XIOU_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XIOU_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XIOU_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr.h
new file mode 100644
index 000000000..cc05672e4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr.h
@@ -0,0 +1,5667 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_SLCR_H__
+#define __XLPD_SLCR_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdSlcr Base Address
+ */
+#define XLPD_SLCR_BASEADDR      0xFF410000UL
+
+/**
+ * Register: XlpdSlcrWprot0
+ */
+#define XLPD_SLCR_WPROT0    ( ( XLPD_SLCR_BASEADDR ) + 0x00000000UL )
+#define XLPD_SLCR_WPROT0_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_WPROT0_ACT_SHIFT   0UL
+#define XLPD_SLCR_WPROT0_ACT_WIDTH   1UL
+#define XLPD_SLCR_WPROT0_ACT_MASK    0x00000001UL
+#define XLPD_SLCR_WPROT0_ACT_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrCtrl
+ */
+#define XLPD_SLCR_CTRL    ( ( XLPD_SLCR_BASEADDR ) + 0x00000004UL )
+#define XLPD_SLCR_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_CTRL_SLVERR_EN_SHIFT   0UL
+#define XLPD_SLCR_CTRL_SLVERR_EN_WIDTH   1UL
+#define XLPD_SLCR_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XLPD_SLCR_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsr
+ */
+#define XLPD_SLCR_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000008UL )
+#define XLPD_SLCR_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrImr
+ */
+#define XLPD_SLCR_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000000CUL )
+#define XLPD_SLCR_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrIer
+ */
+#define XLPD_SLCR_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00000010UL )
+#define XLPD_SLCR_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIdr
+ */
+#define XLPD_SLCR_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000014UL )
+#define XLPD_SLCR_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrItr
+ */
+#define XLPD_SLCR_ITR    ( ( XLPD_SLCR_BASEADDR ) + 0x00000018UL )
+#define XLPD_SLCR_ITR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk0
+ */
+#define XLPD_SLCR_SAFETY_CHK0    ( ( XLPD_SLCR_BASEADDR ) + 0x00000040UL )
+#define XLPD_SLCR_SAFETY_CHK0_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK0_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK0_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK0_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK0_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk1
+ */
+#define XLPD_SLCR_SAFETY_CHK1    ( ( XLPD_SLCR_BASEADDR ) + 0x00000044UL )
+#define XLPD_SLCR_SAFETY_CHK1_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK1_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK1_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK1_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK1_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk2
+ */
+#define XLPD_SLCR_SAFETY_CHK2    ( ( XLPD_SLCR_BASEADDR ) + 0x00000048UL )
+#define XLPD_SLCR_SAFETY_CHK2_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK2_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK2_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK2_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK2_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSafetyChk3
+ */
+#define XLPD_SLCR_SAFETY_CHK3    ( ( XLPD_SLCR_BASEADDR ) + 0x0000004CUL )
+#define XLPD_SLCR_SAFETY_CHK3_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SAFETY_CHK3_VAL_SHIFT   0UL
+#define XLPD_SLCR_SAFETY_CHK3_VAL_WIDTH   32UL
+#define XLPD_SLCR_SAFETY_CHK3_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SAFETY_CHK3_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrXcsupmuWdtClkSel
+ */
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL    ( ( XLPD_SLCR_BASEADDR ) + 0x00000050UL )
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_SHIFT   0UL
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_WIDTH   1UL
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_MASK    0x00000001UL
+#define XLPD_SLCR_XCSUPMU_WDT_CLK_SEL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAdmaCfg
+ */
+#define XLPD_SLCR_ADMA_CFG    ( ( XLPD_SLCR_BASEADDR ) + 0x0000200CUL )
+#define XLPD_SLCR_ADMA_CFG_RSTVAL   0x00000028UL
+
+#define XLPD_SLCR_ADMA_CFG_BUSWID_SHIFT   5UL
+#define XLPD_SLCR_ADMA_CFG_BUSWID_WIDTH   2UL
+#define XLPD_SLCR_ADMA_CFG_BUSWID_MASK    0x00000060UL
+#define XLPD_SLCR_ADMA_CFG_BUSWID_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_SHIFT   0UL
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_WIDTH   5UL
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_MASK    0x0000001fUL
+#define XLPD_SLCR_ADMA_CFG_NUM_CH_DEFVAL  0x8UL
+
+/**
+ * Register: XlpdSlcrAdmaRam
+ */
+#define XLPD_SLCR_ADMA_RAM    ( ( XLPD_SLCR_BASEADDR ) + 0x00002010UL )
+#define XLPD_SLCR_ADMA_RAM_RSTVAL   0x00003b3bUL
+
+#define XLPD_SLCR_ADMA_RAM1_EMAB_SHIFT   12UL
+#define XLPD_SLCR_ADMA_RAM1_EMAB_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM1_EMAB_MASK    0x00007000UL
+#define XLPD_SLCR_ADMA_RAM1_EMAB_DEFVAL  0x3UL
+
+#define XLPD_SLCR_ADMA_RAM1_EMASA_SHIFT   11UL
+#define XLPD_SLCR_ADMA_RAM1_EMASA_WIDTH   1UL
+#define XLPD_SLCR_ADMA_RAM1_EMASA_MASK    0x00000800UL
+#define XLPD_SLCR_ADMA_RAM1_EMASA_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ADMA_RAM1_EMAA_SHIFT   8UL
+#define XLPD_SLCR_ADMA_RAM1_EMAA_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM1_EMAA_MASK    0x00000700UL
+#define XLPD_SLCR_ADMA_RAM1_EMAA_DEFVAL  0x3UL
+
+#define XLPD_SLCR_ADMA_RAM0_EMAB_SHIFT   4UL
+#define XLPD_SLCR_ADMA_RAM0_EMAB_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM0_EMAB_MASK    0x00000070UL
+#define XLPD_SLCR_ADMA_RAM0_EMAB_DEFVAL  0x3UL
+
+#define XLPD_SLCR_ADMA_RAM0_EMASA_SHIFT   3UL
+#define XLPD_SLCR_ADMA_RAM0_EMASA_WIDTH   1UL
+#define XLPD_SLCR_ADMA_RAM0_EMASA_MASK    0x00000008UL
+#define XLPD_SLCR_ADMA_RAM0_EMASA_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ADMA_RAM0_EMAA_SHIFT   0UL
+#define XLPD_SLCR_ADMA_RAM0_EMAA_WIDTH   3UL
+#define XLPD_SLCR_ADMA_RAM0_EMAA_MASK    0x00000007UL
+#define XLPD_SLCR_ADMA_RAM0_EMAA_DEFVAL  0x3UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiIsr
+ */
+#define XLPD_SLCR_ERR_AIBAXI_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003000UL )
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_ISR_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiImr
+ */
+#define XLPD_SLCR_ERR_AIBAXI_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003008UL )
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RSTVAL   0x1dcf000fUL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_DDR_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_OCMS_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_MAIN_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB1S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_USB0S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUS0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_RPUM0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_OCM_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_FPD_LPDIBS_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_IMR_AFIFS0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiIer
+ */
+#define XLPD_SLCR_ERR_AIBAXI_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00003010UL )
+#define XLPD_SLCR_ERR_AIBAXI_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_IER_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibaxiIdr
+ */
+#define XLPD_SLCR_ERR_AIBAXI_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003018UL )
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_SHIFT   27UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAXI_IDR_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibapbIsr
+ */
+#define XLPD_SLCR_ERR_AIBAPB_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003020UL )
+#define XLPD_SLCR_ERR_AIBAPB_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_ISR_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibapbImr
+ */
+#define XLPD_SLCR_ERR_AIBAPB_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00003024UL )
+#define XLPD_SLCR_ERR_AIBAPB_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_IMR_GPU_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrErrAibapbIer
+ */
+#define XLPD_SLCR_ERR_AIBAPB_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00003028UL )
+#define XLPD_SLCR_ERR_AIBAPB_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_IER_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAibapbIdr
+ */
+#define XLPD_SLCR_ERR_AIBAPB_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000302CUL )
+#define XLPD_SLCR_ERR_AIBAPB_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_SHIFT   0UL
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_WIDTH   1UL
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_AIBAPB_IDR_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibaxiReq
+ */
+#define XLPD_SLCR_ISO_AIBAXI_REQ    ( ( XLPD_SLCR_BASEADDR ) + 0x00003030UL )
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_SHIFT   27UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAXI_REQ_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibaxiType
+ */
+#define XLPD_SLCR_ISO_AIBAXI_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x00003038UL )
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RSTVAL   0x19cf000fUL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_SHIFT   27UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_DDR_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_MAIN_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB1S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_USB0S_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUS0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_RPUM0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_OCM_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_FPD_LPDIBS_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAXI_TYPE_AFIFS0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrIsoAibaxiAck
+ */
+#define XLPD_SLCR_ISO_AIBAXI_ACK    ( ( XLPD_SLCR_BASEADDR ) + 0x00003040UL )
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_SHIFT   28UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_MASK    0x10000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_SHIFT   27UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_MASK    0x08000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_DDR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_SHIFT   26UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_MASK    0x04000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_OCMS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_SHIFT   24UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_MASK    0x01000000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_MAIN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_SHIFT   23UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_MASK    0x00800000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB1S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_SHIFT   22UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_MASK    0x00400000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_USB0S_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_SHIFT   19UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_MASK    0x00080000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_SHIFT   18UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_MASK    0x00040000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUS0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_SHIFT   17UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_MASK    0x00020000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_SHIFT   16UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_MASK    0x00010000UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_RPUM0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_SHIFT   3UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_MASK    0x00000008UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_OCM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_SHIFT   2UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_MASK    0x00000004UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_FPD_LPDIBS_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_SHIFT   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_MASK    0x00000002UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAXI_ACK_AFIFS0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibapbReq
+ */
+#define XLPD_SLCR_ISO_AIBAPB_REQ    ( ( XLPD_SLCR_BASEADDR ) + 0x00003048UL )
+#define XLPD_SLCR_ISO_AIBAPB_REQ_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAPB_REQ_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrIsoAibapbType
+ */
+#define XLPD_SLCR_ISO_AIBAPB_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x0000304CUL )
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAPB_TYPE_GPU_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrIsoAibapbAck
+ */
+#define XLPD_SLCR_ISO_AIBAPB_ACK    ( ( XLPD_SLCR_BASEADDR ) + 0x00003050UL )
+#define XLPD_SLCR_ISO_AIBAPB_ACK_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_SHIFT   0UL
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_WIDTH   1UL
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_MASK    0x00000001UL
+#define XLPD_SLCR_ISO_AIBAPB_ACK_GPU_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAtbIsr
+ */
+#define XLPD_SLCR_ERR_ATB_ISR    ( ( XLPD_SLCR_BASEADDR ) + 0x00006000UL )
+#define XLPD_SLCR_ERR_ATB_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_ISR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_ISR_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAtbImr
+ */
+#define XLPD_SLCR_ERR_ATB_IMR    ( ( XLPD_SLCR_BASEADDR ) + 0x00006004UL )
+#define XLPD_SLCR_ERR_ATB_IMR_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_IMR_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_IMR_LPDM_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrErrAtbIer
+ */
+#define XLPD_SLCR_ERR_ATB_IER    ( ( XLPD_SLCR_BASEADDR ) + 0x00006008UL )
+#define XLPD_SLCR_ERR_ATB_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_IER_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_IER_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrErrAtbIdr
+ */
+#define XLPD_SLCR_ERR_ATB_IDR    ( ( XLPD_SLCR_BASEADDR ) + 0x0000600CUL )
+#define XLPD_SLCR_ERR_ATB_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ERR_ATB_IDR_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ERR_ATB_IDR_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAtbCmdStoreEn
+ */
+#define XLPD_SLCR_ATB_CMD_STORE_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00006010UL )
+#define XLPD_SLCR_ATB_CMD_STORE_EN_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ATB_CMD_STORE_EN_LPDM_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrAtbRespEn
+ */
+#define XLPD_SLCR_ATB_RESP_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00006014UL )
+#define XLPD_SLCR_ATB_RESP_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ATB_RESP_EN_AFIFS2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ATB_RESP_EN_LPDM_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAtbRespType
+ */
+#define XLPD_SLCR_ATB_RESP_TYPE    ( ( XLPD_SLCR_BASEADDR ) + 0x00006018UL )
+#define XLPD_SLCR_ATB_RESP_TYPE_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_SHIFT   1UL
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_MASK    0x00000002UL
+#define XLPD_SLCR_ATB_RESP_TYPE_AFIFS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_SHIFT   0UL
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_WIDTH   1UL
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_MASK    0x00000001UL
+#define XLPD_SLCR_ATB_RESP_TYPE_LPDM_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrAtbPrescale
+ */
+#define XLPD_SLCR_ATB_PRESCALE    ( ( XLPD_SLCR_BASEADDR ) + 0x00006020UL )
+#define XLPD_SLCR_ATB_PRESCALE_RSTVAL   0x0000ffffUL
+
+#define XLPD_SLCR_ATB_PRESCALE_EN_SHIFT   16UL
+#define XLPD_SLCR_ATB_PRESCALE_EN_WIDTH   1UL
+#define XLPD_SLCR_ATB_PRESCALE_EN_MASK    0x00010000UL
+#define XLPD_SLCR_ATB_PRESCALE_EN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_ATB_PRESCALE_VAL_SHIFT   0UL
+#define XLPD_SLCR_ATB_PRESCALE_VAL_WIDTH   16UL
+#define XLPD_SLCR_ATB_PRESCALE_VAL_MASK    0x0000ffffUL
+#define XLPD_SLCR_ATB_PRESCALE_VAL_DEFVAL  0xffffUL
+
+/**
+ * Register: XlpdSlcrMutex0
+ */
+#define XLPD_SLCR_MUTEX0    ( ( XLPD_SLCR_BASEADDR ) + 0x00007000UL )
+#define XLPD_SLCR_MUTEX0_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX0_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX0_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX0_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX0_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrMutex1
+ */
+#define XLPD_SLCR_MUTEX1    ( ( XLPD_SLCR_BASEADDR ) + 0x00007004UL )
+#define XLPD_SLCR_MUTEX1_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX1_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX1_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX1_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX1_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrMutex2
+ */
+#define XLPD_SLCR_MUTEX2    ( ( XLPD_SLCR_BASEADDR ) + 0x00007008UL )
+#define XLPD_SLCR_MUTEX2_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX2_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX2_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX2_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX2_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrMutex3
+ */
+#define XLPD_SLCR_MUTEX3    ( ( XLPD_SLCR_BASEADDR ) + 0x0000700CUL )
+#define XLPD_SLCR_MUTEX3_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_MUTEX3_ID_SHIFT   0UL
+#define XLPD_SLCR_MUTEX3_ID_WIDTH   32UL
+#define XLPD_SLCR_MUTEX3_ID_MASK    0xffffffffUL
+#define XLPD_SLCR_MUTEX3_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqSts
+ */
+#define XLPD_SLCR_GICP0_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008000UL )
+#define XLPD_SLCR_GICP0_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqMsk
+ */
+#define XLPD_SLCR_GICP0_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008004UL )
+#define XLPD_SLCR_GICP0_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqEn
+ */
+#define XLPD_SLCR_GICP0_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008008UL )
+#define XLPD_SLCR_GICP0_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqDis
+ */
+#define XLPD_SLCR_GICP0_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000800CUL )
+#define XLPD_SLCR_GICP0_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp0IrqTrig
+ */
+#define XLPD_SLCR_GICP0_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008010UL )
+#define XLPD_SLCR_GICP0_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP0_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqSts
+ */
+#define XLPD_SLCR_GICP1_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008014UL )
+#define XLPD_SLCR_GICP1_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqMsk
+ */
+#define XLPD_SLCR_GICP1_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008018UL )
+#define XLPD_SLCR_GICP1_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqEn
+ */
+#define XLPD_SLCR_GICP1_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x0000801CUL )
+#define XLPD_SLCR_GICP1_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqDis
+ */
+#define XLPD_SLCR_GICP1_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008020UL )
+#define XLPD_SLCR_GICP1_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp1IrqTrig
+ */
+#define XLPD_SLCR_GICP1_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008024UL )
+#define XLPD_SLCR_GICP1_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP1_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqSts
+ */
+#define XLPD_SLCR_GICP2_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008028UL )
+#define XLPD_SLCR_GICP2_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqMsk
+ */
+#define XLPD_SLCR_GICP2_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x0000802CUL )
+#define XLPD_SLCR_GICP2_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqEn
+ */
+#define XLPD_SLCR_GICP2_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008030UL )
+#define XLPD_SLCR_GICP2_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqDis
+ */
+#define XLPD_SLCR_GICP2_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008034UL )
+#define XLPD_SLCR_GICP2_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp2IrqTrig
+ */
+#define XLPD_SLCR_GICP2_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008038UL )
+#define XLPD_SLCR_GICP2_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP2_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqSts
+ */
+#define XLPD_SLCR_GICP3_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000803CUL )
+#define XLPD_SLCR_GICP3_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqMsk
+ */
+#define XLPD_SLCR_GICP3_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008040UL )
+#define XLPD_SLCR_GICP3_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqEn
+ */
+#define XLPD_SLCR_GICP3_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008044UL )
+#define XLPD_SLCR_GICP3_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqDis
+ */
+#define XLPD_SLCR_GICP3_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008048UL )
+#define XLPD_SLCR_GICP3_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp3IrqTrig
+ */
+#define XLPD_SLCR_GICP3_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x0000804CUL )
+#define XLPD_SLCR_GICP3_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP3_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqSts
+ */
+#define XLPD_SLCR_GICP4_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x00008050UL )
+#define XLPD_SLCR_GICP4_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqMsk
+ */
+#define XLPD_SLCR_GICP4_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x00008054UL )
+#define XLPD_SLCR_GICP4_IRQ_MSK_RSTVAL   0xffffffffUL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC31_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC30_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC29_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC28_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC27_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC26_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC25_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC24_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC23_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC22_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC21_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC20_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC19_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC18_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC17_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC16_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC15_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC14_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC13_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC12_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC11_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC10_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC9_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC8_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqEn
+ */
+#define XLPD_SLCR_GICP4_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x00008058UL )
+#define XLPD_SLCR_GICP4_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqDis
+ */
+#define XLPD_SLCR_GICP4_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x0000805CUL )
+#define XLPD_SLCR_GICP4_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicp4IrqTrig
+ */
+#define XLPD_SLCR_GICP4_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x00008060UL )
+#define XLPD_SLCR_GICP4_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_SHIFT   31UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_MASK    0x80000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC31_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_SHIFT   30UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_MASK    0x40000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC30_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_SHIFT   29UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_MASK    0x20000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC29_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_SHIFT   28UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_MASK    0x10000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC28_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_SHIFT   27UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_MASK    0x08000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC27_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_SHIFT   26UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_MASK    0x04000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC26_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_SHIFT   25UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_MASK    0x02000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC25_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_SHIFT   24UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_MASK    0x01000000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC24_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_SHIFT   23UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_MASK    0x00800000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC23_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_SHIFT   22UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_MASK    0x00400000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC22_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_SHIFT   21UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_MASK    0x00200000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC21_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_SHIFT   20UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_MASK    0x00100000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC20_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_SHIFT   19UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_MASK    0x00080000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC19_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_SHIFT   18UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_MASK    0x00040000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC18_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_SHIFT   17UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_MASK    0x00020000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC17_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_SHIFT   16UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_MASK    0x00010000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC16_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_SHIFT   15UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_MASK    0x00008000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_SHIFT   14UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_MASK    0x00004000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_SHIFT   13UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_MASK    0x00002000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_SHIFT   12UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_MASK    0x00001000UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_SHIFT   11UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_MASK    0x00000800UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC11_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_SHIFT   10UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_MASK    0x00000400UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_SHIFT   9UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_MASK    0x00000200UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_SHIFT   8UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_MASK    0x00000100UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP4_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqSts
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_STS    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A0UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_STS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqMsk
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A4UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_RSTVAL   0x000000ffUL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC7_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC6_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_MSK_SRC0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqEn
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_EN    ( ( XLPD_SLCR_BASEADDR ) + 0x000080A8UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_EN_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqDis
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS    ( ( XLPD_SLCR_BASEADDR ) + 0x000080ACUL )
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_DIS_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrGicpPmuIrqTrig
+ */
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG    ( ( XLPD_SLCR_BASEADDR ) + 0x000080B0UL )
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_SHIFT   7UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_MASK    0x00000080UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_SHIFT   6UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_MASK    0x00000040UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_SHIFT   5UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_MASK    0x00000020UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_SHIFT   4UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_MASK    0x00000010UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_SHIFT   3UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_MASK    0x00000008UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_SHIFT   2UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_MASK    0x00000004UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_SHIFT   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_MASK    0x00000002UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_SHIFT   0UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_WIDTH   1UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_MASK    0x00000001UL
+#define XLPD_SLCR_GICP_PMU_IRQ_TRIG_SRC0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrAfiFs
+ */
+#define XLPD_SLCR_AFI_FS    ( ( XLPD_SLCR_BASEADDR ) + 0x00009000UL )
+#define XLPD_SLCR_AFI_FS_RSTVAL   0x00000200UL
+
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_SHIFT   8UL
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_WIDTH   2UL
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_MASK    0x00000300UL
+#define XLPD_SLCR_AFI_FS_DW_SS2_SEL_DEFVAL  0x2UL
+
+/**
+ * Register: XlpdSlcrCci
+ */
+#define XLPD_SLCR_CCI    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A000UL )
+#define XLPD_SLCR_CCI_RSTVAL   0x03801c07UL
+
+#define XLPD_SLCR_CCI_SPR_SHIFT   28UL
+#define XLPD_SLCR_CCI_SPR_WIDTH   4UL
+#define XLPD_SLCR_CCI_SPR_MASK    0xf0000000UL
+#define XLPD_SLCR_CCI_SPR_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVNVNETS4_SHIFT   27UL
+#define XLPD_SLCR_CCI_QVNVNETS4_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS4_MASK    0x08000000UL
+#define XLPD_SLCR_CCI_QVNVNETS4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVNVNETS3_SHIFT   26UL
+#define XLPD_SLCR_CCI_QVNVNETS3_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS3_MASK    0x04000000UL
+#define XLPD_SLCR_CCI_QVNVNETS3_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVNVNETS2_SHIFT   25UL
+#define XLPD_SLCR_CCI_QVNVNETS2_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS2_MASK    0x02000000UL
+#define XLPD_SLCR_CCI_QVNVNETS2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_QVNVNETS1_SHIFT   24UL
+#define XLPD_SLCR_CCI_QVNVNETS1_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS1_MASK    0x01000000UL
+#define XLPD_SLCR_CCI_QVNVNETS1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_QVNVNETS0_SHIFT   23UL
+#define XLPD_SLCR_CCI_QVNVNETS0_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVNVNETS0_MASK    0x00800000UL
+#define XLPD_SLCR_CCI_QVNVNETS0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_QOS_OVRRD_SHIFT   18UL
+#define XLPD_SLCR_CCI_QOS_OVRRD_WIDTH   5UL
+#define XLPD_SLCR_CCI_QOS_OVRRD_MASK    0x007c0000UL
+#define XLPD_SLCR_CCI_QOS_OVRRD_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVN_EN_M2_SHIFT   17UL
+#define XLPD_SLCR_CCI_QVN_EN_M2_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVN_EN_M2_MASK    0x00020000UL
+#define XLPD_SLCR_CCI_QVN_EN_M2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_QVN_EN_M1_SHIFT   16UL
+#define XLPD_SLCR_CCI_QVN_EN_M1_WIDTH   1UL
+#define XLPD_SLCR_CCI_QVN_EN_M1_MASK    0x00010000UL
+#define XLPD_SLCR_CCI_QVN_EN_M1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_STRPG_GRAN_SHIFT   13UL
+#define XLPD_SLCR_CCI_STRPG_GRAN_WIDTH   3UL
+#define XLPD_SLCR_CCI_STRPG_GRAN_MASK    0x0000e000UL
+#define XLPD_SLCR_CCI_STRPG_GRAN_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ACCHNLLEN4_SHIFT   12UL
+#define XLPD_SLCR_CCI_ACCHNLLEN4_WIDTH   1UL
+#define XLPD_SLCR_CCI_ACCHNLLEN4_MASK    0x00001000UL
+#define XLPD_SLCR_CCI_ACCHNLLEN4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_ACCHNLLEN3_SHIFT   11UL
+#define XLPD_SLCR_CCI_ACCHNLLEN3_WIDTH   1UL
+#define XLPD_SLCR_CCI_ACCHNLLEN3_MASK    0x00000800UL
+#define XLPD_SLCR_CCI_ACCHNLLEN3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_ACCHNLLEN0_SHIFT   10UL
+#define XLPD_SLCR_CCI_ACCHNLLEN0_WIDTH   1UL
+#define XLPD_SLCR_CCI_ACCHNLLEN0_MASK    0x00000400UL
+#define XLPD_SLCR_CCI_ACCHNLLEN0_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_ECOREVNUM_SHIFT   6UL
+#define XLPD_SLCR_CCI_ECOREVNUM_WIDTH   4UL
+#define XLPD_SLCR_CCI_ECOREVNUM_MASK    0x000003c0UL
+#define XLPD_SLCR_CCI_ECOREVNUM_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ASA2_SHIFT   5UL
+#define XLPD_SLCR_CCI_ASA2_WIDTH   1UL
+#define XLPD_SLCR_CCI_ASA2_MASK    0x00000020UL
+#define XLPD_SLCR_CCI_ASA2_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ASA1_SHIFT   4UL
+#define XLPD_SLCR_CCI_ASA1_WIDTH   1UL
+#define XLPD_SLCR_CCI_ASA1_MASK    0x00000010UL
+#define XLPD_SLCR_CCI_ASA1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ASA0_SHIFT   3UL
+#define XLPD_SLCR_CCI_ASA0_WIDTH   1UL
+#define XLPD_SLCR_CCI_ASA0_MASK    0x00000008UL
+#define XLPD_SLCR_CCI_ASA0_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_OWO2_SHIFT   2UL
+#define XLPD_SLCR_CCI_OWO2_WIDTH   1UL
+#define XLPD_SLCR_CCI_OWO2_MASK    0x00000004UL
+#define XLPD_SLCR_CCI_OWO2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_OWO1_SHIFT   1UL
+#define XLPD_SLCR_CCI_OWO1_WIDTH   1UL
+#define XLPD_SLCR_CCI_OWO1_MASK    0x00000002UL
+#define XLPD_SLCR_CCI_OWO1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_CCI_OWO0_SHIFT   0UL
+#define XLPD_SLCR_CCI_OWO0_WIDTH   1UL
+#define XLPD_SLCR_CCI_OWO0_MASK    0x00000001UL
+#define XLPD_SLCR_CCI_OWO0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrCciAddrmap
+ */
+#define XLPD_SLCR_CCI_ADDRMAP    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A004UL )
+#define XLPD_SLCR_CCI_ADDRMAP_RSTVAL   0x00c000ffUL
+
+#define XLPD_SLCR_CCI_ADDRMAP_15_SHIFT   30UL
+#define XLPD_SLCR_CCI_ADDRMAP_15_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_15_MASK    0xc0000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_15_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_14_SHIFT   28UL
+#define XLPD_SLCR_CCI_ADDRMAP_14_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_14_MASK    0x30000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_14_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_13_SHIFT   26UL
+#define XLPD_SLCR_CCI_ADDRMAP_13_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_13_MASK    0x0c000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_13_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_12_SHIFT   24UL
+#define XLPD_SLCR_CCI_ADDRMAP_12_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_12_MASK    0x03000000UL
+#define XLPD_SLCR_CCI_ADDRMAP_12_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_11_SHIFT   22UL
+#define XLPD_SLCR_CCI_ADDRMAP_11_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_11_MASK    0x00c00000UL
+#define XLPD_SLCR_CCI_ADDRMAP_11_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_10_SHIFT   20UL
+#define XLPD_SLCR_CCI_ADDRMAP_10_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_10_MASK    0x00300000UL
+#define XLPD_SLCR_CCI_ADDRMAP_10_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_9_SHIFT   18UL
+#define XLPD_SLCR_CCI_ADDRMAP_9_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_9_MASK    0x000c0000UL
+#define XLPD_SLCR_CCI_ADDRMAP_9_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_8_SHIFT   16UL
+#define XLPD_SLCR_CCI_ADDRMAP_8_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_8_MASK    0x00030000UL
+#define XLPD_SLCR_CCI_ADDRMAP_8_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_7_SHIFT   14UL
+#define XLPD_SLCR_CCI_ADDRMAP_7_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_7_MASK    0x0000c000UL
+#define XLPD_SLCR_CCI_ADDRMAP_7_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_6_SHIFT   12UL
+#define XLPD_SLCR_CCI_ADDRMAP_6_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_6_MASK    0x00003000UL
+#define XLPD_SLCR_CCI_ADDRMAP_6_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_5_SHIFT   10UL
+#define XLPD_SLCR_CCI_ADDRMAP_5_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_5_MASK    0x00000c00UL
+#define XLPD_SLCR_CCI_ADDRMAP_5_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_4_SHIFT   8UL
+#define XLPD_SLCR_CCI_ADDRMAP_4_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_4_MASK    0x00000300UL
+#define XLPD_SLCR_CCI_ADDRMAP_4_DEFVAL  0x0UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_3_SHIFT   6UL
+#define XLPD_SLCR_CCI_ADDRMAP_3_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_3_MASK    0x000000c0UL
+#define XLPD_SLCR_CCI_ADDRMAP_3_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_2_SHIFT   4UL
+#define XLPD_SLCR_CCI_ADDRMAP_2_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_2_MASK    0x00000030UL
+#define XLPD_SLCR_CCI_ADDRMAP_2_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_1_SHIFT   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_1_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_1_MASK    0x0000000cUL
+#define XLPD_SLCR_CCI_ADDRMAP_1_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_ADDRMAP_0_SHIFT   0UL
+#define XLPD_SLCR_CCI_ADDRMAP_0_WIDTH   2UL
+#define XLPD_SLCR_CCI_ADDRMAP_0_MASK    0x00000003UL
+#define XLPD_SLCR_CCI_ADDRMAP_0_DEFVAL  0x3UL
+
+/**
+ * Register: XlpdSlcrCciQvnprealloc
+ */
+#define XLPD_SLCR_CCI_QVNPREALLOC    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A008UL )
+#define XLPD_SLCR_CCI_QVNPREALLOC_RSTVAL   0x00330330UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_SHIFT   20UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_MASK    0x00f00000UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM2_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_SHIFT   16UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_MASK    0x000f0000UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_WM1_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_SHIFT   8UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_MASK    0x00000f00UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM2_DEFVAL  0x3UL
+
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_SHIFT   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_WIDTH   4UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_MASK    0x000000f0UL
+#define XLPD_SLCR_CCI_QVNPREALLOC_RM1_DEFVAL  0x3UL
+
+/**
+ * Register: XlpdSlcrSmmu
+ */
+#define XLPD_SLCR_SMMU    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A020UL )
+#define XLPD_SLCR_SMMU_RSTVAL   0x0000003fUL
+
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_SHIFT   7UL
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_WIDTH   1UL
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_MASK    0x00000080UL
+#define XLPD_SLCR_SMMU_INTG_SEC_OVRRDE_DEFVAL  0x0UL
+
+#define XLPD_SLCR_SMMU_CTTW_SHIFT   6UL
+#define XLPD_SLCR_SMMU_CTTW_WIDTH   1UL
+#define XLPD_SLCR_SMMU_CTTW_MASK    0x00000040UL
+#define XLPD_SLCR_SMMU_CTTW_DEFVAL  0x0UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_SHIFT   5UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_MASK    0x00000020UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU5_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_SHIFT   4UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_MASK    0x00000010UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU4_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_SHIFT   3UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_MASK    0x00000008UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU3_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_SHIFT   2UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_MASK    0x00000004UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU2_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_SHIFT   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_MASK    0x00000002UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_SHIFT   0UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_WIDTH   1UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_MASK    0x00000001UL
+#define XLPD_SLCR_SMMU_SYSBARDIS_TBU0_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrApu
+ */
+#define XLPD_SLCR_APU    ( ( XLPD_SLCR_BASEADDR ) + 0x0000A040UL )
+#define XLPD_SLCR_APU_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_APU_BRDC_BARRIER_SHIFT   3UL
+#define XLPD_SLCR_APU_BRDC_BARRIER_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_BARRIER_MASK    0x00000008UL
+#define XLPD_SLCR_APU_BRDC_BARRIER_DEFVAL  0x0UL
+
+#define XLPD_SLCR_APU_BRDC_CMNT_SHIFT   2UL
+#define XLPD_SLCR_APU_BRDC_CMNT_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_CMNT_MASK    0x00000004UL
+#define XLPD_SLCR_APU_BRDC_CMNT_DEFVAL  0x0UL
+
+#define XLPD_SLCR_APU_BRDC_INNER_SHIFT   1UL
+#define XLPD_SLCR_APU_BRDC_INNER_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_INNER_MASK    0x00000002UL
+#define XLPD_SLCR_APU_BRDC_INNER_DEFVAL  0x0UL
+
+#define XLPD_SLCR_APU_BRDC_OUTER_SHIFT   0UL
+#define XLPD_SLCR_APU_BRDC_OUTER_WIDTH   1UL
+#define XLPD_SLCR_APU_BRDC_OUTER_MASK    0x00000001UL
+#define XLPD_SLCR_APU_BRDC_OUTER_DEFVAL  0x1UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_SLCR_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr_secure.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr_secure.h
new file mode 100644
index 000000000..aff3bf2fa
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_slcr_secure.h
@@ -0,0 +1,141 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_SLCR_SECURE_H__
+#define __XLPD_SLCR_SECURE_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdSlcrSecure Base Address
+ */
+#define XLPD_SLCR_SECURE_BASEADDR      0xFF4B0000UL
+
+/**
+ * Register: XlpdSlcrSecCtrl
+ */
+#define XLPD_SLCR_SEC_CTRL    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000004UL )
+#define XLPD_SLCR_SEC_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_SHIFT   0UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_WIDTH   1UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_CTRL_SLVERR_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecIsr
+ */
+#define XLPD_SLCR_SEC_ISR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000008UL )
+#define XLPD_SLCR_SEC_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_ISR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecImr
+ */
+#define XLPD_SLCR_SEC_IMR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x0000000CUL )
+#define XLPD_SLCR_SEC_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IMR_ADDR_DECD_ERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdSlcrSecIer
+ */
+#define XLPD_SLCR_SEC_IER    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000010UL )
+#define XLPD_SLCR_SEC_IER_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IER_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecIdr
+ */
+#define XLPD_SLCR_SEC_IDR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000014UL )
+#define XLPD_SLCR_SEC_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_IDR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecItr
+ */
+#define XLPD_SLCR_SEC_ITR    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000018UL )
+#define XLPD_SLCR_SEC_ITR_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_SHIFT   0UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_WIDTH   1UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_ITR_ADDR_DECD_ERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecRpu
+ */
+#define XLPD_SLCR_SEC_RPU    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000020UL )
+#define XLPD_SLCR_SEC_RPU_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_SHIFT   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_WIDTH   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_MASK    0x00000002UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_1_DEFVAL  0x0UL
+
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_SHIFT   0UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_WIDTH   1UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_RPU_TZ_R5_0_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecAdma
+ */
+#define XLPD_SLCR_SEC_ADMA    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000024UL )
+#define XLPD_SLCR_SEC_ADMA_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_ADMA_TZ_SHIFT   0UL
+#define XLPD_SLCR_SEC_ADMA_TZ_WIDTH   8UL
+#define XLPD_SLCR_SEC_ADMA_TZ_MASK    0x000000ffUL
+#define XLPD_SLCR_SEC_ADMA_TZ_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecSafetyChk
+ */
+#define XLPD_SLCR_SEC_SAFETY_CHK    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000030UL )
+#define XLPD_SLCR_SEC_SAFETY_CHK_RSTVAL   0x00000000UL
+
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_SHIFT   0UL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_WIDTH   32UL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_MASK    0xffffffffUL
+#define XLPD_SLCR_SEC_SAFETY_CHK_VAL_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdSlcrSecUsb
+ */
+#define XLPD_SLCR_SEC_USB    ( ( XLPD_SLCR_SECURE_BASEADDR ) + 0x00000034UL )
+#define XLPD_SLCR_SEC_USB_RSTVAL   0x00000003UL
+
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_SHIFT   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_WIDTH   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_MASK    0x00000002UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_1_DEFVAL  0x1UL
+
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_SHIFT   0UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_WIDTH   1UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_MASK    0x00000001UL
+#define XLPD_SLCR_SEC_USB_TZ_USB3_0_DEFVAL  0x1UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_SLCR_SECURE_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu.h
new file mode 100644
index 000000000..a5145eac7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu.h
@@ -0,0 +1,858 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_XPPU_H__
+#define __XLPD_XPPU_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdXppu Base Address
+ */
+#define XLPD_XPPU_BASEADDR      0xFF980000UL
+
+/**
+ * Register: XlpdXppuCtrl
+ */
+#define XLPD_XPPU_CTRL    ( ( XLPD_XPPU_BASEADDR ) + 0x00000000UL )
+#define XLPD_XPPU_CTRL_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_SHIFT   2UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_MASK    0x00000004UL
+#define XLPD_XPPU_CTRL_APER_PARITY_EN_DEFVAL  0x0UL
+
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_SHIFT   1UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_MASK    0x00000002UL
+#define XLPD_XPPU_CTRL_MID_PARITY_EN_DEFVAL  0x0UL
+
+#define XLPD_XPPU_CTRL_EN_SHIFT   0UL
+#define XLPD_XPPU_CTRL_EN_WIDTH   1UL
+#define XLPD_XPPU_CTRL_EN_MASK    0x00000001UL
+#define XLPD_XPPU_CTRL_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuErrSts1
+ */
+#define XLPD_XPPU_ERR_STS1    ( ( XLPD_XPPU_BASEADDR ) + 0x00000004UL )
+#define XLPD_XPPU_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuErrSts2
+ */
+#define XLPD_XPPU_ERR_STS2    ( ( XLPD_XPPU_BASEADDR ) + 0x00000008UL )
+#define XLPD_XPPU_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XLPD_XPPU_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuPoison
+ */
+#define XLPD_XPPU_POISON    ( ( XLPD_XPPU_BASEADDR ) + 0x0000000CUL )
+#define XLPD_XPPU_POISON_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_POISON_BASE_SHIFT   0UL
+#define XLPD_XPPU_POISON_BASE_WIDTH   20UL
+#define XLPD_XPPU_POISON_BASE_MASK    0x000fffffUL
+#define XLPD_XPPU_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuIsr
+ */
+#define XLPD_XPPU_ISR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000010UL )
+#define XLPD_XPPU_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_ISR_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_ISR_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_ISR_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_ISR_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_ISR_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_ISR_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_ISR_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_ISR_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_ISR_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_ISR_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_ISR_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_ISR_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_ISR_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_ISR_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_ISR_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_ISR_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_ISR_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_ISR_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuImr
+ */
+#define XLPD_XPPU_IMR    ( ( XLPD_XPPU_BASEADDR ) + 0x00000014UL )
+#define XLPD_XPPU_IMR_RSTVAL   0x000000efUL
+
+#define XLPD_XPPU_IMR_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IMR_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IMR_APER_PARITY_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IMR_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IMR_APER_TZ_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IMR_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IMR_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IMR_APER_PERM_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IMR_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IMR_MID_PARITY_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IMR_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IMR_MID_RO_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IMR_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IMR_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IMR_MID_MISS_DEFVAL  0x1UL
+
+#define XLPD_XPPU_IMR_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IMR_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IMR_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuIen
+ */
+#define XLPD_XPPU_IEN    ( ( XLPD_XPPU_BASEADDR ) + 0x00000018UL )
+#define XLPD_XPPU_IEN_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_IEN_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IEN_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IEN_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IEN_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IEN_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IEN_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IEN_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IEN_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IEN_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IEN_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IEN_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IEN_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IEN_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IEN_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IEN_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IEN_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IEN_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IEN_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuIds
+ */
+#define XLPD_XPPU_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000001CUL )
+#define XLPD_XPPU_IDS_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_IDS_APER_PARITY_SHIFT   7UL
+#define XLPD_XPPU_IDS_APER_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_PARITY_MASK    0x00000080UL
+#define XLPD_XPPU_IDS_APER_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_APER_TZ_SHIFT   6UL
+#define XLPD_XPPU_IDS_APER_TZ_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_TZ_MASK    0x00000040UL
+#define XLPD_XPPU_IDS_APER_TZ_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_APER_PERM_SHIFT   5UL
+#define XLPD_XPPU_IDS_APER_PERM_WIDTH   1UL
+#define XLPD_XPPU_IDS_APER_PERM_MASK    0x00000020UL
+#define XLPD_XPPU_IDS_APER_PERM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_PARITY_SHIFT   3UL
+#define XLPD_XPPU_IDS_MID_PARITY_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_PARITY_MASK    0x00000008UL
+#define XLPD_XPPU_IDS_MID_PARITY_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_RO_SHIFT   2UL
+#define XLPD_XPPU_IDS_MID_RO_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_RO_MASK    0x00000004UL
+#define XLPD_XPPU_IDS_MID_RO_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_MID_MISS_SHIFT   1UL
+#define XLPD_XPPU_IDS_MID_MISS_WIDTH   1UL
+#define XLPD_XPPU_IDS_MID_MISS_MASK    0x00000002UL
+#define XLPD_XPPU_IDS_MID_MISS_DEFVAL  0x0UL
+
+#define XLPD_XPPU_IDS_INV_APB_SHIFT   0UL
+#define XLPD_XPPU_IDS_INV_APB_WIDTH   1UL
+#define XLPD_XPPU_IDS_INV_APB_MASK    0x00000001UL
+#define XLPD_XPPU_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMMstrIds
+ */
+#define XLPD_XPPU_M_MSTR_IDS    ( ( XLPD_XPPU_BASEADDR ) + 0x0000003CUL )
+#define XLPD_XPPU_M_MSTR_IDS_RSTVAL   0x00000014UL
+
+#define XLPD_XPPU_M_MSTR_IDS_NO_SHIFT   0UL
+#define XLPD_XPPU_M_MSTR_IDS_NO_WIDTH   32UL
+#define XLPD_XPPU_M_MSTR_IDS_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_MSTR_IDS_NO_DEFVAL  0x14UL
+
+/**
+ * Register: XlpdXppuMAperture32b
+ */
+#define XLPD_XPPU_M_APERTURE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000040UL )
+#define XLPD_XPPU_M_APERTURE_32B_RSTVAL   0x00000080UL
+
+#define XLPD_XPPU_M_APERTURE_32B_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_32B_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_32B_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_32B_NO_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMAperture64kb
+ */
+#define XLPD_XPPU_M_APERTURE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000044UL )
+#define XLPD_XPPU_M_APERTURE_64KB_RSTVAL   0x00000100UL
+
+#define XLPD_XPPU_M_APERTURE_64KB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_64KB_NO_DEFVAL  0x100UL
+
+/**
+ * Register: XlpdXppuMAperture1mb
+ */
+#define XLPD_XPPU_M_APERTURE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000048UL )
+#define XLPD_XPPU_M_APERTURE_1MB_RSTVAL   0x00000010UL
+
+#define XLPD_XPPU_M_APERTURE_1MB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_1MB_NO_DEFVAL  0x10UL
+
+/**
+ * Register: XlpdXppuMAperture512mb
+ */
+#define XLPD_XPPU_M_APERTURE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000004CUL )
+#define XLPD_XPPU_M_APERTURE_512MB_RSTVAL   0x00000001UL
+
+#define XLPD_XPPU_M_APERTURE_512MB_NO_SHIFT   0UL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_WIDTH   32UL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_MASK    0xffffffffUL
+#define XLPD_XPPU_M_APERTURE_512MB_NO_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuBase32b
+ */
+#define XLPD_XPPU_BASE_32B    ( ( XLPD_XPPU_BASEADDR ) + 0x00000050UL )
+#define XLPD_XPPU_BASE_32B_RSTVAL   0xff990000UL
+
+#define XLPD_XPPU_BASE_32B_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_32B_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_32B_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_32B_ADDR_DEFVAL  0xff990000UL
+
+/**
+ * Register: XlpdXppuBase64kb
+ */
+#define XLPD_XPPU_BASE_64KB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000054UL )
+#define XLPD_XPPU_BASE_64KB_RSTVAL   0xff000000UL
+
+#define XLPD_XPPU_BASE_64KB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_64KB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_64KB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_64KB_ADDR_DEFVAL  0xff000000UL
+
+/**
+ * Register: XlpdXppuBase1mb
+ */
+#define XLPD_XPPU_BASE_1MB    ( ( XLPD_XPPU_BASEADDR ) + 0x00000058UL )
+#define XLPD_XPPU_BASE_1MB_RSTVAL   0xfe000000UL
+
+#define XLPD_XPPU_BASE_1MB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_1MB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_1MB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_1MB_ADDR_DEFVAL  0xfe000000UL
+
+/**
+ * Register: XlpdXppuBase512mb
+ */
+#define XLPD_XPPU_BASE_512MB    ( ( XLPD_XPPU_BASEADDR ) + 0x0000005CUL )
+#define XLPD_XPPU_BASE_512MB_RSTVAL   0xc0000000UL
+
+#define XLPD_XPPU_BASE_512MB_ADDR_SHIFT   0UL
+#define XLPD_XPPU_BASE_512MB_ADDR_WIDTH   32UL
+#define XLPD_XPPU_BASE_512MB_ADDR_MASK    0xffffffffUL
+#define XLPD_XPPU_BASE_512MB_ADDR_DEFVAL  0xc0000000UL
+
+/**
+ * Register: XlpdXppuMstrId00
+ */
+#define XLPD_XPPU_MSTR_ID00    ( ( XLPD_XPPU_BASEADDR ) + 0x00000100UL )
+#define XLPD_XPPU_MSTR_ID00_RSTVAL   0x83ff0040UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID00_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID00_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID00_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID00_MIDM_DEFVAL  0x3ffUL
+
+#define XLPD_XPPU_MSTR_ID00_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID00_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID00_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID00_MID_DEFVAL  0x40UL
+
+/**
+ * Register: XlpdXppuMstrId01
+ */
+#define XLPD_XPPU_MSTR_ID01    ( ( XLPD_XPPU_BASEADDR ) + 0x00000104UL )
+#define XLPD_XPPU_MSTR_ID01_RSTVAL   0x03f00000UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID01_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID01_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID01_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID01_MIDM_DEFVAL  0x3f0UL
+
+#define XLPD_XPPU_MSTR_ID01_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID01_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID01_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID01_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId02
+ */
+#define XLPD_XPPU_MSTR_ID02    ( ( XLPD_XPPU_BASEADDR ) + 0x00000108UL )
+#define XLPD_XPPU_MSTR_ID02_RSTVAL   0x83f00010UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID02_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID02_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID02_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID02_MIDM_DEFVAL  0x3f0UL
+
+#define XLPD_XPPU_MSTR_ID02_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID02_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID02_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID02_MID_DEFVAL  0x10UL
+
+/**
+ * Register: XlpdXppuMstrId03
+ */
+#define XLPD_XPPU_MSTR_ID03    ( ( XLPD_XPPU_BASEADDR ) + 0x0000010CUL )
+#define XLPD_XPPU_MSTR_ID03_RSTVAL   0x83c00080UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID03_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID03_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID03_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID03_MIDM_DEFVAL  0x3c0UL
+
+#define XLPD_XPPU_MSTR_ID03_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID03_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID03_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID03_MID_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMstrId04
+ */
+#define XLPD_XPPU_MSTR_ID04    ( ( XLPD_XPPU_BASEADDR ) + 0x00000110UL )
+#define XLPD_XPPU_MSTR_ID04_RSTVAL   0x83c30080UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID04_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID04_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID04_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID04_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID04_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID04_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID04_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID04_MID_DEFVAL  0x80UL
+
+/**
+ * Register: XlpdXppuMstrId05
+ */
+#define XLPD_XPPU_MSTR_ID05    ( ( XLPD_XPPU_BASEADDR ) + 0x00000114UL )
+#define XLPD_XPPU_MSTR_ID05_RSTVAL   0x03c30081UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID05_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID05_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID05_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID05_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID05_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID05_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID05_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID05_MID_DEFVAL  0x81UL
+
+/**
+ * Register: XlpdXppuMstrId06
+ */
+#define XLPD_XPPU_MSTR_ID06    ( ( XLPD_XPPU_BASEADDR ) + 0x00000118UL )
+#define XLPD_XPPU_MSTR_ID06_RSTVAL   0x03c30082UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID06_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID06_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID06_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID06_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID06_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID06_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID06_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID06_MID_DEFVAL  0x82UL
+
+/**
+ * Register: XlpdXppuMstrId07
+ */
+#define XLPD_XPPU_MSTR_ID07    ( ( XLPD_XPPU_BASEADDR ) + 0x0000011CUL )
+#define XLPD_XPPU_MSTR_ID07_RSTVAL   0x83c30083UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID07_MIDP_DEFVAL  0x1UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID07_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID07_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID07_MIDM_DEFVAL  0x3c3UL
+
+#define XLPD_XPPU_MSTR_ID07_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID07_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID07_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID07_MID_DEFVAL  0x83UL
+
+/**
+ * Register: XlpdXppuMstrId08
+ */
+#define XLPD_XPPU_MSTR_ID08    ( ( XLPD_XPPU_BASEADDR ) + 0x00000120UL )
+#define XLPD_XPPU_MSTR_ID08_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID08_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID08_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID08_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID08_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID08_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID08_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID08_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId09
+ */
+#define XLPD_XPPU_MSTR_ID09    ( ( XLPD_XPPU_BASEADDR ) + 0x00000124UL )
+#define XLPD_XPPU_MSTR_ID09_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID09_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID09_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID09_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID09_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID09_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID09_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID09_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId10
+ */
+#define XLPD_XPPU_MSTR_ID10    ( ( XLPD_XPPU_BASEADDR ) + 0x00000128UL )
+#define XLPD_XPPU_MSTR_ID10_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID10_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID10_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID10_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID10_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID10_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID10_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID10_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId11
+ */
+#define XLPD_XPPU_MSTR_ID11    ( ( XLPD_XPPU_BASEADDR ) + 0x0000012CUL )
+#define XLPD_XPPU_MSTR_ID11_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID11_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID11_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID11_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID11_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID11_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID11_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID11_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId12
+ */
+#define XLPD_XPPU_MSTR_ID12    ( ( XLPD_XPPU_BASEADDR ) + 0x00000130UL )
+#define XLPD_XPPU_MSTR_ID12_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID12_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID12_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID12_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID12_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID12_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID12_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID12_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId13
+ */
+#define XLPD_XPPU_MSTR_ID13    ( ( XLPD_XPPU_BASEADDR ) + 0x00000134UL )
+#define XLPD_XPPU_MSTR_ID13_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID13_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID13_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID13_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID13_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID13_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID13_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID13_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId14
+ */
+#define XLPD_XPPU_MSTR_ID14    ( ( XLPD_XPPU_BASEADDR ) + 0x00000138UL )
+#define XLPD_XPPU_MSTR_ID14_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID14_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID14_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID14_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID14_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID14_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID14_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID14_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId15
+ */
+#define XLPD_XPPU_MSTR_ID15    ( ( XLPD_XPPU_BASEADDR ) + 0x0000013CUL )
+#define XLPD_XPPU_MSTR_ID15_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID15_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID15_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID15_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID15_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID15_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID15_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID15_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId16
+ */
+#define XLPD_XPPU_MSTR_ID16    ( ( XLPD_XPPU_BASEADDR ) + 0x00000140UL )
+#define XLPD_XPPU_MSTR_ID16_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID16_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID16_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID16_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID16_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID16_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID16_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID16_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId17
+ */
+#define XLPD_XPPU_MSTR_ID17    ( ( XLPD_XPPU_BASEADDR ) + 0x00000144UL )
+#define XLPD_XPPU_MSTR_ID17_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID17_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID17_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID17_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID17_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID17_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID17_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID17_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId18
+ */
+#define XLPD_XPPU_MSTR_ID18    ( ( XLPD_XPPU_BASEADDR ) + 0x00000148UL )
+#define XLPD_XPPU_MSTR_ID18_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID18_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID18_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID18_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID18_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID18_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID18_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID18_MID_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuMstrId19
+ */
+#define XLPD_XPPU_MSTR_ID19    ( ( XLPD_XPPU_BASEADDR ) + 0x0000014CUL )
+#define XLPD_XPPU_MSTR_ID19_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDP_SHIFT   31UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_MASK    0x80000000UL
+#define XLPD_XPPU_MSTR_ID19_MIDP_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDR_SHIFT   30UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_WIDTH   1UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_MASK    0x40000000UL
+#define XLPD_XPPU_MSTR_ID19_MIDR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MIDM_SHIFT   16UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_MASK    0x03ff0000UL
+#define XLPD_XPPU_MSTR_ID19_MIDM_DEFVAL  0x0UL
+
+#define XLPD_XPPU_MSTR_ID19_MID_SHIFT   0UL
+#define XLPD_XPPU_MSTR_ID19_MID_WIDTH   10UL
+#define XLPD_XPPU_MSTR_ID19_MID_MASK    0x000003ffUL
+#define XLPD_XPPU_MSTR_ID19_MID_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_XPPU_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu_sink.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu_sink.h
new file mode 100644
index 000000000..95f7e20a2
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xlpd_xppu_sink.h
@@ -0,0 +1,81 @@
+/* ### HEADER ### */
+
+#ifndef __XLPD_XPPU_SINK_H__
+#define __XLPD_XPPU_SINK_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XlpdXppuSink Base Address
+ */
+#define XLPD_XPPU_SINK_BASEADDR      0xFF9C0000UL
+
+/**
+ * Register: XlpdXppuSinkErrSts
+ */
+#define XLPD_XPPU_SINK_ERR_STS    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF00UL )
+#define XLPD_XPPU_SINK_ERR_STS_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_SHIFT   31UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_WIDTH   1UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_MASK    0x80000000UL
+#define XLPD_XPPU_SINK_ERR_STS_RDWR_DEFVAL  0x0UL
+
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_SHIFT   0UL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_WIDTH   12UL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_MASK    0x00000fffUL
+#define XLPD_XPPU_SINK_ERR_STS_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkIsr
+ */
+#define XLPD_XPPU_SINK_ISR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF10UL )
+#define XLPD_XPPU_SINK_ISR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_ISRADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkImr
+ */
+#define XLPD_XPPU_SINK_IMR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF14UL )
+#define XLPD_XPPU_SINK_IMR_RSTVAL   0x00000001UL
+
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IMRADDRDECDERR_DEFVAL  0x1UL
+
+/**
+ * Register: XlpdXppuSinkIer
+ */
+#define XLPD_XPPU_SINK_IER    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF18UL )
+#define XLPD_XPPU_SINK_IER_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_IERADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IERADDRDECDERR_DEFVAL  0x0UL
+
+/**
+ * Register: XlpdXppuSinkIdr
+ */
+#define XLPD_XPPU_SINK_IDR    ( ( XLPD_XPPU_SINK_BASEADDR ) + 0x0000FF1CUL )
+#define XLPD_XPPU_SINK_IDR_RSTVAL   0x00000000UL
+
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_SHIFT   0UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_WIDTH   1UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_MASK    0x00000001UL
+#define XLPD_XPPU_SINK_IDRADDRDECDERR_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XLPD_XPPU_SINK_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xocm_xmpu_cfg.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xocm_xmpu_cfg.h
new file mode 100644
index 000000000..5e3631f3e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/includes_ps/xocm_xmpu_cfg.h
@@ -0,0 +1,1304 @@
+/* ### HEADER ### */
+
+#ifndef __XOCM_XMPU_CFG_H__
+#define __XOCM_XMPU_CFG_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * XocmXmpuCfg Base Address
+ */
+#define XOCM_XMPU_CFG_BASEADDR      0xFFA70000UL
+
+/**
+ * Register: XocmXmpuCfgCtrl
+ */
+#define XOCM_XMPU_CFG_CTRL    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000000UL )
+#define XOCM_XMPU_CFG_CTRL_RSTVAL   0x00000003UL
+
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_SHIFT   3UL
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_CTRL_ALIGNCFG_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_SHIFT   2UL
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_CTRL_POISONCFG_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_CTRL_DEFWRALWD_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_SHIFT   0UL
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_CTRL_DEFRDALWD_DEFVAL  0x1UL
+
+/**
+ * Register: XocmXmpuCfgErrSts1
+ */
+#define XOCM_XMPU_CFG_ERR_STS1    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000004UL )
+#define XOCM_XMPU_CFG_ERR_STS1_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_WIDTH   32UL
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_MASK    0xffffffffUL
+#define XOCM_XMPU_CFG_ERR_STS1_AXI_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgErrSts2
+ */
+#define XOCM_XMPU_CFG_ERR_STS2    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000008UL )
+#define XOCM_XMPU_CFG_ERR_STS2_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_ERR_STS2_AXI_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgPoison
+ */
+#define XOCM_XMPU_CFG_POISON    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000000CUL )
+#define XOCM_XMPU_CFG_POISON_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_POISON_ATTRIB_SHIFT   20UL
+#define XOCM_XMPU_CFG_POISON_ATTRIB_WIDTH   12UL
+#define XOCM_XMPU_CFG_POISON_ATTRIB_MASK    0xfff00000UL
+#define XOCM_XMPU_CFG_POISON_ATTRIB_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_POISON_BASE_SHIFT   0UL
+#define XOCM_XMPU_CFG_POISON_BASE_WIDTH   20UL
+#define XOCM_XMPU_CFG_POISON_BASE_MASK    0x000fffffUL
+#define XOCM_XMPU_CFG_POISON_BASE_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgIsr
+ */
+#define XOCM_XMPU_CFG_ISR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000010UL )
+#define XOCM_XMPU_CFG_ISR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_ISR_SECURTYVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_ISR_WRPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_ISR_RDPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_ISR_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_ISR_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_ISR_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_ISR_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgImr
+ */
+#define XOCM_XMPU_CFG_IMR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000014UL )
+#define XOCM_XMPU_CFG_IMR_RSTVAL   0x0000000fUL
+
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_IMR_SECURTYVIO_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_IMR_WRPERMVIO_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_IMR_RDPERMVIO_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_IMR_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_IMR_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_IMR_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_IMR_INV_APB_DEFVAL  0x1UL
+
+/**
+ * Register: XocmXmpuCfgIen
+ */
+#define XOCM_XMPU_CFG_IEN    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000018UL )
+#define XOCM_XMPU_CFG_IEN_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_IEN_SECURTYVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_IEN_WRPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_IEN_RDPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IEN_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_IEN_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_IEN_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_IEN_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgIds
+ */
+#define XOCM_XMPU_CFG_IDS    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000001CUL )
+#define XOCM_XMPU_CFG_IDS_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_SHIFT   3UL
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_IDS_SECURTYVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_SHIFT   2UL
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_IDS_WRPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_SHIFT   1UL
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_IDS_RDPERMVIO_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_IDS_INV_APB_SHIFT   0UL
+#define XOCM_XMPU_CFG_IDS_INV_APB_WIDTH   1UL
+#define XOCM_XMPU_CFG_IDS_INV_APB_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_IDS_INV_APB_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgLock
+ */
+#define XOCM_XMPU_CFG_LOCK    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000020UL )
+#define XOCM_XMPU_CFG_LOCK_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_SHIFT   0UL
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_WIDTH   1UL
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_LOCK_REGWRDIS_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00Strt
+ */
+#define XOCM_XMPU_CFG_R00_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000100UL )
+#define XOCM_XMPU_CFG_R00_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R00_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00End
+ */
+#define XOCM_XMPU_CFG_R00_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000104UL )
+#define XOCM_XMPU_CFG_R00_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R00_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R00_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R00_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00Mstr
+ */
+#define XOCM_XMPU_CFG_R00_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000108UL )
+#define XOCM_XMPU_CFG_R00_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R00_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R00_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R00_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR00
+ */
+#define XOCM_XMPU_CFG_R00    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000010CUL )
+#define XOCM_XMPU_CFG_R00_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R00_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R00_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R00_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R00_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R00_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R00_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R00_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R00_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R00_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R00_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R00_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R00_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01Strt
+ */
+#define XOCM_XMPU_CFG_R01_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000110UL )
+#define XOCM_XMPU_CFG_R01_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R01_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01End
+ */
+#define XOCM_XMPU_CFG_R01_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000114UL )
+#define XOCM_XMPU_CFG_R01_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R01_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R01_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R01_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01Mstr
+ */
+#define XOCM_XMPU_CFG_R01_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000118UL )
+#define XOCM_XMPU_CFG_R01_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R01_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R01_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R01_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR01
+ */
+#define XOCM_XMPU_CFG_R01    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000011CUL )
+#define XOCM_XMPU_CFG_R01_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R01_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R01_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R01_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R01_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R01_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R01_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R01_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R01_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R01_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R01_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R01_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R01_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02Strt
+ */
+#define XOCM_XMPU_CFG_R02_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000120UL )
+#define XOCM_XMPU_CFG_R02_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R02_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02End
+ */
+#define XOCM_XMPU_CFG_R02_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000124UL )
+#define XOCM_XMPU_CFG_R02_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R02_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R02_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R02_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02Mstr
+ */
+#define XOCM_XMPU_CFG_R02_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000128UL )
+#define XOCM_XMPU_CFG_R02_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R02_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R02_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R02_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR02
+ */
+#define XOCM_XMPU_CFG_R02    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000012CUL )
+#define XOCM_XMPU_CFG_R02_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R02_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R02_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R02_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R02_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R02_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R02_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R02_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R02_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R02_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R02_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R02_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R02_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03Strt
+ */
+#define XOCM_XMPU_CFG_R03_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000130UL )
+#define XOCM_XMPU_CFG_R03_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R03_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03End
+ */
+#define XOCM_XMPU_CFG_R03_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000134UL )
+#define XOCM_XMPU_CFG_R03_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R03_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R03_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R03_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03Mstr
+ */
+#define XOCM_XMPU_CFG_R03_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000138UL )
+#define XOCM_XMPU_CFG_R03_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R03_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R03_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R03_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR03
+ */
+#define XOCM_XMPU_CFG_R03    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000013CUL )
+#define XOCM_XMPU_CFG_R03_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R03_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R03_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R03_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R03_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R03_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R03_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R03_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R03_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R03_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R03_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R03_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R03_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04Strt
+ */
+#define XOCM_XMPU_CFG_R04_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000140UL )
+#define XOCM_XMPU_CFG_R04_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R04_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04End
+ */
+#define XOCM_XMPU_CFG_R04_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000144UL )
+#define XOCM_XMPU_CFG_R04_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R04_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R04_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R04_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04Mstr
+ */
+#define XOCM_XMPU_CFG_R04_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000148UL )
+#define XOCM_XMPU_CFG_R04_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R04_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R04_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R04_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR04
+ */
+#define XOCM_XMPU_CFG_R04    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000014CUL )
+#define XOCM_XMPU_CFG_R04_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R04_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R04_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R04_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R04_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R04_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R04_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R04_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R04_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R04_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R04_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R04_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R04_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05Strt
+ */
+#define XOCM_XMPU_CFG_R05_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000150UL )
+#define XOCM_XMPU_CFG_R05_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R05_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05End
+ */
+#define XOCM_XMPU_CFG_R05_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000154UL )
+#define XOCM_XMPU_CFG_R05_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R05_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R05_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R05_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05Mstr
+ */
+#define XOCM_XMPU_CFG_R05_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000158UL )
+#define XOCM_XMPU_CFG_R05_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R05_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R05_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R05_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR05
+ */
+#define XOCM_XMPU_CFG_R05    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000015CUL )
+#define XOCM_XMPU_CFG_R05_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R05_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R05_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R05_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R05_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R05_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R05_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R05_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R05_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R05_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R05_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R05_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R05_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06Strt
+ */
+#define XOCM_XMPU_CFG_R06_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000160UL )
+#define XOCM_XMPU_CFG_R06_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R06_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06End
+ */
+#define XOCM_XMPU_CFG_R06_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000164UL )
+#define XOCM_XMPU_CFG_R06_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R06_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R06_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R06_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06Mstr
+ */
+#define XOCM_XMPU_CFG_R06_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000168UL )
+#define XOCM_XMPU_CFG_R06_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R06_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R06_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R06_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR06
+ */
+#define XOCM_XMPU_CFG_R06    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000016CUL )
+#define XOCM_XMPU_CFG_R06_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R06_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R06_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R06_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R06_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R06_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R06_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R06_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R06_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R06_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R06_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R06_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R06_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07Strt
+ */
+#define XOCM_XMPU_CFG_R07_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000170UL )
+#define XOCM_XMPU_CFG_R07_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R07_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07End
+ */
+#define XOCM_XMPU_CFG_R07_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000174UL )
+#define XOCM_XMPU_CFG_R07_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R07_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R07_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R07_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07Mstr
+ */
+#define XOCM_XMPU_CFG_R07_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000178UL )
+#define XOCM_XMPU_CFG_R07_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R07_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R07_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R07_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR07
+ */
+#define XOCM_XMPU_CFG_R07    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000017CUL )
+#define XOCM_XMPU_CFG_R07_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R07_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R07_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R07_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R07_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R07_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R07_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R07_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R07_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R07_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R07_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R07_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R07_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08Strt
+ */
+#define XOCM_XMPU_CFG_R08_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000180UL )
+#define XOCM_XMPU_CFG_R08_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R08_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08End
+ */
+#define XOCM_XMPU_CFG_R08_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000184UL )
+#define XOCM_XMPU_CFG_R08_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R08_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R08_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R08_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08Mstr
+ */
+#define XOCM_XMPU_CFG_R08_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000188UL )
+#define XOCM_XMPU_CFG_R08_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R08_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R08_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R08_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR08
+ */
+#define XOCM_XMPU_CFG_R08    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000018CUL )
+#define XOCM_XMPU_CFG_R08_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R08_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R08_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R08_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R08_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R08_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R08_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R08_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R08_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R08_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R08_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R08_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R08_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09Strt
+ */
+#define XOCM_XMPU_CFG_R09_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000190UL )
+#define XOCM_XMPU_CFG_R09_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R09_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09End
+ */
+#define XOCM_XMPU_CFG_R09_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000194UL )
+#define XOCM_XMPU_CFG_R09_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R09_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R09_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R09_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09Mstr
+ */
+#define XOCM_XMPU_CFG_R09_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x00000198UL )
+#define XOCM_XMPU_CFG_R09_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R09_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R09_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R09_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR09
+ */
+#define XOCM_XMPU_CFG_R09    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x0000019CUL )
+#define XOCM_XMPU_CFG_R09_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R09_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R09_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R09_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R09_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R09_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R09_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R09_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R09_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R09_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R09_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R09_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R09_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10Strt
+ */
+#define XOCM_XMPU_CFG_R10_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A0UL )
+#define XOCM_XMPU_CFG_R10_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R10_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10End
+ */
+#define XOCM_XMPU_CFG_R10_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A4UL )
+#define XOCM_XMPU_CFG_R10_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R10_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R10_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R10_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10Mstr
+ */
+#define XOCM_XMPU_CFG_R10_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001A8UL )
+#define XOCM_XMPU_CFG_R10_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R10_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R10_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R10_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR10
+ */
+#define XOCM_XMPU_CFG_R10    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ACUL )
+#define XOCM_XMPU_CFG_R10_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R10_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R10_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R10_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R10_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R10_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R10_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R10_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R10_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R10_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R10_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R10_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R10_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11Strt
+ */
+#define XOCM_XMPU_CFG_R11_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B0UL )
+#define XOCM_XMPU_CFG_R11_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R11_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11End
+ */
+#define XOCM_XMPU_CFG_R11_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B4UL )
+#define XOCM_XMPU_CFG_R11_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R11_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R11_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R11_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11Mstr
+ */
+#define XOCM_XMPU_CFG_R11_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001B8UL )
+#define XOCM_XMPU_CFG_R11_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R11_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R11_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R11_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR11
+ */
+#define XOCM_XMPU_CFG_R11    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001BCUL )
+#define XOCM_XMPU_CFG_R11_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R11_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R11_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R11_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R11_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R11_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R11_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R11_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R11_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R11_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R11_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R11_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R11_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12Strt
+ */
+#define XOCM_XMPU_CFG_R12_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C0UL )
+#define XOCM_XMPU_CFG_R12_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R12_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12End
+ */
+#define XOCM_XMPU_CFG_R12_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C4UL )
+#define XOCM_XMPU_CFG_R12_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R12_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R12_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R12_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12Mstr
+ */
+#define XOCM_XMPU_CFG_R12_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001C8UL )
+#define XOCM_XMPU_CFG_R12_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R12_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R12_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R12_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR12
+ */
+#define XOCM_XMPU_CFG_R12    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001CCUL )
+#define XOCM_XMPU_CFG_R12_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R12_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R12_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R12_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R12_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R12_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R12_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R12_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R12_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R12_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R12_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R12_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R12_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13Strt
+ */
+#define XOCM_XMPU_CFG_R13_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D0UL )
+#define XOCM_XMPU_CFG_R13_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R13_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13End
+ */
+#define XOCM_XMPU_CFG_R13_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D4UL )
+#define XOCM_XMPU_CFG_R13_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R13_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R13_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R13_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13Mstr
+ */
+#define XOCM_XMPU_CFG_R13_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001D8UL )
+#define XOCM_XMPU_CFG_R13_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R13_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R13_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R13_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR13
+ */
+#define XOCM_XMPU_CFG_R13    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001DCUL )
+#define XOCM_XMPU_CFG_R13_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R13_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R13_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R13_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R13_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R13_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R13_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R13_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R13_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R13_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R13_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R13_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R13_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14Strt
+ */
+#define XOCM_XMPU_CFG_R14_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E0UL )
+#define XOCM_XMPU_CFG_R14_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R14_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14End
+ */
+#define XOCM_XMPU_CFG_R14_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E4UL )
+#define XOCM_XMPU_CFG_R14_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R14_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R14_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R14_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14Mstr
+ */
+#define XOCM_XMPU_CFG_R14_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001E8UL )
+#define XOCM_XMPU_CFG_R14_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R14_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R14_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R14_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR14
+ */
+#define XOCM_XMPU_CFG_R14    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001ECUL )
+#define XOCM_XMPU_CFG_R14_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R14_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R14_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R14_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R14_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R14_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R14_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R14_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R14_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R14_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R14_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R14_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R14_EN_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15Strt
+ */
+#define XOCM_XMPU_CFG_R15_STRT    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F0UL )
+#define XOCM_XMPU_CFG_R15_STRT_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R15_STRT_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15End
+ */
+#define XOCM_XMPU_CFG_R15_END    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F4UL )
+#define XOCM_XMPU_CFG_R15_END_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R15_END_ADDR_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_END_ADDR_WIDTH   28UL
+#define XOCM_XMPU_CFG_R15_END_ADDR_MASK    0x0fffffffUL
+#define XOCM_XMPU_CFG_R15_END_ADDR_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15Mstr
+ */
+#define XOCM_XMPU_CFG_R15_MSTR    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001F8UL )
+#define XOCM_XMPU_CFG_R15_MSTR_RSTVAL   0x00000000UL
+
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_SHIFT   16UL
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_WIDTH   16UL
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_MASK    0xffff0000UL
+#define XOCM_XMPU_CFG_R15_MSTR_MSK_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_MSTR_ID_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_MSTR_ID_WIDTH   16UL
+#define XOCM_XMPU_CFG_R15_MSTR_ID_MASK    0x0000ffffUL
+#define XOCM_XMPU_CFG_R15_MSTR_ID_DEFVAL  0x0UL
+
+/**
+ * Register: XocmXmpuCfgR15
+ */
+#define XOCM_XMPU_CFG_R15    ( ( XOCM_XMPU_CFG_BASEADDR ) + 0x000001FCUL )
+#define XOCM_XMPU_CFG_R15_RSTVAL   0x00000008UL
+
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_SHIFT   4UL
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_MASK    0x00000010UL
+#define XOCM_XMPU_CFG_R15_NSCHKTYPE_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_REGNNS_SHIFT   3UL
+#define XOCM_XMPU_CFG_R15_REGNNS_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_REGNNS_MASK    0x00000008UL
+#define XOCM_XMPU_CFG_R15_REGNNS_DEFVAL  0x1UL
+
+#define XOCM_XMPU_CFG_R15_WRALWD_SHIFT   2UL
+#define XOCM_XMPU_CFG_R15_WRALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_WRALWD_MASK    0x00000004UL
+#define XOCM_XMPU_CFG_R15_WRALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_RDALWD_SHIFT   1UL
+#define XOCM_XMPU_CFG_R15_RDALWD_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_RDALWD_MASK    0x00000002UL
+#define XOCM_XMPU_CFG_R15_RDALWD_DEFVAL  0x0UL
+
+#define XOCM_XMPU_CFG_R15_EN_SHIFT   0UL
+#define XOCM_XMPU_CFG_R15_EN_WIDTH   1UL
+#define XOCM_XMPU_CFG_R15_EN_MASK    0x00000001UL
+#define XOCM_XMPU_CFG_R15_EN_DEFVAL  0x0UL
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __XOCM_XMPU_CFG_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/isatty.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/isatty.c
new file mode 100644
index 000000000..242d8faf3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/isatty.c
@@ -0,0 +1,56 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 _isatty(sint32 fd);
+}
+#endif
+
+/*
+ * isatty -- returns 1 if connected to a terminal device,
+ *           returns 0 if not. Since we're hooked up to a
+ *           serial port, we'll say yes _AND return a 1.
+ */
+__attribute__((weak)) sint32 isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
+
+__attribute__((weak)) sint32 _isatty(sint32 fd)
+{
+  (void)fd;
+  return (1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/kill.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/kill.c
new file mode 100644
index 000000000..1c67ace57
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/kill.c
@@ -0,0 +1,60 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _kill(s32 pid, s32 sig);
+}
+#endif
+
+/*
+ * kill -- go out via exit...
+ */
+
+__attribute__((weak)) s32 kill(s32 pid, s32 sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
+
+__attribute__((weak)) s32 _kill(s32 pid, s32 sig)
+{
+  if(pid == 1) {
+    _exit(sig);
+  }
+  return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/lseek.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/lseek.c
new file mode 100644
index 000000000..5cd5a2dd1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/lseek.c
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence);
+}
+#endif
+/*
+ * lseek --  Since a serial port is non-seekable, we return an error.
+ */
+__attribute__((weak)) off_t lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
+
+__attribute__((weak)) off_t _lseek(s32 fd, off_t offset, s32 whence)
+{
+  (void)fd;
+  (void)offset;
+  (void)whence;
+  errno = ESPIPE;
+  return ((off_t)-1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/mpu.c
new file mode 100644
index 000000000..bf5ddeefe
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/mpu.c
@@ -0,0 +1,283 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2016 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file mpu.c
+*
+* This file contains initial configuration of the MPU.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 5.04	pkp  12/18/15 Updated MPU initialization as per the proper address map
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xreg_cortexr5.h"
+#include "xil_mpu.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+static const struct {
+	u64 size;
+	unsigned int encoding;
+}region_size[] = {
+	{ 0x20, REGION_32B },
+	{ 0x40, REGION_64B },
+	{ 0x80, REGION_128B },
+	{ 0x100, REGION_256B },
+	{ 0x200, REGION_512B },
+	{ 0x400, REGION_1K },
+	{ 0x800, REGION_2K },
+	{ 0x1000, REGION_4K },
+	{ 0x2000, REGION_8K },
+	{ 0x4000, REGION_16K },
+	{ 0x8000, REGION_32K },
+	{ 0x10000, REGION_64K },
+	{ 0x20000, REGION_128K },
+	{ 0x40000, REGION_256K },
+	{ 0x80000, REGION_512K },
+	{ 0x100000, REGION_1M },
+	{ 0x200000, REGION_2M },
+	{ 0x400000, REGION_4M },
+	{ 0x800000, REGION_8M },
+	{ 0x1000000, REGION_16M },
+	{ 0x2000000, REGION_32M },
+	{ 0x4000000, REGION_64M },
+	{ 0x8000000, REGION_128M },
+	{ 0x10000000, REGION_256M },
+	{ 0x20000000, REGION_512M },
+	{ 0x40000000, REGION_1G },
+	{ 0x80000000, REGION_2G },
+	{ 0x100000000, REGION_4G },
+};
+
+/************************** Function Prototypes ******************************/
+void Init_MPU(void);
+static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
+static void Xil_DisableMPURegions(void);
+
+/*****************************************************************************
+*
+* Initialize MPU for a given address map and Enabled the background Region in
+* MPU with default memory attributes for rest of address range for Cortex R5
+* processor.
+*
+* @param	None.
+*
+* @return	None.
+*
+*
+******************************************************************************/
+
+void Init_MPU(void)
+{
+	u32 Addr;
+	u32 RegSize;
+	u32 Attrib;
+	u32 RegNum = 0, i;
+	u64 size;
+
+	Xil_DisableMPURegions();
+
+	Addr = 0x00000000U;
+#ifdef	XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR
+	/* If the DDR is present, configure region as per DDR size */
+	size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1;
+	if (size < 0x80000000) {
+		/* Lookup the size.  */
+		for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
+			if (size <= region_size[i].size) {
+				RegSize = region_size[i].encoding;
+				break;
+			}
+		}
+	} else {
+		/* if the DDR size is > 2GB, truncate it to 2GB */
+		RegSize = REGION_2G;
+	}
+#else
+	/* For DDRless system, configure region for TCM */
+	RegSize = REGION_256K;
+#endif
+	Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/*
+	 * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
+	 * 512 MB - LPD-PL interface
+	 * 256 MB - FPD-PL (HPM0) interface
+	 * 256 MB - FPD-PL (HPM1) interface
+	 */
+	Addr = 0x80000000;
+	RegSize = REGION_1G;
+	Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */
+	Addr = 0xC0000000U;
+	RegSize = REGION_512M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */
+	Addr = 0xE0000000U;
+	RegSize = REGION_256M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */
+	Addr = 0xF8000000U;
+	RegSize = REGION_16M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */
+	Addr = 0xF9000000U;
+	RegSize = REGION_1M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */
+	Addr = 0xFD000000U;
+	RegSize = REGION_16M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */
+	Addr = 0xFE000000U;
+	RegSize = REGION_16M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/*
+	 * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
+	 * CSU, PMU, TCM, OCM
+	 */
+	Addr = 0xFF000000U;
+	RegSize = REGION_16M;
+	Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW   ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+	RegNum++;
+
+	/* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */
+	Addr = 0xFFFC0000U;
+	RegSize = REGION_256K;
+	Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW  ;
+	Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
+
+	/* A total of 10 MPU regions are allocated with another 6 being free for users */
+
+}
+
+/*****************************************************************************
+*
+* Set the memory attributes for a section of memory with starting address addr
+* of the region size defined by reg_size having attributes attrib of region number
+* reg_num
+*
+* @param	addr is the address for which attributes are to be set.
+* @param	attrib specifies the attributes for that memory region.
+* @param	reg_size specifies the size for that memory region.
+* @param	reg_num specifies the number for that memory region.
+* @return	None.
+*
+*
+******************************************************************************/
+static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib)
+{
+	u32 Local_reg_size = reg_size;
+
+	Local_reg_size = Local_reg_size<<1U;
+	Local_reg_size |= REGION_EN;
+	dsb();
+	mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
+	isb();
+	mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); 		/* Set base address of a region */
+	mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); 	/* Set the control attribute */
+	mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size);	/* set the region size and enable it*/
+	dsb();
+	isb();						/* synchronize context on this processor */
+}
+
+
+/*****************************************************************************
+*
+* Disable all the MPU regions if any of them is enabled
+*
+* @param	None.
+*
+* @return	None.
+*
+*
+******************************************************************************/
+static void Xil_DisableMPURegions(void)
+{
+	u32 Temp;
+	u32 Index;
+	for (Index = 0; Index <= 15; Index++) {
+		mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
+		Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
+		Temp &= (~REGION_EN);
+		dsb();
+		mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
+		dsb();
+		isb();
+	}
+
+}
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/open.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/open.c
new file mode 100644
index 000000000..c32530bab
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/open.c
@@ -0,0 +1,57 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* Use toolchain function for openamp applications*/
+
+#ifndef UNDEFINE_FILE_OPS
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode);
+}
+#endif
+/*
+ * open -- open a file descriptor. We don't have a filesystem, so
+ *         we return an error.
+ */
+__attribute__((weak)) s32 open(char8 *buf, s32 flags, s32 mode)
+{
+  (void *)buf;
+  (void)flags;
+  (void)mode;
+  errno = EIO;
+  return (-1);
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/outbyte.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/outbyte.c
new file mode 100644
index 000000000..3c6430886
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/outbyte.c
@@ -0,0 +1,15 @@
+#include "xparameters.h"
+#include "xuartps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+void outbyte(char c); 
+
+#ifdef __cplusplus
+}
+#endif 
+
+void outbyte(char c) {
+	 XUartPs_SendByte(STDOUT_BASEADDRESS, c);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c
new file mode 100644
index 000000000..31d7b1989
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/print.c
@@ -0,0 +1,32 @@
+/* print.c -- print a string on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ *
+ */
+
+/*
+ * print -- do a raw print of a string
+ */
+#include "xil_printf.h"
+
+void print(const char8 *ptr)
+{
+#ifdef STDOUT_BASEADDRESS
+  while (*ptr != (char8)0) {
+    outbyte (*ptr);
+	*ptr++;
+  }
+#else
+(void)ptr;
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c
new file mode 100644
index 000000000..86d3a74e8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/putnum.c
@@ -0,0 +1,59 @@
+/* putnum.c -- put a hex number on the output device.
+ *
+ * Copyright (c) 1995 Cygnus Support
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+/*
+ * putnum -- print a 32 bit number in hex
+ */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Function Prototypes ******************************/
+extern void print (const char8 *ptr);
+void putnum(u32 num);
+
+void putnum(u32 num)
+{
+  char8  buf[9];
+  u32   cnt;
+  s32 i;
+  char8  *ptr;
+  u32  digit;
+  for(i = 0; i<9; i++) {
+	buf[i] = '0';
+  }
+
+  ptr = buf;
+  for (cnt = 7U ; cnt >= 0U ; cnt--) {
+    digit = (num >> (cnt * 4U)) & 0x0000000fU;
+
+    if ((digit <= 9U) && (ptr != NULL)) {
+		digit += (u32)'0';
+		*ptr = ((char8) digit);
+		ptr += 1;
+	} else if (ptr != NULL) {
+		digit += ((u32)'a' - (u32)10);
+		*ptr = ((char8)digit);
+		ptr += 1;
+	} else {
+		/*Made for MisraC Compliance*/;
+	}
+  }
+
+  if(ptr != NULL) {
+	  *ptr = (char8) 0;
+  }
+  print (buf);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c
new file mode 100644
index 000000000..90fb25029
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/read.c
@@ -0,0 +1,115 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/* Use toolchain function for openamp applications*/
+
+#ifndef UNDEFINE_FILE_OPS
+
+/* read.c -- read bytes from a input device.
+ */
+
+#include "xparameters.h"
+#include "xil_printf.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _read (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * read  -- read bytes from the serial port. Ignore fd, since
+ *          we only have stdin.
+ */
+__attribute__((weak)) s32
+read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    *LocalBuf = inbyte();
+	    if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
+	        break;
+		}
+	}
+	if(LocalBuf != NULL) {
+	LocalBuf -= i;
+	}
+  }
+
+  return (i + 1);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_read (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDIN_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    *LocalBuf = inbyte();
+	    if ((*LocalBuf == '\n' )|| (*LocalBuf == '\r')) {
+	        break;
+		}
+	}
+	if(LocalBuf != NULL) {
+	LocalBuf -= i;
+	}
+  }
+
+  return (i + 1);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c
new file mode 100644
index 000000000..7f94fabb4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sbrk.c
@@ -0,0 +1,65 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) char8 *sbrk (s32 nbytes);
+}
+#endif
+
+extern u8 _heap_start[];
+extern u8 _heap_end[];
+extern char8 HeapBase[];
+extern char8 HeapLimit[];
+
+
+
+__attribute__((weak)) char8 *sbrk (s32 nbytes)
+{
+  char8 *base;
+  static char8 *heap_ptr = HeapBase;
+
+  base = heap_ptr;
+  if(heap_ptr != NULL) {
+	heap_ptr += nbytes;
+  }
+
+/*  if (heap_ptr <= ((char8 *)&_heap_end + 1)) */
+  if (heap_ptr <= ((char8 *)&HeapLimit + 1)) {
+    return base;
+  }	else {
+    errno = ENOMEM;
+    return ((char8 *)-1);
+  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c
new file mode 100644
index 000000000..508b30f61
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.c
@@ -0,0 +1,125 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************
+*
+* @file sleep.c
+*
+* This function provides a second delay using the Global Timer register in
+* the ARM Cortex R5 MP core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+* 5.04  pkp		 02/19/16 sleep routine is modified to use TTC3 if present
+*						  else it will use set of assembly instructions to
+*						  provide the required delay
+* 5.04	pkp		 03/09/16 Assembly routine for sleep is modified to avoid
+*						  disabling the interrupt
+* 5.04	pkp		 03/11/16 Compare the counter value to previously read value
+*						  to detect the overflow for TTC3
+* 

+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+
+/*****************************************************************************/
+/*
+*
+* This API is used to provide delays in seconds.
+*
+* @param	seconds requested
+*
+* @return	0 always
+*
+* @note		The sleep API is implemented using TTC3 counter 0 timer if present.
+*			When TTC3 is absent, sleep is implemented using assembly
+*			instructions which is tested with instruction and data caches
+*			enabled and it gives proper delay. It may give more delay than
+*			exepcted when caches are disabled. If interrupt comes when sleep
+*			using assembly instruction is being executed, the delay may be
+*			greater than what is expected since once the interrupt is served
+*			count resumes from where it was interrupted unlike the case of TTC3
+*			where counter keeps running while interrupt is being served.
+*
+****************************************************************************/
+
+s32 sleep(u32 seconds)
+{
+#ifdef SLEEP_TIMER_BASEADDR
+	u64 tEnd;
+	u64 tCur;
+	u32 TimeHighVal;
+	XTime TimeLowVal1;
+	XTime TimeLowVal2;
+
+	TimeHighVal = 0;
+
+	XTime_GetTime(&TimeLowVal1);
+	tEnd  = (u64)TimeLowVal1 + (((u64) seconds) * COUNTS_PER_SECOND);
+
+	do
+	{
+
+	    XTime_GetTime(&TimeLowVal2);
+	    if (TimeLowVal2 < TimeLowVal1) {
+				TimeHighVal++;
+		}
+
+		TimeLowVal1 = TimeLowVal2;
+	    tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2;
+
+	} while (tCur < tEnd);
+
+	return 0;
+#else
+	__asm__ __volatile__ (
+			" push {r0,r1}		\n\t"
+			" mov r0, %[sec]	\n\t"
+			" 1: \n\t"
+			" mov r1, %[iter] 	\n\t"
+			" 2:				\n\t"
+			" subs r1, r1, #0x1 \n\t"
+			" bne   2b    		\n\t"
+			" subs r0,r0,#0x1 	\n\t"
+			"  bne 1b 			\n\t"
+			" pop {r0,r1} 		\n\t"
+			:: [iter] "r" (ITERS_PER_SEC), [sec] "r" (seconds)
+	);
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h
new file mode 100644
index 000000000..9b49173c6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/sleep.h
@@ -0,0 +1,49 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+#ifndef SLEEP_H
+#define SLEEP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "xil_types.h"
+#include "xil_io.h"
+
+s32 usleep(u32 useconds);
+s32 sleep(u32 seconds);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/uart.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/uart.c
new file mode 100644
index 000000000..bff3ed24f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/uart.c
@@ -0,0 +1,160 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file uart.c
+*
+* This file contains APIs for configuring the UART.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#include "xil_types.h"
+#include "xparameters.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/* Register offsets */
+#define UART_CR_OFFSET		0x00000000U
+#define UART_MR_OFFSET		0x00000004U
+#define UART_BAUDGEN_OFFSET	0x00000018U
+#define UART_BAUDDIV_OFFSET	0x00000034U
+
+#define MAX_BAUD_ERROR_RATE	0x00000003U	/* max % error allowed */
+#define UART_BAUDRATE	115200U
+#define CSU_VERSION_REG     0xFFCA0044U
+
+void Init_Uart(void);
+
+void Init_Uart(void)
+{
+#ifdef STDOUT_BASEADDRESS
+	u8 IterBAUDDIV;		/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud rate */
+	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFFU;
+	u32 PercentError;
+	u32 InputClk;
+   u32 BaudRate = UART_BAUDRATE;
+
+#if (STDOUT_BASEADDRESS == XPAR_XUARTPS_0_BASEADDR)
+	InputClk = XPAR_XUARTPS_0_UART_CLK_FREQ_HZ;
+#elif (STDOUT_BASEADDRESS == XPAR_XUARTPS_1_BASEADDR)
+	InputClk = XPAR_XUARTPS_1_UART_CLK_FREQ_HZ;
+#else
+	/* STDIO is not set or axi_uart is being used for STDIO */
+	return;
+#endif
+InputClk = 25000000U;
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4U; IterBAUDDIV < 255U; IterBAUDDIV++) {
+
+		/*
+		 * Calculate the value for BRGR register
+		 */
+		BRGR_Value = InputClk / (BaudRate * ((u32)IterBAUDDIV + 0x00000001U));
+
+		/*
+		 * Calculate the baud rate from the BRGR value
+		 */
+		CalcBaudRate = InputClk/ (BRGR_Value * ((u32)IterBAUDDIV + 0x00000001U));
+
+		/*
+		 * Avoid unsigned integer underflow
+		 */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		} else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/*
+		 * Find the calculated baud rate closest to requested baud rate.
+		 */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+
+		}
+	}
+
+	/*
+	 * Make sure the best error is not too large.
+	 */
+	PercentError = (Best_Error * 100U) / BaudRate;
+	if (MAX_BAUD_ERROR_RATE < PercentError) {
+		return;
+	}
+
+	/* set CD and BDIV */
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, Best_BRGR);
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, (u32)Best_BAUDDIV);
+
+    /*
+     * Veloce specific code
+     */
+    if((Xil_In32(CSU_VERSION_REG) & 0x0000F000U) == 0x00002000U ) {
+	Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDGEN_OFFSET, 0x00000002U);
+	    Xil_Out32(STDOUT_BASEADDRESS + UART_BAUDDIV_OFFSET, 0x00000004U);
+    }
+
+	/*
+	 * 8 data, 1 stop, 0 parity bits
+	 * sel_clk=uart_clk=APB clock
+	 */
+	Xil_Out32(STDOUT_BASEADDRESS + UART_MR_OFFSET, 0x00000020U);
+
+	/* enable Tx/Rx and reset Tx/Rx data path */
+	Xil_Out32((STDOUT_BASEADDRESS + UART_CR_OFFSET), 0x00000017U);
+
+	return;
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c
new file mode 100644
index 000000000..0c9f0f78e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/unlink.c
@@ -0,0 +1,50 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+#include 
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) sint32 unlink(char8 *path);
+}
+#endif
+/*
+ * unlink -- since we have no file system,
+ *           we just return an error.
+ */
+__attribute__((weak)) sint32 unlink(char8 *path)
+{
+  (void *)path;
+  errno = EIO;
+  return (-1);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c
new file mode 100644
index 000000000..afc9414bb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/usleep.c
@@ -0,0 +1,127 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file usleep.c
+*
+* This function provides a microsecond delay using the Global Timer register in
+* the ARM Cortex R5 MP core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+* 5.04  pkp		 02/19/16 usleep routine is modified to use TTC3 if present
+*						  else it will use set of assembly instructions to
+*						  provide the required delay
+* 5.04	pkp		 03/09/16 Assembly routine for usleep is modified to avoid
+*						  disabling the interrupt
+* 5.04	pkp		 03/11/16 Compare the counter value to previously read value
+*						  to detect the overflow for TTC3
+* 

+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "sleep.h"
+#include "xtime_l.h"
+#include "xparameters.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexr5.h"
+
+/*****************************************************************************/
+/**
+*
+* This API gives a delay in microseconds
+*
+* @param	useconds requested
+*
+* @return	0 always
+*
+* @note		The usleep API is implemented using TTC3 counter 0 timer if present
+*			When TTC3 is absent, usleep is implemented using assembly
+*			instructions which is tested with instruction and data caches
+*			enabled and it gives proper delay. It may give more delay than
+*			exepcted when caches are disabled. If interrupt comes when usleep
+*			using assembly instruction is being executed, the delay may be
+*			greater than what is expected since once the interrupt is served
+*			count resumes from where it was interrupted unlike the case of TTC3
+*			where counter keeps running while interrupt is being served.
+*
+****************************************************************************/
+
+s32 usleep(u32 useconds)
+{
+
+#ifdef SLEEP_TIMER_BASEADDR
+	u64 tEnd;
+	u64 tCur;
+	u32 TimeHighVal;
+	XTime TimeLowVal1;
+	XTime TimeLowVal2;
+
+	TimeHighVal = 0;
+
+	XTime_GetTime(&TimeLowVal1);
+	tEnd  = (u64)TimeLowVal1 + (((u64) useconds) * COUNTS_PER_USECOND);
+
+	do
+	{
+		XTime_GetTime(&TimeLowVal2);
+	    if (TimeLowVal2 < TimeLowVal1) {
+				TimeHighVal++;
+		}
+		TimeLowVal1 = TimeLowVal2;
+		tCur = (((u64) TimeHighVal) << 32U) | (u64)TimeLowVal2;
+	} while (tCur < tEnd);
+
+	return 0;
+#else
+	__asm__ __volatile__ (
+			" push {r0,r1}		\n\t"
+			" mov r0, %[usec]	\n\t"
+			" 1: \n\t"
+			" mov r1, %[iter] 	\n\t"
+			" 2:				\n\t"
+			" subs r1, r1, #0x1 \n\t"
+			" bne   2b    		\n\t"
+			" subs r0,r0,#0x1 	\n\t"
+			"  bne 1b 			\n\t"
+			" pop {r0,r1} 		\n\t"
+			:: [iter] "r" (ITERS_PER_USEC), [usec] "r" (useconds)
+	);
+#endif
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c
new file mode 100644
index 000000000..73162672f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.c
@@ -0,0 +1,168 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.c
+*
+* This file contains the C level vectors for the ARM Cortex R5 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xil_exception.h"
+#include "vectors.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+extern XExc_VectorTableEntry XExc_VectorTable[];
+
+/************************** Function Prototypes ******************************/
+
+
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the FIQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void FIQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_FIQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_FIQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the IRQ interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void IRQInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_IRQ_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_IRQ_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the SW Interrupt called from the vectors.s
+* file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void SWInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_SWI_INT].Handler(XExc_VectorTable[
+					XIL_EXCEPTION_ID_SWI_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the DataAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void DataAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_DATA_ABORT_INT].Data);
+}
+
+/*****************************************************************************/
+/**
+*
+* This is the C level wrapper for the PrefetchAbort Interrupt called from the
+* vectors.s file.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void PrefetchAbortInterrupt(void)
+{
+	XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Handler(
+		XExc_VectorTable[XIL_EXCEPTION_ID_PREFETCH_ABORT_INT].Data);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h
new file mode 100644
index 000000000..ad4d8ece3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/vectors.h
@@ -0,0 +1,81 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file vectors.h
+*
+* This file contains the C level vector prototypes for the ARM Cortex R5 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef VECTORS_H_
+#define VECTORS_H_
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+void FIQInterrupt(void);
+void IRQInterrupt(void);
+void SWInterrupt(void);
+void DataAbortInterrupt(void);
+void PrefetchAbortInterrupt(void);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c
new file mode 100644
index 000000000..4ae96c29f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/write.c
@@ -0,0 +1,116 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/* Use toolchain function for openamp applications*/
+
+#ifndef UNDEFINE_FILE_OPS
+
+/* write.c -- write bytes to an output device.
+ */
+
+#include "xparameters.h"
+#include "xil_printf.h"
+
+#ifdef __cplusplus
+extern "C" {
+	__attribute__((weak)) s32 _write (s32 fd, char8* buf, s32 nbytes);
+}
+#endif
+
+/*
+ * write -- write bytes to the serial port. Ignore fd, since
+ *          stdout and stderr are the same. Since we have no filesystem,
+ *          open will only return an error.
+ */
+__attribute__((weak)) s32
+write (s32 fd, char8* buf, s32 nbytes)
+
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+
+__attribute__((weak)) s32
+_write (s32 fd, char8* buf, s32 nbytes)
+{
+#ifdef STDOUT_BASEADDRESS
+  s32 i;
+  char8* LocalBuf = buf;
+
+  (void)fd;
+  for (i = 0; i < nbytes; i++) {
+	if(LocalBuf != NULL) {
+		LocalBuf += i;
+	}
+	if(LocalBuf != NULL) {
+	    if (*LocalBuf == '\n') {
+	      outbyte ('\r');
+	    }
+	    outbyte (*LocalBuf);
+	}
+	if(LocalBuf != NULL) {
+		LocalBuf -= i;
+	}
+  }
+  return (nbytes);
+#else
+  (void)fd;
+  (void)buf;
+  (void)nbytes;
+  return 0;
+#endif
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xbasic_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xbasic_types.h
new file mode 100644
index 000000000..787212ca7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xbasic_types.h
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xbasic_types.h
+*
+*
+* @note  Dummy File for backwards compatibility
+*
+
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a adk   1/31/14  Added in bsp common folder for backward compatibility
+* 

+*
+******************************************************************************/
+
+#ifndef XBASIC_TYPES_H	/* prevent circular inclusions */
+#define XBASIC_TYPES_H	/* by using protection macros */
+
+/** @name Legacy types
+ * Deprecated legacy types.
+ * @{
+ */
+typedef unsigned char	Xuint8;		/**< unsigned 8-bit */
+typedef char		Xint8;		/**< signed 8-bit */
+typedef unsigned short	Xuint16;	/**< unsigned 16-bit */
+typedef short		Xint16;		/**< signed 16-bit */
+typedef unsigned long	Xuint32;	/**< unsigned 32-bit */
+typedef long		Xint32;		/**< signed 32-bit */
+typedef float		Xfloat32;	/**< 32-bit floating point */
+typedef double		Xfloat64;	/**< 64-bit double precision FP */
+typedef unsigned long	Xboolean;	/**< boolean (XTRUE or XFALSE) */
+
+#if !defined __XUINT64__
+typedef struct
+{
+	Xuint32 Upper;
+	Xuint32 Lower;
+} Xuint64;
+#endif
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XIL_TYPES_H
+typedef Xuint32         u32;
+typedef Xuint16         u16;
+typedef Xuint8          u8;
+#endif
+#else
+#include 
+#endif
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+/*
+ * Xilinx NULL, TRUE and FALSE legacy support. Deprecated.
+ * Please use NULL, TRUE and FALSE
+ */
+#define XNULL		NULL
+#define XTRUE		TRUE
+#define XFALSE		FALSE
+
+/*
+ * This file is deprecated and users
+ * should use xil_types.h and xil_assert.h\n\r
+ */
+#warning  The xbasics_type.h file is deprecated and users should use xil_types.h and xil_assert.
+#warning  Please refer the Standalone BSP UG647 for further details
+
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xdebug.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xdebug.h
new file mode 100644
index 000000000..650946bd0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xdebug.h
@@ -0,0 +1,32 @@
+#ifndef XDEBUG  /* prevent circular inclusions */
+#define XDEBUG  /* by using protection macros */
+
+#if defined(DEBUG) && !defined(NDEBUG)
+
+#ifndef XDEBUG_WARNING
+#define XDEBUG_WARNING
+#warning DEBUG is enabled
+#endif
+
+int printf(const char *format, ...);
+
+#define XDBG_DEBUG_ERROR             0x00000001U    /* error  condition messages */
+#define XDBG_DEBUG_GENERAL           0x00000002U    /* general debug  messages */
+#define XDBG_DEBUG_ALL               0xFFFFFFFFU    /* all debugging data */
+
+#define xdbg_current_types (XDBG_DEBUG_GENERAL)
+
+#define xdbg_stmnt(x)  x
+
+#define xdbg_printf(type, ...) (((type) & xdbg_current_types) ? printf (__VA_ARGS__) : 0)
+
+
+#else /* defined(DEBUG) && !defined(NDEBUG) */
+
+#define xdbg_stmnt(x)
+
+#define xdbg_printf(...)
+
+#endif /* defined(DEBUG) && !defined(NDEBUG) */
+
+#endif /* XDEBUG */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv.h
new file mode 100644
index 000000000..3d97bebd4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv.h
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv.h
+*
+* Defines common services that are typically found in a host operating.
+* environment. This include file simply includes an OS specific file based
+* on the compile-time constant BUILD_ENV_*, where * is the name of the target
+* environment.
+*
+* All services are defined as macros.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00b ch   10/24/02 Added XENV_LINUX
+* 1.00a rmm  04/17/02 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XENV_H /* prevent circular inclusions */
+#define XENV_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Select which target environment we are operating under
+ */
+
+/* VxWorks target environment */
+#if defined XENV_VXWORKS
+#include "xenv_vxworks.h"
+
+/* Linux target environment */
+#elif defined XENV_LINUX
+#include "xenv_linux.h"
+
+/* Unit test environment */
+#elif defined XENV_UNITTEST
+#include "ut_xenv.h"
+
+/* Integration test environment */
+#elif defined XENV_INTTEST
+#include "int_xenv.h"
+
+/* Standalone environment selected */
+#else
+#include "xenv_standalone.h"
+#endif
+
+
+/*
+ * The following comments specify the types and macro wrappers that are
+ * expected to be defined by the target specific header files
+ */
+
+/**************************** Type Definitions *******************************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP
+ *
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_COPY(void *DestPtr, void *SrcPtr, unsigned Bytes)
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param   DestPtr is the destination address to copy data to.
+ * @param   SrcPtr is the source address to copy data from.
+ * @param   Bytes is the number of bytes to copy.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_MEM_FILL(void *DestPtr, char Data, unsigned Bytes)
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param   DestPtr is the destination address to set.
+ * @param   Data contains the value to set.
+ * @param   Bytes is the number of bytes to set.
+ *
+ * @return  None
+ */
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ *
+ * Samples the processor's or external timer's time base counter.
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_US(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of microseconds.
+ */
+
+/*****************************************************************************/
+/**
+ *
+ * XENV_TIME_STAMP_DELTA_MS(XTIME_STAMP *Stamp1Ptr, XTIME_STAMP* Stamp2Ptr)
+ *
+ * Computes the delta between the two time stamps.
+ *
+ * @param   Stamp1Ptr - First sampled time stamp.
+ * @param   Stamp1Ptr - Sedond sampled time stamp.
+ *
+ * @return  An unsigned int value with units of milliseconds.
+ */
+
+/*****************************************************************************//**
+ *
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds.
+ *
+ * @param   delay is the number of microseconds to delay.
+ *
+ * @return  None
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif            /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv_standalone.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv_standalone.h
new file mode 100644
index 000000000..f18601874
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xenv_standalone.h
@@ -0,0 +1,368 @@
+/******************************************************************************
+*
+* Copyright (C) 2002 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xenv_standalone.h
+*
+* Defines common services specified by xenv.h.
+*
+* @note
+* 	This file is not intended to be included directly by driver code.
+* 	Instead, the generic xenv.h file is intended to be included by driver
+* 	code.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a wgr  02/28/07 Added cache handling macros.
+* 1.00a wgr  02/27/07 Simplified code. Deprecated old-style macro names.
+* 1.00a rmm  01/24/06 Implemented XENV_USLEEP. Assume implementation is being
+*                     used under Xilinx standalone BSP.
+* 1.00a xd   11/03/04 Improved support for doxygen.
+* 1.00a rmm  03/21/02 First release
+* 1.00a wgr  03/22/07 Converted to new coding style.
+* 1.00a rpm  06/29/07 Added udelay macro for standalone
+* 1.00a xd   07/19/07 Included xparameters.h as XPAR_ constants are referred
+*                     to in MICROBLAZE section
+* 1.00a ecm  09/19/08 updated for v7.20 of Microblaze, new functionality
+*
+* 

+*
+*
+******************************************************************************/
+
+#ifndef XENV_STANDALONE_H
+#define XENV_STANDALONE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+/******************************************************************************
+ *
+ * Get the processor dependent includes
+ *
+ ******************************************************************************/
+
+#include 
+
+#if defined __MICROBLAZE__
+#  include "mb_interface.h"
+#  include "xparameters.h"   /* XPAR constants used below in MB section */
+
+#elif defined __PPC__
+#  include "sleep.h"
+#  include "xcache_l.h"      /* also include xcache_l.h for caching macros */
+#endif
+
+/******************************************************************************
+ *
+ * MEMCPY / MEMSET related macros.
+ *
+ * The following are straight forward implementations of memset and memcpy.
+ *
+ * NOTE: memcpy may not work if source and target memory area are overlapping.
+ *
+ ******************************************************************************/
+/*****************************************************************************/
+/**
+ *
+ * Copies a non-overlapping block of memory.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	SrcPtr
+ * 		Source address to copy data from.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_COPY is deprecated. Use memcpy() instead.
+ *
+ * @note
+ * 		This implemention MAY BREAK work if source and target memory
+ * 		area are overlapping.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_COPY(DestPtr, SrcPtr, Bytes) \
+	memcpy((void *) DestPtr, (const void *) SrcPtr, (size_t) Bytes)
+
+
+
+/*****************************************************************************/
+/**
+ *
+ * Fills an area of memory with constant data.
+ *
+ * @param	DestPtr
+ *		Destination address to copy data to.
+ *
+ * @param	Data
+ * 		Value to set.
+ *
+ * @param	Bytes
+ * 		Number of bytes to copy.
+ *
+ * @return	None.
+ *
+ * @note
+ * 		The use of XENV_MEM_FILL is deprecated. Use memset() instead.
+ *
+ *****************************************************************************/
+
+#define XENV_MEM_FILL(DestPtr, Data, Bytes) \
+	memset((void *) DestPtr, (s32) Data, (size_t) Bytes)
+
+
+
+/******************************************************************************
+ *
+ * TIME related macros
+ *
+ ******************************************************************************/
+
+/**
+ * A structure that contains a time stamp used by other time stamp macros
+ * defined below. This structure is processor dependent.
+ */
+typedef s32 XENV_TIME_STAMP;
+
+/*****************************************************************************/
+/**
+ *
+ * Time is derived from the 64 bit PPC timebase register
+ *
+ * @param   StampPtr is the storage for the retrieved time stamp.
+ *
+ * @return  None.
+ *
+ * @note
+ *
+ * Signature: void XENV_TIME_STAMP_GET(XTIME_STAMP *StampPtr)
+ * 


+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_GET(StampPtr)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_US(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ *
+ * This macro is not yet implemented and always returns 0.
+ *
+ * @param   Stamp1Ptr is the first sampled time stamp.
+ * @param   Stamp2Ptr is the second sampled time stamp.
+ *
+ * @return  0
+ *
+ * @note
+ *
+ * This macro must be implemented by the user.
+ *
+ *****************************************************************************/
+#define XENV_TIME_STAMP_DELTA_MS(Stamp1Ptr, Stamp2Ptr)     (0)
+
+/*****************************************************************************/
+/**
+ * XENV_USLEEP(unsigned delay)
+ *
+ * Delay the specified number of microseconds. Not implemented without OS
+ * support.
+ *
+ * @param	delay
+ * 		Number of microseconds to delay.
+ *
+ * @return	None.
+ *
+ *****************************************************************************/
+
+#ifdef __PPC__
+#define XENV_USLEEP(delay)	usleep(delay)
+#define udelay(delay)	usleep(delay)
+#else
+#define XENV_USLEEP(delay)
+#define udelay(delay)
+#endif
+
+
+/******************************************************************************
+ *
+ * CACHE handling macros / mappings
+ *
+ ******************************************************************************/
+/******************************************************************************
+ *
+ * Processor independent macros
+ *
+ ******************************************************************************/
+
+#define XCACHE_ENABLE_CACHE()	\
+		{ XCACHE_ENABLE_DCACHE(); XCACHE_ENABLE_ICACHE(); }
+
+#define XCACHE_DISABLE_CACHE()	\
+		{ XCACHE_DISABLE_DCACHE(); XCACHE_DISABLE_ICACHE(); }
+
+
+/******************************************************************************
+ *
+ * MicroBlaze case
+ *
+ * NOTE: Currently the following macros will only work on systems that contain
+ * only ONE MicroBlaze processor. Also, the macros will only be enabled if the
+ * system is built using a xparameters.h file.
+ *
+ ******************************************************************************/
+
+#if defined __MICROBLAZE__
+
+/* Check if MicroBlaze data cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_DCACHE == 1)
+#  define XCACHE_ENABLE_DCACHE()		microblaze_enable_dcache()
+#  define XCACHE_DISABLE_DCACHE()		microblaze_disable_dcache()
+#  define XCACHE_INVALIDATE_DCACHE()  	microblaze_invalidate_dcache()
+
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+
+#if (XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK == 1)
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_flush_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_flush_dcache_range((s32)(Addr), (s32)(Len))
+#else
+#  define XCACHE_FLUSH_DCACHE()  		microblaze_invalidate_dcache()
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_dcache_range((s32)(Addr), (s32)(Len))
+#endif	/*XPAR_MICROBLAZE_DCACHE_USE_WRITEBACK*/
+
+#else
+#  define XCACHE_ENABLE_DCACHE()
+#  define XCACHE_DISABLE_DCACHE()
+#  define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len)
+#  define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len)
+#endif	/*XPAR_MICROBLAZE_USE_DCACHE*/
+
+
+/* Check if MicroBlaze instruction cache was built into the core.
+ */
+#if (XPAR_MICROBLAZE_USE_ICACHE == 1)
+#  define XCACHE_ENABLE_ICACHE()		microblaze_enable_icache()
+#  define XCACHE_DISABLE_ICACHE()		microblaze_disable_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE()  	microblaze_invalidate_icache()
+
+#  define XCACHE_INVALIDATE_ICACHE_RANGE(Addr, Len) \
+			microblaze_invalidate_icache_range((s32)(Addr), (s32)(Len))
+
+#else
+#  define XCACHE_ENABLE_ICACHE()
+#  define XCACHE_DISABLE_ICACHE()
+#endif	/*XPAR_MICROBLAZE_USE_ICACHE*/
+
+
+/******************************************************************************
+ *
+ * PowerPC case
+ *
+ *   Note that the XCACHE_ENABLE_xxx functions are hardcoded to enable a
+ *   specific memory region (0x80000001). Each bit (0-30) in the regions
+ *   bitmask stands for 128MB of memory. Bit 31 stands for the upper 2GB
+ *   range.
+ *
+ *   regions    --> cached address range
+ *   ------------|--------------------------------------------------
+ *   0x80000000  | [0, 0x7FFFFFF]
+ *   0x00000001  | [0xF8000000, 0xFFFFFFFF]
+ *   0x80000001  | [0, 0x7FFFFFF],[0xF8000000, 0xFFFFFFFF]
+ *
+ ******************************************************************************/
+
+#elif defined __PPC__
+
+#define XCACHE_ENABLE_DCACHE()		XCache_EnableDCache(0x80000001)
+#define XCACHE_DISABLE_DCACHE()		XCache_DisableDCache()
+#define XCACHE_ENABLE_ICACHE()		XCache_EnableICache(0x80000001)
+#define XCACHE_DISABLE_ICACHE()		XCache_DisableICache()
+
+#define XCACHE_INVALIDATE_DCACHE_RANGE(Addr, Len) \
+		XCache_InvalidateDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_FLUSH_DCACHE_RANGE(Addr, Len) \
+		XCache_FlushDCacheRange((u32)(Addr), (u32)(Len))
+
+#define XCACHE_INVALIDATE_ICACHE()	XCache_InvalidateICache()
+
+
+/******************************************************************************
+ *
+ * Unknown processor / architecture
+ *
+ ******************************************************************************/
+
+#else
+/* #error "Unknown processor / architecture. Must be MicroBlaze or PowerPC." */
+#endif
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* #ifndef XENV_STANDALONE_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S
new file mode 100644
index 000000000..cca2f0d69
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil-crt0.S
@@ -0,0 +1,130 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil-crt0.S
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00 	pkp  02/10/14 First release
+* 5.04  pkp  12/18/15 Initialized global constructor for C++ applications
+* 5.04  pkp  02/19/16 Added timer configuration using XTime_StartTimer API when
+*		      TTC3 is present
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+#include "xparameters.h"
+	.file	"xil-crt0.S"
+	.section ".got2","aw"
+	.align	2
+
+	.text
+.Lsbss_start:
+	.long	__sbss_start
+
+.Lsbss_end:
+	.long	__sbss_end
+
+.Lbss_start:
+	.long	__bss_start__
+
+.Lbss_end:
+	.long	__bss_end__
+
+.Lstack:
+	.long	__stack
+
+
+	.globl	_startup
+
+_startup:
+	bl      __cpu_init		/* Initialize the CPU first (BSP provides this) */
+
+	mov	r0, #0
+
+	/* clear sbss */
+	ldr 	r1,.Lsbss_start		/* calculate beginning of the SBSS */
+	ldr	r2,.Lsbss_end		/* calculate end of the SBSS */
+
+.Lloop_sbss:
+	cmp	r1,r2
+	bge	.Lenclsbss		/* If no SBSS, no clearing required */
+	str	r0, [r1], #4
+	b	.Lloop_sbss
+
+.Lenclsbss:
+	/* clear bss */
+	ldr	r1,.Lbss_start		/* calculate beginning of the BSS */
+	ldr	r2,.Lbss_end		/* calculate end of the BSS */
+
+.Lloop_bss:
+	cmp	r1,r2
+	bge	.Lenclbss		/* If no BSS, no clearing required */
+	str	r0, [r1], #4
+	b	.Lloop_bss
+
+.Lenclbss:
+
+	/* set stack pointer */
+	ldr	r13,.Lstack		/* stack address */
+
+	/* configure the timer if TTC3 is present */
+#ifdef SLEEP_TIMER_BASEADDR
+	bl XTime_StartTimer
+#endif
+
+	/* run global constructors */
+	bl __libc_init_array
+
+	/* make sure argc and argv are valid */
+	mov	r0, #0
+	mov	r1, #0
+
+	bl	main			/* Jump to main C code */
+
+	/* Cleanup global constructors */
+	bl __libc_fini_array
+
+	bl	exit
+
+.Lexit:	/* should never get here */
+	b .Lexit
+
+.Lstart:
+	.size	_startup,.Lstart-_startup
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c
new file mode 100644
index 000000000..42db07deb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.c
@@ -0,0 +1,146 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.c
+*
+* This file contains basic assert related functions for Xilinx software IP.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 Initial release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/**
+ * This variable allows testing to be done easier with asserts. An assert
+ * sets this variable such that a driver can evaluate this variable
+ * to determine if an assert occurred.
+ */
+u32 Xil_AssertStatus;
+
+/**
+ * This variable allows the assert functionality to be changed for testing
+ * such that it does not wait infinitely. Use the debugger to disable the
+ * waiting during testing of asserts.
+ */
+/*s32 Xil_AssertWait = 1*/
+
+/* The callback function to be invoked when an assert is taken */
+static Xil_AssertCallback Xil_AssertCallbackRoutine = NULL;
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Implement assert. Currently, it calls a user-defined callback function
+* if one has been set.  Then, it potentially enters an infinite loop depending
+* on the value of the Xil_AssertWait variable.
+*
+* @param    file is the name of the filename of the source
+* @param    line is the linenumber within File
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void Xil_Assert(const char8 *File, s32 Line)
+{
+	s32 Xil_AssertWait = 1;
+	/* if the callback has been set then invoke it */
+	if (Xil_AssertCallbackRoutine != 0) {
+		(*Xil_AssertCallbackRoutine)(File, Line);
+	}
+
+	/* if specified, wait indefinitely such that the assert will show up
+	 * in testing
+	 */
+	while (Xil_AssertWait != 0) {
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Set up a callback function to be invoked when an assert occurs. If there
+* was already a callback installed, then it is replaced.
+*
+* @param    routine is the callback to be invoked when an assert is taken
+*
+* @return   None.
+*
+* @note     This function has no effect if NDEBUG is set
+*
+******************************************************************************/
+void Xil_AssertSetCallback(Xil_AssertCallback Routine)
+{
+	Xil_AssertCallbackRoutine = Routine;
+}
+
+/*****************************************************************************/
+/**
+*
+* Null handler function. This follows the XInterruptHandler signature for
+* interrupt handlers. It can be used to assign a null handler (a stub) to an
+* interrupt controller vector table.
+*
+* @param    NullParameter is an arbitrary void pointer and not used.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+void XNullHandler(void *NullParameter)
+{
+ (void *) NullParameter;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h
new file mode 100644
index 000000000..7034bc9ad
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_assert.h
@@ -0,0 +1,189 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_assert.h
+*
+* This file contains assert related functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_ASSERT_H	/* prevent circular inclusions */
+#define XIL_ASSERT_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/***************************** Include Files *********************************/
+
+
+/************************** Constant Definitions *****************************/
+
+#define XIL_ASSERT_NONE     0U
+#define XIL_ASSERT_OCCURRED 1U
+#define XNULL NULL
+
+extern u32 Xil_AssertStatus;
+extern void Xil_Assert(const char8 *File, s32 Line);
+void XNullHandler(void *NullParameter);
+
+/**
+ * This data type defines a callback to be invoked when an
+ * assert occurs. The callback is invoked only when asserts are enabled
+ */
+typedef void (*Xil_AssertCallback) (const char8 *File, s32 Line);
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#ifndef NDEBUG
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do not return anything
+* (void). This in conjunction with the Xil_AssertWait boolean can be used to
+* accomodate tests so that asserts which fail allow execution to continue.
+*
+* @param    Expression is the expression to evaluate. If it evaluates to
+*           false, the assert occurs.
+*
+* @return   Returns void unless the Xil_AssertWait variable is true, in which
+*           case no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_AssertVoid(Expression)                \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return;                                    \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* This assert macro is to be used for functions that do return a value. This in
+* conjunction with the Xil_AssertWait boolean can be used to accomodate tests
+* so that asserts which fail allow execution to continue.
+*
+* @param    Expression is the expression to evaluate. If it evaluates to false,
+*           the assert occurs.
+*
+* @return   Returns 0 unless the Xil_AssertWait variable is true, in which
+* 	    case no return is made and an infinite loop is entered.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoid(Expression)             \
+{                                                  \
+    if (Expression) {                              \
+        Xil_AssertStatus = XIL_ASSERT_NONE;       \
+    } else {                                       \
+        Xil_Assert(__FILE__, __LINE__);            \
+        Xil_AssertStatus = XIL_ASSERT_OCCURRED;   \
+        return 0;                                  \
+    }                                              \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do not
+* return anything (void). Use for instances where an assert should always
+* occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	  case no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define Xil_AssertVoidAlways()                   \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return;                                         \
+}
+
+/*****************************************************************************/
+/**
+* Always assert. This assert macro is to be used for functions that do return
+* a value. Use for instances where an assert should always occur.
+*
+* @return Returns void unless the Xil_AssertWait variable is true, in which
+*	  case no return is made and an infinite loop is entered.
+*
+* @note   None.
+*
+******************************************************************************/
+#define Xil_AssertNonvoidAlways()                \
+{                                                  \
+   Xil_Assert(__FILE__, __LINE__);                 \
+   Xil_AssertStatus = XIL_ASSERT_OCCURRED;        \
+   return 0;                                       \
+}
+
+
+#else
+
+#define Xil_AssertVoid(Expression)
+#define Xil_AssertVoidAlways()
+#define Xil_AssertNonvoid(Expression)
+#define Xil_AssertNonvoidAlways()
+
+#endif
+
+/************************** Function Prototypes ******************************/
+
+void Xil_AssertSetCallback(Xil_AssertCallback Routine);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.c
new file mode 100644
index 000000000..2ba080dff
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.c
@@ -0,0 +1,580 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.c
+*
+* Contains required functions for the ARM cache functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xpseudo_asm.h"
+#include "xparameters.h"
+#include "xreg_cortexr5.h"
+#include "xil_exception.h"
+
+
+/************************** Variable Definitions *****************************/
+
+#define IRQ_FIQ_MASK 0xC0	/* Mask IRQ and FIQ interrupts in cpsr */
+
+
+extern s32  _stack_end;
+extern s32  __undef_stack;
+
+/****************************************************************************/
+/************************** Function Prototypes ******************************/
+
+/****************************************************************************
+*
+* Enable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheEnable(void)
+{
+	register u32 CtrlReg;
+
+	/* enable caches only if they are disabled */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+	if ((CtrlReg & XREG_CP15_CONTROL_C_BIT)==0x00000000U) {
+		/* invalidate the Data cache */
+		Xil_DCacheInvalidate();
+
+		/* enable the Data cache */
+		CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	}
+}
+
+/****************************************************************************
+*
+* Disable the Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheDisable(void)
+{
+	register u32 CtrlReg;
+
+	/* clean and invalidate the Data cache */
+	Xil_DCacheFlush();
+
+	/* disable the Data cache */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+	CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************
+*
+* Invalidate the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidate(void)
+{
+	u32 currmask;
+	u32 stack_start,stack_end,stack_size;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+
+	stack_end = (u32 )&_stack_end;
+	stack_start = (u32 )&__undef_stack;
+	stack_size = stack_start-stack_end;
+
+	/* Flush stack memory to save return address */
+	Xil_DCacheFlushRange(stack_end, stack_size);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+	/*invalidate all D cache*/
+	mtcp(XREG_CP15_INVAL_DC_ALL, 0);
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the modified contents
+* are lost and are NOT written to system memory before the line is
+* invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateLine(INTPTR adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+	mtcp(XREG_CP15_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+		/* Wait for invalidate to complete */
+	dsb();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated.	If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param	Start address of range to be invalidated.
+* @param	Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len)
+{
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 tempadr = adr;
+	u32 tempend;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0U) {
+		end = tempadr + len;
+		tempend = end;
+		/* Select L1 Data cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 0U);
+
+		if ((tempadr & (cacheline-1U)) != 0U) {
+			tempadr &= (~(cacheline - 1U));
+
+			Xil_DCacheFlushLine(tempadr);
+		}
+		if ((tempend & (cacheline-1U)) != 0U) {
+			tempend &= (~(cacheline - 1U));
+
+			Xil_DCacheFlushLine(tempend);
+		}
+
+		while (tempadr < tempend) {
+
+		/* Invalidate Data cache line */
+		asm_inval_dc_line_mva_poc(tempadr);
+
+		tempadr += cacheline;
+		}
+	}
+
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush the entire Data cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlush(void)
+{
+	register u32 CsidReg, C7Reg;
+	u32 CacheSize, LineSize, NumWays;
+	u32 Way, WayIndex, Set, SetIndex, NumSet;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	/* Select cache level 0 and D cache in CSSR */
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+	CsidReg = mfcp(XREG_CP15_CACHE_SIZE_ID);
+
+	/* Determine Cache Size */
+
+	CacheSize = (CsidReg >> 13U) & 0x000001FFU;
+	CacheSize += 0x00000001U;
+	CacheSize *= (u32)128;    /* to get number of bytes */
+
+	/* Number of Ways */
+	NumWays = (CsidReg & 0x000003ffU) >> 3U;
+	NumWays += 0x00000001U;
+
+	/* Get the cacheline size, way size, index size from csidr */
+	LineSize = (CsidReg & 0x00000007U) + 0x00000004U;
+
+	NumSet = CacheSize/NumWays;
+	NumSet /= (0x00000001U << LineSize);
+
+	Way = 0U;
+	Set = 0U;
+
+	/* Invalidate all the cachelines */
+	for (WayIndex = 0U; WayIndex < NumWays; WayIndex++) {
+		for (SetIndex = 0U; SetIndex < NumSet; SetIndex++) {
+			C7Reg = Way | Set;
+			/* Flush by Set/Way */
+			asm_clean_inval_dc_line_sw(C7Reg);
+
+			Set += (0x00000001U << LineSize);
+		}
+		Set = 0U;
+		Way += 0x40000000U;
+	}
+
+	/* Wait for flush to complete */
+	dsb();
+	mtcpsr(currmask);
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Flush a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache, the cacheline containing that byte is
+* invalidated.	If the cacheline is modified (dirty), the entire
+* contents of the cacheline are written to system memory before the
+* line is invalidated.
+*
+* @param	Address to be flushed.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheFlushLine(INTPTR adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+
+	mtcp(XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+		/* Wait for flush to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+* Flush the Data cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated.	If the cacheline
+* is modified (dirty), the written to system memory first before the
+* before the line is invalidated.
+*
+* @param	Start address of range to be flushed.
+* @param	Length of range to be flushed in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_DCacheFlushRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	if (len != 0x00000000U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr &= ~(cacheline - 1U);
+
+		while (LocalAddr < end) {
+			/* Flush Data cache line */
+			asm_clean_inval_dc_line_mva_poc(LocalAddr);
+
+			LocalAddr += cacheline;
+		}
+	}
+	dsb();
+	mtcpsr(currmask);
+}
+/****************************************************************************
+*
+* Store a Data cache line. If the byte specified by the address (adr)
+* is cached by the Data cache and the cacheline is modified (dirty),
+* the entire contents of the cacheline are written to system memory.
+* After the store completes, the cacheline is marked as unmodified
+* (not dirty).
+*
+* @param	Address to be stored.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_DCacheStoreLine(INTPTR adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 0);
+	mtcp(XREG_CP15_CLEAN_DC_LINE_MVA_POC, (adr & (~0x1F)));
+
+	/* Wait for store to complete */
+	dsb();
+	isb();
+
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Enable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheEnable(void)
+{
+	register u32 CtrlReg;
+
+	/* enable caches only if they are disabled */
+
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+	if ((CtrlReg & XREG_CP15_CONTROL_I_BIT)==0x00000000U) {
+		/* invalidate the instruction cache */
+		mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+		/* enable the instruction cache */
+		CtrlReg |= (XREG_CP15_CONTROL_I_BIT);
+
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	}
+}
+
+/****************************************************************************
+*
+* Disable the instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheDisable(void)
+{
+	register u32 CtrlReg;
+
+	dsb();
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+		/* disable the instruction cache */
+
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+
+	CtrlReg &= ~(XREG_CP15_CONTROL_I_BIT);
+
+	mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+}
+
+/****************************************************************************
+*
+* Invalidate the entire instruction cache.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidate(void)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+
+	/* invalidate the instruction cache */
+	mtcp(XREG_CP15_INVAL_IC_POU, 0);
+
+	/* Wait for invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate an instruction cache line.	If the instruction specified by the
+* parameter adr is cached by the instruction cache, the cacheline containing
+* that instruction is invalidated.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		The bottom 4 bits are set to 0, forced by architecture.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateLine(INTPTR adr)
+{
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+
+	mtcp(XREG_CP15_CACHE_SIZE_SEL, 1);
+	mtcp(XREG_CP15_INVAL_IC_LINE_MVA_POU, (adr & (~0x1F)));
+
+		/* Wait for invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
+
+/****************************************************************************
+*
+* Invalidate the instruction cache for the given address range.
+* If the bytes specified by the address (adr) are cached by the Data cache,
+* the cacheline containing that byte is invalidated. If the cacheline
+* is modified (dirty), the modified contents are lost and are NOT
+* written to system memory before the line is invalidated.
+*
+* @param	Start address of range to be invalidated.
+* @param	Length of range to be invalidated in bytes.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len)
+{
+	u32 LocalAddr = adr;
+	const u32 cacheline = 32U;
+	u32 end;
+	u32 currmask;
+
+	currmask = mfcpsr();
+	mtcpsr(currmask | IRQ_FIQ_MASK);
+	if (len != 0x00000000U) {
+		/* Back the starting address up to the start of a cache line
+		 * perform cache operations until adr+len
+		 */
+		end = LocalAddr + len;
+		LocalAddr = LocalAddr & ~(cacheline - 1U);
+
+		/* Select cache L0 I-cache in CSSR */
+		mtcp(XREG_CP15_CACHE_SIZE_SEL, 1U);
+
+		while (LocalAddr < end) {
+
+			/* Invalidate L1 I-cache line */
+			asm_inval_ic_line_mva_pou(LocalAddr);
+
+			LocalAddr += cacheline;
+		}
+	}
+
+	/* Wait for invalidate to complete */
+	dsb();
+	mtcpsr(currmask);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.h
new file mode 100644
index 000000000..581db3f16
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache.h
@@ -0,0 +1,89 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache.h
+*
+* Contains required functions for the ARM cache functionality
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 

+*
+******************************************************************************/
+#ifndef XIL_CACHE_H
+#define XIL_CACHE_H
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define asm_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_INVAL_DC_LINE_MVA_POC :: "r" (param))
+
+#define asm_clean_inval_dc_line_sw(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_CLEAN_INVAL_DC_LINE_SW :: "r" (param))
+
+#define asm_clean_inval_dc_line_mva_poc(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC :: "r" (param))
+
+#define asm_inval_ic_line_mva_pou(param) __asm__ __volatile__("mcr " \
+		XREG_CP15_INVAL_IC_LINE_MVA_POU :: "r" (param))
+
+void Xil_DCacheEnable(void);
+void Xil_DCacheDisable(void);
+void Xil_DCacheInvalidate(void);
+void Xil_DCacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_DCacheFlush(void);
+void Xil_DCacheFlushRange(INTPTR adr, u32 len);
+void Xil_DCacheInvalidateLine(INTPTR adr);
+void Xil_DCacheFlushLine(INTPTR adr);
+void Xil_DCacheStoreLine(INTPTR adr);
+
+void Xil_ICacheEnable(void);
+void Xil_ICacheDisable(void);
+void Xil_ICacheInvalidate(void);
+void Xil_ICacheInvalidateRange(INTPTR adr, u32 len);
+void Xil_ICacheInvalidateLine(INTPTR adr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h
new file mode 100644
index 000000000..6e8cfa75f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_cache_vxworks.h
@@ -0,0 +1,93 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_cache_vxworks.h
+*
+* Contains the cache related functions for VxWorks that is wrapped by
+* xil_cache.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  12/11/09 Initial release
+*
+* 

+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_CACHE_VXWORKS_H
+#define XIL_CACHE_VXWORKS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "vxWorks.h"
+#include "vxLib.h"
+#include "sysLibExtra.h"
+#include "cacheLib.h"
+
+#if (CPU_FAMILY==PPC)
+
+#define Xil_DCacheEnable()		cacheEnable(DATA_CACHE)
+
+#define Xil_DCacheDisable()		cacheDisable(DATA_CACHE)
+
+#define Xil_DCacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_DCacheFlushRange(Addr, Len) \
+		cacheFlush(DATA_CACHE, (void *)(Addr), (Len))
+
+#define Xil_ICacheEnable()		cacheEnable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheDisable()		cacheDisable(INSTRUCTION_CACHE)
+
+#define Xil_ICacheInvalidateRange(Addr, Len) \
+		cacheInvalidate(INSTRUCTION_CACHE, (void *)(Addr), (Len))
+
+
+#else
+#error "Unknown processor / architecture. Must be PPC for VxWorks."
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c
new file mode 100644
index 000000000..f41976eec
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.c
@@ -0,0 +1,218 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xil_exception.c
+*
+* This file contains low-level driver functions for the Cortex R5 exception
+* Handler.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xpseudo_asm.h"
+#include "xdebug.h"
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef struct {
+	Xil_ExceptionHandler Handler;
+	void *Data;
+} XExc_VectorTableEntry;
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+static void Xil_ExceptionNullHandler(void *Data);
+/************************** Variable Definitions *****************************/
+/*
+ * Exception vector table to store handlers for each exception vector.
+ */
+XExc_VectorTableEntry XExc_VectorTable[XIL_EXCEPTION_ID_LAST + 1] =
+{
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_PrefetchAbortHandler, NULL},
+	{Xil_DataAbortHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+	{Xil_ExceptionNullHandler, NULL},
+};
+
+/*****************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function is a stub Handler that is the default Handler that gets called
+* if the application has not setup a Handler for a specific  exception. The
+* function interface has to match the interface specified for a Handler even
+* though none of the arguments are used.
+*
+* @param	Data is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void Xil_ExceptionNullHandler(void *Data)
+{
+	(void *)Data;
+DieLoop: goto DieLoop;
+}
+
+/****************************************************************************/
+/**
+* The function is a common API used to initialize exception handlers across all
+* processors supported. For ARM CortexR5, the exception handlers are being
+* initialized statically and hence this function does not do anything.
+*
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xil_ExceptionInit(void)
+{
+	return;
+}
+
+/*****************************************************************************/
+/**
+*
+* Makes the connection between the Id of the exception source and the
+* associated Handler that is to run when the exception is recognized. The
+* argument provided in this call as the Data is used as the argument
+* for the Handler when it is called.
+*
+* @param	exception_id contains the ID of the exception source and should
+*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+		See xil_exception_l.h for further information.
+* @param	Handler to the Handler for that exception.
+* @param	Data is a reference to Data that will be passed to the
+*		Handler when it gets called.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRegisterHandler(u32 Exception_id,
+				    Xil_ExceptionHandler Handler,
+				    void *Data)
+{
+	XExc_VectorTable[Exception_id].Handler = Handler;
+	XExc_VectorTable[Exception_id].Data = Data;
+}
+
+/*****************************************************************************/
+/**
+*
+* Removes the Handler for a specific exception Id. The stub Handler is then
+* registered for this exception Id.
+*
+* @param	exception_id contains the ID of the exception source and should
+*		be in the range of 0 to XIL_EXCEPTION_ID_LAST.
+*		See xil_exception_l.h for further information.
+
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_ExceptionRemoveHandler(u32 Exception_id)
+{
+	Xil_ExceptionRegisterHandler(Exception_id,
+				       Xil_ExceptionNullHandler,
+				       NULL);
+}
+/*****************************************************************************/
+/**
+*
+* Default Data abort handler which prints a debug message on console if
+* Debug flag is enabled
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+
+void Xil_DataAbortHandler(void *CallBackRef){
+
+	xdbg_printf(XDBG_DEBUG_ERROR, "Data abort \n");
+	while(1) {
+		;
+	}
+}
+
+/*****************************************************************************/
+/**
+*
+* Default Prefetch abort handler which printsa debug message on console if
+* Debug flag is enabled
+*
+* @param	None
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void Xil_PrefetchAbortHandler(void *CallBackRef){
+
+	xdbg_printf(XDBG_DEBUG_ERROR, "Prefetch abort \n");
+	while(1) {
+		;
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h
new file mode 100644
index 000000000..9d903175c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_exception.h
@@ -0,0 +1,215 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_exception.h
+*
+* This header file contains ARM Cortex R5 specific exception related APIs.
+* For exception related functions that can be used across all Xilinx supported
+* processors, please use xil_exception.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  02/20/14 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_EXCEPTION_H /* prevent circular inclusions */
+#define XIL_EXCEPTION_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions ****************************/
+
+#define XIL_EXCEPTION_FIQ	XREG_CPSR_FIQ_ENABLE
+#define XIL_EXCEPTION_IRQ	XREG_CPSR_IRQ_ENABLE
+#define XIL_EXCEPTION_ALL	(XREG_CPSR_FIQ_ENABLE | XREG_CPSR_IRQ_ENABLE)
+
+#define XIL_EXCEPTION_ID_FIRST			0U
+#define XIL_EXCEPTION_ID_RESET			0U
+#define XIL_EXCEPTION_ID_UNDEFINED_INT		1U
+#define XIL_EXCEPTION_ID_SWI_INT		2U
+#define XIL_EXCEPTION_ID_PREFETCH_ABORT_INT	3U
+#define XIL_EXCEPTION_ID_DATA_ABORT_INT		4U
+#define XIL_EXCEPTION_ID_IRQ_INT		5U
+#define XIL_EXCEPTION_ID_FIQ_INT		6U
+#define XIL_EXCEPTION_ID_LAST			6U
+
+/*
+ * XIL_EXCEPTION_ID_INT is defined for all Xilinx processors.
+ */
+#define XIL_EXCEPTION_ID_INT	XIL_EXCEPTION_ID_IRQ_INT
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef is the exception handler function.
+ */
+typedef void (*Xil_ExceptionHandler)(void *data);
+typedef void (*Xil_InterruptHandler)(void *data);
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Enable Exceptions.
+*
+* @param	Mask for exceptions to be enabled.
+*
+* @return	None.
+*
+* @note		If bit is 0, exception is enabled.
+*		C-Style signature: void Xil_ExceptionEnableMask(Mask)
+*
+******************************************************************************/
+#define Xil_ExceptionEnableMask(Mask)	\
+		mtcpsr(mfcpsr() & ~ ((Mask) & XIL_EXCEPTION_ALL))
+
+
+/****************************************************************************/
+/**
+* Enable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionEnable() \
+		Xil_ExceptionEnableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* Disable Exceptions.
+*
+* @param	Mask for exceptions to be enabled.
+*
+* @return	None.
+*
+* @note		If bit is 1, exception is disabled.
+*		C-Style signature: Xil_ExceptionDisableMask(Mask)
+*
+******************************************************************************/
+#define Xil_ExceptionDisableMask(Mask)	\
+		mtcpsr(mfcpsr() | ((Mask) & XIL_EXCEPTION_ALL))
+
+/****************************************************************************/
+/**
+* Disable the IRQ exception.
+*
+* @return   None.
+*
+* @note     None.
+*
+******************************************************************************/
+#define Xil_ExceptionDisable() \
+		Xil_ExceptionDisableMask(XIL_EXCEPTION_IRQ)
+
+/****************************************************************************/
+/**
+* Enable nested interrupts by clearing the I and F bits it CPSR
+*
+* @return   None.
+*
+* @note     This macro is supposed to be used from interrupt handlers. In the
+*			interrupt handler the interrupts are disabled by default (I and F
+*			are 1). To allow nesting of interrupts, this macro should be
+*			used. It clears the I and F bits by changing the ARM mode to
+*			system mode. Once these bits are cleared and provided the
+*			preemption of interrupt conditions are met in the GIC, nesting of
+*			interrupts will start happening.
+*			Caution: This macro must be used with caution. Before calling this
+*			macro, the user must ensure that the source of the current IRQ
+*			is appropriately cleared. Otherwise, as soon as we clear the I and
+*			F bits, there can be an infinite loop of interrupts with an
+*			eventual crash (all the stack space getting consumed).
+******************************************************************************/
+#define Xil_EnableNestedInterrupts() \
+		__asm__ __volatile__ ("mrs     lr, spsr");  \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x1F"); \
+		__asm__ __volatile__ ("stmfd   sp!, {lr}");
+
+/****************************************************************************/
+/**
+* Disable the nested interrupts by setting the I and F bits.
+*
+* @return   None.
+*
+* @note     This macro is meant to be called in the interrupt service routines.
+*			This macro cannot be used independently. It can only be used when
+*			nesting of interrupts have been enabled by using the macro
+*			Xil_EnableNestedInterrupts(). In a typical flow, the user first
+*			calls the Xil_EnableNestedInterrupts in the ISR at the appropriate
+*			point. The user then must call this macro before exiting the interrupt
+*			service routine. This macro puts the ARM back in IRQ/FIQ mode and
+*			hence sets back the I and F bits.
+******************************************************************************/
+#define Xil_DisableNestedInterrupts() \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}");   \
+		__asm__ __volatile__ ("msr     cpsr_c, #0x92"); \
+		__asm__ __volatile__ ("ldmfd   sp!, {lr}"); \
+		__asm__ __volatile__ ("msr     spsr_cxsf, lr");
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+extern void Xil_ExceptionRegisterHandler(u32 Exception_id,
+					 Xil_ExceptionHandler Handler,
+					 void *Data);
+
+extern void Xil_ExceptionRemoveHandler(u32 Exception_id);
+
+extern void Xil_ExceptionInit(void);
+
+extern void Xil_DataAbortHandler(void *CallBackRef);
+
+extern void Xil_PrefetchAbortHandler(void *CallBackRef);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_EXCEPTION_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_hal.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_hal.h
new file mode 100644
index 000000000..d4434d07f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_hal.h
@@ -0,0 +1,61 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_hal.h
+*
+* Contains all the HAL header files.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+*
+* 

+*
+* @note
+*
+******************************************************************************/
+
+#ifndef XIL_HAL_H
+#define XIL_HAL_H
+
+#include "xil_cache.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+#include "xil_exception.h"
+#include "xil_types.h"
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c
new file mode 100644
index 000000000..90fd22559
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.c
@@ -0,0 +1,380 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.c
+*
+* Contains I/O functions for memory-mapped or non-memory-mapped I/O
+* architectures.  These functions encapsulate Cortex R5 architecture-specific
+* I/O requirements.
+*
+* @note
+*
+* This file contains architecture-dependent code.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+* 

+******************************************************************************/
+
+
+/***************************** Include Files *********************************/
+#include "xil_io.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xpseudo_asm.h"
+#include "xreg_cortexr5.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for an 8-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u8 Xil_In8(INTPTR Addr)
+{
+	return *(volatile u8 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_In16(INTPTR Addr)
+{
+	return *(volatile u16 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the Value read from that address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_In32(INTPTR Addr)
+{
+	return *(volatile u32 *) Addr;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for an 8-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out8(INTPTR Addr, u8 Value)
+{
+	volatile u8 *LocalAddr = (u8 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out16(INTPTR Addr, u16 Value)
+{
+	volatile u16 *LocalAddr = (u16 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out32(INTPTR Addr, u32 Value)
+{
+	volatile u32 *LocalAddr = (u32 *)Addr;
+	*LocalAddr = Value;
+}
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 64-bit memory location by writing the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out64(INTPTR Addr, u64 Value)
+{
+	volatile u64 *LocalAddr = (u64 *)Addr;
+	*LocalAddr = Value;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 64-bit memory location by reading the
+* specified Value to the the specified address.
+*
+* @param	Addr contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+u64 Xil_In64(INTPTR Addr)
+{
+	return *(volatile u64 *) Addr;
+}
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 16-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The byte-swapped Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_In16BE(INTPTR Addr)
+{
+	u16 temp;
+	u16 result;
+
+	temp = Xil_In16(Addr);
+
+	result = Xil_EndianSwap16(temp);
+
+	return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an input operation for a 32-bit memory location by reading from the
+* specified address and returning the byte-swapped Value read from that
+* address.
+*
+* @param	Addr contains the address to perform the input operation
+*		at.
+*
+* @return	The byte-swapped Value read from the specified input address.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_In32BE(INTPTR Addr)
+{
+	u32 temp;
+	u32 result;
+
+	temp = Xil_In32(Addr);
+
+	result = Xil_EndianSwap32(temp);
+
+	return result;
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 16-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param	OutAddress contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out16BE(INTPTR Addr, u16 Value)
+{
+	u16 temp;
+
+	temp = Xil_EndianSwap16(Value);
+
+    Xil_Out16(Addr, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Performs an output operation for a 32-bit memory location by writing the
+* specified Value to the the specified address. The Value is byte-swapped
+* before being written.
+*
+* @param	OutAddress contains the address to perform the output operation
+*		at.
+* @param	Value contains the Value to be output at the specified address.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void Xil_Out32BE(INTPTR Addr, u32 Value)
+{
+	u32 temp;
+
+	temp = Xil_EndianSwap32(Value);
+
+    Xil_Out32(Addr, temp);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 16-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u16 Xil_EndianSwap16(u16 Data)
+{
+	return (u16) (((Data & 0xFF00U) >> 8U) | ((Data & 0x00FFU) << 8U));
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a 32-bit endian converion.
+*
+* @param	Data contains the value to be converted.
+*
+* @return	converted value.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 Xil_EndianSwap32(u32 Data)
+{
+	u16 LoWord;
+	u16 HiWord;
+
+	/* get each of the half words from the 32 bit word */
+
+	LoWord = (u16) (Data & 0x0000FFFFU);
+	HiWord = (u16) ((Data & 0xFFFF0000U) >> 16U);
+
+	/* byte swap each of the 16 bit half words */
+
+	LoWord = (((LoWord & 0xFF00U) >> 8U) | ((LoWord & 0x00FFU) << 8U));
+	HiWord = (((HiWord & 0xFF00U) >> 8U) | ((HiWord & 0x00FFU) << 8U));
+
+	/* swap the half words before returning the value */
+
+	return ((((u32)LoWord) << 16U) | (u32)HiWord);
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.h
new file mode 100644
index 000000000..18cdebf7a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_io.h
@@ -0,0 +1,244 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_io.h
+*
+* This file contains the interface for the general IO component, which
+* encapsulates the Input/Output functions for processors that do not
+* require any special I/O handling.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 02/20/14 First release
+* 

+******************************************************************************/
+
+#ifndef XIL_IO_H           /* prevent circular inclusions */
+#define XIL_IO_H           /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#include "xil_printf.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#if defined __GNUC__
+#  define SYNCHRONIZE_IO	dmb()
+#  define INST_SYNC		isb()
+#  define DATA_SYNC		dsb()
+#else
+#  define SYNCHRONIZE_IO
+#  define INST_SYNC
+#  define DATA_SYNC
+#endif /* __GNUC__ */
+
+/*****************************************************************************/
+/**
+*
+* Perform an big-endian input operation for a 16-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In16LE(Addr) Xil_In16((Addr))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian input operation for a 32-bit memory location
+* by reading from the specified address and returning the Value read from
+* that address.
+*
+* @param	Addr contains the address to perform the input operation at.
+*
+* @return	The Value read from the specified input address with the
+*		proper endianness. The return Value has the same endianness
+*		as that of the processor, i.e. if the processor is
+*		little-engian, the return Value is the byte-swapped Value read
+*		from the address.
+*
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_In32LE(Addr) Xil_In32((Addr))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 16-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out16LE(Addr, Value) Xil_Out16((Addr), (Value))
+
+/*****************************************************************************/
+/**
+*
+* Perform a big-endian output operation for a 32-bit memory location
+* by writing the specified Value to the specified address.
+*
+* @param	Addr contains the address to perform the output operation at.
+* @param	Value contains the Value to be output at the specified address.
+*		The Value has the same endianness as that of the processor.
+*		If the processor is little-endian, the byte-swapped Value is
+*		written to the address.
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Out32LE(Addr, Value) Xil_Out32((Addr), (Value))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from host byte order to network byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htonl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from host byte order to network byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in network byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Htons(Data) Xil_EndianSwap16((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 32-bit number from network byte order to host byte order.
+*
+* @param	Data the 32-bit number to be converted.
+*
+* @return	The converted 32-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohl(Data) Xil_EndianSwap32((Data))
+
+/*****************************************************************************/
+/**
+*
+* Convert a 16-bit number from network byte order to host byte order.
+*
+* @param	Data the 16-bit number to be converted.
+*
+* @return	The converted 16-bit number in host byte order.
+*
+* @note		None.
+*
+******************************************************************************/
+#define Xil_Ntohs(Data) Xil_EndianSwap16((Data))
+
+/************************** Function Prototypes ******************************/
+
+/* The following functions allow the software to be transportable across
+ * processors which may use memory mapped I/O or I/O which is mapped into a
+ * seperate address space.
+ */
+u8 Xil_In8(INTPTR Addr);
+u16 Xil_In16(INTPTR Addr);
+u32 Xil_In32(INTPTR Addr);
+u64 Xil_In64(INTPTR Addr);
+
+void Xil_Out8(INTPTR Addr, u8 Value);
+void Xil_Out16(INTPTR Addr, u16 Value);
+void Xil_Out32(INTPTR Addr, u32 Value);
+void Xil_Out64(INTPTR Addr, u64 Value);
+
+u16 Xil_In16BE(INTPTR Addr);
+u32 Xil_In32BE(INTPTR Addr);
+void Xil_Out16BE(INTPTR Addr, u16 Value);
+void Xil_Out32BE(INTPTR Addr, u32 Value);
+
+u16 Xil_EndianSwap16(u16 Data);
+u32 Xil_EndianSwap32(u32 Data);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_macroback.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_macroback.h
new file mode 100644
index 000000000..ebafde87d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_macroback.h
@@ -0,0 +1,1052 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*********************************************************************/
+/**
+ * @file xil_macroback.h
+ *
+ * This header file is meant to bring back the removed _m macros.
+ * This header file must be included last.
+ * The following macros are not defined here due to the driver change:
+ *   XGpio_mSetDataDirection
+ *   XGpio_mGetDataReg
+ *   XGpio_mSetDataReg
+ *   XIIC_RESET
+ *   XIIC_CLEAR_STATS
+ *   XSpi_mReset
+ *   XSysAce_mSetCfgAddr
+ *   XSysAce_mIsCfgDone
+ *   XTft_mSetPixel
+ *   XTft_mGetPixel
+ *   XWdtTb_mEnableWdt
+ *   XWdtTb_mDisbleWdt
+ *   XWdtTb_mRestartWdt
+ *   XWdtTb_mGetTimebaseReg
+ *   XWdtTb_mHasReset
+ *
+ * Please refer the corresonding driver document for replacement.
+ *
+ *********************************************************************/
+
+#ifndef XIL_MACROBACK_H
+#define XIL_MACROBACK_H
+
+/*********************************************************************/
+/**
+ * Macros for Driver XCan
+ *
+ *********************************************************************/
+#ifndef XCan_mReadReg
+#define XCan_mReadReg XCan_ReadReg
+#endif
+
+#ifndef XCan_mWriteReg
+#define XCan_mWriteReg XCan_WriteReg
+#endif
+
+#ifndef XCan_mIsTxDone
+#define XCan_mIsTxDone XCan_IsTxDone
+#endif
+
+#ifndef XCan_mIsTxFifoFull
+#define XCan_mIsTxFifoFull XCan_IsTxFifoFull
+#endif
+
+#ifndef XCan_mIsHighPriorityBufFull
+#define XCan_mIsHighPriorityBufFull XCan_IsHighPriorityBufFull
+#endif
+
+#ifndef XCan_mIsRxEmpty
+#define XCan_mIsRxEmpty XCan_IsRxEmpty
+#endif
+
+#ifndef XCan_mIsAcceptFilterBusy
+#define XCan_mIsAcceptFilterBusy XCan_IsAcceptFilterBusy
+#endif
+
+#ifndef XCan_mCreateIdValue
+#define XCan_mCreateIdValue XCan_CreateIdValue
+#endif
+
+#ifndef XCan_mCreateDlcValue
+#define XCan_mCreateDlcValue XCan_CreateDlcValue
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDmaCentral
+ *
+ *********************************************************************/
+#ifndef XDmaCentral_mWriteReg
+#define XDmaCentral_mWriteReg XDmaCentral_WriteReg
+#endif
+
+#ifndef XDmaCentral_mReadReg
+#define XDmaCentral_mReadReg XDmaCentral_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsAdc
+ *
+ *********************************************************************/
+#ifndef XDsAdc_mWriteReg
+#define XDsAdc_mWriteReg XDsAdc_WriteReg
+#endif
+
+#ifndef XDsAdc_mReadReg
+#define XDsAdc_mReadReg XDsAdc_ReadReg
+#endif
+
+#ifndef XDsAdc_mIsEmpty
+#define XDsAdc_mIsEmpty XDsAdc_IsEmpty
+#endif
+
+#ifndef XDsAdc_mSetFstmReg
+#define XDsAdc_mSetFstmReg XDsAdc_SetFstmReg
+#endif
+
+#ifndef XDsAdc_mGetFstmReg
+#define XDsAdc_mGetFstmReg XDsAdc_GetFstmReg
+#endif
+
+#ifndef XDsAdc_mEnableConversion
+#define XDsAdc_mEnableConversion XDsAdc_EnableConversion
+#endif
+
+#ifndef XDsAdc_mDisableConversion
+#define XDsAdc_mDisableConversion XDsAdc_DisableConversion
+#endif
+
+#ifndef XDsAdc_mGetFifoOccyReg
+#define XDsAdc_mGetFifoOccyReg XDsAdc_GetFifoOccyReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XDsDac
+ *
+ *********************************************************************/
+#ifndef XDsDac_mWriteReg
+#define XDsDac_mWriteReg XDsDac_WriteReg
+#endif
+
+#ifndef XDsDac_mReadReg
+#define XDsDac_mReadReg XDsDac_ReadReg
+#endif
+
+#ifndef XDsDac_mIsEmpty
+#define XDsDac_mIsEmpty XDsDac_IsEmpty
+#endif
+
+#ifndef XDsDac_mFifoIsFull
+#define XDsDac_mFifoIsFull XDsDac_FifoIsFull
+#endif
+
+#ifndef XDsDac_mGetVacancy
+#define XDsDac_mGetVacancy XDsDac_GetVacancy
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XEmacLite
+ *
+ *********************************************************************/
+#ifndef XEmacLite_mReadReg
+#define XEmacLite_mReadReg XEmacLite_ReadReg
+#endif
+
+#ifndef XEmacLite_mWriteReg
+#define XEmacLite_mWriteReg XEmacLite_WriteReg
+#endif
+
+#ifndef XEmacLite_mGetTxStatus
+#define XEmacLite_mGetTxStatus XEmacLite_GetTxStatus
+#endif
+
+#ifndef XEmacLite_mSetTxStatus
+#define XEmacLite_mSetTxStatus XEmacLite_SetTxStatus
+#endif
+
+#ifndef XEmacLite_mGetRxStatus
+#define XEmacLite_mGetRxStatus XEmacLite_GetRxStatus
+#endif
+
+#ifndef XEmacLite_mSetRxStatus
+#define XEmacLite_mSetRxStatus XEmacLite_SetRxStatus
+#endif
+
+#ifndef XEmacLite_mIsTxDone
+#define XEmacLite_mIsTxDone XEmacLite_IsTxDone
+#endif
+
+#ifndef XEmacLite_mIsRxEmpty
+#define XEmacLite_mIsRxEmpty XEmacLite_IsRxEmpty
+#endif
+
+#ifndef XEmacLite_mNextTransmitAddr
+#define XEmacLite_mNextTransmitAddr XEmacLite_NextTransmitAddr
+#endif
+
+#ifndef XEmacLite_mNextReceiveAddr
+#define XEmacLite_mNextReceiveAddr XEmacLite_NextReceiveAddr
+#endif
+
+#ifndef XEmacLite_mIsMdioConfigured
+#define XEmacLite_mIsMdioConfigured XEmacLite_IsMdioConfigured
+#endif
+
+#ifndef XEmacLite_mIsLoopbackConfigured
+#define XEmacLite_mIsLoopbackConfigured XEmacLite_IsLoopbackConfigured
+#endif
+
+#ifndef XEmacLite_mGetReceiveDataLength
+#define XEmacLite_mGetReceiveDataLength XEmacLite_GetReceiveDataLength
+#endif
+
+#ifndef XEmacLite_mGetTxActive
+#define XEmacLite_mGetTxActive XEmacLite_GetTxActive
+#endif
+
+#ifndef XEmacLite_mSetTxActive
+#define XEmacLite_mSetTxActive XEmacLite_SetTxActive
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XGpio
+ *
+ *********************************************************************/
+#ifndef XGpio_mWriteReg
+#define XGpio_mWriteReg XGpio_WriteReg
+#endif
+
+#ifndef XGpio_mReadReg
+#define XGpio_mReadReg XGpio_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XHwIcap
+ *
+ *********************************************************************/
+#ifndef XHwIcap_mFifoWrite
+#define XHwIcap_mFifoWrite XHwIcap_FifoWrite
+#endif
+
+#ifndef XHwIcap_mFifoRead
+#define XHwIcap_mFifoRead XHwIcap_FifoRead
+#endif
+
+#ifndef XHwIcap_mSetSizeReg
+#define XHwIcap_mSetSizeReg XHwIcap_SetSizeReg
+#endif
+
+#ifndef XHwIcap_mGetControlReg
+#define XHwIcap_mGetControlReg XHwIcap_GetControlReg
+#endif
+
+#ifndef XHwIcap_mStartConfig
+#define XHwIcap_mStartConfig XHwIcap_StartConfig
+#endif
+
+#ifndef XHwIcap_mStartReadBack
+#define XHwIcap_mStartReadBack XHwIcap_StartReadBack
+#endif
+
+#ifndef XHwIcap_mGetStatusReg
+#define XHwIcap_mGetStatusReg XHwIcap_GetStatusReg
+#endif
+
+#ifndef XHwIcap_mIsTransferDone
+#define XHwIcap_mIsTransferDone XHwIcap_IsTransferDone
+#endif
+
+#ifndef XHwIcap_mIsDeviceBusy
+#define XHwIcap_mIsDeviceBusy XHwIcap_IsDeviceBusy
+#endif
+
+#ifndef XHwIcap_mIntrGlobalEnable
+#define XHwIcap_mIntrGlobalEnable XHwIcap_IntrGlobalEnable
+#endif
+
+#ifndef XHwIcap_mIntrGlobalDisable
+#define XHwIcap_mIntrGlobalDisable XHwIcap_IntrGlobalDisable
+#endif
+
+#ifndef XHwIcap_mIntrGetStatus
+#define XHwIcap_mIntrGetStatus XHwIcap_IntrGetStatus
+#endif
+
+#ifndef XHwIcap_mIntrDisable
+#define XHwIcap_mIntrDisable XHwIcap_IntrDisable
+#endif
+
+#ifndef XHwIcap_mIntrEnable
+#define XHwIcap_mIntrEnable XHwIcap_IntrEnable
+#endif
+
+#ifndef XHwIcap_mIntrGetEnabled
+#define XHwIcap_mIntrGetEnabled XHwIcap_IntrGetEnabled
+#endif
+
+#ifndef XHwIcap_mIntrClear
+#define XHwIcap_mIntrClear XHwIcap_IntrClear
+#endif
+
+#ifndef XHwIcap_mGetWrFifoVacancy
+#define XHwIcap_mGetWrFifoVacancy XHwIcap_GetWrFifoVacancy
+#endif
+
+#ifndef XHwIcap_mGetRdFifoOccupancy
+#define XHwIcap_mGetRdFifoOccupancy XHwIcap_GetRdFifoOccupancy
+#endif
+
+#ifndef XHwIcap_mSliceX2Col
+#define XHwIcap_mSliceX2Col XHwIcap_SliceX2Col
+#endif
+
+#ifndef XHwIcap_mSliceY2Row
+#define XHwIcap_mSliceY2Row XHwIcap_SliceY2Row
+#endif
+
+#ifndef XHwIcap_mSliceXY2Slice
+#define XHwIcap_mSliceXY2Slice XHwIcap_SliceXY2Slice
+#endif
+
+#ifndef XHwIcap_mReadReg
+#define XHwIcap_mReadReg XHwIcap_ReadReg
+#endif
+
+#ifndef XHwIcap_mWriteReg
+#define XHwIcap_mWriteReg XHwIcap_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIic
+ *
+ *********************************************************************/
+#ifndef XIic_mReadReg
+#define XIic_mReadReg XIic_ReadReg
+#endif
+
+#ifndef XIic_mWriteReg
+#define XIic_mWriteReg XIic_WriteReg
+#endif
+
+#ifndef XIic_mEnterCriticalRegion
+#define XIic_mEnterCriticalRegion XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIic_mExitCriticalRegion
+#define XIic_mExitCriticalRegion XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_GINTR_DISABLE
+#define XIIC_GINTR_DISABLE XIic_IntrGlobalDisable
+#endif
+
+#ifndef XIIC_GINTR_ENABLE
+#define XIIC_GINTR_ENABLE XIic_IntrGlobalEnable
+#endif
+
+#ifndef XIIC_IS_GINTR_ENABLED
+#define XIIC_IS_GINTR_ENABLED XIic_IsIntrGlobalEnabled
+#endif
+
+#ifndef XIIC_WRITE_IISR
+#define XIIC_WRITE_IISR XIic_WriteIisr
+#endif
+
+#ifndef XIIC_READ_IISR
+#define XIIC_READ_IISR XIic_ReadIisr
+#endif
+
+#ifndef XIIC_WRITE_IIER
+#define XIIC_WRITE_IIER XIic_WriteIier
+#endif
+
+#ifndef XIic_mClearIisr
+#define XIic_mClearIisr XIic_ClearIisr
+#endif
+
+#ifndef XIic_mSend7BitAddress
+#define XIic_mSend7BitAddress XIic_Send7BitAddress
+#endif
+
+#ifndef XIic_mDynSend7BitAddress
+#define XIic_mDynSend7BitAddress XIic_DynSend7BitAddress
+#endif
+
+#ifndef XIic_mDynSendStartStopAddress
+#define XIic_mDynSendStartStopAddress XIic_DynSendStartStopAddress
+#endif
+
+#ifndef XIic_mDynSendStop
+#define XIic_mDynSendStop XIic_DynSendStop
+#endif
+
+#ifndef XIic_mSend10BitAddrByte1
+#define XIic_mSend10BitAddrByte1 XIic_Send10BitAddrByte1
+#endif
+
+#ifndef XIic_mSend10BitAddrByte2
+#define XIic_mSend10BitAddrByte2 XIic_Send10BitAddrByte2
+#endif
+
+#ifndef XIic_mSend7BitAddr
+#define XIic_mSend7BitAddr XIic_Send7BitAddr
+#endif
+
+#ifndef XIic_mDisableIntr
+#define XIic_mDisableIntr XIic_DisableIntr
+#endif
+
+#ifndef XIic_mEnableIntr
+#define XIic_mEnableIntr XIic_EnableIntr
+#endif
+
+#ifndef XIic_mClearIntr
+#define XIic_mClearIntr XIic_ClearIntr
+#endif
+
+#ifndef XIic_mClearEnableIntr
+#define XIic_mClearEnableIntr XIic_ClearEnableIntr
+#endif
+
+#ifndef XIic_mFlushRxFifo
+#define XIic_mFlushRxFifo XIic_FlushRxFifo
+#endif
+
+#ifndef XIic_mFlushTxFifo
+#define XIic_mFlushTxFifo XIic_FlushTxFifo
+#endif
+
+#ifndef XIic_mReadRecvByte
+#define XIic_mReadRecvByte XIic_ReadRecvByte
+#endif
+
+#ifndef XIic_mWriteSendByte
+#define XIic_mWriteSendByte XIic_WriteSendByte
+#endif
+
+#ifndef XIic_mSetControlRegister
+#define XIic_mSetControlRegister XIic_SetControlRegister
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XIntc
+ *
+ *********************************************************************/
+#ifndef XIntc_mMasterEnable
+#define XIntc_mMasterEnable XIntc_MasterEnable
+#endif
+
+#ifndef XIntc_mMasterDisable
+#define XIntc_mMasterDisable XIntc_MasterDisable
+#endif
+
+#ifndef XIntc_mEnableIntr
+#define XIntc_mEnableIntr XIntc_EnableIntr
+#endif
+
+#ifndef XIntc_mDisableIntr
+#define XIntc_mDisableIntr XIntc_DisableIntr
+#endif
+
+#ifndef XIntc_mAckIntr
+#define XIntc_mAckIntr XIntc_AckIntr
+#endif
+
+#ifndef XIntc_mGetIntrStatus
+#define XIntc_mGetIntrStatus XIntc_GetIntrStatus
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XLlDma
+ *
+ *********************************************************************/
+#ifndef XLlDma_mBdRead
+#define XLlDma_mBdRead XLlDma_BdRead
+#endif
+
+#ifndef XLlDma_mBdWrite
+#define XLlDma_mBdWrite XLlDma_BdWrite
+#endif
+
+#ifndef XLlDma_mWriteReg
+#define XLlDma_mWriteReg XLlDma_WriteReg
+#endif
+
+#ifndef XLlDma_mReadReg
+#define XLlDma_mReadReg XLlDma_ReadReg
+#endif
+
+#ifndef XLlDma_mBdClear
+#define XLlDma_mBdClear XLlDma_BdClear
+#endif
+
+#ifndef XLlDma_mBdSetStsCtrl
+#define XLlDma_mBdSetStsCtrl XLlDma_BdSetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdGetStsCtrl
+#define XLlDma_mBdGetStsCtrl XLlDma_BdGetStsCtrl
+#endif
+
+#ifndef XLlDma_mBdSetLength
+#define XLlDma_mBdSetLength XLlDma_BdSetLength
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mBdSetId
+#define XLlDma_mBdSetId XLlDma_BdSetId
+#endif
+
+#ifndef XLlDma_mBdGetId
+#define XLlDma_mBdGetId XLlDma_BdGetId
+#endif
+
+#ifndef XLlDma_mBdSetBufAddr
+#define XLlDma_mBdSetBufAddr XLlDma_BdSetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetBufAddr
+#define XLlDma_mBdGetBufAddr XLlDma_BdGetBufAddr
+#endif
+
+#ifndef XLlDma_mBdGetLength
+#define XLlDma_mBdGetLength XLlDma_BdGetLength
+#endif
+
+#ifndef XLlDma_mGetTxRing
+#define XLlDma_mGetTxRing XLlDma_GetTxRing
+#endif
+
+#ifndef XLlDma_mGetRxRing
+#define XLlDma_mGetRxRing XLlDma_GetRxRing
+#endif
+
+#ifndef XLlDma_mGetCr
+#define XLlDma_mGetCr XLlDma_GetCr
+#endif
+
+#ifndef XLlDma_mSetCr
+#define XLlDma_mSetCr XLlDma_SetCr
+#endif
+
+#ifndef XLlDma_mBdRingCntCalc
+#define XLlDma_mBdRingCntCalc XLlDma_BdRingCntCalc
+#endif
+
+#ifndef XLlDma_mBdRingMemCalc
+#define XLlDma_mBdRingMemCalc XLlDma_BdRingMemCalc
+#endif
+
+#ifndef XLlDma_mBdRingGetCnt
+#define XLlDma_mBdRingGetCnt XLlDma_BdRingGetCnt
+#endif
+
+#ifndef XLlDma_mBdRingGetFreeCnt
+#define XLlDma_mBdRingGetFreeCnt XLlDma_BdRingGetFreeCnt
+#endif
+
+#ifndef XLlDma_mBdRingSnapShotCurrBd
+#define XLlDma_mBdRingSnapShotCurrBd XLlDma_BdRingSnapShotCurrBd
+#endif
+
+#ifndef XLlDma_mBdRingNext
+#define XLlDma_mBdRingNext XLlDma_BdRingNext
+#endif
+
+#ifndef XLlDma_mBdRingPrev
+#define XLlDma_mBdRingPrev XLlDma_BdRingPrev
+#endif
+
+#ifndef XLlDma_mBdRingGetSr
+#define XLlDma_mBdRingGetSr XLlDma_BdRingGetSr
+#endif
+
+#ifndef XLlDma_mBdRingSetSr
+#define XLlDma_mBdRingSetSr XLlDma_BdRingSetSr
+#endif
+
+#ifndef XLlDma_mBdRingGetCr
+#define XLlDma_mBdRingGetCr XLlDma_BdRingGetCr
+#endif
+
+#ifndef XLlDma_mBdRingSetCr
+#define XLlDma_mBdRingSetCr XLlDma_BdRingSetCr
+#endif
+
+#ifndef XLlDma_mBdRingBusy
+#define XLlDma_mBdRingBusy XLlDma_BdRingBusy
+#endif
+
+#ifndef XLlDma_mBdRingIntEnable
+#define XLlDma_mBdRingIntEnable XLlDma_BdRingIntEnable
+#endif
+
+#ifndef XLlDma_mBdRingIntDisable
+#define XLlDma_mBdRingIntDisable XLlDma_BdRingIntDisable
+#endif
+
+#ifndef XLlDma_mBdRingIntGetEnabled
+#define XLlDma_mBdRingIntGetEnabled XLlDma_BdRingIntGetEnabled
+#endif
+
+#ifndef XLlDma_mBdRingGetIrq
+#define XLlDma_mBdRingGetIrq XLlDma_BdRingGetIrq
+#endif
+
+#ifndef XLlDma_mBdRingAckIrq
+#define XLlDma_mBdRingAckIrq XLlDma_BdRingAckIrq
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMbox
+ *
+ *********************************************************************/
+#ifndef XMbox_mWriteReg
+#define XMbox_mWriteReg XMbox_WriteReg
+#endif
+
+#ifndef XMbox_mReadReg
+#define XMbox_mReadReg XMbox_ReadReg
+#endif
+
+#ifndef XMbox_mWriteMBox
+#define XMbox_mWriteMBox XMbox_WriteMBox
+#endif
+
+#ifndef XMbox_mReadMBox
+#define XMbox_mReadMBox XMbox_ReadMBox
+#endif
+
+#ifndef XMbox_mFSLReadMBox
+#define XMbox_mFSLReadMBox XMbox_FSLReadMBox
+#endif
+
+#ifndef XMbox_mFSLWriteMBox
+#define XMbox_mFSLWriteMBox XMbox_FSLWriteMBox
+#endif
+
+#ifndef XMbox_mFSLIsEmpty
+#define XMbox_mFSLIsEmpty XMbox_FSLIsEmpty
+#endif
+
+#ifndef XMbox_mFSLIsFull
+#define XMbox_mFSLIsFull XMbox_FSLIsFull
+#endif
+
+#ifndef XMbox_mIsEmpty
+#define XMbox_mIsEmpty XMbox_IsEmptyHw
+#endif
+
+#ifndef XMbox_mIsFull
+#define XMbox_mIsFull XMbox_IsFullHw
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMpmc
+ *
+ *********************************************************************/
+#ifndef XMpmc_mReadReg
+#define XMpmc_mReadReg XMpmc_ReadReg
+#endif
+
+#ifndef XMpmc_mWriteReg
+#define XMpmc_mWriteReg XMpmc_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XMutex
+ *
+ *********************************************************************/
+#ifndef XMutex_mWriteReg
+#define XMutex_mWriteReg XMutex_WriteReg
+#endif
+
+#ifndef XMutex_mReadReg
+#define XMutex_mReadReg XMutex_ReadReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XPcie
+ *
+ *********************************************************************/
+#ifndef XPcie_mReadReg
+#define XPcie_mReadReg XPcie_ReadReg
+#endif
+
+#ifndef XPcie_mWriteReg
+#define XPcie_mWriteReg XPcie_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSpi
+ *
+ *********************************************************************/
+#ifndef XSpi_mIntrGlobalEnable
+#define XSpi_mIntrGlobalEnable XSpi_IntrGlobalEnable
+#endif
+
+#ifndef XSpi_mIntrGlobalDisable
+#define XSpi_mIntrGlobalDisable XSpi_IntrGlobalDisable
+#endif
+
+#ifndef XSpi_mIsIntrGlobalEnabled
+#define XSpi_mIsIntrGlobalEnabled XSpi_IsIntrGlobalEnabled
+#endif
+
+#ifndef XSpi_mIntrGetStatus
+#define XSpi_mIntrGetStatus XSpi_IntrGetStatus
+#endif
+
+#ifndef XSpi_mIntrClear
+#define XSpi_mIntrClear XSpi_IntrClear
+#endif
+
+#ifndef XSpi_mIntrEnable
+#define XSpi_mIntrEnable XSpi_IntrEnable
+#endif
+
+#ifndef XSpi_mIntrDisable
+#define XSpi_mIntrDisable XSpi_IntrDisable
+#endif
+
+#ifndef XSpi_mIntrGetEnabled
+#define XSpi_mIntrGetEnabled XSpi_IntrGetEnabled
+#endif
+
+#ifndef XSpi_mSetControlReg
+#define XSpi_mSetControlReg XSpi_SetControlReg
+#endif
+
+#ifndef XSpi_mGetControlReg
+#define XSpi_mGetControlReg XSpi_GetControlReg
+#endif
+
+#ifndef XSpi_mGetStatusReg
+#define XSpi_mGetStatusReg XSpi_GetStatusReg
+#endif
+
+#ifndef XSpi_mSetSlaveSelectReg
+#define XSpi_mSetSlaveSelectReg XSpi_SetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mGetSlaveSelectReg
+#define XSpi_mGetSlaveSelectReg XSpi_GetSlaveSelectReg
+#endif
+
+#ifndef XSpi_mEnable
+#define XSpi_mEnable XSpi_Enable
+#endif
+
+#ifndef XSpi_mDisable
+#define XSpi_mDisable XSpi_Disable
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysAce
+ *
+ *********************************************************************/
+#ifndef XSysAce_mGetControlReg
+#define XSysAce_mGetControlReg XSysAce_GetControlReg
+#endif
+
+#ifndef XSysAce_mSetControlReg
+#define XSysAce_mSetControlReg XSysAce_SetControlReg
+#endif
+
+#ifndef XSysAce_mOrControlReg
+#define XSysAce_mOrControlReg XSysAce_OrControlReg
+#endif
+
+#ifndef XSysAce_mAndControlReg
+#define XSysAce_mAndControlReg XSysAce_AndControlReg
+#endif
+
+#ifndef XSysAce_mGetErrorReg
+#define XSysAce_mGetErrorReg XSysAce_GetErrorReg
+#endif
+
+#ifndef XSysAce_mGetStatusReg
+#define XSysAce_mGetStatusReg XSysAce_GetStatusReg
+#endif
+
+#ifndef XSysAce_mWaitForLock
+#define XSysAce_mWaitForLock XSysAce_WaitForLock
+#endif
+
+#ifndef XSysAce_mEnableIntr
+#define XSysAce_mEnableIntr XSysAce_EnableIntr
+#endif
+
+#ifndef XSysAce_mDisableIntr
+#define XSysAce_mDisableIntr XSysAce_DisableIntr
+#endif
+
+#ifndef XSysAce_mIsReadyForCmd
+#define XSysAce_mIsReadyForCmd XSysAce_IsReadyForCmd
+#endif
+
+#ifndef XSysAce_mIsMpuLocked
+#define XSysAce_mIsMpuLocked XSysAce_IsMpuLocked
+#endif
+
+#ifndef XSysAce_mIsIntrEnabled
+#define XSysAce_mIsIntrEnabled XSysAce_IsIntrEnabled
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XSysMon
+ *
+ *********************************************************************/
+#ifndef XSysMon_mIsEventSamplingModeSet
+#define XSysMon_mIsEventSamplingModeSet XSysMon_IsEventSamplingModeSet
+#endif
+
+#ifndef XSysMon_mIsDrpBusy
+#define XSysMon_mIsDrpBusy XSysMon_IsDrpBusy
+#endif
+
+#ifndef XSysMon_mIsDrpLocked
+#define XSysMon_mIsDrpLocked XSysMon_IsDrpLocked
+#endif
+
+#ifndef XSysMon_mRawToTemperature
+#define XSysMon_mRawToTemperature XSysMon_RawToTemperature
+#endif
+
+#ifndef XSysMon_mRawToVoltage
+#define XSysMon_mRawToVoltage XSysMon_RawToVoltage
+#endif
+
+#ifndef XSysMon_mTemperatureToRaw
+#define XSysMon_mTemperatureToRaw XSysMon_TemperatureToRaw
+#endif
+
+#ifndef XSysMon_mVoltageToRaw
+#define XSysMon_mVoltageToRaw XSysMon_VoltageToRaw
+#endif
+
+#ifndef XSysMon_mReadReg
+#define XSysMon_mReadReg XSysMon_ReadReg
+#endif
+
+#ifndef XSysMon_mWriteReg
+#define XSysMon_mWriteReg XSysMon_WriteReg
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XTmrCtr
+ *
+ *********************************************************************/
+#ifndef XTimerCtr_mReadReg
+#define XTimerCtr_mReadReg XTimerCtr_ReadReg
+#endif
+
+#ifndef XTmrCtr_mWriteReg
+#define XTmrCtr_mWriteReg XTmrCtr_WriteReg
+#endif
+
+#ifndef XTmrCtr_mSetControlStatusReg
+#define XTmrCtr_mSetControlStatusReg XTmrCtr_SetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetControlStatusReg
+#define XTmrCtr_mGetControlStatusReg XTmrCtr_GetControlStatusReg
+#endif
+
+#ifndef XTmrCtr_mGetTimerCounterReg
+#define XTmrCtr_mGetTimerCounterReg XTmrCtr_GetTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mSetLoadReg
+#define XTmrCtr_mSetLoadReg XTmrCtr_SetLoadReg
+#endif
+
+#ifndef XTmrCtr_mGetLoadReg
+#define XTmrCtr_mGetLoadReg XTmrCtr_GetLoadReg
+#endif
+
+#ifndef XTmrCtr_mEnable
+#define XTmrCtr_mEnable XTmrCtr_Enable
+#endif
+
+#ifndef XTmrCtr_mDisable
+#define XTmrCtr_mDisable XTmrCtr_Disable
+#endif
+
+#ifndef XTmrCtr_mEnableIntr
+#define XTmrCtr_mEnableIntr XTmrCtr_EnableIntr
+#endif
+
+#ifndef XTmrCtr_mDisableIntr
+#define XTmrCtr_mDisableIntr XTmrCtr_DisableIntr
+#endif
+
+#ifndef XTmrCtr_mLoadTimerCounterReg
+#define XTmrCtr_mLoadTimerCounterReg XTmrCtr_LoadTimerCounterReg
+#endif
+
+#ifndef XTmrCtr_mHasEventOccurred
+#define XTmrCtr_mHasEventOccurred XTmrCtr_HasEventOccurred
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartLite
+ *
+ *********************************************************************/
+#ifndef XUartLite_mUpdateStats
+#define XUartLite_mUpdateStats XUartLite_UpdateStats
+#endif
+
+#ifndef XUartLite_mWriteReg
+#define XUartLite_mWriteReg XUartLite_WriteReg
+#endif
+
+#ifndef XUartLite_mReadReg
+#define XUartLite_mReadReg XUartLite_ReadReg
+#endif
+
+#ifndef XUartLite_mClearStats
+#define XUartLite_mClearStats XUartLite_ClearStats
+#endif
+
+#ifndef XUartLite_mSetControlReg
+#define XUartLite_mSetControlReg XUartLite_SetControlReg
+#endif
+
+#ifndef XUartLite_mGetStatusReg
+#define XUartLite_mGetStatusReg XUartLite_GetStatusReg
+#endif
+
+#ifndef XUartLite_mIsReceiveEmpty
+#define XUartLite_mIsReceiveEmpty XUartLite_IsReceiveEmpty
+#endif
+
+#ifndef XUartLite_mIsTransmitFull
+#define XUartLite_mIsTransmitFull XUartLite_IsTransmitFull
+#endif
+
+#ifndef XUartLite_mIsIntrEnabled
+#define XUartLite_mIsIntrEnabled XUartLite_IsIntrEnabled
+#endif
+
+#ifndef XUartLite_mEnableIntr
+#define XUartLite_mEnableIntr XUartLite_EnableIntr
+#endif
+
+#ifndef XUartLite_mDisableIntr
+#define XUartLite_mDisableIntr XUartLite_DisableIntr
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUartNs550
+ *
+ *********************************************************************/
+#ifndef XUartNs550_mUpdateStats
+#define XUartNs550_mUpdateStats XUartNs550_UpdateStats
+#endif
+
+#ifndef XUartNs550_mReadReg
+#define XUartNs550_mReadReg XUartNs550_ReadReg
+#endif
+
+#ifndef XUartNs550_mWriteReg
+#define XUartNs550_mWriteReg XUartNs550_WriteReg
+#endif
+
+#ifndef XUartNs550_mClearStats
+#define XUartNs550_mClearStats XUartNs550_ClearStats
+#endif
+
+#ifndef XUartNs550_mGetLineStatusReg
+#define XUartNs550_mGetLineStatusReg XUartNs550_GetLineStatusReg
+#endif
+
+#ifndef XUartNs550_mGetLineControlReg
+#define XUartNs550_mGetLineControlReg XUartNs550_GetLineControlReg
+#endif
+
+#ifndef XUartNs550_mSetLineControlReg
+#define XUartNs550_mSetLineControlReg XUartNs550_SetLineControlReg
+#endif
+
+#ifndef XUartNs550_mEnableIntr
+#define XUartNs550_mEnableIntr XUartNs550_EnableIntr
+#endif
+
+#ifndef XUartNs550_mDisableIntr
+#define XUartNs550_mDisableIntr XUartNs550_DisableIntr
+#endif
+
+#ifndef XUartNs550_mIsReceiveData
+#define XUartNs550_mIsReceiveData XUartNs550_IsReceiveData
+#endif
+
+#ifndef XUartNs550_mIsTransmitEmpty
+#define XUartNs550_mIsTransmitEmpty XUartNs550_IsTransmitEmpty
+#endif
+
+/*********************************************************************/
+/**
+ * Macros for Driver XUsb
+ *
+ *********************************************************************/
+#ifndef XUsb_mReadReg
+#define XUsb_mReadReg XUsb_ReadReg
+#endif
+
+#ifndef XUsb_mWriteReg
+#define XUsb_mWriteReg XUsb_WriteReg
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mmu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mmu.h
new file mode 100644
index 000000000..8e43e8227
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mmu.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+* This file only includes xil_mpu.h which contains Xil_SetTlbAttributes API
+* defined for MPU in R5. R5 does not have mmu and for usage of similiar API
+* the file has been created.
+*
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.0	pkp  2/12/15 Initial version
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XIL_MMU_H
+#define XIL_MMU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/***************************** Include Files *********************************/
+
+#include "xil_mpu.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MMU_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.c
new file mode 100644
index 000000000..7c028c515
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.c
@@ -0,0 +1,258 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mpu.c
+*
+* This file provides APIs for enabling/disabling MPU and setting the memory
+* attributes for sections, in the MPU translation table.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_cache.h"
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+#include "xil_mpu.h"
+#include "xdebug.h"
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+static const struct {
+	u64 size;
+	unsigned int encoding;
+}region_size[] = {
+	{ 0x20, REGION_32B },
+	{ 0x40, REGION_64B },
+	{ 0x80, REGION_128B },
+	{ 0x100, REGION_256B },
+	{ 0x200, REGION_512B },
+	{ 0x400, REGION_1K },
+	{ 0x800, REGION_2K },
+	{ 0x1000, REGION_4K },
+	{ 0x2000, REGION_8K },
+	{ 0x4000, REGION_16K },
+	{ 0x8000, REGION_32K },
+	{ 0x10000, REGION_64K },
+	{ 0x20000, REGION_128K },
+	{ 0x40000, REGION_256K },
+	{ 0x80000, REGION_512K },
+	{ 0x100000, REGION_1M },
+	{ 0x200000, REGION_2M },
+	{ 0x400000, REGION_4M },
+	{ 0x800000, REGION_8M },
+	{ 0x1000000, REGION_16M },
+	{ 0x2000000, REGION_32M },
+	{ 0x4000000, REGION_64M },
+	{ 0x8000000, REGION_128M },
+	{ 0x10000000, REGION_256M },
+	{ 0x20000000, REGION_512M },
+	{ 0x40000000, REGION_1G },
+	{ 0x80000000, REGION_2G },
+	{ 0x100000000, REGION_4G },
+};
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************
+*
+* Set the memory attributes for a section of memory with starting address addr
+* of the region size 1MB having attributes attrib
+*
+* @param	addr is the address for which attributes are to be set.
+* @param	attrib specifies the attributes for that memory region.
+* @return	None.
+*
+*
+******************************************************************************/
+void Xil_SetTlbAttributes(INTPTR addr, u32 attrib)
+{
+	INTPTR Localaddr = addr;
+	Localaddr &= (~(0xFFFFFU));
+	/* Setting the MPU region with given attribute with 1MB size */
+	Xil_SetMPURegion(Localaddr, 0x100000, attrib);
+}
+
+/*****************************************************************************
+*
+* Set the memory attributes for a section of memory with starting address addr
+* of the region size size and having attributes attrib
+*
+* @param	addr is the address for which attributes are to be set.
+* @param	size is the size of the region.
+* @param	attrib specifies the attributes for that memory region.
+* @return	None.
+*
+*
+******************************************************************************/
+void Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib)
+{
+	u32 Regionsize = 0;
+	INTPTR Localaddr = addr;
+	u32 NextAvailableMemRegion;
+	unsigned int i;
+
+	Xil_DCacheFlush();
+	Xil_ICacheInvalidate();
+	NextAvailableMemRegion = mfcp(XREG_CP15_MPU_MEMORY_REG_NUMBER);
+	NextAvailableMemRegion++;
+	if (NextAvailableMemRegion > 16) {
+		xdbg_printf(DEBUG, "No regions available\r\n");
+		return;
+	}
+	mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,NextAvailableMemRegion);
+	isb();
+
+	/* Lookup the size.  */
+	for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
+		if (size <= region_size[i].size) {
+			Regionsize = region_size[i].encoding;
+			break;
+		}
+	}
+
+	Localaddr &= ~(region_size[i].size - 1);
+
+	Regionsize <<= 1;
+	Regionsize |= REGION_EN;
+	dsb();
+	mtcp(XREG_CP15_MPU_REG_BASEADDR, Localaddr);	/* Set base address of a region */
+	mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL, attrib);	/* Set the control attribute */
+	mtcp(XREG_CP15_MPU_REG_SIZE_EN, Regionsize);	/* set the region size and enable it*/
+	dsb();
+	isb();
+}
+/*****************************************************************************
+*
+* Enable MPU for Cortex R5 processor. This function invalidates I cache and
+* flush the D Caches before enabling the MPU.
+*
+*
+* @param	None.
+* @return	None.
+*
+******************************************************************************/
+void Xil_EnableMPU(void)
+{
+	u32 CtrlReg, Reg;
+	s32 DCacheStatus=0, ICacheStatus=0;
+	/* enable caches only if they are disabled */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+	if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
+		DCacheStatus=1;
+	}
+	if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
+		ICacheStatus=1;
+	}
+
+	if(DCacheStatus != 0) {
+		Xil_DCacheDisable();
+	}
+	if(ICacheStatus != 0){
+		Xil_ICacheDisable();
+	}
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+	Reg |= 0x00000001U;
+	dsb();
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+	isb();
+	/* enable caches only if they are disabled in routine*/
+	if(DCacheStatus != 0) {
+		Xil_DCacheEnable();
+	}
+	if(ICacheStatus != 0) {
+		Xil_ICacheEnable();
+	}
+}
+
+/*****************************************************************************
+*
+* Disable MPU for Cortex R5 processors. This function invalidates I cache and
+* flush the D Caches before disabling the MPU.
+*
+* @param	None.
+*
+* @return	None.
+*
+******************************************************************************/
+void Xil_DisableMPU(void)
+{
+	u32 CtrlReg, Reg;
+	s32 DCacheStatus=0, ICacheStatus=0;
+	/* enable caches only if they are disabled */
+	CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+	if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
+		DCacheStatus=1;
+	}
+	if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
+		ICacheStatus=1;
+	}
+
+	if(DCacheStatus != 0) {
+		Xil_DCacheDisable();
+	}
+	if(ICacheStatus != 0){
+		Xil_ICacheDisable();
+	}
+
+	mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
+	Reg = mfcp(XREG_CP15_SYS_CONTROL);
+	Reg &= ~(0x00000001U);
+	dsb();
+	mtcp(XREG_CP15_SYS_CONTROL, Reg);
+	isb();
+	/* enable caches only if they are disabled in routine*/
+	if(DCacheStatus != 0) {
+		Xil_DCacheEnable();
+	}
+	if(ICacheStatus != 0) {
+		Xil_ICacheEnable();
+	}
+}
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.h
new file mode 100644
index 000000000..a55be916e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_mpu.h
@@ -0,0 +1,80 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xil_mmu.h
+*
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- ---------------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XIL_MPU_H
+#define XIL_MPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+#include "xil_types.h"
+/***************************** Include Files *********************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+void Xil_SetTlbAttributes(INTPTR Addr, u32 attrib);
+void Xil_EnableMPU(void);
+void Xil_DisableMPU(void);
+void Xil_SetMPURegion(INTPTR addr, u64 size, u32 attrib);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XIL_MPU_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c
new file mode 100644
index 000000000..0f0db4fc9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.c
@@ -0,0 +1,360 @@
+/*---------------------------------------------------*/
+/* Modified from :                                   */
+/* Public Domain version of printf                   */
+/* Rud Merriam, Compsult, Inc. Houston, Tx.          */
+/* For Embedded Systems Programming, 1991            */
+/*                                                   */
+/*---------------------------------------------------*/
+#include "xil_printf.h"
+#include "xil_types.h"
+#include "xil_assert.h"
+#include 
+#include 
+#include 
+
+static void padding( const s32 l_flag,const struct params_s *par);
+static void outs(const charptr lp, struct params_s *par);
+static s32 getnum( charptr* linep);
+
+typedef struct params_s {
+    s32 len;
+    s32 num1;
+    s32 num2;
+    char8 pad_character;
+    s32 do_padding;
+    s32 left_flag;
+    s32 unsigned_flag;
+} params_t;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine puts pad characters into the output  */
+/* buffer.                                           */
+/*                                                   */
+static void padding( const s32 l_flag, const struct params_s *par)
+{
+    s32 i;
+
+    if ((par->do_padding != 0) && (l_flag != 0) && (par->len < par->num1)) {
+		i=(par->len);
+        for (; i<(par->num1); i++) {
+#ifdef STDOUT_BASEADDRESS
+            outbyte( par->pad_character);
+#endif
+		}
+    }
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a string to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+static void outs(const charptr lp, struct params_s *par)
+{
+    charptr LocalPtr;
+	LocalPtr = lp;
+    /* pad on left if needed                         */
+	if(LocalPtr != NULL) {
+		par->len = (s32)strlen( LocalPtr);
+	}
+    padding( !(par->left_flag), par);
+
+    /* Move string to the buffer                     */
+    while (((*LocalPtr) != (char8)0) && ((par->num2) != 0)) {
+		(par->num2)--;
+#ifdef STDOUT_BASEADDRESS
+        outbyte(*LocalPtr);
+		LocalPtr += 1;
+#endif
+}
+
+    /* Pad on right if needed                        */
+    /* CR 439175 - elided next stmt. Seemed bogus.   */
+    /* par->len = strlen( lp)                      */
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine moves a number to the output buffer  */
+/* as directed by the padding and positioning flags. */
+/*                                                   */
+
+static void outnum( const s32 n, const s32 base, struct params_s *par)
+{
+    charptr cp;
+    s32 negative;
+	s32 i;
+    char8 outbuf[32];
+    const char8 digits[] = "0123456789ABCDEF";
+    u32 num;
+    for(i = 0; i<32; i++) {
+	outbuf[i] = '0';
+    }
+
+    /* Check if number is negative                   */
+    if ((par->unsigned_flag == 0) && (base == 10) && (n < 0L)) {
+        negative = 1;
+		num =(-(n));
+    }
+    else{
+        num = n;
+        negative = 0;
+    }
+
+    /* Build number (backwards) in outbuf            */
+    i = 0;
+    do {
+		outbuf[i] = digits[(num % base)];
+		i++;
+		num /= base;
+    } while (num > 0);
+
+    if (negative != 0) {
+		outbuf[i] = '-';
+		i++;
+	}
+
+    outbuf[i] = 0;
+    i--;
+
+    /* Move the converted number to the buffer and   */
+    /* add in the padding where needed.              */
+    par->len = (s32)strlen(outbuf);
+    padding( !(par->left_flag), par);
+    while (&outbuf[i] >= outbuf) {
+#ifdef STDOUT_BASEADDRESS
+	outbyte( outbuf[i] );
+		i--;
+#endif
+}
+    padding( par->left_flag, par);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine gets a number from the format        */
+/* string.                                           */
+/*                                                   */
+static s32 getnum( charptr* linep)
+{
+    s32 n;
+    s32 ResultIsDigit = 0;
+    charptr cptr;
+    n = 0;
+    cptr = *linep;
+	if(cptr != NULL){
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    while (ResultIsDigit != 0) {
+		if(cptr != NULL){
+			n = ((n*10) + (((s32)*cptr) - (s32)'0'));
+			cptr += 1;
+			if(cptr != NULL){
+				ResultIsDigit = isdigit(((s32)*cptr));
+			}
+		}
+		ResultIsDigit = isdigit(((s32)*cptr));
+	}
+    *linep = ((charptr )(cptr));
+    return(n);
+}
+
+/*---------------------------------------------------*/
+/*                                                   */
+/* This routine operates just like a printf/sprintf  */
+/* routine. It outputs a set of data under the       */
+/* control of a formatting string. Not all of the    */
+/* standard C format control are supported. The ones */
+/* provided are primarily those needed for embedded  */
+/* systems work. Primarily the floating point        */
+/* routines are omitted. Other formats could be      */
+/* added easily by following the examples shown for  */
+/* the supported formats.                            */
+/*                                                   */
+
+/* void esp_printf( const func_ptr f_ptr,
+   const charptr ctrl1, ...) */
+void xil_printf( const char8 *ctrl1, ...)
+{
+	s32 Check;
+    s32 long_flag;
+    s32 dot_flag;
+
+    params_t par;
+
+    char8 ch;
+    va_list argp;
+    char8 *ctrl = (char8 *)ctrl1;
+
+    va_start( argp, ctrl1);
+
+    while ((ctrl != NULL) && (*ctrl != (char8)0)) {
+
+        /* move format string chars to buffer until a  */
+        /* format control is found.                    */
+        if (*ctrl != '%') {
+#ifdef STDOUT_BASEADDRESS
+            outbyte(*ctrl);
+			ctrl += 1;
+#endif
+            continue;
+        }
+
+        /* initialize all the flags for this format.   */
+        dot_flag = 0;
+		long_flag = 0;
+        par.unsigned_flag = 0;
+		par.left_flag = 0;
+		par.do_padding = 0;
+        par.pad_character = ' ';
+        par.num2=32767;
+		par.num1=0;
+		par.len=0;
+
+ try_next:
+		if(ctrl != NULL) {
+			ctrl += 1;
+		}
+		if(ctrl != NULL) {
+			ch = *ctrl;
+		}
+		else {
+			ch = *ctrl;
+		}
+
+        if (isdigit((s32)ch) != 0) {
+            if (dot_flag != 0) {
+                par.num2 = getnum(&ctrl);
+			}
+            else {
+                if (ch == '0') {
+                    par.pad_character = '0';
+				}
+				if(ctrl != NULL) {
+			par.num1 = getnum(&ctrl);
+				}
+                par.do_padding = 1;
+            }
+            if(ctrl != NULL) {
+			ctrl -= 1;
+			}
+            goto try_next;
+        }
+
+        switch (tolower((s32)ch)) {
+            case '%':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( '%');
+#endif
+                Check = 1;
+                break;
+
+            case '-':
+                par.left_flag = 1;
+                Check = 0;
+                break;
+
+            case '.':
+                dot_flag = 1;
+                Check = 0;
+                break;
+
+            case 'l':
+                long_flag = 1;
+                Check = 0;
+                break;
+
+            case 'u':
+                par.unsigned_flag = 1;
+                /* fall through */
+            case 'i':
+            case 'd':
+                if ((long_flag != 0) || (ch == 'D')) {
+                    outnum( va_arg(argp, s32), 10L, &par);
+                }
+                else {
+                    outnum( va_arg(argp, s32), 10L, &par);
+                }
+				Check = 1;
+                break;
+            case 'p':
+            case 'X':
+            case 'x':
+                par.unsigned_flag = 1;
+                outnum((s32)va_arg(argp, s32), 16L, &par);
+                Check = 1;
+                break;
+
+            case 's':
+                outs( va_arg( argp, char *), &par);
+                Check = 1;
+                break;
+
+            case 'c':
+#ifdef STDOUT_BASEADDRESS
+                outbyte( va_arg( argp, s32));
+#endif
+                Check = 1;
+                break;
+
+            case '\\':
+                switch (*ctrl) {
+                    case 'a':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x07));
+#endif
+                        break;
+                    case 'h':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x08));
+#endif
+                        break;
+                    case 'r':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x0D));
+#endif
+                        break;
+                    case 'n':
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( ((char8)0x0D));
+                        outbyte( ((char8)0x0A));
+#endif
+                        break;
+                    default:
+#ifdef STDOUT_BASEADDRESS
+                        outbyte( *ctrl);
+#endif
+                        break;
+                }
+                ctrl += 1;
+                Check = 0;
+                break;
+
+            default:
+		Check = 1;
+		break;
+        }
+        if(Check == 1) {
+			if(ctrl != NULL) {
+				ctrl += 1;
+			}
+                continue;
+        }
+        goto try_next;
+    }
+    va_end( argp);
+}
+
+/*---------------------------------------------------*/
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.h
new file mode 100644
index 000000000..2be5c5734
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_printf.h
@@ -0,0 +1,44 @@
+ #ifndef XIL_PRINTF_H
+ #define XIL_PRINTF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include 
+#include 
+#include 
+#include "xil_types.h"
+#include "xparameters.h"
+
+/*----------------------------------------------------*/
+/* Use the following parameter passing structure to   */
+/* make xil_printf re-entrant.                        */
+/*----------------------------------------------------*/
+
+struct params_s;
+
+
+/*---------------------------------------------------*/
+/* The purpose of this routine is to output data the */
+/* same as the standard printf function without the  */
+/* overhead most run-time libraries involve. Usually */
+/* the printf brings in many kilobytes of code and   */
+/* that is unacceptable in most embedded systems.    */
+/*---------------------------------------------------*/
+
+typedef char8* charptr;
+typedef s32 (*func_ptr)(int c);
+
+/*                                                   */
+
+void xil_printf( const char8 *ctrl1, ...);
+void print( const char8 *ptr);
+extern void outbyte (char8 c);
+extern char8 inbyte(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.c
new file mode 100644
index 000000000..a2c4b0bbf
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.c
@@ -0,0 +1,366 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.c
+*
+* Contains utility functions to test cache.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date	 Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/28/09 Initial release
+* 4.1   asa  05/09/14 Ensured that the address uses for cache test is aligned
+*				      cache line.
+* 

+*
+* @note
+*
+* This file contain functions that all operate on HAL.
+*
+******************************************************************************/
+#ifdef __ARM__
+#include "xil_cache.h"
+#include "xil_testcache.h"
+#include "xil_types.h"
+#include "xpseudo_asm.h"
+#ifdef __aarch64__
+#include "xreg_cortexa53.h"
+#else
+#include "xreg_cortexr5.h"
+#endif
+
+#include "xil_types.h"
+
+extern void xil_printf(const char8 *ctrl1, ...);
+
+#define DATA_LENGTH 128
+
+#ifdef __aarch64__
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(64)));
+#else
+static INTPTR Data[DATA_LENGTH] __attribute__ ((aligned(32)));
+#endif
+
+/**
+* Perform DCache range related API test such as Xil_DCacheFlushRange and
+* Xil_DCacheInvalidateRange. This test function writes a constant value
+* to the Data array, flushes the range, writes a new value, then invalidates
+* the corresponding range.
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     - -1 is returned for a failure
+*/
+s32 Xil_TestDCacheRange(void)
+{
+	s32 Index;
+	s32 Status = 0;
+	u32 CtrlReg;
+	INTPTR Value;
+
+	xil_printf("-- Cache Range Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A00505;
+
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    flush range done\r\n");
+
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A00505) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("	Flush worked\r\n");
+	}
+	else {
+		xil_printf("Error: flush dcache range not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+		#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+		#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0C505;
+
+
+
+	Xil_DCacheFlushRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidateRange((INTPTR)Data, DATA_LENGTH * sizeof(INTPTR));
+
+	xil_printf("    invalidate dcache range done\r\n");
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0xA0A0A05;
+	dsb();
+	#ifdef __aarch64__
+			CtrlReg = mfcp(SCTLR_EL3);
+			CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+			mtcp(SCTLR_EL3,CtrlReg);
+	#else
+			CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0xA0A0A05) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+
+	if (!Status) {
+		xil_printf("    Invalidate worked\r\n");
+	}
+	else {
+		xil_printf("Error: Invalidate dcache range not working\r\n");
+	}
+	xil_printf("-- Cache Range Test Complete --\r\n");
+	return Status;
+
+}
+
+/**
+* Perform DCache all related API test such as Xil_DCacheFlush and
+* Xil_DCacheInvalidate. This test function writes a constant value
+* to the Data array, flushes the DCache, writes a new value, then invalidates
+* the DCache.
+*
+* @return
+*     - 0 is returned for a pass
+*     - -1 is returned for a failure
+*/
+s32 Xil_TestDCacheAll(void)
+{
+	s32 Index;
+	s32 Status;
+	INTPTR Value;
+	u32 CtrlReg;
+
+	xil_printf("-- Cache All Test --\n\r");
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50500A0A;
+	xil_printf("    initialize Data done:\r\n");
+
+	Xil_DCacheFlush();
+	xil_printf("    flush all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+
+		if (Value != 0x50500A0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Flush all worked\r\n");
+	}
+	else {
+		xil_printf("Error: Flush dcache all not working\r\n");
+	}
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+			CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+			mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x505FFA0A;
+
+	Xil_DCacheFlush();
+
+
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = Index + 3;
+
+	Xil_DCacheInvalidate();
+
+	xil_printf("    invalidate all done\r\n");
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg &= ~(XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg &= ~(XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	for (Index = 0; Index < DATA_LENGTH; Index++)
+		Data[Index] = 0x50CFA0A;
+	dsb();
+	#ifdef __aarch64__
+		CtrlReg = mfcp(SCTLR_EL3);
+		CtrlReg |= (XREG_CONTROL_DCACHE_BIT);
+		mtcp(SCTLR_EL3,CtrlReg);
+	#else
+		CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
+		CtrlReg |= (XREG_CP15_CONTROL_C_BIT);
+		mtcp(XREG_CP15_SYS_CONTROL, CtrlReg);
+	#endif
+	dsb();
+	Status = 0;
+
+	for (Index = 0; Index < DATA_LENGTH; Index++) {
+		Value = Data[Index];
+		if (Value != 0x50CFA0A) {
+			Status = -1;
+			xil_printf("Data[%d] = %x\r\n", Index, Value);
+			break;
+		}
+	}
+
+	if (!Status) {
+		xil_printf("    Invalidate all worked\r\n");
+	}
+	else {
+			xil_printf("Error: Invalidate dcache all not working\r\n");
+	}
+
+	xil_printf("-- DCache all Test Complete --\n\r");
+
+	return Status;
+}
+
+
+/**
+* Perform Xil_ICacheInvalidateRange() on a few function pointers.
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     The function will hang if it fails.
+*/
+s32 Xil_TestICacheRange(void)
+{
+
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestICacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheRange, 1024);
+	Xil_ICacheInvalidateRange((INTPTR)Xil_TestDCacheAll, 1024);
+
+	xil_printf("-- Invalidate icache range done --\r\n");
+
+	return 0;
+}
+
+/**
+* Perform Xil_ICacheInvalidate().
+*
+* @return
+*
+*     - 0 is returned for a pass
+*     The function will hang if it fails.
+*/
+s32 Xil_TestICacheAll(void)
+{
+	Xil_ICacheInvalidate();
+	xil_printf("-- Invalidate icache all done --\r\n");
+	return 0;
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.h
new file mode 100644
index 000000000..b3c416cd0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testcache.h
@@ -0,0 +1,63 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testcache.h
+*
+* This file contains utility functions to test cache.
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  07/29/09 First release
+*
+******************************************************************************/
+
+#ifndef XIL_TESTCACHE_H	/* prevent circular inclusions */
+#define XIL_TESTCACHE_H	/* by using protection macros */
+
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern s32 Xil_TestDCacheRange(void);
+extern s32 Xil_TestDCacheAll(void);
+extern s32 Xil_TestICacheRange(void);
+extern s32 Xil_TestICacheAll(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.c
new file mode 100644
index 000000000..a68d7652f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.c
@@ -0,0 +1,301 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmemend.c
+*
+* Contains the memory test utility functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testio.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+
+
+/**
+ *
+ * Endian swap a 16-bit word.
+ * @param	Data is the 16-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u16 Swap16(u16 Data)
+{
+	return ((Data >> 8U) & 0x00FFU) | ((Data << 8U) & 0xFF00U);
+}
+
+/**
+ *
+ * Endian swap a 32-bit word.
+ * @param	Data is the 32-bit word to be swapped.
+ * @return	The endian swapped value.
+ *
+ */
+static u32 Swap32(u32 Data)
+{
+	u16 Lo16;
+	u16 Hi16;
+
+	u16 Swap16Lo;
+	u16 Swap16Hi;
+
+	Hi16 = (u16)((Data >> 16U) & 0x0000FFFFU);
+	Lo16 = (u16)(Data & 0x0000FFFFU);
+
+	Swap16Lo = Swap16(Lo16);
+	Swap16Hi = Swap16(Hi16);
+
+	return (((u32)(Swap16Lo)) << 16U) | ((u32)Swap16Hi);
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 8-bit wide register IO test where the register is
+* accessed using Xil_Out8 and Xil_In8, and comparing the reading and writing
+* values.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Length is the Length of the block.
+* @param	Value is the constant used for writting the memory.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value)
+{
+	u8 ValueIn;
+	s32 Index;
+	s32 Status = 0;
+
+	for (Index = 0; Index < Length; Index++) {
+		Xil_Out8((INTPTR)Addr, Value);
+
+		ValueIn = Xil_In8((INTPTR)Addr);
+
+		if ((Value != ValueIn) && (Status == 0)) {
+			Status = -1;
+			break;
+		}
+	}
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 16-bit wide register IO test. Each location is tested
+* by sequentially writing a 16-bit wide register, reading the register, and
+* comparing value. This function tests three kinds of register IO functions,
+* normal register IO, little-endian register IO, and big-endian register IO.
+* When testing little/big-endian IO, the function performs the following
+* sequence, Xil_Out16LE/Xil_Out16BE, Xil_In16, Compare In-Out values,
+* Xil_Out16, Xil_In16LE/Xil_In16BE, Compare In-Out values. Whether to swap the
+* read-in value before comparing is controlled by the 5th argument.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Length is the Length of the block.
+* @param	Value is the constant used for writting the memory.
+* @param	Kind is the test kind. Acceptable values are:
+*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap indicates whether to byte swap the read-in value.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+
+s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap)
+{
+	u16 *TempAddr16;
+	u16 ValueIn = 0U;
+	s32 Index;
+	TempAddr16 = Addr;
+	Xil_AssertNonvoid(TempAddr16 != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out16LE((INTPTR)TempAddr16, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out16BE((INTPTR)TempAddr16, Value);
+			break;
+		default:
+			Xil_Out16((INTPTR)TempAddr16, Value);
+			break;
+		}
+
+		ValueIn = Xil_In16((INTPTR)TempAddr16);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out16((INTPTR)TempAddr16, Value);
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In16LE((INTPTR)TempAddr16);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In16BE((INTPTR)TempAddr16);
+			break;
+		default:
+			ValueIn = Xil_In16((INTPTR)TempAddr16);
+			break;
+		}
+
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap16(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr16 += sizeof(u16);
+	}
+	return 0;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 32-bit wide register IO test. Each location is tested
+* by sequentially writing a 32-bit wide regsiter, reading the register, and
+* comparing value. This function tests three kinds of register IO functions,
+* normal register IO, little-endian register IO, and big-endian register IO.
+* When testing little/big-endian IO, the function perform the following
+* sequence, Xil_Out32LE/Xil_Out32BE, Xil_In32, Compare,
+* Xil_Out32, Xil_In32LE/Xil_In32BE, Compare. Whether to swap the read-in value
+* before comparing is controlled by the 5th argument.
+*
+* @param	Addr is a pointer to the region of memory to be tested.
+* @param	Length is the Length of the block.
+* @param	Value is the constant used for writting the memory.
+* @param	Kind is the test kind. Acceptable values are:
+*		XIL_TESTIO_DEFAULT, XIL_TESTIO_LE, XIL_TESTIO_BE.
+* @param	Swap indicates whether to byte swap the read-in value.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+*****************************************************************************/
+s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap)
+{
+	u32 *TempAddr;
+	u32 ValueIn = 0U;
+	s32 Index;
+	TempAddr = Addr;
+	Xil_AssertNonvoid(TempAddr != NULL);
+
+	for (Index = 0; Index < Length; Index++) {
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			Xil_Out32LE((INTPTR)TempAddr, Value);
+			break;
+		case XIL_TESTIO_BE:
+			Xil_Out32BE((INTPTR)TempAddr, Value);
+			break;
+		default:
+			Xil_Out32((INTPTR)TempAddr, Value);
+			break;
+		}
+
+		ValueIn = Xil_In32((INTPTR)TempAddr);
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+
+		/* second round */
+		Xil_Out32((INTPTR)TempAddr, Value);
+
+
+		switch (Kind) {
+		case XIL_TESTIO_LE:
+			ValueIn = Xil_In32LE((INTPTR)TempAddr);
+			break;
+		case XIL_TESTIO_BE:
+			ValueIn = Xil_In32BE((INTPTR)TempAddr);
+			break;
+		default:
+			ValueIn = Xil_In32((INTPTR)TempAddr);
+			break;
+		}
+
+		if ((Kind != 0) && (Swap != 0)) {
+			ValueIn = Swap32(ValueIn);
+		}
+
+		if (Value != ValueIn) {
+			return -1;
+		}
+		TempAddr += sizeof(u32);
+	}
+	return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.h
new file mode 100644
index 000000000..fba0c1060
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testio.h
@@ -0,0 +1,91 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmemend.h
+*
+* This file contains utility functions to teach endian related memory
+* IO functions.
+*
+* Memory test description
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00 hbm  08/05/09 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_TESTIO_H	/* prevent circular inclusions */
+#define XIL_TESTIO_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+#define XIL_TESTIO_DEFAULT 	0
+#define XIL_TESTIO_LE		1
+#define XIL_TESTIO_BE		2
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+extern s32 Xil_TestIO8(u8 *Addr, s32 Length, u8 Value);
+extern s32 Xil_TestIO16(u16 *Addr, s32 Length, u16 Value, s32 Kind, s32 Swap);
+extern s32 Xil_TestIO32(u32 *Addr, s32 Length, u32 Value, s32 Kind, s32 Swap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.c
new file mode 100644
index 000000000..19a3b6608
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.c
@@ -0,0 +1,882 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.c
+*
+* Contains the memory test utility functions.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xil_testmem.h"
+#include "xil_io.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions ****************************/
+/************************** Function Prototypes *****************************/
+
+static u32 RotateLeft(u32 Input, u8 Width);
+
+/* define ROTATE_RIGHT to give access to this functionality */
+/* #define ROTATE_RIGHT */
+#ifdef ROTATE_RIGHT
+static u32 RotateRight(u32 Input, u8 Width);
+#endif /* ROTATE_RIGHT */
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 32-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - 0 is returned for a pass
+* - -1 is returned for a failure
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u32 Val;
+	u32 FirtVal;
+	u32 WordMem32;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= (u8)XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			*(Addr+I) = Val;
+			Val++;
+		}
+
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			WordMem32 = *(Addr+I);
+
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (1U << j);
+
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u32) RotateLeft(Val, 32U);
+			}
+
+			/*
+			 * Restore the reference 'val' to the
+			 * initial value
+			 */
+			Val = 1U << j;
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+
+				WordMem32 = *(Addr+I);
+
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = (u32)RotateLeft(Val, 32U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible
+		 * initial test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)32; j++) {
+
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = ~(1U << j);
+
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)32; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+
+			Val = ~(1U << j);
+
+			/* Read the values from each location that was
+			 * written */
+			for (I = 0U; I < (u32)32; I++) {
+				/* read memory location */
+				WordMem32 = *(Addr+I);
+				if (WordMem32 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u32)RotateLeft(~Val, 32U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* Read the location */
+			WordMem32 = *(Addr+I);
+			Val = (u32) (~((INTPTR) (&Addr[I])));
+
+			if ((WordMem32 ^ Val) != 0x00000000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u32)0) {
+			Val = 0xDEADBEEFU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+
+			/* read memory location */
+
+			WordMem32 = *(Addr+I);
+			if (WordMem32 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 16-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant Pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u16 Val;
+	u16 FirtVal;
+	u16 WordMem16;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * selectthe proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+
+			Val = (u16)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u16)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u16)RotateLeft(Val, 16U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)16; j++) {
+			/*
+			 * Generate an initial value for walking ones
+			 * test to test for bad
+			 * data bits
+			 */
+
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+
+			for (I = 0U; I < (u32)16; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)16; I++) {
+				/* read memory location */
+				WordMem16 = *(Addr+I);
+				if (WordMem16 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = ~((u16)RotateLeft(~Val, 16U));
+			}
+
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u16) (~((INTPTR)(&Addr[I])));
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			Val = (u16) (~((INTPTR) (&Addr[I])));
+			if ((WordMem16 ^ Val) != 0x0000U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+		if (Pattern == (u16)0) {
+			Val = 0xDEADU;
+		}
+		else {
+			Val = Pattern;
+		}
+
+		/*
+		 * Fill the memory with fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem16 = *(Addr+I);
+			if (WordMem16 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Perform a destructive 8-bit wide memory test.
+*
+* @param    Addr is a pointer to the region of memory to be tested.
+* @param    Words is the length of the block.
+* @param    Pattern is the constant used for the constant pattern test, if 0,
+*           0xDEADBEEF is used.
+* @param    Subtest is the test selected. See xil_testmem.h for possible
+*	    values.
+*
+* @return
+*
+* - -1 is returned for a failure
+* - 0 is returned for a pass
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** Width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+*****************************************************************************/
+s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest)
+{
+	u32 I;
+	u32 j;
+	u8 Val;
+	u8 FirtVal;
+	u8 WordMem8;
+	s32 Status = 0;
+
+	Xil_AssertNonvoid(Words != (u32)0);
+	Xil_AssertNonvoid(Subtest <= XIL_TESTMEM_MAXTEST);
+	Xil_AssertNonvoid(Addr != NULL);
+
+	/*
+	 * variable initialization
+	 */
+	Val = XIL_TESTMEM_INIT_VALUE;
+	FirtVal = XIL_TESTMEM_INIT_VALUE;
+
+	/*
+	 * select the proper Subtest(s)
+	 */
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INCREMENT)) {
+		/*
+		 * Fill the memory with incrementing
+		 * values starting from 'FirtVal'
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+			Val++;
+		}
+		/*
+		 * Restore the reference 'Val' to the
+		 * initial value
+		 */
+		Val = FirtVal;
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the incrementing reference
+		 * Val
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+			Val++;
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKONES)) {
+		/*
+		 * set up to cycle through all possible initial
+		 * test Patterns for walking ones test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test
+			 * to test for bad data bits
+			 */
+			Val = (u8)((u32)1 << j);
+			/*
+			 * START walking ones test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = (u8)((u32)1 << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+				Val = (u8)RotateLeft(Val, 8U);
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_WALKZEROS)) {
+		/*
+		 * set up to cycle through all possible initial test
+		 * Patterns for walking zeros test
+		 */
+
+		for (j = 0U; j < (u32)8; j++) {
+			/*
+			 * Generate an initial value for walking ones test to test
+			 * for bad data bits
+			 */
+			Val = ~(1U << j);
+			/*
+			 * START walking zeros test
+			 * Write a one to each data bit indifferent locations
+			 */
+			for (I = 0U; I < (u32)8; I++) {
+				/* write memory location */
+				*(Addr+I) = Val;
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+			/*
+			 * Restore the reference 'Val' to the
+			 * initial value
+			 */
+			Val = ~(1U << j);
+			/* Read the values from each location that was written */
+			for (I = 0U; I < (u32)8; I++) {
+				/* read memory location */
+				WordMem8 = *(Addr+I);
+				if (WordMem8 != Val) {
+					Status = -1;
+					goto End_Label;
+				}
+
+				Val = ~((u8)RotateLeft(~Val, 8U));
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_INVERSEADDR)) {
+		/* Fill the memory with inverse of address */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			*(Addr+I) = Val;
+		}
+
+		/*
+		 * Check every word within the words
+		 * of tested memory
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			Val = (u8) (~((INTPTR) (&Addr[I])));
+			if ((WordMem8 ^ Val) != 0x00U) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+	if((Subtest == XIL_TESTMEM_ALLMEMTESTS) || (Subtest == XIL_TESTMEM_FIXEDPATTERN)) {
+		/*
+		 * Generate an initial value for
+		 * memory testing
+		 */
+
+		if (Pattern == (u8)0) {
+			Val = 0xA5U;
+		}
+		else {
+			Val = Pattern;
+		}
+		/*
+		 * Fill the memory with fixed Pattern
+		 */
+		for (I = 0U; I < Words; I++) {
+			/* write memory location */
+			*(Addr+I) = Val;
+		}
+		/*
+		 * Check every word within the words
+		 * of tested memory and compare it
+		 * with the fixed Pattern
+		 */
+
+		for (I = 0U; I < Words; I++) {
+			/* read memory location */
+			WordMem8 = *(Addr+I);
+			if (WordMem8 != Val) {
+				Status = -1;
+				goto End_Label;
+			}
+		}
+	}
+
+End_Label:
+	return Status;
+}
+
+
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the left one bit position
+*
+* @param    Input is value to be rotated to the left
+* @param    Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting unsigned long value of the rotate left
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateLeft(u32 Input, u8 Width)
+{
+	u32 Msb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << (u32)1) - (u32)1;
+
+	/*
+	 * set the Width of the Input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	Msb = LocalInput & MsbMask;
+
+	ReturnVal = LocalInput << 1U;
+
+	if (Msb != 0x00000000U) {
+		ReturnVal = ReturnVal | (u32)0x00000001;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+
+#ifdef ROTATE_RIGHT
+/*****************************************************************************/
+/**
+*
+* Rotates the provided value to the right one bit position
+*
+* @param    Input is value to be rotated to the right
+* @param    Width is the number of bits in the input data
+*
+* @return
+*
+* The resulting u32 value of the rotate right
+*
+* @note
+*
+* None.
+*
+*****************************************************************************/
+static u32 RotateRight(u32 Input, u8 Width)
+{
+	u32 Lsb;
+	u32 ReturnVal;
+	u32 WidthMask;
+	u32 MsbMask;
+	u32 LocalInput = Input;
+	/*
+	 * set up the WidthMask and the MsbMask
+	 */
+
+	MsbMask = 1U << (Width - 1U);
+
+	WidthMask = (MsbMask << 1U) - 1U;
+
+	/*
+	 * set the width of the input to the correct width
+	 */
+
+	LocalInput = LocalInput & WidthMask;
+
+	ReturnVal = LocalInput >> 1U;
+
+	Lsb = LocalInput & 0x00000001U;
+
+	if (Lsb != 0x00000000U) {
+		ReturnVal = ReturnVal | MsbMask;
+	}
+
+	ReturnVal = ReturnVal & WidthMask;
+
+	return ReturnVal;
+
+}
+#endif /* ROTATE_RIGHT */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.h
new file mode 100644
index 000000000..4cbfd878b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_testmem.h
@@ -0,0 +1,162 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_testmem.h
+*
+* This file contains utility functions to test memory.
+*
+* Memory test description
+*
+* A subset of the memory tests can be selected or all of the tests can be run
+* in order. If there is an error detected by a subtest, the test stops and the
+* failure code is returned. Further tests are not run even if all of the tests
+* are selected.
+*
+* Subtest descriptions:
+* 
+* XIL_TESTMEM_ALLMEMTESTS:
+*       Runs all of the following tests
+*
+* XIL_TESTMEM_INCREMENT:
+*       Incrementing Value Test.
+*       This test starts at 'XIL_TESTMEM_INIT_VALUE' and uses the
+*	incrementing value as the test value for memory.
+*
+* XIL_TESTMEM_WALKONES:
+*       Walking Ones Test.
+*       This test uses a walking '1' as the test value for memory.
+*       location 1 = 0x00000001
+*       location 2 = 0x00000002
+*       ...
+*
+* XIL_TESTMEM_WALKZEROS:
+*       Walking Zero's Test.
+*       This test uses the inverse value of the walking ones test
+*       as the test value for memory.
+*       location 1 = 0xFFFFFFFE
+*       location 2 = 0xFFFFFFFD
+*       ...
+*
+* XIL_TESTMEM_INVERSEADDR:
+*       Inverse Address Test.
+*       This test uses the inverse of the address of the location under test
+*       as the test value for memory.
+*
+* XIL_TESTMEM_FIXEDPATTERN:
+*       Fixed Pattern Test.
+*       This test uses the provided patters as the test value for memory.
+*       If zero is provided as the pattern the test uses '0xDEADBEEF".
+* 

+*
+* WARNING
+*
+* The tests are DESTRUCTIVE. Run before any initialized memory spaces
+* have been set up.
+*
+* The address provided to the memory tests is not checked for
+* validity except for the NULL case. It is possible to provide a code-space
+* pointer for this test to start with and ultimately destroy executable code
+* causing random failures.
+*
+* @note
+*
+* Used for spaces where the address range of the region is smaller than
+* the data width. If the memory range is greater than 2 ** width,
+* the patterns used in XIL_TESTMEM_WALKONES and XIL_TESTMEM_WALKZEROS will
+* repeat on a boundry of a power of two making it more difficult to detect
+* addressing errors. The XIL_TESTMEM_INCREMENT and XIL_TESTMEM_INVERSEADDR
+* tests suffer the same problem. Ideally, if large blocks of memory are to be
+* tested, break them up into smaller regions of memory to allow the test
+* patterns used not to repeat over the region tested.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver    Who    Date    Changes
+* ----- ---- -------- -----------------------------------------------
+* 1.00a hbm  08/25/09 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_TESTMEM_H	/* prevent circular inclusions */
+#define XIL_TESTMEM_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/* xutil_memtest defines */
+
+#define XIL_TESTMEM_INIT_VALUE	1U
+
+/** @name Memory subtests
+ * @{
+ */
+/**
+ * See the detailed description of the subtests in the file description.
+ */
+#define XIL_TESTMEM_ALLMEMTESTS     0x00U
+#define XIL_TESTMEM_INCREMENT       0x01U
+#define XIL_TESTMEM_WALKONES        0x02U
+#define XIL_TESTMEM_WALKZEROS       0x03U
+#define XIL_TESTMEM_INVERSEADDR     0x04U
+#define XIL_TESTMEM_FIXEDPATTERN    0x05U
+#define XIL_TESTMEM_MAXTEST         XIL_TESTMEM_FIXEDPATTERN
+/* @} */
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+/* xutil_testmem prototypes */
+
+extern s32 Xil_TestMem32(u32 *Addr, u32 Words, u32 Pattern, u8 Subtest);
+extern s32 Xil_TestMem16(u16 *Addr, u32 Words, u16 Pattern, u8 Subtest);
+extern s32 Xil_TestMem8(u8 *Addr, u32 Words, u8 Pattern, u8 Subtest);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_types.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_types.h
new file mode 100644
index 000000000..e8b78b7c6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xil_types.h
@@ -0,0 +1,200 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xil_types.h
+*
+* This file contains basic types for Xilinx software IP.
+
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 1.00a hbm  07/14/09 First release
+* 3.03a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
+* 5.00 	pkp  05/29/14 Made changes for 64 bit architecture
+*	srt  07/14/14 Use standard definitions from stdint.h and stddef.h
+*		      Define LONG and ULONG datatypes and mask values
+* 

+*
+******************************************************************************/
+
+#ifndef XIL_TYPES_H	/* prevent circular inclusions */
+#define XIL_TYPES_H	/* by using protection macros */
+
+#include 
+#include 
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#  define TRUE		1U
+#endif
+
+#ifndef FALSE
+#  define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#define XIL_COMPONENT_IS_READY     0x11111111U  /**< component has been initialized */
+#define XIL_COMPONENT_IS_STARTED   0x22222222U  /**< component has been started */
+
+/** @name New types
+ * New simple types.
+ * @{
+ */
+#ifndef __KERNEL__
+#ifndef XBASIC_TYPES_H
+/**
+ * guarded against xbasic_types.h.
+ */
+typedef uint8_t u8;
+typedef uint16_t u16;
+typedef uint32_t u32;
+
+#define __XUINT64__
+typedef struct
+{
+	u32 Upper;
+	u32 Lower;
+} Xuint64;
+
+
+/*****************************************************************************/
+/**
+* Return the most significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The upper 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_MSW(x) ((x).Upper)
+
+/*****************************************************************************/
+/**
+* Return the least significant half of the 64 bit data type.
+*
+* @param    x is the 64 bit word.
+*
+* @return   The lower 32 bits of the 64 bit word.
+*
+* @note     None.
+*
+******************************************************************************/
+#define XUINT64_LSW(x) ((x).Lower)
+
+#endif /* XBASIC_TYPES_H */
+
+/**
+ * xbasic_types.h does not typedef s* or u64
+ */
+
+typedef char char8;
+typedef int8_t s8;
+typedef int16_t s16;
+typedef int32_t s32;
+typedef int64_t s64;
+typedef uint64_t u64;
+typedef int sint32;
+
+typedef intptr_t INTPTR;
+typedef uintptr_t UINTPTR;
+typedef ptrdiff_t PTRDIFF;
+
+#if !defined(LONG) || !defined(ULONG)
+typedef long LONG;
+typedef unsigned long ULONG;
+#endif
+
+#define ULONG64_HI_MASK	0xFFFFFFFF00000000U
+#define ULONG64_LO_MASK	~ULONG64_HI_MASK
+
+#else
+#include 
+#endif
+
+
+/**
+ * This data type defines an interrupt handler for a device.
+ * The argument points to the instance of the component
+ */
+typedef void (*XInterruptHandler) (void *InstancePtr);
+
+/**
+ * This data type defines an exception handler for a processor.
+ * The argument points to the instance of the component
+ */
+typedef void (*XExceptionHandler) (void *InstancePtr);
+
+/**
+ * UPPER_32_BITS - return bits 32-63 of a number
+ * @n: the number we're accessing
+ *
+ * A basic shift-right of a 64- or 32-bit quantity.  Use this to suppress
+ * the "right shift count >= width of type" warning when that quantity is
+ * 32-bits.
+ */
+#define UPPER_32_BITS(n) ((u32)(((n) >> 16) >> 16))
+
+/**
+ * LOWER_32_BITS - return bits 0-31 of a number
+ * @n: the number we're accessing
+ */
+#define LOWER_32_BITS(n) ((u32)(n))
+
+/*@}*/
+
+
+/************************** Constant Definitions *****************************/
+
+#ifndef TRUE
+#define TRUE		1U
+#endif
+
+#ifndef FALSE
+#define FALSE		0U
+#endif
+
+#ifndef NULL
+#define NULL		0U
+#endif
+
+#endif	/* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h
new file mode 100644
index 000000000..91d6b6408
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xparameters_ps.h
@@ -0,0 +1,358 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xparameters_ps.h
+*
+* This file contains the address definitions for the hard peripherals
+* attached to the ARM Cortex R5 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------- -------- ---------------------------------------------------
+* 5.00  pkp  	02/29/14 Initial version
+* 

+*
+* @note
+*
+* None.
+*
+******************************************************************************/
+
+#ifndef XPARAMETERS_PS_H_
+#define XPARAMETERS_PS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock
+ */
+
+/* Canonical definitions for DDR MEMORY */
+#define XPAR_DDR_MEM_BASEADDR		0x00000000U
+#define XPAR_DDR_MEM_HIGHADDR		0x3FFFFFFFU
+
+/* Canonical definitions for Interrupts  */
+#define XPAR_XUARTPS_0_INTR		XPS_UART0_INT_ID
+#define XPAR_XUARTPS_1_INTR		XPS_UART1_INT_ID
+#define XPAR_XIICPS_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_XIICPS_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_XSPIPS_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_XSPIPS_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_XCANPS_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_XCANPS_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_XGPIOPS_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_XEMACPS_0_INTR		XPS_GEM0_INT_ID
+#define XPAR_XEMACPS_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_XEMACPS_1_INTR		XPS_GEM1_INT_ID
+#define XPAR_XEMACPS_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_XEMACPS_2_INTR		XPS_GEM2_INT_ID
+#define XPAR_XEMACPS_2_WAKE_INTR	XPS_GEM2_WAKE_INT_ID
+#define XPAR_XEMACPS_3_INTR		XPS_GEM3_INT_ID
+#define XPAR_XEMACPS_3_WAKE_INTR	XPS_GEM3_WAKE_INT_ID
+#define XPAR_XSDIOPS_0_INTR		XPS_SDIO0_INT_ID
+#define XPAR_XQSPIPS_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_XSDIOPS_1_INTR		XPS_SDIO1_INT_ID
+#define XPAR_XWDTPS_0_INTR		XPS_WDT_INT_ID
+#define XPAR_XDCFG_0_INTR		XPS_DVC_INT_ID
+#define XPAR_SCUTIMER_INTR		XPS_SCU_TMR_INT_ID
+#define XPAR_SCUWDT_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_XTTCPS_0_INTR		XPS_TTC0_0_INT_ID
+#define XPAR_XTTCPS_1_INTR		XPS_TTC0_1_INT_ID
+#define XPAR_XTTCPS_2_INTR		XPS_TTC0_2_INT_ID
+#define XPAR_XTTCPS_3_INTR		XPS_TTC1_0_INT_ID
+#define XPAR_XTTCPS_4_INTR		XPS_TTC1_1_INT_ID
+#define XPAR_XTTCPS_5_INTR		XPS_TTC1_2_INT_ID
+#define XPAR_XTTCPS_6_INTR		XPS_TTC2_0_INT_ID
+#define XPAR_XTTCPS_7_INTR		XPS_TTC2_1_INT_ID
+#define XPAR_XTTCPS_8_INTR		XPS_TTC2_2_INT_ID
+#define XPAR_XTTCPS_9_INTR		XPS_TTC3_0_INT_ID
+#define XPAR_XTTCPS_10_INTR		XPS_TTC3_1_INT_ID
+#define XPAR_XTTCPS_11_INTR		XPS_TTC3_2_INT_ID
+#define XPAR_XDMAPS_0_FAULT_INTR	XPS_DMA0_ABORT_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_0	XPS_DMA0_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_1	XPS_DMA1_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_2	XPS_DMA2_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_3	XPS_DMA3_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_4	XPS_DMA4_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_5	XPS_DMA5_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_6	XPS_DMA6_INT_ID
+#define XPAR_XDMAPS_0_DONE_INTR_7	XPS_DMA7_INT_ID
+#define XPAR_XNANDPS8_0_INTR        	XPS_NAND_INT_ID
+#define XPAR_XADMAPS_0_INTR 		XPS_ADMA_CH0_INT_ID
+#define XPAR_XADMAPS_1_INTR 		XPS_ADMA_CH1_INT_ID
+#define XPAR_XADMAPS_2_INTR		XPS_ADMA_CH2_INT_ID
+#define XPAR_XADMAPS_3_INTR 		XPS_ADMA_CH3_INT_ID
+#define XPAR_XADMAPS_4_INTR		XPS_ADMA_CH4_INT_ID
+#define XPAR_XADMAPS_5_INTR 		XPS_ADMA_CH5_INT_ID
+#define XPAR_XADMAPS_6_INTR 		XPS_ADMA_CH6_INT_ID
+#define XPAR_XADMAPS_7_INTR 		XPS_ADMA_CH7_INT_ID
+#define XPAR_XCSUDMA_INTR 		XPS_CSU_DMA_INT_ID
+#define XPAR_XMPU_LPD_INTR 		XPS_XMPU_LPD_INT_ID
+#define XPAR_XZDMAPS_0_INTR		XPS_ZDMA_CH0_INT_ID
+#define XPAR_XZDMAPS_1_INTR		XPS_ZDMA_CH1_INT_ID
+#define XPAR_XZDMAPS_2_INTR 		XPS_ZDMA_CH2_INT_ID
+#define XPAR_XZDMAPS_3_INTR 		XPS_ZDMA_CH3_INT_ID
+#define XPAR_XZDMAPS_4_INTR		XPS_ZDMA_CH4_INT_ID
+#define XPAR_XZDMAPS_5_INTR 		XPS_ZDMA_CH5_INT_ID
+#define XPAR_XZDMAPS_6_INTR 		XPS_ZDMA_CH6_INT_ID
+#define XPAR_XZDMAPS_7_INTR 		XPS_ZDMA_CH7_INT_ID
+#define XPAR_XMPU_FPD_INTR 		XPS_XMPU_FPD_INT_ID
+#define XPAR_XCCI_FPD_INTR 		XPS_FPD_CCI_INT_ID
+#define XPAR_XSMMU_FPD_INTR 		XPS_FPD_SMMU_INT_ID
+#define XPAR_XUSBPS_0_INTR		XPS_USB3_0_ENDPT_INT_ID
+#define XPAR_XUSBPS_1_INTR		XPS_USB3_1_ENDPT_INT_ID
+#define	XPAR_XRTCPSU_ALARM_INTR 	XPS_RTC_ALARM_INT_ID
+#define	XPAR_XRTCPSU_SECONDS_INTR	XPS_RTC_SEC_INT_ID
+#define XPAR_XAPMPS_0_INTR		XPS_APM0_INT_ID
+#define XPAR_XAPMPS_1_INTR		XPS_APM1_INT_ID
+#define XPAR_XAPMPS_2_INTR		XPS_APM2_INT_ID
+#define XPAR_XAPMPS_5_INTR		XPS_APM5_INT_ID
+#define XPAR_XSYSMONPSU_INTR		XPS_AMS_INT_ID
+
+/* Canonical definitions for SCU GIC */
+#define XPAR_SCUGIC_NUM_INSTANCES	1U
+#define XPAR_SCUGIC_SINGLE_DEVICE_ID	0U
+#define XPAR_SCUGIC_CPU_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00001000U)
+#define XPAR_SCUGIC_DIST_BASEADDR	(XPS_SCU_PERIPH_BASE + 0x00002000U)
+#define XPAR_SCUGIC_ACK_BEFORE		0U
+
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
+
+
+/*
+ * This block contains constant declarations for the peripherals
+ * within the hardblock. These have been put for bacwards compatibilty
+ */
+
+#define XPS_SYS_CTRL_BASEADDR	0xFF180000U
+#define XPS_SCU_PERIPH_BASE		0xF9000000U
+
+
+/* Shared Peripheral Interrupts (SPI) */
+
+/* FIXME */
+/*#define XPS_FPGA0_INT_ID		100U */
+#define XPS_FPGA1_INT_ID		62U
+#define XPS_FPGA2_INT_ID		63U
+#define XPS_FPGA3_INT_ID		64U
+#define XPS_FPGA4_INT_ID		65U
+#define XPS_FPGA5_INT_ID		66U
+#define XPS_FPGA6_INT_ID		67U
+#define XPS_FPGA7_INT_ID		68U
+#define XPS_DMA4_INT_ID			72U
+#define XPS_DMA5_INT_ID			73U
+#define XPS_DMA6_INT_ID			74U
+#define XPS_DMA7_INT_ID			75U
+#define XPS_FPGA8_INT_ID		84U
+#define XPS_FPGA9_INT_ID		85U
+#define XPS_FPGA10_INT_ID		86U
+#define XPS_FPGA11_INT_ID		87U
+#define XPS_FPGA12_INT_ID		88U
+#define XPS_FPGA13_INT_ID		89U
+#define XPS_FPGA14_INT_ID		90U
+#define XPS_FPGA15_INT_ID		91U
+
+/* Updated Interrupt-IDs */
+#define XPS_OCMINTR_INT_ID		(10U + 32U)
+#define XPS_NAND_INT_ID        		(14U + 32U)
+#define XPS_QSPI_INT_ID			(15U + 32U)
+#define XPS_GPIO_INT_ID			(16U + 32U)
+#define XPS_I2C0_INT_ID			(17U + 32U)
+#define XPS_I2C1_INT_ID			(18U + 32U)
+#define XPS_SPI0_INT_ID			(19U + 32U)
+#define XPS_SPI1_INT_ID			(20U + 32U)
+#define XPS_UART0_INT_ID		(21U + 32U)
+#define XPS_UART1_INT_ID		(22U + 32U)
+#define XPS_CAN0_INT_ID			(23U + 32U)
+#define XPS_CAN1_INT_ID			(24U + 32U)
+#define	XPS_RTC_ALARM_INT_ID 	(26U + 32U)
+#define	XPS_RTC_SEC_INT_ID	 	(27U + 32U)
+#define XPS_WDT_INT_ID			(52U + 32U)
+#define XPS_TTC0_0_INT_ID		(36U + 32U)
+#define XPS_TTC0_1_INT_ID		(37U + 32U)
+#define XPS_TTC0_2_INT_ID 		(38U + 32U)
+#define XPS_TTC1_0_INT_ID		(39U + 32U)
+#define XPS_TTC1_1_INT_ID		(40U + 32U)
+#define XPS_TTC1_2_INT_ID		(41U + 32U)
+#define XPS_TTC2_0_INT_ID		(42U + 32U)
+#define XPS_TTC2_1_INT_ID		(43U + 32U)
+#define XPS_TTC2_2_INT_ID		(44U + 32U)
+#define XPS_TTC3_0_INT_ID		(45U + 32U)
+#define XPS_TTC3_1_INT_ID		(46U + 32U)
+#define XPS_TTC3_2_INT_ID		(47U + 32U)
+#define XPS_SDIO0_INT_ID		(48U + 32U)
+#define XPS_SDIO1_INT_ID		(49U + 32U)
+#define XPS_AMS_INT_ID			(56U + 32U)
+#define XPS_GEM0_INT_ID			(57U + 32U)
+#define XPS_GEM0_WAKE_INT_ID		(58U + 32U)
+#define XPS_GEM1_INT_ID			(59U + 32U)
+#define XPS_GEM1_WAKE_INT_ID		(60U + 32U)
+#define XPS_GEM2_INT_ID			(61U + 32U)
+#define XPS_GEM2_WAKE_INT_ID		(62U + 32U)
+#define XPS_GEM3_INT_ID			(63U + 32U)
+#define XPS_GEM3_WAKE_INT_ID		(64U + 32U)
+#define XPS_USB3_0_ENDPT_INT_ID		(65U + 32U)
+#define XPS_USB3_1_ENDPT_INT_ID		(70U + 32U)
+#define XPS_ADMA_CH0_INT_ID		(77U + 32U)
+#define XPS_ADMA_CH1_INT_ID		(78U + 32U)
+#define XPS_ADMA_CH2_INT_ID		(79U + 32U)
+#define XPS_ADMA_CH3_INT_ID		(80U + 32U)
+#define XPS_ADMA_CH4_INT_ID		(81U + 32U)
+#define XPS_ADMA_CH5_INT_ID		(82U + 32U)
+#define XPS_ADMA_CH6_INT_ID		(83U + 32U)
+#define XPS_ADMA_CH7_INT_ID		(84U + 32U)
+#define XPS_CSU_DMA_INT_ID		(86U + 32U)
+#define XPS_XMPU_LPD_INT_ID		(88U + 32U)
+#define XPS_ZDMA_CH0_INT_ID		(124U + 32U)
+#define XPS_ZDMA_CH1_INT_ID		(125U + 32U)
+#define XPS_ZDMA_CH2_INT_ID		(126U + 32U)
+#define XPS_ZDMA_CH3_INT_ID		(127U + 32U)
+#define XPS_ZDMA_CH4_INT_ID		(128U + 32U)
+#define XPS_ZDMA_CH5_INT_ID		(129U + 32U)
+#define XPS_ZDMA_CH6_INT_ID		(130U + 32U)
+#define XPS_ZDMA_CH7_INT_ID		(131U + 32U)
+#define XPS_XMPU_FPD_INT_ID		(134U + 32U)
+#define XPS_FPD_CCI_INT_ID		(154U + 32U)
+#define XPS_FPD_SMMU_INT_ID		(155U + 32U)
+#define XPS_APM0_INT_ID		(123U + 32U)
+#define XPS_APM1_INT_ID		(25U + 32U)
+#define XPS_APM2_INT_ID		(25U + 32U)
+#define XPS_APM5_INT_ID		(123U + 32U)
+
+/* REDEFINES for TEST APP */
+/* Definitions for UART */
+#define XPAR_PS7_UART_0_INTR		XPS_UART0_INT_ID
+#define XPAR_PS7_UART_1_INTR		XPS_UART1_INT_ID
+#define XPAR_PS7_USB_0_INTR		XPS_USB0_INT_ID
+#define XPAR_PS7_USB_1_INTR		XPS_USB1_INT_ID
+#define XPAR_PS7_I2C_0_INTR		XPS_I2C0_INT_ID
+#define XPAR_PS7_I2C_1_INTR		XPS_I2C1_INT_ID
+#define XPAR_PS7_SPI_0_INTR		XPS_SPI0_INT_ID
+#define XPAR_PS7_SPI_1_INTR		XPS_SPI1_INT_ID
+#define XPAR_PS7_CAN_0_INTR		XPS_CAN0_INT_ID
+#define XPAR_PS7_CAN_1_INTR		XPS_CAN1_INT_ID
+#define XPAR_PS7_GPIO_0_INTR		XPS_GPIO_INT_ID
+#define XPAR_PS7_ETHERNET_0_INTR	XPS_GEM0_INT_ID
+#define XPAR_PS7_ETHERNET_0_WAKE_INTR	XPS_GEM0_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_1_INTR	XPS_GEM1_INT_ID
+#define XPAR_PS7_ETHERNET_1_WAKE_INTR	XPS_GEM1_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_2_INTR	XPS_GEM2_INT_ID
+#define XPAR_PS7_ETHERNET_2_WAKE_INTR	XPS_GEM2_WAKE_INT_ID
+#define XPAR_PS7_ETHERNET_3_INTR	XPS_GEM3_INT_ID
+#define XPAR_PS7_ETHERNET_3_WAKE_INTR	XPS_GEM3_WAKE_INT_ID
+
+#define XPAR_PS7_QSPI_0_INTR		XPS_QSPI_INT_ID
+#define XPAR_PS7_WDT_0_INTR		XPS_WDT_INT_ID
+#define XPAR_PS7_SCUWDT_0_INTR		XPS_SCU_WDT_INT_ID
+#define XPAR_PS7_SCUTIMER_0_INTR	XPS_SCU_TMR_INT_ID
+#define XPAR_PS7_XADC_0_INTR		XPS_SYSMON_INT_ID
+
+#define XPAR_PSU_UART_0_INTR        XPS_UART0_INT_ID
+#define XPAR_PSU_UART_1_INTR        XPS_UART1_INT_ID
+#define XPAR_PSU_USB_0_INTR     XPS_USB0_INT_ID
+#define XPAR_PSU_USB_1_INTR     XPS_USB1_INT_ID
+#define XPAR_PSU_I2C_0_INTR     XPS_I2C0_INT_ID
+#define XPAR_PSU_I2C_1_INTR     XPS_I2C1_INT_ID
+#define XPAR_PSU_SPI_0_INTR     XPS_SPI0_INT_ID
+#define XPAR_PSU_SPI_1_INTR     XPS_SPI1_INT_ID
+#define XPAR_PSU_CAN_0_INTR     XPS_CAN0_INT_ID
+#define XPAR_PSU_CAN_1_INTR     XPS_CAN1_INT_ID
+#define XPAR_PSU_GPIO_0_INTR        XPS_GPIO_INT_ID
+#define XPAR_PSU_ETHERNET_0_INTR    XPS_GEM0_INT_ID
+#define XPAR_PSU_ETHERNET_0_WAKE_INTR   XPS_GEM0_WAKE_INT_ID
+#define XPAR_PSU_ETHERNET_1_INTR    XPS_GEM1_INT_ID
+#define XPAR_PSU_ETHERNET_1_WAKE_INTR   XPS_GEM1_WAKE_INT_ID
+#define XPAR_PSU_ETHERNET_2_INTR    XPS_GEM2_INT_ID
+#define XPAR_PSU_ETHERNET_2_WAKE_INTR   XPS_GEM2_WAKE_INT_ID
+#define XPAR_PSU_ETHERNET_3_INTR    XPS_GEM3_INT_ID
+#define XPAR_PSU_ETHERNET_3_WAKE_INTR   XPS_GEM3_WAKE_INT_ID
+#define XPAR_PSU_QSPI_0_INTR        XPS_QSPI_INT_ID
+#define XPAR_PSU_WDT_0_INTR     XPS_WDT_INT_ID
+#define XPAR_PSU_SCUWDT_0_INTR      XPS_SCU_WDT_INT_ID
+#define XPAR_PSU_SCUTIMER_0_INTR    XPS_SCU_TMR_INT_ID
+#define XPAR_PSU_XADC_0_INTR        XPS_SYSMON_INT_ID
+#define XPAR_PSU_TTC_0_INTR         XPS_TTC0_0_INT_ID
+#define XPAR_PSU_TTC_1_INTR         XPS_TTC0_1_INT_ID
+#define XPAR_PSU_TTC_2_INTR         XPS_TTC0_2_INT_ID
+#define XPAR_PSU_TTC_3_INTR         XPS_TTC1_0_INT_ID
+#define XPAR_PSU_TTC_4_INTR         XPS_TTC1_1_INT_ID
+#define XPAR_PSU_TTC_5_INTR         XPS_TTC1_2_INT_ID
+#define XPAR_PSU_TTC_6_INTR			XPS_TTC2_0_INT_ID
+#define XPAR_PSU_TTC_7_INTR			XPS_TTC2_1_INT_ID
+#define XPAR_PSU_TTC_8_INTR			XPS_TTC2_2_INT_ID
+#define XPAR_PSU_TTC_9_INTR			XPS_TTC3_0_INT_ID
+#define XPAR_PSU_TTC_10_INTR		XPS_TTC3_1_INT_ID
+#define XPAR_PSU_TTC_11_INTR		XPS_TTC3_2_INT_ID
+
+#define XPAR_XADCPS_NUM_INSTANCES 1U
+#define XPAR_XADCPS_0_DEVICE_ID   0U
+#define XPAR_XADCPS_0_BASEADDR	  (0xF8007000U)
+#define XPAR_XADCPS_INT_ID		XPS_SYSMON_INT_ID
+
+/* For backwards compatibilty */
+#define XPAR_XUARTPS_0_CLOCK_HZ		XPAR_XUARTPS_0_UART_CLK_FREQ_HZ
+#define XPAR_XUARTPS_1_CLOCK_HZ		XPAR_XUARTPS_1_UART_CLK_FREQ_HZ
+#define XPAR_XTTCPS_0_CLOCK_HZ		XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_1_CLOCK_HZ		XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_2_CLOCK_HZ		XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_3_CLOCK_HZ		XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_4_CLOCK_HZ		XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ
+#define XPAR_XTTCPS_5_CLOCK_HZ		XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ
+#define XPAR_XIICPS_0_CLOCK_HZ		XPAR_XIICPS_0_I2C_CLK_FREQ_HZ
+#define XPAR_XIICPS_1_CLOCK_HZ		XPAR_XIICPS_1_I2C_CLK_FREQ_HZ
+
+#define XPAR_XQSPIPS_0_CLOCK_HZ		XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ
+
+#ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ
+#endif
+
+#ifdef XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
+#define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ	XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ
+#endif
+
+#define XPAR_SCUWDT_DEVICE_ID		0U
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c
new file mode 100644
index 000000000..fea992e40
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.c
@@ -0,0 +1,133 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.c
+*
+* This file contains information about hardware for which the code is built
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date   Changes
+* ----- ---- -------- -------------------------------------------------------
+* 5.00  pkp  12/15/14 Initial release
+* 5.04  pkp  01/12/16 Added platform information support for Cortex-A53 32bit
+*					  mode
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+*
+* This API is used to provide information about platform
+*
+* @param    None.
+*
+* @return   The information about platform defined in xplatform_info.h
+*
+* @note     None.
+*
+******************************************************************************/
+u32 XGetPlatform_Info()
+{
+	u32 reg;
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+	return XPLAT_ZYNQ_ULTRA_MP;
+#elif (__microblaze__)
+	return XPLAT_MICROBLAZE;
+#else
+	return XPLAT_ZYNQ;
+#endif
+}
+
+/*****************************************************************************/
+/**
+*
+* This API is used to provide information about zynq ultrascale MP platform
+*
+* @param    None.
+*
+* @return   The information about zynq ultrascale MP platform defined in
+*			xplatform_info.h
+*
+* @note     None.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info()
+{
+	u32 reg;
+	reg = ((Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET) >> 12U )& XPLAT_INFO_MASK);
+	return reg;
+}
+#endif
+
+/*****************************************************************************/
+/**
+*
+* This API is used to provide information about PS Silicon version
+*
+* @param    None.
+*
+* @return   The information about PS Silicon version.
+*
+* @note     None.
+*
+******************************************************************************/
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGetPSVersion_Info()
+{
+	u32 reg;
+	reg = (Xil_In32(XPAR_CSU_BASEADDR + XPAR_CSU_VER_OFFSET)
+			& XPS_VERSION_INFO_MASK);
+	return reg;
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.h
new file mode 100644
index 000000000..7028a83af
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xplatform_info.h
@@ -0,0 +1,91 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xplatform_info.h
+*
+* This file contains definitions for various platforms available
+*
+******************************************************************************/
+
+#ifndef XPLATFORM_INFO_H		/* prevent circular inclusions */
+#define XPLATFORM_INFO_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+#define XPAR_CSU_BASEADDR 0xFFCA0000U
+#define	XPAR_CSU_VER_OFFSET 0x00000044U
+
+#define XPLAT_ZYNQ_ULTRA_MP_SILICON 0x0
+#define XPLAT_ZYNQ_ULTRA_MP 0x1
+#define XPLAT_ZYNQ_ULTRA_MPVEL 0x2
+#define XPLAT_ZYNQ_ULTRA_MPQEMU 0x3
+#define XPLAT_ZYNQ 0x4
+#define XPLAT_MICROBLAZE 0x5
+
+#define XPS_VERSION_1 0x0
+#define XPS_VERSION_2 0x1
+
+#define XPLAT_INFO_MASK (0xF)
+#define XPS_VERSION_INFO_MASK (0xF)
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+u32 XGetPlatform_Info();
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGetPSVersion_Info();
+#endif
+
+#if defined (ARMR5) || (__aarch64__) || (ARMA53_32)
+u32 XGet_Zynq_UltraMp_Platform_info();
+#endif
+/************************** Function Prototypes ******************************/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.c
new file mode 100644
index 000000000..0851408cc
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.c
@@ -0,0 +1,292 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.c
+*
+* This file contains APIs for configuring and controlling the Cortex-R5
+* Performance Monitor Events. For more information about the event counters,
+* see xpm_counter.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xpm_counter.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+typedef const u32 PmcrEventCfg32[XPM_CTRCOUNT];
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions *****************************/
+
+
+
+/************************** Function Prototypes ******************************/
+
+void Xpm_DisableEventCounters(void);
+void Xpm_EnableEventCounters (void);
+void Xpm_ResetEventCounters (void);
+
+/******************************************************************************/
+
+/****************************************************************************/
+/**
+*
+* This function disables the Cortex R5 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_DisableEventCounters(void)
+{
+	/* Disable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_CLR, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the Cortex R5 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_EnableEventCounters(void)
+{
+	/* Enable the event counters */
+	mtcp(XREG_CP15_COUNT_ENABLE_SET, 0x3f);
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets the Cortex R5 event counters.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_ResetEventCounters(void)
+{
+	u32 Reg;
+
+#ifdef __GNUC__
+	Reg = mfcp(XREG_CP15_PERF_MONITOR_CTRL);
+#else
+	{ register u32 C15Reg __asm(XREG_CP15_PERF_MONITOR_CTRL);
+	  Reg = C15Reg; }
+#endif
+	Reg |= (1U << 2U); /* reset event counters */
+	mtcp(XREG_CP15_PERF_MONITOR_CTRL, Reg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function configures the Cortex R5 event counters controller, with the
+* event codes, in a configuration selected by the user and enables the counters.
+*
+* @param	PmcrCfg is configuration value based on which the event counters
+*		are configured.
+*		Use XPM_CNTRCFG* values defined in xpm_counter.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_SetEvents(s32 PmcrCfg)
+{
+	u32 Counter;
+	static PmcrEventCfg32 PmcrEvents[] = {
+		{
+			XPM_EVENT_SOFTINCR,
+			XPM_EVENT_INSRFETCH_CACHEREFILL,
+			XPM_EVENT_INSTRFECT_TLBREFILL,
+			XPM_EVENT_DATA_CACHEREFILL,
+			XPM_EVENT_DATA_CACHEACCESS,
+			XPM_EVENT_DATA_TLBREFILL
+		},
+		{
+			XPM_EVENT_DATA_READS,
+			XPM_EVENT_DATA_WRITE,
+			XPM_EVENT_EXCEPTION,
+			XPM_EVENT_EXCEPRETURN,
+			XPM_EVENT_CHANGECONTEXT,
+			XPM_EVENT_SW_CHANGEPC
+		},
+		{
+			XPM_EVENT_IMMEDBRANCH,
+			XPM_EVENT_UNALIGNEDACCESS,
+			XPM_EVENT_BRANCHMISS,
+			XPM_EVENT_CLOCKCYCLES,
+			XPM_EVENT_BRANCHPREDICT,
+			XPM_EVENT_JAVABYTECODE
+		},
+		{
+			XPM_EVENT_SWJAVABYTECODE,
+			XPM_EVENT_JAVABACKBRANCH,
+			XPM_EVENT_COHERLINEMISS,
+			XPM_EVENT_COHERLINEHIT,
+			XPM_EVENT_INSTRSTALL,
+			XPM_EVENT_DATASTALL
+		},
+		{
+			XPM_EVENT_MAINTLBSTALL,
+			XPM_EVENT_STREXPASS,
+			XPM_EVENT_STREXFAIL,
+			XPM_EVENT_DATAEVICT,
+			XPM_EVENT_NODISPATCH,
+			XPM_EVENT_ISSUEEMPTY
+		},
+		{
+			XPM_EVENT_INSTRRENAME,
+			XPM_EVENT_PREDICTFUNCRET,
+			XPM_EVENT_MAINEXEC,
+			XPM_EVENT_SECEXEC,
+			XPM_EVENT_LDRSTR,
+			XPM_EVENT_FLOATRENAME
+		},
+		{
+			XPM_EVENT_NEONRENAME,
+			XPM_EVENT_PLDSTALL,
+			XPM_EVENT_WRITESTALL,
+			XPM_EVENT_INSTRTLBSTALL,
+			XPM_EVENT_DATATLBSTALL,
+			XPM_EVENT_INSTR_uTLBSTALL
+		},
+		{
+			XPM_EVENT_DATA_uTLBSTALL,
+			XPM_EVENT_DMB_STALL,
+			XPM_EVENT_INT_CLKEN,
+			XPM_EVENT_DE_CLKEN,
+			XPM_EVENT_INSTRISB,
+			XPM_EVENT_INSTRDSB
+		},
+		{
+			XPM_EVENT_INSTRDMB,
+			XPM_EVENT_EXTINT,
+			XPM_EVENT_PLE_LRC,
+			XPM_EVENT_PLE_LRS,
+			XPM_EVENT_PLE_FLUSH,
+			XPM_EVENT_PLE_CMPL
+		},
+		{
+			XPM_EVENT_PLE_OVFL,
+			XPM_EVENT_PLE_PROG,
+			XPM_EVENT_PLE_LRC,
+			XPM_EVENT_PLE_LRS,
+			XPM_EVENT_PLE_FLUSH,
+			XPM_EVENT_PLE_CMPL
+		},
+		{
+			XPM_EVENT_DATASTALL,
+			XPM_EVENT_INSRFETCH_CACHEREFILL,
+			XPM_EVENT_INSTRFECT_TLBREFILL,
+			XPM_EVENT_DATA_CACHEREFILL,
+			XPM_EVENT_DATA_CACHEACCESS,
+			XPM_EVENT_DATA_TLBREFILL
+		},
+	};
+	const u32 *ptr = PmcrEvents[PmcrCfg];
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+		/* Selecet event counter */
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+
+		/* Set the event */
+		mtcp(XREG_CP15_EVENT_TYPE_SEL, ptr[Counter]);
+	}
+
+	Xpm_ResetEventCounters();
+	Xpm_EnableEventCounters();
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the event counters and returns the counter values.
+*
+* @param	PmCtrValue is a pointer to an array of type u32 PmCtrValue[6].
+*		It is an output parameter which is used to return the PM
+*		counter values.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void Xpm_GetEventCounters(u32 *PmCtrValue)
+{
+	u32 Counter;
+
+	Xpm_DisableEventCounters();
+
+	for(Counter = 0U; Counter < XPM_CTRCOUNT; Counter++) {
+
+		mtcp(XREG_CP15_EVENT_CNTR_SEL, Counter);
+#ifdef __GNUC__
+		PmCtrValue[Counter] = mfcp(XREG_CP15_PERF_MONITOR_COUNT);
+#else
+		{ register u32 Cp15Reg __asm(XREG_CP15_PERF_MONITOR_COUNT);
+		  PmCtrValue[Counter] = Cp15Reg; }
+#endif
+	}
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.h
new file mode 100644
index 000000000..5679d4bb5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpm_counter.h
@@ -0,0 +1,571 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpm_counter.h
+*
+* This header file contains APIs for configuring and controlling the Cortex-R5
+* Performance Monitor Events.
+* Cortex-R5 Performance Monitor has 6 event counters which can be used to
+* count a variety of events described in Coretx-R5 TRM. This file defines
+* configurations, where value configures the event counters to count a
+* set of events.
+*
+* Xpm_SetEvents can be used to set the event counters to count a set of events
+* and Xpm_GetEventCounters can be used to read the counter values.
+*
+* @note
+*
+* This file doesn't handle the Cortex-R5 cycle counter, as the cycle counter is
+* being used for time keeping.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 

+*
+******************************************************************************/
+
+#ifndef XPMCOUNTER_H /* prevent circular inclusions */
+#define XPMCOUNTER_H /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include 
+#include "xpseudo_asm.h"
+#include "xil_types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/* Number of performance counters */
+#define XPM_CTRCOUNT 6U
+
+/* The following constants define the Cortex-R5 Performance Monitor Events */
+
+/*
+ * Software increment. The register is incremented only on writes to the
+ * Software Increment Register
+ */
+#define XPM_EVENT_SOFTINCR 0x00U
+
+/*
+ * Instruction fetch that causes a refill at (at least) the lowest level(s) of
+ * instruction or unified cache. Includes the speculative linefills in the
+ * count
+ */
+#define XPM_EVENT_INSRFETCH_CACHEREFILL 0x01U
+
+/*
+ * Instruction fetch that causes a TLB refill at (at least) the lowest level of
+ * TLB. Includes the speculative requests in the count
+ */
+#define XPM_EVENT_INSTRFECT_TLBREFILL 0x02U
+
+/*
+ * Data read or write operation that causes a refill at (at least) the lowest
+ * level(s)of data or unified cache. Counts the number of allocations performed
+ * in the Data Cache due to a read or a write
+ */
+#define XPM_EVENT_DATA_CACHEREFILL 0x03U
+
+/*
+ * Data read or write operation that causes a cache access at (at least) the
+ * lowest level(s) of data or unified cache. This includes speculative reads
+ */
+#define XPM_EVENT_DATA_CACHEACCESS 0x04U
+
+/*
+ * Data read or write operation that causes a TLB refill at (at least) the
+ * lowest level of TLB. This does not include micro TLB misses due to PLD, PLI,
+ * CP15 Cache operation by MVA and CP15 VA to PA operations
+ */
+#define XPM_EVENT_DATA_TLBREFILL 0x05U
+
+/*
+ * Data read architecturally executed. Counts the number of data read
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted LDR/LDM, as well as the reads due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_READS 0x06U
+
+/*
+ * Data write architecturally executed. Counts the number of data write
+ * instructions accepted by the Load Store Unit. This includes counting the
+ * speculative and aborted STR/STM, as well as the writes due to the SWP
+ * instructions
+ */
+#define XPM_EVENT_DATA_WRITE 0x07U
+
+/* Exception taken. Counts the number of exceptions architecturally taken.*/
+#define XPM_EVENT_EXCEPTION 0x09U
+
+/* Exception return architecturally executed.*/
+#define XPM_EVENT_EXCEPRETURN 0x0AU
+
+/*
+ * Change to ContextID retired. Counts the number of instructions
+ * architecturally executed writing into the ContextID Register
+ */
+#define XPM_EVENT_CHANGECONTEXT 0x0BU
+
+/*
+ * Software change of PC, except by an exception, architecturally executed.
+ * Count the number of PC changes architecturally executed, excluding the PC
+ * changes due to taken exceptions
+ */
+#define XPM_EVENT_SW_CHANGEPC 0x0CU
+
+/*
+ * Immediate branch architecturally executed (taken or not taken). This includes
+ * the branches which are flushed due to a previous load/store which aborts
+ * late
+ */
+#define XPM_EVENT_IMMEDBRANCH 0x0DU
+
+/*
+ * Unaligned access architecturally executed. Counts the number of aborted
+ * unaligned accessed architecturally executed, and the number of not-aborted
+ * unaligned accesses, including the speculative ones
+ */
+#define XPM_EVENT_UNALIGNEDACCESS 0x0FU
+
+/*
+ * Branch mispredicted/not predicted. Counts the number of mispredicted or
+ * not-predicted branches executed. This includes the branches which are flushed
+ * due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHMISS 0x10U
+
+/*
+ * Counts clock cycles when the Cortex-R5 processor is not in WFE/WFI. This
+ * event is not exported on the PMUEVENT bus
+ */
+#define XPM_EVENT_CLOCKCYCLES 0x11U
+
+/*
+ * Branches or other change in program flow that could have been predicted by
+ * the branch prediction resources of the processor. This includes the branches
+ * which are flushed due to a previous load/store which aborts late
+ */
+#define XPM_EVENT_BRANCHPREDICT 0x12U
+
+/*
+ * Java bytecode execute. Counts the number of Java bytecodes being decoded,
+ * including speculative ones
+ */
+#define XPM_EVENT_JAVABYTECODE 0x40U
+
+/*
+ * Software Java bytecode executed. Counts the number of software java bytecodes
+ * being decoded, including speculative ones
+ */
+#define XPM_EVENT_SWJAVABYTECODE 0x41U
+
+/*
+ * Jazelle backward branches executed. Counts the number of Jazelle taken
+ * branches being executed. This includes the branches which are flushed due
+ * to a previous load/store which aborts late
+ */
+#define XPM_EVENT_JAVABACKBRANCH 0x42U
+
+/*
+ * Coherent linefill miss Counts the number of coherent linefill requests
+ * performed by the Cortex-R5 processor which also miss in all the other
+ * Cortex-R5 processors, meaning that the request is sent to the external
+ * memory
+ */
+#define XPM_EVENT_COHERLINEMISS 0x50U
+
+/*
+ * Coherent linefill hit. Counts the number of coherent linefill requests
+ * performed by the Cortex-R5 processor which hit in another Cortex-R5
+ * processor, meaning that the linefill data is fetched directly from the
+ * relevant Cortex-R5 cache
+ */
+#define XPM_EVENT_COHERLINEHIT 0x51U
+
+/*
+ * Instruction cache dependent stall cycles. Counts the number of cycles where
+ * the processor is ready to accept new instructions, but does not receive any
+ * due to the instruction side not being able to provide any and the
+ * instruction cache is currently performing at least one linefill
+ */
+#define XPM_EVENT_INSTRSTALL 0x60U
+
+/*
+ * Data cache dependent stall cycles. Counts the number of cycles where the core
+ * has some instructions that it cannot issue to any pipeline, and the Load
+ * Store unit has at least one pending linefill request, and no pending
+ */
+#define XPM_EVENT_DATASTALL 0x61U
+
+/*
+ * Main TLB miss stall cycles. Counts the number of cycles where the processor
+ * is stalled waiting for the completion of translation table walks from the
+ * main TLB. The processor stalls can be due to the instruction side not being
+ * able to provide the instructions, or to the data side not being able to
+ * provide the necessary data, due to them waiting for the main TLB translation
+ * table walk to complete
+ */
+#define XPM_EVENT_MAINTLBSTALL 0x62U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * passed
+ */
+#define XPM_EVENT_STREXPASS 0x63U
+
+/*
+ * Counts the number of STREX instructions architecturally executed and
+ * failed
+ */
+#define XPM_EVENT_STREXFAIL 0x64U
+
+/*
+ * Data eviction. Counts the number of eviction requests due to a linefill in
+ * the data cache
+ */
+#define XPM_EVENT_DATAEVICT 0x65U
+
+/*
+ * Counts the number of cycles where the issue stage does not dispatch any
+ * instruction because it is empty or cannot dispatch any instructions
+ */
+#define XPM_EVENT_NODISPATCH 0x66U
+
+/*
+ * Counts the number of cycles where the issue stage is empty
+ */
+#define XPM_EVENT_ISSUEEMPTY 0x67U
+
+/*
+ * Counts the number of instructions going through the Register Renaming stage.
+ * This number is an approximate number of the total number of instructions
+ * speculatively executed, and even more approximate of the total number of
+ * instructions architecturally executed. The approximation depends mainly on
+ * the branch misprediction rate.
+ * The renaming stage can handle two instructions in the same cycle so the event
+ * is two bits long:
+ *    - b00 no instructions renamed
+ *    - b01 one instruction renamed
+ *    - b10 two instructions renamed
+ */
+#define XPM_EVENT_INSTRRENAME 0x68U
+
+/*
+ * Counts the number of procedure returns whose condition codes do not fail,
+ * excluding all returns from exception. This count includes procedure returns
+ * which are flushed due to a previous load/store which aborts late.
+ * Only the following instructions are reported:
+ * - BX R14
+ * - MOV PC LR
+ * - POP {..,pc}
+ * - LDR pc,[sp],#offset
+ * The following instructions are not reported:
+ * - LDMIA R9!,{..,PC} (ThumbEE state only)
+ * - LDR PC,[R9],#offset (ThumbEE state only)
+ * - BX R0 (Rm != R14)
+ * - MOV PC,R0 (Rm != R14)
+ * - LDM SP,{...,PC} (writeback not specified)
+ * - LDR PC,[SP,#offset] (wrong addressing mode)
+ */
+#define XPM_EVENT_PREDICTFUNCRET 0x6EU
+
+/*
+ * Counts the number of instructions being executed in the main execution
+ * pipeline of the processor, the multiply pipeline and arithmetic logic unit
+ * pipeline. The counted instructions are still speculative
+ */
+#define XPM_EVENT_MAINEXEC 0x70U
+
+/*
+ * Counts the number of instructions being executed in the processor second
+ * execution pipeline (ALU). The counted instructions are still speculative
+ */
+#define XPM_EVENT_SECEXEC 0x71U
+
+/*
+ * Counts the number of instructions being executed in the Load/Store unit. The
+ * counted instructions are still speculative
+ */
+#define XPM_EVENT_LDRSTR 0x72U
+
+/*
+ * Counts the number of Floating-point instructions going through the Register
+ * Rename stage. Instructions are still speculative in this stage.
+ *Two floating-point instructions can be renamed in the same cycle so the event
+ * is two bitslong:
+ *0b00 no floating-point instruction renamed
+ *0b01 one floating-point instruction renamed
+ *0b10 two floating-point instructions renamed
+ */
+#define XPM_EVENT_FLOATRENAME 0x73U
+
+/*
+ * Counts the number of Neon instructions going through the Register Rename
+ * stage.Instructions are still speculative in this stage.
+ * Two NEON instructions can be renamed in the same cycle so the event is two
+ * bits long:
+ *0b00 no NEON instruction renamed
+ *0b01 one NEON instruction renamed
+ *0b10 two NEON instructions renamed
+ */
+#define XPM_EVENT_NEONRENAME 0x74U
+
+/*
+ * Counts the number of cycles where the processor is stalled because PLD slots
+ * are all full
+ */
+#define XPM_EVENT_PLDSTALL 0x80U
+
+/*
+ * Counts the number of cycles when the processor is stalled and the data side
+ * is stalled too because it is full and executing writes to the external
+ * memory
+ */
+#define XPM_EVENT_WRITESTALL 0x81U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the instruction side
+ */
+#define XPM_EVENT_INSTRTLBSTALL 0x82U
+
+/*
+ * Counts the number of stall cycles due to main TLB misses on requests issued
+ * by the data side
+ */
+#define XPM_EVENT_DATATLBSTALL 0x83U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the instruction
+ * side. This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_INSTR_uTLBSTALL 0x84U
+
+/*
+ * Counts the number of stall cycles due to micro TLB misses on the data side.
+ * This event does not include main TLB miss stall cycles that are already
+ * counted in the corresponding main TLB event
+ */
+#define XPM_EVENT_DATA_uTLBSTALL 0x85U
+
+/*
+ * Counts the number of stall cycles because of the execution of a DMB memory
+ * barrier. This includes all DMB instructions being executed, even
+ * speculatively
+ */
+#define XPM_EVENT_DMB_STALL 0x86U
+
+/*
+ * Counts the number of cycles during which the integer core clock is enabled
+ */
+#define XPM_EVENT_INT_CLKEN 0x8AU
+
+/*
+ * Counts the number of cycles during which the Data Engine clock is enabled
+ */
+#define XPM_EVENT_DE_CLKEN 0x8BU
+
+/*
+ * Counts the number of ISB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRISB 0x90U
+
+/*
+ * Counts the number of DSB instructions architecturally executed
+ */
+#define XPM_EVENT_INSTRDSB 0x91U
+
+/*
+ * Counts the number of DMB instructions speculatively executed
+ */
+#define XPM_EVENT_INSTRDMB 0x92U
+
+/*
+ * Counts the number of external interrupts executed by the processor
+ */
+#define XPM_EVENT_EXTINT 0x93U
+
+/*
+ * PLE cache line request completed
+ */
+#define XPM_EVENT_PLE_LRC 0xA0U
+
+/*
+ * PLE cache line request skipped
+ */
+#define XPM_EVENT_PLE_LRS 0xA1U
+
+/*
+ * PLE FIFO flush
+ */
+#define XPM_EVENT_PLE_FLUSH 0xA2U
+
+/*
+ * PLE request complete
+ */
+#define XPM_EVENT_PLE_CMPL 0xA3U
+
+/*
+ * PLE FIFO overflow
+ */
+#define XPM_EVENT_PLE_OVFL 0xA4U
+
+/*
+ * PLE request programmed
+ */
+#define XPM_EVENT_PLE_PROG 0xA5U
+
+/*
+ * The following constants define the configurations for Cortex-R5 Performance
+ * Monitor Events. Each configuration configures the event counters for a set
+ * of events.
+ * -----------------------------------------------
+ * Config		PmCtr0... PmCtr5
+ * -----------------------------------------------
+ * XPM_CNTRCFG1		{ XPM_EVENT_SOFTINCR,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ *
+ * XPM_CNTRCFG2		{ XPM_EVENT_DATA_READS,
+ *			  XPM_EVENT_DATA_WRITE,
+ *			  XPM_EVENT_EXCEPTION,
+ *			  XPM_EVENT_EXCEPRETURN,
+ *			  XPM_EVENT_CHANGECONTEXT,
+ *			  XPM_EVENT_SW_CHANGEPC }
+ *
+ * XPM_CNTRCFG3		{ XPM_EVENT_IMMEDBRANCH,
+ *			  XPM_EVENT_UNALIGNEDACCESS,
+ *			  XPM_EVENT_BRANCHMISS,
+ *			  XPM_EVENT_CLOCKCYCLES,
+ *			  XPM_EVENT_BRANCHPREDICT,
+ *			  XPM_EVENT_JAVABYTECODE }
+ *
+ * XPM_CNTRCFG4		{ XPM_EVENT_SWJAVABYTECODE,
+ *			  XPM_EVENT_JAVABACKBRANCH,
+ *			  XPM_EVENT_COHERLINEMISS,
+ *			  XPM_EVENT_COHERLINEHIT,
+ *			  XPM_EVENT_INSTRSTALL,
+ *			  XPM_EVENT_DATASTALL }
+ *
+ * XPM_CNTRCFG5		{ XPM_EVENT_MAINTLBSTALL,
+ *			  XPM_EVENT_STREXPASS,
+ *			  XPM_EVENT_STREXFAIL,
+ *			  XPM_EVENT_DATAEVICT,
+ *			  XPM_EVENT_NODISPATCH,
+ *			  XPM_EVENT_ISSUEEMPTY }
+ *
+ * XPM_CNTRCFG6		{ XPM_EVENT_INSTRRENAME,
+ *			  XPM_EVENT_PREDICTFUNCRET,
+ *			  XPM_EVENT_MAINEXEC,
+ *			  XPM_EVENT_SECEXEC,
+ *			  XPM_EVENT_LDRSTR,
+ *			  XPM_EVENT_FLOATRENAME }
+ *
+ * XPM_CNTRCFG7		{ XPM_EVENT_NEONRENAME,
+ *			  XPM_EVENT_PLDSTALL,
+ *			  XPM_EVENT_WRITESTALL,
+ *			  XPM_EVENT_INSTRTLBSTALL,
+ *			  XPM_EVENT_DATATLBSTALL,
+ *			  XPM_EVENT_INSTR_uTLBSTALL }
+ *
+ * XPM_CNTRCFG8		{ XPM_EVENT_DATA_uTLBSTALL,
+ *			  XPM_EVENT_DMB_STALL,
+ *			  XPM_EVENT_INT_CLKEN,
+ *			  XPM_EVENT_DE_CLKEN,
+ *			  XPM_EVENT_INSTRISB,
+ *			  XPM_EVENT_INSTRDSB }
+ *
+ * XPM_CNTRCFG9		{ XPM_EVENT_INSTRDMB,
+ *			  XPM_EVENT_EXTINT,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG10	{ XPM_EVENT_PLE_OVFL,
+ *			  XPM_EVENT_PLE_PROG,
+ *			  XPM_EVENT_PLE_LRC,
+ *			  XPM_EVENT_PLE_LRS,
+ *			  XPM_EVENT_PLE_FLUSH,
+ *			  XPM_EVENT_PLE_CMPL }
+ *
+ * XPM_CNTRCFG11	{ XPM_EVENT_DATASTALL,
+ *			  XPM_EVENT_INSRFETCH_CACHEREFILL,
+ *			  XPM_EVENT_INSTRFECT_TLBREFILL,
+ *			  XPM_EVENT_DATA_CACHEREFILL,
+ *			  XPM_EVENT_DATA_CACHEACCESS,
+ *			  XPM_EVENT_DATA_TLBREFILL }
+ */
+#define XPM_CNTRCFG1	0
+#define XPM_CNTRCFG2	1
+#define XPM_CNTRCFG3	2
+#define XPM_CNTRCFG4	3
+#define XPM_CNTRCFG5	4
+#define XPM_CNTRCFG6	5
+#define XPM_CNTRCFG7	6
+#define XPM_CNTRCFG8	7
+#define XPM_CNTRCFG9	8
+#define XPM_CNTRCFG10	9
+#define XPM_CNTRCFG11	10
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/* Interface fuctions to access perfromance counters from abstraction layer */
+void Xpm_SetEvents(s32 PmcrCfg);
+void Xpm_GetEventCounters(u32 *PmCtrValue);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm.h
new file mode 100644
index 000000000..aff19d5a9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm.h
@@ -0,0 +1,54 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm.h
+*
+* This header file contains macros for using inline assembler code.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who  Date     Changes
+* ----- ---- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 

+*
+******************************************************************************/
+#ifndef XPSEUDO_ASM_H /* prevent circular inclusions */
+#define XPSEUDO_ASM_H /* by using protection macros */
+
+#include "xreg_cortexr5.h"
+#include "xpseudo_asm_gcc.h"
+
+#endif /* XPSEUDO_ASM_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h
new file mode 100644
index 000000000..2b382acb8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xpseudo_asm_gcc.h
@@ -0,0 +1,175 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xpseudo_asm_gcc.h
+*
+* This header file contains macros for using inline assembler code. It is
+* written specifically for the GNU compiler.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00 	pkp  	 05/29/14 First release
+* 

+*
+******************************************************************************/
+
+#ifndef XPSEUDO_ASM_GCC_H  /* prevent circular inclusions */
+#define XPSEUDO_ASM_GCC_H  /* by using protection macros */
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/* necessary for pre-processor */
+#define stringify(s)	tostring(s)
+#define tostring(s)	#s
+
+/* pseudo assembler instructions */
+#define mfcpsr()	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mrs	%0, cpsr\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+#define mtcpsr(v)	__asm__ __volatile__(\
+			  "msr	cpsr,%0\n"\
+			  : : "r" (v)\
+			)
+
+#define cpsiei()	__asm__ __volatile__("cpsie	i\n")
+#define cpsidi()	__asm__ __volatile__("cpsid	i\n")
+
+#define cpsief()	__asm__ __volatile__("cpsie	f\n")
+#define cpsidf()	__asm__ __volatile__("cpsid	f\n")
+
+
+
+#define mtgpr(rn, v)	__asm__ __volatile__(\
+			  "mov r" stringify(rn) ", %0 \n"\
+			  : : "r" (v)\
+			)
+
+#define mfgpr(rn)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "mov %0,r" stringify(rn) "\n"\
+			    : "=r" (rval)\
+			  );\
+			  rval;\
+			 })
+
+/* memory synchronization operations */
+
+/* Instruction Synchronization Barrier */
+#define isb() __asm__ __volatile__ ("isb" : : : "memory")
+
+/* Data Synchronization Barrier */
+#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")
+
+/* Data Memory Barrier */
+#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")
+
+
+/* Memory Operations */
+#define ldr(adr)	({u32 rval; \
+			  __asm__ __volatile__(\
+			    "ldr	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define ldrb(adr)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "ldrb	%0,[%1]"\
+			    : "=r" (rval) : "r" (adr)\
+			  );\
+			  rval;\
+			 })
+
+#define str(adr, val)	__asm__ __volatile__(\
+			  "str	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+#define strb(adr, val)	__asm__ __volatile__(\
+			  "strb	%0,[%1]\n"\
+			  : : "r" (val), "r" (adr)\
+			)
+
+/* Count leading zeroes (clz) */
+#define clz(arg)	({u8 rval; \
+			  __asm__ __volatile__(\
+			    "clz	%0,%1"\
+			    : "=r" (rval) : "r" (arg)\
+			  );\
+			  rval;\
+			 })
+
+/* CP15 operations */
+#define mtcp(rn, v)	__asm__ __volatile__(\
+			 "mcr " rn "\n"\
+			 : : "r" (v)\
+			);
+
+#define mfcp(rn)	({u32 rval; \
+			 __asm__ __volatile__(\
+			   "mrc " rn "\n"\
+			   : "=r" (rval)\
+			 );\
+			 rval;\
+			 })
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XPSEUDO_ASM_GCC_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xreg_cortexr5.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xreg_cortexr5.h
new file mode 100644
index 000000000..9d28c0acb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xreg_cortexr5.h
@@ -0,0 +1,445 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xreg_cortexr5.h
+*
+* This header file contains definitions for using inline assembler code. It is
+* written specifically for the GNU, IAR, ARMCC compiler.
+*
+* All of the ARM Cortex R5 GPRs, SPRs, and Debug Registers are defined along
+* with the positions of the bits within the registers.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who      Date     Changes
+* ----- -------- -------- -----------------------------------------------
+* 5.00  pkp  02/10/14 Initial version
+* 

+*
+******************************************************************************/
+#ifndef XREG_CORTEXR5_H	/* prevent circular inclusions */
+#define XREG_CORTEXR5_H	/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* GPRs */
+#define XREG_GPR0				r0
+#define XREG_GPR1				r1
+#define XREG_GPR2				r2
+#define XREG_GPR3				r3
+#define XREG_GPR4				r4
+#define XREG_GPR5				r5
+#define XREG_GPR6				r6
+#define XREG_GPR7				r7
+#define XREG_GPR8				r8
+#define XREG_GPR9				r9
+#define XREG_GPR10				r10
+#define XREG_GPR11				r11
+#define XREG_GPR12				r12
+#define XREG_GPR13				r13
+#define XREG_GPR14				r14
+#define XREG_GPR15				r15
+#define XREG_CPSR				cpsr
+
+/* Coprocessor number defines */
+#define XREG_CP0				0
+#define XREG_CP1				1
+#define XREG_CP2				2
+#define XREG_CP3				3
+#define XREG_CP4				4
+#define XREG_CP5				5
+#define XREG_CP6				6
+#define XREG_CP7				7
+#define XREG_CP8				8
+#define XREG_CP9				9
+#define XREG_CP10				10
+#define XREG_CP11				11
+#define XREG_CP12				12
+#define XREG_CP13				13
+#define XREG_CP14				14
+#define XREG_CP15				15
+
+/* Coprocessor control register defines */
+#define XREG_CR0				cr0
+#define XREG_CR1				cr1
+#define XREG_CR2				cr2
+#define XREG_CR3				cr3
+#define XREG_CR4				cr4
+#define XREG_CR5				cr5
+#define XREG_CR6				cr6
+#define XREG_CR7				cr7
+#define XREG_CR8				cr8
+#define XREG_CR9				cr9
+#define XREG_CR10				cr10
+#define XREG_CR11				cr11
+#define XREG_CR12				cr12
+#define XREG_CR13				cr13
+#define XREG_CR14				cr14
+#define XREG_CR15				cr15
+
+/* Current Processor Status Register (CPSR) Bits */
+#define XREG_CPSR_THUMB_MODE			0x20U
+#define XREG_CPSR_MODE_BITS			0x1FU
+#define XREG_CPSR_SYSTEM_MODE			0x1FU
+#define XREG_CPSR_UNDEFINED_MODE		0x1BU
+#define XREG_CPSR_DATA_ABORT_MODE		0x17U
+#define XREG_CPSR_SVC_MODE			0x13U
+#define XREG_CPSR_IRQ_MODE			0x12U
+#define XREG_CPSR_FIQ_MODE			0x11U
+#define XREG_CPSR_USER_MODE			0x10U
+
+#define XREG_CPSR_IRQ_ENABLE			0x80U
+#define XREG_CPSR_FIQ_ENABLE			0x40U
+
+#define XREG_CPSR_N_BIT				0x80000000U
+#define XREG_CPSR_Z_BIT				0x40000000U
+#define XREG_CPSR_C_BIT				0x20000000U
+#define XREG_CPSR_V_BIT				0x10000000U
+
+/*MPU region definitions*/
+#define REGION_32B     0x00000004U
+#define REGION_64B     0x00000005U
+#define REGION_128B    0x00000006U
+#define REGION_256B    0x00000007U
+#define REGION_512B    0x00000008U
+#define REGION_1K      0x00000009U
+#define REGION_2K      0x0000000AU
+#define REGION_4K      0x0000000BU
+#define REGION_8K      0x0000000CU
+#define REGION_16K     0x0000000DU
+#define REGION_32K     0x0000000EU
+#define REGION_64K     0x0000000FU
+#define REGION_128K    0x00000010U
+#define REGION_256K    0x00000011U
+#define REGION_512K    0x00000012U
+#define REGION_1M      0x00000013U
+#define REGION_2M      0x00000014U
+#define REGION_4M      0x00000015U
+#define REGION_8M      0x00000016U
+#define REGION_16M     0x00000017U
+#define REGION_32M     0x00000018U
+#define REGION_64M     0x00000019U
+#define REGION_128M    0x0000001AU
+#define REGION_256M    0x0000001BU
+#define REGION_512M    0x0000001CU
+#define REGION_1G      0x0000001DU
+#define REGION_2G      0x0000001EU
+#define REGION_4G      0x0000001FU
+
+#define REGION_EN  0x00000001U
+
+
+
+#define SHAREABLE				0x00000004U 	/*shareable */
+#define STRONG_ORDERD_SHARED	0x00000000U	/*strongly ordered, always shareable*/
+
+#define DEVICE_SHARED			0x00000001U	/*device, shareable*/
+#define DEVICE_NONSHARED		0x00000010U	/*device, non shareable*/
+
+#define NORM_NSHARED_WT_NWA		0x00000002U 	/*Outer and Inner write-through, no write-allocate non-shareable*/
+#define NORM_SHARED_WT_NWA		0x00000006U 	/*Outer and Inner write-through, no write-allocate shareable*/
+
+#define NORM_NSHARED_WB_NWA 	0x00000003U 	/*Outer and Inner write-back, no write-allocate non shareable*/
+#define NORM_SHARED_WB_NWA 		0x00000007U 	/*Outer and Inner write-back, no write-allocate shareable*/
+
+#define NORM_NSHARED_NCACHE 	0x00000008U 	/*Outer and Inner Non cacheable  non shareable*/
+#define NORM_SHARED_NCACHE 		0x0000000CU 	/*Outer and Inner Non cacheable shareable*/
+
+#define NORM_NSHARED_WB_WA 		0x0000000BU 	/*Outer and Inner write-back non shared*/
+#define NORM_SHARED_WB_WA 		0x0000000FU 	/*Outer and Inner write-back shared*/
+
+/* inner and outer cache policies can be combined for different combinations */
+
+#define NORM_IN_POLICY_NCACHE	0x00000020U	/*inner non cacheable*/
+#define NORM_IN_POLICY_WB_WA	0x00000021U	/*inner write back write allocate*/
+#define NORM_IN_POLICY_WT_NWA	0x00000022U	/*inner write through no write allocate*/
+#define NORM_IN_POLICY_WB_NWA	0x00000023U	/*inner write back no write allocate*/
+
+#define NORM_OUT_POLICY_NCACHE	0x00000020U	/*outer non cacheable*/
+#define NORM_OUT_POLICY_WB_WA	0x00000028U	/*outer write back write allocate*/
+#define NORM_OUT_POLICY_WT_NWA	0x00000030U	/*outer write through no write allocate*/
+#define NORM_OUT_POLICY_WB_NWA	0x00000038U	/*outer write back no write allocate*/
+
+#define NO_ACCESS				(0x00000000U<<8U)	/*No access*/
+#define PRIV_RW_USER_NA			(0x00000001U<<8U) /*Privileged access only*/
+#define PRIV_RW_USER_RO			(0x00000002U<<8U) /*Writes in User mode generate permission faults*/
+#define	PRIV_RW_USER_RW			(0x00000003U<<8U)	/*Full Access*/
+#define PRIV_RO_USER_NA			(0x00000005U<<8U) /*Privileged eead only*/
+#define PRIV_RO_USER_RO			(0x00000006U<<8U) /*Privileged/User read-only*/
+
+#define EXECUTE_NEVER  			(0x00000001U<<12U)  /* Bit 12*/
+
+
+/* CP15 defines */
+
+/* C0 Register defines */
+#define XREG_CP15_MAIN_ID			"p15, 0, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_TYPE			"p15, 0, %0,  c0,  c0, 1"
+#define XREG_CP15_TCM_TYPE			"p15, 0, %0,  c0,  c0, 2"
+#define XREG_CP15_TLB_TYPE			"p15, 0, %0,  c0,  c0, 3"
+#define XREG_CP15_MPU_TYPE			"p15, 0, %0,  c0,  c0, 4"
+#define XREG_CP15_MULTI_PROC_AFFINITY		"p15, 0, %0,  c0,  c0, 5"
+
+#define XREG_CP15_PROC_FEATURE_0		"p15, 0, %0,  c0,  c1, 0"
+#define XREG_CP15_PROC_FEATURE_1		"p15, 0, %0,  c0,  c1, 1"
+#define XREG_CP15_DEBUG_FEATURE_0		"p15, 0, %0,  c0,  c1, 2"
+#define XREG_CP15_MEMORY_FEATURE_0		"p15, 0, %0,  c0,  c1, 4"
+#define XREG_CP15_MEMORY_FEATURE_1		"p15, 0, %0,  c0,  c1, 5"
+#define XREG_CP15_MEMORY_FEATURE_2		"p15, 0, %0,  c0,  c1, 6"
+#define XREG_CP15_MEMORY_FEATURE_3		"p15, 0, %0,  c0,  c1, 7"
+
+#define XREG_CP15_INST_FEATURE_0		"p15, 0, %0,  c0,  c2, 0"
+#define XREG_CP15_INST_FEATURE_1		"p15, 0, %0,  c0,  c2, 1"
+#define XREG_CP15_INST_FEATURE_2		"p15, 0, %0,  c0,  c2, 2"
+#define XREG_CP15_INST_FEATURE_3		"p15, 0, %0,  c0,  c2, 3"
+#define XREG_CP15_INST_FEATURE_4		"p15, 0, %0,  c0,  c2, 4"
+#define XREG_CP15_INST_FEATURE_5		"p15, 0, %0,  c0,  c2, 5"
+
+#define XREG_CP15_CACHE_SIZE_ID			"p15, 1, %0,  c0,  c0, 0"
+#define XREG_CP15_CACHE_LEVEL_ID		"p15, 1, %0,  c0,  c0, 1"
+#define XREG_CP15_AUXILARY_ID			"p15, 1, %0,  c0,  c0, 7"
+
+#define XREG_CP15_CACHE_SIZE_SEL		"p15, 2, %0,  c0,  c0, 0"
+
+/* C1 Register Defines */
+#define XREG_CP15_SYS_CONTROL			"p15, 0, %0,  c1,  c0, 0"
+#define XREG_CP15_AUX_CONTROL			"p15, 0, %0,  c1,  c0, 1"
+#define XREG_CP15_CP_ACCESS_CONTROL		"p15, 0, %0,  c1,  c0, 2"
+
+
+/* XREG_CP15_CONTROL bit defines */
+#define XREG_CP15_CONTROL_TE_BIT		0x40000000U
+#define XREG_CP15_CONTROL_AFE_BIT		0x20000000U
+#define XREG_CP15_CONTROL_TRE_BIT		0x10000000U
+#define XREG_CP15_CONTROL_NMFI_BIT		0x08000000U
+#define XREG_CP15_CONTROL_EE_BIT		0x02000000U
+#define XREG_CP15_CONTROL_HA_BIT		0x00020000U
+#define XREG_CP15_CONTROL_RR_BIT		0x00004000U
+#define XREG_CP15_CONTROL_V_BIT			0x00002000U
+#define XREG_CP15_CONTROL_I_BIT			0x00001000U
+#define XREG_CP15_CONTROL_Z_BIT			0x00000800U
+#define XREG_CP15_CONTROL_SW_BIT		0x00000400U
+#define XREG_CP15_CONTROL_B_BIT			0x00000080U
+#define XREG_CP15_CONTROL_C_BIT			0x00000004U
+#define XREG_CP15_CONTROL_A_BIT			0x00000002U
+#define XREG_CP15_CONTROL_M_BIT			0x00000001U
+/* C2 Register Defines */
+/* Not Used */
+
+/* C3 Register Defines */
+/* Not Used */
+
+/* C4 Register Defines */
+/* Not Used */
+
+/* C5 Register Defines */
+#define XREG_CP15_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 0"
+#define XREG_CP15_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c0, 1"
+
+#define XREG_CP15_AUX_DATA_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 0"
+#define XREG_CP15_AUX_INST_FAULT_STATUS		"p15, 0, %0,  c5,  c1, 1"
+
+/* C6 Register Defines */
+#define XREG_CP15_DATA_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 0"
+#define XREG_CP15_INST_FAULT_ADDRESS		"p15, 0, %0,  c6,  c0, 2"
+
+#define XREG_CP15_MPU_REG_BASEADDR			"p15, 0, %0,  c6,  c1, 0"
+#define XREG_CP15_MPU_REG_SIZE_EN			"p15, 0, %0,  c6,  c1, 2"
+#define XREG_CP15_MPU_REG_ACCESS_CTRL		"p15, 0, %0,  c6,  c1, 4"
+
+#define XREG_CP15_MPU_MEMORY_REG_NUMBER			"p15, 0, %0,  c6,  c2, 0"
+
+/* C7 Register Defines */
+#define XREG_CP15_NOP				"p15, 0, %0,  c7,  c0, 4"
+
+#define XREG_CP15_INVAL_IC_POU			"p15, 0, %0,  c7,  c5, 0"
+#define XREG_CP15_INVAL_IC_LINE_MVA_POU		"p15, 0, %0,  c7,  c5, 1"
+
+/* The CP15 register access below has been deprecated in favor of the new
+ * isb instruction in Cortex R5.
+ */
+#define XREG_CP15_INST_SYNC_BARRIER		"p15, 0, %0,  c7,  c5, 4"
+#define XREG_CP15_INVAL_BRANCH_ARRAY		"p15, 0, %0,  c7,  c5, 6"
+#define XREG_CP15_INVAL_BRANCH_ARRAY_LINE		"p15, 0, %0,  c7,  c5, 7"
+
+#define XREG_CP15_INVAL_DC_LINE_MVA_POC		"p15, 0, %0,  c7,  c6, 1"
+#define XREG_CP15_INVAL_DC_LINE_SW		"p15, 0, %0,  c7,  c6, 2"
+
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POC		"p15, 0, %0,  c7, c10, 1"
+#define XREG_CP15_CLEAN_DC_LINE_SW		"p15, 0, %0,  c7, c10, 2"
+
+#define XREG_CP15_INVAL_DC_ALL		"p15, 0, %0,  c15, c5, 0"
+/* The next two CP15 register accesses below have been deprecated in favor
+ * of the new dsb and dmb instructions in Cortex R5.
+ */
+#define XREG_CP15_DATA_SYNC_BARRIER		"p15, 0, %0,  c7, c10, 4"
+#define XREG_CP15_DATA_MEMORY_BARRIER		"p15, 0, %0,  c7, c10, 5"
+
+#define XREG_CP15_CLEAN_DC_LINE_MVA_POU		"p15, 0, %0,  c7, c11, 1"
+
+#define XREG_CP15_NOP2				"p15, 0, %0,  c7, c13, 1"
+
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_MVA_POC	"p15, 0, %0,  c7, c14, 1"
+#define XREG_CP15_CLEAN_INVAL_DC_LINE_SW	"p15, 0, %0,  c7, c14, 2"
+
+/* C8 Register Defines */
+/* Not Used */
+
+
+/* C9 Register Defines */
+
+#define XREG_CP15_ATCM_REG_SIZE_ADDR		"p15, 0, %0,  c9, c1, 1"
+#define XREG_CP15_BTCM_REG_SIZE_ADDR		"p15, 0, %0,  c9, c1, 0"
+#define XREG_CP15_TCM_SELECTION				"p15, 0, %0,  c9, c2, 0"
+
+#define XREG_CP15_PERF_MONITOR_CTRL		"p15, 0, %0,  c9, c12, 0"
+#define XREG_CP15_COUNT_ENABLE_SET		"p15, 0, %0,  c9, c12, 1"
+#define XREG_CP15_COUNT_ENABLE_CLR		"p15, 0, %0,  c9, c12, 2"
+#define XREG_CP15_V_FLAG_STATUS			"p15, 0, %0,  c9, c12, 3"
+#define XREG_CP15_SW_INC			"p15, 0, %0,  c9, c12, 4"
+#define XREG_CP15_EVENT_CNTR_SEL		"p15, 0, %0,  c9, c12, 5"
+
+#define XREG_CP15_PERF_CYCLE_COUNTER		"p15, 0, %0,  c9, c13, 0"
+#define XREG_CP15_EVENT_TYPE_SEL		"p15, 0, %0,  c9, c13, 1"
+#define XREG_CP15_PERF_MONITOR_COUNT		"p15, 0, %0,  c9, c13, 2"
+
+#define XREG_CP15_USER_ENABLE			"p15, 0, %0,  c9, c14, 0"
+#define XREG_CP15_INTR_ENABLE_SET		"p15, 0, %0,  c9, c14, 1"
+#define XREG_CP15_INTR_ENABLE_CLR		"p15, 0, %0,  c9, c14, 2"
+
+/* C10 Register Defines */
+/* Not used */
+
+/* C11 Register Defines */
+/* Not used */
+
+/* C12 Register Defines */
+/* Not used */
+
+/* C13 Register Defines */
+#define XREG_CP15_CONTEXT_ID			"p15, 0, %0, c13,  c0, 1"
+#define USER_RW_THREAD_PID			"p15, 0, %0, c13,  c0, 2"
+#define USER_RO_THREAD_PID			"p15, 0, %0, c13,  c0, 3"
+#define USER_PRIV_THREAD_PID			"p15, 0, %0, c13,  c0, 4"
+
+/* C14 Register Defines */
+/* not used */
+
+/* C15 Register Defines */
+#define XREG_CP15_SEC_AUX_CTRL			"p15, 0, %0, c15,  c0, 0"
+
+
+
+
+/* MPE register definitions */
+#define XREG_FPSID				c0
+#define XREG_FPSCR				c1
+#define XREG_MVFR1				c6
+#define XREG_MVFR0				c7
+#define XREG_FPEXC				c8
+#define XREG_FPINST				c9
+#define XREG_FPINST2			c10
+
+/* FPSID bits */
+#define XREG_FPSID_IMPLEMENTER_BIT	(24U)
+#define XREG_FPSID_IMPLEMENTER_MASK	(0x000000FFU << FPSID_IMPLEMENTER_BIT)
+#define XREG_FPSID_SOFTWARE		(0X00000001U << 23U)
+#define XREG_FPSID_ARCH_BIT		(16U)
+#define XREG_FPSID_ARCH_MASK		(0x0000000FU  << FPSID_ARCH_BIT)
+#define XREG_FPSID_PART_BIT		(8U)
+#define XREG_FPSID_PART_MASK		(0x000000FFU << FPSID_PART_BIT)
+#define XREG_FPSID_VARIANT_BIT		(4U)
+#define XREG_FPSID_VARIANT_MASK		(0x0000000FU  << FPSID_VARIANT_BIT)
+#define XREG_FPSID_REV_BIT		(0U)
+#define XREG_FPSID_REV_MASK		(0x0000000FU  << FPSID_REV_BIT)
+
+/* FPSCR bits */
+#define XREG_FPSCR_N_BIT		(0X00000001U << 31U)
+#define XREG_FPSCR_Z_BIT		(0X00000001U << 30U)
+#define XREG_FPSCR_C_BIT		(0X00000001U << 29U)
+#define XREG_FPSCR_V_BIT		(0X00000001U << 28U)
+#define XREG_FPSCR_QC			(0X00000001U << 27U)
+#define XREG_FPSCR_AHP			(0X00000001U << 26U)
+#define XREG_FPSCR_DEFAULT_NAN		(0X00000001U << 25U)
+#define XREG_FPSCR_FLUSHTOZERO		(0X00000001U << 24U)
+#define XREG_FPSCR_ROUND_NEAREST	(0X00000000U << 22U)
+#define XREG_FPSCR_ROUND_PLUSINF	(0X00000001U << 22U)
+#define XREG_FPSCR_ROUND_MINUSINF	(0X00000002U << 22U)
+#define XREG_FPSCR_ROUND_TOZERO		(0X00000003U << 22U)
+#define XREG_FPSCR_RMODE_BIT		(22U)
+#define XREG_FPSCR_RMODE_MASK		(0X00000003U << FPSCR_RMODE_BIT)
+#define XREG_FPSCR_STRIDE_BIT		(20U)
+#define XREG_FPSCR_STRIDE_MASK		(0X00000003U << FPSCR_STRIDE_BIT)
+#define XREG_FPSCR_LENGTH_BIT		(16U)
+#define XREG_FPSCR_LENGTH_MASK		(0X00000007U << FPSCR_LENGTH_BIT)
+#define XREG_FPSCR_IDC			(0X00000001U << 7U)
+#define XREG_FPSCR_IXC			(0X00000001U << 4U)
+#define XREG_FPSCR_UFC			(0X00000001U << 3U)
+#define XREG_FPSCR_OFC			(0X00000001U << 2U)
+#define XREG_FPSCR_DZC			(0X00000001U << 1U)
+#define XREG_FPSCR_IOC			(0X00000001U << 0U)
+
+/* MVFR0 bits */
+#define XREG_MVFR0_RMODE_BIT		(28U)
+#define XREG_MVFR0_RMODE_MASK		(0x0000000FU << XREG_MVFR0_RMODE_BIT)
+#define XREG_MVFR0_SHORT_VEC_BIT	(24U)
+#define XREG_MVFR0_SHORT_VEC_MASK	(0x0000000FU << XREG_MVFR0_SHORT_VEC_BIT)
+#define XREG_MVFR0_SQRT_BIT		(20U)
+#define XREG_MVFR0_SQRT_MASK		(0x0000000FU << XREG_MVFR0_SQRT_BIT)
+#define XREG_MVFR0_DIVIDE_BIT		(16U)
+#define XREG_MVFR0_DIVIDE_MASK		(0x0000000FU << XREG_MVFR0_DIVIDE_BIT)
+#define XREG_MVFR0_EXEC_TRAP_BIT	(12U)
+#define XREG_MVFR0_EXEC_TRAP_MASK	(0x0000000FU << XREG_MVFR0_EXEC_TRAP_BIT)
+#define XREG_MVFR0_DP_BIT		(8U)
+#define XREG_MVFR0_DP_MASK		(0x0000000FU << XREG_MVFR0_DP_BIT)
+#define XREG_MVFR0_SP_BIT		(4U)
+#define XREG_MVFR0_SP_MASK		(0x0000000FU << XREG_MVFR0_SP_BIT)
+#define XREG_MVFR0_A_SIMD_BIT		(0U)
+#define XREG_MVFR0_A_SIMD_MASK		(0x0000000FU << MVFR0_A_SIMD_BIT)
+
+/* FPEXC bits */
+#define XREG_FPEXC_EX			(0X00000001U << 31U)
+#define XREG_FPEXC_EN			(0X00000001U << 30U)
+#define XREG_FPEXC_DEX			(0X00000001U << 29U)
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XREG_CORTEXR5_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h
new file mode 100644
index 000000000..ba5f96b20
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xstatus.h
@@ -0,0 +1,430 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xstatus.h
+*
+* This file contains Xilinx software status codes.  Status codes have their
+* own data type called int.  These codes are used throughout the Xilinx
+* device drivers.
+*
+******************************************************************************/
+
+#ifndef XSTATUS_H		/* prevent circular inclusions */
+#define XSTATUS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+
+/************************** Constant Definitions *****************************/
+
+/*********************** Common statuses 0 - 500 *****************************/
+
+#define XST_SUCCESS                     0L
+#define XST_FAILURE                     1L
+#define XST_DEVICE_NOT_FOUND            2L
+#define XST_DEVICE_BLOCK_NOT_FOUND      3L
+#define XST_INVALID_VERSION             4L
+#define XST_DEVICE_IS_STARTED           5L
+#define XST_DEVICE_IS_STOPPED           6L
+#define XST_FIFO_ERROR                  7L	/* an error occurred during an
+						   operation with a FIFO such as
+						   an underrun or overrun, this
+						   error requires the device to
+						   be reset */
+#define XST_RESET_ERROR                 8L	/* an error occurred which requires
+						   the device to be reset */
+#define XST_DMA_ERROR                   9L	/* a DMA error occurred, this error
+						   typically requires the device
+						   using the DMA to be reset */
+#define XST_NOT_POLLED                  10L	/* the device is not configured for
+						   polled mode operation */
+#define XST_FIFO_NO_ROOM                11L	/* a FIFO did not have room to put
+						   the specified data into */
+#define XST_BUFFER_TOO_SMALL            12L	/* the buffer is not large enough
+						   to hold the expected data */
+#define XST_NO_DATA                     13L	/* there was no data available */
+#define XST_REGISTER_ERROR              14L	/* a register did not contain the
+						   expected value */
+#define XST_INVALID_PARAM               15L	/* an invalid parameter was passed
+						   into the function */
+#define XST_NOT_SGDMA                   16L	/* the device is not configured for
+						   scatter-gather DMA operation */
+#define XST_LOOPBACK_ERROR              17L	/* a loopback test failed */
+#define XST_NO_CALLBACK                 18L	/* a callback has not yet been
+						   registered */
+#define XST_NO_FEATURE                  19L	/* device is not configured with
+						   the requested feature */
+#define XST_NOT_INTERRUPT               20L	/* device is not configured for
+						   interrupt mode operation */
+#define XST_DEVICE_BUSY                 21L	/* device is busy */
+#define XST_ERROR_COUNT_MAX             22L	/* the error counters of a device
+						   have maxed out */
+#define XST_IS_STARTED                  23L	/* used when part of device is
+						   already started i.e.
+						   sub channel */
+#define XST_IS_STOPPED                  24L	/* used when part of device is
+						   already stopped i.e.
+						   sub channel */
+#define XST_DATA_LOST                   26L	/* driver defined error */
+#define XST_RECV_ERROR                  27L	/* generic receive error */
+#define XST_SEND_ERROR                  28L	/* generic transmit error */
+#define XST_NOT_ENABLED                 29L	/* a requested service is not
+						   available because it has not
+						   been enabled */
+
+/***************** Utility Component statuses 401 - 500  *********************/
+
+#define XST_MEMTEST_FAILED              401L	/* memory test failed */
+
+
+/***************** Common Components statuses 501 - 1000 *********************/
+
+/********************* Packet Fifo statuses 501 - 510 ************************/
+
+#define XST_PFIFO_LACK_OF_DATA          501L	/* not enough data in FIFO   */
+#define XST_PFIFO_NO_ROOM               502L	/* not enough room in FIFO   */
+#define XST_PFIFO_BAD_REG_VALUE         503L	/* self test, a register value
+						   was invalid after reset */
+#define XST_PFIFO_ERROR                 504L	/* generic packet FIFO error */
+#define XST_PFIFO_DEADLOCK              505L	/* packet FIFO is reporting
+						 * empty and full simultaneously
+						 */
+
+/************************** DMA statuses 511 - 530 ***************************/
+
+#define XST_DMA_TRANSFER_ERROR          511L	/* self test, DMA transfer
+						   failed */
+#define XST_DMA_RESET_REGISTER_ERROR    512L	/* self test, a register value
+						   was invalid after reset */
+#define XST_DMA_SG_LIST_EMPTY           513L	/* scatter gather list contains
+						   no buffer descriptors ready
+						   to be processed */
+#define XST_DMA_SG_IS_STARTED           514L	/* scatter gather not stopped */
+#define XST_DMA_SG_IS_STOPPED           515L	/* scatter gather not running */
+#define XST_DMA_SG_LIST_FULL            517L	/* all the buffer desciptors of
+						   the scatter gather list are
+						   being used */
+#define XST_DMA_SG_BD_LOCKED            518L	/* the scatter gather buffer
+						   descriptor which is to be
+						   copied over in the scatter
+						   list is locked */
+#define XST_DMA_SG_NOTHING_TO_COMMIT    519L	/* no buffer descriptors have been
+						   put into the scatter gather
+						   list to be commited */
+#define XST_DMA_SG_COUNT_EXCEEDED       521L	/* the packet count threshold
+						   specified was larger than the
+						   total # of buffer descriptors
+						   in the scatter gather list */
+#define XST_DMA_SG_LIST_EXISTS          522L	/* the scatter gather list has
+						   already been created */
+#define XST_DMA_SG_NO_LIST              523L	/* no scatter gather list has
+						   been created */
+#define XST_DMA_SG_BD_NOT_COMMITTED     524L	/* the buffer descriptor which was
+						   being started was not committed
+						   to the list */
+#define XST_DMA_SG_NO_DATA              525L	/* the buffer descriptor to start
+						   has already been used by the
+						   hardware so it can't be reused
+						 */
+#define XST_DMA_SG_LIST_ERROR           526L	/* general purpose list access
+						   error */
+#define XST_DMA_BD_ERROR                527L	/* general buffer descriptor
+						   error */
+
+/************************** IPIF statuses 531 - 550 ***************************/
+
+#define XST_IPIF_REG_WIDTH_ERROR        531L	/* an invalid register width
+						   was passed into the function */
+#define XST_IPIF_RESET_REGISTER_ERROR   532L	/* the value of a register at
+						   reset was not valid */
+#define XST_IPIF_DEVICE_STATUS_ERROR    533L	/* a write to the device interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_DEVICE_ACK_ERROR       534L	/* the device interrupt status
+						   register did not reset when
+						   acked */
+#define XST_IPIF_DEVICE_ENABLE_ERROR    535L	/* the device interrupt enable
+						   register was not updated when
+						   other registers changed */
+#define XST_IPIF_IP_STATUS_ERROR        536L	/* a write to the IP interrupt
+						   status register did not read
+						   back correctly */
+#define XST_IPIF_IP_ACK_ERROR           537L	/* the IP interrupt status register
+						   did not reset when acked */
+#define XST_IPIF_IP_ENABLE_ERROR        538L	/* IP interrupt enable register was
+						   not updated correctly when other
+						   registers changed */
+#define XST_IPIF_DEVICE_PENDING_ERROR   539L	/* The device interrupt pending
+						   register did not indicate the
+						   expected value */
+#define XST_IPIF_DEVICE_ID_ERROR        540L	/* The device interrupt ID register
+						   did not indicate the expected
+						   value */
+#define XST_IPIF_ERROR                  541L	/* generic ipif error */
+
+/****************** Device specific statuses 1001 - 4095 *********************/
+
+/********************* Ethernet statuses 1001 - 1050 *************************/
+
+#define XST_EMAC_MEMORY_SIZE_ERROR  1001L	/* Memory space is not big enough
+						 * to hold the minimum number of
+						 * buffers or descriptors */
+#define XST_EMAC_MEMORY_ALLOC_ERROR 1002L	/* Memory allocation failed */
+#define XST_EMAC_MII_READ_ERROR     1003L	/* MII read error */
+#define XST_EMAC_MII_BUSY           1004L	/* An MII operation is in progress */
+#define XST_EMAC_OUT_OF_BUFFERS     1005L	/* Driver is out of buffers */
+#define XST_EMAC_PARSE_ERROR        1006L	/* Invalid driver init string */
+#define XST_EMAC_COLLISION_ERROR    1007L	/* Excess deferral or late
+						 * collision on polled send */
+
+/*********************** UART statuses 1051 - 1075 ***************************/
+#define XST_UART
+
+#define XST_UART_INIT_ERROR         1051L
+#define XST_UART_START_ERROR        1052L
+#define XST_UART_CONFIG_ERROR       1053L
+#define XST_UART_TEST_FAIL          1054L
+#define XST_UART_BAUD_ERROR         1055L
+#define XST_UART_BAUD_RANGE         1056L
+
+
+/************************ IIC statuses 1076 - 1100 ***************************/
+
+#define XST_IIC_SELFTEST_FAILED         1076	/* self test failed            */
+#define XST_IIC_BUS_BUSY                1077	/* bus found busy              */
+#define XST_IIC_GENERAL_CALL_ADDRESS    1078	/* mastersend attempted with   */
+					     /* general call address        */
+#define XST_IIC_STAND_REG_RESET_ERROR   1079	/* A non parameterizable reg   */
+					     /* value after reset not valid */
+#define XST_IIC_TX_FIFO_REG_RESET_ERROR 1080	/* Tx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_RX_FIFO_REG_RESET_ERROR 1081	/* Rx fifo included in design  */
+					     /* value after reset not valid */
+#define XST_IIC_TBA_REG_RESET_ERROR     1082	/* 10 bit addr incl in design  */
+					     /* value after reset not valid */
+#define XST_IIC_CR_READBACK_ERROR       1083	/* Read of the control register */
+					     /* didn't return value written */
+#define XST_IIC_DTR_READBACK_ERROR      1084	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_DRR_READBACK_ERROR      1085	/* Read of the data Receive reg */
+					     /* didn't return value written */
+#define XST_IIC_ADR_READBACK_ERROR      1086	/* Read of the data Tx reg     */
+					     /* didn't return value written */
+#define XST_IIC_TBA_READBACK_ERROR      1087	/* Read of the 10 bit addr reg */
+					     /* didn't return written value */
+#define XST_IIC_NOT_SLAVE               1088	/* The device isn't a slave    */
+
+/*********************** ATMC statuses 1101 - 1125 ***************************/
+
+#define XST_ATMC_ERROR_COUNT_MAX    1101L	/* the error counters in the ATM
+						   controller hit the max value
+						   which requires the statistics
+						   to be cleared */
+
+/*********************** Flash statuses 1126 - 1150 **************************/
+
+#define XST_FLASH_BUSY                1126L	/* Flash is erasing or programming
+						 */
+#define XST_FLASH_READY               1127L	/* Flash is ready for commands */
+#define XST_FLASH_ERROR               1128L	/* Flash had detected an internal
+						   error. Use XFlash_DeviceControl
+						   to retrieve device specific codes
+						 */
+#define XST_FLASH_ERASE_SUSPENDED     1129L	/* Flash is in suspended erase state
+						 */
+#define XST_FLASH_WRITE_SUSPENDED     1130L	/* Flash is in suspended write state
+						 */
+#define XST_FLASH_PART_NOT_SUPPORTED  1131L	/* Flash type not supported by
+						   driver */
+#define XST_FLASH_NOT_SUPPORTED       1132L	/* Operation not supported */
+#define XST_FLASH_TOO_MANY_REGIONS    1133L	/* Too many erase regions */
+#define XST_FLASH_TIMEOUT_ERROR       1134L	/* Programming or erase operation
+						   aborted due to a timeout */
+#define XST_FLASH_ADDRESS_ERROR       1135L	/* Accessed flash outside its
+						   addressible range */
+#define XST_FLASH_ALIGNMENT_ERROR     1136L	/* Write alignment error */
+#define XST_FLASH_BLOCKING_CALL_ERROR 1137L	/* Couldn't return immediately from
+						   write/erase function with
+						   XFL_NON_BLOCKING_WRITE/ERASE
+						   option cleared */
+#define XST_FLASH_CFI_QUERY_ERROR     1138L	/* Failed to query the device */
+
+/*********************** SPI statuses 1151 - 1175 ****************************/
+
+#define XST_SPI_MODE_FAULT          1151	/* master was selected as slave */
+#define XST_SPI_TRANSFER_DONE       1152	/* data transfer is complete */
+#define XST_SPI_TRANSMIT_UNDERRUN   1153	/* slave underruns transmit register */
+#define XST_SPI_RECEIVE_OVERRUN     1154	/* device overruns receive register */
+#define XST_SPI_NO_SLAVE            1155	/* no slave has been selected yet */
+#define XST_SPI_TOO_MANY_SLAVES     1156	/* more than one slave is being
+						 * selected */
+#define XST_SPI_NOT_MASTER          1157	/* operation is valid only as master */
+#define XST_SPI_SLAVE_ONLY          1158	/* device is configured as slave-only
+						 */
+#define XST_SPI_SLAVE_MODE_FAULT    1159	/* slave was selected while disabled */
+#define XST_SPI_SLAVE_MODE          1160	/* device has been addressed as slave */
+#define XST_SPI_RECEIVE_NOT_EMPTY   1161	/* device received data in slave mode */
+
+#define XST_SPI_COMMAND_ERROR       1162	/* unrecognised command - qspi only */
+
+/********************** OPB Arbiter statuses 1176 - 1200 *********************/
+
+#define XST_OPBARB_INVALID_PRIORITY  1176	/* the priority registers have either
+						 * one master assigned to two or more
+						 * priorities, or one master not
+						 * assigned to any priority
+						 */
+#define XST_OPBARB_NOT_SUSPENDED     1177	/* an attempt was made to modify the
+						 * priority levels without first
+						 * suspending the use of priority
+						 * levels
+						 */
+#define XST_OPBARB_PARK_NOT_ENABLED  1178	/* bus parking by id was enabled but
+						 * bus parking was not enabled
+						 */
+#define XST_OPBARB_NOT_FIXED_PRIORITY 1179	/* the arbiter must be in fixed
+						 * priority mode to allow the
+						 * priorities to be changed
+						 */
+
+/************************ Intc statuses 1201 - 1225 **************************/
+
+#define XST_INTC_FAIL_SELFTEST      1201	/* self test failed */
+#define XST_INTC_CONNECT_ERROR      1202	/* interrupt already in use */
+
+/********************** TmrCtr statuses 1226 - 1250 **************************/
+
+#define XST_TMRCTR_TIMER_FAILED     1226	/* self test failed */
+
+/********************** WdtTb statuses 1251 - 1275 ***************************/
+
+#define XST_WDTTB_TIMER_FAILED      1251L
+
+/********************** PlbArb statuses 1276 - 1300 **************************/
+
+#define XST_PLBARB_FAIL_SELFTEST    1276L
+
+/********************** Plb2Opb statuses 1301 - 1325 *************************/
+
+#define XST_PLB2OPB_FAIL_SELFTEST   1301L
+
+/********************** Opb2Plb statuses 1326 - 1350 *************************/
+
+#define XST_OPB2PLB_FAIL_SELFTEST   1326L
+
+/********************** SysAce statuses 1351 - 1360 **************************/
+
+#define XST_SYSACE_NO_LOCK          1351L	/* No MPU lock has been granted */
+
+/********************** PCI Bridge statuses 1361 - 1375 **********************/
+
+#define XST_PCI_INVALID_ADDRESS     1361L
+
+/********************** FlexRay constants 1400 - 1409 *************************/
+
+#define XST_FR_TX_ERROR			1400
+#define XST_FR_TX_BUSY			1401
+#define XST_FR_BUF_LOCKED		1402
+#define XST_FR_NO_BUF			1403
+
+/****************** USB constants 1410 - 1420  *******************************/
+
+#define XST_USB_ALREADY_CONFIGURED	1410
+#define XST_USB_BUF_ALIGN_ERROR		1411
+#define XST_USB_NO_DESC_AVAILABLE	1412
+#define XST_USB_BUF_TOO_BIG		1413
+#define XST_USB_NO_BUF			1414
+
+/****************** HWICAP constants 1421 - 1429  *****************************/
+
+#define XST_HWICAP_WRITE_DONE		1421
+
+
+/****************** AXI VDMA constants 1430 - 1440  *****************************/
+
+#define XST_VDMA_MISMATCH_ERROR		1430
+
+/*********************** NAND Flash statuses 1441 - 1459  *********************/
+
+#define XST_NAND_BUSY			1441L	/* Flash is erasing or
+						 * programming
+						 */
+#define XST_NAND_READY			1442L	/* Flash is ready for commands
+						 */
+#define XST_NAND_ERROR			1443L	/* Flash had detected an
+						 * internal error.
+						 */
+#define XST_NAND_PART_NOT_SUPPORTED	1444L	/* Flash type not supported by
+						 * driver
+						 */
+#define XST_NAND_OPT_NOT_SUPPORTED	1445L	/* Operation not supported
+						 */
+#define XST_NAND_TIMEOUT_ERROR		1446L	/* Programming or erase
+						 * operation aborted due to a
+						 * timeout
+						 */
+#define XST_NAND_ADDRESS_ERROR		1447L	/* Accessed flash outside its
+						 * addressible range
+						 */
+#define XST_NAND_ALIGNMENT_ERROR	1448L	/* Write alignment error
+						 */
+#define XST_NAND_PARAM_PAGE_ERROR	1449L	/* Failed to read parameter
+						 * page of the device
+						 */
+#define XST_NAND_CACHE_ERROR		1450L	/* Flash page buffer error
+						 */
+
+#define XST_NAND_WRITE_PROTECTED	1451L	/* Flash is write protected
+						 */
+
+/**************************** Type Definitions *******************************/
+
+typedef int XStatus;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c
new file mode 100644
index 000000000..a17ee404b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.c
@@ -0,0 +1,187 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.c
+*
+* This file contains low level functions to get/set time from the Global Timer
+* register in the ARM Cortex R5 core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp    08/29/14 First release
+* 5.04  pkp	   02/19/16 XTime_StartTimer API is added to configure TTC3 timer
+*						when present. XTime_GetTime is modified to give 64bit
+*						output using timer overflow when TTC3 present.
+*						XTime_SetTime is modified to configure TTC3 counter
+*						value when present.
+* 5.04	pkp	   03/11/16 XTime_StartTimer is modified to avoid enabling the
+*						overflow interrupt and XTime_GetTime & XTime_SetTime
+*						are modified to read and write TTC counter value
+*						respectively
+* 5.04	pkp
+* 

+*
+* @note		None.
+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xtime_l.h"
+#include "xpseudo_asm.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/**************************** Type Definitions *******************************/
+
+/************************** Constant Definitions *****************************/
+#define RST_LPD_IOU2 					0xFF5E0238U
+#define RST_LPD_IOU2_TTC3_RESET_MASK	0x00004000U
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/* Function definitions are applicable only when TTC3 is present*/
+#ifdef SLEEP_TIMER_BASEADDR
+/****************************************************************************
+*
+* Start the TTC timer.
+*
+* @param	None.
+*
+* @return	None.
+*
+* @note		In multiprocessor environment reference time will reset/lost for
+*		all processors, when this function called by any one processor.
+*
+****************************************************************************/
+void XTime_StartTimer(void)
+{
+	u32 LpdRst;
+	u32 TimerPrescalar;
+	u32 TimerCntrl;
+
+	LpdRst = Xil_In32(RST_LPD_IOU2);
+	if ((LpdRst & RST_LPD_IOU2_TTC3_RESET_MASK) != 0 ) {
+			LpdRst = LpdRst & (~RST_LPD_IOU2_TTC3_RESET_MASK);
+			Xil_Out32(RST_LPD_IOU2, LpdRst);
+
+	} else {
+		TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
+								SLEEP_TIMER_CNTR_CNTRL_OFFSET);
+		/* check if Timer is disabled */
+		if ((TimerCntrl & SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK) == 0) {
+			TimerPrescalar = Xil_In32(SLEEP_TIMER_BASEADDR +
+									SLEEP_TIMER_CLK_CNTRL_OFFSET);
+
+		/* check if Timer is configured with proper functionalty for sleep */
+			if ((TimerPrescalar & SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK) == 0)
+						return;
+		}
+	}
+	/* Disable the timer to configure */
+	TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
+							SLEEP_TIMER_CNTR_CNTRL_OFFSET);
+	TimerCntrl = TimerCntrl | SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK;
+	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
+				TimerCntrl);
+
+	/* Disable the prescalar */
+	TimerPrescalar = Xil_In32(SLEEP_TIMER_BASEADDR +
+								SLEEP_TIMER_CLK_CNTRL_OFFSET);
+	TimerPrescalar = TimerPrescalar & (~SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK);
+	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CLK_CNTRL_OFFSET,
+				TimerPrescalar);
+
+	/* Enable the Timer */
+	TimerCntrl = SLEEP_TIMER_COUNTER_CONTROL_RST_MASK &
+					(~SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK);
+	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
+				TimerCntrl);
+
+}
+/****************************************************************************
+*
+* Set the time in the Timer Counter Register.
+*
+* @param	Value to be written to the Timer Counter Register.
+*
+* @return	None.
+*
+* @note		In multiprocessor environment reference time will reset/lost for
+*		all processors, when this function called by any one processor.
+*
+****************************************************************************/
+void XTime_SetTime(XTime Xtime_Global)
+{
+	u32 TimerCntrl;
+	/* Disable the timer to configure */
+	TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
+							SLEEP_TIMER_CNTR_CNTRL_OFFSET);
+	TimerCntrl = TimerCntrl | SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK;
+	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
+				TimerCntrl);
+
+	/* Write the lower 32bit value to timer counter register */
+	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_VAL_OFFSET,
+				Xtime_Global);
+
+	/* Enable the Timer */
+	TimerCntrl = Xil_In32(SLEEP_TIMER_BASEADDR +
+							SLEEP_TIMER_CNTR_CNTRL_OFFSET);
+	TimerCntrl = TimerCntrl & (~SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK);
+	Xil_Out32(SLEEP_TIMER_BASEADDR + SLEEP_TIMER_CNTR_CNTRL_OFFSET,
+				TimerCntrl);
+}
+
+/****************************************************************************
+*
+* Get the time from the Timer Counter Register.
+*
+* @param	Pointer to the location to be updated with the time.
+*
+* @return	None.
+*
+* @note		None.
+*
+****************************************************************************/
+void XTime_GetTime(XTime *Xtime_Global)
+{
+	*Xtime_Global = Xil_In32(SLEEP_TIMER_BASEADDR +
+								SLEEP_TIMER_CNTR_VAL_OFFSET);
+}
+#endif
\ No newline at end of file
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.h
new file mode 100644
index 000000000..36c416d5a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/standalone_v5_4/src/xtime_l.h
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 - 2015 Xilinx, Inc. All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xtime_l.h
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------------
+* 5.00 	pkp	   05/29/14 First release
+* 5.04  pkp	   02/19/16 Added timer configuration register offset definitions
+* 5.04	pkp	   03/11/16 Removed definitions for overflow interrupt register
+*						and mask
+* 

+*
+* @note		None.
+*
+******************************************************************************/
+
+#ifndef XTIME_H /* prevent circular inclusions */
+#define XTIME_H /* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xparameters.h"
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Constant Definitions *****************************/
+
+#ifdef SLEEP_TIMER_BASEADDR
+
+#define COUNTS_PER_SECOND				SLEEP_TIMER_FREQUENCY
+#define COUNTS_PER_USECOND 				COUNTS_PER_SECOND/1000000
+
+/* Timer Register Offset*/
+#define SLEEP_TIMER_CLK_CNTRL_OFFSET 		0x00000000U
+#define SLEEP_TIMER_CNTR_CNTRL_OFFSET		0x0000000CU
+#define SLEEP_TIMER_CNTR_VAL_OFFSET			0x00000018U
+
+/*Timer register values*/
+#define SLEEP_TIMER_COUNTER_CONTROL_DIS_MASK    0x00000001U
+#define SLEEP_TIMER_CLOCK_CONTROL_PS_EN_MASK    0x00000001U
+#define SLEEP_TIMER_COUNTER_CONTROL_RST_MASK    0x00000010U
+#else
+#define ITERS_PER_SEC  (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4)
+#define ITERS_PER_USEC  (XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ / 4000000)
+#define IRQ_FIQ_MASK 	0xC0	/* Mask IRQ and FIQ interrupts in cpsr */
+#endif
+
+/**************************** Type Definitions *******************************/
+
+/* The following definitions are applicable only when TTC3 is present*/
+#ifdef SLEEP_TIMER_BASEADDR
+typedef u32 XTime;
+
+void XTime_SetTime(XTime Xtime_Global);
+void XTime_GetTime(XTime *Xtime_Global);
+#endif
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* XTIME_H */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/Makefile
new file mode 100644
index 000000000..b832910b8
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xsysmonpsu_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling sysmonpsu"
+
+xsysmonpsu_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xsysmonpsu_includes
+
+xsysmonpsu_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c
new file mode 100644
index 000000000..a30a257fb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.c
@@ -0,0 +1,1749 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsysmonpsu.c
+*
+* Functions in this file are the minimum required functions for the XSysMonPsu
+* driver. See xsysmonpsu.h for a detailed description of the driver.
+*
+* @note 	None.
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	    Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.0   kvn    12/15/15 First release.
+*              02/15/16 Corrected Assert function call in
+*                       XSysMonPsu_GetMonitorStatus API.
+*              03/03/16 Added Temperature remote channel for Setsingle
+*                       channel API. Also corrected external mux channel
+*                       numbers.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xsysmonpsu.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void XSysMonPsu_StubHandler(void *CallBackRef);
+
+/************************** Variable Definitions ****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes XSysMonPsu device/instance. This function
+* must be called prior to using the System Monitor device.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	ConfigPtr points to the XSysMonPsu device configuration structure.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. If the address translation is not used then the
+*		physical address is passed.
+*		Unexpected errors may occur if the address mapping is changed
+*		after this function is invoked.
+*
+* @return
+*		- XST_SUCCESS if successful.
+*
+* @note		The user needs to first call the XSysMonPsu_LookupConfig() API
+*		which returns the Configuration structure pointer which is
+*		passed as a parameter to the XSysMonPsu_CfgInitialize() API.
+*
+******************************************************************************/
+s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigPtr,
+			  u32 EffectiveAddr)
+{
+	u32 PsSysmonControlStatus;
+	u32 PlSysmonControlStatus;
+
+	/* Assert the input arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/* Set the values read from the device config and the base address. */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+
+	/* Set all handlers to stub values, let user configure this data later. */
+	InstancePtr->Handler = XSysMonPsu_StubHandler;
+
+	/* Reset the device such that it is in a known state. */
+	XSysMonPsu_Reset(InstancePtr);
+
+	PsSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
+
+	/* Check if the PS Sysmon is in Idle / ready state or not */
+	while(PsSysmonControlStatus != XSYSMONPSU_PS_SYSMON_READY) {
+		PsSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
+	}
+
+	PlSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_PL_SYSMON_CSTS_OFFSET);
+
+	/* Check if the PL Sysmon is accessible to PS Sysmon or not */
+	while((PlSysmonControlStatus & XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK)
+				!= XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK) {
+		PlSysmonControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_PL_SYSMON_CSTS_OFFSET);
+	}
+
+	/* Indicate the instance is now ready to use, initialized without error */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	return XST_SUCCESS;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param	CallBackRef is unused by this function.
+* @param	Event is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XSysMonPsu_StubHandler(void *CallBackRef)
+{
+	(void *) CallBackRef;
+
+	/* Assert occurs always since this is a stub and should never be called */
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets the SystemMonitor
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	None.
+*
+* @note		Upon reset, all Maximum and Minimum status registers will be
+*		reset to their default values. Currently running and any averaging
+*		will restart. Refer to the device data sheet for the device status and
+*		register values after the reset.
+*
+******************************************************************************/
+void XSysMonPsu_Reset(XSysMonPsu *InstancePtr)
+{
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* RESET the PS SYSMON */
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPS_BA_OFFSET +
+			XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK);
+
+	/* RESET the PL SYSMON */
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XPL_BA_OFFSET +
+			XSYSMONPSU_VP_VN_OFFSET, XSYSMONPSU_VP_VN_MASK);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the contents of the Status Register.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	A 32-bit value representing the contents of the Status Register.
+*		Use the XSYSMONPSU_MON_STS_* constants defined in xsysmonpsu_hw.h to
+*		interpret the returned value.
+*
+* @note		None.
+*****************************************************************************/
+u32 XSysMonPsu_GetStatus(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 Status;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the Sysmon Status Register and return the value. */
+	Status = XSysmonPsu_ReadReg(EffectiveBaseAddress + XSYSMONPSU_MON_STS_OFFSET);
+
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function starts the ADC conversion in the Single Channel event driven
+* sampling mode. The EOC bit in Status Register will be set once the conversion
+* is finished. Refer to the device specification for more details.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	None.
+*
+* @note		The default state of the CONVST bit is a logic 0. The conversion
+*		is started when the CONVST bit is set to 1 from 0.
+*		This bit is self-clearing so that the next conversion
+*		can be started by setting this bit.
+*
+*****************************************************************************/
+void XSysMonPsu_StartAdcConversion(XSysMonPsu *InstancePtr)
+{
+	u32 ControlStatus;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Start the conversion by setting the CONVST bit to 1 only if auto-convst
+	 * bit is not enabled. This convst bit is self-clearing.
+	 */
+	ControlStatus = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
+
+	if ((ControlStatus & XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK )
+			!= XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK) {
+		XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_PS_SYSMON_CSTS_OFFSET,
+					(ControlStatus | (u32)XSYSMONPSU_PS_SYSMON_CSTS_CONVST_MASK));
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* Get the ADC converted data for the specified channel.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Channel is the channel number. Use the XSM_CH_* defined in
+*		the file xsysmonpsu.h. The valid channels for PS / PL SysMon are 0 - 6,
+*		8 - 10 and 13 - 37. For AMS, 38 - 53 channels are valid.
+* @param	Block is the value that tells whether it is for PS Sysmon block
+*       or PL Sysmon block or the AMS controller register region.
+*
+* @return	A 16-bit value representing the ADC converted data for the
+*		specified channel. The System Monitor device guarantees
+* 		a 10 bit resolution for the ADC converted data and data is the
+*		10 MSB bits of the 16 data read from the device.
+*
+* @note		Please make sure that the proper channel number is passed.
+*
+*****************************************************************************/
+u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 Block)
+{
+	u16 AdcData;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XSM_CH_SUPPLY3) ||
+			  ((Channel >= XSM_CH_SUPPLY_CALIB) &&
+			  (Channel <= XSM_CH_GAINERR_CALIB)) ||
+			  ((Channel >= XSM_CH_SUPPLY4) &&
+			  (Channel <= XSM_CH_RESERVE1)));
+	Xil_AssertNonvoid((Block == XSYSMON_PS)||(Block == XSYSMON_PL)
+						||(Block == XSYSMON_AMS));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					Block);
+
+	/*
+	 * Read the selected ADC converted data for the specified channel
+	 * and return the value.
+	 */
+	if (Channel <= XSM_CH_AUX_MAX) {
+		AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + ((u32)Channel << 2U)));
+	} else if ((Channel >= XSM_CH_SUPPLY7) && (Channel <= XSM_CH_TEMP_REMTE)){
+		AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + XSM_ADC_CH_OFFSET +
+				(((u32)Channel - XSM_CH_SUPPLY7) << 2U)));
+	} else {
+		AdcData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress + XSM_AMS_CH_OFFSET +
+				(((u32)Channel - XSM_CH_VCC_PSLL0) << 2U)));
+	}
+
+	return AdcData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the calibration coefficient data for the specified
+* parameter.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	CoeffType specifies the calibration coefficient
+*		to be read. Use XSM_CALIB_* constants defined in xsysmonpsu.h to
+*		specify the calibration coefficient to be read.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	A 16-bit value representing the calibration coefficient.
+*		The System Monitor device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of the 16
+*		data read from the device.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XSysMonPsu_GetCalibCoefficient(XSysMonPsu *InstancePtr, u8 CoeffType,
+		u32 SysmonBlk)
+{
+	u16 CalibData;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(CoeffType <= XSM_CALIB_GAIN_ERROR_COEFF);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the selected calibration coefficient. */
+	CalibData = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_CAL_SUP_OFF_OFFSET + ((u32)CoeffType << 2U));
+
+	return CalibData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function reads the Minimum/Maximum measurement for one of the
+* XSM_MIN_* or XSM_MAX_* constants defined in xsysmonpsu.h
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	MeasurementType specifies the parameter for which the
+*		Minimum/Maximum measurement has to be read.
+*		Use XSM_MAX_* and XSM_MIN_* constants defined in xsysmonpsu.h to
+*		specify the data to be read.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	A 16-bit value representing the maximum/minimum measurement for
+*		specified parameter.
+*		The System Monitor device guarantees a 10 bit resolution for
+*		the ADC converted data and data is the 10 MSB bits of  16 bit
+*		data read from the device.
+*
+*****************************************************************************/
+u16 XSysMonPsu_GetMinMaxMeasurement(XSysMonPsu *InstancePtr, u8 MeasurementType,
+		u32 SysmonBlk)
+{
+	u16 MinMaxData;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((MeasurementType <= XSM_MAX_SUPPLY6) ||
+			((MeasurementType >= XSM_MIN_SUPPLY4) &&
+			(MeasurementType <= XSM_MIN_SUPPLY6)) ||
+			((MeasurementType >= XSM_MAX_SUPPLY7) &&
+			(MeasurementType <= XSM_MAX_TEMP_REMOTE)) ||
+			((MeasurementType >= XSM_MIN_SUPPLY7) &&
+			(MeasurementType <= XSM_MIN_TEMP_REMOTE)));
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read and return the specified Minimum/Maximum measurement. */
+	MinMaxData = (u16) (XSysmonPsu_ReadReg(EffectiveBaseAddress +
+							XSM_MIN_MAX_CH_OFFSET + ((u32)MeasurementType << 2U)));
+
+	return MinMaxData;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of samples of averaging that is to be done for
+* all the channels in both the single channel mode and sequence mode of
+* operations.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Average is the number of samples of averaging programmed to the
+*		Configuration Register 0. Use the XSM_AVG_* definitions defined
+*		in xsysmonpsu.h file :
+*		- XSM_AVG_0_SAMPLES for no averaging
+*		- XSM_AVG_16_SAMPLES for 16 samples of averaging
+*		- XSM_AVG_64_SAMPLES for 64 samples of averaging
+*		- XSM_AVG_256_SAMPLES for 256 samples of averaging
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_SetAvg(XSysMonPsu *InstancePtr, u8 Average, u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(Average <= XSM_AVG_256_SAMPLES);
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Write the averaging value into the Configuration Register 0. */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET)
+						& (u32)(~XSYSMONPSU_CFG_REG0_AVRGNG_MASK);
+	RegValue |= (((u32) Average << XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT));
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
+			 RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the number of samples of averaging configured for all
+* the channels in the Configuration Register 0.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	The averaging read from the Configuration Register 0 is
+*		returned. Use the XSM_AVG_* bit definitions defined in xsysmonpsu.h
+*		file to interpret the returned value :
+*		- XSM_AVG_0_SAMPLES means no averaging
+*		- XSM_AVG_16_SAMPLES means 16 samples of averaging
+*		- XSM_AVG_64_SAMPLES means 64 samples of averaging
+*		- XSM_AVG_256_SAMPLES means 256 samples of averaging
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XSysMonPsu_GetAvg(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 Average;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the averaging value from the Configuration Register 0. */
+	Average = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+				XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
+
+	return (u8)(Average >> XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the given parameters in the Configuration Register 0 in
+* the single channel mode.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Channel is the channel number for conversion. The valid
+*		channels are 0 - 6, 8 - 10, 13 - 37.
+* @param	IncreaseAcqCycles is a boolean parameter which specifies whether
+*		the Acquisition time for the external channels has to be
+*		increased to 10 ADCCLK cycles (specify TRUE) or remain at the
+*		default 4 ADCCLK cycles (specify FALSE). This parameter is
+*		only valid for the external channels.
+* @param	IsEventMode is a boolean parameter that specifies continuous
+*		sampling (specify FALSE) or event driven sampling mode (specify
+*		TRUE) for the given channel.
+* @param	IsDifferentialMode is a boolean parameter which specifies
+*		unipolar(specify FALSE) or differential mode (specify TRUE) for
+*		the analog inputs. The 	input mode is only valid for the
+*		external channels.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Configuration Register 0.
+*		- XST_FAILURE if the channel sequencer is enabled or the input
+*		parameters are not valid for the selected channel.
+*
+* @note
+*		- The number of samples for the averaging for all the channels
+*		is set by using the function XSysMonPsu_SetAvg.
+*		- The calibration of the device is done by doing a ADC
+*		conversion on the calibration channel(channel 8). The input
+*		parameters IncreaseAcqCycles, IsDifferentialMode and
+*		IsEventMode are not valid for this channel.
+*
+*****************************************************************************/
+s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
+				u32 IncreaseAcqCycles, u32 IsEventMode,
+				u32 IsDifferentialMode, u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+	s32 Status;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Channel <= XSM_CH_SUPPLY3) ||
+			  ((Channel >= XSM_CH_SUPPLY_CALIB) &&
+			  (Channel <= XSM_CH_GAINERR_CALIB)) ||
+			  ((Channel >= XSM_CH_SUPPLY4) &&
+			  (Channel <= XSM_CH_TEMP_REMTE)));
+	Xil_AssertNonvoid((IncreaseAcqCycles == TRUE) ||
+			  (IncreaseAcqCycles == FALSE));
+	Xil_AssertNonvoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+	Xil_AssertNonvoid((IsDifferentialMode == TRUE) ||
+			  (IsDifferentialMode == FALSE));
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Check if the device is in single channel mode else return failure */
+	if ((XSysMonPsu_GetSequencerMode(InstancePtr, SysmonBlk)
+				!= XSM_SEQ_MODE_SINGCHAN)) {
+		Status = (s32)XST_FAILURE;
+		goto End;
+	}
+
+	/* Read the Configuration Register 0 and extract out Averaging value. */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_CFG_REG0_OFFSET) & XSYSMONPSU_CFG_REG0_AVRGNG_MASK;
+
+	/*
+	 * Select the number of acquisition cycles. The acquisition cycles is
+	 * only valid for the external channels.
+	 */
+	if (IncreaseAcqCycles == TRUE) {
+		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
+		    || (Channel == XSM_CH_VPVN)) {
+			RegValue |= XSYSMONPSU_CFG_REG0_ACQ_MASK;
+		} else {
+			Status = (s32)XST_FAILURE;
+			goto End;
+		}
+	}
+
+	/*
+	 * Select the input mode. The input mode is only valid for the
+	 * external channels.
+	 */
+	if (IsDifferentialMode == TRUE) {
+
+		if (((Channel >= XSM_CH_AUX_MIN) && (Channel <= XSM_CH_AUX_MAX))
+		    || (Channel == XSM_CH_VPVN)) {
+			RegValue |= XSYSMONPSU_CFG_REG0_BU_MASK;
+		} else {
+			Status = (s32)XST_FAILURE;
+			goto End;
+		}
+	}
+
+	/* Select the ADC mode. */
+	if (IsEventMode == TRUE) {
+		RegValue |= XSYSMONPSU_CFG_REG0_EC_MASK;
+	}
+
+	/* Write the given values into the Configuration Register 0. */
+	RegValue |= ((u32)Channel & XSYSMONPSU_CFG_REG0_MUX_CH_MASK);
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
+			 RegValue);
+
+	Status = (s32)XST_SUCCESS;
+
+End:
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the alarm outputs for the specified alarms in the
+* Configuration Registers 1:
+*
+*		- OT for Over Temperature (XSYSMONPSU_CFR_REG1_ALRM_OT_MASK)
+*		- ALM0 for On board Temperature (XSYSMONPSU_CFR_REG1_ALRM_TEMP_MASK)
+*		- ALM1 for SUPPLY1 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY1_MASK)
+*		- ALM2 for SUPPLY2 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY2_MASK)
+* 		- ALM3 for SUPPLY3 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY3_MASK)
+* 		- ALM4 for SUPPLY4 (XSYSMONPSU_CFR_REG1_ALRM__SUPPLY4_MASK)
+*		- ALM5 for SUPPLY5 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY5_MASK)
+* 		- ALM6 for SUPPLY6 (XSYSMONPSU_CFR_REG1_ALRM_SUPPLY6_MASK)
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	AlmEnableMask is the bit-mask of the alarm outputs to be enabled
+*		in the Configuration Register 1.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will be
+*		disabled. This mask is formed by OR'ing XSYSMONPSU_CFR_REG1_ALRM_*_MASK
+*		masks defined in xsysmonpsu.h.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that the alarms for bit positions of 0 will
+*		be enabled and alarms for bit positions of 1 will be disabled.
+*		The alarm outputs specified by the AlmEnableMask are negated
+*		before writing to the Configuration Register 1 because it
+*		was Disable register bits.
+*
+*****************************************************************************/
+void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
+		u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(AlmEnableMask <= XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG1_OFFSET);
+	RegValue &= (u32)(~XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+	RegValue |= (~AlmEnableMask & (u32)XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+
+	/*
+	 * Enable/disables the alarm enables for the specified alarm bits in the
+	 * Configuration Register 1.
+	 */
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG1_OFFSET,
+			 RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of the alarm output enables in the
+* Configuration Register 1.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	This is the bit-mask of the enabled alarm outputs in the
+*		Configuration Register 1. Use the masks XSYSMONPSU_CFG_REG1_ALRM_*_MASK
+*		masks defined in xsysmonpsu.h to interpret the returned value.
+*
+*		Bit positions of 1 indicate that the alarm output is enabled.
+*		Bit positions of 0 indicate that the alarm output is disabled.
+*
+*
+* @note		The implementation of the alarm enables in the Configuration
+*		register 1 is such that alarms for the bit positions of 1 will
+*		be disabled and alarms for bit positions of 0 will be enabled.
+*		The enabled alarm outputs returned by this function is the
+*		negated value of the the data read from the Configuration
+*		Register 1.
+*
+*****************************************************************************/
+u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the status of alarm output enables from the Configuration
+	 * Register 1.
+	 */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_CFG_REG1_OFFSET) & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK;
+	RegValue = (~RegValue & XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK);
+
+	return RegValue;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the specified Channel Sequencer Mode in the Configuration
+* Register 1 :
+*		- Default safe mode (XSM_SEQ_MODE_SAFE)
+*		- One pass through sequence (XSM_SEQ_MODE_ONEPASS)
+*		- Continuous channel sequencing (XSM_SEQ_MODE_CONTINPASS)
+*		- Single Channel/Sequencer off (XSM_SEQ_MODE_SINGCHAN)
+*		- Olympus sampling mode (XSM_SEQ_MODE_OYLMPUS)
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SequencerMode is the sequencer mode to be set.
+*		Use XSM_SEQ_MODE_* bits defined in xsysmonpsu.h.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		Only one of the modes can be enabled at a time.
+*
+*****************************************************************************/
+void XSysMonPsu_SetSequencerMode(XSysMonPsu *InstancePtr, u8 SequencerMode,
+		u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((SequencerMode <= XSM_SEQ_MODE_SINGCHAN) ||
+			(SequencerMode == XSM_SEQ_MODE_OYLMPUS));
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Set the specified sequencer mode in the Configuration Register 1. */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG1_OFFSET);
+	RegValue &= (u32)(~ XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK);
+	RegValue |= (((u32)SequencerMode  << XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT) &
+					XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK);
+	XSysmonPsu_WriteReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG1_OFFSET, RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel sequencer mode from the Configuration
+* Register 1.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	The channel sequencer mode :
+*		- XSM_SEQ_MODE_SAFE : Default safe mode
+*		- XSM_SEQ_MODE_ONEPASS : One pass through sequence
+*		- XSM_SEQ_MODE_CONTINPASS : Continuous channel sequencing
+*		- XSM_SEQ_MODE_SINGCHAN : Single channel/Sequencer off
+*		- XSM_SEQ_MODE_OLYMPUS : Olympus sampling mode
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XSysMonPsu_GetSequencerMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u8 SequencerMode;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the channel sequencer mode from the Configuration Register 1. */
+	SequencerMode =  ((u8) ((XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_CFG_REG1_OFFSET) & XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK) >>
+			XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT));
+
+	return SequencerMode;
+}
+
+/****************************************************************************/
+/**
+*
+* The function enables the Event mode or Continuous mode in the sequencer mode.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	IsEventMode is a boolean parameter that specifies continuous
+*		sampling (specify FALSE) or event driven sampling mode (specify
+*		TRUE) for the channel.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_SetSequencerEvent(XSysMonPsu *InstancePtr, u32 IsEventMode,
+		u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((IsEventMode == TRUE) || (IsEventMode == FALSE));
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the Configuration Register 0. */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG0_OFFSET);
+
+	/* Set the ADC mode. */
+	if (IsEventMode == TRUE) {
+		RegValue |= XSYSMONPSU_CFG_REG0_EC_MASK;
+	} else {
+		RegValue &= (u32)(~XSYSMONPSU_CFG_REG0_EC_MASK);
+	}
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
+			 RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* The function returns the mode of the sequencer.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	Returns the Sequencer mode. XSYSMONPSU_EVENT_MODE for Event mode
+* 		and XSYSMONPSU_CONTINUOUS_MODE for continuous mode.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XSysMonPsu_GetSequencerEvent(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	s32 Mode;
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the Configuration Register 0. */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG0_OFFSET);
+
+	RegValue &= XSYSMONPSU_CFG_REG0_EC_MASK;
+
+	if (RegValue == XSYSMONPSU_CFG_REG0_EC_MASK) {
+		Mode = XSYSMONPSU_EVENT_MODE;
+	} else {
+		Mode = XSYSMONPSU_CONTINUOUS_MODE;
+	}
+
+	return Mode;
+}
+
+/****************************************************************************/
+/**
+*
+* The function enables the external mux and connects a channel to the mux.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Channel is the channel number used to connect to the external
+*		Mux. The valid channels are 0 to 5 and 16 to 31.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Configuration Register 0.
+*		- XST_FAILURE if the channel sequencer is enabled or the input
+*		parameters are not valid for the selected channel.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Channel <= XSM_CH_VREFN) ||
+			  ((Channel >= XSM_CH_AUX_MIN) &&
+			  (Channel <= XSM_CH_AUX_MAX)));
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the Configuration Register 0 and the clear the channel selection
+	 * bits.
+	 */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG0_OFFSET);
+	RegValue &= ~(XSYSMONPSU_CFG_REG0_MUX_CH_MASK);
+
+	/* Enable the External Mux and select the channel. */
+	RegValue |= (XSYSMONPSU_CFG_REG0_XTRNL_MUX_MASK | (u32)Channel);
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG0_OFFSET,
+			 RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* The function returns the external mux channel.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	Returns the channel number used to connect to the external
+*		Mux. The valid channels are 0 to 6, 8 to 16, and 31 to 36..
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the Configuration Register 0 and derive the channel selection
+	 * bits.
+	 */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG0_OFFSET);
+	RegValue &= XSYSMONPSU_CFG_REG0_MUX_CH_MASK;
+
+	return RegValue;
+}
+
+/****************************************************************************/
+/**
+*
+* The function sets the frequency of the ADCCLK by configuring the DCLK to
+* ADCCLK ratio in the Configuration Register #2.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Divisor is clock divisor used to derive ADCCLK from DCLK.
+*		Valid values of the divisor are
+*		PS:
+*		 - 0 means divide by 8.
+*		 - 1,2 means divide by 2.
+*		 - 3 to 255 means divide by that value.
+*       PL:
+*		 - 0,1,2 means divide by 2.
+*		 - 3 to 255 means divide by that value.
+*		Refer to the device specification for more details.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		- The ADCCLK is an internal clock used by the ADC and is
+*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		divided by the user selection in the Configuration Register 2.
+*		- There is no Assert on the minimum value of the Divisor.
+*
+*****************************************************************************/
+void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor,
+            u32 SysmonBlk)
+{
+	u32 RegValue;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the Configuration Register 2 and the clear the clock divisor
+	 * bits.
+	 */
+	RegValue = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_CFG_REG2_OFFSET);
+	RegValue &= ~(XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK);
+
+	/* Write the divisor value into the Configuration Register 2. */
+	RegValue |= ((u32)Divisor << XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT) &
+					XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK;
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_CFG_REG2_OFFSET,
+			 RegValue);
+
+}
+
+/****************************************************************************/
+/**
+*
+* The function gets the ADCCLK divisor from the Configuration Register 2.
+*
+* @param	InstancePtr is a pointer to the XSysMon instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	The divisor read from the Configuration Register 2.
+*
+* @note		The ADCCLK is an internal clock used by the ADC and is
+*		synchronized to the DCLK clock. The ADCCLK is equal to DCLK
+*		divided by the user selection in the Configuration Register 2.
+*
+*****************************************************************************/
+u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u16 Divisor;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Read the divisor value from the Configuration Register 2. */
+	Divisor = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
+							XSYSMONPSU_CFG_REG2_OFFSET);
+
+	return (u8) (Divisor >> XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT);
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified channels in the ADC Channel Selection
+* Sequencer Registers. The sequencer must be in the Safe Mode before writing
+* to these registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	ChEnableMask is the bit mask of all the channels to be enabled.
+*		Use XSYSMONPSU_SEQ_CH* defined in xsysmon_hw.h to specify the Channel
+*		numbers. Bit masks of 1 will be enabled and bit mask of 0 will
+*		be disabled.
+*		The ChEnableMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Selection Sequencer Registers.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Selection Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
+		u32 SysmonBlk)
+{
+	s32 Status;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/*
+	 * The sequencer must be in the Default Safe Mode before writing
+	 * to these registers. Return XST_FAILURE if the channel sequencer
+	 * is enabled.
+	 */
+	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk) != XSM_SEQ_MODE_SAFE)) {
+		Status = (s32)XST_FAILURE;
+		goto End;
+	}
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Enable the specified channels in the ADC Channel Selection Sequencer
+	 * Registers.
+	 */
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH0_OFFSET,
+			 (ChEnableMask & XSYSMONPSU_SEQ_CH0_VALID_MASK));
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_CH1_OFFSET,
+			 (ChEnableMask >> XSM_SEQ_CH_SHIFT) &
+			 XSYSMONPSU_SEQ_CH1_VALID_MASK);
+
+	Status = (s32)XST_SUCCESS;
+
+End:
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the channel enable bits status from the ADC Channel
+* Selection Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	Gets the channel enable bits. Use XSYSMONPSU_SEQ_CH* defined in
+*		xsysmonpsu_hw.h to interpret the Channel numbers. Bit masks of 1
+*		are the channels that are enabled and bit mask of 0 are
+*		the channels that are disabled.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 RegVal;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the channel enable bits for all the channels from the ADC
+	 * Channel Selection Register.
+	 */
+	RegVal = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_CH0_OFFSET) & XSYSMONPSU_SEQ_CH0_VALID_MASK;
+	RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_CH1_OFFSET) & XSYSMONPSU_SEQ_CH1_VALID_MASK) <<
+					XSM_SEQ_CH_SHIFT;
+
+	return RegVal;
+}
+
+/****************************************************************************/
+/**
+*
+* This function enables the averaging for the specified channels in the ADC
+* Channel Averaging Enable Sequencer Registers. The sequencer must be in
+* the Safe Mode before writing to these registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	AvgEnableChMask is the bit mask of all the channels for which
+*		averaging is to be enabled. Use XSYSMONPSU_SEQ_AVERAGE* defined in
+*		xsysmonpsu_hw.h to specify the Channel numbers. Averaging will be
+*		enabled for bit masks of 1 and disabled for bit mask of 0.
+*		The AvgEnableChMask is a 32 bit mask that is written to the
+*		two 16 bit ADC Channel Averaging Enable Sequencer Registers.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Averaging Enables Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
+		u32 SysmonBlk)
+{
+	s32 Status;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * The sequencer must be disabled for writing any of these registers.
+	 * Return XST_FAILURE if the channel sequencer is enabled.
+	 */
+	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
+	                                     != XSM_SEQ_MODE_SAFE)) {
+		Status = (s32)XST_FAILURE;
+		goto End;
+	}
+
+	/*
+	 * Enable/disable the averaging for the specified channels in the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	XSysmonPsu_WriteReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_AVERAGE0_OFFSET,
+			(AvgEnableChMask & XSYSMONPSU_SEQ_AVERAGE0_MASK));
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_AVERAGE1_OFFSET,
+			 (AvgEnableChMask >> XSM_SEQ_CH_SHIFT) &
+			 XSYSMONPSU_SEQ_AVERAGE1_MASK);
+
+	Status = (s32)XST_SUCCESS;
+End:
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the channels for which the averaging has been enabled
+* in the ADC Channel Averaging Enables Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @returns 	The status of averaging (enabled/disabled) for all the channels.
+*		Use XSYSMONPSU_SEQ_AVERAGE* defined in xsysmonpsu_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		averaging is enabled and bit mask of 0 are the channels for
+*		averaging is disabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 RegVal;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the averaging enable status for all the channels from the
+	 * ADC Channel Averaging Enables Sequencer Registers.
+	 */
+	RegVal = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_AVERAGE0_OFFSET) & XSYSMONPSU_SEQ_AVERAGE0_MASK;
+	RegVal |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_AVERAGE1_OFFSET) & XSYSMONPSU_SEQ_AVERAGE1_MASK) <<
+			XSM_SEQ_CH_SHIFT;
+
+	return RegVal;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Analog input mode for the specified channels in the
+* ADC Channel Analog-Input Mode Sequencer Registers. The sequencer must be in
+* the Safe Mode before writing to these registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	InputModeChMask is the bit mask of all the channels for which
+*		the input mode is differential mode. Use XSYSMONPSU_SEQ_INPUT_MDE*
+*		defined in xsysmonpsu_hw.h to specify the channel numbers. Differential
+*		or  Bipolar input mode will be set for bit masks of 1 and unipolar input
+*		mode for bit masks of 0.
+*		The InputModeChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Analog-Input Mode Sequencer Registers.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the ADC Channel Analog-Input Mode Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
+		u32 SysmonBlk)
+{
+	s32 Status;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/*
+	 * The sequencer must be in the Safe Mode before writing to
+	 * these registers. Return XST_FAILURE if the channel sequencer
+	 * is enabled.
+	 */
+	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
+	                                      != XSM_SEQ_MODE_SAFE)) {
+		Status = (s32)XST_FAILURE;
+		goto End;
+	}
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Set the input mode for the specified channels in the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	XSysmonPsu_WriteReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET,
+			 (InputModeChMask & XSYSMONPSU_SEQ_INPUT_MDE0_MASK));
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET,
+			 (InputModeChMask >> XSM_SEQ_CH_SHIFT) &
+			 XSYSMONPSU_SEQ_INPUT_MDE1_MASK);
+
+	Status = (s32)XST_SUCCESS;
+
+End:
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Analog input mode for all the channels from
+* the ADC Channel Analog-Input Mode Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @returns 	The input mode for all the channels.
+*		Use XSYSMONPSU_SEQ_INPUT_MDE* defined in xsysmonpsu_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		input mode is differential/Bipolar and bit mask of 0 are the channels
+*		for which input mode is unipolar.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 InputMode;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 *  Get the input mode for all the channels from the ADC Channel
+	 * Analog-Input Mode Sequencer Registers.
+	 */
+	InputMode = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET) & XSYSMONPSU_SEQ_INPUT_MDE0_MASK;
+	InputMode |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET) & XSYSMONPSU_SEQ_INPUT_MDE1_MASK) <<
+				XSM_SEQ_CH_SHIFT;
+
+	return InputMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the number of Acquisition cycles in the ADC Channel
+* Acquisition Time Sequencer Registers. The sequencer must be in the Safe Mode
+* before writing to these registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	AcqCyclesChMask is the bit mask of all the channels for which
+*		the number of acquisition cycles is to be extended.
+*		Use XSYSMONPSU_SEQ_ACQ* defined in xsysmonpsu_hw.h to specify the Channel
+*		numbers. Acquisition cycles will be extended to 10 ADCCLK cycles
+*		for bit masks of 1 and will be the default 4 ADCCLK cycles for
+*		bit masks of 0.
+*		The AcqCyclesChMask is a 32 bit mask that is written to the two
+*		16 bit ADC Channel Acquisition Time Sequencer Registers.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return
+*		- XST_SUCCESS if the given values were written successfully to
+*		the Channel Sequencer Registers.
+*		- XST_FAILURE if the channel sequencer is enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
+		u32 SysmonBlk)
+{
+	s32 Status;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/*
+	 * The sequencer must be in the Safe Mode before writing
+	 * to these registers. Return XST_FAILURE if the channel
+	 * sequencer is enabled.
+	 */
+	if ((XSysMonPsu_GetSequencerMode(InstancePtr,SysmonBlk)
+	                                     != XSM_SEQ_MODE_SAFE)) {
+		Status = (s32)XST_FAILURE;
+		goto End;
+	}
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Set the Acquisition time for the specified channels in the
+	 * ADC Channel Acquisition Time Sequencer Registers.
+	 */
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ0_OFFSET,
+			 (AcqCyclesChMask & XSYSMONPSU_SEQ_ACQ0_MASK));
+
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_SEQ_ACQ1_OFFSET,
+			 (AcqCyclesChMask >> XSM_SEQ_CH_SHIFT) & XSYSMONPSU_SEQ_ACQ1_MASK);
+
+	Status = (s32)XST_SUCCESS;
+
+End:
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the status of acquisition time from the ADC Channel Acquisition
+* Time Sequencer Registers.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @returns 	The acquisition time for all the channels.
+*		Use XSYSMONPSU_SEQ_ACQ* defined in xsysmonpsu_hw.h to interpret the
+*		Channel numbers. Bit masks of 1 are the channels for which
+*		acquisition cycles are extended and bit mask of 0 are the
+*		channels for which acquisition cycles are not extended.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk)
+{
+	u32 RegValAcq;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Get the Acquisition cycles for the specified channels from the ADC
+	 * Channel Acquisition Time Sequencer Registers.
+	 */
+	RegValAcq = XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_SEQ_ACQ0_OFFSET) & XSYSMONPSU_SEQ_ACQ0_MASK;
+	RegValAcq |= (XSysmonPsu_ReadReg(EffectiveBaseAddress +
+					XSYSMONPSU_SEQ_ACQ1_OFFSET) & XSYSMONPSU_SEQ_ACQ1_MASK) <<
+					XSM_SEQ_CH_SHIFT;
+
+	return RegValAcq;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the contents of the given Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register to
+*		be set. Use XSM_ATR_* constants defined in xsysmonpsu.h to
+*		specify the index.
+* @param	Value is the 16-bit threshold value to write into the register.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_SetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
+		u16 Value, u32 SysmonBlk)
+{
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((AlarmThrReg <= XSM_ATR_TEMP_RMTE_UPPER) ||
+			((AlarmThrReg >= XSM_ATR_SUP7_LOWER) &&
+			(AlarmThrReg <= XSM_ATR_TEMP_RMTE_LOWER)));
+	Xil_AssertVoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/* Write the value into the specified Alarm Threshold Register. */
+	XSysmonPsu_WriteReg(EffectiveBaseAddress + XSYSMONPSU_ALRM_TEMP_UPR_OFFSET +
+			((u32)AlarmThrReg << 2U), Value);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the contents of the specified Alarm Threshold Register.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	AlarmThrReg is the index of an Alarm Threshold Register
+*		to be read. Use XSM_ATR_* constants defined in xsysmonpsu.h
+*		to specify the index.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon
+*       block or PL Sysmon block register region.
+*
+* @return	A 16-bit value representing the contents of the selected Alarm
+*		Threshold Register.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XSysMonPsu_GetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
+		u32 SysmonBlk)
+{
+	u16 AlarmThreshold;
+	u32 EffectiveBaseAddress;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((AlarmThrReg <= XSM_ATR_TEMP_RMTE_UPPER) ||
+			((AlarmThrReg >= XSM_ATR_SUP7_LOWER) &&
+			(AlarmThrReg <= XSM_ATR_TEMP_RMTE_LOWER)));
+	Xil_AssertNonvoid((SysmonBlk == XSYSMON_PS)||(SysmonBlk == XSYSMON_PL));
+
+	/* Calculate the effective baseaddress based on the Sysmon instance. */
+	EffectiveBaseAddress =
+			XSysMonPsu_GetEffBaseAddress(InstancePtr->Config.BaseAddress,
+					SysmonBlk);
+
+	/*
+	 * Read the specified Alarm Threshold Register and return
+	 * the value.
+	 */
+	AlarmThreshold = (u16) XSysmonPsu_ReadReg(EffectiveBaseAddress +
+			XSYSMONPSU_ALRM_TEMP_UPR_OFFSET + ((u32)AlarmThrReg << 2));
+
+	return AlarmThreshold;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the conversion to be automatic for PS SysMon.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	None
+*
+* @note		In the auto-trigger mode, sample rate is of 1 Million samples.
+*
+*****************************************************************************/
+void XSysMonPsu_SetPSAutoConversion(XSysMonPsu *InstancePtr)
+{
+	u32 PSSysMonStatusReg;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Set the automatic conversion triggering in PS control register. */
+	PSSysMonStatusReg = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET);
+	PSSysMonStatusReg |= XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK;
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_PS_SYSMON_CSTS_OFFSET, PSSysMonStatusReg);
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the AMS monitor status.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	Returns the monitor status. See XSYSMONPSU_MON_STS_*_MASK
+* 		definations present in xsysmonpsu_hw.h for knowing the status.
+*
+* @note		None
+* .
+*****************************************************************************/
+u32 XSysMonPsu_GetMonitorStatus(XSysMonPsu *InstancePtr)
+{
+	u32 AMSMonStatusReg;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the AMS monitor status. This gives tells about JTAG Locked / ADC
+	 * busy / ADC Current Channel number and its ADC output.
+	 */
+	AMSMonStatusReg = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+			XSYSMONPSU_MON_STS_OFFSET);
+
+	return AMSMonStatusReg;
+}
+
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h
new file mode 100644
index 000000000..ae55db9ce
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu.h
@@ -0,0 +1,592 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+* @file xsysmonpsu.h
+*
+* The XSysMon driver supports the Xilinx System Monitor device.
+*
+* The System Monitor device has the following features:
+*	- PL Sysmon instance has 10-bit, 200-KSPS (kilo samples per second)
+*		Analog-to-Digital Converter (ADC)
+*	- PS Sysmon instance has 10-bit, 1000-KSPS ADC.
+*	- Monitoring of on-chip supply voltages and temperature
+*	- 1 dedicated differential analog-input pair and
+*	  16 auxiliary differential analog-input pairs
+*	- Automatic alarms based on user defined limits for the on-chip
+*	  supply voltages and temperature
+*	- Automatic Channel Sequencer, programmable averaging, programmable
+*	  acquisition time for the external inputs, unipolar or differential
+*	  input selection for the external inputs
+*	- Inbuilt Calibration
+*	- Optional interrupt request generation
+*	- External Mux
+*
+*
+* The user should refer to the hardware device specification for detailed
+* information about the device.
+*
+* This header file contains the prototypes of driver functions that can
+* be used to access the System Monitor device.
+*
+*
+*  System Monitor Channel Sequencer Modes 
+*
+* The  System Monitor Channel Sequencer supports the following operating modes:
+*
+*   -  Default : This is the default mode after power up.
+*		In this mode of operation the System Monitor operates in
+*		a sequence mode, monitoring the on chip sensors:
+*		Temperature, VCCINT, and VCCAUX.
+*   -  One pass through sequence : In this mode the System Monitor
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers for a single pass and then stops.
+*   -  Continuous cycling of sequence : In this mode the System Monitor
+*		converts the channels enabled in the Sequencer Channel Enable
+*		registers continuously.
+*   -  Single channel mode: In this mode the System Monitor Channel
+*		Sequencer is disabled and the System Monitor operates in a
+*		Single Channel Mode.
+*		The System Monitor can operate either in a Continuous or Event
+*		driven sampling mode in the single channel mode.
+*
+*
+*  Initialization and Configuration 
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the System Monitor device.
+*
+* XSysMonPsu_CfgInitialize() API is used to initialize the System Monitor
+* device. The user needs to first call the XSysMonPsu_LookupConfig() API which
+* returns the Configuration structure pointer which is passed as a parameter to
+* the XSysMonPsu_CfgInitialize() API.
+*
+*
+* Interrupts
+*
+* The System Monitor device supports interrupt driven mode and the default
+* operation mode is polling mode.
+*
+* This driver does not provide a Interrupt Service Routine (ISR) for the device.
+* It is the responsibility of the application to provide one if needed. Refer to
+* the interrupt example provided with this driver for details on using the
+* device in interrupt mode.
+*
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*
+*  Building the driver 
+*
+* The XSysMonPsu driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+*
+*  Limitations of the driver 
+*
+* System Monitor device can be accessed through the JTAG port and the AXI
+* interface. The driver implementation does not support the simultaneous access
+* of the device by both these interfaces. The user has to take care of this
+* situation in the user application code.
+*
+*
+*
+* 


+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.00  kvn    12/15/15 First release
+*              02/15/16 Corrected Assert function call in
+*                       XSysMonPsu_GetMonitorStatus API.
+*              03/03/16 Added Temperature remote channel for Setsingle
+*                       channel API. Also corrected external mux channel
+*                       numbers.
+*
+* 

+*
+******************************************************************************/
+
+
+#ifndef XSYSMONPSU_H_			/* prevent circular inclusions */
+#define XSYSMONPSU_H_			/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xsysmonpsu_hw.h"
+#include "xil_types.h"
+
+/************************** Constant Definitions *****************************/
+
+/**
+ * @name Indexes for the different channels.
+ * @{
+ */
+#define XSM_CH_TEMP 		0x0U  /**< On Chip Temperature */
+#define XSM_CH_SUPPLY1		0x1U  /**< SUPPLY1 VCC_PSINTLP */
+#define XSM_CH_SUPPLY2		0x2U  /**< SUPPLY2 VCC_PSINTFP */
+#define XSM_CH_VPVN 		0x3U  /**< VP/VN Dedicated analog inputs */
+#define XSM_CH_VREFP		0x4U  /**< VREFP */
+#define XSM_CH_VREFN		0x5U  /**< VREFN */
+#define XSM_CH_SUPPLY3		0x6U  /**< SUPPLY3 VCC_PSAUX */
+#define XSM_CH_SUPPLY_CALIB	0x08U /**< Supply Calib Data Reg */
+#define XSM_CH_ADC_CALIB	0x09U /**< ADC Offset Channel Reg */
+#define XSM_CH_GAINERR_CALIB 	0x0AU /**< Gain Error Channel Reg  */
+#define XSM_CH_SUPPLY4		0x0DU /**< SUPPLY4 VCC_PSDDR_504 */
+#define XSM_CH_SUPPLY5		0x0EU /**< SUPPLY5 VCC_PSIO3_503 */
+#define XSM_CH_SUPPLY6		0x0FU /**< SUPPLY6 VCC_PSIO0_500 */
+#define XSM_CH_AUX_MIN		16U   /**< Channel number for 1st Aux Channel */
+#define XSM_CH_AUX_MAX		31U   /**< Channel number for Last Aux channel */
+#define XSM_CH_SUPPLY7      32U   /**< SUPPLY7 VCC_PSIO1_501 */
+#define XSM_CH_SUPPLY8      33U   /**< SUPPLY8 VCC_PSIO2_502 */
+#define XSM_CH_SUPPLY9      34U   /**< SUPPLY9 PS_MGTRAVCC */
+#define XSM_CH_SUPPLY10     35U   /**< SUPPLY10 PS_MGTRAVTT */
+#define XSM_CH_VCCAMS       36U   /**< VCCAMS */
+#define XSM_CH_TEMP_REMTE   37U   /**< Temperature Remote */
+#define XSM_CH_VCC_PSLL0    38U   /**< VCC_PSLL0 */
+#define XSM_CH_VCC_PSLL1    39U   /**< VCC_PSLL1 */
+#define XSM_CH_VCC_PSLL2    40U   /**< VCC_PSLL2 */
+#define XSM_CH_VCC_PSLL3    41U   /**< VCC_PSLL3 */
+#define XSM_CH_VCC_PSLL4    42U   /**< VCC_PSLL4 */
+#define XSM_CH_VCC_PSBATT   43U   /**< VCC_PSBATT */
+#define XSM_CH_VCCINT       44U   /**< VCCINT */
+#define XSM_CH_VCCBRAM      45U   /**< VCCBRAM */
+#define XSM_CH_VCCAUX       46U   /**< VCCAUX */
+#define XSM_CH_VCC_PSDDRPLL 47U   /**< VCC_PSDDRPLL */
+#define XSM_CH_DDRPHY_VREF  48U   /**< DDRPHY_VREF */
+#define XSM_CH_DDRPHY_AT0   49U   /**< DDRPHY_AT0 */
+#define XSM_CH_PSGT_AT0     50U   /**< PSGT_AT0 */
+#define XSM_CH_PSGT_AT1     51U   /**< PSGT_AT0 */
+#define XSM_CH_RESERVE0     52U   /**< PSGT_AT0 */
+#define XSM_CH_RESERVE1     53U   /**< PSGT_AT0 */
+
+/*@}*/
+
+/**
+ * @name Indexes for reading the Calibration Coefficient Data.
+ * @{
+ */
+#define XSM_CALIB_SUPPLY_OFFSET_COEFF 0U /**< Supply Offset Calib Coefficient */
+#define XSM_CALIB_ADC_OFFSET_COEFF    1U /**< ADC Offset Calib Coefficient */
+#define XSM_CALIB_GAIN_ERROR_COEFF    2U /**< Gain Error Calib Coefficient*/
+
+/*@}*/
+
+/**
+ * @name Indexes for reading the Minimum/Maximum Measurement Data.
+ * @{
+ */
+#define XSM_MAX_TEMP		0U    /**< Maximum Temperature Data */
+#define XSM_MAX_SUPPLY1		1U    /**< Maximum SUPPLY1 Data */
+#define XSM_MAX_SUPPLY2		2U    /**< Maximum SUPPLY2 Data */
+#define XSM_MAX_SUPPLY3		3U    /**< Maximum SUPPLY3 Data */
+#define XSM_MIN_TEMP		4U    /**< Minimum Temperature Data */
+#define XSM_MIN_SUPPLY1		5U    /**< Minimum SUPPLY1 Data */
+#define XSM_MIN_SUPPLY2     6U    /**< Minimum SUPPLY2 Data */
+#define XSM_MIN_SUPPLY3     7U    /**< Minimum SUPPLY3 Data */
+#define XSM_MAX_SUPPLY4		8U    /**< Maximum SUPPLY4 Data */
+#define XSM_MAX_SUPPLY5		9U    /**< Maximum SUPPLY5 Data */
+#define XSM_MAX_SUPPLY6		0xAU  /**< Maximum SUPPLY6 Data */
+#define XSM_MIN_SUPPLY4     0xCU  /**< Minimum SUPPLY4 Data */
+#define XSM_MIN_SUPPLY5     0xDU  /**< Minimum SUPPLY5 Data */
+#define XSM_MIN_SUPPLY6     0xEU  /**< Minimum SUPPLY6 Data */
+#define XSM_MAX_SUPPLY7		0x80U  /**< Maximum SUPPLY7 Data */
+#define XSM_MAX_SUPPLY8		0x81U  /**< Maximum SUPPLY8 Data */
+#define XSM_MAX_SUPPLY9		0x82U  /**< Maximum SUPPLY9 Data */
+#define XSM_MAX_SUPPLY10	0x83U  /**< Maximum SUPPLY10 Data */
+#define XSM_MAX_VCCAMS  	0x84U  /**< Maximum VCCAMS Data */
+#define XSM_MAX_TEMP_REMOTE  	0x85U  /**< Maximum Remote Temperature Data */
+#define XSM_MIN_SUPPLY7     0x88U  /**< Minimum SUPPLY7 Data */
+#define XSM_MIN_SUPPLY8     0x89U  /**< Minimum SUPPLY8 Data */
+#define XSM_MIN_SUPPLY9     0x8AU  /**< Minimum SUPPLY9 Data */
+#define XSM_MIN_SUPPLY10    0x8BU  /**< Minimum SUPPLY10 Data */
+#define XSM_MIN_VCCAMS      0x8CU  /**< Minimum VCCAMS Data */
+#define XSM_MIN_TEMP_REMOTE     0x8DU  /**< Minimum Remote Temperature Data */
+
+/*@}*/
+
+/**
+ * @name Averaging to be done for the channels.
+ * @{
+ */
+#define XSM_AVG_0_SAMPLES	0U /**< No Averaging */
+#define XSM_AVG_16_SAMPLES	1U /**< Average 16 samples */
+#define XSM_AVG_64_SAMPLES	2U /**< Average 64 samples */
+#define XSM_AVG_256_SAMPLES	3U /**< Average 256 samples */
+
+/*@}*/
+
+/**
+ * @name Channel Sequencer Modes of operation.
+ * @{
+ */
+#define XSM_SEQ_MODE_SAFE	 0U /**< Default Safe Mode */
+#define XSM_SEQ_MODE_ONEPASS	 1U /**< Onepass through Sequencer */
+#define XSM_SEQ_MODE_CONTINPASS	 2U /**< Continuous Cycling Seqquencer */
+#define XSM_SEQ_MODE_SINGCHAN	 3U /**< Single channel - No Sequencing */
+#define XSM_SEQ_MODE_OYLMPUS	 6U /**< Olympus mode */
+
+/*@}*/
+
+/**
+ * @name Clock Divisor values range.
+ * @{
+ */
+#define XSM_CLK_DIV_MIN	 0U /**< Minimum Clock Divisor value */
+#define XSM_CLK_DIV_MAX	 255U /**< Maximum Clock Divisor value */
+
+/*@}*/
+
+/**
+ * @name Alarm Threshold(Limit) Register (ATR) indexes.
+ * @{
+ */
+#define XSM_ATR_TEMP_UPPER	 0U   /**< High user Temperature limit */
+#define XSM_ATR_SUP1_UPPER	 1U   /**< Supply1 high voltage limit */
+#define XSM_ATR_SUP2_UPPER	 2U   /**< Supply2 high voltage limit */
+#define XSM_ATR_OT_UPPER	 3U   /**< Upper Over Temperature limit */
+#define XSM_ATR_TEMP_LOWER	 4U   /**< Low user Temperature */
+#define XSM_ATR_SUP1_LOWER	 5U   /**< Suuply1 low voltage limit */
+#define XSM_ATR_SUP2_LOWER	 6U   /**< Supply2 low voltage limit */
+#define XSM_ATR_OT_LOWER	 7U   /**< Lower Over Temperature limit */
+#define XSM_ATR_SUP3_UPPER	 8U   /**< Supply3 high voltage limit */
+#define XSM_ATR_SUP4_UPPER 	 9U   /**< Supply4 high voltage limit */
+#define XSM_ATR_SUP5_UPPER 	 0xAU /**< Supply5 high voltage limit */
+#define XSM_ATR_SUP6_UPPER 	 0xBU /**< Supply6 high voltage limit */
+#define XSM_ATR_SUP3_LOWER	 0xCU /**< Supply3 low voltage limit */
+#define XSM_ATR_SUP4_LOWER 	 0xDU /**< Supply4 low voltage limit */
+#define XSM_ATR_SUP5_LOWER 	 0xEU /**< Supply5 low voltage limit */
+#define XSM_ATR_SUP6_LOWER 	 0xFU /**< Supply6 low voltage limit */
+#define XSM_ATR_SUP7_UPPER	 0x10U /**< Supply7 high voltage limit */
+#define XSM_ATR_SUP8_UPPER	 0x11U /**< Supply8 high voltage limit */
+#define XSM_ATR_SUP9_UPPER	 0x12U /**< Supply9 high voltage limit */
+#define XSM_ATR_SUP10_UPPER	 0x13U /**< Supply10 high voltage limit */
+#define XSM_ATR_VCCAMS_UPPER	 0x14U /**< VCCAMS high voltage limit */
+#define XSM_ATR_TEMP_RMTE_UPPER	 0x15U /**< High remote Temperature limit */
+#define XSM_ATR_SUP7_LOWER	 0x18U /**< Supply7 low voltage limit */
+#define XSM_ATR_SUP8_LOWER	 0x19U /**< Supply8 low voltage limit */
+#define XSM_ATR_SUP9_LOWER	 0x1AU /**< Supply9 low voltage limit */
+#define XSM_ATR_SUP10_LOWER	 0x1BU /**< Supply10 low voltage limit */
+#define XSM_ATR_VCCAMS_LOWER	 0x1CU /**< VCCAMS low voltage limit */
+#define XSM_ATR_TEMP_RMTE_LOWER	 0x1DU /**< Low remote Temperature limit */
+
+/*@}*/
+
+/**
+ * @name Alarm masks for channels in Configuration registers 1
+ * @{
+ */
+#define XSM_CFR_ALM_SUPPLY6_MASK	0x0800 /**< Alarm 6 - SUPPLY6 */
+#define XSM_CFR_ALM_SUPPLY5_MASK	0x0400 /**< Alarm 5 - SUPPLY5 */
+#define XSM_CFR_ALM_SUPPLY4_MASK	0x0200 /**< Alarm 4 - SUPPLY4 */
+#define XSM_CFR_ALM_SUPPLY3_MASK 	0x0100 /**< Alarm 3 - SUPPLY3 */
+#define XSM_CFR_ALM_SUPPLY2_MASK	0x0008 /**< Alarm 2 - SUPPLY2 */
+#define XSM_CFR_ALM_SUPPLY1_MASK	0x0004 /**< Alarm 1 - SUPPLY1 */
+#define XSM_CFR_ALM_TEMP_MASK		0x0002 /**< Alarm 0 - Temperature */
+#define XSM_CFR_ALM_OT_MASK		0x0001 /**< Over Temperature Alarm */
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ *
+ ******************************************************************************/
+typedef void (*XSysMonPsu_Handler) (void *CallBackRef);
+
+/**
+ * This typedef contains configuration information for a device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddress;		/**< Register base address */
+} XSysMonPsu_Config;
+
+/**
+ * The XSysmonPsu driver instance data. The user is required to allocate a
+ * variable of this type for the SYSMON device in the system. A pointer
+ * to a variable of this type is then passed to the driver API functions.
+ */
+typedef struct {
+	XSysMonPsu_Config Config; 	/**< Device configuration */
+	u32 IsReady;				/**< Device is initialized and ready */
+	XSysMonPsu_Handler Handler;
+	void *CallBackRef;			/**< Callback reference for event handler */
+} XSysMonPsu;
+
+/* BaseAddress Offsets */
+#define XSYSMON_PS 1U
+#define XSYSMON_PL 2U
+#define XSYSMON_AMS 3U
+#define XPS_BA_OFFSET   0x00000800U
+#define XPL_BA_OFFSET   0x00000C00U
+#define XSM_ADC_CH_OFFSET 0x00000200U
+#define XSM_AMS_CH_OFFSET 0x00000060U
+#define XSM_MIN_MAX_CH_OFFSET 0x00000080U
+
+/************************* Variable Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro converts System Monitor Raw Data to Temperature(centigrades)
+* for On-Chip Sensors.
+*
+* @param	AdcData is the SysMon Raw ADC Data.
+*
+* @return 	The Temperature in centigrades.
+*
+* @note		C-Style signature:
+*		float XSysMon_RawToTemperature_OnChip(u32 AdcData)
+*
+*****************************************************************************/
+#define XSysMonPsu_RawToTemperature_OnChip(AdcData)				\
+	((((float)(AdcData)/65536.0f)/0.00199451786f ) - 273.6777f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts System Monitor Raw Data to Temperature(centigrades)
+* for external reference.
+*
+* @param	AdcData is the SysMon Raw ADC Data.
+*
+* @return 	The Temperature in centigrades.
+*
+* @note		C-Style signature:
+*		float XSysMon_RawToTemperature_ExternalRef(u32 AdcData)
+*
+*****************************************************************************/
+#define XSysMonPsu_RawToTemperature_ExternalRef(AdcData)			\
+	((((float)(AdcData)/65536.0f)/0.00198842814f ) - 273.8195f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts System Monitor Raw Data to Voltage(volts).
+*
+* @param	AdcData is the System Monitor ADC Raw Data.
+*
+* @return 	The Voltage in volts.
+*
+* @note		C-Style signature:
+*		float XSysMon_RawToVoltage(u32 AdcData)
+*
+*****************************************************************************/
+#define XSysMonPsu_RawToVoltage(AdcData) 					\
+	((((float)(AdcData))* (3.0f))/65536.0f)
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to System Monitor Raw Data
+* for On-Chip Sensors.
+*
+* @param	Temperature is the Temperature in centigrades to be
+*		converted to System Monitor ADC Raw Data.
+*
+* @return 	The System Monitor ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XSysMon_TemperatureToRaw_OnChip(float Temperature)
+*
+*****************************************************************************/
+#define XSysMonPsu_TemperatureToRaw_OnChip(Temperature)				\
+	((int)(((Temperature) + 273.6777f)*65536.0f*0.00199451786f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Temperature in centigrades to System Monitor Raw Data
+* for external reference.
+*
+* @param	Temperature is the Temperature in centigrades to be
+*		converted to System Monitor ADC Raw Data.
+*
+* @return 	The System Monitor ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XSysMon_TemperatureToRaw_ExternalRef(float Temperature)
+*
+*****************************************************************************/
+#define XSysMonPsu_TemperatureToRaw_ExternalRef(Temperature)		\
+	((int)(((Temperature) + 273.8195f)*65536.0f*0.00198842814f))
+
+/****************************************************************************/
+/**
+*
+* This macro converts Voltage in Volts to System Monitor Raw Data.
+*
+* @param	Voltage is the Voltage in volts to be converted to
+*		System Monitor/ADC Raw Data.
+*
+* @return 	The System Monitor ADC Raw Data.
+*
+* @note		C-Style signature:
+*		int XSysMon_VoltageToRaw(float Voltage)
+*
+*****************************************************************************/
+#define XSysMonPsu_VoltageToRaw(Voltage)			 		\
+	((s32)((Voltage)*65536.0f/3.0f))
+
+/****************************************************************************/
+/**
+*
+* This static inline macro calculates the effective baseaddress based on the
+* Sysmon instance. For PS Sysmon, use additional offset XPS_BA_OFFSET and For
+* PL Sysmon, use additional offset XPL_BA_OFFSET.
+*
+* @param	BaseAddress is the starting address of the SysMon block in
+* 		register database.
+* @param	SysmonBlk is the value that tells whether it is for PS Sysmon block
+*       or PL Sysmon block or the AMS controller register region.
+*
+* @return 	Returns the effective baseaddress of the sysmon instance.
+*
+*****************************************************************************/
+static inline u32 XSysMonPsu_GetEffBaseAddress(u32 BaseAddress, u32 SysmonBlk)
+	{
+		u32 EffBaseAddr;
+
+		if (SysmonBlk == XSYSMON_PS) {
+			EffBaseAddr = BaseAddress + XPS_BA_OFFSET;
+		} else if(SysmonBlk == XSYSMON_PL) {
+			EffBaseAddr = BaseAddress + XPL_BA_OFFSET;
+		} else {
+			EffBaseAddr = BaseAddress;
+		}
+
+		return EffBaseAddr;
+	}
+
+/************************** Function Prototypes ******************************/
+
+/* Functions in xsysmonpsu.c */
+s32 XSysMonPsu_CfgInitialize(XSysMonPsu *InstancePtr, XSysMonPsu_Config *ConfigPtr,
+			  u32 EffectiveAddr);
+void XSysMonPsu_Reset(XSysMonPsu *InstancePtr);
+void XSysMonPsu_Reset_FromLPD(XSysMonPsu *InstancePtr);
+u32 XSysMonPsu_GetStatus(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_StartAdcConversion(XSysMonPsu *InstancePtr);
+u16 XSysMonPsu_GetAdcData(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk);
+u16 XSysMonPsu_GetCalibCoefficient(XSysMonPsu *InstancePtr, u8 CoeffType, u32 SysmonBlk);
+u16 XSysMonPsu_GetMinMaxMeasurement(XSysMonPsu *InstancePtr, u8 MeasurementType,
+		u32 SysmonBlk);
+void XSysMonPsu_SetAvg(XSysMonPsu *InstancePtr, u8 Average, u32 SysmonBlk);
+u8 XSysMonPsu_GetAvg(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSingleChParams(XSysMonPsu *InstancePtr, u8 Channel,
+				u32 IncreaseAcqCycles, u32 IsEventMode,
+				u32 IsDifferentialMode, u32 SysmonBlk);
+void XSysMonPsu_SetAlarmEnables(XSysMonPsu *InstancePtr, u32 AlmEnableMask,
+		u32 SysmonBlk);
+u32 XSysMonPsu_GetAlarmEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_SetSequencerMode(XSysMonPsu *InstancePtr, u8 SequencerMode,
+		u32 SysmonBlk);
+u8 XSysMonPsu_GetSequencerMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_SetSequencerEvent(XSysMonPsu *InstancePtr, u32 IsEventMode,
+		u32 SysmonBlk);
+s32 XSysMonPsu_GetSequencerEvent(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_SetExtenalMux(XSysMonPsu *InstancePtr, u8 Channel, u32 SysmonBlk);
+u32 XSysMonPsu_GetExtenalMux(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_SetAdcClkDivisor(XSysMonPsu *InstancePtr, u8 Divisor, u32 SysmonBlk);
+u8 XSysMonPsu_GetAdcClkDivisor(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqChEnables(XSysMonPsu *InstancePtr, u32 ChEnableMask,
+		u32 SysmonBlk);
+u32 XSysMonPsu_GetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+u32 XSysMonPsu_GetSeqChEnables(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqAvgEnables(XSysMonPsu *InstancePtr, u32 AvgEnableChMask,
+		u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqInputMode(XSysMonPsu *InstancePtr, u32 InputModeChMask,
+		u32 SysmonBlk);
+u32 XSysMonPsu_GetSeqInputMode(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+s32 XSysMonPsu_SetSeqAcqTime(XSysMonPsu *InstancePtr, u32 AcqCyclesChMask,
+		u32 SysmonBlk);
+u32 XSysMonPsu_GetSeqAcqTime(XSysMonPsu *InstancePtr, u32 SysmonBlk);
+void XSysMonPsu_SetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
+		u16 Value, u32 SysmonBlk);
+u16 XSysMonPsu_GetAlarmThreshold(XSysMonPsu *InstancePtr, u8 AlarmThrReg,
+		u32 SysmonBlk);
+void XSysMonPsu_SetPSAutoConversion(XSysMonPsu *InstancePtr);
+u32 XSysMonPsu_GetMonitorStatus(XSysMonPsu *InstancePtr);
+
+/* interrupt functions in xsysmonpsu_intr.c */
+void XSysMonPsu_IntrEnable(XSysMonPsu *InstancePtr, u64 Mask);
+void XSysMonPsu_IntrDisable(XSysMonPsu *InstancePtr, u64 Mask);
+u64 XSysMonPsu_IntrGetEnabled(XSysMonPsu *InstancePtr);
+u64 XSysMonPsu_IntrGetStatus(XSysMonPsu *InstancePtr);
+void XSysMonPsu_IntrClear(XSysMonPsu *InstancePtr, u64 Mask);
+
+/* Functions in xsysmonpsu_selftest.c */
+s32 XSysMonPsu_SelfTest(XSysMonPsu *InstancePtr);
+
+/* Functions in xsysmonpsu_sinit.c */
+XSysMonPsu_Config *XSysMonPsu_LookupConfig(u16 DeviceId);
+
+
+#endif /* XSYSMONPSU_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
new file mode 100644
index 000000000..ace39e369
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_g.c
@@ -0,0 +1,55 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xsysmonpsu.h"
+
+/*
+* The configuration table for devices
+*/
+
+XSysMonPsu_Config XSysMonPsu_ConfigTable[] =
+{
+	{
+		XPAR_PSU_AMS_DEVICE_ID,
+		XPAR_PSU_AMS_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h
new file mode 100644
index 000000000..3012bf327
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_hw.h
@@ -0,0 +1,2268 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsysmonpsu_hw.h
+*
+* This header file contains the identifiers and basic driver functions (or
+* macros) that can be used to access the device. Other driver functions
+* are defined in xsysmonpsu.h.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.0   kvn	  12/15/15 First release
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XSYSMONPSU_HW_H__
+#define XSYSMONPSU_HW_H__
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+#include "xparameters.h"
+
+/**
+ * XSysmonPsu Base Address
+ */
+#define XSYSMONPSU_BASEADDR      0xFFA50000U
+
+/**
+ * Register: XSysmonPsuMisc
+ */
+#define XSYSMONPSU_MISC_OFFSET   0x00000000U
+#define XSYSMONPSU_MISC_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MISC_SLVERR_EN_DRP_SHIFT   1U
+#define XSYSMONPSU_MISC_SLVERR_EN_DRP_WIDTH   1U
+#define XSYSMONPSU_MISC_SLVERR_EN_DRP_MASK    0x00000002U
+
+#define XSYSMONPSU_MISC_SLVERR_EN_SHIFT   0U
+#define XSYSMONPSU_MISC_SLVERR_EN_WIDTH   1U
+#define XSYSMONPSU_MISC_SLVERR_EN_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuIsr0
+ */
+#define XSYSMONPSU_ISR_0_OFFSET   0x00000010U
+#define XSYSMONPSU_ISR_0_MASK	  0xffffffffU
+#define XSYSMONPSU_ISR_0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_15_SHIFT   31U
+#define XSYSMONPSU_ISR_0_PL_ALM_15_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_15_MASK    0x80000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_14_SHIFT   30U
+#define XSYSMONPSU_ISR_0_PL_ALM_14_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_14_MASK    0x40000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_13_SHIFT   29U
+#define XSYSMONPSU_ISR_0_PL_ALM_13_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_13_MASK    0x20000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_12_SHIFT   28U
+#define XSYSMONPSU_ISR_0_PL_ALM_12_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_12_MASK    0x10000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_11_SHIFT   27U
+#define XSYSMONPSU_ISR_0_PL_ALM_11_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_11_MASK    0x08000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_10_SHIFT   26U
+#define XSYSMONPSU_ISR_0_PL_ALM_10_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_10_MASK    0x04000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_9_SHIFT   25U
+#define XSYSMONPSU_ISR_0_PL_ALM_9_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_9_MASK    0x02000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_8_SHIFT   24U
+#define XSYSMONPSU_ISR_0_PL_ALM_8_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_8_MASK    0x01000000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_7_SHIFT   23U
+#define XSYSMONPSU_ISR_0_PL_ALM_7_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_7_MASK    0x00800000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_6_SHIFT   22U
+#define XSYSMONPSU_ISR_0_PL_ALM_6_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_6_MASK    0x00400000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_5_SHIFT   21U
+#define XSYSMONPSU_ISR_0_PL_ALM_5_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_5_MASK    0x00200000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_4_SHIFT   20U
+#define XSYSMONPSU_ISR_0_PL_ALM_4_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_4_MASK    0x00100000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_3_SHIFT   19U
+#define XSYSMONPSU_ISR_0_PL_ALM_3_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_3_MASK    0x00080000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_2_SHIFT   18U
+#define XSYSMONPSU_ISR_0_PL_ALM_2_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_2_MASK    0x00040000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_1_SHIFT   17U
+#define XSYSMONPSU_ISR_0_PL_ALM_1_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_1_MASK    0x00020000U
+
+#define XSYSMONPSU_ISR_0_PL_ALM_0_SHIFT   16U
+#define XSYSMONPSU_ISR_0_PL_ALM_0_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PL_ALM_0_MASK    0x00010000U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_15_SHIFT   15U
+#define XSYSMONPSU_ISR_0_PS_ALM_15_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_15_MASK    0x00008000U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_14_SHIFT   14U
+#define XSYSMONPSU_ISR_0_PS_ALM_14_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_14_MASK    0x00004000U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_13_SHIFT   13U
+#define XSYSMONPSU_ISR_0_PS_ALM_13_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_13_MASK    0x00002000U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_12_SHIFT   12U
+#define XSYSMONPSU_ISR_0_PS_ALM_12_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_12_MASK    0x00001000U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_11_SHIFT   11U
+#define XSYSMONPSU_ISR_0_PS_ALM_11_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_11_MASK    0x00000800U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_10_SHIFT   10U
+#define XSYSMONPSU_ISR_0_PS_ALM_10_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_10_MASK    0x00000400U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_9_SHIFT   9U
+#define XSYSMONPSU_ISR_0_PS_ALM_9_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_9_MASK    0x00000200U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_8_SHIFT   8U
+#define XSYSMONPSU_ISR_0_PS_ALM_8_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_8_MASK    0x00000100U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_7_SHIFT   7U
+#define XSYSMONPSU_ISR_0_PS_ALM_7_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_7_MASK    0x00000080U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_6_SHIFT   6U
+#define XSYSMONPSU_ISR_0_PS_ALM_6_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_6_MASK    0x00000040U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_5_SHIFT   5U
+#define XSYSMONPSU_ISR_0_PS_ALM_5_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_5_MASK    0x00000020U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_4_SHIFT   4U
+#define XSYSMONPSU_ISR_0_PS_ALM_4_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_4_MASK    0x00000010U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_3_SHIFT   3U
+#define XSYSMONPSU_ISR_0_PS_ALM_3_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_3_MASK    0x00000008U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_2_SHIFT   2U
+#define XSYSMONPSU_ISR_0_PS_ALM_2_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_2_MASK    0x00000004U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_1_SHIFT   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_1_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_1_MASK    0x00000002U
+
+#define XSYSMONPSU_ISR_0_PS_ALM_0_SHIFT   0U
+#define XSYSMONPSU_ISR_0_PS_ALM_0_WIDTH   1U
+#define XSYSMONPSU_ISR_0_PS_ALM_0_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuIsr1
+ */
+#define XSYSMONPSU_ISR_1_OFFSET   0x00000014U
+#define XSYSMONPSU_ISR_1_MASK	  0xe000001fU
+#define XSYSMONPSU_ISR_1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_SHIFT   31U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_WIDTH   1U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_MASK    0x80000000U
+
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
+
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
+#define XSYSMONPSU_ISR_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
+
+#define XSYSMONPSU_ISR_1_EOS_SHIFT   4U
+#define XSYSMONPSU_ISR_1_EOS_WIDTH   1U
+#define XSYSMONPSU_ISR_1_EOS_MASK    0x00000010U
+
+#define XSYSMONPSU_ISR_1_EOC_SHIFT   3U
+#define XSYSMONPSU_ISR_1_EOC_WIDTH   1U
+#define XSYSMONPSU_ISR_1_EOC_MASK    0x00000008U
+
+#define XSYSMONPSU_ISR_1_PL_OT_SHIFT   2U
+#define XSYSMONPSU_ISR_1_PL_OT_WIDTH   1U
+#define XSYSMONPSU_ISR_1_PL_OT_MASK    0x00000004U
+
+#define XSYSMONPSU_ISR_1_PS_LPD_OT_SHIFT   1U
+#define XSYSMONPSU_ISR_1_PS_LPD_OT_WIDTH   1U
+#define XSYSMONPSU_ISR_1_PS_LPD_OT_MASK    0x00000002U
+
+#define XSYSMONPSU_ISR_1_PS_FPD_OT_SHIFT   0U
+#define XSYSMONPSU_ISR_1_PS_FPD_OT_WIDTH   1U
+#define XSYSMONPSU_ISR_1_PS_FPD_OT_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuImr0
+ */
+#define XSYSMONPSU_IMR_0_OFFSET   0x00000018U
+#define XSYSMONPSU_IMR_0_RSTVAL   0xffffffffU
+
+#define XSYSMONPSU_IMR_0_PL_ALM_15_SHIFT   31U
+#define XSYSMONPSU_IMR_0_PL_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_15_MASK    0x80000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_14_SHIFT   30U
+#define XSYSMONPSU_IMR_0_PL_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_14_MASK    0x40000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_13_SHIFT   29U
+#define XSYSMONPSU_IMR_0_PL_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_13_MASK    0x20000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_12_SHIFT   28U
+#define XSYSMONPSU_IMR_0_PL_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_12_MASK    0x10000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_11_SHIFT   27U
+#define XSYSMONPSU_IMR_0_PL_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_11_MASK    0x08000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_10_SHIFT   26U
+#define XSYSMONPSU_IMR_0_PL_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_10_MASK    0x04000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_9_SHIFT   25U
+#define XSYSMONPSU_IMR_0_PL_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_9_MASK    0x02000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_8_SHIFT   24U
+#define XSYSMONPSU_IMR_0_PL_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_8_MASK    0x01000000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_7_SHIFT   23U
+#define XSYSMONPSU_IMR_0_PL_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_7_MASK    0x00800000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_6_SHIFT   22U
+#define XSYSMONPSU_IMR_0_PL_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_6_MASK    0x00400000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_5_SHIFT   21U
+#define XSYSMONPSU_IMR_0_PL_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_5_MASK    0x00200000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_4_SHIFT   20U
+#define XSYSMONPSU_IMR_0_PL_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_4_MASK    0x00100000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_3_SHIFT   19U
+#define XSYSMONPSU_IMR_0_PL_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_3_MASK    0x00080000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_2_SHIFT   18U
+#define XSYSMONPSU_IMR_0_PL_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_2_MASK    0x00040000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_1_SHIFT   17U
+#define XSYSMONPSU_IMR_0_PL_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_1_MASK    0x00020000U
+
+#define XSYSMONPSU_IMR_0_PL_ALM_0_SHIFT   16U
+#define XSYSMONPSU_IMR_0_PL_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PL_ALM_0_MASK    0x00010000U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_15_SHIFT   15U
+#define XSYSMONPSU_IMR_0_PS_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_15_MASK    0x00008000U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_14_SHIFT   14U
+#define XSYSMONPSU_IMR_0_PS_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_14_MASK    0x00004000U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_13_SHIFT   13U
+#define XSYSMONPSU_IMR_0_PS_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_13_MASK    0x00002000U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_12_SHIFT   12U
+#define XSYSMONPSU_IMR_0_PS_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_12_MASK    0x00001000U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_11_SHIFT   11U
+#define XSYSMONPSU_IMR_0_PS_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_11_MASK    0x00000800U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_10_SHIFT   10U
+#define XSYSMONPSU_IMR_0_PS_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_10_MASK    0x00000400U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_9_SHIFT   9U
+#define XSYSMONPSU_IMR_0_PS_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_9_MASK    0x00000200U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_8_SHIFT   8U
+#define XSYSMONPSU_IMR_0_PS_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_8_MASK    0x00000100U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_7_SHIFT   7U
+#define XSYSMONPSU_IMR_0_PS_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_7_MASK    0x00000080U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_6_SHIFT   6U
+#define XSYSMONPSU_IMR_0_PS_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_6_MASK    0x00000040U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_5_SHIFT   5U
+#define XSYSMONPSU_IMR_0_PS_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_5_MASK    0x00000020U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_4_SHIFT   4U
+#define XSYSMONPSU_IMR_0_PS_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_4_MASK    0x00000010U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_3_SHIFT   3U
+#define XSYSMONPSU_IMR_0_PS_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_3_MASK    0x00000008U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_2_SHIFT   2U
+#define XSYSMONPSU_IMR_0_PS_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_2_MASK    0x00000004U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_1_SHIFT   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_1_MASK    0x00000002U
+
+#define XSYSMONPSU_IMR_0_PS_ALM_0_SHIFT   0U
+#define XSYSMONPSU_IMR_0_PS_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IMR_0_PS_ALM_0_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuImr1
+ */
+#define XSYSMONPSU_IMR_1_OFFSET   0x0000001CU
+#define XSYSMONPSU_IMR_1_RSTVAL   0xe000001fU
+
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_SHIFT   31U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_WIDTH   1U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_MASK    0x80000000U
+
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
+
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IMR_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
+
+#define XSYSMONPSU_IMR_1_EOS_SHIFT   4U
+#define XSYSMONPSU_IMR_1_EOS_WIDTH   1U
+#define XSYSMONPSU_IMR_1_EOS_MASK    0x00000010U
+
+#define XSYSMONPSU_IMR_1_EOC_SHIFT   3U
+#define XSYSMONPSU_IMR_1_EOC_WIDTH   1U
+#define XSYSMONPSU_IMR_1_EOC_MASK    0x00000008U
+
+#define XSYSMONPSU_IMR_1_PL_OT_SHIFT   2U
+#define XSYSMONPSU_IMR_1_PL_OT_WIDTH   1U
+#define XSYSMONPSU_IMR_1_PL_OT_MASK    0x00000004U
+
+#define XSYSMONPSU_IMR_1_PS_LPD_OT_SHIFT   1U
+#define XSYSMONPSU_IMR_1_PS_LPD_OT_WIDTH   1U
+#define XSYSMONPSU_IMR_1_PS_LPD_OT_MASK    0x00000002U
+
+#define XSYSMONPSU_IMR_1_PS_FPD_OT_SHIFT   0U
+#define XSYSMONPSU_IMR_1_PS_FPD_OT_WIDTH   1U
+#define XSYSMONPSU_IMR_1_PS_FPD_OT_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuIer0
+ */
+#define XSYSMONPSU_IER_0_OFFSET   0x00000020U
+#define XSYSMONPSU_IXR_0_MASK     0xFFFFFFFFU
+#define XSYSMONPSU_IER_0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_15_SHIFT   31U
+#define XSYSMONPSU_IER_0_PL_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_15_MASK    0x80000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_14_SHIFT   30U
+#define XSYSMONPSU_IER_0_PL_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_14_MASK    0x40000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_13_SHIFT   29U
+#define XSYSMONPSU_IER_0_PL_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_13_MASK    0x20000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_12_SHIFT   28U
+#define XSYSMONPSU_IER_0_PL_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_12_MASK    0x10000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_11_SHIFT   27U
+#define XSYSMONPSU_IER_0_PL_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_11_MASK    0x08000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_10_SHIFT   26U
+#define XSYSMONPSU_IER_0_PL_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_10_MASK    0x04000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_9_SHIFT   25U
+#define XSYSMONPSU_IER_0_PL_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_9_MASK    0x02000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_8_SHIFT   24U
+#define XSYSMONPSU_IER_0_PL_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_8_MASK    0x01000000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_7_SHIFT   23U
+#define XSYSMONPSU_IER_0_PL_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_7_MASK    0x00800000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_6_SHIFT   22U
+#define XSYSMONPSU_IER_0_PL_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_6_MASK    0x00400000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_5_SHIFT   21U
+#define XSYSMONPSU_IER_0_PL_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_5_MASK    0x00200000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_4_SHIFT   20U
+#define XSYSMONPSU_IER_0_PL_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_4_MASK    0x00100000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_3_SHIFT   19U
+#define XSYSMONPSU_IER_0_PL_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_3_MASK    0x00080000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_2_SHIFT   18U
+#define XSYSMONPSU_IER_0_PL_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_2_MASK    0x00040000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_1_SHIFT   17U
+#define XSYSMONPSU_IER_0_PL_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_1_MASK    0x00020000U
+
+#define XSYSMONPSU_IER_0_PL_ALM_0_SHIFT   16U
+#define XSYSMONPSU_IER_0_PL_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IER_0_PL_ALM_0_MASK    0x00010000U
+
+#define XSYSMONPSU_IER_0_PS_ALM_15_SHIFT   15U
+#define XSYSMONPSU_IER_0_PS_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_15_MASK    0x00008000U
+
+#define XSYSMONPSU_IER_0_PS_ALM_14_SHIFT   14U
+#define XSYSMONPSU_IER_0_PS_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_14_MASK    0x00004000U
+
+#define XSYSMONPSU_IER_0_PS_ALM_13_SHIFT   13U
+#define XSYSMONPSU_IER_0_PS_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_13_MASK    0x00002000U
+
+#define XSYSMONPSU_IER_0_PS_ALM_12_SHIFT   12U
+#define XSYSMONPSU_IER_0_PS_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_12_MASK    0x00001000U
+
+#define XSYSMONPSU_IER_0_PS_ALM_11_SHIFT   11U
+#define XSYSMONPSU_IER_0_PS_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_11_MASK    0x00000800U
+
+#define XSYSMONPSU_IER_0_PS_ALM_10_SHIFT   10U
+#define XSYSMONPSU_IER_0_PS_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_10_MASK    0x00000400U
+
+#define XSYSMONPSU_IER_0_PS_ALM_9_SHIFT   9U
+#define XSYSMONPSU_IER_0_PS_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_9_MASK    0x00000200U
+
+#define XSYSMONPSU_IER_0_PS_ALM_8_SHIFT   8U
+#define XSYSMONPSU_IER_0_PS_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_8_MASK    0x00000100U
+
+#define XSYSMONPSU_IER_0_PS_ALM_7_SHIFT   7U
+#define XSYSMONPSU_IER_0_PS_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_7_MASK    0x00000080U
+
+#define XSYSMONPSU_IER_0_PS_ALM_6_SHIFT   6U
+#define XSYSMONPSU_IER_0_PS_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_6_MASK    0x00000040U
+
+#define XSYSMONPSU_IER_0_PS_ALM_5_SHIFT   5U
+#define XSYSMONPSU_IER_0_PS_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_5_MASK    0x00000020U
+
+#define XSYSMONPSU_IER_0_PS_ALM_4_SHIFT   4U
+#define XSYSMONPSU_IER_0_PS_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_4_MASK    0x00000010U
+
+#define XSYSMONPSU_IER_0_PS_ALM_3_SHIFT   3U
+#define XSYSMONPSU_IER_0_PS_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_3_MASK    0x00000008U
+
+#define XSYSMONPSU_IER_0_PS_ALM_2_SHIFT   2U
+#define XSYSMONPSU_IER_0_PS_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_2_MASK    0x00000004U
+
+#define XSYSMONPSU_IER_0_PS_ALM_1_SHIFT   1U
+#define XSYSMONPSU_IER_0_PS_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_1_MASK    0x00000002U
+
+#define XSYSMONPSU_IER_0_PS_ALM_0_SHIFT   0U
+#define XSYSMONPSU_IER_0_PS_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IER_0_PS_ALM_0_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuIer1
+ */
+#define XSYSMONPSU_IER_1_OFFSET   0x00000024U
+#define XSYSMONPSU_IXR_1_MASK     0xE000001FU
+#define XSYSMONPSU_IER_1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_SHIFT   31U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_WIDTH   1U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_MASK    0x80000000U
+
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
+
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IER_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
+
+#define XSYSMONPSU_IER_1_EOS_SHIFT   4U
+#define XSYSMONPSU_IER_1_EOS_WIDTH   1U
+#define XSYSMONPSU_IER_1_EOS_MASK    0x00000010U
+
+#define XSYSMONPSU_IER_1_EOC_SHIFT   3U
+#define XSYSMONPSU_IER_1_EOC_WIDTH   1U
+#define XSYSMONPSU_IER_1_EOC_MASK    0x00000008U
+
+#define XSYSMONPSU_IER_1_PL_OT_SHIFT   2U
+#define XSYSMONPSU_IER_1_PL_OT_WIDTH   1U
+#define XSYSMONPSU_IER_1_PL_OT_MASK    0x00000004U
+
+#define XSYSMONPSU_IER_1_PS_LPD_OT_SHIFT   1U
+#define XSYSMONPSU_IER_1_PS_LPD_OT_WIDTH   1U
+#define XSYSMONPSU_IER_1_PS_LPD_OT_MASK    0x00000002U
+
+#define XSYSMONPSU_IER_1_PS_FPD_OT_SHIFT   0U
+#define XSYSMONPSU_IER_1_PS_FPD_OT_WIDTH   1U
+#define XSYSMONPSU_IER_1_PS_FPD_OT_MASK    0x00000001U
+
+#define XSYSMONPSU_IXR_1_SHIFT  32U
+
+/**
+ * Register: XSysmonPsuIdr0
+ */
+#define XSYSMONPSU_IDR_0_OFFSET   0x00000028U
+#define XSYSMONPSU_IDR_0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_15_SHIFT   31U
+#define XSYSMONPSU_IDR_0_PL_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_15_MASK    0x80000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_14_SHIFT   30U
+#define XSYSMONPSU_IDR_0_PL_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_14_MASK    0x40000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_13_SHIFT   29U
+#define XSYSMONPSU_IDR_0_PL_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_13_MASK    0x20000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_12_SHIFT   28U
+#define XSYSMONPSU_IDR_0_PL_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_12_MASK    0x10000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_11_SHIFT   27U
+#define XSYSMONPSU_IDR_0_PL_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_11_MASK    0x08000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_10_SHIFT   26U
+#define XSYSMONPSU_IDR_0_PL_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_10_MASK    0x04000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_9_SHIFT   25U
+#define XSYSMONPSU_IDR_0_PL_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_9_MASK    0x02000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_8_SHIFT   24U
+#define XSYSMONPSU_IDR_0_PL_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_8_MASK    0x01000000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_7_SHIFT   23U
+#define XSYSMONPSU_IDR_0_PL_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_7_MASK    0x00800000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_6_SHIFT   22U
+#define XSYSMONPSU_IDR_0_PL_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_6_MASK    0x00400000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_5_SHIFT   21U
+#define XSYSMONPSU_IDR_0_PL_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_5_MASK    0x00200000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_4_SHIFT   20U
+#define XSYSMONPSU_IDR_0_PL_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_4_MASK    0x00100000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_3_SHIFT   19U
+#define XSYSMONPSU_IDR_0_PL_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_3_MASK    0x00080000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_2_SHIFT   18U
+#define XSYSMONPSU_IDR_0_PL_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_2_MASK    0x00040000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_1_SHIFT   17U
+#define XSYSMONPSU_IDR_0_PL_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_1_MASK    0x00020000U
+
+#define XSYSMONPSU_IDR_0_PL_ALM_0_SHIFT   16U
+#define XSYSMONPSU_IDR_0_PL_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PL_ALM_0_MASK    0x00010000U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_15_SHIFT   15U
+#define XSYSMONPSU_IDR_0_PS_ALM_15_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_15_MASK    0x00008000U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_14_SHIFT   14U
+#define XSYSMONPSU_IDR_0_PS_ALM_14_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_14_MASK    0x00004000U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_13_SHIFT   13U
+#define XSYSMONPSU_IDR_0_PS_ALM_13_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_13_MASK    0x00002000U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_12_SHIFT   12U
+#define XSYSMONPSU_IDR_0_PS_ALM_12_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_12_MASK    0x00001000U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_11_SHIFT   11U
+#define XSYSMONPSU_IDR_0_PS_ALM_11_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_11_MASK    0x00000800U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_10_SHIFT   10U
+#define XSYSMONPSU_IDR_0_PS_ALM_10_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_10_MASK    0x00000400U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_9_SHIFT   9U
+#define XSYSMONPSU_IDR_0_PS_ALM_9_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_9_MASK    0x00000200U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_8_SHIFT   8U
+#define XSYSMONPSU_IDR_0_PS_ALM_8_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_8_MASK    0x00000100U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_7_SHIFT   7U
+#define XSYSMONPSU_IDR_0_PS_ALM_7_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_7_MASK    0x00000080U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_6_SHIFT   6U
+#define XSYSMONPSU_IDR_0_PS_ALM_6_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_6_MASK    0x00000040U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_5_SHIFT   5U
+#define XSYSMONPSU_IDR_0_PS_ALM_5_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_5_MASK    0x00000020U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_4_SHIFT   4U
+#define XSYSMONPSU_IDR_0_PS_ALM_4_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_4_MASK    0x00000010U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_3_SHIFT   3U
+#define XSYSMONPSU_IDR_0_PS_ALM_3_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_3_MASK    0x00000008U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_2_SHIFT   2U
+#define XSYSMONPSU_IDR_0_PS_ALM_2_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_2_MASK    0x00000004U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_1_SHIFT   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_1_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_1_MASK    0x00000002U
+
+#define XSYSMONPSU_IDR_0_PS_ALM_0_SHIFT   0U
+#define XSYSMONPSU_IDR_0_PS_ALM_0_WIDTH   1U
+#define XSYSMONPSU_IDR_0_PS_ALM_0_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuIdr1
+ */
+#define XSYSMONPSU_IDR_1_OFFSET   0x0000002CU
+#define XSYSMONPSU_IDR_1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_SHIFT   31U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_WIDTH   1U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_MASK    0x80000000U
+
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_SHIFT   30U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PL_SYSMON_MASK    0x40000000U
+
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_SHIFT   29U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_WIDTH   1U
+#define XSYSMONPSU_IDR_1_ADD_DECD_ERR_PS_SYSMON_MASK    0x20000000U
+
+#define XSYSMONPSU_IDR_1_EOS_SHIFT   4U
+#define XSYSMONPSU_IDR_1_EOS_WIDTH   1U
+#define XSYSMONPSU_IDR_1_EOS_MASK    0x00000010U
+
+#define XSYSMONPSU_IDR_1_EOC_SHIFT   3U
+#define XSYSMONPSU_IDR_1_EOC_WIDTH   1U
+#define XSYSMONPSU_IDR_1_EOC_MASK    0x00000008U
+
+#define XSYSMONPSU_IDR_1_PL_OT_SHIFT   2U
+#define XSYSMONPSU_IDR_1_PL_OT_WIDTH   1U
+#define XSYSMONPSU_IDR_1_PL_OT_MASK    0x00000004U
+
+#define XSYSMONPSU_IDR_1_PS_LPD_OT_SHIFT   1U
+#define XSYSMONPSU_IDR_1_PS_LPD_OT_WIDTH   1U
+#define XSYSMONPSU_IDR_1_PS_LPD_OT_MASK    0x00000002U
+
+#define XSYSMONPSU_IDR_1_PS_FPD_OT_SHIFT   0U
+#define XSYSMONPSU_IDR_1_PS_FPD_OT_WIDTH   1U
+#define XSYSMONPSU_IDR_1_PS_FPD_OT_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuPsSysmonSts
+ */
+#define XSYSMONPSU_PS_SYSMON_CSTS_OFFSET   0x00000040U
+#define XSYSMONPSU_PS_SYSMON_CSTS_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_SHIFT   24U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_WIDTH   4U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_STE_MASK    0x0f000000U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_SHIFT   16U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_WIDTH   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_DNE_MASK    0x00010000U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_SHIFT   3U
+#define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_WIDTH   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_AUTO_CONVST_MASK    0x00000008U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_SHIFT   2U
+#define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_WIDTH   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_CONVST_MASK    0x00000004U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_SHIFT   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_WIDTH   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_RST_USR_MASK    0x00000002U
+
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_SHIFT   0U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_WIDTH   1U
+#define XSYSMONPSU_PS_SYSMON_CSTS_STRTUP_TRIG_MASK    0x00000001U
+
+#define XSYSMONPSU_PS_SYSMON_READY 0x08010000U
+
+/**
+ * Register: XSysmonPsuPlSysmonSts
+ */
+#define XSYSMONPSU_PL_SYSMON_CSTS_OFFSET   0x00000044U
+#define XSYSMONPSU_PL_SYSMON_CSTS_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_SHIFT   0U
+#define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_WIDTH   1U
+#define XSYSMONPSU_PL_SYSMON_CSTS_ACESBLE_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuMonSts
+ */
+#define XSYSMONPSU_MON_STS_OFFSET   0x00000050U
+#define XSYSMONPSU_MON_STS_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MON_STS_JTAG_LCKD_SHIFT   23U
+#define XSYSMONPSU_MON_STS_JTAG_LCKD_WIDTH   1U
+#define XSYSMONPSU_MON_STS_JTAG_LCKD_MASK    0x00800000U
+
+#define XSYSMONPSU_MON_STS_BSY_SHIFT   22U
+#define XSYSMONPSU_MON_STS_BSY_WIDTH   1U
+#define XSYSMONPSU_MON_STS_BSY_MASK    0x00400000U
+
+#define XSYSMONPSU_MON_STS_CH_SHIFT   16U
+#define XSYSMONPSU_MON_STS_CH_WIDTH   6U
+#define XSYSMONPSU_MON_STS_CH_MASK    0x003f0000U
+
+#define XSYSMONPSU_MON_STS_DATA_SHIFT   0U
+#define XSYSMONPSU_MON_STS_DATA_WIDTH   16U
+#define XSYSMONPSU_MON_STS_DATA_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPspll0
+ */
+#define XSYSMONPSU_VCC_PSPLL0_OFFSET   0x00000060U
+#define XSYSMONPSU_VCC_PSPLL0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSPLL0_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSPLL0_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSPLL0_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPspll1
+ */
+#define XSYSMONPSU_VCC_PSPLL1_OFFSET   0x00000064U
+#define XSYSMONPSU_VCC_PSPLL1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSPLL1_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSPLL1_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSPLL1_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPspll2
+ */
+#define XSYSMONPSU_VCC_PSPLL2_OFFSET   0x00000068U
+#define XSYSMONPSU_VCC_PSPLL2_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSPLL2_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSPLL2_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSPLL2_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPspll3
+ */
+#define XSYSMONPSU_VCC_PSPLL3_OFFSET   0x0000006CU
+#define XSYSMONPSU_VCC_PSPLL3_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSPLL3_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSPLL3_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSPLL3_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPspll4
+ */
+#define XSYSMONPSU_VCC_PSPLL4_OFFSET   0x00000070U
+#define XSYSMONPSU_VCC_PSPLL4_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSPLL4_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSPLL4_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSPLL4_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPsbatt
+ */
+#define XSYSMONPSU_VCC_PSBATT_OFFSET   0x00000074U
+#define XSYSMONPSU_VCC_PSBATT_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSBATT_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSBATT_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSBATT_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccint
+ */
+#define XSYSMONPSU_VCCINT_OFFSET   0x00000078U
+#define XSYSMONPSU_VCCINT_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCCINT_VAL_SHIFT   0U
+#define XSYSMONPSU_VCCINT_VAL_WIDTH   16U
+#define XSYSMONPSU_VCCINT_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccbram
+ */
+#define XSYSMONPSU_VCCBRAM_OFFSET   0x0000007CU
+#define XSYSMONPSU_VCCBRAM_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCCBRAM_VAL_SHIFT   0U
+#define XSYSMONPSU_VCCBRAM_VAL_WIDTH   16U
+#define XSYSMONPSU_VCCBRAM_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccaux
+ */
+#define XSYSMONPSU_VCCAUX_OFFSET   0x00000080U
+#define XSYSMONPSU_VCCAUX_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCCAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VCCAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VCCAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccPsddrpll
+ */
+#define XSYSMONPSU_VCC_PSDDRPLL_OFFSET   0x00000084U
+#define XSYSMONPSU_VCC_PSDDRPLL_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCC_PSDDRPLL_VAL_SHIFT   0U
+#define XSYSMONPSU_VCC_PSDDRPLL_VAL_WIDTH   16U
+#define XSYSMONPSU_VCC_PSDDRPLL_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuDdrphyVref
+ */
+#define XSYSMONPSU_DDRPHY_VREF_OFFSET   0x00000088U
+#define XSYSMONPSU_DDRPHY_VREF_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_DDRPHY_VREF_VAL_SHIFT   0U
+#define XSYSMONPSU_DDRPHY_VREF_VAL_WIDTH   16U
+#define XSYSMONPSU_DDRPHY_VREF_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuDdrphyAto
+ */
+#define XSYSMONPSU_DDRPHY_ATO_OFFSET   0x0000008CU
+#define XSYSMONPSU_DDRPHY_ATO_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_DDRPHY_ATO_VAL_SHIFT   0U
+#define XSYSMONPSU_DDRPHY_ATO_VAL_WIDTH   16U
+#define XSYSMONPSU_DDRPHY_ATO_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuPsgtAt0
+ */
+#define XSYSMONPSU_PSGT_AT0_OFFSET   0x00000090U
+#define XSYSMONPSU_PSGT_AT0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_PSGT_AT0_VAL_SHIFT   0U
+#define XSYSMONPSU_PSGT_AT0_VAL_WIDTH   16U
+#define XSYSMONPSU_PSGT_AT0_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuPsgtAt1
+ */
+#define XSYSMONPSU_PSGT_AT1_OFFSET   0x00000094U
+#define XSYSMONPSU_PSGT_AT1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_PSGT_AT1_VAL_SHIFT   0U
+#define XSYSMONPSU_PSGT_AT1_VAL_WIDTH   16U
+#define XSYSMONPSU_PSGT_AT1_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuReserve0
+ */
+#define XSYSMONPSU_RESERVE0_OFFSET   0x00000098U
+#define XSYSMONPSU_RESERVE0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_RESERVE0_VAL_SHIFT   0U
+#define XSYSMONPSU_RESERVE0_VAL_WIDTH   16U
+#define XSYSMONPSU_RESERVE0_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuReserve1
+ */
+#define XSYSMONPSU_RESERVE1_OFFSET   0x0000009CU
+#define XSYSMONPSU_RESERVE1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_RESERVE1_VAL_SHIFT   0U
+#define XSYSMONPSU_RESERVE1_VAL_WIDTH   16U
+#define XSYSMONPSU_RESERVE1_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuTemp
+ */
+#define XSYSMONPSU_TEMP_OFFSET   0x00000000U
+#define XSYSMONPSU_TEMP_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_TEMP_SHIFT   0U
+#define XSYSMONPSU_TEMP_WIDTH   16U
+#define XSYSMONPSU_TEMP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup1
+ */
+#define XSYSMONPSU_SUP1_OFFSET   0x00000004U
+#define XSYSMONPSU_SUP1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP1_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP1_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP1_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup2
+ */
+#define XSYSMONPSU_SUP2_OFFSET   0x00000008U
+#define XSYSMONPSU_SUP2_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP2_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP2_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP2_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVpVn
+ */
+#define XSYSMONPSU_VP_VN_OFFSET   0x0000000CU
+#define XSYSMONPSU_VP_VN_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VP_VN_SHIFT   0U
+#define XSYSMONPSU_VP_VN_WIDTH   16U
+#define XSYSMONPSU_VP_VN_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVrefp
+ */
+#define XSYSMONPSU_VREFP_OFFSET   0x00000010U
+#define XSYSMONPSU_VREFP_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VREFP_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_VREFP_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_VREFP_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVrefn
+ */
+#define XSYSMONPSU_VREFN_OFFSET   0x00000014U
+#define XSYSMONPSU_VREFN_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VREFN_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_VREFN_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_VREFN_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup3
+ */
+#define XSYSMONPSU_SUP3_OFFSET   0x00000018U
+#define XSYSMONPSU_SUP3_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP3_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP3_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP3_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuCalSupOff
+ */
+#define XSYSMONPSU_CAL_SUP_OFF_OFFSET   0x00000020U
+#define XSYSMONPSU_CAL_SUP_OFF_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CAL_SUP_OFF_VAL_SHIFT   0U
+#define XSYSMONPSU_CAL_SUP_OFF_VAL_WIDTH   16U
+#define XSYSMONPSU_CAL_SUP_OFF_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuCalAdcBiplrOff
+ */
+#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_OFFSET   0x00000024U
+#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_SHIFT   0U
+#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_WIDTH   16U
+#define XSYSMONPSU_CAL_ADC_BIPLR_OFF_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuCalGainErr
+ */
+#define XSYSMONPSU_CAL_GAIN_ERR_OFFSET   0x00000028U
+#define XSYSMONPSU_CAL_GAIN_ERR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CAL_GAIN_ERR_VAL_SHIFT   0U
+#define XSYSMONPSU_CAL_GAIN_ERR_VAL_WIDTH   16U
+#define XSYSMONPSU_CAL_GAIN_ERR_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup4
+ */
+#define XSYSMONPSU_SUP4_OFFSET   0x00000034U
+#define XSYSMONPSU_SUP4_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP4_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP4_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP4_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup5
+ */
+#define XSYSMONPSU_SUP5_OFFSET   0x00000038U
+#define XSYSMONPSU_SUP5_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP5_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP5_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP5_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup6
+ */
+#define XSYSMONPSU_SUP6_OFFSET   0x0000003CU
+#define XSYSMONPSU_SUP6_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP6_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP6_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP6_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux00
+ */
+#define XSYSMONPSU_VAUX00_OFFSET   0x00000040U
+#define XSYSMONPSU_VAUX00_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX00_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX00_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX00_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux01
+ */
+#define XSYSMONPSU_VAUX01_OFFSET   0x00000044U
+#define XSYSMONPSU_VAUX01_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX01_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX01_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX01_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux02
+ */
+#define XSYSMONPSU_VAUX02_OFFSET   0x00000048U
+#define XSYSMONPSU_VAUX02_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX02_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX02_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX02_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux03
+ */
+#define XSYSMONPSU_VAUX03_OFFSET   0x0000004CU
+#define XSYSMONPSU_VAUX03_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX03_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX03_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX03_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux04
+ */
+#define XSYSMONPSU_VAUX04_OFFSET   0x00000050U
+#define XSYSMONPSU_VAUX04_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX04_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX04_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX04_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux05
+ */
+#define XSYSMONPSU_VAUX05_OFFSET   0x00000054U
+#define XSYSMONPSU_VAUX05_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX05_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX05_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX05_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux06
+ */
+#define XSYSMONPSU_VAUX06_OFFSET   0x00000058U
+#define XSYSMONPSU_VAUX06_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX06_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX06_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX06_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux07
+ */
+#define XSYSMONPSU_VAUX07_OFFSET   0x0000005CU
+#define XSYSMONPSU_VAUX07_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX07_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX07_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX07_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux08
+ */
+#define XSYSMONPSU_VAUX08_OFFSET   0x00000060U
+#define XSYSMONPSU_VAUX08_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX08_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX08_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX08_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux09
+ */
+#define XSYSMONPSU_VAUX09_OFFSET   0x00000064U
+#define XSYSMONPSU_VAUX09_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX09_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX09_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX09_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0a
+ */
+#define XSYSMONPSU_VAUX0A_OFFSET   0x00000068U
+#define XSYSMONPSU_VAUX0A_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0A_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0A_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0A_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0b
+ */
+#define XSYSMONPSU_VAUX0B_OFFSET   0x0000006CU
+#define XSYSMONPSU_VAUX0B_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0B_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0B_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0B_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0c
+ */
+#define XSYSMONPSU_VAUX0C_OFFSET   0x00000070U
+#define XSYSMONPSU_VAUX0C_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0C_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0C_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0C_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0d
+ */
+#define XSYSMONPSU_VAUX0D_OFFSET   0x00000074U
+#define XSYSMONPSU_VAUX0D_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0D_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0D_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0D_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0e
+ */
+#define XSYSMONPSU_VAUX0E_OFFSET   0x00000078U
+#define XSYSMONPSU_VAUX0E_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0E_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0E_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0E_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVaux0f
+ */
+#define XSYSMONPSU_VAUX0F_OFFSET   0x0000007CU
+#define XSYSMONPSU_VAUX0F_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VAUX0F_VAUX_VAL_SHIFT   0U
+#define XSYSMONPSU_VAUX0F_VAUX_VAL_WIDTH   16U
+#define XSYSMONPSU_VAUX0F_VAUX_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxTemp
+ */
+#define XSYSMONPSU_MAX_TEMP_OFFSET   0x00000080U
+#define XSYSMONPSU_MAX_TEMP_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_TEMP_SHIFT   0U
+#define XSYSMONPSU_MAX_TEMP_WIDTH   16U
+#define XSYSMONPSU_MAX_TEMP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup1
+ */
+#define XSYSMONPSU_MAX_SUP1_OFFSET   0x00000084U
+#define XSYSMONPSU_MAX_SUP1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP1_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP1_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP1_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup2
+ */
+#define XSYSMONPSU_MAX_SUP2_OFFSET   0x00000088U
+#define XSYSMONPSU_MAX_SUP2_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP2_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP2_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP2_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup3
+ */
+#define XSYSMONPSU_MAX_SUP3_OFFSET   0x0000008CU
+#define XSYSMONPSU_MAX_SUP3_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP3_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP3_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP3_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinTemp
+ */
+#define XSYSMONPSU_MIN_TEMP_OFFSET   0x00000090U
+#define XSYSMONPSU_MIN_TEMP_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_TEMP_SHIFT   0U
+#define XSYSMONPSU_MIN_TEMP_WIDTH   16U
+#define XSYSMONPSU_MIN_TEMP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup1
+ */
+#define XSYSMONPSU_MIN_SUP1_OFFSET   0x00000094U
+#define XSYSMONPSU_MIN_SUP1_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP1_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP1_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP1_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup2
+ */
+#define XSYSMONPSU_MIN_SUP2_OFFSET   0x00000098U
+#define XSYSMONPSU_MIN_SUP2_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP2_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP2_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP2_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup3
+ */
+#define XSYSMONPSU_MIN_SUP3_OFFSET   0x0000009CU
+#define XSYSMONPSU_MIN_SUP3_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP3_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP3_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP3_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup4
+ */
+#define XSYSMONPSU_MAX_SUP4_OFFSET   0x000000A0U
+#define XSYSMONPSU_MAX_SUP4_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP4_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP4_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP4_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup5
+ */
+#define XSYSMONPSU_MAX_SUP5_OFFSET   0x000000A4U
+#define XSYSMONPSU_MAX_SUP5_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP5_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP5_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP5_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup6
+ */
+#define XSYSMONPSU_MAX_SUP6_OFFSET   0x000000A8U
+#define XSYSMONPSU_MAX_SUP6_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP6_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP6_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP6_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup4
+ */
+#define XSYSMONPSU_MIN_SUP4_OFFSET   0x000000B0U
+#define XSYSMONPSU_MIN_SUP4_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP4_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP4_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP4_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup5
+ */
+#define XSYSMONPSU_MIN_SUP5_OFFSET   0x000000B4U
+#define XSYSMONPSU_MIN_SUP5_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP5_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP5_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP5_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup6
+ */
+#define XSYSMONPSU_MIN_SUP6_OFFSET   0x000000B8U
+#define XSYSMONPSU_MIN_SUP6_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP6_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP6_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP6_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuStsFlag
+ */
+#define XSYSMONPSU_STS_FLAG_OFFSET   0x000000FCU
+#define XSYSMONPSU_STS_FLAG_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_SHIFT   15U
+#define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_CLK_OSC_USED_MASK    0x00008000U
+
+#define XSYSMONPSU_STS_FLAG_BLK_IN_RST_SHIFT   14U
+#define XSYSMONPSU_STS_FLAG_BLK_IN_RST_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_BLK_IN_RST_MASK    0x00004000U
+
+#define XSYSMONPSU_STS_FLAG_JTAG_DISD_SHIFT   11U
+#define XSYSMONPSU_STS_FLAG_JTAG_DISD_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_JTAG_DISD_MASK    0x00000800U
+
+#define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_SHIFT   10U
+#define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_JTAG_RD_ONLY_MASK    0x00000400U
+
+#define XSYSMONPSU_STS_FLAG_INTRNL_REF_SHIFT   9U
+#define XSYSMONPSU_STS_FLAG_INTRNL_REF_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_INTRNL_REF_MASK    0x00000200U
+
+#define XSYSMONPSU_STS_FLAG_DISD_SHIFT   8U
+#define XSYSMONPSU_STS_FLAG_DISD_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_DISD_MASK    0x00000100U
+
+#define XSYSMONPSU_STS_FLAG_ALM_6_3_SHIFT   4U
+#define XSYSMONPSU_STS_FLAG_ALM_6_3_WIDTH   4U
+#define XSYSMONPSU_STS_FLAG_ALM_6_3_MASK    0x000000f0U
+
+#define XSYSMONPSU_STS_FLAG_OT_SHIFT   3U
+#define XSYSMONPSU_STS_FLAG_OT_WIDTH   1U
+#define XSYSMONPSU_STS_FLAG_OT_MASK    0x00000008U
+
+#define XSYSMONPSU_STS_FLAG_ALM_2_0_SHIFT   0U
+#define XSYSMONPSU_STS_FLAG_ALM_2_0_WIDTH   3U
+#define XSYSMONPSU_STS_FLAG_ALM_2_0_MASK    0x00000007U
+
+/**
+ * Register: XSysmonPsuCfgReg0
+ */
+#define XSYSMONPSU_CFG_REG0_OFFSET   0x00000100U
+#define XSYSMONPSU_CFG_REG0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CFG_REG0_AVRGNG_SHIFT   12U
+#define XSYSMONPSU_CFG_REG0_AVRGNG_WIDTH   2U
+#define XSYSMONPSU_CFG_REG0_AVRGNG_MASK    0x00003000U
+
+#define XSYSMONPSU_CFG_REG0_XTRNL_MUX_SHIFT   11U
+#define XSYSMONPSU_CFG_REG0_XTRNL_MUX_WIDTH   1U
+#define XSYSMONPSU_CFG_REG0_XTRNL_MUX_MASK    0x00000800U
+
+#define XSYSMONPSU_CFG_REG0_BU_SHIFT   10U
+#define XSYSMONPSU_CFG_REG0_BU_WIDTH   1U
+#define XSYSMONPSU_CFG_REG0_BU_MASK    0x00000400U
+
+#define XSYSMONPSU_CFG_REG0_EC_SHIFT   9U
+#define XSYSMONPSU_CFG_REG0_EC_WIDTH   1U
+#define XSYSMONPSU_CFG_REG0_EC_MASK    0x00000200U
+
+#define XSYSMONPSU_EVENT_MODE	1
+#define XSYSMONPSU_CONTINUOUS_MODE 2
+
+#define XSYSMONPSU_CFG_REG0_ACQ_SHIFT   8U
+#define XSYSMONPSU_CFG_REG0_ACQ_WIDTH   1U
+#define XSYSMONPSU_CFG_REG0_ACQ_MASK    0x00000100U
+
+#define XSYSMONPSU_CFG_REG0_MUX_CH_SHIFT   0U
+#define XSYSMONPSU_CFG_REG0_MUX_CH_WIDTH   6U
+#define XSYSMONPSU_CFG_REG0_MUX_CH_MASK    0x0000003fU
+
+/**
+ * Register: XSysmonPsuCfgReg1
+ */
+#define XSYSMONPSU_CFG_REG1_OFFSET   0x00000104U
+#define XSYSMONPSU_CFG_REG1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CFG_REG1_SEQ_MDE_SHIFT   12U
+#define XSYSMONPSU_CFG_REG1_SEQ_MDE_WIDTH   4U
+#define XSYSMONPSU_CFG_REG1_SEQ_MDE_MASK    0x0000f000U
+
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_SHIFT   8U
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_WIDTH   4U
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS6TO3_MASK    0x00000f00U
+
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_SHIFT   1U
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_WIDTH   3U
+#define XSYSMONPSU_CFG_REG1_ALRM_DIS2TO0_MASK    0x0000000eU
+
+#define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_SHIFT   0U
+#define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_WIDTH   1U
+#define XSYSMONPSU_CFG_REG1_OVR_TEMP_DIS_MASK    0x00000001U
+
+#define XSYSMONPSU_CFG_REG1_ALRM_ALL_MASK 0x00000f0fU
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP6_MASK		0x0800U
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP5_MASK		0x0400U
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP4_MASK		0x0200U
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP3_MASK		0x0100U
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP2_MASK		0x0008U
+#define XSYSMONPSU_CFR_REG1_ALRM_SUP1_MASK		0x0004U
+#define XSYSMONPSU_CFR_REG1_ALRM_TEMP_MASK		0x0002U
+#define XSYSMONPSU_CFR_REG1_ALRM_OT_MASK		0x0001U
+
+/**
+ * Register: XSysmonPsuCfgReg2
+ */
+#define XSYSMONPSU_CFG_REG2_OFFSET   0x00000108U
+#define XSYSMONPSU_CFG_REG2_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_CFG_REG2_CLK_DVDR_SHIFT   8U
+#define XSYSMONPSU_CFG_REG2_CLK_DVDR_WIDTH   8U
+#define XSYSMONPSU_CFG_REG2_CLK_DVDR_MASK    0x0000ff00U
+
+#define XSYSMONPSU_CLK_DVDR_MIN_VAL			0U
+#define XSYSMONPSU_CLK_DVDR_MAX_VAL			255U
+
+#define XSYSMONPSU_CFG_REG2_PWR_DOWN_SHIFT   4U
+#define XSYSMONPSU_CFG_REG2_PWR_DOWN_WIDTH   4U
+#define XSYSMONPSU_CFG_REG2_PWR_DOWN_MASK    0x000000f0U
+
+#define XSYSMONPSU_CFG_REG2_TST_CH_EN_SHIFT   2U
+#define XSYSMONPSU_CFG_REG2_TST_CH_EN_WIDTH   1U
+#define XSYSMONPSU_CFG_REG2_TST_CH_EN_MASK    0x00000004U
+
+#define XSYSMONPSU_CFG_REG2_TST_MDE_SHIFT   0U
+#define XSYSMONPSU_CFG_REG2_TST_MDE_WIDTH   2U
+#define XSYSMONPSU_CFG_REG2_TST_MDE_MASK    0x00000003U
+
+/**
+ * Register: XSysmonPsuSeqCh0
+ */
+#define XSYSMONPSU_SEQ_CH0_OFFSET   0x00000120U
+#define XSYSMONPSU_SEQ_CH0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_CH0_CUR_MON_SHIFT   15U
+#define XSYSMONPSU_SEQ_CH0_CUR_MON_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_CUR_MON_MASK    0x00008000U
+
+#define XSYSMONPSU_SEQ_CH0_SUP3_SHIFT   14U
+#define XSYSMONPSU_SEQ_CH0_SUP3_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP3_MASK    0x00004000U
+
+#define XSYSMONPSU_SEQ_CH0_VREFN_SHIFT   13U
+#define XSYSMONPSU_SEQ_CH0_VREFN_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_VREFN_MASK    0x00002000U
+
+#define XSYSMONPSU_SEQ_CH0_VREFP_SHIFT   12U
+#define XSYSMONPSU_SEQ_CH0_VREFP_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_VREFP_MASK    0x00001000U
+
+#define XSYSMONPSU_SEQ_CH0_VP_VN_SHIFT   11U
+#define XSYSMONPSU_SEQ_CH0_VP_VN_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_VP_VN_MASK    0x00000800U
+
+#define XSYSMONPSU_SEQ_CH0_SUP2_SHIFT   10U
+#define XSYSMONPSU_SEQ_CH0_SUP2_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP2_MASK    0x00000400U
+
+#define XSYSMONPSU_SEQ_CH0_SUP1_SHIFT   9U
+#define XSYSMONPSU_SEQ_CH0_SUP1_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP1_MASK    0x00000200U
+
+#define XSYSMONPSU_SEQ_CH0_TEMP_SHIFT   8U
+#define XSYSMONPSU_SEQ_CH0_TEMP_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_TEMP_MASK    0x00000100U
+
+#define XSYSMONPSU_SEQ_CH0_SUP6_SHIFT   7U
+#define XSYSMONPSU_SEQ_CH0_SUP6_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP6_MASK    0x00000080U
+
+#define XSYSMONPSU_SEQ_CH0_SUP5_SHIFT   6U
+#define XSYSMONPSU_SEQ_CH0_SUP5_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP5_MASK    0x00000040U
+
+#define XSYSMONPSU_SEQ_CH0_SUP4_SHIFT   5U
+#define XSYSMONPSU_SEQ_CH0_SUP4_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_SUP4_MASK    0x00000020U
+
+#define XSYSMONPSU_SEQ_CH0_TST_CH_SHIFT   3U
+#define XSYSMONPSU_SEQ_CH0_TST_CH_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_TST_CH_MASK    0x00000008U
+
+#define XSYSMONPSU_SEQ_CH0_CALIBRTN_SHIFT   0U
+#define XSYSMONPSU_SEQ_CH0_CALIBRTN_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH0_CALIBRTN_MASK    0x00000001U
+
+#define XSYSMONPSU_SEQ_CH0_VALID_MASK     0x0000FFE9U
+
+/**
+ * Register: XSysmonPsuSeqCh1
+ */
+#define XSYSMONPSU_SEQ_CH1_OFFSET         0x00000124U
+#define XSYSMONPSU_SEQ_CH1_VALID_MASK     0x0000FFFFU
+#define XSYSMONPSU_SEQ_CH1_RSTVAL         0x00000000U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0F_SHIFT   15U
+#define XSYSMONPSU_SEQ_CH1_VAUX0F_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0F_MASK    0x00008000U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0E_SHIFT   14U
+#define XSYSMONPSU_SEQ_CH1_VAUX0E_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0E_MASK    0x00004000U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0D_SHIFT   13U
+#define XSYSMONPSU_SEQ_CH1_VAUX0D_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0D_MASK    0x00002000U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0C_SHIFT   12U
+#define XSYSMONPSU_SEQ_CH1_VAUX0C_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0C_MASK    0x00001000U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0B_SHIFT   11U
+#define XSYSMONPSU_SEQ_CH1_VAUX0B_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0B_MASK    0x00000800U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX0A_SHIFT   10U
+#define XSYSMONPSU_SEQ_CH1_VAUX0A_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX0A_MASK    0x00000400U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX09_SHIFT   9U
+#define XSYSMONPSU_SEQ_CH1_VAUX09_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX09_MASK    0x00000200U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX08_SHIFT   8U
+#define XSYSMONPSU_SEQ_CH1_VAUX08_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX08_MASK    0x00000100U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX07_SHIFT   7U
+#define XSYSMONPSU_SEQ_CH1_VAUX07_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX07_MASK    0x00000080U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX06_SHIFT   6U
+#define XSYSMONPSU_SEQ_CH1_VAUX06_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX06_MASK    0x00000040U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX05_SHIFT   5U
+#define XSYSMONPSU_SEQ_CH1_VAUX05_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX05_MASK    0x00000020U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX04_SHIFT   4U
+#define XSYSMONPSU_SEQ_CH1_VAUX04_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX04_MASK    0x00000010U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX03_SHIFT   3U
+#define XSYSMONPSU_SEQ_CH1_VAUX03_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX03_MASK    0x00000008U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX02_SHIFT   2U
+#define XSYSMONPSU_SEQ_CH1_VAUX02_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX02_MASK    0x00000004U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX01_SHIFT   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX01_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX01_MASK    0x00000002U
+
+#define XSYSMONPSU_SEQ_CH1_VAUX00_SHIFT   0U
+#define XSYSMONPSU_SEQ_CH1_VAUX00_WIDTH   1U
+#define XSYSMONPSU_SEQ_CH1_VAUX00_MASK    0x00000001U
+
+#define XSM_SEQ_CH_SHIFT                  16U
+
+/**
+ * Register: XSysmonPsuSeqAverage0
+ */
+#define XSYSMONPSU_SEQ_AVERAGE0_OFFSET   0x00000128U
+#define XSYSMONPSU_SEQ_AVERAGE0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_AVERAGE0_SHIFT   0U
+#define XSYSMONPSU_SEQ_AVERAGE0_WIDTH   16U
+#define XSYSMONPSU_SEQ_AVERAGE0_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSeqAverage1
+ */
+#define XSYSMONPSU_SEQ_AVERAGE1_OFFSET   0x0000012CU
+#define XSYSMONPSU_SEQ_AVERAGE1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_AVERAGE1_SHIFT   0U
+#define XSYSMONPSU_SEQ_AVERAGE1_WIDTH   16U
+#define XSYSMONPSU_SEQ_AVERAGE1_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSeqInputMde0
+ */
+#define XSYSMONPSU_SEQ_INPUT_MDE0_OFFSET   0x00000130U
+#define XSYSMONPSU_SEQ_INPUT_MDE0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_INPUT_MDE0_SHIFT   0U
+#define XSYSMONPSU_SEQ_INPUT_MDE0_WIDTH   16U
+#define XSYSMONPSU_SEQ_INPUT_MDE0_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSeqInputMde1
+ */
+#define XSYSMONPSU_SEQ_INPUT_MDE1_OFFSET   0x00000134U
+#define XSYSMONPSU_SEQ_INPUT_MDE1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_INPUT_MDE1_SHIFT   0U
+#define XSYSMONPSU_SEQ_INPUT_MDE1_WIDTH   16U
+#define XSYSMONPSU_SEQ_INPUT_MDE1_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSeqAcq0
+ */
+#define XSYSMONPSU_SEQ_ACQ0_OFFSET   0x00000138U
+#define XSYSMONPSU_SEQ_ACQ0_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_ACQ0_SHIFT   0U
+#define XSYSMONPSU_SEQ_ACQ0_WIDTH   16U
+#define XSYSMONPSU_SEQ_ACQ0_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSeqAcq1
+ */
+#define XSYSMONPSU_SEQ_ACQ1_OFFSET   0x0000013CU
+#define XSYSMONPSU_SEQ_ACQ1_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SEQ_ACQ1_SHIFT   0U
+#define XSYSMONPSU_SEQ_ACQ1_WIDTH   16U
+#define XSYSMONPSU_SEQ_ACQ1_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmTempUpr
+ */
+#define XSYSMONPSU_ALRM_TEMP_UPR_OFFSET   0x00000140U
+#define XSYSMONPSU_ALRM_TEMP_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_TEMP_UPR_SHIFT   0U
+#define XSYSMONPSU_ALRM_TEMP_UPR_WIDTH   16U
+#define XSYSMONPSU_ALRM_TEMP_UPR_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup1Upr
+ */
+#define XSYSMONPSU_ALRM_SUP1_UPR_OFFSET   0x00000144U
+#define XSYSMONPSU_ALRM_SUP1_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP1_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP1_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP1_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup2Upr
+ */
+#define XSYSMONPSU_ALRM_SUP2_UPR_OFFSET   0x00000148U
+#define XSYSMONPSU_ALRM_SUP2_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP2_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP2_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP2_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmOtUpr
+ */
+#define XSYSMONPSU_ALRM_OT_UPR_OFFSET   0x0000014CU
+#define XSYSMONPSU_ALRM_OT_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_OT_UPR_TEMP_SHIFT   0U
+#define XSYSMONPSU_ALRM_OT_UPR_TEMP_WIDTH   16U
+#define XSYSMONPSU_ALRM_OT_UPR_TEMP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmTempLwr
+ */
+#define XSYSMONPSU_ALRM_TEMP_LWR_OFFSET   0x00000150U
+#define XSYSMONPSU_ALRM_TEMP_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_TEMP_LWR_SHIFT   1U
+#define XSYSMONPSU_ALRM_TEMP_LWR_WIDTH   15U
+#define XSYSMONPSU_ALRM_TEMP_LWR_MASK    0x0000fffeU
+
+#define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_SHIFT   0U
+#define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_WIDTH   1U
+#define XSYSMONPSU_ALRM_TEMP_LWR_TSHLD_MDE_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuAlrmSup1Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP1_LWR_OFFSET   0x00000154U
+#define XSYSMONPSU_ALRM_SUP1_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP1_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP1_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP1_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup2Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP2_LWR_OFFSET   0x00000158U
+#define XSYSMONPSU_ALRM_SUP2_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP2_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP2_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP2_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmOtLwr
+ */
+#define XSYSMONPSU_ALRM_OT_LWR_OFFSET   0x0000015CU
+#define XSYSMONPSU_ALRM_OT_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_OT_LWR_TEMP_SHIFT   1U
+#define XSYSMONPSU_ALRM_OT_LWR_TEMP_WIDTH   15U
+#define XSYSMONPSU_ALRM_OT_LWR_TEMP_MASK    0x0000fffeU
+
+#define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_SHIFT   0U
+#define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_WIDTH   1U
+#define XSYSMONPSU_ALRM_OT_LWR_TSHLD_MDE_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuAlrmSup3Upr
+ */
+#define XSYSMONPSU_ALRM_SUP3_UPR_OFFSET   0x00000160U
+#define XSYSMONPSU_ALRM_SUP3_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP3_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP3_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP3_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup4Upr
+ */
+#define XSYSMONPSU_ALRM_SUP4_UPR_OFFSET   0x00000164U
+#define XSYSMONPSU_ALRM_SUP4_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP4_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP4_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP4_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup5Upr
+ */
+#define XSYSMONPSU_ALRM_SUP5_UPR_OFFSET   0x00000168U
+#define XSYSMONPSU_ALRM_SUP5_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP5_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP5_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP5_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup6Upr
+ */
+#define XSYSMONPSU_ALRM_SUP6_UPR_OFFSET   0x0000016CU
+#define XSYSMONPSU_ALRM_SUP6_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP6_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP6_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP6_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup3Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP3_LWR_OFFSET   0x00000170U
+#define XSYSMONPSU_ALRM_SUP3_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP3_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP3_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP3_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup4Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP4_LWR_OFFSET   0x00000174U
+#define XSYSMONPSU_ALRM_SUP4_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP4_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP4_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP4_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup5Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP5_LWR_OFFSET   0x00000178U
+#define XSYSMONPSU_ALRM_SUP5_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP5_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP5_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP5_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup6Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP6_LWR_OFFSET   0x0000017CU
+#define XSYSMONPSU_ALRM_SUP6_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP6_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP6_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP6_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup7Upr
+ */
+#define XSYSMONPSU_ALRM_SUP7_UPR_OFFSET   0x00000180U
+#define XSYSMONPSU_ALRM_SUP7_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP7_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP7_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP7_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup8Upr
+ */
+#define XSYSMONPSU_ALRM_SUP8_UPR_OFFSET   0x00000184U
+#define XSYSMONPSU_ALRM_SUP8_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP8_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP8_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP8_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup9Upr
+ */
+#define XSYSMONPSU_ALRM_SUP9_UPR_OFFSET   0x00000188U
+#define XSYSMONPSU_ALRM_SUP9_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP9_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP9_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP9_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup10Upr
+ */
+#define XSYSMONPSU_ALRM_SUP10_UPR_OFFSET   0x0000018CU
+#define XSYSMONPSU_ALRM_SUP10_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP10_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP10_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP10_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmVccamsUpr
+ */
+#define XSYSMONPSU_ALRM_VCCAMS_UPR_OFFSET   0x00000190U
+#define XSYSMONPSU_ALRM_VCCAMS_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_VCCAMS_UPR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmTremoteUpr
+ */
+#define XSYSMONPSU_ALRM_TREMOTE_UPR_OFFSET   0x00000194U
+#define XSYSMONPSU_ALRM_TREMOTE_UPR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_SHIFT   0U
+#define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_WIDTH   16U
+#define XSYSMONPSU_ALRM_TREMOTE_UPR_TEMP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup7Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP7_LWR_OFFSET   0x000001A0U
+#define XSYSMONPSU_ALRM_SUP7_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP7_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP7_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP7_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup8Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP8_LWR_OFFSET   0x000001A4U
+#define XSYSMONPSU_ALRM_SUP8_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP8_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP8_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP8_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup9Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP9_LWR_OFFSET   0x000001A8U
+#define XSYSMONPSU_ALRM_SUP9_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP9_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP9_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP9_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmSup10Lwr
+ */
+#define XSYSMONPSU_ALRM_SUP10_LWR_OFFSET   0x000001ACU
+#define XSYSMONPSU_ALRM_SUP10_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_SUP10_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_SUP10_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_SUP10_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmVccamsLwr
+ */
+#define XSYSMONPSU_ALRM_VCCAMS_LWR_OFFSET   0x000001B0U
+#define XSYSMONPSU_ALRM_VCCAMS_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_SHIFT   0U
+#define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_WIDTH   16U
+#define XSYSMONPSU_ALRM_VCCAMS_LWR_SUP_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuAlrmTremoteLwr
+ */
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_OFFSET   0x000001B4U
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_SHIFT   1U
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_WIDTH   15U
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TEMP_MASK    0x0000fffeU
+
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_SHIFT   0U
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_WIDTH   1U
+#define XSYSMONPSU_ALRM_TREMOTE_LWR_TSHLD_MDE_MASK    0x00000001U
+
+/**
+ * Register: XSysmonPsuSup7
+ */
+#define XSYSMONPSU_SUP7_OFFSET   0x00000200U
+#define XSYSMONPSU_SUP7_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP7_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP7_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP7_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup8
+ */
+#define XSYSMONPSU_SUP8_OFFSET   0x00000204U
+#define XSYSMONPSU_SUP8_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP8_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP8_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP8_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup9
+ */
+#define XSYSMONPSU_SUP9_OFFSET   0x00000208U
+#define XSYSMONPSU_SUP9_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP9_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP9_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP9_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuSup10
+ */
+#define XSYSMONPSU_SUP10_OFFSET   0x0000020CU
+#define XSYSMONPSU_SUP10_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_SUP10_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_SUP10_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_SUP10_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuVccams
+ */
+#define XSYSMONPSU_VCCAMS_OFFSET   0x00000210U
+#define XSYSMONPSU_VCCAMS_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_VCCAMS_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_VCCAMS_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_VCCAMS_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuTempRemte
+ */
+#define XSYSMONPSU_TEMP_REMTE_OFFSET   0x00000214U
+#define XSYSMONPSU_TEMP_REMTE_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_TEMP_REMTE_SHIFT   0U
+#define XSYSMONPSU_TEMP_REMTE_WIDTH   16U
+#define XSYSMONPSU_TEMP_REMTE_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup7
+ */
+#define XSYSMONPSU_MAX_SUP7_OFFSET   0x00000280U
+#define XSYSMONPSU_MAX_SUP7_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP7_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP7_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP7_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup8
+ */
+#define XSYSMONPSU_MAX_SUP8_OFFSET   0x00000284U
+#define XSYSMONPSU_MAX_SUP8_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP8_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP8_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP8_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup9
+ */
+#define XSYSMONPSU_MAX_SUP9_OFFSET   0x00000288U
+#define XSYSMONPSU_MAX_SUP9_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP9_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP9_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP9_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxSup10
+ */
+#define XSYSMONPSU_MAX_SUP10_OFFSET   0x0000028CU
+#define XSYSMONPSU_MAX_SUP10_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_SUP10_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_SUP10_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_SUP10_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxVccams
+ */
+#define XSYSMONPSU_MAX_VCCAMS_OFFSET   0x00000290U
+#define XSYSMONPSU_MAX_VCCAMS_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MAX_VCCAMS_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMaxTempRemte
+ */
+#define XSYSMONPSU_MAX_TEMP_REMTE_OFFSET   0x00000294U
+#define XSYSMONPSU_MAX_TEMP_REMTE_RSTVAL   0x00000000U
+
+#define XSYSMONPSU_MAX_TEMP_REMTE_SHIFT   0U
+#define XSYSMONPSU_MAX_TEMP_REMTE_WIDTH   16U
+#define XSYSMONPSU_MAX_TEMP_REMTE_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup7
+ */
+#define XSYSMONPSU_MIN_SUP7_OFFSET   0x000002A0U
+#define XSYSMONPSU_MIN_SUP7_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP7_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP7_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP7_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup8
+ */
+#define XSYSMONPSU_MIN_SUP8_OFFSET   0x000002A4U
+#define XSYSMONPSU_MIN_SUP8_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP8_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP8_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP8_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup9
+ */
+#define XSYSMONPSU_MIN_SUP9_OFFSET   0x000002A8U
+#define XSYSMONPSU_MIN_SUP9_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP9_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP9_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP9_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinSup10
+ */
+#define XSYSMONPSU_MIN_SUP10_OFFSET   0x000002ACU
+#define XSYSMONPSU_MIN_SUP10_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_SUP10_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_SUP10_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_SUP10_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinVccams
+ */
+#define XSYSMONPSU_MIN_VCCAMS_OFFSET   0x000002B0U
+#define XSYSMONPSU_MIN_VCCAMS_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_SHIFT   0U
+#define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_WIDTH   16U
+#define XSYSMONPSU_MIN_VCCAMS_SUP_VAL_MASK    0x0000ffffU
+
+/**
+ * Register: XSysmonPsuMinTempRemte
+ */
+#define XSYSMONPSU_MIN_TEMP_REMTE_OFFSET   0x000002B4U
+#define XSYSMONPSU_MIN_TEMP_REMTE_RSTVAL   0x0000ffffU
+
+#define XSYSMONPSU_MIN_TEMP_REMTE_SHIFT   0U
+#define XSYSMONPSU_MIN_TEMP_REMTE_WIDTH   16U
+#define XSYSMONPSU_MIN_TEMP_REMTE_MASK    0x0000ffffU
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	RegisterAddr is the register address in the address
+* 			space of the SYSMONPSU device.
+*
+* @return	The 32-bit value of the register
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XSysmonPsu_ReadReg(RegisterAddr) Xil_In32(RegisterAddr)
+
+/****************************************************************************/
+/**
+*
+* This macro writes the given register.
+*
+* @param	RegisterAddr is the register address in the address
+* 			space of the SYSMONPSU device.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+#define XSysmonPsu_WriteReg(RegisterAddr, Data) Xil_Out32(RegisterAddr, (u32)(Data))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XSYSMONPSU_HW_H__ */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c
new file mode 100644
index 000000000..b178c2e11
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_intr.c
@@ -0,0 +1,250 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsysmonpsu_intr.c
+*
+* This file contains functions related to SYSMONPSU interrupt handling.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.0   kvn    12/15/15 First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xsysmonpsu.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Variable Definitions *****************************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* This function enables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Mask is the 64 bit-mask of the interrupts to be enabled.
+*		Bit positions of 1 will be enabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XSYSMONPSU_IER_0_* and XSYSMONPSU_IER_1_* bits defined in
+*		xsysmonpsu_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_IntrEnable(XSysMonPsu *InstancePtr, u64 Mask)
+{
+	u32 RegValue;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Enable the specified interrupts in the AMS Interrupt Enable Register. */
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_IER_0_OFFSET);
+	RegValue |= (u32)(Mask & (u64)XSYSMONPSU_IXR_0_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IER_0_OFFSET,
+			  RegValue);
+
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_IER_1_OFFSET);
+	RegValue |= (u32)((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IER_1_OFFSET,
+			  RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function disables the specified interrupts in the device.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Mask is the 64 bit-mask of the interrupts to be disabled.
+*		Bit positions of 1 will be disabled. Bit positions of 0 will
+*		keep the previous setting. This mask is formed by OR'ing
+*		XSYSMONPSU_IDR_0_* and XSYSMONPSU_IDR_1_* bits defined in
+*		xsysmonpsu_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_IntrDisable(XSysMonPsu *InstancePtr, u64 Mask)
+{
+	u32 RegValue;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable the specified interrupts in the AMS Interrupt Disable Register. */
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_IDR_0_OFFSET);
+	RegValue |= (u32)(Mask & (u64)XSYSMONPSU_IXR_0_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IDR_0_OFFSET,
+			  RegValue);
+
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_IDR_1_OFFSET);
+	RegValue |= (u32)((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_IDR_1_OFFSET,
+			  RegValue);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the enabled interrupts read from the Interrupt Enable
+* Register (IER). Use the XSYSMONPSU_IER_0_* and XSYSMONPSU_IER_1_* constants
+* defined in xsysmonpsu_hw.h to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	A 64-bit value representing the contents of the Interrupt Mask
+* 			Registers (IMR1 IMR0).
+*
+* @note		None.
+*
+*****************************************************************************/
+u64 XSysMonPsu_IntrGetEnabled(XSysMonPsu *InstancePtr)
+{
+	u64 MaskedInterrupts;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Return the value read from the AMS Interrupt Mask Register. */
+	MaskedInterrupts = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+                         XSYSMONPSU_IMR_0_OFFSET) & (u64)XSYSMONPSU_IXR_0_MASK;
+	MaskedInterrupts |= ((u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+                         XSYSMONPSU_IMR_1_OFFSET) & (u64)XSYSMONPSU_IXR_1_MASK)
+                          << XSYSMONPSU_IXR_1_SHIFT;
+
+	return (~MaskedInterrupts);
+}
+
+/****************************************************************************/
+/**
+*
+* This function returns the interrupt status read from Interrupt Status
+* Register(ISR). Use the XSYSMONPSU_ISR_0_* and XSYSMONPSU_ISR_1_ constants
+* defined in xsysmonpsu_hw.h to interpret the returned value.
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return	A 64-bit value representing the contents of the Interrupt Status
+* 			Registers (ISR1 ISR0).
+*
+* @note		None.
+*
+*****************************************************************************/
+u64 XSysMonPsu_IntrGetStatus(XSysMonPsu *InstancePtr)
+{
+	u64 IntrStatusRegister;
+
+	/* Assert the arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Return the value read from the AMS ISR. */
+	IntrStatusRegister = (u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+                           XSYSMONPSU_ISR_0_OFFSET) & (u64)XSYSMONPSU_IXR_0_MASK;
+	IntrStatusRegister |= ((u64)XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+                           XSYSMONPSU_ISR_1_OFFSET) & (u64)XSYSMONPSU_IXR_1_MASK)
+                           << XSYSMONPSU_IXR_1_SHIFT;
+
+	return IntrStatusRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function clears the specified interrupts in the Interrupt Status
+* Register (ISR).
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+* @param	Mask is the 64 bit-mask of the interrupts to be cleared.
+*		Bit positions of 1 will be cleared. Bit positions of 0 will not
+* 		change the previous interrupt status. This mask is formed by
+* 		OR'ing the XSYSMONPSU_ISR_0_* and XSYSMONPSU_ISR_1_* bits
+* 		which are defined in xsysmonpsu_hw.h.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XSysMonPsu_IntrClear(XSysMonPsu *InstancePtr, u64 Mask)
+{
+	u32 RegValue;
+
+	/* Assert the arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Clear the specified interrupts in the Interrupt Status register. */
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_ISR_0_OFFSET);
+	RegValue &= (u32)(Mask & (u64)XSYSMONPSU_IXR_0_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_ISR_0_OFFSET,
+			  RegValue);
+
+	RegValue = XSysmonPsu_ReadReg(InstancePtr->Config.BaseAddress +
+					XSYSMONPSU_ISR_1_OFFSET);
+	RegValue &= (u32)((Mask >> XSYSMONPSU_IXR_1_SHIFT) & XSYSMONPSU_IXR_1_MASK);
+	XSysmonPsu_WriteReg(InstancePtr->Config.BaseAddress + XSYSMONPSU_ISR_1_OFFSET,
+			  RegValue);
+}
+
+
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c
new file mode 100644
index 000000000..5b709be14
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_selftest.c
@@ -0,0 +1,132 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsysmon_selftest.c
+*
+* This file contains a diagnostic self test function for the XSysMon driver.
+* The self test function does a simple read/write test of the Alarm Threshold
+* Register.
+*
+* See xsysmonpsu.h for more information.
+*
+* @note	None.
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- -----  -------- -----------------------------------------------------
+* 1.0   kvn   12/15/15  First release
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xsysmonpsu.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constant defines the test value to be written
+ * to the Alarm Threshold Register
+ */
+#define XSM_ATR_TEST_VALUE 		0x55U
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+
+/************************** Function Prototypes *****************************/
+
+/*****************************************************************************/
+/**
+*
+* Run a self-test on the driver/device. The test
+*	- Resets the device,
+*	- Writes a value into the Alarm Threshold register and reads it back
+*	for comparison.
+*	- Resets the device again.
+*
+*
+* @param	InstancePtr is a pointer to the XSysMonPsu instance.
+*
+* @return
+*		- XST_SUCCESS if the value read from the Alarm Threshold
+*		register is the same as the value written.
+*		- XST_FAILURE Otherwise
+*
+* @note		This is a destructive test in that resets of the device are
+*		performed. Refer to the device specification for the
+*		device status after the reset operation.
+*
+******************************************************************************/
+s32 XSysMonPsu_SelfTest(XSysMonPsu *InstancePtr)
+{
+	s32 Status;
+	u32 RegValue;
+
+	/* Assert the argument */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Reset the device to get it back to its default state */
+	XSysMonPsu_Reset(InstancePtr);
+
+	/*
+	 * Write a value into the Alarm Threshold registers, read it back, and
+	 * do the comparison
+	 */
+	XSysMonPsu_SetAlarmThreshold(InstancePtr, XSM_ATR_SUP1_UPPER,
+				  XSM_ATR_TEST_VALUE, XSYSMON_PS);
+	RegValue = (u32)XSysMonPsu_GetAlarmThreshold(InstancePtr,
+					XSM_ATR_SUP1_UPPER, XSYSMON_PS);
+
+	if (RegValue == XSM_ATR_TEST_VALUE) {
+		Status = XST_SUCCESS;
+	} else {
+		Status = XST_FAILURE;
+	}
+
+	/* Reset the device again to its default state. */
+	XSysMonPsu_Reset(InstancePtr);
+
+	/* Return the test result. */
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c
new file mode 100644
index 000000000..34249a209
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/sysmonpsu_v1_0/src/xsysmonpsu_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2016 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xsysmonpsu_sinit.c
+*
+* This file contains the implementation of the XSysMonPsu driver's static
+* initialization functionality.
+*
+* @note		None.
+*
+* 
+*
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	    Changes
+* ----- -----  -------- -----------------------------------------------
+* 1.0   kvn    12/15/15 First release.
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xsysmonpsu.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+extern XSysMonPsu_Config XSysMonPsu_ConfigTable[];
+
+/*****************************************************************************/
+/**
+*
+* This function looks for the device configuration based on the unique device
+* ID. The table XSysmonPsu_ConfigTable[] contains the configuration information
+* for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XSysMonPsu_Config *XSysMonPsu_LookupConfig(u16 DeviceId)
+{
+	XSysMonPsu_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XSYSMONPSU_NUM_INSTANCES; Index++) {
+		if (XSysMonPsu_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XSysMonPsu_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return CfgPtr;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/Makefile
new file mode 100644
index 000000000..35c277dde
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner ttcps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling ttcps"
+
+ttcps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: ttcps_includes
+
+ttcps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c
new file mode 100644
index 000000000..4534553f6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.c
@@ -0,0 +1,441 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file contains the implementation of the XTtcPs driver. This driver
+* controls the operation of one timer counter in the Triple Timer Counter (TTC)
+* module in the Ps block. Refer to xttcps.h for more detailed description
+* of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.01	pkp	   01/30/16 Modified XTtcPs_CfgInitialize to add XTtcps_Stop
+*						to stop the timer before configuring
+*
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Initializes a specific XTtcPs instance such that the driver is ready to use.
+* This function initializes a single timer counter in the triple timer counter
+* function block.
+*
+* The state of the device after initialization is:
+*  - Overflow Mode
+*  - Internal (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	ConfigPtr is a reference to a structure containing information
+*		about a specific TTC device.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, then use
+*		ConfigPtr->BaseAddress for this parameter, passing the physical
+*		address instead.
+*
+* @return
+*
+* 		- XST_SUCCESS if the initialization is successful.
+*		- XST_DEVICE_IS_STARTED if the device is started. It must be
+*		  stopped to re-initialize.
+*
+* @note		Device has to be stopped first to call this function to
+*		initialize it.
+*
+******************************************************************************/
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr, XTtcPs_Config *ConfigPtr,
+			      u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 IsStartResult;
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * Set some default values
+	 */
+	InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = ConfigPtr->InputClockHz;
+
+	IsStartResult = XTtcPs_IsStarted(InstancePtr);
+	/*
+	 * If the timer counter has already started, return an error
+	 * Device should be stopped first.
+	 */
+	if(IsStartResult == (u32)TRUE) {
+		Status = XST_DEVICE_IS_STARTED;
+	} else {
+
+		/*
+		 * stop the timer before configuring
+		 */
+		XTtcPs_Stop(InstancePtr);
+		/*
+		 * Reset the count control register to it's default value.
+		 */
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CNT_CNTRL_OFFSET,
+				  XTTCPS_CNT_CNTRL_RESET_VALUE);
+
+		/*
+		 * Reset the rest of the registers to the default values.
+		 */
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CLK_CNTRL_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_INTERVAL_VAL_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_1_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_2_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_MATCH_2_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_IER_OFFSET, 0x00U);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_ISR_OFFSET, XTTCPS_IXR_ALL_MASK);
+
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		/*
+		 * Reset the counter value
+		 */
+		XTtcPs_ResetCounterValue(InstancePtr);
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to set the match registers. There are three match
+* registers.
+*
+* The match 0 register is special. If the waveform output mode is enabled, the
+* waveform will change polarity when the count matches the value in the match 0
+* register. The polarity of the waveform output can also be set using the
+* XTtcPs_SetOptions() function.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+* @param	Value is the 16-bit value to be set in the match register.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value)
+{
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(MatchIndex < (u8)XTTCPS_NUM_MATCH_REG);
+
+	/*
+	 * Write the value to the correct match register with MatchIndex
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTtcPs_Match_N_Offset(MatchIndex), Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function is used to get the value of the match registers. There are
+* three match registers.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	MatchIndex is the index to the match register to be set.
+*		Valid values are 0, 1, or 2.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex)
+{
+	u32 MatchReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(MatchIndex < XTTCPS_NUM_MATCH_REG);
+
+	MatchReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			    XTtcPs_Match_N_Offset(MatchIndex));
+
+	return (u16) MatchReg;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the prescaler enable bit and if needed sets the prescaler
+* bits in the control register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	PrescalerValue is a number from 0-16 that sets the prescaler
+*		to use.
+*		If the parameter is 0 - 15, use a prescaler on the clock of
+*		2^(PrescalerValue+1), or 2-65536.
+*		If the parameter is XTTCPS_CLK_CNTRL_PS_DISABLE, do not use a
+*		prescaler.
+*
+* @return	None
+*
+* @note		None
+*
+****************************************************************************/
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue)
+{
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(PrescalerValue <= XTTCPS_CLK_CNTRL_PS_DISABLE);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+			   XTTCPS_CLK_CNTRL_OFFSET);
+
+	/*
+	 * Clear all of the prescaler control bits in the register
+	 */
+	ClockReg &=
+		~(XTTCPS_CLK_CNTRL_PS_VAL_MASK | XTTCPS_CLK_CNTRL_PS_EN_MASK);
+
+	if (PrescalerValue < XTTCPS_CLK_CNTRL_PS_DISABLE) {
+		/*
+		 * Set the prescaler value and enable prescaler
+		 */
+		ClockReg |= (u32)(((u32)PrescalerValue << (u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT) &
+			(u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK);
+		ClockReg |= (u32)XTTCPS_CLK_CNTRL_PS_EN_MASK;
+	}
+
+	/*
+	 * Write the register with the new values.
+	 */
+	XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+			  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the input clock prescaler
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* 
+* @return	The value(n) from which the prescalar value is calculated
+*		as 2^(n+1). Some example values are given below :
+*
+* 	Value		Prescaler
+* 	0		2
+* 	1		4
+* 	N		2^(n+1)
+* 	15		65536
+* 	16		1
+* 

+*
+* @note		None.
+*
+****************************************************************************/
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr)
+{
+	u8 Status;
+	u32 ClockReg;
+
+	/*
+	 * Assert to validate input arguments.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the clock control register
+	 */
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+
+	if (0 == (ClockReg & XTTCPS_CLK_CNTRL_PS_EN_MASK)) {
+		/*
+		 * Prescaler is disabled. Return the correct flag value
+		 */
+		Status = (u8)XTTCPS_CLK_CNTRL_PS_DISABLE;
+	}
+	else {
+
+		Status = (u8)((ClockReg & (u32)XTTCPS_CLK_CNTRL_PS_VAL_MASK) >>
+			(u32)XTTCPS_CLK_CNTRL_PS_VAL_SHIFT);
+	}
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function calculates the interval value as well as the prescaler value
+* for a given frequency.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Freq is the requested output frequency for the device.
+* @param	Interval is the interval value for the given frequency,
+*		it is the output value for this function.
+* @param	Prescaler is the prescaler value for the given frequency,
+*		it is the output value for this function.
+*
+* @return	None.
+*
+* @note
+*  Upon successful calculation for the given frequency, Interval and Prescaler
+*  carry the settings for the timer counter; Upon unsuccessful calculation,
+*  Interval and Prescaler are set to 0xFF(FF) for their maximum values to
+*  signal the caller of failure. Therefore, caller needs to check the return
+*  interval or prescaler values for whether the function has succeeded.
+*
+****************************************************************************/
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        u16 *Interval, u8 *Prescaler)
+{
+	u8 TmpPrescaler;
+	u32 TempValue;
+	u32 InputClock;
+
+	InputClock = InstancePtr->Config.InputClockHz;
+	/*
+	 * Find the smallest prescaler that will work for a given frequency. The
+	 * smaller the prescaler, the larger the count and the more accurate the
+	 *  PWM setting.
+	 */
+	TempValue = InputClock/ Freq;
+
+	if (TempValue < 4U) {
+		/*
+		 * The frequency is too high, it is too close to the input
+		 * clock value. Use maximum values to signal caller.
+		 */
+		*Interval = 0xFFFFU;
+		*Prescaler = 0xFFU;
+		return;
+	}
+
+	/*
+	 * First, do we need a prescaler or not?
+	 */
+	if (((u32)65536U) > TempValue) {
+		/*
+		 * We do not need a prescaler, so set the values appropriately
+		 */
+		*Interval = (u16)TempValue;
+		*Prescaler = XTTCPS_CLK_CNTRL_PS_DISABLE;
+		return;
+	}
+
+
+	for (TmpPrescaler = 0U; TmpPrescaler < XTTCPS_CLK_CNTRL_PS_DISABLE;
+	     TmpPrescaler++) {
+		TempValue =	InputClock/ (Freq * (1U << (TmpPrescaler + 1U)));
+
+		/*
+		 * The first value less than 2^16 is the best bet
+		 */
+		if (((u32)65536U) > TempValue) {
+			/*
+			 * Set the values appropriately
+			 */
+			*Interval = (u16)TempValue;
+			*Prescaler = TmpPrescaler;
+			return;
+		}
+	}
+
+	/* Can not find interval values that work for the given frequency.
+	 * Return maximum values to signal caller.
+	 */
+	*Interval = 0XFFFFU;
+	*Prescaler = 0XFFU;
+	return;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h
new file mode 100644
index 000000000..646d24db5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps.h
@@ -0,0 +1,412 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps.h
+* @addtogroup ttcps_v3_0
+* @{
+* @details
+*
+* This is the driver for one 16-bit timer counter in the Triple Timer Counter
+* (TTC) module in the Ps block.
+*
+* The TTC module provides three independent timer/counter modules that can each
+* be clocked using either the system clock (pclk) or an externally driven
+* clock (ext_clk). In addition, each counter can independently prescale its
+* selected clock input (divided by 2 to 65536). Counters can be set to
+* decrement or increment.
+*
+* Each of the counters can be programmed to generate interrupt pulses:
+*	. At a regular, predefined period, that is on a timed interval
+*	. When the counter registers overflow
+* 	. When the count matches any one of the three 'match' registers
+*
+* Therefore, up to six different events can trigger a timer interrupt: three
+* match interrupts, an overflow interrupt, an interval interrupt and an event
+* timer interrupt. Note that the overflow interrupt and the interval interrupt
+* are mutually exclusive.
+*
+* Initialization & Configuration
+*
+* An XTtcPs_Config structure is used to configure a driver instance.
+* Information in the XTtcPs_Config structure is the hardware properties
+* about the device.
+*
+* A driver instance is initialized through
+* XTtcPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr). Where CfgPtr
+* is a pointer to the XTtcPs_Config structure, it can be looked up statically
+* through XTtcPs_LookupConfig(DeviceID), or passed in by the caller. The
+* EffectiveAddr can be the static base address of the device or virtual
+* mapped address if address translation is supported.
+*
+* Interrupts
+*
+* Interrupt handler is not provided by the driver, as handling of interrupt
+* is application specific.
+*
+* @note
+* The default setting for a timer/counter is:
+*  - Overflow Mode
+*  - Internal clock (pclk) selected
+*  - Counter disabled
+*  - All Interrupts disabled
+*  - Output waveforms disabled
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------------
+* 1.00a drg/jz 01/20/10 First release..
+* 2.0   adk    12/10/13 Updated as per the New Tcl API's
+* 3.0	pkp    12/09/14 Added support for Zynq Ultrascale Mp.Also code
+*			modified for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+#ifndef XTTCPS_H		/* prevent circular inclusions */
+#define XTTCPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xttcps_hw.h"
+#include "xstatus.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Configuration options
+ *
+ * Options for the device. Each of the options is bit field, so more than one
+ * options can be specified.
+ *
+ * @{
+ */
+#define XTTCPS_OPTION_EXTERNAL_CLK	0x00000001U 	/**< External clock source */
+#define XTTCPS_OPTION_CLK_EDGE_NEG	0x00000002U	/**< Clock on trailing edge for
+						     external clock*/
+#define XTTCPS_OPTION_INTERVAL_MODE	0x00000004U	/**< Interval mode */
+#define XTTCPS_OPTION_DECREMENT		0x00000008U	/**< Decrement the counter */
+#define XTTCPS_OPTION_MATCH_MODE	0x00000010U	/**< Match mode */
+#define XTTCPS_OPTION_WAVE_DISABLE	0x00000020U 	/**< No waveform output */
+#define XTTCPS_OPTION_WAVE_POLARITY	0x00000040U	/**< Waveform polarity */
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	  /**< Unique ID for device */
+	u32 BaseAddress;  /**< Base address for device */
+	u32 InputClockHz; /**< Input clock frequency */
+} XTtcPs_Config;
+
+/**
+ * The XTtcPs driver instance data. The user is required to allocate a
+ * variable of this type for each PS timer/counter device in the system. A
+ * pointer to a variable of this type is then passed to various driver API
+ * functions.
+ */
+typedef struct {
+	XTtcPs_Config Config;	/**< Configuration structure */
+	u32 IsReady;		/**< Device is initialized and ready */
+} XTtcPs;
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*
+ * Internal helper macros
+ */
+#define InstReadReg(InstancePtr, RegOffset) \
+    (Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset)))
+
+#define InstWriteReg(InstancePtr, RegOffset, Data) \
+    (Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/*****************************************************************************/
+/**
+*
+* This function starts the counter/timer without resetting the counter value.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Start(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Start(InstancePtr)	\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) &	\
+		 ~XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function stops the counter/timer. This macro may be called at any time
+* to stop the counter. The counter holds the last value until it is reset,
+* restarted or enabled.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_Stop(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_Stop(InstancePtr)		\
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) |	\
+		 XTTCPS_CNT_CNTRL_DIS_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function checks whether the timer counter has already started.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance
+*
+* @return	Non-zero if the device has started, '0' otherwise.
+*
+* @note		C-style signature:
+*		int XTtcPs_IsStarted(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_IsStarted(InstancePtr) \
+     ((InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) & \
+       XTTCPS_CNT_CNTRL_DIS_MASK) == 0U)
+
+/*****************************************************************************/
+/**
+*
+* This function returns the current 16-bit counter value. It may be called at
+* any time.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	16-bit counter value.
+*
+* @note		C-style signature:
+*		u16 XTtcPs_GetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_GetCounterValue(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_COUNT_VALUE_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function sets the interval value to be used in interval mode.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Value is the 16-bit value to be set in the interval register.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_SetInterval(XTtcPs *InstancePtr, u16 Value)
+*
+****************************************************************************/
+#define XTtcPs_SetInterval(InstancePtr, Value)	\
+		InstWriteReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET, (Value))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the interval value from the interval register.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	16-bit interval value
+*
+* @note		C-style signature:
+*		u16 XTtcPs_GetInterval(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_GetInterval(InstancePtr) \
+		(u16)InstReadReg((InstancePtr), XTTCPS_INTERVAL_VAL_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This macro resets the count register. It may be called at any time. The
+* counter is reset to either 0 or 0xFFFF, or the interval value, depending on
+* the increment/decrement mode. The state of the counter, as started or
+* stopped, is not affected by calling reset.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None
+*
+* @note		C-style signature:
+*		void XTtcPs_ResetCounterValue(XTtcPs *InstancePtr)
+*
+****************************************************************************/
+#define XTtcPs_ResetCounterValue(InstancePtr) \
+		InstWriteReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_CNT_CNTRL_OFFSET) | \
+		 (u32)XTTCPS_CNT_CNTRL_RST_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function enables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be enabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be enabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_EnableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_EnableInterrupts(InstancePtr, InterruptMask)		\
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,		\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) |	\
+		 (InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function disables the interrupts.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be disabled.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be disabled, cleared bits
+*		will not be disabled.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_DisableInterrupts(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_DisableInterrupts(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_IER_OFFSET,	\
+		(InstReadReg((InstancePtr), XTTCPS_IER_OFFSET) &	\
+		 ~(InterruptMask)))
+
+/*****************************************************************************/
+/**
+*
+* This function reads the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_GetInterruptStatus(XTtcPs *InstancePtr)
+*
+******************************************************************************/
+#define XTtcPs_GetInterruptStatus(InstancePtr)	 \
+		InstReadReg((InstancePtr), XTTCPS_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the interrupt status.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	InterruptMask defines which interrupt should be cleared.
+*		Constants are defined in xttcps_hw.h as XTTCPS_IXR_*.
+*		This is a bit mask, all set bits will be cleared, cleared bits
+*		will not be cleared.
+*
+* @return	None.
+*
+* @note
+* C-style signature:
+*	void XTtcPs_ClearInterruptStatus(XTtcPs *InstancePtr, u32 InterruptMask)
+*
+******************************************************************************/
+#define XTtcPs_ClearInterruptStatus(InstancePtr, InterruptMask) \
+		InstWriteReg((InstancePtr), XTTCPS_ISR_OFFSET, \
+		 (InterruptMask))
+
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Initialization functions in xttcps_sinit.c
+ */
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Required functions, in xttcps.c
+ */
+s32 XTtcPs_CfgInitialize(XTtcPs *InstancePtr,
+         XTtcPs_Config * ConfigPtr, u32 EffectiveAddr);
+
+void XTtcPs_SetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex, u16 Value);
+u16 XTtcPs_GetMatchValue(XTtcPs *InstancePtr, u8 MatchIndex);
+
+void XTtcPs_SetPrescaler(XTtcPs *InstancePtr, u8 PrescalerValue);
+u8 XTtcPs_GetPrescaler(XTtcPs *InstancePtr);
+
+void XTtcPs_CalcIntervalFromFreq(XTtcPs *InstancePtr, u32 Freq,
+        u16 *Interval, u8 *Prescaler);
+
+/*
+ * Functions for options, in file xttcps_options.c
+ */
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options);
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr);
+
+/*
+ * Function for self-test, in file xttcps_selftest.c
+ */
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c
new file mode 100644
index 000000000..10c16eb02
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_g.c
@@ -0,0 +1,111 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xttcps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XTtcPs_Config XTtcPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_TTC_0_DEVICE_ID,
+		XPAR_PSU_TTC_0_BASEADDR,
+		XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_1_DEVICE_ID,
+		XPAR_PSU_TTC_1_BASEADDR,
+		XPAR_PSU_TTC_1_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_2_DEVICE_ID,
+		XPAR_PSU_TTC_2_BASEADDR,
+		XPAR_PSU_TTC_2_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_3_DEVICE_ID,
+		XPAR_PSU_TTC_3_BASEADDR,
+		XPAR_PSU_TTC_3_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_4_DEVICE_ID,
+		XPAR_PSU_TTC_4_BASEADDR,
+		XPAR_PSU_TTC_4_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_5_DEVICE_ID,
+		XPAR_PSU_TTC_5_BASEADDR,
+		XPAR_PSU_TTC_5_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_6_DEVICE_ID,
+		XPAR_PSU_TTC_6_BASEADDR,
+		XPAR_PSU_TTC_6_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_7_DEVICE_ID,
+		XPAR_PSU_TTC_7_BASEADDR,
+		XPAR_PSU_TTC_7_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_8_DEVICE_ID,
+		XPAR_PSU_TTC_8_BASEADDR,
+		XPAR_PSU_TTC_8_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_9_DEVICE_ID,
+		XPAR_PSU_TTC_9_BASEADDR,
+		XPAR_PSU_TTC_9_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_10_DEVICE_ID,
+		XPAR_PSU_TTC_10_BASEADDR,
+		XPAR_PSU_TTC_10_TTC_CLK_FREQ_HZ
+	},
+	{
+		XPAR_PSU_TTC_11_DEVICE_ID,
+		XPAR_PSU_TTC_11_BASEADDR,
+		XPAR_PSU_TTC_11_TTC_CLK_FREQ_HZ
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_hw.h
new file mode 100644
index 000000000..af78bcd67
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_hw.h
@@ -0,0 +1,212 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_hw.h
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file defines the hardware interface to one of the three timer counters
+* in the Ps block.
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -------------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+******************************************************************************/
+
+#ifndef XTTCPS_HW_H		/* prevent circular inclusions */
+#define XTTCPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets from the base address of the device.
+ *
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_OFFSET		0x00000000U  /**< Clock Control Register */
+#define XTTCPS_CNT_CNTRL_OFFSET		0x0000000CU  /**< Counter Control Register*/
+#define XTTCPS_COUNT_VALUE_OFFSET	0x00000018U  /**< Current Counter Value */
+#define XTTCPS_INTERVAL_VAL_OFFSET	0x00000024U  /**< Interval Count Value */
+#define XTTCPS_MATCH_0_OFFSET		0x00000030U  /**< Match 1 value */
+#define XTTCPS_MATCH_1_OFFSET		0x0000003CU  /**< Match 2 value */
+#define XTTCPS_MATCH_2_OFFSET		0x00000048U  /**< Match 3 value */
+#define XTTCPS_ISR_OFFSET			0x00000054U  /**< Interrupt Status Register */
+#define XTTCPS_IER_OFFSET			0x00000060U  /**< Interrupt Enable Register */
+/* @} */
+
+/** @name Clock Control Register
+ * Clock Control Register definitions
+ * @{
+ */
+#define XTTCPS_CLK_CNTRL_PS_EN_MASK		0x00000001U  /**< Prescale enable */
+#define XTTCPS_CLK_CNTRL_PS_VAL_MASK	0x0000001EU  /**< Prescale value */
+#define XTTCPS_CLK_CNTRL_PS_VAL_SHIFT			 1U  /**< Prescale shift */
+#define XTTCPS_CLK_CNTRL_PS_DISABLE				16U  /**< Prescale disable */
+#define XTTCPS_CLK_CNTRL_SRC_MASK		0x00000020U  /**< Clock source */
+#define XTTCPS_CLK_CNTRL_EXT_EDGE_MASK	0x00000040U  /**< External Clock edge */
+/* @} */
+
+/** @name Counter Control Register
+ * Counter Control Register definitions
+ * @{
+ */
+#define XTTCPS_CNT_CNTRL_DIS_MASK		0x00000001U /**< Disable the counter */
+#define XTTCPS_CNT_CNTRL_INT_MASK		0x00000002U /**< Interval mode */
+#define XTTCPS_CNT_CNTRL_DECR_MASK		0x00000004U /**< Decrement mode */
+#define XTTCPS_CNT_CNTRL_MATCH_MASK		0x00000008U /**< Match mode */
+#define XTTCPS_CNT_CNTRL_RST_MASK		0x00000010U /**< Reset counter */
+#define XTTCPS_CNT_CNTRL_EN_WAVE_MASK	0x00000020U /**< Enable waveform */
+#define XTTCPS_CNT_CNTRL_POL_WAVE_MASK	0x00000040U /**< Waveform polarity */
+#define XTTCPS_CNT_CNTRL_RESET_VALUE	0x00000021U /**< Reset value */
+/* @} */
+
+/** @name Current Counter Value Register
+ * Current Counter Value Register definitions
+ * @{
+ */
+#define XTTCPS_COUNT_VALUE_MASK		0x0000FFFFU /**< 16-bit counter value */
+/* @} */
+
+/** @name Interval Value Register
+ * Interval Value Register is the maximum value the counter will count up or
+ * down to.
+ * @{
+ */
+#define XTTCPS_INTERVAL_VAL_MASK	0x0000FFFFU /**< 16-bit Interval value*/
+/* @} */
+
+/** @name Match Registers
+ * Definitions for Match registers, each timer counter has three match
+ * registers.
+ * @{
+ */
+#define XTTCPS_MATCH_MASK		0x0000FFFFU /**< 16-bit Match value */
+#define XTTCPS_NUM_MATCH_REG			 3U /**< Num of Match reg */
+/* @} */
+
+/** @name Interrupt Registers
+ * Following register bit mask is for all interrupt registers.
+ *
+ * @{
+ */
+#define XTTCPS_IXR_INTERVAL_MASK	0x00000001U  /**< Interval Interrupt */
+#define XTTCPS_IXR_MATCH_0_MASK		0x00000002U  /**< Match 1 Interrupt */
+#define XTTCPS_IXR_MATCH_1_MASK		0x00000004U  /**< Match 2 Interrupt */
+#define XTTCPS_IXR_MATCH_2_MASK		0x00000008U  /**< Match 3 Interrupt */
+#define XTTCPS_IXR_CNT_OVR_MASK		0x00000010U  /**< Counter Overflow */
+#define XTTCPS_IXR_ALL_MASK			0x0000001FU  /**< All valid Interrupts */
+/* @} */
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XTtcPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XTtcPs_ReadReg(BaseAddress, RegOffset) \
+    (Xil_In32((BaseAddress) + (u32)(RegOffset)))
+
+/****************************************************************************/
+/**
+*
+* Write the given Timer Counter register.
+*
+* @param	BaseAddress is the base address of the timer counter device.
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XTtcPs_WriteReg(XTtcPs BaseAddress, u32 RegOffset,
+*		u32 Data)
+*
+*****************************************************************************/
+#define XTtcPs_WriteReg(BaseAddress, RegOffset, Data) \
+    (Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data)))
+
+/****************************************************************************/
+/**
+*
+* Calculate a match register offset using the Match Register index.
+*
+* @param	MatchIndex is the 0-2 value of the match register
+*
+* @return	MATCH_N_OFFSET.
+*
+* @note		C-style signature:
+*		u32 XTtcPs_Match_N_Offset(u8 MatchIndex)
+*
+*****************************************************************************/
+#define XTtcPs_Match_N_Offset(MatchIndex) \
+		((u32)XTTCPS_MATCH_0_OFFSET + ((u32)(12U) * (u32)(MatchIndex)))
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+#ifdef __cplusplus
+}
+#endif
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_options.c
new file mode 100644
index 000000000..532b235c5
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_options.c
@@ -0,0 +1,243 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_options.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file contains functions to get or set option features for the device.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 1.01a nm     03/05/2012 Removed break statement after return to remove
+*                         compilation warnings.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/*
+ * Create the table of options which are processed to get/set the device
+ * options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+typedef struct {
+	u32 Option;
+	u32 Mask;
+	u32 Register;
+} OptionsMap;
+
+static OptionsMap TmrCtrOptionsTable[] = {
+	{XTTCPS_OPTION_EXTERNAL_CLK, XTTCPS_CLK_CNTRL_SRC_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_CLK_EDGE_NEG, XTTCPS_CLK_CNTRL_EXT_EDGE_MASK,
+	 XTTCPS_CLK_CNTRL_OFFSET},
+	{XTTCPS_OPTION_INTERVAL_MODE, XTTCPS_CNT_CNTRL_INT_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_DECREMENT, XTTCPS_CNT_CNTRL_DECR_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_MATCH_MODE, XTTCPS_CNT_CNTRL_MATCH_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_DISABLE, XTTCPS_CNT_CNTRL_EN_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+	{XTTCPS_OPTION_WAVE_POLARITY, XTTCPS_CNT_CNTRL_POL_WAVE_MASK,
+	 XTTCPS_CNT_CNTRL_OFFSET},
+};
+
+#define XTTCPS_NUM_TMRCTR_OPTIONS (sizeof(TmrCtrOptionsTable) / \
+				sizeof(OptionsMap))
+
+/*****************************************************************************/
+/**
+*
+* This function sets the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+* @param	Options contains the specified options to be set. This is a bit
+*		mask where a 1 means to turn the option on, and a 0 means to
+*		turn the option off. One or more bit values may be contained
+*		in the mask. See the bit definitions named XTTCPS_*_OPTION in
+*		the file xttcps.h.
+*
+* @return
+*		- XST_SUCCESS if options are successfully set.
+*		- XST_FAILURE if any of the options are unknown.
+*
+* @note		None
+*
+******************************************************************************/
+s32 XTtcPs_SetOptions(XTtcPs *InstancePtr, u32 Options)
+{
+	u32 CountReg;
+	u32 ClockReg;
+	u32 Index;
+	s32 Status = XST_SUCCESS;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	ClockReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CLK_CNTRL_OFFSET);
+	CountReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				    XTTCPS_CNT_CNTRL_OFFSET);
+
+	/*
+	 * Loop through the options table, turning the option on or off
+	 * depending on whether the bit is set in the incoming options flag.
+	 */
+	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		if(Status != (s32)XST_FAILURE) {
+			if ((Options & TmrCtrOptionsTable[Index].Option) != (u32)0) {
+
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Add option */
+				ClockReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Add option */
+				CountReg |= TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				Status = XST_FAILURE;
+				break;
+			}
+		}
+		else {
+			switch (TmrCtrOptionsTable[Index].Register) {
+
+			case XTTCPS_CLK_CNTRL_OFFSET:
+				/* Remove option*/
+				ClockReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			case XTTCPS_CNT_CNTRL_OFFSET:
+				/* Remove option*/
+				CountReg &= ~TmrCtrOptionsTable[Index].Mask;
+				break;
+
+			default:
+				Status = XST_FAILURE;
+				break;
+				}
+			}
+		}
+	}
+
+	/*
+	 * Now write the registers. Leave it to the upper layers to restart the
+	 * device.
+	 */
+	if (Status != (s32)XST_FAILURE ) {
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CLK_CNTRL_OFFSET, ClockReg);
+		XTtcPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XTTCPS_CNT_CNTRL_OFFSET, CountReg);
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the settings for the options for the TTC device.
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+* The return u32 contains the specified options that are set. This is a bit
+* mask where a '1' means the option is on, and a'0' means the option is off.
+* One or more bit values may be contained in the mask. See the bit definitions
+* named XTTCPS_*_OPTION in the file xttcps.h.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XTtcPs_GetOptions(XTtcPs *InstancePtr)
+{
+	u32 OptionsFlag = 0U;
+	u32 Register;
+	u32 Index;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+
+	/*
+	 * Loop through the options table to determine which options are set
+	 */
+	for (Index = 0U; Index < XTTCPS_NUM_TMRCTR_OPTIONS; Index++) {
+		/*
+		 * Get the control register to determine which options are
+		 * currently set.
+		 */
+		Register = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+					      TmrCtrOptionsTable[Index].
+					      Register);
+
+		if ((Register & TmrCtrOptionsTable[Index].Mask) != (u32)0) {
+			OptionsFlag |= TmrCtrOptionsTable[Index].Option;
+		}
+	}
+
+	return OptionsFlag;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c
new file mode 100644
index 000000000..4923df667
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_selftest.c
@@ -0,0 +1,109 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_selftest.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* This file contains the implementation of self test function for the
+* XTtcPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* Runs a self-test on the driver/device.
+*
+*
+* @param	InstancePtr is a pointer to the XTtcPs instance.
+*
+* @return
+*
+*	- XST_SUCCESS if successful
+*	- XST_FAILURE indicates a register did not read or write correctly
+*
+* @note		This test fails if it is not called right after initialization.
+*
+******************************************************************************/
+s32 XTtcPs_SelfTest(XTtcPs *InstancePtr)
+{
+	s32 Status;
+	u32 TempReg;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * All the TTC registers should be in their default state right now.
+	 */
+	TempReg = XTtcPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XTTCPS_CNT_CNTRL_OFFSET);
+	if (XTTCPS_CNT_CNTRL_RESET_VALUE != (u32)TempReg) {
+		Status = XST_FAILURE;
+	}
+	else {
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c
new file mode 100644
index 000000000..ef3c6ea6b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/ttcps_v3_1/src/xttcps_sinit.c
@@ -0,0 +1,98 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xttcps_sinit.c
+* @addtogroup ttcps_v3_0
+* @{
+*
+* The implementation of the XTtcPs driver's static initialization functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a drg/jz 01/21/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xttcps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/************************** Function Prototypes ******************************/
+
+/************************** Variable Definitions *****************************/
+extern XTtcPs_Config XTtcPs_ConfigTable[XPAR_XTTCPS_NUM_INSTANCES];
+
+/*****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. A table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the unique ID of the device
+*
+* @return
+*
+* A pointer to the configuration found or NULL if the specified device ID was
+* not found. See xttcps.h for the definition of XTtcPs_Config.
+*
+* @note		None.
+*
+******************************************************************************/
+XTtcPs_Config *XTtcPs_LookupConfig(u16 DeviceId)
+{
+	XTtcPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XTTCPS_NUM_INSTANCES; Index++) {
+		if (XTtcPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XTtcPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XTtcPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/Makefile
new file mode 100644
index 000000000..88b1e625c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner xuartps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling uartps"
+
+xuartps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: xuartps_includes
+
+xuartps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.c
new file mode 100644
index 000000000..a338d1f09
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.c
@@ -0,0 +1,644 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* This file contains the implementation of the interface functions for XUartPs
+* driver. Refer to the header file xuartps.h for more detailed information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	 Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ****************************/
+
+/* The following constant defines the amount of error that is allowed for
+ * a specified baud rate. This error is the difference between the actual
+ * baud rate that will be generated using the specified clock and the
+ * desired baud rate.
+ */
+#define XUARTPS_MAX_BAUD_ERROR_RATE		 3U	/* max % error allowed */
+
+/**************************** Type Definitions ******************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes *****************************/
+
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount);
+
+u32  XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+u32  XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+/****************************************************************************/
+/**
+*
+* Initializes a specific XUartPs instance such that it is ready to be used.
+* The data format of the device is setup for 8 data bits, 1 stop bit, and no
+* parity by default. The baud rate is set to a default value specified by
+* Config->DefaultBaudRate if set, otherwise it is set to 19.2K baud. The
+* receive FIFO threshold is set for 8 bytes. The default operating mode of the
+* driver is polled mode.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Config is a reference to a structure containing information
+*		about a specific XUartPs driver.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the address
+*		mapping from EffectiveAddr to the device physical base address
+*		unchanged once this function is invoked. Unexpected errors may
+*		occur if the address mapping changes after this function is
+*		called. If address translation is not used, pass in the physical
+*		address instead.
+*
+* @return
+*
+*		- XST_SUCCESS if initialization was successful
+*		- XST_UART_BAUD_ERROR if the baud rate is not possible because
+*		  the inputclock frequency is not divisible with an acceptable
+*		  amount of error
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 19,200 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+*   All interrupts are disabled.
+*
+*****************************************************************************/
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				   XUartPs_Config * Config, u32 EffectiveAddr)
+{
+	s32 Status;
+	u32 ModeRegister;
+	u32 BaudRate;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Config != NULL);
+
+	/* Setup the driver instance using passed in parameters */
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+	InstancePtr->Config.InputClockHz = Config->InputClockHz;
+	InstancePtr->Config.ModemPinsConnected = Config->ModemPinsConnected;
+
+	/* Initialize other instance data to default values */
+	InstancePtr->Handler = XUartPs_StubHandler;
+
+	InstancePtr->SendBuffer.NextBytePtr = NULL;
+	InstancePtr->SendBuffer.RemainingBytes = 0U;
+	InstancePtr->SendBuffer.RequestedBytes = 0U;
+
+	InstancePtr->ReceiveBuffer.NextBytePtr = NULL;
+	InstancePtr->ReceiveBuffer.RemainingBytes = 0U;
+	InstancePtr->ReceiveBuffer.RequestedBytes = 0U;
+
+	/* Initialize the platform data */
+	InstancePtr->Platform = XGetPlatform_Info();
+
+	InstancePtr->is_rxbs_error = 0U;
+
+	/* Flag that the driver instance is ready to use */
+	InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+	/*
+	 * Set the default baud rate here, can be changed prior to
+	 * starting the device
+	 */
+	BaudRate = (u32)XUARTPS_DFT_BAUDRATE;
+	Status = XUartPs_SetBaudRate(InstancePtr, BaudRate);
+	if (Status != (s32)XST_SUCCESS) {
+		InstancePtr->IsReady = 0U;
+	} else {
+
+		/*
+		 * Set up the default data format: 8 bit data, 1 stop bit, no
+		 * parity
+		 */
+		ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					  XUARTPS_MR_OFFSET);
+
+		/* Mask off what's already there */
+		ModeRegister &= (~((u32)XUARTPS_MR_CHARLEN_MASK |
+						 (u32)XUARTPS_MR_STOPMODE_MASK |
+						 (u32)XUARTPS_MR_PARITY_MASK));
+
+		/* Set the register value to the desired data format */
+		ModeRegister |=	((u32)XUARTPS_MR_CHARLEN_8_BIT |
+						 (u32)XUARTPS_MR_STOPMODE_1_BIT |
+						 (u32)XUARTPS_MR_PARITY_NONE);
+
+		/* Write the mode register out */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+				   ModeRegister);
+
+		/* Set the RX FIFO trigger at 8 data bytes. */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXWM_OFFSET, 0x08U);
+
+		/* Set the RX timeout to 1, which will be 4 character time */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_RXTOUT_OFFSET, 0x01U);
+
+		/* Disable all interrupts, polled mode is the default */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+				   XUARTPS_IXR_MASK);
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sends the specified buffer using the device in either
+* polled or interrupt driven mode. This function is non-blocking, if the device
+* is busy sending data, it will return and indicate zero bytes were sent.
+* Otherwise, it fills the TX FIFO as much as it can, and return the number of
+* bytes sent.
+*
+* In a polled mode, this function will only send as much data as TX FIFO can
+* buffer. The application may need to call it repeatedly to send the entire
+* buffer.
+*
+* In interrupt mode, this function will start sending the specified buffer,
+* then the interrupt handler will continue sending data until the entire
+* buffer has been sent. A callback function, as specified by the application,
+* will be called to indicate the completion of sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	BufferPtr is pointer to a buffer of data to be sent.
+* @param  	NumBytes contains the number of bytes to be sent. A value of
+*		zero will stop a previous send operation that is in progress
+*		in interrupt mode. Any data that was already put into the
+*		transmit FIFO will be sent.
+*
+* @return	The number of bytes actually sent.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called with
+* a value of zero to stop an operation that is already in progress.
+* 


+*
+*****************************************************************************/
+u32 XUartPs_Send(XUartPs *InstancePtr, u8 *BufferPtr,
+			   u32 NumBytes)
+{
+	u32 BytesSent;
+
+	/* Asserts validate the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable the UART transmit interrupts to allow this call to stop a
+	 * previous operation that may be interrupt driven.
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+					  (XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_TXFULL));
+
+	/* Setup the buffer parameters */
+	InstancePtr->SendBuffer.RequestedBytes = NumBytes;
+	InstancePtr->SendBuffer.RemainingBytes = NumBytes;
+	InstancePtr->SendBuffer.NextBytePtr = BufferPtr;
+
+	/*
+	 * Transmit interrupts will be enabled in XUartPs_SendBuffer(), after
+	 * filling the TX FIFO.
+	 */
+	BytesSent = XUartPs_SendBuffer(InstancePtr);
+
+	return BytesSent;
+}
+
+/****************************************************************************/
+/**
+*
+* This function attempts to receive a specified number of bytes of data
+* from the device and store it into the specified buffer. This function works
+* for both polled or interrupt driven modes. It is non-blocking.
+*
+* In a polled mode, this function will only receive the data already in the
+* RX FIFO. The application may need to call it repeatedly to receive the
+* entire buffer. Polled mode is the default mode of operation for the device.
+*
+* In interrupt mode, this function will start the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue receiving data
+* until the entire buffer has been received. A callback function, as specified
+* by the application, will be called to indicate the completion of the
+* receiving or error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BufferPtr is pointer to buffer for data to be received into
+* @param	NumBytes is the number of bytes to be received. A value of zero
+*		will stop a previous receive operation that is in progress in
+*		interrupt mode.
+*
+* @return	The number of bytes received.
+*
+* @note
+*
+* The number of bytes is not asserted so that this function may be called
+* with a value of zero to stop an operation that is already in progress.
+*
+*****************************************************************************/
+u32 XUartPs_Recv(XUartPs *InstancePtr,
+			  u8 *BufferPtr, u32 NumBytes)
+{
+	u32 ReceivedCount;
+	u32 ImrRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(BufferPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Disable all the interrupts.
+	 * This stops a previous operation that may be interrupt driven
+	 */
+	ImrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/* Setup the buffer parameters */
+	InstancePtr->ReceiveBuffer.RequestedBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.RemainingBytes = NumBytes;
+	InstancePtr->ReceiveBuffer.NextBytePtr = BufferPtr;
+
+	/* Receive the data from the device */
+	ReceivedCount = XUartPs_ReceiveBuffer(InstancePtr);
+
+	/* Restore the interrupt state */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+		ImrRegister);
+
+	return ReceivedCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function sends a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function for the XUartPs driver such that it may be called from a shell
+* function that sets up the buffer or from an interrupt handler.
+*
+* This function sends the specified buffer in either polled or interrupt
+* driven modes. This function is non-blocking.
+*
+* In a polled mode, this function only sends as much data as the TX FIFO
+* can buffer. The application may need to call it repeatedly to send the
+* entire buffer.
+*
+* In interrupt mode, this function starts the sending of the buffer, if not
+* the entire buffer has been sent, then the interrupt handler continues the
+* sending until the entire buffer has been sent. A callback function, as
+* specified by the application, will be called to indicate the completion of
+* sending.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes actually sent
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_SendBuffer(XUartPs *InstancePtr)
+{
+	u32 SentCount = 0U;
+	u32 ImrRegister;
+
+	/*
+	 * If the TX FIFO is full, send nothing.
+	 * Otherwise put bytes into the TX FIFO unil it is full, or all of the
+	 * data has been put into the FIFO.
+	 */
+	while ((!XUartPs_IsTransmitFull(InstancePtr->Config.BaseAddress)) &&
+		   (InstancePtr->SendBuffer.RemainingBytes > SentCount)) {
+
+		/* Fill the FIFO from the buffer */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_FIFO_OFFSET,
+				   ((u32)InstancePtr->SendBuffer.
+				   NextBytePtr[SentCount]));
+
+		/* Increment the send count. */
+		SentCount++;
+	}
+
+	/* Update the buffer to reflect the bytes that were sent from it */
+	InstancePtr->SendBuffer.NextBytePtr += SentCount;
+	InstancePtr->SendBuffer.RemainingBytes -= SentCount;
+
+	/*
+	 * If interrupts are enabled as indicated by the receive interrupt, then
+	 * enable the TX FIFO empty interrupt, so further action can be taken
+	 * for this sending.
+	 */
+	ImrRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_IMR_OFFSET);
+	if (((ImrRegister & XUARTPS_IXR_RXFULL) != (u32)0) ||
+		((ImrRegister & XUARTPS_IXR_RXEMPTY) != (u32)0)||
+		((ImrRegister & XUARTPS_IXR_RXOVR) != (u32)0)) {
+
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+					   XUARTPS_IER_OFFSET,
+					   ImrRegister | (u32)XUARTPS_IXR_TXEMPTY);
+	}
+
+	return SentCount;
+}
+
+/****************************************************************************/
+/*
+*
+* This function receives a buffer that has been previously specified by setting
+* up the instance variables of the instance. This function is an internal
+* function, and it may be called from a shell function that sets up the buffer
+* or from an interrupt handler.
+*
+* This function attempts to receive a specified number of bytes from the
+* device and store it into the specified buffer. This function works for
+* either polled or interrupt driven modes. It is non-blocking.
+*
+* In polled mode, this function only receives as much data as in the RX FIFO.
+* The application may need to call it repeatedly to receive the entire buffer.
+* Polled mode is the default mode for the driver.
+*
+* In interrupt mode, this function starts the receiving, if not the entire
+* buffer has been received, the interrupt handler will continue until the
+* entire buffer has been received. A callback function, as specified by the
+* application, will be called to indicate the completion of the receiving or
+* error conditions.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	The number of bytes received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr)
+{
+	u32 CsrRegister;
+	u32 ReceivedCount = 0U;
+	u32 ByteStatusValue, EventData;
+	u32 Event;
+
+	/*
+	 * Read the Channel Status Register to determine if there is any data in
+	 * the RX FIFO
+	 */
+	CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_SR_OFFSET);
+
+	/*
+	 * Loop until there is no more data in RX FIFO or the specified
+	 * number of bytes has been received
+	 */
+	while((ReceivedCount <= InstancePtr->ReceiveBuffer.RemainingBytes)&&
+		(((CsrRegister & XUARTPS_SR_RXEMPTY) == (u32)0))){
+
+		if (InstancePtr->is_rxbs_error) {
+			ByteStatusValue = XUartPs_ReadReg(
+						InstancePtr->Config.BaseAddress,
+						XUARTPS_RXBS_OFFSET);
+			if((ByteStatusValue & XUARTPS_RXBS_MASK)!= (u32)0) {
+				EventData = ByteStatusValue;
+				Event = XUARTPS_EVENT_PARE_FRAME_BRKE;
+				/*
+				 * Call the application handler to indicate that there is a receive
+				 * error or a break interrupt, if the application cares about the
+				 * error it call a function to get the last errors.
+				 */
+				InstancePtr->Handler(InstancePtr->CallBackRef,
+							Event, EventData);
+			}
+		}
+
+		InstancePtr->ReceiveBuffer.NextBytePtr[ReceivedCount] =
+			XUartPs_ReadReg(InstancePtr->Config.
+				  BaseAddress,
+				  XUARTPS_FIFO_OFFSET);
+
+		ReceivedCount++;
+
+		CsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+								XUARTPS_SR_OFFSET);
+	}
+	InstancePtr->is_rxbs_error = 0;
+	/*
+	 * Update the receive buffer to reflect the number of bytes just
+	 * received
+	 */
+	if(InstancePtr->ReceiveBuffer.NextBytePtr != NULL){
+		InstancePtr->ReceiveBuffer.NextBytePtr += ReceivedCount;
+	}
+	InstancePtr->ReceiveBuffer.RemainingBytes -= ReceivedCount;
+
+	return ReceivedCount;
+}
+
+/*****************************************************************************/
+/**
+*
+* Sets the baud rate for the device. Checks the input value for
+* validity and also verifies that the requested rate can be configured to
+* within the maximum error range specified by XUARTPS_MAX_BAUD_ERROR_RATE.
+* If the provided rate is not possible, the current setting is unchanged.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	BaudRate to be set
+*
+* @return
+*		- XST_SUCCESS if everything configured as expected
+*		- XST_UART_BAUD_ERROR if the requested rate is not available
+*		  because there was too much error
+*
+* @note		None.
+*
+*****************************************************************************/
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate)
+{
+	u32 IterBAUDDIV;	/* Iterator for available baud divisor values */
+	u32 BRGR_Value;		/* Calculated value for baud rate generator */
+	u32 CalcBaudRate;	/* Calculated baud rate */
+	u32 BaudError;		/* Diff between calculated and requested baud rate */
+	u32 Best_BRGR = 0U;	/* Best value for baud rate generator */
+	u8 Best_BAUDDIV = 0U;	/* Best value for baud divisor */
+	u32 Best_Error = 0xFFFFFFFFU;
+	u32 PercentError;
+	u32 ModeReg;
+	u32 InputClk;
+
+	/* Asserts validate the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid(BaudRate <= (u32)XUARTPS_MAX_RATE);
+	Xil_AssertNonvoid(BaudRate >= (u32)XUARTPS_MIN_RATE);
+
+	/*
+	 * Make sure the baud rate is not impossilby large.
+	 * Fastest possible baud rate is Input Clock / 2.
+	 */
+	if ((BaudRate * 2) > InstancePtr->Config.InputClockHz) {
+		return XST_UART_BAUD_ERROR;
+	}
+	/* Check whether the input clock is divided by 8 */
+	ModeReg = XUartPs_ReadReg( InstancePtr->Config.BaseAddress,
+				 XUARTPS_MR_OFFSET);
+
+	InputClk = InstancePtr->Config.InputClockHz;
+	if(ModeReg & XUARTPS_MR_CLKSEL) {
+		InputClk = InstancePtr->Config.InputClockHz / 8;
+	}
+
+	/*
+	 * Determine the Baud divider. It can be 4to 254.
+	 * Loop through all possible combinations
+	 */
+	for (IterBAUDDIV = 4; IterBAUDDIV < 255; IterBAUDDIV++) {
+
+		/* Calculate the value for BRGR register */
+		BRGR_Value = InputClk / (BaudRate * (IterBAUDDIV + 1));
+
+		/* Calculate the baud rate from the BRGR value */
+		CalcBaudRate = InputClk/ (BRGR_Value * (IterBAUDDIV + 1));
+
+		/* Avoid unsigned integer underflow */
+		if (BaudRate > CalcBaudRate) {
+			BaudError = BaudRate - CalcBaudRate;
+		}
+		else {
+			BaudError = CalcBaudRate - BaudRate;
+		}
+
+		/* Find the calculated baud rate closest to requested baud rate. */
+		if (Best_Error > BaudError) {
+
+			Best_BRGR = BRGR_Value;
+			Best_BAUDDIV = IterBAUDDIV;
+			Best_Error = BaudError;
+		}
+	}
+
+	/* Make sure the best error is not too large. */
+	PercentError = (Best_Error * 100) / BaudRate;
+	if (XUARTPS_MAX_BAUD_ERROR_RATE < PercentError) {
+		return XST_UART_BAUD_ERROR;
+	}
+
+	/* Disable TX and RX to avoid glitches when setting the baud rate. */
+	XUartPs_DisableUart(InstancePtr);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDGEN_OFFSET, Best_BRGR);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_BAUDDIV_OFFSET, Best_BAUDDIV);
+
+	/* RX and TX SW reset */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+				XUARTPS_CR_TXRST | XUARTPS_CR_RXRST);
+
+	/* Enable device */
+	XUartPs_EnableUart(InstancePtr);
+
+	InstancePtr->BaudRate = BaudRate;
+
+	return XST_SUCCESS;
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function is a stub handler that is the default handler such that if the
+* application has not set the handler when interrupts are enabled, this
+* function will be called.
+*
+* @param	CallBackRef is unused by this function.
+* @param	Event is unused by this function.
+* @param	ByteCount is unused by this function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void XUartPs_StubHandler(void *CallBackRef, u32 Event,
+				 u32 ByteCount)
+{
+	(void *) CallBackRef;
+	(void) Event;
+	(void) ByteCount;
+	/* Assert occurs always since this is a stub and should never be called */
+	Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h
new file mode 100644
index 000000000..6bd42b21c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps.h
@@ -0,0 +1,511 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps.h
+* @addtogroup uartps_v3_1
+* @{
+* @details
+*
+* This driver supports the following features:
+*
+* - Dynamic data format (baud rate, data bits, stop bits, parity)
+* - Polled mode
+* - Interrupt driven mode
+* - Transmit and receive FIFOs (32 byte FIFO depth)
+* - Access to the external modem control lines
+*
+* Initialization & Configuration
+*
+* The XUartPs_Config structure is used by the driver to configure itself.
+* Fields inside this structure are properties of XUartPs based on its hardware
+* build.
+*
+* To support multiple runtime loading and initialization strategies employed
+* by various operating systems, the driver instance can be initialized in the
+* following way:
+*
+*   - XUartPs_CfgInitialize(InstancePtr, CfgPtr, EffectiveAddr) - Uses a
+*	 configuration structure provided by the caller. If running in a system
+*	 with address translation, the parameter EffectiveAddr should be the
+* 	  virtual address.
+*
+* Baud Rate
+*
+* The UART has an internal baud rate generator, which furnishes the baud rate
+* clock for both the receiver and the transmitter. Ther input clock frequency
+* can be either the master clock or the master clock divided by 8, configured
+* through the mode register.
+*
+* Accompanied with the baud rate divider register, the baud rate is determined
+* by:
+* 
+*	baud_rate = input_clock / (bgen * (bdiv + 1)
+* 

+* where bgen is the value of the baud rate generator, and bdiv is the value of
+* baud rate divider.
+*
+* Interrupts
+*
+* The FIFOs are not flushed when the driver is initialized, but a function is
+* provided to allow the user to reset the FIFOs if desired.
+*
+* The driver defaults to no interrupts at initialization such that interrupts
+* must be enabled if desired. An interrupt is generated for one of the
+* following conditions.
+*
+* - A change in the modem signals
+* - Data in the receive FIFO for a configuable time without receiver activity
+* - A parity error
+* - A framing error
+* - An overrun error
+* - Transmit FIFO is full
+* - Transmit FIFO is empty
+* - Receive FIFO is full
+* - Receive FIFO is empty
+* - Data in the receive FIFO equal to the receive threshold
+*
+* The application can control which interrupts are enabled using the
+* XUartPs_SetInterruptMask() function.
+*
+* In order to use interrupts, it is necessary for the user to connect the
+* driver interrupt handler, XUartPs_InterruptHandler(), to the interrupt
+* system of the application. A separate handler should be provided by the
+* application to communicate with the interrupt system, and conduct
+* application specific interrupt handling. An application registers its own
+* handler through the XUartPs_SetHandler() function.
+*
+* Data Transfer
+*
+* The functions, XUartPs_Send() and XUartPs_Recv(), are provided in the
+* driver to allow data to be sent and received. They can be used in either
+* polled or interrupt mode.
+*
+* @note
+*
+* The default configuration for the UART after initialization is:
+*
+* - 9,600 bps or XPAR_DFT_BAUDRATE if defined
+* - 8 data bits
+* - 1 stop bit
+* - no parity
+* - FIFO's are enabled with a receive threshold of 8 bytes
+* - The RX timeout is enabled with a timeout of 1 (4 char times)
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a	drg/jz 01/12/10 First Release
+* 1.00a sdm    09/27/11 Fixed compiler warnings and also a bug
+*		        in XUartPs_SetFlowDelay where the value was not
+*			being written to the register.
+* 1.01a sdm    12/20/11 Removed the InputClockHz parameter from the XUartPs
+*			instance structure and the driver is updated to use
+*			InputClockHz parameter from the XUartPs_Config config
+*			structure.
+*			Added a parameter to XUartPs_Config structure which
+*			specifies whether the user has selected Modem pins
+*			to be connected to MIO or FMIO.
+*			Added the tcl file to generate the xparameters.h
+* 1.02a sg     05/16/12	Changed XUARTPS_RXWM_MASK to 0x3F for CR 652540 fix.
+* 1.03a sg     07/16/12 Updated XUARTPS_FORMAT_7_BITS and XUARTPS_FORMAT_6_BITS
+*			with the correct values for CR 666724
+* 			Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the name of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added API for uart reset and related
+*			constant definitions.
+* 2.0   hk      03/07/14 Version number revised.
+* 2.1   hk     04/16/14 Change XUARTPS_MAX_RATE to 921600. CR# 780625.
+* 2.2   hk     06/23/14 SW reset of RX and TX should be done when changing
+*                       baud rate. CR# 804281.
+* 3.0   vm     12/09/14 Modified source code according to misrac guideline.
+*			Support for Zynq Ultrascale Mp added.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes. Also added
+*						platform variable in driver instance structure.
+* 3.1   adk   14/03/16  Include interrupt examples in the peripheral test when
+*			uart is connected to a valid interrupt controller CR#946803.
+*
+* 

+*
+*****************************************************************************/
+
+#ifndef XUARTPS_H		/* prevent circular inclusions */
+#define XUARTPS_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files ********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xuartps_hw.h"
+#include "xplatform_info.h"
+
+/************************** Constant Definitions ****************************/
+
+/*
+ * The following constants indicate the max and min baud rates and these
+ * numbers are based only on the testing that has been done. The hardware
+ * is capable of other baud rates.
+ */
+#define XUARTPS_MAX_RATE	 921600U
+#define XUARTPS_MIN_RATE	 110U
+
+#define XUARTPS_DFT_BAUDRATE  115200U   /* Default baud rate */
+
+/** @name Configuration options
+ * @{
+ */
+/**
+ * These constants specify the options that may be set or retrieved
+ * with the driver, each is a unique bit mask such that multiple options
+ * may be specified.  These constants indicate the available options
+ * in active state.
+ *
+ */
+
+#define XUARTPS_OPTION_SET_BREAK	0x0080U /**< Starts break transmission */
+#define XUARTPS_OPTION_STOP_BREAK	0x0040U /**< Stops break transmission */
+#define XUARTPS_OPTION_RESET_TMOUT	0x0020U /**< Reset the receive timeout */
+#define XUARTPS_OPTION_RESET_TX		0x0010U /**< Reset the transmitter */
+#define XUARTPS_OPTION_RESET_RX		0x0008U /**< Reset the receiver */
+#define XUARTPS_OPTION_ASSERT_RTS	0x0004U /**< Assert the RTS bit */
+#define XUARTPS_OPTION_ASSERT_DTR	0x0002U /**< Assert the DTR bit */
+#define XUARTPS_OPTION_SET_FCM		0x0001U /**< Turn on flow control mode */
+/*@}*/
+
+
+/** @name Channel Operational Mode
+ *
+ * The UART can operate in one of four modes: Normal, Local Loopback, Remote
+ * Loopback, or automatic echo.
+ *
+ * @{
+ */
+
+#define XUARTPS_OPER_MODE_NORMAL		(u8)0x00U	/**< Normal Mode */
+#define XUARTPS_OPER_MODE_AUTO_ECHO		(u8)0x01U	/**< Auto Echo Mode */
+#define XUARTPS_OPER_MODE_LOCAL_LOOP	(u8)0x02U	/**< Local Loopback Mode */
+#define XUARTPS_OPER_MODE_REMOTE_LOOP	(u8)0x03U	/**< Remote Loopback Mode */
+
+/* @} */
+
+/** @name Data format values
+ *
+ * These constants specify the data format that the driver supports.
+ * The data format includes the number of data bits, the number of stop
+ * bits and parity.
+ *
+ * @{
+ */
+#define XUARTPS_FORMAT_8_BITS		0U /**< 8 data bits */
+#define XUARTPS_FORMAT_7_BITS		2U /**< 7 data bits */
+#define XUARTPS_FORMAT_6_BITS		3U /**< 6 data bits */
+
+#define XUARTPS_FORMAT_NO_PARITY	4U /**< No parity */
+#define XUARTPS_FORMAT_MARK_PARITY	3U /**< Mark parity */
+#define XUARTPS_FORMAT_SPACE_PARITY	2U /**< parity */
+#define XUARTPS_FORMAT_ODD_PARITY	1U /**< Odd parity */
+#define XUARTPS_FORMAT_EVEN_PARITY	0U /**< Even parity */
+
+#define XUARTPS_FORMAT_2_STOP_BIT	2U /**< 2 stop bits */
+#define XUARTPS_FORMAT_1_5_STOP_BIT	1U /**< 1.5 stop bits */
+#define XUARTPS_FORMAT_1_STOP_BIT	0U /**< 1 stop bit */
+/*@}*/
+
+/** @name Callback events
+ *
+ * These constants specify the handler events that an application can handle
+ * using its specific handler function. Note that these constants are not bit
+ * mask, so only one event can be passed to an application at a time.
+ *
+ * @{
+ */
+#define XUARTPS_EVENT_RECV_DATA			1U /**< Data receiving done */
+#define XUARTPS_EVENT_RECV_TOUT			2U /**< A receive timeout occurred */
+#define XUARTPS_EVENT_SENT_DATA			3U /**< Data transmission done */
+#define XUARTPS_EVENT_RECV_ERROR		4U /**< A receive error detected */
+#define XUARTPS_EVENT_MODEM				5U /**< Modem status changed */
+#define XUARTPS_EVENT_PARE_FRAME_BRKE	6U /**< A receive parity, frame, break
+											 *	error detected */
+#define XUARTPS_EVENT_RECV_ORERR		7U /**< A receive overrun error detected */
+/*@}*/
+
+
+/**************************** Type Definitions ******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;	 /**< Unique ID  of device */
+	u32 BaseAddress; /**< Base address of device (IPIF) */
+	u32 InputClockHz;/**< Input clock frequency */
+	s32 ModemPinsConnected; /** Specifies whether modem pins are connected
+				 *  to MIO or FMIO */
+} XUartPs_Config;
+
+/* Keep track of state information about a data buffer in the interrupt mode. */
+typedef struct {
+	u8 *NextBytePtr;
+	u32 RequestedBytes;
+	u32 RemainingBytes;
+} XUartPsBuffer;
+
+/**
+ * Keep track of data format setting of a device.
+ */
+typedef struct {
+	u32 BaudRate;	/**< In bps, ie 1200 */
+	u32 DataBits;	/**< Number of data bits */
+	u32 Parity;		/**< Parity */
+	u8 StopBits;	/**< Number of stop bits */
+} XUartPsFormat;
+
+/******************************************************************************/
+/**
+ * This data type defines a handler that an application defines to communicate
+ * with interrupt system to retrieve state information about an application.
+ *
+ * @param	CallBackRef is a callback reference passed in by the upper layer
+ *		when setting the handler, and is passed back to the upper layer
+ *		when the handler is called. It is used to find the device driver
+ *		instance.
+ * @param	Event contains one of the event constants indicating events that
+ *		have occurred.
+ * @param	EventData contains the number of bytes sent or received at the
+ *		time of the call for send and receive events and contains the
+ *		modem status for modem events.
+ *
+ ******************************************************************************/
+typedef void (*XUartPs_Handler) (void *CallBackRef, u32 Event,
+				  u32 EventData);
+
+/**
+ * The XUartPs driver instance data structure. A pointer to an instance data
+ * structure is passed around by functions to refer to a specific driver
+ * instance.
+ */
+typedef struct {
+	XUartPs_Config Config;	/* Configuration data structure */
+	u32 InputClockHz;	/* Input clock frequency */
+	u32 IsReady;		/* Device is initialized and ready */
+	u32 BaudRate;		/* Current baud rate */
+
+	XUartPsBuffer SendBuffer;
+	XUartPsBuffer ReceiveBuffer;
+
+	XUartPs_Handler Handler;
+	void *CallBackRef;	/* Callback reference for event handler */
+	u32 Platform;
+	u8 is_rxbs_error;
+} XUartPs;
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/****************************************************************************/
+/**
+* Get the UART Channel Status Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u16 XUartPs_GetChannelStatus(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetChannelStatus(InstancePtr)   \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET)
+
+/****************************************************************************/
+/**
+* Get the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_GetControl(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_GetModeControl(InstancePtr)  \
+	Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET)
+
+/****************************************************************************/
+/**
+* Set the UART Mode Control Register.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*	void XUartPs_SetModeControl(XUartPs *InstancePtr, u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_SetModeControl(InstancePtr, RegisterValue) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_CR_OFFSET, \
+			(u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Enable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_EnableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_EnableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  ((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_EN | (u32)XUARTPS_CR_TX_EN)))
+
+/****************************************************************************/
+/**
+* Disable the transmitter and receiver of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_DisableUart(XUartPs *InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_DisableUart(InstancePtr) \
+   Xil_Out32(((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET), \
+	  (((Xil_In32((InstancePtr)->Config.BaseAddress + (u32)XUARTPS_CR_OFFSET)) & \
+	  (u32)(~XUARTPS_CR_EN_DIS_MASK)) | ((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS)))
+
+/****************************************************************************/
+/**
+* Determine if the transmitter FIFO is empty.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if a byte can be sent
+*		- FALSE if the Transmitter Fifo is not empty
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitEmpty(XUartPs InstancePtr)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitEmpty(InstancePtr)				\
+	((Xil_In32(((InstancePtr)->Config.BaseAddress) + (u32)XUARTPS_SR_OFFSET) & \
+	 (u32)XUARTPS_SR_TXEMPTY) == (u32)XUARTPS_SR_TXEMPTY)
+
+
+/************************** Function Prototypes *****************************/
+
+/* Static lookup function implemented in xuartps_sinit.c */
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId);
+
+/* Interface functions implemented in xuartps.c */
+s32 XUartPs_CfgInitialize(XUartPs *InstancePtr,
+				  XUartPs_Config * Config, u32 EffectiveAddr);
+
+u32 XUartPs_Send(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+u32 XUartPs_Recv(XUartPs *InstancePtr,u8 *BufferPtr,
+			   u32 NumBytes);
+
+s32 XUartPs_SetBaudRate(XUartPs *InstancePtr, u32 BaudRate);
+
+/* Options functions in xuartps_options.c */
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options);
+
+u16 XUartPs_GetOptions(XUartPs *InstancePtr);
+
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel);
+
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr);
+
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr);
+
+u32 XUartPs_IsSending(XUartPs *InstancePtr);
+
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr);
+
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode);
+
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr);
+
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue);
+
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr);
+
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout);
+
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr);
+
+/* interrupt functions in xuartps_intr.c */
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr);
+
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask);
+
+void XUartPs_InterruptHandler(XUartPs *InstancePtr);
+
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+			 void *CallBackRef);
+
+/* self-test functions in xuartps_selftest.c */
+s32 XUartPs_SelfTest(XUartPs *InstancePtr);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c
new file mode 100644
index 000000000..94aaf5b2e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_g.c
@@ -0,0 +1,63 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xuartps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XUartPs_Config XUartPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_UART_0_DEVICE_ID,
+		XPAR_PSU_UART_0_BASEADDR,
+		XPAR_PSU_UART_0_UART_CLK_FREQ_HZ,
+		XPAR_PSU_UART_0_HAS_MODEM
+	},
+	{
+		XPAR_PSU_UART_1_DEVICE_ID,
+		XPAR_PSU_UART_1_BASEADDR,
+		XPAR_PSU_UART_1_UART_CLK_FREQ_HZ,
+		XPAR_PSU_UART_1_HAS_MODEM
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.c
new file mode 100644
index 000000000..299dd35ae
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.c
@@ -0,0 +1,180 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_hw.c
+* @addtogroup uartps_v3_1
+* @{
+*
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.05a hk     08/22/13 Added reset function
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+#include "xuartps_hw.h"
+
+/************************** Constant Definitions ****************************/
+
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+/****************************************************************************/
+/**
+*
+* This function sends one byte using the device. This function operates in
+* polled mode and blocks until the data has been put into the TX FIFO register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	Data contains the byte to be sent.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SendByte(u32 BaseAddress, u8 Data)
+{
+	/* Wait until there is space in TX FIFO */
+	while (XUartPs_IsTransmitFull(BaseAddress)) {
+		;
+	}
+
+	/* Write the byte into the TX FIFO */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_FIFO_OFFSET, (u32)Data);
+}
+
+/****************************************************************************/
+/**
+*
+* This function receives a byte from the device. It operates in polled mode
+* and blocks until a byte has received.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	The data byte received.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_RecvByte(u32 BaseAddress)
+{
+	u32 RecievedByte;
+	/* Wait until there is data */
+	while (!XUartPs_IsReceiveData(BaseAddress)) {
+		;
+	}
+	RecievedByte = XUartPs_ReadReg(BaseAddress, XUARTPS_FIFO_OFFSET);
+	/* Return the byte received */
+	return (u8)RecievedByte;
+}
+
+/****************************************************************************/
+/**
+*
+* This function resets UART
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_ResetHw(u32 BaseAddress)
+{
+
+	/* Disable interrupts */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_IDR_OFFSET, XUARTPS_IXR_MASK);
+
+	/* Disable receive and transmit */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS));
+
+	/*
+	 * Software reset of receive and transmit
+	 * This clears the FIFO.
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_TXRST | (u32)XUARTPS_CR_RXRST));
+
+	/* Clear status flags - SW reset wont clear sticky flags. */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_ISR_OFFSET, XUARTPS_IXR_MASK);
+
+	/*
+	 * Mode register reset value : All zeroes
+	 * Normal mode, even parity, 1 stop bit
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_MR_OFFSET,
+				XUARTPS_MR_CHMODE_NORM);
+
+	/* Rx and TX trigger register reset values */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXWM_OFFSET,
+				XUARTPS_RXWM_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_TXWM_OFFSET,
+				XUARTPS_TXWM_RESET_VAL);
+
+	/* Rx timeout disabled by default */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_RXTOUT_OFFSET,
+				XUARTPS_RXTOUT_DISABLE);
+
+	/* Baud rate generator and dividor reset values */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDGEN_OFFSET,
+				XUARTPS_BAUDGEN_RESET_VAL);
+	XUartPs_WriteReg(BaseAddress, XUARTPS_BAUDDIV_OFFSET,
+				XUARTPS_BAUDDIV_RESET_VAL);
+
+	/*
+	 * Control register reset value -
+	 * RX and TX are disable by default
+	 */
+	XUartPs_WriteReg(BaseAddress, XUARTPS_CR_OFFSET,
+				((u32)XUARTPS_CR_RX_DIS | (u32)XUARTPS_CR_TX_DIS |
+						(u32)XUARTPS_CR_STOPBRK));
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.h
new file mode 100644
index 000000000..9f5f0b700
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_hw.h
@@ -0,0 +1,449 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xuartps_hw.h
+* @addtogroup uartps_v3_1
+* @{
+*
+* This header file contains the hardware interface of an XUartPs device.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00	drg/jz 01/12/10 First Release
+* 1.03a sg     09/04/12 Added defines for XUARTPS_IXR_TOVR,  XUARTPS_IXR_TNFUL
+*			and XUARTPS_IXR_TTRIG.
+*			Modified the names of these defines
+*			XUARTPS_MEDEMSR_DCDX to XUARTPS_MODEMSR_DDCD
+*			XUARTPS_MEDEMSR_RIX to XUARTPS_MODEMSR_TERI
+*			XUARTPS_MEDEMSR_DSRX to XUARTPS_MODEMSR_DDSR
+*			XUARTPS_MEDEMSR_CTSX to XUARTPS_MODEMSR_DCTS
+* 1.05a hk     08/22/13 Added prototype for uart reset and related
+*			constant definitions.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+*
+* 

+*
+******************************************************************************/
+#ifndef XUARTPS_HW_H		/* prevent circular inclusions */
+#define XUARTPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ *
+ * Register offsets for the UART.
+ * @{
+ */
+#define XUARTPS_CR_OFFSET		0x0000U  /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET		0x0004U  /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET		0x0008U  /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET		0x000CU  /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET		0x0010U  /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET		0x0014U  /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET	0x0018U  /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET	0x001CU  /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET		0x0020U  /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET	0x0024U  /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET	0x0028U  /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET		0x002CU  /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET		0x0030U  /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET	0x0034U  /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET	0x0038U  /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET		0x0044U  /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET		0x0048U  /**< RX FIFO Byte Status [11:0] */
+/* @} */
+
+/** @name Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definition
+ */
+
+#define XUARTPS_CR_STOPBRK	0x00000100U  /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK	0x00000080U  /**< Set break */
+#define XUARTPS_CR_TORST	0x00000040U  /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS	0x00000020U  /**< TX disabled. */
+#define XUARTPS_CR_TX_EN	0x00000010U  /**< TX enabled */
+#define XUARTPS_CR_RX_DIS	0x00000008U  /**< RX disabled. */
+#define XUARTPS_CR_RX_EN	0x00000004U  /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK	0x0000003CU  /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST	0x00000002U  /**< TX logic reset */
+#define XUARTPS_CR_RXRST	0x00000001U  /**< RX logic reset */
+/* @}*/
+
+
+/** @name Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definition
+ * @{
+ */
+#define XUARTPS_MR_CCLK				0x00000400U /**< Input clock selection */
+#define XUARTPS_MR_CHMODE_R_LOOP	0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP	0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO		0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM		0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT				8U  /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK		0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT	0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT	0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT			6U  /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK	0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE		0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK		0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE		0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD		0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN		0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT				3U  /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK		0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT	0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT	0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT	0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT			1U  /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK		0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL			0x00000001U /**< Input clock selection */
+/* @} */
+
+
+/** @name Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enbables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ *
+ * @{
+ */
+#define XUARTPS_IXR_RBRK	0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR	0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL	0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG	0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS		0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT	0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 	0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING	0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_OVER	0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 	0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY	0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL 	0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY	0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXOVR  	0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK	0x00003FFFU /**< Valid bit mask */
+/* @} */
+
+
+/** @name Baud Rate Generator Register
+ *
+ * The baud rate generator control register (BRGR) is a 16 bit register that
+ * controls the receiver bit sample clock and baud rate.
+ * Valid values are 1 - 65535.
+ *
+ * Bit Sample Rate = CCLK / BRGR, where the CCLK is selected by the MR_CCLK bit
+ * in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDGEN_DISABLE		0x00000000U /**< Disable clock */
+#define XUARTPS_BAUDGEN_MASK		0x0000FFFFU /**< Valid bits mask */
+#define XUARTPS_BAUDGEN_RESET_VAL	0x0000028BU /**< Reset value */
+
+/** @name Baud Divisor Rate register
+ *
+ * The baud rate divider register (BDIV) controls how much the bit sample
+ * rate is divided by. It sets the baud rate.
+ * Valid values are 0x04 to 0xFF. Writing a value less than 4 will be ignored.
+ *
+ * Baud rate = CCLK / ((BAUDDIV + 1) x BRGR), where the CCLK is selected by
+ * the MR_CCLK bit in the MR register.
+ * @{
+ */
+#define XUARTPS_BAUDDIV_MASK        0x000000FFU	/**< 8 bit baud divider mask */
+#define XUARTPS_BAUDDIV_RESET_VAL   0x0000000FU	/**< Reset value */
+/* @} */
+
+
+/** @name Receiver Timeout Register
+ *
+ * Use the receiver timeout register (RTR) to detect an idle condition on
+ * the receiver data line.
+ *
+ * @{
+ */
+#define XUARTPS_RXTOUT_DISABLE		0x00000000U  /**< Disable time out */
+#define XUARTPS_RXTOUT_MASK			0x000000FFU  /**< Valid bits mask */
+
+/** @name Receiver FIFO Trigger Level Register
+ *
+ * Use the Receiver FIFO Trigger Level Register (RTRIG) to set the value at
+ * which the RX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_RXWM_DISABLE	0x00000000U  /**< Disable RX trigger interrupt */
+#define XUARTPS_RXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_RXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Transmit FIFO Trigger Level Register
+ *
+ * Use the Transmit FIFO Trigger Level Register (TTRIG) to set the value at
+ * which the TX FIFO triggers an interrupt event.
+ * @{
+ */
+
+#define XUARTPS_TXWM_MASK		0x0000003FU  /**< Valid bits mask */
+#define XUARTPS_TXWM_RESET_VAL	0x00000020U  /**< Reset value */
+/* @} */
+
+/** @name Modem Control Register
+ *
+ * This register (MODEMCR) controls the interface with the modem or data set,
+ * or a peripheral device emulating a modem.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMCR_FCM	0x00000010U  /**< Flow control mode */
+#define XUARTPS_MODEMCR_RTS	0x00000002U  /**< Request to send */
+#define XUARTPS_MODEMCR_DTR	0x00000001U  /**< Data terminal ready */
+/* @} */
+
+/** @name Modem Status Register
+ *
+ * This register (MODEMSR) indicates the current state of the control lines
+ * from a modem, or another peripheral device, to the CPU. In addition, four
+ * bits of the modem status register provide change information. These bits
+ * are set to a logic 1 whenever a control input from the modem changes state.
+ *
+ * Note: Whenever the DCTS, DDSR, TERI, or DDCD bit is set to logic 1, a modem
+ * status interrupt is generated and this is reflected in the modem status
+ * register.
+ *
+ * @{
+ */
+#define XUARTPS_MODEMSR_FCMS	0x00000100U  /**< Flow control mode (FCMS) */
+#define XUARTPS_MODEMSR_DCD		0x00000080U  /**< Complement of DCD input */
+#define XUARTPS_MODEMSR_RI		0x00000040U  /**< Complement of RI input */
+#define XUARTPS_MODEMSR_DSR		0x00000020U  /**< Complement of DSR input */
+#define XUARTPS_MODEMSR_CTS		0x00000010U  /**< Complement of CTS input */
+#define XUARTPS_MODEMSR_DDCD	0x00000008U  /**< Delta DCD indicator */
+#define XUARTPS_MODEMSR_TERI  0x00000004U  /**< Trailing Edge Ring Indicator */
+#define XUARTPS_MODEMSR_DDSR	0x00000002U  /**< Change of DSR */
+#define XUARTPS_MODEMSR_DCTS	0x00000001U  /**< Change of CTS */
+/* @} */
+
+/** @name Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ *
+ * @{
+ */
+#define XUARTPS_SR_TNFUL	0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG	0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL	0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE	0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE	0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL	0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY	0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL	0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY	0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RXOVR	0x00000001U /**< RX FIFO fill over trigger */
+/* @} */
+
+/** @name Flow Delay Register
+ *
+ * Operation of the flow delay register (FLOWDEL) is very similar to the
+ * receive FIFO trigger register. An internal trigger signal activates when the
+ * FIFO is filled to the level set by this register. This trigger will not
+ * cause an interrupt, although it can be read through the channel status
+ * register. In hardware flow control mode, RTS is deactivated when the trigger
+ * becomes active. RTS only resets when the FIFO level is four less than the
+ * level of the flow delay trigger and the flow delay trigger is not activated.
+ * A value less than 4 disables the flow delay.
+ * @{
+ */
+#define XUARTPS_FLOWDEL_MASK	XUARTPS_RXWM_MASK	/**< Valid bit mask */
+/* @} */
+
+/** @name Receiver FIFO Byte Status Register
+ *
+ * The Receiver FIFO Status register is used to have a continuous
+ * monitoring of the raw unmasked byte status information. The register
+ * contains frame, parity and break status information for the top
+ * four bytes in the RX FIFO.
+ *
+ * Receiver FIFO Byte Status Register Bit Definition
+ * @{
+ */
+#define XUARTPS_RXBS_BYTE3_BRKE		0x00000800U /**< Byte3 Break Error */
+#define XUARTPS_RXBS_BYTE3_FRME		0x00000400U /**< Byte3 Frame Error */
+#define XUARTPS_RXBS_BYTE3_PARE		0x00000200U /**< Byte3 Parity Error */
+#define XUARTPS_RXBS_BYTE2_BRKE		0x00000100U /**< Byte2 Break Error */
+#define XUARTPS_RXBS_BYTE2_FRME		0x00000080U /**< Byte2 Frame Error */
+#define XUARTPS_RXBS_BYTE2_PARE		0x00000040U /**< Byte2 Parity Error */
+#define XUARTPS_RXBS_BYTE1_BRKE		0x00000020U /**< Byte1 Break Error */
+#define XUARTPS_RXBS_BYTE1_FRME		0x00000010U /**< Byte1 Frame Error */
+#define XUARTPS_RXBS_BYTE1_PARE		0x00000008U /**< Byte1 Parity Error */
+#define XUARTPS_RXBS_BYTE0_BRKE		0x00000004U /**< Byte0 Break Error */
+#define XUARTPS_RXBS_BYTE0_FRME		0x00000002U /**< Byte0 Frame Error */
+#define XUARTPS_RXBS_BYTE0_PARE		0x00000001U /**< Byte0 Parity Error */
+#define XUARTPS_RXBS_MASK		0x00000007U /**< 3 bit RX byte status mask */
+/* @} */
+
+
+/*
+ * Defines for backwards compatabilty, will be removed
+ * in the next version of the driver
+ */
+#define XUARTPS_MEDEMSR_DCDX  XUARTPS_MODEMSR_DDCD
+#define XUARTPS_MEDEMSR_RIX   XUARTPS_MODEMSR_TERI
+#define XUARTPS_MEDEMSR_DSRX  XUARTPS_MODEMSR_DDSR
+#define	XUARTPS_MEDEMSR_CTSX  XUARTPS_MODEMSR_DCTS
+
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+* Read a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+*
+* @return	The value read from the register.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_ReadReg(u32 BaseAddress, int RegOffset)
+*
+******************************************************************************/
+#define XUartPs_ReadReg(BaseAddress, RegOffset) \
+	Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/***************************************************************************/
+/**
+* Write a UART register.
+*
+* @param	BaseAddress contains the base address of the device.
+* @param	RegOffset contains the offset from the base address of the
+*		device.
+* @param	RegisterValue is the value to be written to the register.
+*
+* @return	None.
+*
+* @note		C-Style signature:
+*		void XUartPs_WriteReg(u32 BaseAddress, int RegOffset,
+*						   u16 RegisterValue)
+*
+******************************************************************************/
+#define XUartPs_WriteReg(BaseAddress, RegOffset, RegisterValue) \
+	Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
+
+/****************************************************************************/
+/**
+* Determine if there is receive data in the receiver and/or FIFO.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if there is receive data, FALSE otherwise.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsReceiveData(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsReceiveData(BaseAddress)			 \
+	!((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	(u32)XUARTPS_SR_RXEMPTY) == (u32)XUARTPS_SR_RXEMPTY)
+
+/****************************************************************************/
+/**
+* Determine if a byte of data can be sent with the transmitter.
+*
+* @param	BaseAddress contains the base address of the device.
+*
+* @return	TRUE if the TX FIFO is full, FALSE if a byte can be put in the
+*		FIFO.
+*
+* @note		C-Style signature:
+*		u32 XUartPs_IsTransmitFull(u32 BaseAddress)
+*
+******************************************************************************/
+#define XUartPs_IsTransmitFull(BaseAddress)			 \
+	((Xil_In32((BaseAddress) + XUARTPS_SR_OFFSET) & 	\
+	 (u32)XUARTPS_SR_TXFULL) == (u32)XUARTPS_SR_TXFULL)
+
+/************************** Function Prototypes ******************************/
+
+void XUartPs_SendByte(u32 BaseAddress, u8 Data);
+
+u8 XUartPs_RecvByte(u32 BaseAddress);
+
+void XUartPs_ResetHw(u32 BaseAddress);
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c
new file mode 100644
index 000000000..849cb48db
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_intr.c
@@ -0,0 +1,450 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_intr.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* This file contains the functions for interrupt handling
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 3.1	kvn    04/10/15 Modified code for latest RTL changes.
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Function Prototypes *****************************/
+
+static void ReceiveDataHandler(XUartPs *InstancePtr);
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus);
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr);
+static void ModemHandler(XUartPs *InstancePtr);
+
+
+/* Internal function prototypes implemented in xuartps.c */
+extern u32 XUartPs_ReceiveBuffer(XUartPs *InstancePtr);
+extern u32 XUartPs_SendBuffer(XUartPs *InstancePtr);
+
+/************************** Variable Definitions ****************************/
+
+typedef void (*Handler)(XUartPs *InstancePtr);
+
+/****************************************************************************/
+/**
+*
+* This function gets the interrupt mask
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		The current interrupt mask. The mask indicates which interupts
+*		are enabled.
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_GetInterruptMask(XUartPs *InstancePtr)
+{
+	/* Assert validates the input argument */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	/* Read the Interrupt Mask register */
+	return (XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XUARTPS_IMR_OFFSET));
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the interrupt mask.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	Mask contains the interrupts to be enabled or disabled.
+*		A '1' enables an interupt, and a '0' disables.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetInterruptMask(XUartPs *InstancePtr, u32 Mask)
+{
+	u32 TempMask = Mask;
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	TempMask &= (u32)XUARTPS_IXR_MASK;
+
+	/* Write the mask to the IER Register */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IER_OFFSET, TempMask);
+
+	/* Write the inverse of the Mask to the IDR register */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+		 XUARTPS_IDR_OFFSET, (~TempMask));
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the handler that will be called when an event (interrupt)
+* occurs that needs application's attention.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	FuncPtr is the pointer to the callback function.
+* @param	CallBackRef is the upper layer callback reference passed back
+*		when the callback function is invoked.
+*
+* @return	None.
+*
+* @note
+*
+* There is no assert on the CallBackRef since the driver doesn't know what it
+* is (nor should it)
+*
+*****************************************************************************/
+void XUartPs_SetHandler(XUartPs *InstancePtr, XUartPs_Handler FuncPtr,
+		 void *CallBackRef)
+{
+	/*
+	 * Asserts validate the input arguments
+	 * CallBackRef not checked, no way to know what is valid
+	 */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FuncPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	InstancePtr->Handler = FuncPtr;
+	InstancePtr->CallBackRef = CallBackRef;
+}
+
+/****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the driver.
+* It must be connected to an interrupt system by the application such that it
+* can be called when an interrupt occurs.
+*
+* @param	InstancePtr contains a pointer to the driver instance
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XUartPs_InterruptHandler(XUartPs *InstancePtr)
+{
+	u32 IsrStatus;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the interrupt ID register to determine which
+	 * interrupt is active
+	 */
+	IsrStatus = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+
+	IsrStatus &= XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_ISR_OFFSET);
+
+	/* Dispatch an appropriate handler. */
+	if((IsrStatus & ((u32)XUARTPS_IXR_RXOVR | (u32)XUARTPS_IXR_RXEMPTY |
+			(u32)XUARTPS_IXR_RXFULL)) != (u32)0) {
+		/* Received data interrupt */
+		ReceiveDataHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL))
+									 != (u32)0) {
+		/* Transmit data interrupt */
+		SendDataHandler(InstancePtr, IsrStatus);
+	}
+
+	/* XUARTPS_IXR_RBRK is applicable only for Zynq Ultrascale+ MP */
+	if ((IsrStatus & ((u32)XUARTPS_IXR_OVER | (u32)XUARTPS_IXR_FRAMING |
+			(u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK)) != (u32)0) {
+		/* Received Error Status interrupt */
+		ReceiveErrorHandler(InstancePtr, IsrStatus);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_TOUT)) != (u32)0) {
+		/* Received Timeout interrupt */
+		ReceiveTimeoutHandler(InstancePtr);
+	}
+
+	if((IsrStatus & ((u32)XUARTPS_IXR_DMS)) != (u32)0) {
+		/* Modem status interrupt */
+		ModemHandler(InstancePtr);
+	}
+
+	/* Clear the interrupt status. */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_ISR_OFFSET,
+		IsrStatus);
+
+}
+
+/****************************************************************************/
+/*
+*
+* This function handles interrupts for receive errors which include
+* overrun errors, framing errors, parity errors, and the break interrupt.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveErrorHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+	u32 ByteStatusValue, EventData;
+	u32 Event;
+
+	InstancePtr->is_rxbs_error = 0;
+
+	if ((InstancePtr->Platform == XPLAT_ZYNQ_ULTRA_MP) &&
+		(IsrStatus & ((u32)XUARTPS_IXR_PARITY | (u32)XUARTPS_IXR_RBRK
+					| (u32)XUARTPS_IXR_FRAMING))) {
+		InstancePtr->is_rxbs_error = 1;
+	}
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+
+	(void)XUartPs_ReceiveBuffer(InstancePtr);
+
+	if (!(InstancePtr->is_rxbs_error)) {
+		Event = XUARTPS_EVENT_RECV_ERROR;
+		EventData = InstancePtr->ReceiveBuffer.RequestedBytes -
+			InstancePtr->ReceiveBuffer.RemainingBytes;
+
+		/*
+		 * Call the application handler to indicate that there is a receive
+		 * error or a break interrupt, if the application cares about the
+		 * error it call a function to get the last errors.
+		 */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					Event,
+					EventData);
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the receive timeout interrupt. This interrupt occurs
+* whenever a number of bytes have been present in the RX FIFO and the receive
+* data line has been idle for at lease 4 or more character times, (the timeout
+* is set using XUartPs_SetrecvTimeout() function).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveTimeoutHandler(XUartPs *InstancePtr)
+{
+	u32 Event;
+
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	/*
+	 * If there are no more bytes to receive then indicate that this is
+	 * not a receive timeout but the end of the buffer reached, a timeout
+	 * normally occurs if # of bytes is not divisible by FIFO threshold,
+	 * don't rely on previous test of remaining bytes since receive
+	 * function updates it
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		Event = XUARTPS_EVENT_RECV_TOUT;
+	} else {
+		Event = XUARTPS_EVENT_RECV_DATA;
+	}
+
+	/*
+	 * Call the application handler to indicate that there is a receive
+	 * timeout or data event
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef, Event,
+				 InstancePtr->ReceiveBuffer.RequestedBytes -
+				 InstancePtr->ReceiveBuffer.RemainingBytes);
+
+}
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data is in RX FIFO.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ReceiveDataHandler(XUartPs *InstancePtr)
+{
+	/*
+	 * If there are bytes still to be received in the specified buffer
+	 * go ahead and receive them. Removing bytes from the RX FIFO will
+	 * clear the interrupt.
+	 */
+	 if (InstancePtr->ReceiveBuffer.RemainingBytes != (u32)0) {
+		(void)XUartPs_ReceiveBuffer(InstancePtr);
+	}
+
+	 /* If the last byte of a message was received then call the application
+	 * handler, this code should not use an else from the previous check of
+	 * the number of bytes to receive because the call to receive the buffer
+	 * updates the bytes ramained
+	 */
+	if (InstancePtr->ReceiveBuffer.RemainingBytes == (u32)0) {
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+				XUARTPS_EVENT_RECV_DATA,
+				(InstancePtr->ReceiveBuffer.RequestedBytes -
+				InstancePtr->ReceiveBuffer.RemainingBytes));
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles the interrupt when data has been sent, the transmit
+* FIFO is empty (transmitter holding register).
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+* @param	IsrStatus is the register value for channel status register
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void SendDataHandler(XUartPs *InstancePtr, u32 IsrStatus)
+{
+
+	/*
+	 * If there are not bytes to be sent from the specified buffer then disable
+	 * the transmit interrupt so it will stop interrupting as it interrupts
+	 * any time the FIFO is empty
+	 */
+	if (InstancePtr->SendBuffer.RemainingBytes == (u32)0) {
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				XUARTPS_IDR_OFFSET,
+				((u32)XUARTPS_IXR_TXEMPTY | (u32)XUARTPS_IXR_TXFULL));
+
+		/* Call the application handler to indicate the sending is done */
+		InstancePtr->Handler(InstancePtr->CallBackRef,
+					XUARTPS_EVENT_SENT_DATA,
+					InstancePtr->SendBuffer.RequestedBytes -
+					InstancePtr->SendBuffer.RemainingBytes);
+	}
+
+	/* If TX FIFO is empty, send more. */
+	else if((IsrStatus & ((u32)XUARTPS_IXR_TXEMPTY)) != (u32)0) {
+		(void)XUartPs_SendBuffer(InstancePtr);
+	}
+	else {
+		/* Else with dummy entry for MISRA-C Compliance.*/
+		;
+	}
+}
+
+/****************************************************************************/
+/**
+*
+* This function handles modem interrupts.  It does not do any processing
+* except to call the application handler to indicate a modem event.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+static void ModemHandler(XUartPs *InstancePtr)
+{
+	u32 MsrRegister;
+
+	/*
+	 * Read the modem status register so that the interrupt is acknowledged
+	 * and it can be passed to the callback handler with the event
+	 */
+	MsrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+			  XUARTPS_MODEMSR_OFFSET);
+
+	/*
+	 * Call the application handler to indicate the modem status changed,
+	 * passing the modem status and the event data in the call
+	 */
+	InstancePtr->Handler(InstancePtr->CallBackRef,
+				  XUARTPS_EVENT_MODEM,
+				  MsrRegister);
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c
new file mode 100644
index 000000000..7051d07ec
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_options.c
@@ -0,0 +1,761 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_options.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* The implementation of the options functions for the XUartPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 1.00  sdm    09/27/11 Fixed a bug in XUartPs_SetFlowDelay where the input
+*			value was not being written to the register.
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+*
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+/*
+ * The following data type is a map from an option to the offset in the
+ * register to which it belongs as well as its bit mask in that register.
+ */
+typedef struct {
+	u16 Option;
+	u16 RegisterOffset;
+	u32 Mask;
+} Mapping;
+
+/*
+ * Create the table which contains options which are to be processed to get/set
+ * the options. These options are table driven to allow easy maintenance and
+ * expansion of the options.
+ */
+
+static Mapping OptionsTable[] = {
+	{XUARTPS_OPTION_SET_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STARTBRK},
+	{XUARTPS_OPTION_STOP_BREAK, XUARTPS_CR_OFFSET, XUARTPS_CR_STOPBRK},
+	{XUARTPS_OPTION_RESET_TMOUT, XUARTPS_CR_OFFSET, XUARTPS_CR_TORST},
+	{XUARTPS_OPTION_RESET_TX, XUARTPS_CR_OFFSET, XUARTPS_CR_TXRST},
+	{XUARTPS_OPTION_RESET_RX, XUARTPS_CR_OFFSET, XUARTPS_CR_RXRST},
+	{XUARTPS_OPTION_ASSERT_RTS, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_RTS},
+	{XUARTPS_OPTION_ASSERT_DTR, XUARTPS_MODEMCR_OFFSET,
+	 XUARTPS_MODEMCR_DTR},
+	{XUARTPS_OPTION_SET_FCM, XUARTPS_MODEMCR_OFFSET, XUARTPS_MODEMCR_FCM}
+};
+
+/* Create a constant for the number of entries in the table */
+
+#define XUARTPS_NUM_OPTIONS	  (sizeof(OptionsTable) / sizeof(Mapping))
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Gets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simulataneously.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The current options for the UART. The optionss are bit masks that are
+* contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @note		None.
+*
+*****************************************************************************/
+u16 XUartPs_GetOptions(XUartPs *InstancePtr)
+{
+	u16 Options = 0U;
+	u32 Register;
+	u32 Index;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the physical options in the
+	 * registers of the UART to the logical options to be returned
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the bit in the register which correlates to the option
+		 * is set, then set the corresponding bit in the options,
+		 * ignoring any bits which are zero since the options variable
+		 * is initialized to zero
+		 */
+		if ((Register & OptionsTable[Index].Mask) != (u32)0) {
+			Options |= OptionsTable[Index].Option;
+		}
+	}
+
+	return Options;
+}
+
+/****************************************************************************/
+/**
+*
+* Sets the options for the specified driver instance. The options are
+* implemented as bit masks such that multiple options may be enabled or
+* disabled simultaneously.
+*
+* The GetOptions function may be called to retrieve the currently enabled
+* options. The result is ORed in the desired new settings to be enabled and
+* ANDed with the inverse to clear the settings to be disabled. The resulting
+* value is then used as the options for the SetOption function call.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	Options contains the options to be set which are bit masks
+*		contained in the file xuartps.h and named XUARTPS_OPTION_*.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOptions(XUartPs *InstancePtr, u16 Options)
+{
+	u32 Index;
+	u32 Register;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Loop thru the options table to map the logical options to the
+	 * physical options in the registers of the UART.
+	 */
+	for (Index = 0U; Index < XUARTPS_NUM_OPTIONS; Index++) {
+
+		/*
+		 * Read the register which contains option so that the register
+		 * can be changed without destoying any other bits of the
+		 * register.
+		 */
+		Register = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 OptionsTable[Index].
+						 RegisterOffset);
+
+		/*
+		 * If the option is set in the input, then set the corresponding
+		 * bit in the specified register, otherwise clear the bit in
+		 * the register.
+		 */
+		if ((Options & OptionsTable[Index].Option) != (u16)0) {
+			Register |= OptionsTable[Index].Mask;
+		}
+		else {
+			Register &= ~OptionsTable[Index].Mask;
+		}
+
+		/* Write the new value to the register to set the option */
+		XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+				   OptionsTable[Index].RegisterOffset,
+				   Register);
+	}
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the receive FIFO trigger level. The receive trigger
+* level indicates the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current receive FIFO trigger level. This is a value
+*		from 0-31.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFifoThreshold(XUartPs *InstancePtr)
+{
+	u8 RtrigRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the value of the FIFO control register so that the threshold
+	 * can be retrieved, this read takes special register processing
+	 */
+	RtrigRegister = (u8) XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						   XUARTPS_RXWM_OFFSET);
+
+	/* Return only the trigger level from the register value */
+
+	RtrigRegister &= (u8)XUARTPS_RXWM_MASK;
+	return RtrigRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This functions sets the receive FIFO trigger level. The receive trigger
+* level specifies the number of bytes in the receive FIFO that cause a receive
+* data event (interrupt) to be generated.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	TriggerLevel contains the trigger level to set.
+*
+* @return	None
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFifoThreshold(XUartPs *InstancePtr, u8 TriggerLevel)
+{
+	u32 RtrigRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(TriggerLevel <= (u8)XUARTPS_RXWM_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	RtrigRegister = ((u32)TriggerLevel) & (u32)XUARTPS_RXWM_MASK;
+
+	/*
+	 * Write the new value for the FIFO control register to it such that the
+	 * threshold is changed
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXWM_OFFSET, RtrigRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the modem status from the specified UART. The modem
+* status indicates any changes of the modem signals. This function allows
+* the modem status to be read in a polled mode. The modem status is updated
+* whenever it is read such that reading it twice may not yield the same
+* results.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The modem status which are bit masks that are contained in the file
+* xuartps.h and named XUARTPS_MODEM_*.
+*
+* @note
+*
+* The bit masks used for the modem status are the exact bits of the modem
+* status register with no abstraction.
+*
+*****************************************************************************/
+u16 XUartPs_GetModemStatus(XUartPs *InstancePtr)
+{
+	u32 ModemStatusRegister;
+	u16 TmpRegister;
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the modem status register to return
+	 */
+	ModemStatusRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						XUARTPS_MODEMSR_OFFSET);
+	TmpRegister = (u16)ModemStatusRegister;
+	return TmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function determines if the specified UART is sending data.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*		- TRUE if the UART is sending data
+*		- FALSE if UART is not sending data
+*
+* @note		None.
+*
+*****************************************************************************/
+u32 XUartPs_IsSending(XUartPs *InstancePtr)
+{
+	u32 ChanStatRegister;
+	u32 ChanTmpSRegister;
+	u32 ActiveResult;
+	u32 EmptyResult;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the channel status register to determine if the transmitter is
+	 * active
+	 */
+	ChanStatRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						 XUARTPS_SR_OFFSET);
+
+	/*
+	 * If the transmitter is active, or the TX FIFO is not empty, then indicate
+	 * that the UART is still sending some data
+	 */
+	ActiveResult = ChanStatRegister & ((u32)XUARTPS_SR_TACTIVE);
+	EmptyResult = ChanStatRegister & ((u32)XUARTPS_SR_TXEMPTY);
+	ChanTmpSRegister = (((u32)XUARTPS_SR_TACTIVE) == ActiveResult) ||
+		(((u32)XUARTPS_SR_TXEMPTY) != EmptyResult);
+
+	return ChanTmpSRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The operational mode is specified by constants defined in xuartps.h. The
+* constants are named XUARTPS_OPER_MODE_*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetOperMode(XUartPs *InstancePtr)
+{
+	u32 ModeRegister;
+	u8 OperMode;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Mode register. */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	ModeRegister &= (u32)XUARTPS_MR_CHMODE_MASK;
+	/* Return the constant */
+	switch (ModeRegister) {
+	case XUARTPS_MR_CHMODE_NORM:
+		OperMode = XUARTPS_OPER_MODE_NORMAL;
+		break;
+	case XUARTPS_MR_CHMODE_ECHO:
+		OperMode = XUARTPS_OPER_MODE_AUTO_ECHO;
+		break;
+	case XUARTPS_MR_CHMODE_L_LOOP:
+		OperMode = XUARTPS_OPER_MODE_LOCAL_LOOP;
+		break;
+	case XUARTPS_MR_CHMODE_R_LOOP:
+		OperMode = XUARTPS_OPER_MODE_REMOTE_LOOP;
+		break;
+	default:
+		OperMode = (u8) ((ModeRegister & (u32)XUARTPS_MR_CHMODE_MASK) >>
+			XUARTPS_MR_CHMODE_SHIFT);
+		break;
+	}
+
+	return OperMode;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the operational mode of the UART. The UART can operate
+* in one of four modes: Normal, Local Loopback, Remote Loopback, or automatic
+* echo.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	OperationMode is the mode of the UART.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetOperMode(XUartPs *InstancePtr, u8 OperationMode)
+{
+	u32 ModeRegister;
+
+	/* Assert validates the input arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid(OperationMode <= XUARTPS_OPER_MODE_REMOTE_LOOP);
+
+	/* Read the Mode register. */
+	ModeRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/* Set the correct value by masking the bits, then ORing the const. */
+	ModeRegister &= (u32)(~XUARTPS_MR_CHMODE_MASK);
+
+	switch (OperationMode) {
+		case XUARTPS_OPER_MODE_NORMAL:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_NORM;
+			break;
+		case XUARTPS_OPER_MODE_AUTO_ECHO:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_ECHO;
+			break;
+		case XUARTPS_OPER_MODE_LOCAL_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_L_LOOP;
+			break;
+		case XUARTPS_OPER_MODE_REMOTE_LOOP:
+			ModeRegister |= (u32)XUARTPS_MR_CHMODE_R_LOOP;
+			break;
+		default:
+			/* Default case made for MISRA-C Compliance. */
+			break;
+	}
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 32: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return
+*
+* The Flow Delay is specified by constants defined in xuartps_hw.h. The
+* constants are named XUARTPS_FLOWDEL*
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetFlowDelay(XUartPs *InstancePtr)
+{
+	u32 FdelTmpRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Mode register. */
+	FdelTmpRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XUARTPS_FLOWDEL_OFFSET);
+
+	/* Return the contents of the flow delay register */
+	FdelTmpRegister = (u8)(FdelTmpRegister & (u32)XUARTPS_FLOWDEL_MASK);
+	return  FdelTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Flow Delay.
+* 0 - 3: Flow delay inactive
+* 4 - 63: If Flow Control mode is enabled, UART_rtsN is deactivated when the
+* receive FIFO fills to this level.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FlowDelayValue is the Setting for the flow delay.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetFlowDelay(XUartPs *InstancePtr, u8 FlowDelayValue)
+{
+	u32 FdelRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FlowDelayValue > (u8)XUARTPS_FLOWDEL_MASK);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Set the correct value by shifting the input constant, then masking
+	 * the bits
+	 */
+	FdelRegister = ((u32)FlowDelayValue) & (u32)XUARTPS_FLOWDEL_MASK;
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_FLOWDEL_OFFSET, FdelRegister);
+
+}
+
+/****************************************************************************/
+/**
+*
+* This function gets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+*
+* @return	The current setting for receive time out.
+*
+* @note		None.
+*
+*****************************************************************************/
+u8 XUartPs_GetRecvTimeout(XUartPs *InstancePtr)
+{
+	u32 RtoRegister;
+	u8 RtoRTmpRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Read the Receive Timeout register. */
+	RtoRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+					XUARTPS_RXTOUT_OFFSET);
+
+	/* Return the contents of the mode register shifted appropriately */
+	RtoRTmpRegister = (u8)(RtoRegister & (u32)XUARTPS_RXTOUT_MASK);
+	return RtoRTmpRegister;
+}
+
+/****************************************************************************/
+/**
+*
+* This function sets the Receive Timeout of the UART.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	RecvTimeout setting allows the UART to detect an idle connection
+*		on the reciever data line.
+*		Timeout duration = RecvTimeout x 4 x Bit Period. 0 disables the
+*		timeout function.
+*
+* @return	None.
+*
+* @note		None.
+*
+*****************************************************************************/
+void XUartPs_SetRecvTimeout(XUartPs *InstancePtr, u8 RecvTimeout)
+{
+	u32 RtoRegister;
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Set the correct value by masking the bits */
+	RtoRegister = ((u32)RecvTimeout & (u32)XUARTPS_RXTOUT_MASK);
+
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress,
+			   XUARTPS_RXTOUT_OFFSET, RtoRegister);
+
+	/* Configure CR to restart the receiver timeout counter */
+	RtoRegister =
+		XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_CR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_CR_OFFSET,
+			   (RtoRegister | XUARTPS_CR_TORST));
+
+}
+/****************************************************************************/
+/**
+*
+* Sets the data format for the device. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity. It is the
+* caller's responsibility to ensure that the UART is not sending or receiving
+* data when this function is called.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure containing the data
+*		format to be set.
+*
+* @return
+*		- XST_SUCCESS if the data format was successfully set.
+*		- XST_UART_BAUD_ERROR indicates the baud rate could not be
+*		set because of the amount of error with the baud rate and
+*		the input clock frequency.
+*		- XST_INVALID_PARAM if one of the parameters was not valid.
+*
+* @note
+*
+* The data types in the format type, data bits and parity, are 32 bit fields
+* to prevent a compiler warning.
+* The asserts in this function will cause a warning if these fields are
+* bytes.
+* 


+*
+*****************************************************************************/
+s32 XUartPs_SetDataFormat(XUartPs *InstancePtr,
+			XUartPsFormat * FormatPtr)
+{
+	s32 Status;
+	u32 ModeRegister;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(FormatPtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Verify the inputs specified are valid */
+	if ((FormatPtr->DataBits > ((u32)XUARTPS_FORMAT_6_BITS)) ||
+		(FormatPtr->StopBits > ((u8)XUARTPS_FORMAT_2_STOP_BIT)) ||
+		(FormatPtr->Parity > ((u32)XUARTPS_FORMAT_NO_PARITY))) {
+		Status = XST_INVALID_PARAM;
+	} else {
+
+		/*
+		 * Try to set the baud rate and if it's not successful then don't
+		 * continue altering the data format, this is done first to avoid the
+		 * format from being altered when an error occurs
+		 */
+		Status = XUartPs_SetBaudRate(InstancePtr, FormatPtr->BaudRate);
+		if (Status != (s32)XST_SUCCESS) {
+			;
+		} else {
+
+			ModeRegister =
+				XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+						  XUARTPS_MR_OFFSET);
+
+			/*
+			 * Set the length of data (8,7,6) by first clearing out the bits
+			 * that control it in the register, then set the length in the register
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_CHARLEN_MASK);
+			ModeRegister |= (FormatPtr->DataBits << XUARTPS_MR_CHARLEN_SHIFT);
+
+			/*
+			 * Set the number of stop bits in the mode register by first clearing
+			 * out the bits that control it in the register, then set the number
+			 * of stop bits in the register.
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_STOPMODE_MASK);
+			ModeRegister |= (((u32)FormatPtr->StopBits) << XUARTPS_MR_STOPMODE_SHIFT);
+
+			/*
+			 * Set the parity by first clearing out the bits that control it in the
+			 * register, then set the bits in the register, the default is no parity
+			 * after clearing the register bits
+			 */
+			ModeRegister &= (u32)(~XUARTPS_MR_PARITY_MASK);
+			ModeRegister |= (FormatPtr->Parity << XUARTPS_MR_PARITY_SHIFT);
+
+			/* Update the mode register */
+			XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+					   ModeRegister);
+
+			Status = XST_SUCCESS;
+		}
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Gets the data format for the specified UART. The data format includes the
+* baud rate, number of data bits, number of stop bits, and parity.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance.
+* @param	FormatPtr is a pointer to a format structure that will contain
+*		the data format after this call completes.
+*
+* @return	None.
+*
+* @note		None.
+*
+*
+*****************************************************************************/
+void XUartPs_GetDataFormat(XUartPs *InstancePtr, XUartPsFormat * FormatPtr)
+{
+	u32 ModeRegister;
+
+
+	/* Assert validates the input arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(FormatPtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Get the baud rate from the instance, this is not retrieved from the
+	 * hardware because it is only kept as a divisor such that it is more
+	 * difficult to get back to the baud rate
+	 */
+	FormatPtr->BaudRate = InstancePtr->BaudRate;
+
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				  XUARTPS_MR_OFFSET);
+
+	/* Get the length of data (8,7,6,5) */
+	FormatPtr->DataBits =
+		((ModeRegister & (u32)XUARTPS_MR_CHARLEN_MASK) >>
+		XUARTPS_MR_CHARLEN_SHIFT);
+
+	/* Get the number of stop bits */
+	FormatPtr->StopBits =
+		(u8)((ModeRegister & (u32)XUARTPS_MR_STOPMODE_MASK) >>
+		XUARTPS_MR_STOPMODE_SHIFT);
+
+	/* Determine what parity is */
+	FormatPtr->Parity =
+		(u32)((ModeRegister & (u32)XUARTPS_MR_PARITY_MASK) >>
+		XUARTPS_MR_PARITY_SHIFT);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_selftest.c
new file mode 100644
index 000000000..a1a7dd366
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_selftest.c
@@ -0,0 +1,166 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_selftest.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* This file contains the self-test functions for the XUartPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00	drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xstatus.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XUARTPS_TOTAL_BYTES (u8)32
+
+/************************** Variable Definitions *****************************/
+
+static u8 TestString[XUARTPS_TOTAL_BYTES]="abcdefghABCDEFGH012345677654321";
+static u8 ReturnString[XUARTPS_TOTAL_BYTES];
+
+/************************** Function Prototypes ******************************/
+
+
+/****************************************************************************/
+/**
+*
+* This function runs a self-test on the driver and hardware device. This self
+* test performs a local loopback and verifies data can be sent and received.
+*
+* The time for this test is proportional to the baud rate that has been set
+* prior to calling this function.
+*
+* The mode and control registers are restored before return.
+*
+* @param	InstancePtr is a pointer to the XUartPs instance
+*
+* @return
+*		 - XST_SUCCESS if the test was successful
+*		- XST_UART_TEST_FAIL if the test failed looping back the data
+*
+* @note
+*
+* This function can hang if the hardware is not functioning properly.
+*
+******************************************************************************/
+s32 XUartPs_SelfTest(XUartPs *InstancePtr)
+{
+	s32 Status = XST_SUCCESS;
+	u32 IntrRegister;
+	u32 ModeRegister;
+	u8 Index;
+	u32 ReceiveDataResult;
+
+	/* Assert validates the input arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/* Disable all interrupts in the interrupt disable register */
+	IntrRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_IMR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IDR_OFFSET,
+		XUARTPS_IXR_MASK);
+
+	/* Setup for local loopback */
+	ModeRegister = XUartPs_ReadReg(InstancePtr->Config.BaseAddress,
+				   XUARTPS_MR_OFFSET);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ((ModeRegister & (u32)(~XUARTPS_MR_CHMODE_MASK)) |
+				(u32)XUARTPS_MR_CHMODE_L_LOOP));
+
+	/* Send a number of bytes and receive them, one at a time. */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		/*
+		 * Send out the byte and if it was not sent then the failure
+		 * will be caught in the comparison at the end
+		 */
+		(void)XUartPs_Send(InstancePtr, &TestString[Index], 1U);
+
+		/*
+		 * Wait until the byte is received. This can hang if the HW
+		 * is broken. Watch for the FIFO empty flag to be false.
+		 */
+		ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+				XUARTPS_SR_RXEMPTY;
+		while (ReceiveDataResult == XUARTPS_SR_RXEMPTY ) {
+			ReceiveDataResult = Xil_In32((InstancePtr->Config.BaseAddress) + XUARTPS_SR_OFFSET) &
+					XUARTPS_SR_RXEMPTY;
+		}
+
+		/* Receive the byte */
+		(void)XUartPs_Recv(InstancePtr, &ReturnString[Index], 1U);
+	}
+
+	/*
+	 * Compare the bytes received to the bytes sent to verify the exact data
+	 * was received
+	 */
+	for (Index = 0U; Index < XUARTPS_TOTAL_BYTES; Index++) {
+		if (TestString[Index] != ReturnString[Index]) {
+			Status = XST_UART_TEST_FAIL;
+		}
+	}
+
+	/*
+	 * Restore the registers which were altered to put into polling and
+	 * loopback modes so that this test is not destructive
+	 */
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_IER_OFFSET,
+			   IntrRegister);
+	XUartPs_WriteReg(InstancePtr->Config.BaseAddress, XUARTPS_MR_OFFSET,
+			   ModeRegister);
+
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_sinit.c
new file mode 100644
index 000000000..8dc87dae3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/uartps_v3_1/src/xuartps_sinit.c
@@ -0,0 +1,99 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xuartps_sinit.c
+* @addtogroup uartps_v3_1
+* @{
+*
+* The implementation of the XUartPs driver's static initialzation
+* functionality.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date	Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00  drg/jz 01/13/10 First Release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+*****************************************************************************/
+
+/***************************** Include Files ********************************/
+
+#include "xstatus.h"
+#include "xparameters.h"
+#include "xuartps.h"
+
+/************************** Constant Definitions ****************************/
+
+/**************************** Type Definitions ******************************/
+
+/***************** Macros (Inline Functions) Definitions ********************/
+
+/************************** Variable Definitions ****************************/
+extern XUartPs_Config XUartPs_ConfigTable[XPAR_XUARTPS_NUM_INSTANCES];
+
+/************************** Function Prototypes *****************************/
+
+/****************************************************************************/
+/**
+*
+* Looks up the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId contains the ID of the device
+*
+* @return	A pointer to the configuration structure or NULL if the
+*		specified device is not in the system.
+*
+* @note		None.
+*
+******************************************************************************/
+XUartPs_Config *XUartPs_LookupConfig(u16 DeviceId)
+{
+	XUartPs_Config *CfgPtr = NULL;
+
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XUARTPS_NUM_INSTANCES; Index++) {
+		if (XUartPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XUartPs_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XUartPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/Makefile
new file mode 100644
index 000000000..8efa57289
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner wdtps_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling wdtps"
+
+wdtps_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: wdtps_includes
+
+wdtps_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.c
new file mode 100644
index 000000000..fc5db32fe
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.c
@@ -0,0 +1,486 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xwdtps.c
+* @addtogroup wdtps_v3_0
+* @{
+*
+* Contains the implementation of interface functions of the XWdtPs driver.
+* See xwdtps.h for a description of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 1.02a  sg    07/15/12 Removed code/APIs related to  External Signal
+*			Length functionality for CR 658287
+*			Removed APIs XWdtPs_SetExternalSignalLength,
+*			XWdtPs_GetExternalSignalLength
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xwdtps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* Initialize a specific watchdog timer instance/driver. This function
+* must be called before other functions of the driver are called.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+* @param	ConfigPtr is the config structure.
+* @param	EffectiveAddress is the base address for the device. It could be
+*		a virtual address if address translation is supported in the
+*		system, otherwise it is the physical address.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*		- XST_DEVICE_IS_STARTED if the device has already been started.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XWdtPs_CfgInitialize(XWdtPs *InstancePtr,
+			XWdtPs_Config *ConfigPtr, u32 EffectiveAddress)
+{
+	s32 Status;
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(ConfigPtr != NULL);
+
+	/*
+	 * If the device is started, disallow the initialize and return a
+	 * status indicating it is started. This allows the user to stop the
+	 * device and reinitialize, but prevents a user from inadvertently
+	 * initializing.
+	 */
+	if (InstancePtr->IsStarted == XIL_COMPONENT_IS_STARTED) {
+		Status = XST_DEVICE_IS_STARTED;
+	} else {
+
+		/*
+		 * Copy configuration into instance.
+		 */
+		InstancePtr->Config.DeviceId = ConfigPtr->DeviceId;
+
+		/*
+		 * Save the base address pointer such that the registers of the block
+		 * can be accessed and indicate it has not been started yet.
+		 */
+		InstancePtr->Config.BaseAddress = EffectiveAddress;
+		InstancePtr->IsStarted = 0U;
+
+		/*
+		 * Indicate the instance is ready to use, successfully initialized.
+		 */
+		InstancePtr->IsReady = XIL_COMPONENT_IS_READY;
+
+		Status = XST_SUCCESS;
+	}
+	return Status;
+}
+
+/****************************************************************************/
+/**
+*
+* Start the watchdog timer of the device.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XWdtPs_Start(XWdtPs *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the ZMR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	/*
+	 * Enable the Timer field in the register and Set the access key so the
+	 * write takes place.
+	 */
+	Register |= XWDTPS_ZMR_WDEN_MASK;
+	Register |= XWDTPS_ZMR_ZKEY_VAL;
+
+	/*
+	 * Update the ZMR with the new value.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+			  Register);
+
+	/*
+	 * Indicate that the device is started.
+	 */
+	InstancePtr->IsStarted = XIL_COMPONENT_IS_STARTED;
+
+}
+
+/****************************************************************************/
+/**
+*
+* Disable the watchdog timer.
+*
+* It is the caller's responsibility to disconnect the interrupt handler
+* of the watchdog timer from the interrupt source, typically an interrupt
+* controller, and disable the interrupt in the interrupt controller.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XWdtPs_Stop(XWdtPs *InstancePtr)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the contents of the ZMR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	/*
+	 * Disable the Timer field in the register and
+	 * Set the access key for the write to be done the register.
+	 */
+	Register &= (u32)(~XWDTPS_ZMR_WDEN_MASK);
+	Register |= XWDTPS_ZMR_ZKEY_VAL;
+
+	/*
+	 * Update the ZMR with the new value.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+			  Register);
+
+	InstancePtr->IsStarted = 0U;
+}
+
+
+/****************************************************************************/
+/**
+*
+* Enables the indicated signal/output.
+* Performs a read/modify/write cycle to update the value correctly.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+* @param	Signal is the desired signal/output.
+*		Valid Signal Values are XWDTPS_RESET_SIGNAL and
+*		XWDTPS_IRQ_SIGNAL.
+*		Only one of them can be specified at a time.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XWdtPs_EnableOutput(XWdtPs *InstancePtr, u8 Signal)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Signal == XWDTPS_RESET_SIGNAL) ||
+			(Signal == XWDTPS_IRQ_SIGNAL));
+
+	/*
+	 * Read the contents of the ZMR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	if (Signal == XWDTPS_RESET_SIGNAL) {
+		/*
+		 * Enable the field in the register.
+		 */
+		Register |= XWDTPS_ZMR_RSTEN_MASK;
+
+	} else if (Signal == XWDTPS_IRQ_SIGNAL) {
+		/*
+		 * Enable the field in the register.
+		 */
+		Register |= XWDTPS_ZMR_IRQEN_MASK;
+
+	} else {
+		/* Else was made for misra-c compliance */
+		;
+	}
+
+	/*
+	 * Set the access key so the write takes.
+	 */
+	Register |= XWDTPS_ZMR_ZKEY_VAL;
+
+	/*
+	 * Update the ZMR with the new value.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+			  Register);
+}
+
+/****************************************************************************/
+/**
+*
+* Disables the indicated signal/output.
+* Performs a read/modify/write cycle to update the value correctly.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+* @param	Signal is the desired signal/output.
+*		Valid Signal Values are XWDTPS_RESET_SIGNAL and
+*		XWDTPS_IRQ_SIGNAL
+*		Only one of them can be specified at a time.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XWdtPs_DisableOutput(XWdtPs *InstancePtr, u8 Signal)
+{
+	u32 Register;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Signal == XWDTPS_RESET_SIGNAL) ||
+			(Signal == XWDTPS_IRQ_SIGNAL));
+
+	/*
+	 * Read the contents of the ZMR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	if (Signal == XWDTPS_RESET_SIGNAL) {
+		/*
+		 * Disable the field in the register.
+		 */
+		Register &= (u32)(~XWDTPS_ZMR_RSTEN_MASK);
+
+	} else if (Signal == XWDTPS_IRQ_SIGNAL) {
+		/*
+		 * Disable the field in the register.
+		 */
+		Register &= (u32)(~XWDTPS_ZMR_IRQEN_MASK);
+
+	} else {
+		/* Else was made for misra-c compliance */
+		;
+	}
+
+	/*
+	 * Set the access key so the write takes place.
+	 */
+	Register |= XWDTPS_ZMR_ZKEY_VAL;
+
+	/*
+	 * Update the ZMR with the new value.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+			  Register);
+}
+
+/****************************************************************************/
+/**
+*
+* Returns the current control setting for the indicated signal/output.
+* The register referenced is the Counter Control Register (XWDTPS_CCR_OFFSET)
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+* @param	Control is the desired signal/output.
+*		Valid Control Values are XWDTPS_CLK_PRESCALE and
+*		XWDTPS_COUNTER_RESET. Only one of them can be specified at a
+*		time.
+*
+* @return	The contents of the requested control field in the Counter
+*		Control Register (XWDTPS_CCR_OFFSET).
+*		If the Control is XWDTPS_CLK_PRESCALE then use the
+*		defintions XWDTEPB_CCR_PSCALE_XXXX.
+*		If the Control is XWDTPS_COUNTER_RESET then the values are
+*		0x0 to 0xFFF. This is the Counter Restart value in the CCR
+*		register.
+*
+* @note		None.
+*
+******************************************************************************/
+u32 XWdtPs_GetControlValue(XWdtPs *InstancePtr, u8 Control)
+{
+	u32 Register;
+	u32 ReturnValue = 0U;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertNonvoid((Control == XWDTPS_CLK_PRESCALE) ||
+			(Control == XWDTPS_COUNTER_RESET));
+
+	/*
+	 * Read the contents of the CCR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+			 XWDTPS_CCR_OFFSET);
+
+	if (Control == XWDTPS_CLK_PRESCALE) {
+		/*
+		 * Mask off the field in the register.
+		 */
+		ReturnValue = Register & XWDTPS_CCR_CLKSEL_MASK;
+
+	} else if (Control == XWDTPS_COUNTER_RESET) {
+		/*
+		 * Mask off the field in the register.
+		 */
+		Register &= XWDTPS_CCR_CRV_MASK;
+
+		/*
+		 * Shift over to the right most positions.
+		 */
+		ReturnValue = Register >> XWDTPS_CCR_CRV_SHIFT;
+	} else {
+		/* Else was made for misra-c compliance */
+		;
+	}
+
+	return ReturnValue;
+}
+
+/****************************************************************************/
+/**
+*
+* Updates the current control setting for the indicated signal/output with
+* the provided value.
+*
+* Performs a read/modify/write cycle to update the value correctly.
+* The register referenced is the Counter Control Register (XWDTPS_CCR_OFFSET)
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+* @param	Control is the desired signal/output.
+*		Valid Control Values are XWDTPS_CLK_PRESCALE and
+*		XWDTPS_COUNTER_RESET. Only one of them can be specified at a
+*		time.
+* @param	Value is the desired control value.
+*		If the Control is XWDTPS_CLK_PRESCALE then use the
+*		defintions XWDTEPB_CCR_PSCALE_XXXX.
+*		If the Control is XWDTPS_COUNTER_RESET then the valid values
+*		are 0x0 to 0xFFF, this sets the counter restart value of the CCR
+*		register.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XWdtPs_SetControlValue(XWdtPs *InstancePtr, u8 Control, u32 Value)
+{
+	u32 Register;
+	u32 LocalValue = Value;
+
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+	Xil_AssertVoid((Control == XWDTPS_CLK_PRESCALE) ||
+			(Control == XWDTPS_COUNTER_RESET));
+
+	/*
+	 * Read the contents of the CCR register.
+	 */
+	Register = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_CCR_OFFSET);
+
+	if (Control == XWDTPS_CLK_PRESCALE) {
+		/*
+		 * Zero the field in the register.
+		 */
+		Register &= (u32)(~XWDTPS_CCR_CLKSEL_MASK);
+
+	} else if (Control == XWDTPS_COUNTER_RESET) {
+		/*
+		 * Zero the field in the register.
+		 */
+		Register &= (u32)(~XWDTPS_CCR_CRV_MASK);
+
+		/*
+		 * Shift Value over to the proper positions.
+		 */
+		LocalValue = LocalValue << XWDTPS_CCR_CRV_SHIFT;
+	} else{
+		/* This was made for misrac compliance. */
+		;
+	}
+
+	Register |= LocalValue;
+
+	/*
+	 * Set the access key so the write takes.
+	 */
+	Register |= XWDTPS_CCR_CKEY_VAL;
+
+	/*
+	 * Update the CCR with the new value.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_CCR_OFFSET,
+			  Register);
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h
new file mode 100644
index 000000000..893d516e7
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps.h
@@ -0,0 +1,223 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xwdtps.h
+* @addtogroup wdtps_v3_0
+* @{
+* @details
+*
+* The Xilinx watchdog timer driver supports the Xilinx watchdog timer hardware.
+*
+* The Xilinx watchdog timer (WDT) driver supports the following features:
+*   - Both Interrupt driven and Polled mode
+*   - enabling and disabling the watchdog timer
+*   - restarting the watchdog.
+*   - initializing the most significant digit of the counter restart value.
+*   - multiple individually enabling/disabling outputs
+*
+* It is the responsibility of the application to provide an interrupt handler
+* for the watchdog timer and connect it to the interrupt system if interrupt
+* driven mode is desired.
+*
+* If interrupt is enabled, the watchdog timer device generates an interrupt
+* when the counter reaches zero.
+*
+* If the hardware interrupt signal is not connected/enabled, polled mode is the
+* only option (using IsWdtExpired) for the watchdog.
+*
+* The outputs from the WDT are individually enabled/disabled using
+* _EnableOutput()/_DisableOutput(). The clock divisor ratio and initial restart
+* value of the count is configurable using _SetControlValues().
+*
+* The reset condition of the hardware has the maximum initial count in the
+* Counter Reset Value (CRV) and the WDT is disabled with the reset enable
+* enabled and the reset length set to 32 clocks. i.e.
+* 
+*     register ZMR = 0x1C2
+*     register CCR = 0x3FC
+* 

+*
+* This driver is intended to be RTOS and processor independent. It works with
+* physical addresses only.  Any needs for dynamic memory management, threads
+* or thread mutual exclusion, virtual memory, or cache control must be
+* satisfied by the layer above this driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- -----------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 1.01a asa    02/15/12 Added tcl file to generate xparameters
+* 1.02a  sg    07/15/12 Removed code/APIs related to  External Signal
+*						Length functionality for CR 658287
+*						Removed APIs XWdtPs_SetExternalSignalLength,
+*						XWdtPs_GetExternalSignalLength
+*						Modified the Self Test to use the Reset Length mask
+*						for CR 658287
+* 3.0	pkp	   12/09/14 Added support for Zynq Ultrascale Mp.Also
+*			modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+#ifndef XWDTPS_H		/* prevent circular inclusions */
+#define XWDTPS_H		/* by using protection macros */
+
+/***************************** Include Files *********************************/
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xwdtps_hw.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/************************** Constant Definitions *****************************/
+
+/*
+ * Choices for output selections for the device, used in
+ * XWdtPs_EnableOutput()/XWdtPs_DisableOutput() functions
+ */
+#define XWDTPS_RESET_SIGNAL	0x01U   /**< Reset signal request */
+#define XWDTPS_IRQ_SIGNAL	0x02U   /**< IRQ signal request */
+
+/*
+ * Control value setting flags, used in
+ * XWdtPs_SetControlValues()/XWdtPs_GetControlValues() functions
+ */
+#define XWDTPS_CLK_PRESCALE		0x01U   /**< Clock Prescale request */
+#define XWDTPS_COUNTER_RESET	0x02U   /**< Counter Reset request */
+
+/**************************** Type Definitions *******************************/
+
+/**
+ * This typedef contains configuration information for the device.
+ */
+typedef struct {
+	u16 DeviceId;		/**< Unique ID of device */
+	u32 BaseAddress;	/**< Base address of the device */
+} XWdtPs_Config;
+
+
+/**
+ * The XWdtPs driver instance data. The user is required to allocate a
+ * variable of this type for every watchdog/timer device in the system.
+ * A pointer to a variable of this type is then passed to the driver API
+ * functions.
+ */
+typedef struct {
+	XWdtPs_Config Config;   /**< Hardware Configuration */
+	u32 IsReady;		/**< Device is initialized and ready */
+	u32 IsStarted;		/**< Device watchdog timer is running */
+} XWdtPs;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+/****************************************************************************/
+/**
+*
+* Check if the watchdog timer has expired. This function is used for polled
+* mode and it is also used to check if the last reset was caused by the
+* watchdog timer.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+*
+* @return
+*		- TRUE if the watchdog has expired.
+*		- FALSE if the watchdog has not expired.
+*
+* @note		C-style signature:
+*		int XWdtPs_IsWdtExpired(XWdtPs *InstancePtr)
+*
+******************************************************************************/
+#define XWdtPs_IsWdtExpired(InstancePtr)				  \
+((XWdtPs_ReadReg((InstancePtr)->Config.BaseAddress, XWDTPS_SR_OFFSET) & \
+   XWDTPS_SR_WDZ_MASK) == XWDTPS_SR_WDZ_MASK)
+
+
+/****************************************************************************/
+/**
+*
+* Restart the watchdog timer. An application needs to call this function
+* periodically to keep the timer from asserting the enabled output.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XWdtPs_RestartWdt(XWdtPs *InstancePtr)
+*
+******************************************************************************/
+#define XWdtPs_RestartWdt(InstancePtr)					\
+	XWdtPs_WriteReg((InstancePtr)->Config.BaseAddress,		\
+		XWDTPS_RESTART_OFFSET, XWDTPS_RESTART_KEY_VAL)
+
+/************************** Function Prototypes ******************************/
+
+/*
+ * Lookup configuration in xwdtps_sinit.c.
+ */
+XWdtPs_Config *XWdtPs_LookupConfig(u16 DeviceId);
+
+/*
+ * Interface functions in xwdtps.c
+ */
+s32 XWdtPs_CfgInitialize(XWdtPs *InstancePtr,
+			XWdtPs_Config *ConfigPtr, u32 EffectiveAddress);
+
+void XWdtPs_Start(XWdtPs *InstancePtr);
+
+void XWdtPs_Stop(XWdtPs *InstancePtr);
+
+void XWdtPs_EnableOutput(XWdtPs *InstancePtr, u8 Signal);
+
+void XWdtPs_DisableOutput(XWdtPs *InstancePtr, u8 Signal);
+
+u32 XWdtPs_GetControlValue(XWdtPs *InstancePtr, u8 Control);
+
+void XWdtPs_SetControlValue(XWdtPs *InstancePtr, u8 Control, u32 Value);
+
+/*
+ * Self-test function in xwdttb_selftest.c.
+ */
+s32 XWdtPs_SelfTest(XWdtPs *InstancePtr);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* end of protection macro */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
new file mode 100644
index 000000000..5147be676
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_g.c
@@ -0,0 +1,59 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xwdtps.h"
+
+/*
+* The configuration table for devices
+*/
+
+XWdtPs_Config XWdtPs_ConfigTable[] =
+{
+	{
+		XPAR_PSU_WDT_0_DEVICE_ID,
+		XPAR_PSU_WDT_0_BASEADDR
+	},
+	{
+		XPAR_PSU_WDT_1_DEVICE_ID,
+		XPAR_PSU_WDT_1_BASEADDR
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_hw.h
new file mode 100644
index 000000000..4b5a3df31
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_hw.h
@@ -0,0 +1,193 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xwdtps_hw.h
+* @addtogroup wdtps_v3_0
+* @{
+*
+* This file contains the hardware interface to the System Watch Dog Timer (WDT).
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ---------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 1.02a  sg    07/15/12 Removed defines related to  External Signal
+*			Length functionality for CR 658287
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+#ifndef XWDTPS_HW_H		/* prevent circular inclusions */
+#define XWDTPS_HW_H		/* by using protection macros */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Register Map
+ * Offsets of registers from the start of the device
+ * @{
+ */
+
+#define XWDTPS_ZMR_OFFSET	0x00000000U /**< Zero Mode Register */
+#define XWDTPS_CCR_OFFSET	0x00000004U /**< Counter Control Register */
+#define XWDTPS_RESTART_OFFSET	0x00000008U /**< Restart Register */
+#define XWDTPS_SR_OFFSET	0x0000000CU /**< Status Register */
+/* @} */
+
+
+/** @name Zero Mode Register
+ * This register controls how the time out is indicated and also contains
+ * the access code (0xABC) to allow writes to the register
+ * @{
+ */
+#define XWDTPS_ZMR_WDEN_MASK	0x00000001U /**< enable the WDT */
+#define XWDTPS_ZMR_RSTEN_MASK	0x00000002U /**< enable the reset output */
+#define XWDTPS_ZMR_IRQEN_MASK	0x00000004U /**< enable the IRQ output */
+
+#define XWDTPS_ZMR_RSTLN_MASK	0x00000070U /**< set length of reset pulse */
+#define XWDTPS_ZMR_RSTLN_SHIFT	4U	   /**< shift for reset pulse */
+
+#define XWDTPS_ZMR_IRQLN_MASK	0x00000180U /**< set length of interrupt pulse */
+#define XWDTPS_ZMR_IRQLN_SHIFT	7U	   /**< shift for interrupt pulse */
+
+#define XWDTPS_ZMR_ZKEY_MASK	0x00FFF000U /**< mask for writing access key */
+#define XWDTPS_ZMR_ZKEY_VAL		0x00ABC000U /**< access key, 0xABC << 12 */
+
+/* @} */
+
+/** @name  Counter Control register
+ * This register controls how fast the timer runs and the reset value
+ * and also contains the access code (0x248) to allow writes to the
+ * register
+ * @{
+ */
+
+#define XWDTPS_CCR_CLKSEL_MASK	0x00000003U /**< counter clock prescale */
+
+#define XWDTPS_CCR_CRV_MASK	0x00003FFCU /**< counter reset value */
+#define XWDTPS_CCR_CRV_SHIFT	2U	   /**< shift for writing value */
+
+#define XWDTPS_CCR_CKEY_MASK	0x03FFC000U /**< mask for writing access key */
+#define XWDTPS_CCR_CKEY_VAL	0x00920000U /**< access key, 0x248 << 14 */
+
+/* Bit patterns for Clock prescale divider values */
+
+#define XWDTPS_CCR_PSCALE_0008  0x00000000U /**< divide clock by 8 */
+#define XWDTPS_CCR_PSCALE_0064  0x00000001U /**< divide clock by 64 */
+#define XWDTPS_CCR_PSCALE_0512  0x00000002U /**< divide clock by 512 */
+#define XWDTPS_CCR_PSCALE_4096  0x00000003U /**< divide clock by 4096 */
+
+/* @} */
+
+/** @name  Restart register
+ * This register resets the timer preventing a timeout. Value is specific
+ * 0x1999
+ * @{
+ */
+
+#define XWDTPS_RESTART_KEY_VAL	0x00001999U /**< valid key */
+
+/*@}*/
+
+/** @name Status register
+ * This register indicates timer reached zero count.
+ * @{
+ */
+#define XWDTPS_SR_WDZ_MASK	0x00000001U /**< time out occurred */
+
+/*@}*/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/****************************************************************************/
+/**
+*
+* Read the given register.
+*
+* @param	BaseAddress is the base address of the device
+* @param	RegOffset is the register offset to be read
+*
+* @return	The 32-bit value of the register
+*
+* @note		C-style signature:
+*		u32 XWdtPs_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+*****************************************************************************/
+#define XWdtPs_ReadReg(BaseAddress, RegOffset) \
+	Xil_In32((BaseAddress) + (u32)(RegOffset))
+
+/****************************************************************************/
+/**
+*
+* Write the given register.
+*
+* @param	BaseAddress is the base address of the device
+* @param	RegOffset is the register offset to be written
+* @param	Data is the 32-bit value to write to the register
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XWdtPs_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+*****************************************************************************/
+#define XWdtPs_WriteReg(BaseAddress, RegOffset, Data) \
+	Xil_Out32((BaseAddress) + (u32)(RegOffset), (u32)(Data))
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_selftest.c
new file mode 100644
index 000000000..bcd5f356b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_selftest.c
@@ -0,0 +1,173 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file xwdtps_selftest.c
+* @addtogroup wdtps_v3_0
+* @{
+*
+* Contains diagnostic self-test functions for the XWdtPs driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- --------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 1.02a sg     08/01/12 Modified it use the Reset Length mask for the self
+*		        test for CR 658287
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xil_types.h"
+#include "xil_assert.h"
+#include "xwdtps.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/****************************************************************************/
+/**
+*
+* Run a self-test on the timebase. This test verifies that the register access
+* locking functions. This is tested by trying to alter a register without
+* setting the key value and verifying that the register contents did not
+* change.
+*
+* @param	InstancePtr is a pointer to the XWdtPs instance.
+*
+* @return
+*		- XST_SUCCESS if self-test was successful.
+*		- XST_FAILURE if self-test was not successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XWdtPs_SelfTest(XWdtPs *InstancePtr)
+{
+	u32 ZmrOrig;
+	u32 ZmrValue1;
+	u32 ZmrValue2;
+	s32 Status;
+
+	/*
+	 * Assert to ensure the inputs are valid and the instance has been
+	 * initialized.
+	 */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
+
+	/*
+	 * Read the ZMR register at start the test.
+	 */
+	ZmrOrig = XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	/*
+	 * EX-OR in the length of the interrupt pulse,
+	 * do not set the key value.
+	 */
+	ZmrValue1 = ZmrOrig ^ (u32)XWDTPS_ZMR_RSTLN_MASK;
+
+
+	/*
+	 * Try to write to register w/o key value then read back.
+	 */
+	XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+			  ZmrValue1);
+
+	ZmrValue2 =	XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+				 XWDTPS_ZMR_OFFSET);
+
+	if (ZmrValue1 == ZmrValue2) {
+		/*
+		 * If the values match, the hw failed the test,
+		 * return orig register value.
+		 */
+		XWdtPs_WriteReg(InstancePtr->Config.BaseAddress,
+				  XWDTPS_ZMR_OFFSET,
+				  (ZmrOrig | (u32)XWDTPS_ZMR_ZKEY_VAL));
+		Status = XST_FAILURE;
+	} else {
+
+
+		/*
+		 * Try to write to register with key value then read back.
+		 */
+		XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+				  (ZmrValue1 | XWDTPS_ZMR_ZKEY_VAL));
+
+		ZmrValue2 =	XWdtPs_ReadReg(InstancePtr->Config.BaseAddress,
+					 XWDTPS_ZMR_OFFSET);
+
+		if (ZmrValue1 != ZmrValue2) {
+			/*
+			 * If the values do not match, the hw failed the test,
+			 * return orig register value.
+			 */
+			XWdtPs_WriteReg(InstancePtr->Config.BaseAddress,
+					  XWDTPS_ZMR_OFFSET,
+					  ZmrOrig | XWDTPS_ZMR_ZKEY_VAL);
+			Status = XST_FAILURE;
+
+		} else {
+
+			/*
+			 * The hardware locking feature is functional, return the original value
+			 * and return success.
+			 */
+			XWdtPs_WriteReg(InstancePtr->Config.BaseAddress, XWDTPS_ZMR_OFFSET,
+					  ZmrOrig | XWDTPS_ZMR_ZKEY_VAL);
+
+			Status = XST_SUCCESS;
+		}
+	}
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_sinit.c
new file mode 100644
index 000000000..f468c9903
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/wdtps_v3_0/src/xwdtps_sinit.c
@@ -0,0 +1,96 @@
+/******************************************************************************
+*
+* Copyright (C) 2010 - 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xwdtps_sinit.c
+* @addtogroup wdtps_v3_0
+* @{
+*
+* This file contains method for static initialization (compile-time) of the
+* driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who    Date     Changes
+* ----- ------ -------- ----------------------------------------------
+* 1.00a ecm/jz 01/15/10 First release
+* 3.00  kvn    02/13/15 Modified code for MISRA-C:2012 compliance.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xwdtps.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+/**************************** Type Definitions *******************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*************************** Variable Definitions ****************************/
+extern XWdtPs_Config XWdtPs_ConfigTable[XPAR_XWDTPS_NUM_INSTANCES];
+
+/************************** Function Prototypes ******************************/
+
+/*****************************************************************************/
+/**
+* Lookup the device configuration based on the unique device ID. The table
+* contains the configuration info for each device in the system.
+*
+* @param	DeviceId is the unique device ID of the device being looked up.
+*
+* @return	A pointer to the configuration table entry corresponding to the
+*		given device ID, or NULL if no match is found.
+*
+* @note		None.
+*
+******************************************************************************/
+XWdtPs_Config *XWdtPs_LookupConfig(u16 DeviceId)
+{
+	XWdtPs_Config *CfgPtr = NULL;
+	u32 Index;
+
+	for (Index = 0U; Index < (u32)XPAR_XWDTPS_NUM_INSTANCES; Index++) {
+		if (XWdtPs_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XWdtPs_ConfigTable[Index];
+			break;
+		}
+	}
+	return (XWdtPs_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/Makefile b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/Makefile
new file mode 100644
index 000000000..9cd372526
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/Makefile
@@ -0,0 +1,40 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+CC_FLAGS = $(COMPILER_FLAGS)
+ECC_FLAGS = $(EXTRA_COMPILER_FLAGS)
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+OUTS = *.o
+
+LIBSOURCES:=*.c
+INCLUDEFILES:=*.h
+
+OBJECTS =	$(addsuffix .o, $(basename $(wildcard *.c)))
+
+libs: banner zdma_libs clean
+
+%.o: %.c
+	${COMPILER} $(CC_FLAGS) $(ECC_FLAGS) $(INCLUDES) -o $@ $<
+
+banner:
+	echo "Compiling zdma"
+
+zdma_libs: ${OBJECTS}
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OBJECTS}
+
+.PHONY: include
+include: zdma_includes
+
+zdma_includes:
+	${CP} ${INCLUDEFILES} ${INCLUDEDIR}
+
+clean:
+	rm -rf ${OBJECTS}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.c
new file mode 100644
index 000000000..c203f585d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.c
@@ -0,0 +1,1275 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma.c
+* @addtogroup zdma_v1_0
+* @{
+*
+* This file contains the implementation of the interface functions for ZDMA
+* driver. Refer to the header file xzdma.h for more detailed information.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+*       vns    16/10/15  Corrected Destination descriptor addresss calculation
+*                        in XZDma_CreateBDList API
+* 1.1   vns    05/11/15  Modified XZDma_SetMode to return XST_FAILURE on
+*                        selecting DMA mode other than normal mode in
+*                        scatter gather mode data transfer and corrected
+*                        XZDma_SetChDataConfig API to set over fetch and
+*                        src issue parameters correctly.
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+
+/************************** Function Prototypes ******************************/
+
+static void StubCallBack(void *CallBackRef, u32 Mask);
+static void StubDoneCallBack(void *CallBackRef);
+static void XZDma_SimpleMode(XZDma *InstancePtr, XZDma_Transfer *Data);
+static void XZDma_ScatterGather(XZDma *InstancePtr, XZDma_Transfer *Data,
+								u32 Num);
+static void XZDma_LinearMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+	XZDma_LiDscr *SrcDscrPtr,XZDma_LiDscr *DstDscrPtr, u8 IsLast);
+static void XZDma_ConfigLinear(XZDma_LiDscr *DscrPtr, u64 Addr, u32 Size,
+								u32 CtrlValue);
+static void XZDma_LinkedListMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+	XZDma_LlDscr *SrcDscrPtr,XZDma_LlDscr *DstDscrPtr, u8 IsLast);
+static void XZDma_ConfigLinkedList(XZDma_LlDscr *DscrPtr, u64 Addr, u32 Size,
+					u32 CtrlValue, u64 NextDscrAddr);
+static void XZDma_Enable(XZDma *InstancePtr);
+static void XZDma_GetConfigurations(XZDma *InstancePtr);
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This function initializes an ZDMA core. This function must be called
+* prior to using an ZDMA core. Initialization of an ZDMA includes setting
+* up the instance data and ensuring the hardware is in a quiescent state and
+* resets all the hardware configurations.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	CfgPtr is a reference to a structure containing information
+*		about a specific XZDma instance.
+* @param	EffectiveAddr is the device base address in the virtual memory
+*		address space. The caller is responsible for keeping the
+*		address mapping from EffectiveAddr to the device physical
+*		base address unchanged once this function is invoked.
+*		Unexpected errors may occur if the address mapping changes
+*		after this function is called. If address translation is not
+*		used, pass in the physical address instead.
+*
+* @return
+*		- XST_SUCCESS if initialization was successful.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr,
+			u32 EffectiveAddr)
+{
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CfgPtr != NULL);
+	Xil_AssertNonvoid(EffectiveAddr != ((u32)0x00));
+
+	InstancePtr->Config.BaseAddress = CfgPtr->BaseAddress;
+	InstancePtr->Config.DeviceId = CfgPtr->DeviceId;
+	InstancePtr->Config.DmaType = CfgPtr->DmaType;
+
+	InstancePtr->Config.BaseAddress = EffectiveAddr;
+
+	InstancePtr->IsReady = (u32)(XIL_COMPONENT_IS_READY);
+
+	InstancePtr->IsSgDma = FALSE;
+	InstancePtr->Mode = XZDMA_NORMAL_MODE;
+	InstancePtr->IntrMask = 0x00U;
+	InstancePtr->ChannelState = XZDMA_IDLE;
+
+	/*
+	 * Set all handlers to stub values, let user configure this
+	 * data later
+	 */
+	InstancePtr->DoneHandler =
+				(XZDma_DoneHandler)((void *)StubDoneCallBack);
+	InstancePtr->ErrorHandler =
+				(XZDma_ErrorHandler)((void *)StubCallBack);
+
+	XZDma_Reset(InstancePtr);
+	XZDma_GetConfigurations(InstancePtr);
+
+	return (XST_SUCCESS);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the pointer type and mode in which ZDMA needs to transfer
+* the data.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	IsSgDma is a variable which specifies whether transfer has to
+*		to be done in scatter gather mode or simple mode.
+*		- TRUE  - Scatter gather pointer type
+*		- FALSE - Simple pointer type
+* @param	Mode is the type of the mode in which data has to be initiated
+*		- XZDMA_NORMAL_MODE   - Normal data transfer from source to
+*					destination (Valid for both Scatter
+*					gather and simple types)
+*		- XZDMA_WRONLY_MODE  - Write only mode (Valid only for Simple)
+*		- XZDMA_RDONLY_MODE  - Read only mode (Valid only for Simple)
+*
+* @return
+*		- XST_SUCCESS - If mode has been set successfully.
+*		- XST_FAILURE - If mode has not been set.
+*
+* @note		Mode cannot be changed while ZDMA is not in IDLE state.
+*
+******************************************************************************/
+s32 XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma, XZDma_Mode Mode)
+{
+	u32 Data;
+	s32 Status;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((IsSgDma == TRUE) || (IsSgDma == FALSE));
+	Xil_AssertNonvoid(Mode <= XZDMA_RDONLY_MODE);
+
+	if (InstancePtr->ChannelState != XZDMA_IDLE) {
+		Status = XST_FAILURE;
+		goto End;
+	}
+	else {
+		Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_CTRL0_OFFSET);
+		/* Simple mode */
+		if (IsSgDma != TRUE) {
+			Data = (Data & (~XZDMA_CTRL0_POINT_TYPE_MASK));
+			if (Mode == XZDMA_NORMAL_MODE) {
+				Data &= (~XZDMA_CTRL0_MODE_MASK);
+			}
+			else if (Mode == XZDMA_WRONLY_MODE) {
+				Data |= XZDMA_CTRL0_WRONLY_MASK;
+			}
+			else {
+				Data |= XZDMA_CTRL0_RDONLY_MASK;
+			}
+			XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_CTRL0_OFFSET, Data);
+			InstancePtr->IsSgDma = FALSE;
+			InstancePtr->Mode = Mode;
+		}
+
+		else {
+			if (Mode != XZDMA_NORMAL_MODE) {
+				Status = XST_FAILURE;
+				goto End;
+			}
+			else {
+				Data |= (XZDMA_CTRL0_POINT_TYPE_MASK);
+				Data &= ~(XZDMA_CTRL0_MODE_MASK);
+				XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_CTRL0_OFFSET, Data);
+
+				InstancePtr->IsSgDma = TRUE;
+				InstancePtr->Mode = Mode;
+			}
+		}
+		Status = XST_SUCCESS;
+	}
+
+End:
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the descriptor type and descriptor pointer's start address
+* of both source and destination based on the memory allocated by user and also
+* calculates no of descriptors(BDs) can be created in the allocated memory.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	TypeOfDscr is a variable which specifies descriptor type
+*		whether Linear or linked list type of descriptor.
+*		- XZDMA_LINEAR    - Linear type of descriptor.
+*		- XZDMA_LINKEDLIST- Linked list type of descriptor.
+* @param	Dscr_MemPtr is a pointer to the allocated memory for creating
+*		descriptors. It Should be aligned to 64 bytes.
+*
+* @param	NoOfBytes specifies the number of bytes allocated for
+*		descriptors
+*
+* @return	The Count of the descriptors can be created.
+*
+* @note		User should allocate the memory for descriptors which should
+*		be capable of how many transfers he wish to do in one start.
+*		For Linear mode each descriptor needs 128 bit memory so for
+*		one data transfer it requires 2*128 = 256 bits i.e. 32 bytes
+*		Similarly for Linked list mode for each descriptor it needs
+*		256 bit, so for one data transfer it require 2*256 = 512 bits
+*		i.e. 64 bytes.
+*
+******************************************************************************/
+u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr,
+					UINTPTR Dscr_MemPtr, u32 NoOfBytes)
+{
+	u32 Size;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid((TypeOfDscr == XZDMA_LINEAR) ||
+					(TypeOfDscr == XZDMA_LINKEDLIST));
+	Xil_AssertNonvoid(Dscr_MemPtr != 0x00);
+	Xil_AssertNonvoid(NoOfBytes != 0x00U);
+
+	InstancePtr->Descriptor.DscrType = TypeOfDscr;
+
+	if (TypeOfDscr == XZDMA_LINEAR) {
+		Size = sizeof(XZDma_LiDscr);
+	}
+	else {
+		Size = sizeof(XZDma_LlDscr);
+	}
+	InstancePtr->Descriptor.DscrCount =
+						(NoOfBytes >> 1) / Size;
+	InstancePtr->Descriptor.SrcDscrPtr = (void *)Dscr_MemPtr;
+	InstancePtr->Descriptor.DstDscrPtr =
+			(void *)Dscr_MemPtr + (Size * InstancePtr->Descriptor.DscrCount);
+
+	Xil_DCacheInvalidateRange((INTPTR)Dscr_MemPtr, NoOfBytes);
+
+	return (InstancePtr->Descriptor.DscrCount);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the data attributes and control configurations of a
+* ZDMA core based on the inputs provided.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Configure is a pointer to the XZDma_ChDataConfig structure
+*		which has all the configuration fields.
+*		The fields of the structure are:
+*		- OverFetch - Allows over fetch or not
+*			- 0 - Not allowed to over-fetch on SRC
+*			- 1 - Allowed to over-fetch on SRC
+*		- SrcIssue  - Outstanding transaction on SRC
+*			- Range is 1 to 32
+*		- SrcBurstType - Burst Type for SRC AXI transaction
+*			- XZDMA_FIXED_BURST - Fixed burst
+*			- XZDMA_INCR_BURST  - Incremental burst
+*		- SrcBurstLen - AXI Length for Data Read.
+*			- Range of values is (1,2,4,8,16).
+*		- DstBurstType - Burst Type for SRC AXI transaction
+*			- XZDMA_FIXED_BURST - Fixed burst
+*			- XZDMA_INCR_BURST - Incremental burst
+*		- DstBurstLen     - AXI Length for Data write.
+*			- Range of values is (1,2,4,8,16).
+*		- SrcCache - AXI cache bits for Data read
+*		- SrcQos - Configurable QoS bits for AXI Data read
+*		- DstCache - AXI cache bits for Data write
+*		- DstQos - configurable QoS bits for AXI Data write
+*
+* @return
+* 		- XST_FAILURE  If ZDMA Core is not in Idle state and
+* 		- XST_SUCCESS If Configurations are made successfully
+*
+* @note
+* 		- These configurations will last till we modify or Reset
+*		  by XZDma_Reset(XZDma *InstancePtr).
+* 		- Configurations should be modified only when ZDMA channel
+* 		  is IDLE this can be confirmed by using
+*		  XZDma_ChannelState(XZDma *InstancePtr) API.
+*
+******************************************************************************/
+s32 XZDma_SetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure)
+{
+	u32 Data;
+	s32 Status;
+
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Configure != NULL);
+
+	if (InstancePtr->ChannelState != XZDMA_IDLE) {
+		Status = XST_FAILURE;
+	}
+	else {
+		InstancePtr->DataConfig.DstBurstType = Configure->DstBurstType;
+		InstancePtr->DataConfig.DstBurstLen = Configure->DstBurstLen;
+		InstancePtr->DataConfig.SrcBurstType = Configure->SrcBurstType;
+		InstancePtr->DataConfig.SrcBurstLen = Configure->SrcBurstLen;
+		InstancePtr->DataConfig.OverFetch = Configure->OverFetch;
+		InstancePtr->DataConfig.SrcIssue = Configure->SrcIssue;
+		InstancePtr->DataConfig.SrcCache = Configure->SrcCache;
+		InstancePtr->DataConfig.SrcQos = Configure->SrcQos;
+		InstancePtr->DataConfig.DstCache = Configure->DstCache;
+		InstancePtr->DataConfig.DstQos = Configure->DstQos;
+
+		/* Setting over fetch */
+		Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_CTRL0_OFFSET) & (~XZDMA_CTRL0_OVR_FETCH_MASK);
+
+		Data |= (((u32)(Configure->OverFetch) <<
+				XZDMA_CTRL0_OVR_FETCH_SHIFT) &
+					XZDMA_CTRL0_OVR_FETCH_MASK);
+
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+					XZDMA_CH_CTRL0_OFFSET, Data);
+
+		/* Setting source issue */
+		Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_CTRL1_OFFSET) & (~XZDMA_CTRL1_SRC_ISSUE_MASK);
+		Data |= (u32)(Configure->SrcIssue & XZDMA_CTRL1_SRC_ISSUE_MASK);
+
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_CTRL1_OFFSET, Data);
+
+		/* Setting Burst length and burst type */
+		Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+						XZDMA_CH_DATA_ATTR_OFFSET);
+		Data = (Data & (~(XZDMA_DATA_ATTR_ARBURST_MASK |
+				 XZDMA_DATA_ATTR_ARLEN_MASK |
+				 XZDMA_DATA_ATTR_AWBURST_MASK |
+				 XZDMA_DATA_ATTR_AWLEN_MASK |
+				 XZDMA_DATA_ATTR_ARCACHE_MASK |
+				 XZDMA_DATA_ATTR_AWCACHE_MASK |
+				 XZDMA_DATA_ATTR_AWQOS_MASK |
+				 XZDMA_DATA_ATTR_ARQOS_MASK)));
+
+		Data |= ((((u32)(Configure->SrcBurstType) <<
+				XZDMA_DATA_ATTR_ARBURST_SHIFT) &
+				XZDMA_DATA_ATTR_ARBURST_MASK) |
+				(((u32)(Configure->SrcCache) <<
+				XZDMA_DATA_ATTR_ARCACHE_SHIFT) &
+				XZDMA_DATA_ATTR_ARCACHE_MASK) |
+				(((u32)(Configure->SrcQos) <<
+				XZDMA_DATA_ATTR_ARQOS_SHIFT) &
+				XZDMA_DATA_ATTR_ARQOS_MASK) |
+			(((u32)(Configure->SrcBurstLen) <<
+				XZDMA_DATA_ATTR_ARLEN_SHIFT) &
+				XZDMA_DATA_ATTR_ARLEN_MASK) |
+			(((u32)(Configure->DstBurstType) <<
+				XZDMA_DATA_ATTR_AWBURST_SHIFT) &
+				XZDMA_DATA_ATTR_AWBURST_MASK) |
+			(((u32)(Configure->DstCache) <<
+				XZDMA_DATA_ATTR_AWCACHE_SHIFT) &
+				XZDMA_DATA_ATTR_AWCACHE_MASK) |
+			(((u32)(Configure->DstQos) <<
+				XZDMA_DATA_ATTR_AWQOS_SHIFT) &
+				XZDMA_DATA_ATTR_AWQOS_MASK) |
+			(((u32)(Configure->DstBurstLen)) &
+				XZDMA_DATA_ATTR_AWLEN_MASK));
+
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+					XZDMA_CH_DATA_ATTR_OFFSET, Data);
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the data attributes and control configurations of a
+* ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Configure is a pointer to the XZDma_ChDataConfig structure
+*		which has all the configuration fields.
+*		The fields of the structure are:
+*		- OverFetch - Allows over fetch or not
+*			- 0 - Not allowed to over-fetch on SRC
+*			- 1 - Allowed to over-fetch on SRC
+*		- SrcIssue  - Outstanding transaction on SRC
+*			- Range is 1 to 32
+*		- SrcBurstType - Burst Type for SRC AXI transaction
+*			- XZDMA_FIXED_BURST - Fixed burst
+*			- XZDMA_INCR_BURST  - Incremental burst
+*		- SrcBurstLen - AXI Length for Data Read.
+*			- Can be max of 16 to be compatible with AXI3
+*		- DstBurstType - Burst Type for SRC AXI transaction
+*			- XZDMA_FIXED_BURST - Fixed burst
+*			- XZDMA_INCR_BURST - Incremental burst
+*		- DstBurstLen     - AXI Length for Data write.
+*			- Can be max of 16 to be compatible with AXI3
+*		- SrcCache - AXI cache bits for Data read
+*		- SrcQos - Configurable QoS bits for AXI Data read
+*		- DstCache - AXI cache bits for Data write
+*		- DstQos - Configurable QoS bits for AXI Data write
+*
+* @return	None
+*
+* @note		None.
+*
+******************************************************************************/
+void XZDma_GetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure)
+{
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Configure != NULL);
+
+	Configure->SrcBurstType = InstancePtr->DataConfig.SrcBurstType;
+	Configure->SrcCache = InstancePtr->DataConfig.SrcCache;
+	Configure->SrcQos = InstancePtr->DataConfig.SrcQos;
+	Configure->SrcBurstLen = InstancePtr->DataConfig.SrcBurstLen;
+
+	Configure->DstBurstType = InstancePtr->DataConfig.DstBurstType;
+	Configure->DstCache = InstancePtr->DataConfig.DstCache;
+	Configure->DstQos = InstancePtr->DataConfig.DstQos;
+	Configure->DstBurstLen = InstancePtr->DataConfig.DstBurstLen;
+
+	Configure->OverFetch = InstancePtr->DataConfig.OverFetch;
+	Configure->SrcIssue = InstancePtr->DataConfig.SrcIssue;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets the descriptor attributes based on the inputs provided
+* in the structure.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Configure is a pointer to the XZDma_ChDscrConfig structure
+*		which has all the configuration fields.
+*		The fields of the structure are:
+*		- AxCoherent - AXI transactions generated for the descriptor.
+*			- 0 - Non coherent
+*			- 1 - Coherent
+*		- AXCache    - AXI cache bit used for DSCR fetch
+*				(both on SRC and DST Side)
+*		- AXQos      - QoS bit used for DSCR fetch
+*				(both on SRC and DST Side)
+*
+* @return
+*		- XST_FAILURE  If ZDMA core is not in Idle state and
+* 		- XST_SUCCESS If Configurations are made successfully
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XZDma_SetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure)
+{
+	u32 Data;
+	s32 Status;
+
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Configure != NULL);
+
+	if (InstancePtr->ChannelState != XZDMA_IDLE) {
+		Status = XST_FAILURE;
+	}
+
+	else {
+		InstancePtr->DscrConfig.AXCache = Configure->AXCache;
+		InstancePtr->DscrConfig.AXQos = Configure->AXQos;
+		InstancePtr->DscrConfig.AxCoherent = Configure->AxCoherent;
+
+		Data = ((((u32)(Configure->AxCoherent) <<
+				XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT) &
+				XZDMA_DSCR_ATTR_AXCOHRNT_MASK) |
+			(((u32)(Configure->AXCache) <<
+				XZDMA_DSCR_ATTR_AXCACHE_SHIFT) &
+				XZDMA_DSCR_ATTR_AXCACHE_MASK) |
+			(((u32)Configure->AXQos) &
+				XZDMA_DSCR_ATTR_AXQOS_MASK));
+
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_DSCR_ATTR_OFFSET, Data);
+
+		Status = XST_SUCCESS;
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This function gets the descriptor attributes of the channel.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Configure is a pointer to the XZDma_ChDscrConfig structure
+*		which has all the configuration fields.
+*		The fields of the structure are:
+*		- AxCoherent - AXI transactions generated for the descriptor.
+*			- 0 - Non coherent
+*			- 1 - Coherent
+*		- AXCache    - AXI cache bit used for DSCR fetch
+*				(both on SRC and DST Side)
+*		- AXQos      - QoS bit used for DSCR fetch
+*				(both on SRC and DST Side)
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+void XZDma_GetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure)
+{
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Configure != NULL);
+
+	Configure->AXCache = InstancePtr->DscrConfig.AXCache;
+	Configure->AXQos = InstancePtr->DscrConfig.AXQos;
+	Configure->AxCoherent = InstancePtr->DscrConfig.AxCoherent;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function preloads the buffers which will be used in write only mode.
+* In write only mode the data in the provided buffer will be written in
+* destination address for specified size.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Buffer is a pointer to an array of 64/128 bit data.
+*		i.e. pointer to 32 bit array of size 2/4
+*		 - Array of Size 2 for ADMA
+*		 - Array of Size 4 for GDMA
+*
+* @return	None.
+*
+* @note		Valid only in simple mode.
+* 		Prior to call this function ZDMA instance should be set in
+* 		Write only mode by using
+*		XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma,
+*							XZDma_Mode Mode)
+*		To initiate data transfer after this API need to call
+*		XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num)
+*		In which only destination fields has to be filled.
+*
+******************************************************************************/
+void XZDma_WOData(XZDma *InstancePtr, u32 *Buffer)
+{
+	u32 *LocBuf = Buffer;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Buffer != NULL);
+
+	if (InstancePtr->Config.DmaType == (u8)0) {
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD0_OFFSET, *LocBuf);
+		LocBuf++;
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD1_OFFSET, *LocBuf);
+		LocBuf++;
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD2_OFFSET, *LocBuf);
+		LocBuf++;
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD3_OFFSET, *LocBuf);
+	}
+
+	else {
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD0_OFFSET, *LocBuf);
+		LocBuf++;
+		XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_WR_ONLY_WORD1_OFFSET, *LocBuf);
+	}
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resume the paused state of ZDMA core and starts the transfer
+* from where it has paused.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		Valid only for scatter gather mode.
+*
+******************************************************************************/
+void XZDma_Resume(XZDma *InstancePtr)
+{
+	u32 Value;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->IsSgDma == TRUE);
+	Xil_AssertVoid(InstancePtr->ChannelState == XZDMA_PAUSE);
+
+	Value = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_CTRL0_OFFSET) & (~XZDMA_CTRL0_CONT_ADDR_MASK);
+	Value |= XZDMA_CTRL0_CONT_MASK;
+	InstancePtr->ChannelState = XZDMA_BUSY;
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_CTRL0_OFFSET, Value);
+}
+
+/*****************************************************************************/
+/**
+*
+* This function resets the ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		This function resets all the configurations made previously.
+*		Disables all the interrupts and clears interrupt status.
+*
+*****************************************************************************/
+void XZDma_Reset(XZDma *InstancePtr)
+{
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(InstancePtr->ChannelState == XZDMA_IDLE);
+
+	/* Disable's the channel */
+	XZDma_DisableCh(InstancePtr);
+
+	/* Disables all interrupts */
+	XZDma_DisableIntr(InstancePtr, XZDMA_IXR_ALL_INTR_MASK);
+	XZDma_IntrClear(InstancePtr, XZDMA_IXR_ALL_INTR_MASK);
+	InstancePtr->IntrMask = 0x00U;
+
+	/* All configurations are being reset */
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
+					XZDMA_CTRL0_RESET_VALUE);
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL1_OFFSET,
+					XZDMA_CTRL1_RESET_VALUE);
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_DATA_ATTR_OFFSET, XZDMA_DATA_ATTR_RESET_VALUE);
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_DSCR_ATTR_OFFSET, XZDMA_DSCR_ATTR_RESET_VALUE);
+
+	/* Clears total byte */
+	XZDma_TotalByteClear(InstancePtr);
+
+	/* Clears interrupt count of both source and destination channels */
+	(void)XZDma_GetSrcIntrCnt(InstancePtr);
+	(void)XZDma_GetDstIntrCnt(InstancePtr);
+
+	InstancePtr->ChannelState = XZDMA_IDLE;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function returns the state of ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	This function returns state of ZDMA core
+*		- XZDMA_IDLE - If ZDMA core is in idle state.
+*		- XZDMA_PAUSE - If ZDMA is in paused state.
+*		- XZDMA_BUSY - If ZDMA is in busy state.
+* @note		None.
+*		C-style signature:
+*		XZDmaState XZDma_ChannelState(XZDma *InstancePtr)
+*
+******************************************************************************/
+XZDmaState XZDma_ChannelState(XZDma *InstancePtr)
+{
+	XZDmaState Status;
+	u32 Value;
+
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	Value = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+			(XZDMA_CH_STS_OFFSET)) & (XZDMA_STS_ALL_MASK);
+
+	if ((Value == XZDMA_STS_DONE_MASK) ||
+			(Value == XZDMA_STS_DONE_ERR_MASK)) {
+		Status = XZDMA_IDLE;
+	}
+	else if (Value == XZDMA_STS_PAUSE_MASK) {
+		Status = XZDMA_PAUSE;
+	}
+	else {
+		Status = XZDMA_BUSY;
+	}
+
+	return Status;
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This function sets all the required fields for initiating data transfer. Data
+* transfer elements needs to be passed through structure pointer.
+* Data transfer can be done in any of the three modes (simple, Linear or Linked
+* List) based on the selected mode but before calling this API make sure that
+* ZDMA is in Idle state.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Data is a pointer of array to the XZDma_Transfer structure which
+*		has all the configuration fields for initiating data transfer.
+*		The fields of the structure are:
+*		- SrcAddr      - Source address
+*		- DstAddr     - Destination address
+*		- Size      - size of the data to be transferred in bytes
+*		- SrcCoherent  - AXI transactions generated to process the
+*				descriptor payload for source channel
+*			- 0 - Non coherent
+*			- 1 - Coherent
+*		- DstCoherent - AXI transactions generated to process the
+*				descriptor payload for destination channel
+*			- 0 - Non coherent
+*			- 1 - Coherent
+*		- Pause 	-  Valid only for scatter gather mode.
+*				Will pause after completion of this descriptor.
+* @param	Num specifies number of array elements of Data pointer.
+*		- For simple mode Num should be equal to 1
+*		- For Scatter gather mode (either linear or linked list) Num
+*		  can be any choice. (But based on which memory should be
+*		  allocated by Application) It should be less than the return
+*		  value of XZDma_CreateBDList.
+*
+* @return
+*		- XST_SUCCESS - if ZDMA initiated the transfer.
+*		- XST_FAILURE - if ZDMA has not initiated data transfer.
+*
+* @note		After Pause to resume the transfer need to use the following
+*		API
+*		- XZDma_Resume
+*		User should provide allocated memory and descriptor type in
+*		scatter gather mode through the following API before calling
+*		the start API.
+*		- XZDma_SetDescriptorType(XZDma *InstancePtr,
+*			XZDma_DscrType TypeOfDscr, UINTPTR Dscr_MemPtr,
+*							u32 NoOfBytes)
+*
+******************************************************************************/
+s32 XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num)
+{
+	s32 Status;
+
+	/* Verify arguments */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(Data != NULL);
+	Xil_AssertNonvoid(Num != 0x00U);
+
+	if ((InstancePtr->ChannelState == XZDMA_BUSY) &&
+			(Num >= InstancePtr->Descriptor.DscrCount)) {
+		Status = XST_FAILURE;
+	}
+	else {
+		if (InstancePtr->IsSgDma != TRUE) {
+			XZDma_SimpleMode(InstancePtr, Data);
+			Status = XST_SUCCESS;
+		}
+		else {
+
+			XZDma_ScatterGather(InstancePtr, Data, Num);
+			Status = XST_SUCCESS;
+		}
+
+		XZDma_Enable(InstancePtr);
+	}
+
+	return Status;
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in simple mode.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Data is a pointer of array to the XZDma_Transfer structure
+*		which has all the configuration fields for initiating data
+*		transfer.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_SimpleMode(XZDma *InstancePtr, XZDma_Transfer *Data)
+{
+
+	u32 Value;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Data != NULL);
+
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_SRC_DSCR_WORD0_OFFSET,
+			(Data->SrcAddr & XZDMA_WORD0_LSB_MASK));
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_SRC_DSCR_WORD1_OFFSET,
+		(((u64)Data->SrcAddr >> XZDMA_WORD1_MSB_SHIFT) &
+		XZDMA_WORD1_MSB_MASK));
+
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_DST_DSCR_WORD0_OFFSET,
+		(Data->DstAddr & XZDMA_WORD0_LSB_MASK));
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_DST_DSCR_WORD1_OFFSET,
+		(((u64)Data->DstAddr >> XZDMA_WORD1_MSB_SHIFT) &
+		XZDMA_WORD1_MSB_MASK));
+
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_SRC_DSCR_WORD2_OFFSET,
+		(Data->Size & XZDMA_WORD2_SIZE_MASK));
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_DST_DSCR_WORD2_OFFSET,
+		(Data->Size & XZDMA_WORD2_SIZE_MASK));
+
+	Value = (u32)(Data->SrcCoherent & XZDMA_WORD3_COHRNT_MASK);
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+		XZDMA_CH_SRC_DSCR_WORD3_OFFSET, Value);
+
+	Value = (u32)(Data->DstCoherent & XZDMA_WORD3_COHRNT_MASK);
+	XZDma_WriteReg((InstancePtr->Config.BaseAddress),
+			XZDMA_CH_DST_DSCR_WORD3_OFFSET, Value);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in scatter gather mode.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Data is a pointer of array to the XZDma_Transfer structure
+*		which has all the configuration fields for initiating data
+*		transfer.
+* @param	Num specifies number of array elements of Data pointer.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_ScatterGather(XZDma *InstancePtr, XZDma_Transfer *Data,
+								u32 Num)
+{
+	u32 Count = 0x00U;
+	u8 Last;
+	XZDma_Transfer *LocalData = Data;
+	XZDma_LiDscr *LiSrcDscr =
+		(XZDma_LiDscr *)(void *)(InstancePtr->Descriptor.SrcDscrPtr);
+	XZDma_LiDscr *LiDstDscr =
+		(XZDma_LiDscr *)(void *)(InstancePtr->Descriptor.DstDscrPtr);
+	XZDma_LlDscr *LlSrcDscr =
+		(XZDma_LlDscr *)(void *)(InstancePtr->Descriptor.SrcDscrPtr);
+	XZDma_LlDscr *LlDstDscr =
+		(XZDma_LlDscr *)(void *)(InstancePtr->Descriptor.DstDscrPtr);
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Data != NULL);
+	Xil_AssertVoid(Num != 0x00U);
+
+	if (InstancePtr->Descriptor.DscrType == XZDMA_LINEAR) {
+		Last = FALSE;
+		do {
+			if (Count == (Num- 1)) {
+				Last = TRUE;
+			}
+			XZDma_LinearMode(InstancePtr, LocalData, LiSrcDscr,
+							LiDstDscr, Last);
+			Count++;
+			LiSrcDscr++;
+			LiDstDscr++;
+			LocalData++;
+		} while(Count < Num);
+	}
+	else {
+		Last = FALSE;
+		do {
+			if (Count == (Num - 1)) {
+				Last = TRUE;
+			}
+			XZDma_LinkedListMode(InstancePtr, LocalData, LlSrcDscr,
+							LlDstDscr, Last);
+			Count++;
+			LlDstDscr++;
+			LlSrcDscr++;
+			LocalData++;
+		} while(Count < Num);
+	}
+
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_SRC_START_LSB_OFFSET,
+		((UINTPTR)(InstancePtr->Descriptor.SrcDscrPtr) &
+					XZDMA_WORD0_LSB_MASK));
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_SRC_START_MSB_OFFSET,
+		(((u64)(UINTPTR)(InstancePtr->Descriptor.SrcDscrPtr) >>
+			XZDMA_WORD1_MSB_SHIFT) & XZDMA_WORD1_MSB_MASK));
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_DST_START_LSB_OFFSET,
+		((UINTPTR)(InstancePtr->Descriptor.DstDscrPtr) &
+					XZDMA_WORD0_LSB_MASK));
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_DST_START_MSB_OFFSET,
+		(((u64)(UINTPTR)(InstancePtr->Descriptor.DstDscrPtr) >>
+			XZDMA_WORD1_MSB_SHIFT) & XZDMA_WORD1_MSB_MASK));
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linear descriptor type.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Data is a pointer of array to the XZDma_Transfer structure which
+*		has all the configuration fields for initiating data transfer.
+* @param	SrcDscrPtr is descriptor pointer of source in which Data fields
+*		has to be filled.
+* @param	DstDscrPtr is descriptor pointer of destination in which Data
+*		fields has to be filled.
+* @param	IsLast specifies whether provided descriptor pointer is last
+*		one or not.
+*		- XZDMA_TRUE - If descriptor is last
+*		- XZDMA_FALSE - If descriptor is not last
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_LinearMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+	XZDma_LiDscr *SrcDscrPtr, XZDma_LiDscr *DstDscrPtr, u8 IsLast)
+{
+	u32 Value;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Data != NULL);
+	Xil_AssertVoid(SrcDscrPtr != NULL);
+	Xil_AssertVoid(DstDscrPtr != NULL);
+	Xil_AssertVoid((IsLast == TRUE) || (IsLast == FALSE));
+
+	if (Data->Pause == TRUE) {
+		Value = XZDMA_WORD3_CMD_PAUSE_MASK;
+	}
+	else if (IsLast == TRUE) {
+		Value = XZDMA_WORD3_CMD_STOP_MASK;
+	}
+	else {
+		Value = XZDMA_WORD3_CMD_NXTVALID_MASK;
+	}
+	if (Data->SrcCoherent == TRUE) {
+		Value |= XZDMA_WORD3_COHRNT_MASK;
+	}
+
+	XZDma_ConfigLinear(SrcDscrPtr, (u64)Data->SrcAddr, Data->Size, Value);
+
+	Value = 0U;
+
+	if (Data->DstCoherent == TRUE) {
+		Value |= XZDMA_WORD3_COHRNT_MASK;
+	}
+
+	XZDma_ConfigLinear(DstDscrPtr, (u64)Data->DstAddr, Data->Size, Value);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linear descriptor type.
+*
+* @param	DscrPtr is a pointer to source/destination descriptor.
+* @param	Addr is a 64 bit variable which denotes the address of data.
+* @param	Size specifies the amount of the data to be transferred.
+* @param	CtrlValue contains all the control fields of descriptor.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_ConfigLinear(XZDma_LiDscr *DscrPtr, u64 Addr, u32 Size,
+								u32 CtrlValue)
+{
+	/* Verify arguments */
+	Xil_AssertVoid(DscrPtr != NULL);
+	Xil_AssertVoid(Addr != 0x00U);
+
+	DscrPtr->Address = Addr;
+	DscrPtr->Size = Size & XZDMA_WORD2_SIZE_MASK;
+	DscrPtr->Cntl = CtrlValue;
+
+	Xil_DCacheFlushRange((UINTPTR)DscrPtr, sizeof(XZDma_LlDscr));
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linked list descriptor type.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Data is a pointer of array to the XZDma_Transfer structure which
+*		has all the configuration fields for initiating data transfer.
+* @param	SrcDscrPtr is descriptor pointer of source in which Data fields
+*		has to be filled.
+* @param	DstDscrPtr is descriptor pointer of destination in which Data
+*		fields has to be filled.
+* @param	IsLast specifies whether provided descriptor pointer is last
+*		one or not.
+*		- TRUE - If descriptor is last
+*		- FALSE - If descriptor is not last
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_LinkedListMode(XZDma *InstancePtr, XZDma_Transfer *Data,
+	XZDma_LlDscr *SrcDscrPtr,XZDma_LlDscr *DstDscrPtr, u8 IsLast)
+{
+	u32 Value;
+	XZDma_LlDscr *NextSrc = SrcDscrPtr;
+	XZDma_LlDscr *NextDst = DstDscrPtr;
+	u64 NextSrcAdrs = 0x00U;
+	u64 NextDstAdrs = 0x00U;
+
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+	Xil_AssertVoid(Data != NULL);
+	Xil_AssertVoid(SrcDscrPtr != NULL);
+	Xil_AssertVoid(DstDscrPtr != NULL);
+	Xil_AssertVoid((IsLast == TRUE) || (IsLast == FALSE));
+
+	NextDst++;
+	NextSrc++;
+
+	if (Data->Pause == TRUE) {
+		Value = XZDMA_WORD3_CMD_PAUSE_MASK;
+		if (IsLast != TRUE) {
+			NextSrcAdrs = (u64)(UINTPTR)NextSrc;
+			NextDstAdrs = (u64)(UINTPTR)NextDst;
+		}
+	}
+	else if (IsLast == TRUE) {
+		Value = XZDMA_WORD3_CMD_STOP_MASK;
+	}
+	else {
+		Value = XZDMA_WORD3_CMD_NXTVALID_MASK;
+		NextSrcAdrs = (u64)(UINTPTR)NextSrc;
+		NextDstAdrs = (u64)(UINTPTR)NextDst;
+	}
+	if (Data->SrcCoherent == TRUE) {
+		Value |= XZDMA_WORD3_COHRNT_MASK;
+	}
+
+	XZDma_ConfigLinkedList(SrcDscrPtr, (u64)Data->SrcAddr,
+					Data->Size, Value, NextSrcAdrs);
+
+	Value = 0U;
+
+	if (Data->DstCoherent == TRUE) {
+		Value |= XZDMA_WORD3_COHRNT_MASK;
+	}
+
+	XZDma_ConfigLinkedList(DstDscrPtr, (u64)Data->DstAddr,
+					Data->Size, Value, NextDstAdrs);
+
+}
+
+/*****************************************************************************/
+/**
+*
+* This static function sets all the required fields for initiating data
+* transfer in Linked list descriptor type.
+*
+* @param	DscrPtr is a pointer to source/destination descriptor.
+* @param	Addr is a 64 bit variable which denotes the address of data.
+* @param	Size specifies the amount of the data to be transferred.
+* @param	CtrlValue contains all the control fields of descriptor.
+* @param	NextDscrAddr is the address of next descriptor.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_ConfigLinkedList(XZDma_LlDscr *DscrPtr, u64 Addr, u32 Size,
+			u32 CtrlValue, u64 NextDscrAddr)
+{
+	/* Verify arguments */
+	Xil_AssertVoid(DscrPtr != NULL);
+	Xil_AssertVoid(Addr != 0x00U);
+
+	DscrPtr->Address = Addr;
+	DscrPtr->Size = Size & XZDMA_WORD2_SIZE_MASK;
+	DscrPtr->Cntl = CtrlValue;
+	DscrPtr->NextDscr = NextDscrAddr;
+	DscrPtr->Reserved = 0U;
+
+	Xil_DCacheFlushRange((UINTPTR)DscrPtr, sizeof(XZDma_LlDscr));
+}
+
+/*****************************************************************************/
+/**
+* This static function enable's all the interrupts which user intended to
+* enable and enables the ZDMA channel for initiating data transfer.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+
+static void XZDma_Enable(XZDma *InstancePtr)
+{
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_IEN_OFFSET,
+			(InstancePtr->IntrMask & XZDMA_IXR_ALL_INTR_MASK));
+	InstancePtr->ChannelState = XZDMA_BUSY;
+	XZDma_EnableCh(InstancePtr);
+
+}
+
+/*****************************************************************************/
+/**
+* This static function gets all the reset configurations of ZDMA.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void XZDma_GetConfigurations(XZDma *InstancePtr)
+{
+	/* Verify arguments */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	InstancePtr->DataConfig.SrcIssue = (u8)XZDMA_CTRL1_SRC_ISSUE_MASK;
+	InstancePtr->DataConfig.SrcBurstType = XZDMA_INCR_BURST;
+	InstancePtr->DataConfig.SrcBurstLen = 0xFU;
+	InstancePtr->DataConfig.OverFetch = 1U;
+	InstancePtr->DataConfig.DstBurstType = XZDMA_INCR_BURST;
+	InstancePtr->DataConfig.DstBurstLen = 0xFU;
+	InstancePtr->DataConfig.SrcCache = 0x2U;
+	InstancePtr->DataConfig.DstCache = 0x2U;
+	InstancePtr->DataConfig.SrcQos = 0x0U;
+	InstancePtr->DataConfig.DstQos = 0x0U;
+
+	InstancePtr->DscrConfig.AXCache = 0U;
+	InstancePtr->DscrConfig.AXQos = 0U;
+	InstancePtr->DscrConfig.AxCoherent = 0U;
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine is a stub for the asynchronous callbacks. The stub is here in
+* case the upper layer forgot to set the handlers. On initialization, All
+* handlers are set to this callback. It is considered an error for this
+* handler to be invoked.
+*
+* @param	CallBackRef is a callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked.
+* @param	Mask is the type of the interrupts to enable. Use OR'ing of
+*		XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+*		this parameter value.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubCallBack(void *CallBackRef, u32 Mask)
+{
+	/* Verify arguments. */
+	Xil_AssertVoid(CallBackRef != NULL);
+	Xil_AssertVoid(Mask != (u32)0x00);
+	Xil_AssertVoidAlways();
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine is a stub for the DMA done callback. The stub is here in
+* case the upper layer forgot to set the handlers. On initialization, Done
+* handler are set to this callback.
+*
+* @param	CallBackRef is a callback reference passed in by the upper
+*		layer when setting the callback functions, and passed back to
+*		the upper layer when the callback is invoked.
+*
+* @return	None.
+*
+* @note		None.
+*
+******************************************************************************/
+static void StubDoneCallBack(void *CallBackRef)
+{
+	/* Verify arguments. */
+	Xil_AssertVoid(CallBackRef != NULL);
+	Xil_AssertVoidAlways();
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.h
new file mode 100644
index 000000000..1f268d43c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma.h
@@ -0,0 +1,681 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma.h
+* @addtogroup zdma_v1_0
+* @{
+* @details
+*
+* ZDMA is a general purpose DMA designed to support memory to memory and memory
+* to IO buffer transfers. ALTO has two instance of general purpose ZDMA.
+* One is located in FPD (full power domain) which is GDMA and other is located
+* in LPD (low power domain) which is ADMA.
+*
+* GMDA & ADMA are configured each with 8 DMA channels and and each channel can
+* be programmed secure or non-secure.
+* Each channel is divided into two functional sides, Source (Read) and
+* Destination (Write). Each DMA channel can be independently programmed
+* in one of following DMA modes.
+*	- Simple DMA
+*		- Normal data transfer from source to destination.
+*		- Write Only mode.
+*		- Read Only mode.
+*	- Scatter Gather DMA
+*		- Only Normal mode it can't support other two modes.
+* In Scatter gather descriptor can be of 3 types
+*	- Linear descriptor.
+*	- Linked list descriptor
+*	- Hybrid descriptor (Combination of both Linear and Linked list)
+* Our driver will not support Hybrid type of descriptor.
+*
+* Initialization & Configuration
+*
+* The device driver enables higher layer software (e.g., an application) to
+* communicate to the ZDMA core.
+*
+* XZDma_CfgInitialize() API is used to initialize the ZDMA core.
+* The user needs to first call the XZDma_LookupConfig() API which returns
+* the Configuration structure pointer which is passed as a parameter to the
+* XZDma_CfgInitialize() API.
+*
+*  Interrupts 
+* The driver provides an interrupt handler XZDma_IntrHandler for handling
+* the interrupt from the ZDMA core. The users of this driver have to
+* register this handler with the interrupt system and provide the callback
+* functions by using XZDma_SetCallBack API. In this version Descriptor done
+* option is disabled.
+*
+*  Virtual Memory 
+*
+* This driver supports Virtual Memory. The RTOS is responsible for calculating
+* the correct device base address in Virtual Memory space.
+*
+*  Threads 
+*
+* This driver is not thread safe. Any needs for threads or thread mutual
+* exclusion must be satisfied by the layer above this driver.
+*
+*  Asserts 
+*
+* Asserts are used within all Xilinx drivers to enforce constraints on argument
+* values. Asserts can be turned off on a system-wide basis by defining, at
+* compile time, the NDEBUG identifier. By default, asserts are turned on and it
+* is recommended that users leave asserts on during development.
+*
+*  Building the driver 
+*
+* The XZDma driver is composed of several source files. This allows the user
+* to build and link only those parts of the driver that are necessary.
+*
+* This header file contains identifiers and register-level driver functions (or
+* macros), range macros, structure typedefs that can be used to access the
+* Xilinx ZDMA core instance.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+* 1.1   vns    15/02/16  Corrected Destination descriptor addresss calculation
+*                        in XZDma_CreateBDList API
+*                        Modified XZDma_SetMode to return XST_FAILURE on
+*                        selecting DMA mode other than normal mode in
+*                        scatter gather mode data transfer and corrected
+*                        XZDma_SetChDataConfig API to set over fetch and
+*                        src issue parameters correctly.
+
+* 

+*
+******************************************************************************/
+#ifndef XZDMA_H_
+#define XZDMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xzdma_hw.h"
+#include "xil_assert.h"
+#include "xstatus.h"
+#include "xil_cache.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/**************************** Type Definitions *******************************/
+
+/** @name ZDMA Handler Types
+ * @{
+ */
+typedef enum {
+	XZDMA_HANDLER_DONE,	/**< For Done Handler */
+	XZDMA_HANDLER_ERROR,	/**< For Error Handler */
+} XZDma_Handler;
+/*@}*/
+
+/** @name ZDMA Descriptors Types
+ * @{
+ */
+typedef enum {
+	XZDMA_LINEAR,		/**< Linear descriptor */
+	XZDMA_LINKEDLIST,	/**< Linked list descriptor */
+} XZDma_DscrType;
+/*@}*/
+
+/** @name ZDMA Operation modes
+ * @{
+ */
+typedef enum {
+	XZDMA_NORMAL_MODE,	/**< Normal transfer from source to
+				  *  destination*/
+	XZDMA_WRONLY_MODE,	/**< Write only mode */
+	XZDMA_RDONLY_MODE	/**< Read only mode */
+} XZDma_Mode;
+/*@}*/
+
+/** @name ZDMA state
+ * @{
+ */
+typedef enum {
+	XZDMA_IDLE,		/**< ZDMA is in Idle state */
+	XZDMA_PAUSE,		/**< Paused state */
+	XZDMA_BUSY,		/**< Busy state */
+} XZDmaState;
+/*@}*/
+
+/** @name ZDMA AXI Burst type
+ * @{
+ */
+typedef enum {
+	XZDMA_FIXED_BURST = 0,	/**< Fixed burst type */
+	XZDMA_INCR_BURST	/**< Increment burst type */
+} XZDma_BurstType;
+/*@}*/
+
+/******************************************************************************/
+/**
+* This typedef contains scatter gather descriptor fields for ZDMA core.
+*/
+typedef struct {
+	void *SrcDscrPtr;	/**< Source Descriptor pointer */
+	void *DstDscrPtr;	/**< Destination Descriptor pointer */
+	u32 DscrCount;		/**< Count of descriptors available */
+	XZDma_DscrType DscrType;/**< Type of descriptor either Linear or
+				  *  Linked list type */
+} XZDma_Descriptor;
+
+/******************************************************************************/
+/**
+* This typedef contains scatter gather descriptor fields for ZDMA core.
+*/
+typedef struct {
+	u64 Address;	/**< Address */
+	u32 Size;	/**< Word2, Size of data */
+	u32 Cntl;	/**< Word3 Control data */
+	u64 NextDscr; 	/**< Address of next descriptor */
+	u64 Reserved;	/**< Reserved address */
+} __attribute__ ((packed)) XZDma_LlDscr;
+
+/******************************************************************************/
+/**
+* This typedef contains Linear descriptor fields for ZDMA core.
+*/
+typedef struct {
+	u64 Address;	/**< Address */
+	u32 Size;	/**< Word3, Size of data */
+	u32 Cntl;	/**< Word4, control data */
+}  __attribute__ ((packed)) XZDma_LiDscr;
+
+/******************************************************************************/
+/**
+*
+* This typedef contains the data configurations of ZDMA core
+*/
+typedef struct {
+	u8 OverFetch;		/**< Enable Over fetch */
+	u8 SrcIssue;		/**< Outstanding transactions for Source */
+	XZDma_BurstType SrcBurstType;
+				/**< Burst type for SRC */
+	u8 SrcBurstLen;		/**< AXI length for data read */
+	XZDma_BurstType DstBurstType;
+				/**< Burst type for DST */
+	u8 DstBurstLen;		/**< AXI length for data write */
+	u8 SrcCache;		/**< AXI cache bits for data read */
+	u8 SrcQos;		/**< AXI QOS bits for data read */
+	u8 DstCache;		/**< AXI cache bits for data write */
+	u8 DstQos;		/**< AXI QOS bits for data write */
+} XZDma_DataConfig;
+
+/******************************************************************************/
+/**
+*
+* This typedef contains the descriptor configurations of ZDMA core
+*/
+typedef struct{
+	u8 AxCoherent;	/**< AXI transactions are coherent or non-coherent */
+	u8 AXCache;	/**< AXI cache for DSCR fetch */
+	u8 AXQos;	/**< Qos bit for DSCR fetch */
+} XZDma_DscrConfig;
+
+/******************************************************************************/
+/**
+* Callback type for Completion of all data transfers.
+*
+* @param 	CallBackRef is a callback reference passed in by the upper layer
+*		when setting the callback functions, and passed back to the
+*		upper layer when the callback is invoked.
+*******************************************************************************/
+typedef void (*XZDma_DoneHandler) (void *CallBackRef);
+
+/******************************************************************************/
+/**
+* Callback type for all error interrupts.
+*
+* @param 	CallBackRef is a callback reference passed in by the upper layer
+*		when setting the callback functions, and passed back to the
+*		upper layer when the callback is invoked.
+* @param	ErrorMask is a bit mask indicating the cause of the error. Its
+*		value equals 'OR'ing one or more XZDMA_IXR_* values defined in
+*		xzdma_hw.h
+****************************************************************************/
+typedef void (*XZDma_ErrorHandler) (void *CallBackRef, u32 ErrorMask);
+
+/**
+* This typedef contains configuration information for a ZDMA core
+* Each ZDMA core should have a configuration structure associated.
+*/
+typedef struct {
+	u16 DeviceId;		/**< Device Id of ZDMA */
+	u32 BaseAddress;	/**< BaseAddress of ZDMA */
+	u8 DmaType;		/**< Type of DMA */
+} XZDma_Config;
+
+/******************************************************************************/
+/**
+*
+* The XZDma driver instance data structure. A pointer to an instance data
+* structure is passed around by functions to refer to a specific driver
+* instance.
+*/
+typedef struct {
+	XZDma_Config Config;	/**< Hardware configuration */
+	u32 IsReady;		/**< Device and the driver instance
+				  *  are initialized */
+	u32 IntrMask;		/**< Mask for enabling interrupts */
+
+	XZDma_Mode Mode;	/**< Mode of ZDMA core to be operated */
+	u8 IsSgDma;		/**< Is ZDMA core is in scatter gather or
+				  *  not will be specified */
+	XZDma_Descriptor Descriptor;	/**< It contains information about
+					  * descriptors */
+
+	XZDma_DoneHandler DoneHandler;	/**< Call back for transfer
+					  *  done interrupt */
+	void *DoneRef;			/**< To be passed to the done
+					  * interrupt callback */
+
+	XZDma_ErrorHandler ErrorHandler;/**< Call back for error
+					  *  interrupt */
+	void *ErrorRef;			/**< To be passed to the error
+					  * interrupt callback */
+	XZDma_DataConfig DataConfig;	/**< Current configurations */
+	XZDma_DscrConfig DscrConfig;	/**< Current configurations */
+	XZDmaState ChannelState;	 /**< ZDMA channel is busy */
+
+} XZDma;
+
+/******************************************************************************/
+/**
+*
+* This typedef contains the fields for transfer of data.
+*/
+typedef struct {
+	UINTPTR SrcAddr;	/**< Source address */
+	UINTPTR DstAddr;	/**< Destination Address */
+	u32 Size;		/**< Size of the data to be transferred */
+	u8 SrcCoherent;		/**< Source coherent */
+	u8 DstCoherent;		/**< Destination coherent */
+	u8 Pause;		/**< Will pause data transmission after
+				  *  this transfer only for SG mode */
+} XZDma_Transfer;
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+/*****************************************************************************/
+/**
+*
+* This function returns interrupt status read from Interrupt Status Register.
+* Use the XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to interpret the
+* returned value.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	The pending interrupts of the ZDMA core.
+*		Use the masks specified in xzdma_hw.h to interpret
+*		the returned value.
+* @note
+* 		C-style signature:
+*		void XZDma_IntrGetStatus(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_IntrGetStatus(InstancePtr) \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, XZDMA_CH_ISR_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears interrupt(s). Every bit set in Interrupt Status
+* Register indicates that a specific type of interrupt is occurring, and this
+* function clears one or more interrupts by writing a bit mask to Interrupt
+* Clear Register.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Mask is the type of the interrupts to enable. Use OR'ing of
+*		XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+*		this parameter value.
+*
+* @return	None.
+*
+* @note
+* 		C-style signature:
+*		void XZDma_IntrClear(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_IntrClear(InstancePtr, Mask) \
+	XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_ISR_OFFSET, ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function returns interrupt mask to know which interrupts are
+* enabled and which of them were disabled.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	The current interrupt mask. The mask indicates which interrupts
+*		are enabled/disabled.
+*		0 bit represents .....corresponding interrupt is enabled.
+*		1 bit represents .....Corresponding interrupt is disabled.
+*
+* @note
+* 		C-style signature:
+*		void XZDma_GetIntrMask(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetIntrMask(InstancePtr) \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress,  \
+			(u32)(XZDMA_CH_IMR_OFFSET))
+
+/*****************************************************************************/
+/**
+*
+* This function enables individual interrupts of the ZDMA core by updating
+* the Interrupt Enable register.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Mask is the type of the interrupts to enable. Use OR'ing of
+*		XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+*		this parameter value.
+*
+* @return	None.
+*
+* @note		The existing enabled interrupt(s) will remain enabled.
+* 		C-style signature:
+*		void XZDma_EnableIntr(XZDma *InstancePtr, u32 Mask)
+*
+******************************************************************************/
+#define XZDma_EnableIntr(InstancePtr, Mask) \
+	(InstancePtr)->IntrMask = ((InstancePtr)->IntrMask | (Mask))
+
+/*****************************************************************************/
+/**
+*
+* This function disables individual interrupts of the ZDMA core by updating
+* the Interrupt Disable register.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+* @param	Mask is the type of the interrupts to disable. Use OR'ing of
+*		XZDMA_IXR_DMA_*_MASK constants defined in xzdma_hw.h to create
+*		this parameter value.
+*
+* @return	None.
+*
+* @note		The existing disabled interrupt(s) will remain disabled.
+* 		C-style signature:
+*		void XZDma_DisableIntr(XZDma *InstancePtr, u32 Mask)
+*
+******************************************************************************/
+#define XZDma_DisableIntr(InstancePtr, Mask) \
+	XZDma_WriteReg( (InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_IDS_OFFSET, \
+	((u32)XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_IDS_OFFSET) | ((u32)(Mask) & (u32)XZDMA_IXR_ALL_INTR_MASK)))
+
+/*****************************************************************************/
+/**
+*
+* This function returns source current payload address under process
+* of ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		This address may not be precise due to ZDMA pipeline structure
+*		C-style signature:
+*		u64 XZDma_SrcCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_SrcCurPyld(InstancePtr) \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET)) | \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function returns destination current payload address under process
+* of ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		This address may not be precise due to ZDMA pipeline structure
+*		C-style signature:
+*		u64 XZDma_DstCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_DstCurPyld(InstancePtr) \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET)) | \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function returns source descriptor current payload address under
+* process of ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		This address may not be precise due to ZDMA pipeline structure
+*		C-style signature:
+*		u64 XZDma_SrcDscrCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_SrcDscrCurPyld(InstancePtr) \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET)) | \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+
+/*****************************************************************************/
+/**
+*
+* This function returns destination descriptor current payload address under
+* process of ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		This address may not be precise due to ZDMA pipeline structure
+*		C-style signature:
+*		u64 XZDma_DstDscrCurPyld(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_DstDscrCurPyld(InstancePtr) \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET)) | \
+	((u64)(XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+	XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET)) << XZDMA_WORD1_MSB_SHIFT))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the count of total bytes transferred through core
+* since last clear in ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note
+*		C-style signature:
+*		void XZDma_GetTotalByte(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetTotalByte(InstancePtr) \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_TOTAL_BYTE_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function clears the count of total bytes transferred in ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note
+*		C-style signature:
+*		void XZDma_TotalByteClear(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_TotalByteClear(InstancePtr) \
+	XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
+		XZDMA_CH_TOTAL_BYTE_OFFSET, \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+		XZDMA_CH_TOTAL_BYTE_OFFSET))
+
+/*****************************************************************************/
+/**
+*
+* This function gets the total number of Interrupt count for source after last
+* call of this API.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		Once this API is called then count will become zero.
+*		C-style signature:
+*		void XZDma_GetSrcIntrCnt(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetSrcIntrCnt(InstancePtr) \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_IRQ_SRC_ACCT_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function gets the total number of Interrupt count for destination
+* after last call of this API.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		Once this API is called then count will become zero.
+*		C-style signature:
+*		void XZDma_GetDstIntrCnt(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_GetDstIntrCnt(InstancePtr) \
+	XZDma_ReadReg((InstancePtr)->Config.BaseAddress, \
+			XZDMA_CH_IRQ_DST_ACCT_OFFSET)
+
+/*****************************************************************************/
+/**
+*
+* This function Enable's the ZDMA core for initiating the data transfer once the
+* data transfer completes it will be automatically disabled.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		None.
+*		C-style signature:
+*		void XZDma_EnableCh(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_EnableCh(InstancePtr) \
+	XZDma_WriteReg((InstancePtr)->Config.BaseAddress, \
+			(XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_EN_MASK))
+
+/*****************************************************************************/
+/**
+*
+* This function Disable's the ZDMA core.
+*
+* @param	InstancePtr is a pointer to the XZDma instance.
+*
+* @return	None.
+*
+* @note		None.
+*		C-style signature:
+*		void XZDma_DisableCh(XZDma *InstancePtr)
+*
+******************************************************************************/
+#define XZDma_DisableCh(InstancePtr) \
+	XZDma_WriteReg((InstancePtr)->Config.BaseAddress,\
+		(XZDMA_CH_CTRL2_OFFSET), (XZDMA_CH_CTRL2_DIS_MASK))
+
+/************************ Prototypes of functions **************************/
+
+XZDma_Config *XZDma_LookupConfig(u16 DeviceId);
+
+s32 XZDma_CfgInitialize(XZDma *InstancePtr, XZDma_Config *CfgPtr,
+			u32 EffectiveAddr);
+s32 XZDma_SetMode(XZDma *InstancePtr, u8 IsSgDma, XZDma_Mode Mode);
+u32 XZDma_CreateBDList(XZDma *InstancePtr, XZDma_DscrType TypeOfDscr,
+					UINTPTR Dscr_MemPtr, u32 NoOfBytes);
+s32 XZDma_SetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
+void XZDma_GetChDataConfig(XZDma *InstancePtr, XZDma_DataConfig *Configure);
+s32 XZDma_SetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
+void XZDma_GetChDscrConfig(XZDma *InstancePtr, XZDma_DscrConfig *Configure);
+s32 XZDma_Start(XZDma *InstancePtr, XZDma_Transfer *Data, u32 Num);
+void XZDma_WOData(XZDma *InstancePtr, u32 *Buffer);
+void XZDma_Resume(XZDma *InstancePtr);
+void XZDma_Reset(XZDma *InstancePtr);
+XZDmaState XZDma_ChannelState(XZDma *InstancePtr);
+
+s32 XZDma_SelfTest(XZDma *InstancePtr);
+
+void XZDma_IntrHandler(void *Instance);
+s32 XZDma_SetCallBack(XZDma *InstancePtr, XZDma_Handler HandlerType,
+	void *CallBackFunc, void *CallBackRef);
+
+/*@}*/
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif /* XZDMA_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c
new file mode 100644
index 000000000..33202264d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_g.c
@@ -0,0 +1,131 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by HSI.
+* Version: 
+* DO NOT EDIT.
+*
+* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
+*Permission is hereby granted, free of charge, to any person obtaining a copy
+*of this software and associated documentation files (the Software), to deal
+*in the Software without restriction, including without limitation the rights
+*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+*copies of the Software, and to permit persons to whom the Software is
+*furnished to do so, subject to the following conditions:
+*
+*The above copyright notice and this permission notice shall be included in
+*all copies or substantial portions of the Software.
+* 
+* Use of the Software is limited solely to applications:
+*(a) running on a Xilinx device, or
+*(b) that interact with a Xilinx device through a bus or interconnect.
+*
+*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 
+*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
+*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*
+*Except as contained in this notice, the name of the Xilinx shall not be used
+*in advertising or otherwise to promote the sale, use or other dealings in
+*this Software without prior written authorization from Xilinx.
+*
+
+* 
+* Description: Driver configuration
+*
+*******************************************************************/
+
+#include "xparameters.h"
+#include "xzdma.h"
+
+/*
+* The configuration table for devices
+*/
+
+XZDma_Config XZDma_ConfigTable[] =
+{
+	{
+		XPAR_PSU_ADMA_0_DEVICE_ID,
+		XPAR_PSU_ADMA_0_BASEADDR,
+		XPAR_PSU_ADMA_0_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_1_DEVICE_ID,
+		XPAR_PSU_ADMA_1_BASEADDR,
+		XPAR_PSU_ADMA_1_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_2_DEVICE_ID,
+		XPAR_PSU_ADMA_2_BASEADDR,
+		XPAR_PSU_ADMA_2_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_3_DEVICE_ID,
+		XPAR_PSU_ADMA_3_BASEADDR,
+		XPAR_PSU_ADMA_3_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_4_DEVICE_ID,
+		XPAR_PSU_ADMA_4_BASEADDR,
+		XPAR_PSU_ADMA_4_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_5_DEVICE_ID,
+		XPAR_PSU_ADMA_5_BASEADDR,
+		XPAR_PSU_ADMA_5_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_6_DEVICE_ID,
+		XPAR_PSU_ADMA_6_BASEADDR,
+		XPAR_PSU_ADMA_6_DMA_MODE
+	},
+	{
+		XPAR_PSU_ADMA_7_DEVICE_ID,
+		XPAR_PSU_ADMA_7_BASEADDR,
+		XPAR_PSU_ADMA_7_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_0_DEVICE_ID,
+		XPAR_PSU_GDMA_0_BASEADDR,
+		XPAR_PSU_GDMA_0_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_1_DEVICE_ID,
+		XPAR_PSU_GDMA_1_BASEADDR,
+		XPAR_PSU_GDMA_1_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_2_DEVICE_ID,
+		XPAR_PSU_GDMA_2_BASEADDR,
+		XPAR_PSU_GDMA_2_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_3_DEVICE_ID,
+		XPAR_PSU_GDMA_3_BASEADDR,
+		XPAR_PSU_GDMA_3_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_4_DEVICE_ID,
+		XPAR_PSU_GDMA_4_BASEADDR,
+		XPAR_PSU_GDMA_4_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_5_DEVICE_ID,
+		XPAR_PSU_GDMA_5_BASEADDR,
+		XPAR_PSU_GDMA_5_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_6_DEVICE_ID,
+		XPAR_PSU_GDMA_6_BASEADDR,
+		XPAR_PSU_GDMA_6_DMA_MODE
+	},
+	{
+		XPAR_PSU_GDMA_7_DEVICE_ID,
+		XPAR_PSU_GDMA_7_BASEADDR,
+		XPAR_PSU_GDMA_7_DMA_MODE
+	}
+};
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_hw.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_hw.h
new file mode 100644
index 000000000..85f630228
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_hw.h
@@ -0,0 +1,383 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_hw.h
+* @addtogroup zdma_v1_0
+* @{
+*
+* This header file contains identifiers and register-level driver functions (or
+* macros) that can be used to access the Xilinx ZDMA core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+* 

+*
+******************************************************************************/
+#ifndef XZDMA_HW_H_
+#define XZDMA_HW_H_		/**< Prevent circular inclusions
+				  *  by using protection macros	*/
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************** Include Files *********************************/
+
+#include "xil_io.h"
+
+/************************** Constant Definitions *****************************/
+
+/** @name Registers offsets
+ * @{
+ */
+#define XZDMA_ERR_CTRL				(0x000U)
+#define XZDMA_CH_ECO				(0x004U)
+#define XZDMA_CH_ISR_OFFSET			(0x100U)
+#define XZDMA_CH_IMR_OFFSET			(0x104U)
+#define XZDMA_CH_IEN_OFFSET			(0x108U)
+#define XZDMA_CH_IDS_OFFSET			(0x10CU)
+#define XZDMA_CH_CTRL0_OFFSET			(0x110U)
+#define XZDMA_CH_CTRL1_OFFSET			(0x114U)
+#define XZDMA_CH_PERIF_OFFSET			(0x118U)
+#define XZDMA_CH_STS_OFFSET			(0x11CU)
+#define XZDMA_CH_DATA_ATTR_OFFSET		(0x120U)
+#define XZDMA_CH_DSCR_ATTR_OFFSET		(0x124U)
+#define XZDMA_CH_SRC_DSCR_WORD0_OFFSET		(0x128U)
+#define XZDMA_CH_SRC_DSCR_WORD1_OFFSET		(0x12CU)
+#define XZDMA_CH_SRC_DSCR_WORD2_OFFSET		(0x130U)
+#define XZDMA_CH_SRC_DSCR_WORD3_OFFSET		(0x134U)
+#define XZDMA_CH_DST_DSCR_WORD0_OFFSET		(0x138U)
+#define XZDMA_CH_DST_DSCR_WORD1_OFFSET		(0x13CU)
+#define XZDMA_CH_DST_DSCR_WORD2_OFFSET		(0x140U)
+#define XZDMA_CH_DST_DSCR_WORD3_OFFSET		(0x144U)
+#define XZDMA_CH_WR_ONLY_WORD0_OFFSET		(0x148U)
+#define XZDMA_CH_WR_ONLY_WORD1_OFFSET		(0x14CU)
+#define XZDMA_CH_WR_ONLY_WORD2_OFFSET		(0x150U)
+#define XZDMA_CH_WR_ONLY_WORD3_OFFSET		(0x154U)
+#define XZDMA_CH_SRC_START_LSB_OFFSET		(0x158U)
+#define XZDMA_CH_SRC_START_MSB_OFFSET		(0x15CU)
+#define XZDMA_CH_DST_START_LSB_OFFSET		(0x160U)
+#define XZDMA_CH_DST_START_MSB_OFFSET		(0x164U)
+#define XZDMA_CH_SRC_CUR_PYLD_LSB_OFFSET	(0x168U)
+#define XZDMA_CH_SRC_CUR_PYLD_MSB_OFFSET	(0x16CU)
+#define XZDMA_CH_DST_CUR_PYLD_LSB_OFFSET	(0x170U)
+#define XZDMA_CH_DST_CUR_PYLD_MSB_OFFSET	(0x174U)
+#define XZDMA_CH_SRC_CUR_DSCR_LSB_OFFSET	(0x178U)
+#define XZDMA_CH_SRC_CUR_DSCR_MSB_OFFSET	(0x17CU)
+#define XZDMA_CH_DST_CUR_DSCR_LSB_OFFSET	(0x180U)
+#define XZDMA_CH_DST_CUR_DSCR_MSB_OFFSET	(0x184U)
+#define XZDMA_CH_TOTAL_BYTE_OFFSET		(0x188U)
+#define XZDMA_CH_RATE_CNTL_OFFSET		(0x18CU)
+#define XZDMA_CH_IRQ_SRC_ACCT_OFFSET		(0x190U)
+#define XZDMA_CH_IRQ_DST_ACCT_OFFSET		(0x194U)
+#define XZDMA_CH_CTRL2_OFFSET			(0x200U)
+/*@}*/
+
+/** @name Interrupt Enable/Disable/Mask/Status registers bit masks and shifts
+ * @{
+ */
+#define XZDMA_IXR_DMA_PAUSE_MASK	(0x00000800U) /**< IXR pause mask */
+#define XZDMA_IXR_DMA_DONE_MASK		(0x00000400U) /**< IXR done mask */
+#define XZDMA_IXR_AXI_WR_DATA_MASK	(0x00000200U) /**< IXR AXI write data
+							*  error mask */
+#define XZDMA_IXR_AXI_RD_DATA_MASK	(0x00000100U) /**< IXR AXI read data
+							*  error mask */
+#define XZDMA_IXR_AXI_RD_DST_DSCR_MASK	(0x00000080U) /**< IXR AXI read
+							*  descriptor error
+							*  mask */
+#define XZDMA_IXR_AXI_RD_SRC_DSCR_MASK	(0x00000040U) /**< IXR AXI write
+							*  descriptor error
+							*  mask */
+#define XZDMA_IXR_DST_ACCT_ERR_MASK	(0x00000020U) /**< IXR DST interrupt
+							*  count overflow
+							*  mask */
+#define XZDMA_IXR_SRC_ACCT_ERR_MASK	(0x00000010U) /**< IXR SRC interrupt
+							*  count overflow
+							*  mask */
+#define XZDMA_IXR_BYTE_CNT_OVRFL_MASK	(0x00000008U) /**< IXR byte count over
+							* flow mask */
+#define XZDMA_IXR_DST_DSCR_DONE_MASK	(0x00000004U) /**< IXR destination
+							*  descriptor done
+							*  mask */
+#define XZDMA_IXR_SRC_DSCR_DONE_MASK	(0x00000002U) /**< IXR source
+							*  descriptor done
+							*  mask */
+#define XZDMA_IXR_INV_APB_MASK		(0x00000001U) /**< IXR invalid APB
+							*  access mask */
+#define XZDMA_IXR_ALL_INTR_MASK		(0x00000FFFU) /**< IXR OR of all the
+							*  interrupts mask */
+#define XZDMA_IXR_DONE_MASK		(0x00000400U) /**< IXR All done mask */
+
+#define XZDMA_IXR_ERR_MASK		(0x00000BF9U) /**< IXR all Error mask*/
+					/**< Or of XZDMA_IXR_AXI_WR_DATA_MASK,
+					  * XZDMA_IXR_AXI_RD_DATA_MASK,
+					  * XZDMA_IXR_AXI_RD_DST_DSCR_MASK,
+					  * XZDMA_IXR_AXI_RD_SRC_DSCR_MASK,
+					  * XZDMA_IXR_INV_APB_MASK,
+					  * XZDMA_IXR_DMA_PAUSE_MASK,
+					  * XZDMA_IXR_BYTE_CNT_OVRFL_MASK,
+					  * XZDMA_IXR_SRC_ACCT_ERR_MASK,
+					  *  XZDMA_IXR_DST_ACCT_ERR_MASK */
+/*@}*/
+
+/** @name Channel Control0 register bit masks and shifts
+ * @{
+ */
+#define XZDMA_CTRL0_OVR_FETCH_MASK	(0x00000080U) /**< Over fetch mask */
+#define XZDMA_CTRL0_POINT_TYPE_MASK	(0x00000040U) /**< Pointer type mask */
+#define XZDMA_CTRL0_MODE_MASK		(0x00000030U) /**< Mode mask */
+#define XZDMA_CTRL0_WRONLY_MASK		(0x00000010U) /**< Write only mask */
+#define XZDMA_CTRL0_RDONLY_MASK		(0x00000020U) /**< Read only mask */
+#define XZDMA_CTRL0_RATE_CNTL_MASK	(0x00000008U) /**< Rate control mask */
+#define XZDMA_CTRL0_CONT_ADDR_MASK	(0x00000004U) /**< Continue address
+							*  specified mask */
+#define XZDMA_CTRL0_CONT_MASK		(0x00000002U) /**< Continue mask */
+
+#define XZDMA_CTRL0_OVR_FETCH_SHIFT	(7U)	/**< Over fetch shift */
+#define XZDMA_CTRL0_POINT_TYPE_SHIFT	(6U)	/**< Pointer type shift */
+#define XZDMA_CTRL0_MODE_SHIFT		(4U)	/**< Mode type shift */
+#define XZDMA_CTRL0_RESET_VALUE		(0x00000080U) /**< CTRL0 reset value */
+
+/*@}*/
+
+/** @name Channel Control1 register bit masks and shifts
+ * @{
+ */
+#define XZDMA_CTRL1_SRC_ISSUE_MASK	(0x0000001FU) /**< Source issue mask */
+#define XZDMA_CTRL1_RESET_VALUE		(0x000003FFU) /**< CTRL1 reset value */
+/*@}*/
+
+/** @name Channel Peripheral register bit masks and shifts
+ * @{
+ */
+#define XZDMA_PERIF_PROG_CELL_CNT_MASK	(0x0000003EU) /**< Peripheral program
+							*  cell count */
+#define XZDMA_PERIF_SIDE_MASK		(0x00000002U) /**< Interface attached
+							* the side mask */
+#define XZDMA_PERIF_EN_MASK		(0x00000001U) /**< Peripheral flow
+							* control mask */
+/*@}*/
+
+/** @name Channel Status register bit masks and shifts
+ * @{
+ */
+#define XZDMA_STS_DONE_ERR_MASK	(0x00000003U) /**< Done with errors mask */
+#define XZDMA_STS_BUSY_MASK	(0x00000002U) /**< ZDMA is busy in transfer
+						*  mask */
+#define XZDMA_STS_PAUSE_MASK	(0x00000001U) /**< ZDMA is in Pause state
+						*  mask */
+#define XZDMA_STS_DONE_MASK	(0x00000000U) /**< ZDMA done mask */
+#define XZDMA_STS_ALL_MASK	(0x00000003U) /**< ZDMA status mask */
+
+/*@}*/
+
+/** @name Channel Data Attribute register bit masks and shifts
+ * @{
+ */
+#define XZDMA_DATA_ATTR_ARBURST_MASK	(0x0C000000U) /**< Data ArBurst mask */
+#define XZDMA_DATA_ATTR_ARCACHE_MASK	(0x03C00000U) /**< Data ArCache mask */
+#define XZDMA_DATA_ATTR_ARQOS_MASK	(0x003C0000U) /**< Data ARQos masks */
+#define XZDMA_DATA_ATTR_ARLEN_MASK	(0x0003C000U) /**< Data Arlen mask */
+#define XZDMA_DATA_ATTR_AWBURST_MASK	(0x00003000U) /**< Data Awburst mask */
+#define XZDMA_DATA_ATTR_AWCACHE_MASK	(0x00000F00U) /**< Data AwCache mask */
+#define XZDMA_DATA_ATTR_AWQOS_MASK	(0x000000F0U) /**< Data AwQos mask */
+#define XZDMA_DATA_ATTR_AWLEN_MASK	(0x0000000FU) /**< Data Awlen mask */
+
+#define XZDMA_DATA_ATTR_ARBURST_SHIFT	(26U) /**< Data Arburst shift */
+#define XZDMA_DATA_ATTR_ARCACHE_SHIFT	(22U) /**< Data ArCache shift */
+#define XZDMA_DATA_ATTR_ARQOS_SHIFT	(18U) /**< Data ARQos shift */
+#define XZDMA_DATA_ATTR_ARLEN_SHIFT	(14U) /**< Data Arlen shift */
+#define XZDMA_DATA_ATTR_AWBURST_SHIFT	(12U) /**< Data Awburst shift  */
+#define XZDMA_DATA_ATTR_AWCACHE_SHIFT	(8U)  /**< Data Awcache shift */
+#define XZDMA_DATA_ATTR_AWQOS_SHIFT	(4U)  /**< Data Awqos shift */
+#define XZDMA_DATA_ATTR_RESET_VALUE	(0x0483D20FU) /**< Data Attributes
+							*  reset value */
+
+/*@}*/
+
+/** @name Channel DSCR Attribute register bit masks and shifts
+ * @{
+ */
+#define XZDMA_DSCR_ATTR_AXCOHRNT_MASK	(0x00000100U) /**< Descriptor coherent
+							*  mask */
+#define XZDMA_DSCR_ATTR_AXCACHE_MASK	(0x000000F0U) /**< Descriptor cache
+							* mask */
+#define XZDMA_DSCR_ATTR_AXQOS_MASK	(0x0000000FU) /**< Descriptor AxQos
+							*  mask */
+
+#define XZDMA_DSCR_ATTR_AXCOHRNT_SHIFT	(8U) /**< Descriptor coherent shift */
+#define XZDMA_DSCR_ATTR_AXCACHE_SHIFT	(7U) /**< Descriptor cache shift */
+#define XZDMA_DSCR_ATTR_RESET_VALUE	(0x00000000U) /**< Dscr Attributes
+							*  reset value */
+
+/*@}*/
+
+/** @name Channel Source/Destination Word0 register bit mask
+ * @{
+ */
+#define XZDMA_WORD0_LSB_MASK	(0xFFFFFFFFU)	/**< LSB Address mask */
+/*@}*/
+
+/** @name Channel Source/Destination Word1 register bit mask
+ * @{
+ */
+#define XZDMA_WORD1_MSB_MASK	(0x0001FFFFU)	/**< MSB Address mask */
+#define XZDMA_WORD1_MSB_SHIFT	(32U)		/**< MSB Address shift */
+/*@}*/
+
+/** @name Channel Source/Destination Word2 register bit mask
+ * @{
+ */
+#define XZDMA_WORD2_SIZE_MASK	(0x3FFFFFFFU) /**< Size mask */
+/*@}*/
+
+/** @name Channel Source/Destination Word3 register bit masks and shifts
+ * @{
+ */
+#define XZDMA_WORD3_CMD_MASK		(0x00000018U)	/**< Cmd mask */
+#define XZDMA_WORD3_CMD_SHIFT		(3U)		/**< Cmd shift */
+#define XZDMA_WORD3_CMD_NXTVALID_MASK	(0x00000000U)	/**< Next Dscr is valid
+							  *  mask */
+#define XZDMA_WORD3_CMD_PAUSE_MASK	(0x00000008U)	/**< Pause after this
+							  * dscr mask */
+#define XZDMA_WORD3_CMD_STOP_MASK	(0x00000010U)	/**< Stop after this
+							..*  dscr mask */
+#define XZDMA_WORD3_INTR_MASK		(0x00000004U)	/**< Interrupt
+							  *  enable or disable
+							  *  mask */
+#define XZDMA_WORD3_INTR_SHIFT		(2U)		/**< Interrupt enable
+							  *  disable
+							  *  shift */
+#define XZDMA_WORD3_TYPE_MASK		(0x00000002U)	/**< Type of Descriptor
+							  *  mask */
+#define XZDMA_WORD3_TYPE_SHIFT		(1U)		/**< Type of Descriptor
+							  *  Shift */
+#define XZDMA_WORD3_COHRNT_MASK		(0x00000001U)	/**< Coherence mask */
+/*@}*/
+
+/** @name Channel Source/Destination start address or current payload
+ *  MSB register bit mask
+ * @{
+ */
+#define XZDMA_START_MSB_ADDR_MASK	(0x0001FFFFU)	/**< Start msb address
+							  *  mask */
+/*@}*/
+
+/** @name Channel Rate control count register bit mask
+ * @{
+ */
+#define XZDMA_CH_RATE_CNTL_MASK		(0x00000FFFU) /**< Channel rate control
+							*  mask */
+/*@}*/
+
+/** @name Channel Source/Destination Interrupt account count register bit mask
+ * @{
+ */
+#define XZDMA_CH_IRQ_ACCT_MASK		(0x000000FFU) /**< Interrupt count
+							*  mask */
+/*@}*/
+
+/** @name Channel debug register 0/1 bit mask
+ * @{
+ */
+#define XZDMA_CH_DBG_CMN_BUF_MASK	(0x000001FFU) /**< Common buffer count
+							* mask */
+/*@}*/
+
+/** @name Channel control2 register bit mask
+ * @{
+ */
+#define XZDMA_CH_CTRL2_EN_MASK		(0x00000001U) /**< Channel enable
+							*  mask */
+#define XZDMA_CH_CTRL2_DIS_MASK		(0x00000000U) /**< Channel disable
+							*  mask */
+/*@}*/
+
+/** @name Channel control2 register bit mask
+ * @{
+ */
+ #define XZDMA_WRITE_TO_CLEAR_MASK	(0x00000000U) /**< Write to clear
+							*  mask */
+ /*@}*/
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+#define XZDma_In32		Xil_In32	/**< Input operation */
+#define XZDma_Out32		Xil_Out32	/**< Output operation */
+
+/*****************************************************************************/
+/**
+*
+* This macro reads the given register.
+*
+* @param	BaseAddress is the Xilinx base address of the ZDMA core.
+* @param	RegOffset is the register offset of the register.
+*
+* @return	The 32-bit value of the register.
+*
+* @note		C-style signature:
+*		u32 XZDma_ReadReg(u32 BaseAddress, u32 RegOffset)
+*
+******************************************************************************/
+#define XZDma_ReadReg(BaseAddress, RegOffset) \
+		XZDma_In32((BaseAddress) + (u32)(RegOffset))
+
+/*****************************************************************************/
+/**
+*
+* This macro writes the value into the given register.
+*
+* @param	BaseAddress is the Xilinx base address of the ZDMA core.
+* @param	RegOffset is the register offset of the register.
+* @param	Data is the 32-bit value to write to the register.
+*
+* @return	None.
+*
+* @note		C-style signature:
+*		void XZDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
+*
+******************************************************************************/
+#define XZDma_WriteReg(BaseAddress, RegOffset, Data) \
+		XZDma_Out32(((BaseAddress) + (u32)(RegOffset)), (u32)(Data))
+
+#ifdef __cplusplus
+}
+
+#endif
+
+#endif /* XZDMA_HW_H_ */
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_intr.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_intr.c
new file mode 100644
index 000000000..e828d16a4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_intr.c
@@ -0,0 +1,205 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_intr.c
+* @addtogroup zdma_v1_0
+* @{
+*
+* This file contains interrupt related functions of Xilinx ZDMA core.
+* Please see xzdma.h for more details of the driver.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+
+/*****************************************************************************/
+/**
+*
+* This function is the interrupt handler for the ZDMA core.
+*
+* This handler reads the pending interrupt from Status register, determines the
+* source of the interrupts and calls the respective callbacks for the
+* interrupts that are enabled in IRQ_ENABLE register, and finally clears the
+* interrupts.
+*
+* The application is responsible for connecting this function to the interrupt
+* system. Application beyond this driver is also responsible for providing
+* callbacks to handle interrupts and installing the callbacks using
+* XZDma_SetCallBack() during initialization phase. .
+*
+* @param	Instance is a pointer to the XZDma instance to be worked on.
+*
+* @return	None.
+*
+* @note		To generate interrupt required interrupts should be enabled.
+*
+******************************************************************************/
+void XZDma_IntrHandler(void *Instance)
+{
+	u32 PendingIntr;
+	u32 ErrorStatus;
+	XZDma *InstancePtr = NULL;
+	InstancePtr = (XZDma *)((void *)Instance);
+
+	/* Verify arguments. */
+	Xil_AssertVoid(InstancePtr != NULL);
+
+	/* Get pending interrupts */
+	PendingIntr = (u32)(XZDma_IntrGetStatus(InstancePtr));
+	PendingIntr &= (~XZDma_GetIntrMask(InstancePtr));
+
+	/* ZDMA transfer has completed */
+	ErrorStatus = (PendingIntr) & (XZDMA_IXR_DMA_DONE_MASK);
+	if ((ErrorStatus) != 0U) {
+		XZDma_DisableIntr(InstancePtr, XZDMA_IXR_ALL_INTR_MASK);
+		InstancePtr->ChannelState = XZDMA_IDLE;
+		InstancePtr->DoneHandler(InstancePtr->DoneRef);
+	}
+
+	/* An error has been occurred */
+	ErrorStatus = PendingIntr & (XZDMA_IXR_ERR_MASK);
+	if ((ErrorStatus) != 0U) {
+		if ((ErrorStatus & XZDMA_IXR_DMA_PAUSE_MASK) ==
+				XZDMA_IXR_DMA_PAUSE_MASK) {
+			InstancePtr->ChannelState = XZDMA_PAUSE;
+		}
+		else {
+			if ((ErrorStatus & (XZDMA_IXR_AXI_WR_DATA_MASK |
+				XZDMA_IXR_AXI_RD_DATA_MASK |
+				XZDMA_IXR_AXI_RD_DST_DSCR_MASK |
+				XZDMA_IXR_AXI_RD_SRC_DSCR_MASK)) != 0x00U) {
+				InstancePtr->ChannelState = XZDMA_IDLE;
+			}
+		}
+		InstancePtr->ErrorHandler(InstancePtr->ErrorRef, ErrorStatus);
+	}
+
+	/* Clear pending interrupt(s) */
+	XZDma_IntrClear(InstancePtr, PendingIntr);
+}
+
+/*****************************************************************************/
+/**
+*
+* This routine installs an asynchronous callback function for the given
+* HandlerType.
+*
+* 
+* HandlerType              Callback Function Type
+* -----------------------  --------------------------------------------------
+* XZDMA_HANDLER_DONE	   Done handler
+* XZDMA_HANDLER_ERROR	   Error handler
+*
+* 

+*
+* @param	InstancePtr is a pointer to the XZDma instance to be worked on.
+* @param	HandlerType specifies which callback is to be attached.
+* @param	CallBackFunc is the address of the callback function.
+* @param	CallBackRef is a user data item that will be passed to the
+* 		callback function when it is invoked.
+*
+* @return
+*		- XST_SUCCESS when handler is installed.
+*		- XST_INVALID_PARAM when HandlerType is invalid.
+*
+* @note		Invoking this function for a handler that already has been
+*		installed replaces it with the new handler.
+*
+******************************************************************************/
+s32 XZDma_SetCallBack(XZDma *InstancePtr, XZDma_Handler HandlerType,
+	void *CallBackFunc, void *CallBackRef)
+{
+	s32 Status;
+
+	/* Verify arguments. */
+	Xil_AssertNonvoid(InstancePtr != NULL);
+	Xil_AssertNonvoid(CallBackFunc != NULL);
+	Xil_AssertNonvoid(CallBackRef != NULL);
+	Xil_AssertNonvoid((HandlerType == XZDMA_HANDLER_DONE) ||
+				(HandlerType == XZDMA_HANDLER_ERROR));
+	Xil_AssertNonvoid(InstancePtr->IsReady ==
+				(u32)(XIL_COMPONENT_IS_READY));
+
+	/*
+	 * Calls the respective callback function corresponding to
+	 * the handler type
+	 */
+	switch (HandlerType) {
+		case XZDMA_HANDLER_DONE:
+			InstancePtr->DoneHandler =
+				(XZDma_DoneHandler)((void *)CallBackFunc);
+			InstancePtr->DoneRef = CallBackRef;
+			Status = (XST_SUCCESS);
+			break;
+
+		case XZDMA_HANDLER_ERROR:
+			InstancePtr->ErrorHandler =
+				(XZDma_ErrorHandler)((void *)CallBackFunc);
+			InstancePtr->ErrorRef = CallBackRef;
+			Status = (XST_SUCCESS);
+			break;
+
+		default:
+			Status = (XST_INVALID_PARAM);
+			break;
+	}
+
+	return Status;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_selftest.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_selftest.c
new file mode 100644
index 000000000..893a5402f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_selftest.c
@@ -0,0 +1,119 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_selftest.c
+* @addtogroup zdma_v1_0
+* @{
+*
+* This file contains the self-test function for the ZDMA core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+* 

+*
+******************************************************************************/
+
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* This file contains a diagnostic self-test function for the ZDMA driver.
+* Refer to the header file xzdma.h for more detailed information.
+*
+* @param	InstancePtr is a pointer to XZDma instance.
+*
+* @return
+*		- XST_SUCCESS if the test is successful.
+*		- XST_FAILURE if the test is failed.
+*
+* @note		None.
+*
+******************************************************************************/
+s32 XZDma_SelfTest(XZDma *InstancePtr)
+{
+
+	u32 Data;
+	s32 Status;
+
+	Xil_AssertNonvoid(InstancePtr != NULL);
+
+	Data = XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+				XZDMA_CH_CTRL0_OFFSET);
+
+	/* Changing DMA channel to over fetch */
+
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
+			(Data | XZDMA_CTRL0_OVR_FETCH_MASK));
+
+	if (((u32)XZDma_ReadReg(InstancePtr->Config.BaseAddress,
+		XZDMA_CH_CTRL0_OFFSET) & XZDMA_CTRL0_OVR_FETCH_MASK) !=
+						XZDMA_CTRL0_OVR_FETCH_MASK) {
+		Status = (s32)XST_FAILURE;
+	}
+	else {
+		Status = (s32)XST_SUCCESS;
+	}
+
+	/* Retrieving the change settings */
+	XZDma_WriteReg(InstancePtr->Config.BaseAddress, XZDMA_CH_CTRL0_OFFSET,
+				Data);
+
+	return Status;
+
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_sinit.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_sinit.c
new file mode 100644
index 000000000..ae2c44d1c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/psu_cortexr5_0/libsrc/zdma_v1_1/src/xzdma_sinit.c
@@ -0,0 +1,106 @@
+/******************************************************************************
+*
+* Copyright (C) 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/*****************************************************************************/
+/**
+*
+* @file xzdma_sinit.c
+* @addtogroup zdma_v1_0
+* @{
+*
+* This file contains static initialization methods for Xilinx ZDMA core.
+*
+* 
+* MODIFICATION HISTORY:
+*
+* Ver   Who     Date     Changes
+* ----- ------  -------- ------------------------------------------------------
+* 1.0   vns     2/27/15  First release
+* 

+*
+******************************************************************************/
+/***************************** Include Files *********************************/
+
+#include "xzdma.h"
+#include "xparameters.h"
+
+/************************** Constant Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *********************/
+
+
+/**************************** Type Definitions *******************************/
+
+
+/************************** Function Prototypes ******************************/
+
+
+/************************** Variable Definitions *****************************/
+
+
+/************************** Function Definitions *****************************/
+
+/*****************************************************************************/
+/**
+*
+* XZDma_LookupConfig returns a reference to an XZDma_Config structure
+* based on the unique device id, DeviceId. The return value will refer
+* to an entry in the device configuration table defined in the xzdma_g.c
+* file.
+*
+* @param	DeviceId is the unique device ID of the device for the lookup
+*		operation.
+*
+* @return	CfgPtr is a reference to a config record in the configuration
+*		table (in xzdma_g.c) corresponding to DeviceId, or
+*		NULL if no match is found.
+*
+* @note		None.
+******************************************************************************/
+XZDma_Config *XZDma_LookupConfig(u16 DeviceId)
+{
+	extern XZDma_Config XZDma_ConfigTable[XPAR_XZDMA_NUM_INSTANCES];
+	XZDma_Config *CfgPtr = NULL;
+	u32 Index;
+
+	/* Checks all the instances */
+	for (Index = (u32)0x0; Index < (u32)(XPAR_XZDMA_NUM_INSTANCES);
+								Index++) {
+		if (XZDma_ConfigTable[Index].DeviceId == DeviceId) {
+			CfgPtr = &XZDma_ConfigTable[Index];
+			break;
+		}
+	}
+
+	return (XZDma_Config *)CfgPtr;
+}
+/** @} */
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
new file mode 100644
index 000000000..5a742ad93
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/RTOSDemo_R5_bsp/system.mss
@@ -0,0 +1,694 @@
+
+ PARAMETER VERSION = 2.2.0
+
+
+BEGIN OS
+ PARAMETER OS_NAME = standalone
+ PARAMETER OS_VER = 5.4
+ PARAMETER PROC_INSTANCE = psu_cortexr5_0
+ PARAMETER stdin = psu_uart_0
+ PARAMETER stdout = psu_uart_0
+END
+
+
+BEGIN PROCESSOR
+ PARAMETER DRIVER_NAME = cpu_cortexr5
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_cortexr5_0
+ PARAMETER extra_compiler_flags = -g -DARMR5 -mfpu=vfpv3-d16
+END
+
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scugic
+ PARAMETER DRIVER_VER = 3.2
+ PARAMETER HW_INSTANCE = psu_acpu_gic
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_adma_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_adma_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_adma_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_adma_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_adma_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_adma_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_adma_6
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_adma_7
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_afi_6
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sysmonpsu
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_ams
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.4
+ PARAMETER HW_INSTANCE = psu_apm_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.4
+ PARAMETER HW_INSTANCE = psu_apm_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.4
+ PARAMETER HW_INSTANCE = psu_apm_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = axipmon
+ PARAMETER DRIVER_VER = 6.4
+ PARAMETER HW_INSTANCE = psu_apm_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_apu
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_bbram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = canps
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_can_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_cci_gpv
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_cci_reg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = coresightps_dcc
+ PARAMETER DRIVER_VER = 1.2
+ PARAMETER HW_INSTANCE = psu_coresight_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_crf_apb
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_crl_apb
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_csu_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = csudma
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_csudma
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_phy
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_qos_ctrl
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu0_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu1_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu2_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu3_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu4_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddr_xmpu5_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ddrc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_dp
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_dpdma
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_efuse
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = emacps
+ PARAMETER DRIVER_VER = 3.2
+ PARAMETER HW_INSTANCE = psu_ethernet_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_fpd_gpv
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_fpd_slcr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_fpd_slcr_secure
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_fpd_xmpu_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_fpd_xmpu_sink
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_gdma_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_gdma_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_gdma_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_gdma_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_gdma_4
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_gdma_5
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_gdma_6
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = zdma
+ PARAMETER DRIVER_VER = 1.1
+ PARAMETER HW_INSTANCE = psu_gdma_7
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = gpiops
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_gpio_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_gpu
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_i2c_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = iicps
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_i2c_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_iou_s
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_iou_scntr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_iou_scntrs
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_iousecure_slcr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_iouslcr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ipipsu
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ipi_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ipipsu
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ipi_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_lpd_slcr
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_lpd_slcr_secure
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_lpd_xppu
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_lpd_xppu_sink
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_mbistjtag
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ocm
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ocm_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ocm_ram_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_ocm_xmpu_cfg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pcie
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pcie_attrib_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pcie_dma
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pmu_global_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pmu_iomodule
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_pmu_ram
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = qspipsu
+ PARAMETER DRIVER_VER = 1.0
+ PARAMETER HW_INSTANCE = psu_qspi_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_qspi_linear_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_0_atcm
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_0_atcm_lockstep
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_0_btcm
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_0_btcm_lockstep
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_1_atcm
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_1_btcm
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_ddr_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_r5_tcm_ram_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = scugic
+ PARAMETER DRIVER_VER = 3.2
+ PARAMETER HW_INSTANCE = psu_rcpu_gic
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_rpu
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_rsa
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = rtcpsu
+ PARAMETER DRIVER_VER = 1.2
+ PARAMETER HW_INSTANCE = psu_rtc
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_sata
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = sdps
+ PARAMETER DRIVER_VER = 2.7
+ PARAMETER HW_INSTANCE = psu_sd_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_serdes
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_siou
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_smmu_gpv
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_smmu_reg
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ttc_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ttc_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ttc_2
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = ttcps
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_ttc_3
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_uart_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = uartps
+ PARAMETER DRIVER_VER = 3.1
+ PARAMETER HW_INSTANCE = psu_uart_1
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = generic
+ PARAMETER DRIVER_VER = 2.0
+ PARAMETER HW_INSTANCE = psu_usb_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = wdtps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_wdt_0
+END
+
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = wdtps
+ PARAMETER DRIVER_VER = 3.0
+ PARAMETER HW_INSTANCE = psu_wdt_1
+END
+
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/.project b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/.project
new file mode 100644
index 000000000..78fcf3cf0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/.project
@@ -0,0 +1,41 @@
+
+
+	ZynqMP_ZCU102_hw_platform
+	Created by SDK v2016.1
+	
+	
+	
+	
+	
+		com.xilinx.sdk.hw.HwProject
+	
+	
+		
+			1462451796084
+			
+			6
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-*.xml
+			
+		
+		
+			1462451796084
+			
+			6
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-*.svd
+			
+		
+		
+			1462451796094
+			
+			6
+			
+				org.eclipse.ui.ide.multiFilter
+				1.0-name-matches-false-false-*.hwh
+			
+		
+	
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c
new file mode 100644
index 000000000..ec9441e4c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.c
@@ -0,0 +1,19394 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file psu_init.c
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+#include 
+#include 
+#include "psu_init.h"
+
+int mask_pollOnValue(u32 add , u32 mask, u32 value );
+
+int mask_poll(u32 add , u32 mask );
+
+void mask_delay(u32 delay);
+
+u32 mask_read(u32 add , u32 mask );
+
+static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned long val)
+{
+	unsigned long RegVal = 0x0;
+	RegVal = Xil_In32 (offset);
+	RegVal &= ~(mask);
+	RegVal |= (val & mask);
+	Xil_Out32 (offset, RegVal);
+}
+
+	void prog_reg (unsigned long addr, unsigned long mask, unsigned long shift, unsigned long value) {
+	    int rdata =0;
+	    rdata  = Xil_In32(addr);
+	    rdata  = rdata & (~mask);
+	    rdata  = rdata | (value << shift);
+	    Xil_Out32(addr,rdata);
+	    } 
+
+unsigned long psu_pll_init_data() {
+		// : RPLL INIT
+		/*Register : RPLL_CFG @ 0XFF5E0034

+
+		PLL loop filter resistor control
+		PSU_CRL_APB_RPLL_CFG_RES                                                        0x2
+
+		PLL charge pump control
+		PSU_CRL_APB_RPLL_CFG_CP                                                         0x3
+
+		PLL loop filter high frequency capacitor control
+		PSU_CRL_APB_RPLL_CFG_LFHF                                                       0x3
+
+		Lock circuit counter setting
+		PSU_CRL_APB_RPLL_CFG_LOCK_CNT                                                   0x258
+
+		Lock circuit configuration settings for lock windowsize
+		PSU_CRL_APB_RPLL_CFG_LOCK_DLY                                                   0x3f
+
+		Helper data. Values are to be looked up in a table from Data Sheet
+		(OFFSET, MASK, VALUE)      (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U)  
+		RegMask = (CRL_APB_RPLL_CFG_RES_MASK | CRL_APB_RPLL_CFG_CP_MASK | CRL_APB_RPLL_CFG_LFHF_MASK | CRL_APB_RPLL_CFG_LOCK_CNT_MASK | CRL_APB_RPLL_CFG_LOCK_DLY_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRL_APB_RPLL_CFG_RES_SHIFT
+			| 0x00000003U << CRL_APB_RPLL_CFG_CP_SHIFT
+			| 0x00000003U << CRL_APB_RPLL_CFG_LFHF_SHIFT
+			| 0x00000258U << CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT
+			| 0x0000003FU << CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
+	/*############################################################################################################################ */
+
+		// : UPDATE FB_DIV
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		PSU_CRL_APB_RPLL_CTRL_PRE_SRC                                                   0x0
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRL_APB_RPLL_CTRL_FBDIV                                                     0x48
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRL_APB_RPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00717F00U ,0x00014800U)  
+		RegMask = (CRL_APB_RPLL_CTRL_PRE_SRC_MASK | CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT
+			| 0x00000048U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00717F00U ,0x00014800U);
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000008U)  
+		RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRL_APB_RPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000001U)  
+		RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRL_APB_RPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000000U)  
+		RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFF5E0040

+
+		RPLL is locked
+		PSU_CRL_APB_PLL_STATUS_RPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000002U ,0x00000002U)  */
+		mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000002U);
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000000U)  
+		RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048

+
+		Divisor value for this clock.
+		PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0                                           0x3
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFF5E0048, 0x00003F00U ,0x00000300U)  
+		RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		// : RPLL FRAC CFG
+		/*Register : RPLL_FRAC_CFG @ 0XFF5E0038

+
+		Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.
+		PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED                                               0x0
+
+		Fractional value for the Feedback value.
+		PSU_CRL_APB_RPLL_FRAC_CFG_DATA                                                  0x0
+
+		Fractional control for the PLL
+		(OFFSET, MASK, VALUE)      (0XFF5E0038, 0x8000FFFFU ,0x00000000U)  
+		RegMask = (CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_RPLL_FRAC_CFG_DATA_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT
+			| 0x00000000U << CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : IOPLL INIT
+		/*Register : IOPLL_CFG @ 0XFF5E0024

+
+		PLL loop filter resistor control
+		PSU_CRL_APB_IOPLL_CFG_RES                                                       0xc
+
+		PLL charge pump control
+		PSU_CRL_APB_IOPLL_CFG_CP                                                        0x3
+
+		PLL loop filter high frequency capacitor control
+		PSU_CRL_APB_IOPLL_CFG_LFHF                                                      0x3
+
+		Lock circuit counter setting
+		PSU_CRL_APB_IOPLL_CFG_LOCK_CNT                                                  0x339
+
+		Lock circuit configuration settings for lock windowsize
+		PSU_CRL_APB_IOPLL_CFG_LOCK_DLY                                                  0x3f
+
+		Helper data. Values are to be looked up in a table from Data Sheet
+		(OFFSET, MASK, VALUE)      (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU)  
+		RegMask = (CRL_APB_IOPLL_CFG_RES_MASK | CRL_APB_IOPLL_CFG_CP_MASK | CRL_APB_IOPLL_CFG_LFHF_MASK | CRL_APB_IOPLL_CFG_LOCK_CNT_MASK | CRL_APB_IOPLL_CFG_LOCK_DLY_MASK |  0 );
+
+		RegVal = ((0x0000000CU << CRL_APB_IOPLL_CFG_RES_SHIFT
+			| 0x00000003U << CRL_APB_IOPLL_CFG_CP_SHIFT
+			| 0x00000003U << CRL_APB_IOPLL_CFG_LFHF_SHIFT
+			| 0x00000339U << CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT
+			| 0x0000003FU << CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E672C6CU);
+	/*############################################################################################################################ */
+
+		// : UPDATE FB_DIV
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		PSU_CRL_APB_IOPLL_CTRL_PRE_SRC                                                  0x0
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRL_APB_IOPLL_CTRL_FBDIV                                                    0x2d
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRL_APB_IOPLL_CTRL_DIV2                                                     0x0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00717F00U ,0x00002D00U)  
+		RegMask = (CRL_APB_IOPLL_CTRL_PRE_SRC_MASK | CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT
+			| 0x0000002DU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
+			| 0x00000000U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00717F00U ,0x00002D00U);
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000008U)  
+		RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRL_APB_IOPLL_CTRL_RESET                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000001U)  
+		RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRL_APB_IOPLL_CTRL_RESET                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000000U)  
+		RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFF5E0040

+
+		IOPLL is locked
+		PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK                                               1
+		(OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000001U ,0x00000001U)  */
+		mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000001U);
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000000U)  
+		RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044

+
+		Divisor value for this clock.
+		PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0                                          0x3
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFF5E0044, 0x00003F00U ,0x00000300U)  
+		RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000003U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		// : IOPLL FRAC CFG
+		/*Register : IOPLL_FRAC_CFG @ 0XFF5E0028

+
+		Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.
+		PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED                                              0x0
+
+		Fractional value for the Feedback value.
+		PSU_CRL_APB_IOPLL_FRAC_CFG_DATA                                                 0x0
+
+		Fractional control for the PLL
+		(OFFSET, MASK, VALUE)      (0XFF5E0028, 0x8000FFFFU ,0x00000000U)  
+		RegMask = (CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_IOPLL_FRAC_CFG_DATA_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT
+			| 0x00000000U << CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : APU_PLL INIT
+		/*Register : APLL_CFG @ 0XFD1A0024

+
+		PLL loop filter resistor control
+		PSU_CRF_APB_APLL_CFG_RES                                                        0x2
+
+		PLL charge pump control
+		PSU_CRF_APB_APLL_CFG_CP                                                         0x3
+
+		PLL loop filter high frequency capacitor control
+		PSU_CRF_APB_APLL_CFG_LFHF                                                       0x3
+
+		Lock circuit counter setting
+		PSU_CRF_APB_APLL_CFG_LOCK_CNT                                                   0x258
+
+		Lock circuit configuration settings for lock windowsize
+		PSU_CRF_APB_APLL_CFG_LOCK_DLY                                                   0x3f
+
+		Helper data. Values are to be looked up in a table from Data Sheet
+		(OFFSET, MASK, VALUE)      (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U)  
+		RegMask = (CRF_APB_APLL_CFG_RES_MASK | CRF_APB_APLL_CFG_CP_MASK | CRF_APB_APLL_CFG_LFHF_MASK | CRF_APB_APLL_CFG_LOCK_CNT_MASK | CRF_APB_APLL_CFG_LOCK_DLY_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_APLL_CFG_RES_SHIFT
+			| 0x00000003U << CRF_APB_APLL_CFG_CP_SHIFT
+			| 0x00000003U << CRF_APB_APLL_CFG_LFHF_SHIFT
+			| 0x00000258U << CRF_APB_APLL_CFG_LOCK_CNT_SHIFT
+			| 0x0000003FU << CRF_APB_APLL_CFG_LOCK_DLY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
+	/*############################################################################################################################ */
+
+		// : UPDATE FB_DIV
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		PSU_CRF_APB_APLL_CTRL_PRE_SRC                                                   0x0
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_APLL_CTRL_FBDIV                                                     0x42
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_APLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00717F00U ,0x00014200U)  
+		RegMask = (CRF_APB_APLL_CTRL_PRE_SRC_MASK | CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_PRE_SRC_SHIFT
+			| 0x00000042U << CRF_APB_APLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00717F00U ,0x00014200U);
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_APLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000008U)  
+		RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_APLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000001U)  
+		RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_APLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000000U)  
+		RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044

+
+		APLL is locked
+		PSU_CRF_APB_PLL_STATUS_APLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000001U ,0x00000001U)  */
+		mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000001U);
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_APLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000000U)  
+		RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048

+
+		Divisor value for this clock.
+		PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0                                           0x3
+
+		Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A0048, 0x00003F00U ,0x00000300U)  
+		RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000003U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		// : APLL FRAC CFG
+		/*Register : APLL_FRAC_CFG @ 0XFD1A0028

+
+		Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.
+		PSU_CRF_APB_APLL_FRAC_CFG_ENABLED                                               0x0
+
+		Fractional value for the Feedback value.
+		PSU_CRF_APB_APLL_FRAC_CFG_DATA                                                  0x0
+
+		Fractional control for the PLL
+		(OFFSET, MASK, VALUE)      (0XFD1A0028, 0x8000FFFFU ,0x00000000U)  
+		RegMask = (CRF_APB_APLL_FRAC_CFG_ENABLED_MASK | CRF_APB_APLL_FRAC_CFG_DATA_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT
+			| 0x00000000U << CRF_APB_APLL_FRAC_CFG_DATA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : DDR_PLL INIT
+		/*Register : DPLL_CFG @ 0XFD1A0030

+
+		PLL loop filter resistor control
+		PSU_CRF_APB_DPLL_CFG_RES                                                        0x2
+
+		PLL charge pump control
+		PSU_CRF_APB_DPLL_CFG_CP                                                         0x3
+
+		PLL loop filter high frequency capacitor control
+		PSU_CRF_APB_DPLL_CFG_LFHF                                                       0x3
+
+		Lock circuit counter setting
+		PSU_CRF_APB_DPLL_CFG_LOCK_CNT                                                   0x258
+
+		Lock circuit configuration settings for lock windowsize
+		PSU_CRF_APB_DPLL_CFG_LOCK_DLY                                                   0x3f
+
+		Helper data. Values are to be looked up in a table from Data Sheet
+		(OFFSET, MASK, VALUE)      (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U)  
+		RegMask = (CRF_APB_DPLL_CFG_RES_MASK | CRF_APB_DPLL_CFG_CP_MASK | CRF_APB_DPLL_CFG_LFHF_MASK | CRF_APB_DPLL_CFG_LOCK_CNT_MASK | CRF_APB_DPLL_CFG_LOCK_DLY_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DPLL_CFG_RES_SHIFT
+			| 0x00000003U << CRF_APB_DPLL_CFG_CP_SHIFT
+			| 0x00000003U << CRF_APB_DPLL_CFG_LFHF_SHIFT
+			| 0x00000258U << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT
+			| 0x0000003FU << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
+	/*############################################################################################################################ */
+
+		// : UPDATE FB_DIV
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		PSU_CRF_APB_DPLL_CTRL_PRE_SRC                                                   0x0
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_DPLL_CTRL_FBDIV                                                     0x40
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_DPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00717F00U ,0x00014000U)  
+		RegMask = (CRF_APB_DPLL_CTRL_PRE_SRC_MASK | CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT
+			| 0x00000040U << CRF_APB_DPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00717F00U ,0x00014000U);
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000008U)  
+		RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_DPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000001U)  
+		RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_DPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000000U)  
+		RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044

+
+		DPLL is locked
+		PSU_CRF_APB_PLL_STATUS_DPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000002U ,0x00000002U)  */
+		mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000002U);
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000000U)  
+		RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C

+
+		Divisor value for this clock.
+		PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
+
+		Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A004C, 0x00003F00U ,0x00000300U)  
+		RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000003U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		// : DPLL FRAC CFG
+		/*Register : DPLL_FRAC_CFG @ 0XFD1A0034

+
+		Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.
+		PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED                                               0x0
+
+		Fractional value for the Feedback value.
+		PSU_CRF_APB_DPLL_FRAC_CFG_DATA                                                  0x0
+
+		Fractional control for the PLL
+		(OFFSET, MASK, VALUE)      (0XFD1A0034, 0x8000FFFFU ,0x00000000U)  
+		RegMask = (CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_DPLL_FRAC_CFG_DATA_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT
+			| 0x00000000U << CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : VIDEO_PLL INIT
+		/*Register : VPLL_CFG @ 0XFD1A003C

+
+		PLL loop filter resistor control
+		PSU_CRF_APB_VPLL_CFG_RES                                                        0x2
+
+		PLL charge pump control
+		PSU_CRF_APB_VPLL_CFG_CP                                                         0x3
+
+		PLL loop filter high frequency capacitor control
+		PSU_CRF_APB_VPLL_CFG_LFHF                                                       0x3
+
+		Lock circuit counter setting
+		PSU_CRF_APB_VPLL_CFG_LOCK_CNT                                                   0x28a
+
+		Lock circuit configuration settings for lock windowsize
+		PSU_CRF_APB_VPLL_CFG_LOCK_DLY                                                   0x3f
+
+		Helper data. Values are to be looked up in a table from Data Sheet
+		(OFFSET, MASK, VALUE)      (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U)  
+		RegMask = (CRF_APB_VPLL_CFG_RES_MASK | CRF_APB_VPLL_CFG_CP_MASK | CRF_APB_VPLL_CFG_LFHF_MASK | CRF_APB_VPLL_CFG_LOCK_CNT_MASK | CRF_APB_VPLL_CFG_LOCK_DLY_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_VPLL_CFG_RES_SHIFT
+			| 0x00000003U << CRF_APB_VPLL_CFG_CP_SHIFT
+			| 0x00000003U << CRF_APB_VPLL_CFG_LFHF_SHIFT
+			| 0x0000028AU << CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT
+			| 0x0000003FU << CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E514C62U);
+	/*############################################################################################################################ */
+
+		// : UPDATE FB_DIV
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		PSU_CRF_APB_VPLL_CTRL_PRE_SRC                                                   0x0
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_VPLL_CTRL_FBDIV                                                     0x39
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_VPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00717F00U ,0x00013900U)  
+		RegMask = (CRF_APB_VPLL_CTRL_PRE_SRC_MASK | CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT
+			| 0x00000039U << CRF_APB_VPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00717F00U ,0x00013900U);
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000008U)  
+		RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_VPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000001U)  
+		RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_VPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000000U)  
+		RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044

+
+		VPLL is locked
+		PSU_CRF_APB_PLL_STATUS_VPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000004U ,0x00000004U)  */
+		mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000004U);
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000000U)  
+		RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050

+
+		Divisor value for this clock.
+		PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
+
+		Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A0050, 0x00003F00U ,0x00000300U)  
+		RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000003U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		// : VIDEO FRAC CFG
+		/*Register : VPLL_FRAC_CFG @ 0XFD1A0040

+
+		Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.
+		PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED                                               0x1
+
+		Fractional value for the Feedback value.
+		PSU_CRF_APB_VPLL_FRAC_CFG_DATA                                                  0x820c
+
+		Fractional control for the PLL
+		(OFFSET, MASK, VALUE)      (0XFD1A0040, 0x8000FFFFU ,0x8000820CU)  
+		RegMask = (CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_VPLL_FRAC_CFG_DATA_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT
+			| 0x0000820CU << CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x8000820CU);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_clock_init_data() {
+		// : CLOCK CONTROL SLCR REGISTER
+		/*Register : GEM0_REF_CTRL @ 0XFF5E0050

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0                                              0x8
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0050, 0x063F3F07U ,0x06010800U)  
+		RegMask = (CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000008U << CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_GEM0_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
+	/*############################################################################################################################ */
+
+		/*Register : GEM1_REF_CTRL @ 0XFF5E0054

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0                                              0x8
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0054, 0x063F3F07U ,0x06010800U)  
+		RegMask = (CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000008U << CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_GEM1_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
+	/*############################################################################################################################ */
+
+		/*Register : GEM2_REF_CTRL @ 0XFF5E0058

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM2_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0                                              0x8
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0058, 0x063F3F07U ,0x06010800U)  
+		RegMask = (CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000008U << CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_GEM2_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
+	/*############################################################################################################################ */
+
+		/*Register : GEM3_REF_CTRL @ 0XFF5E005C

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM3_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0                                              0xc
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E005C, 0x063F3F07U ,0x06010C00U)  
+		RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000CU << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_GEM3_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010C00U);
+	/*############################################################################################################################ */
+
+		/*Register : GEM_TSU_REF_CTRL @ 0XFF5E0100

+
+		6 bit divider
+		PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0                                           0x6
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL                                             0x2
+
+		6 bit divider
+		PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1                                           0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0100, 0x013F3F07U ,0x01010602U)  
+		RegMask = (CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK | CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000006U << CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000001U << CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_GEM_TSU_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U);
+	/*############################################################################################################################ */
+
+		/*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT                                            0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1                                          0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0                                          0x6
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL                                            0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0060, 0x023F3F07U ,0x02010600U)  
+		RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000006U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_USB0_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010600U);
+	/*############################################################################################################################ */
+
+		/*Register : USB1_BUS_REF_CTRL @ 0XFF5E0064

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_USB1_BUS_REF_CTRL_CLKACT                                            0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1                                          0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0                                          0x4
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_USB1_BUS_REF_CTRL_SRCSEL                                            0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0064, 0x023F3F07U ,0x02010400U)  
+		RegMask = (CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000004U << CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_USB1_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010400U);
+	/*############################################################################################################################ */
+
+		/*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT                                           0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1                                         0xf
+
+		6 bit divider
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0                                         0x5
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL                                           0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E004C, 0x023F3F07U ,0x020F0500U)  
+		RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
+			| 0x0000000FU << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000005U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET ,0x023F3F07U ,0x020F0500U);
+	/*############################################################################################################################ */
+
+		/*Register : QSPI_REF_CTRL @ 0XFF5E0068

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_QSPI_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                                              0xc
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010C00U)  
+		RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000CU << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U);
+	/*############################################################################################################################ */
+
+		/*Register : SDIO0_REF_CTRL @ 0XFF5E006C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1                                             0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0                                             0x7
+
+		000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL                                               0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E006C, 0x013F3F07U ,0x01010702U)  
+		RegMask = (CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000007U << CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_SDIO0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
+	/*############################################################################################################################ */
+
+		/*Register : SDIO1_REF_CTRL @ 0XFF5E0070

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1                                             0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0                                             0x6
+
+		000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL                                               0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0070, 0x013F3F07U ,0x01010602U)  
+		RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000006U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_SDIO1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U);
+	/*############################################################################################################################ */
+
+		/*Register : SDIO_CLK_CTRL @ 0XFF18030C

+
+		MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]
+		PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL                                     0
+
+		SoC Debug Clock Control
+		(OFFSET, MASK, VALUE)      (0XFF18030C, 0x00020000U ,0x00000000U)  
+		RegMask = (IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_SDIO_CLK_CTRL_OFFSET ,0x00020000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : UART0_REF_CTRL @ 0XFF5E0074

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_UART0_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1                                             0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0                                             0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_UART0_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0074, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_UART0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : UART1_REF_CTRL @ 0XFF5E0078

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_UART1_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1                                             0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0                                             0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_UART1_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0078, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_UART1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : I2C0_REF_CTRL @ 0XFF5E0120

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_I2C0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0                                              0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0120, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_I2C0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : I2C1_REF_CTRL @ 0XFF5E0124

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_I2C1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0                                              0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0124, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_I2C1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : SPI0_REF_CTRL @ 0XFF5E007C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SPI0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0                                              0x7
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL                                                0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E007C, 0x013F3F07U ,0x01010702U)  
+		RegMask = (CRL_APB_SPI0_REF_CTRL_CLKACT_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000007U << CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_SPI0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
+	/*############################################################################################################################ */
+
+		/*Register : SPI1_REF_CTRL @ 0XFF5E0080

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SPI1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0                                              0x7
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL                                                0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0080, 0x013F3F07U ,0x01010702U)  
+		RegMask = (CRL_APB_SPI1_REF_CTRL_CLKACT_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000007U << CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_SPI1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
+	/*############################################################################################################################ */
+
+		/*Register : CAN0_REF_CTRL @ 0XFF5E0084

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CAN0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0                                              0xa
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0084, 0x013F3F07U ,0x01010A00U)  
+		RegMask = (CRL_APB_CAN0_REF_CTRL_CLKACT_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000AU << CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_CAN0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010A00U);
+	/*############################################################################################################################ */
+
+		/*Register : CAN1_REF_CTRL @ 0XFF5E0088

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CAN1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0                                              0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0088, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_CAN1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : CPU_R5_CTRL @ 0XFF5E0090

+
+		Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
+		d lead to system hang
+		PSU_CRL_APB_CPU_R5_CTRL_CLKACT                                                  0x1
+
+		6 bit divider
+		PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0                                                0x3
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CPU_R5_CTRL_SRCSEL                                                  0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0090, 0x01003F07U ,0x01000302U)  
+		RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
+			| 0x00000003U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_CPU_R5_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
+	/*############################################################################################################################ */
+
+		/*Register : IOU_SWITCH_CTRL @ 0XFF5E009C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0                                            0x6
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL                                              0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E009C, 0x01003F07U ,0x01000602U)  
+		RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
+			| 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOU_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
+	/*############################################################################################################################ */
+
+		/*Register : CSU_PLL_CTRL @ 0XFF5E00A0

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CSU_PLL_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_CSU_PLL_CTRL_DIVISOR0                                               0x3
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CSU_PLL_CTRL_SRCSEL                                                 0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00A0, 0x01003F07U ,0x01000302U)  
+		RegMask = (CRL_APB_CSU_PLL_CTRL_CLKACT_MASK | CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK | CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT
+			| 0x00000003U << CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_CSU_PLL_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
+	/*############################################################################################################################ */
+
+		/*Register : PCAP_CTRL @ 0XFF5E00A4

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PCAP_CTRL_CLKACT                                                    0x1
+
+		6 bit divider
+		PSU_CRL_APB_PCAP_CTRL_DIVISOR0                                                  0x6
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PCAP_CTRL_SRCSEL                                                    0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00A4, 0x01003F07U ,0x01000602U)  
+		RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT
+			| 0x00000006U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_PCAP_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
+	/*############################################################################################################################ */
+
+		/*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0                                            0x3
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL                                              0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00A8, 0x01003F07U ,0x01000302U)  
+		RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
+			| 0x00000003U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_LPD_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
+	/*############################################################################################################################ */
+
+		/*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0                                             0xf
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL                                               0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00AC, 0x01003F07U ,0x01000F02U)  
+		RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
+			| 0x0000000FU << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_LPD_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000F02U);
+	/*############################################################################################################################ */
+
+		/*Register : DBG_LPD_CTRL @ 0XFF5E00B0

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_DBG_LPD_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0                                               0x6
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL                                                 0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B0, 0x01003F07U ,0x01000602U)  
+		RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
+			| 0x00000006U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_DBG_LPD_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
+	/*############################################################################################################################ */
+
+		/*Register : NAND_REF_CTRL @ 0XFF5E00B4

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_NAND_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0                                              0xa
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_NAND_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B4, 0x013F3F07U ,0x01010A00U)  
+		RegMask = (CRL_APB_NAND_REF_CTRL_CLKACT_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK | CRL_APB_NAND_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000AU << CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_NAND_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010A00U);
+	/*############################################################################################################################ */
+
+		/*Register : ADMA_REF_CTRL @ 0XFF5E00B8

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_ADMA_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0                                              0x3
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL                                                0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B8, 0x01003F07U ,0x01000302U)  
+		RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
+			| 0x00000003U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_ADMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
+	/*############################################################################################################################ */
+
+		/*Register : PL0_REF_CTRL @ 0XFF5E00C0

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PL0_REF_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0                                               0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PL0_REF_CTRL_SRCSEL                                                 0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00C0, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_PL0_REF_CTRL_CLKACT_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_PL0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : PL1_REF_CTRL @ 0XFF5E00C4

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PL1_REF_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1                                               0x4
+
+		6 bit divider
+		PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0                                               0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PL1_REF_CTRL_SRCSEL                                                 0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00C4, 0x013F3F07U ,0x01040F00U)  
+		RegMask = (CRL_APB_PL1_REF_CTRL_CLKACT_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000004U << CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_PL1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01040F00U);
+	/*############################################################################################################################ */
+
+		/*Register : PL2_REF_CTRL @ 0XFF5E00C8

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PL2_REF_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0                                               0x4
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PL2_REF_CTRL_SRCSEL                                                 0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00C8, 0x013F3F07U ,0x01010402U)  
+		RegMask = (CRL_APB_PL2_REF_CTRL_CLKACT_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL2_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000004U << CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_PL2_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010402U);
+	/*############################################################################################################################ */
+
+		/*Register : PL3_REF_CTRL @ 0XFF5E00CC

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PL3_REF_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0                                               0x3
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PL3_REF_CTRL_SRCSEL                                                 0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00CC, 0x013F3F07U ,0x01010302U)  
+		RegMask = (CRL_APB_PL3_REF_CTRL_CLKACT_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL3_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000003U << CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_PL3_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010302U);
+	/*############################################################################################################################ */
+
+		/*Register : AMS_REF_CTRL @ 0XFF5E0108

+
+		6 bit divider
+		PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0                                               0x1d
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_AMS_REF_CTRL_SRCSEL                                                 0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_AMS_REF_CTRL_CLKACT                                                 0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0108, 0x013F3F07U ,0x01011D02U)  
+		RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000001DU << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_AMS_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011D02U);
+	/*############################################################################################################################ */
+
+		/*Register : DLL_REF_CTRL @ 0XFF5E0104

+
+		000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
+		is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_DLL_REF_CTRL_SRCSEL                                                 0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0104, 0x00000007U ,0x00000000U)  
+		RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_DLL_REF_CTRL_OFFSET ,0x00000007U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128

+
+		6 bit divider
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0                                         0xf
+
+		1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 
+		 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL                                           0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT                                           0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0128, 0x01003F07U ,0x01000F00U)  
+		RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x0000000FU << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET ,0x01003F07U ,0x01000F00U);
+	/*############################################################################################################################ */
+
+		/*Register : SATA_REF_CTRL @ 0XFD1A00A0

+
+		000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_SATA_REF_CTRL_SRCSEL                                                0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_SATA_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0                                              0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00A0, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_SATA_REF_CTRL_SRCSEL_MASK | CRF_APB_SATA_REF_CTRL_CLKACT_MASK | CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_SATA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : PCIE_REF_CTRL @ 0XFD1A00B4

+
+		000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
+		es of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL                                                0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_PCIE_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0                                              0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00B4, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_PCIE_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070

+
+		6 bit divider
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1                                          0x1
+
+		6 bit divider
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0                                          0x3
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 
+		ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL                                            0x3
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT                                            0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0070, 0x013F3F07U ,0x01010303U)  
+		RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010303U);
+	/*############################################################################################################################ */
+
+		/*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074

+
+		6 bit divider
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1                                          0x1
+
+		6 bit divider
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0                                          0x27
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 
+		ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL                                            0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT                                            0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0074, 0x013F3F07U ,0x01012700U)  
+		RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000027U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01012700U);
+	/*############################################################################################################################ */
+
+		/*Register : DP_STC_REF_CTRL @ 0XFD1A007C

+
+		6 bit divider
+		PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1                                            0x1
+
+		6 bit divider
+		PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0                                            0x11
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
+		e new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL                                              0x3
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT                                              0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A007C, 0x013F3F07U ,0x01011103U)  
+		RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000011U << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000003U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DP_STC_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011103U);
+	/*############################################################################################################################ */
+
+		/*Register : ACPU_CTRL @ 0XFD1A0060

+
+		6 bit divider
+		PSU_CRF_APB_ACPU_CTRL_DIVISOR0                                                  0x1
+
+		000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_ACPU_CTRL_SRCSEL                                                    0x0
+
+		Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock
+		PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF                                               0x1
+
+		Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
+		 to the entire APU
+		PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0060, 0x03003F07U ,0x03000100U)  
+		RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
+			| 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_ACPU_CTRL_OFFSET ,0x03003F07U ,0x03000100U);
+	/*############################################################################################################################ */
+
+		/*Register : DBG_TRACE_CTRL @ 0XFD1A0064

+
+		6 bit divider
+		PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0                                             0x2
+
+		000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL                                               0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0064, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DBG_TRACE_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : DBG_FPD_CTRL @ 0XFD1A0068

+
+		6 bit divider
+		PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0                                               0x2
+
+		000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL                                                 0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DBG_FPD_CTRL_CLKACT                                                 0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0068, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DBG_FPD_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : DDR_CTRL @ 0XFD1A0080

+
+		6 bit divider
+		PSU_CRF_APB_DDR_CTRL_DIVISOR0                                                   0x2
+
+		000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This 
+		s not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DDR_CTRL_SRCSEL                                                     0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0080, 0x00003F07U ,0x00000200U)  
+		RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DDR_CTRL_OFFSET ,0x00003F07U ,0x00000200U);
+	/*############################################################################################################################ */
+
+		/*Register : GPU_REF_CTRL @ 0XFD1A0084

+
+		6 bit divider
+		PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0                                               0x1
+
+		000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GPU_REF_CTRL_SRCSEL                                                 0x0
+
+		Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).
+		PSU_CRF_APB_GPU_REF_CTRL_CLKACT                                                 0x1
+
+		Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
+		PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT                                             0x1
+
+		Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
+		PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0084, 0x07003F07U ,0x07000100U)  
+		RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_GPU_REF_CTRL_OFFSET ,0x07003F07U ,0x07000100U);
+	/*############################################################################################################################ */
+
+		/*Register : GDMA_REF_CTRL @ 0XFD1A00B8

+
+		6 bit divider
+		PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0                                              0x2
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL                                                0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_GDMA_REF_CTRL_CLKACT                                                0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00B8, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_GDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : DPDMA_REF_CTRL @ 0XFD1A00BC

+
+		6 bit divider
+		PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0                                             0x2
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL                                               0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00BC, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0

+
+		6 bit divider
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0                                            0x2
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL                                              0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT                                              0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C0, 0x01003F07U ,0x01000202U)  
+		RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_TOPSW_MAIN_CTRL_OFFSET ,0x01003F07U ,0x01000202U);
+	/*############################################################################################################################ */
+
+		/*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4

+
+		6 bit divider
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0                                           0x5
+
+		000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL                                             0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C4, 0x01003F07U ,0x01000502U)  
+		RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000005U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000502U);
+	/*############################################################################################################################ */
+
+		/*Register : GTGREF0_REF_CTRL @ 0XFD1A00C8

+
+		6 bit divider
+		PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0                                           0x4
+
+		000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL                                             0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C8, 0x01003F07U ,0x01000400U)  
+		RegMask = (CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK | CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK | CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000004U << CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_GTGREF0_REF_CTRL_OFFSET ,0x01003F07U ,0x01000400U);
+	/*############################################################################################################################ */
+
+		/*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8

+
+		6 bit divider
+		PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0                                             0x2
+
+		000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00F8, 0x00003F07U ,0x00000200U)  
+		RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DBG_TSTMP_CTRL_OFFSET ,0x00003F07U ,0x00000200U);
+	/*############################################################################################################################ */
+
+		/*Register : IOU_TTC_APB_CLK @ 0XFF180380

+
+		00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
+		0" = Select the R5 clock for the APB interface of TTC0
+		PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL                                           0
+
+		00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
+		0" = Select the R5 clock for the APB interface of TTC1
+		PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL                                           0
+
+		00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
+		0" = Select the R5 clock for the APB interface of TTC2
+		PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL                                           0
+
+		00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
+		0" = Select the R5 clock for the APB interface of TTC3
+		PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL                                           0
+
+		TTC APB clock select
+		(OFFSET, MASK, VALUE)      (0XFF180380, 0x000000FFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_IOU_TTC_APB_CLK_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : WDT_CLK_SEL @ 0XFD610100

+
+		System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)
+		PSU_FPD_SLCR_WDT_CLK_SEL_SELECT                                                 0
+
+		SWDT clock source select
+		(OFFSET, MASK, VALUE)      (0XFD610100, 0x00000001U ,0x00000000U)  
+		RegMask = (FPD_SLCR_WDT_CLK_SEL_SELECT_MASK |  0 );
+
+		RegVal = ((0x00000000U << FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (FPD_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : WDT_CLK_SEL @ 0XFF180300

+
+		System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout 
+		ia MIO
+		PSU_IOU_SLCR_WDT_CLK_SEL_SELECT                                                 0
+
+		SWDT clock source select
+		(OFFSET, MASK, VALUE)      (0XFF180300, 0x00000001U ,0x00000000U)  
+		RegMask = (IOU_SLCR_WDT_CLK_SEL_SELECT_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050

+
+		System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk
+		PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT                                          0
+
+		SWDT clock source select
+		(OFFSET, MASK, VALUE)      (0XFF410050, 0x00000001U ,0x00000000U)  
+		RegMask = (LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK |  0 );
+
+		RegVal = ((0x00000000U << LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_ddr_init_data() {
+		// : DDR INITIALIZATION
+		// : DDR CONTROLLER RESET
+		/*Register : RST_DDR_SS @ 0XFD1A0108

+
+		DDR block level reset inside of the DDR Sub System
+		PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X1
+
+		DDR sub system block level reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000008U)  
+		RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MSTR @ 0XFD070000

+
+		Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 
+		evice
+		PSU_DDRC_MSTR_DEVICE_CONFIG                                                     0x1
+
+		Choose which registers are used. - 0 - Original registers - 1 - Shadow registers
+		PSU_DDRC_MSTR_FREQUENCY_MODE                                                    0x0
+
+		Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
+		esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - 
+		ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
+		ks - 1111 - Four ranks
+		PSU_DDRC_MSTR_ACTIVE_RANKS                                                      0x1
+
+		SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
+		 of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls 
+		he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
+		-fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
+		 is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
+		PSU_DDRC_MSTR_BURST_RDWR                                                        0x4
+
+		Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM 
+		n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
+		l_off_mode is not supported, and this bit must be set to '0'.
+		PSU_DDRC_MSTR_DLL_OFF_MODE                                                      0x0
+
+		Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
+		AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
+		dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
+		figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).
+		PSU_DDRC_MSTR_DATA_BUS_WIDTH                                                    0x0
+
+		1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
+		 only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode 
+		s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set
+		PSU_DDRC_MSTR_GEARDOWN_MODE                                                     0x0
+
+		If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held 
+		or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in 
+		PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
+		ing is not supported in DDR4 geardown mode.
+		PSU_DDRC_MSTR_EN_2T_TIMING_MODE                                                 0x0
+
+		When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
+		t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
+		 (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
+		_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'
+		PSU_DDRC_MSTR_BURSTCHOP                                                         0x0
+
+		Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
+		port LPDDR4.
+		PSU_DDRC_MSTR_LPDDR4                                                            0x0
+
+		Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support 
+		DR4.
+		PSU_DDRC_MSTR_DDR4                                                              0x1
+
+		Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
+		port LPDDR3.
+		PSU_DDRC_MSTR_LPDDR3                                                            0x0
+
+		Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
+		port LPDDR2.
+		PSU_DDRC_MSTR_LPDDR2                                                            0x0
+
+		Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
+		
+		PSU_DDRC_MSTR_DDR3                                                              0x0
+
+		Master Register
+		(OFFSET, MASK, VALUE)      (0XFD070000, 0xE30FBE3DU ,0x41040010U)  
+		RegMask = (DDRC_MSTR_DEVICE_CONFIG_MASK | DDRC_MSTR_FREQUENCY_MODE_MASK | DDRC_MSTR_ACTIVE_RANKS_MASK | DDRC_MSTR_BURST_RDWR_MASK | DDRC_MSTR_DLL_OFF_MODE_MASK | DDRC_MSTR_DATA_BUS_WIDTH_MASK | DDRC_MSTR_GEARDOWN_MODE_MASK | DDRC_MSTR_EN_2T_TIMING_MODE_MASK | DDRC_MSTR_BURSTCHOP_MASK | DDRC_MSTR_LPDDR4_MASK | DDRC_MSTR_DDR4_MASK | DDRC_MSTR_LPDDR3_MASK | DDRC_MSTR_LPDDR2_MASK | DDRC_MSTR_DDR3_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_MSTR_DEVICE_CONFIG_SHIFT
+			| 0x00000000U << DDRC_MSTR_FREQUENCY_MODE_SHIFT
+			| 0x00000001U << DDRC_MSTR_ACTIVE_RANKS_SHIFT
+			| 0x00000004U << DDRC_MSTR_BURST_RDWR_SHIFT
+			| 0x00000000U << DDRC_MSTR_DLL_OFF_MODE_SHIFT
+			| 0x00000000U << DDRC_MSTR_DATA_BUS_WIDTH_SHIFT
+			| 0x00000000U << DDRC_MSTR_GEARDOWN_MODE_SHIFT
+			| 0x00000000U << DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT
+			| 0x00000000U << DDRC_MSTR_BURSTCHOP_SHIFT
+			| 0x00000000U << DDRC_MSTR_LPDDR4_SHIFT
+			| 0x00000001U << DDRC_MSTR_DDR4_SHIFT
+			| 0x00000000U << DDRC_MSTR_LPDDR3_SHIFT
+			| 0x00000000U << DDRC_MSTR_LPDDR2_SHIFT
+			| 0x00000000U << DDRC_MSTR_DDR3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_MSTR_OFFSET ,0xE30FBE3DU ,0x41040010U);
+	/*############################################################################################################################ */
+
+		/*Register : MRCTRL0 @ 0XFD070010

+
+		Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
+		 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
+		re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
+		PSU_DDRC_MRCTRL0_MR_WR                                                          0x0
+
+		Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
+		 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
+		R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
+		dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well 
+		s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
+		put Inversion of RDIMMs.
+		PSU_DDRC_MRCTRL0_MR_ADDR                                                        0x0
+
+		Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
+		 However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
+		amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks 
+		 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3
+		PSU_DDRC_MRCTRL0_MR_RANK                                                        0x3
+
+		Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. 
+		or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
+		 be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared 
+		o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
+		n is not allowed - 1 - Software intervention is allowed
+		PSU_DDRC_MRCTRL0_SW_INIT_INT                                                    0x0
+
+		Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
+		PSU_DDRC_MRCTRL0_PDA_EN                                                         0x0
+
+		Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
+		PSU_DDRC_MRCTRL0_MPR_EN                                                         0x0
+
+		Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
+		d
+		PSU_DDRC_MRCTRL0_MR_TYPE                                                        0x0
+
+		Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i
+		it_int - pda_en - mpr_en
+		(OFFSET, MASK, VALUE)      (0XFD070010, 0x8000F03FU ,0x00000030U)  
+		RegMask = (DDRC_MRCTRL0_MR_WR_MASK | DDRC_MRCTRL0_MR_ADDR_MASK | DDRC_MRCTRL0_MR_RANK_MASK | DDRC_MRCTRL0_SW_INIT_INT_MASK | DDRC_MRCTRL0_PDA_EN_MASK | DDRC_MRCTRL0_MPR_EN_MASK | DDRC_MRCTRL0_MR_TYPE_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_MRCTRL0_MR_WR_SHIFT
+			| 0x00000000U << DDRC_MRCTRL0_MR_ADDR_SHIFT
+			| 0x00000003U << DDRC_MRCTRL0_MR_RANK_SHIFT
+			| 0x00000000U << DDRC_MRCTRL0_SW_INIT_INT_SHIFT
+			| 0x00000000U << DDRC_MRCTRL0_PDA_EN_SHIFT
+			| 0x00000000U << DDRC_MRCTRL0_MPR_EN_SHIFT
+			| 0x00000000U << DDRC_MRCTRL0_MR_TYPE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_MRCTRL0_OFFSET ,0x8000F03FU ,0x00000030U);
+	/*############################################################################################################################ */
+
+		/*Register : DERATEEN @ 0XFD070020

+
+		Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
+		 Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
+		g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.
+		PSU_DDRC_DERATEEN_RC_DERATE_VALUE                                               0x3
+
+		Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
+		r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
+		PSU_DDRC_DERATEEN_DERATE_BYTE                                                   0x0
+
+		Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
+		4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
+		for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.
+		PSU_DDRC_DERATEEN_DERATE_VALUE                                                  0x0
+
+		Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
+		Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
+		mode.
+		PSU_DDRC_DERATEEN_DERATE_ENABLE                                                 0x0
+
+		Temperature Derate Enable Register
+		(OFFSET, MASK, VALUE)      (0XFD070020, 0x000003F3U ,0x00000300U)  
+		RegMask = (DDRC_DERATEEN_RC_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_BYTE_MASK | DDRC_DERATEEN_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_ENABLE_MASK |  0 );
+
+		RegVal = ((0x00000003U << DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT
+			| 0x00000000U << DDRC_DERATEEN_DERATE_BYTE_SHIFT
+			| 0x00000000U << DDRC_DERATEEN_DERATE_VALUE_SHIFT
+			| 0x00000000U << DDRC_DERATEEN_DERATE_ENABLE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DERATEEN_OFFSET ,0x000003F3U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		/*Register : DERATEINT @ 0XFD070024

+
+		Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
+		DR3/LPDDR4. This register must not be set to zero
+		PSU_DDRC_DERATEINT_MR4_READ_INTERVAL                                            0x800000
+
+		Temperature Derate Interval Register
+		(OFFSET, MASK, VALUE)      (0XFD070024, 0xFFFFFFFFU ,0x00800000U)  
+		RegMask = (DDRC_DERATEINT_MR4_READ_INTERVAL_MASK |  0 );
+
+		RegVal = ((0x00800000U << DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DERATEINT_OFFSET ,0xFFFFFFFFU ,0x00800000U);
+	/*############################################################################################################################ */
+
+		/*Register : PWRCTL @ 0XFD070030

+
+		Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
+		r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 
+		 - Allow transition from Self refresh state
+		PSU_DDRC_PWRCTL_STAY_IN_SELFREF                                                 0x0
+
+		A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
+		M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
+		are Exit from Self Refresh
+		PSU_DDRC_PWRCTL_SELFREF_SW                                                      0x0
+
+		When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
+		st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For 
+		on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
+		DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PWRCTL_MPSM_EN                                                         0x0
+
+		Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
+		is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
+		4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in 
+		ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
+		rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)
+		PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE                                         0x0
+
+		When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
+		et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down 
+		xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
+		 should not be set to 1. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN                                                0x0
+
+		If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
+		RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.
+		PSU_DDRC_PWRCTL_POWERDOWN_EN                                                    0x0
+
+		If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
+		f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.
+		PSU_DDRC_PWRCTL_SELFREF_EN                                                      0x0
+
+		Low Power Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070030, 0x0000007FU ,0x00000000U)  
+		RegMask = (DDRC_PWRCTL_STAY_IN_SELFREF_MASK | DDRC_PWRCTL_SELFREF_SW_MASK | DDRC_PWRCTL_MPSM_EN_MASK | DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK | DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK | DDRC_PWRCTL_POWERDOWN_EN_MASK | DDRC_PWRCTL_SELFREF_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_SELFREF_SW_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_MPSM_EN_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_POWERDOWN_EN_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_SELFREF_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PWRCTL_OFFSET ,0x0000007FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : PWRTMG @ 0XFD070034

+
+		After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in 
+		he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PWRTMG_SELFREF_TO_X32                                                  0x40
+
+		Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
+		ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
+		iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PWRTMG_T_DPD_X4096                                                     0x84
+
+		After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
+		 PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
+		PSU_DDRC_PWRTMG_POWERDOWN_TO_X32                                                0x10
+
+		Low Power Timing Register
+		(OFFSET, MASK, VALUE)      (0XFD070034, 0x00FFFF1FU ,0x00408410U)  
+		RegMask = (DDRC_PWRTMG_SELFREF_TO_X32_MASK | DDRC_PWRTMG_T_DPD_X4096_MASK | DDRC_PWRTMG_POWERDOWN_TO_X32_MASK |  0 );
+
+		RegVal = ((0x00000040U << DDRC_PWRTMG_SELFREF_TO_X32_SHIFT
+			| 0x00000084U << DDRC_PWRTMG_T_DPD_X4096_SHIFT
+			| 0x00000010U << DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PWRTMG_OFFSET ,0x00FFFF1FU ,0x00408410U);
+	/*############################################################################################################################ */
+
+		/*Register : RFSHCTL0 @ 0XFD070050

+
+		Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
+		d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
+		 It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
+		may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
+		om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.
+		PSU_DDRC_RFSHCTL0_REFRESH_MARGIN                                                0x2
+
+		If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
+		1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
+		 would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
+		HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
+		formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
+		ued to the uMCTL2. FOR PERFORMANCE ONLY.
+		PSU_DDRC_RFSHCTL0_REFRESH_TO_X32                                                0x10
+
+		The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
+		reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
+		reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
+		RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
+		. - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
+		tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
+		fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
+		ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
+		tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
+		d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
+		initiated update is complete.
+		PSU_DDRC_RFSHCTL0_REFRESH_BURST                                                 0x0
+
+		- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
+		t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
+		support LPDDR2/LPDDR3/LPDDR4
+		PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH                                              0x0
+
+		Refresh Control Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070050, 0x00F1F1F4U ,0x00210000U)  
+		RegMask = (DDRC_RFSHCTL0_REFRESH_MARGIN_MASK | DDRC_RFSHCTL0_REFRESH_TO_X32_MASK | DDRC_RFSHCTL0_REFRESH_BURST_MASK | DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT
+			| 0x00000010U << DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT
+			| 0x00000000U << DDRC_RFSHCTL0_REFRESH_BURST_SHIFT
+			| 0x00000000U << DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_RFSHCTL0_OFFSET ,0x00F1F1F4U ,0x00210000U);
+	/*############################################################################################################################ */
+
+		/*Register : RFSHCTL3 @ 0XFD070060

+
+		Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
+		ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
+		orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
+		self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in 
+		uture version of the uMCTL2.
+		PSU_DDRC_RFSHCTL3_REFRESH_MODE                                                  0x0
+
+		Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value 
+		s automatically updated when exiting reset, so it does not need to be toggled initially.
+		PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL                                          0x0
+
+		When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
+		ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
+		auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
+		is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. 
+		his register field is changeable on the fly.
+		PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH                                              0x1
+
+		Refresh Control Register 3
+		(OFFSET, MASK, VALUE)      (0XFD070060, 0x00000073U ,0x00000001U)  
+		RegMask = (DDRC_RFSHCTL3_REFRESH_MODE_MASK | DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK | DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_RFSHCTL3_REFRESH_MODE_SHIFT
+			| 0x00000000U << DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT
+			| 0x00000001U << DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_RFSHCTL3_OFFSET ,0x00000073U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : RFSHTMG @ 0XFD070064

+
+		tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
+		 for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
+		, this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should 
+		e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
+		ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
+		programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
+		TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.
+		PSU_DDRC_RFSHTMG_T_RFC_NOM_X32                                                  0x82
+
+		Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the 
+		REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
+		 - 0 - tREFBW parameter not used - 1 - tREFBW parameter used
+		PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN                                               0x1
+
+		tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
+		 RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
+		DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
+		 per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
+		equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
+		opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.
+		PSU_DDRC_RFSHTMG_T_RFC_MIN                                                      0x8b
+
+		Refresh Timing Register
+		(OFFSET, MASK, VALUE)      (0XFD070064, 0x0FFF83FFU ,0x0082808BU)  
+		RegMask = (DDRC_RFSHTMG_T_RFC_NOM_X32_MASK | DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK | DDRC_RFSHTMG_T_RFC_MIN_MASK |  0 );
+
+		RegVal = ((0x00000082U << DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT
+			| 0x00000001U << DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT
+			| 0x0000008BU << DDRC_RFSHTMG_T_RFC_MIN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_RFSHTMG_OFFSET ,0x0FFF83FFU ,0x0082808BU);
+	/*############################################################################################################################ */
+
+		/*Register : ECCCFG0 @ 0XFD070070

+
+		Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined
+		PSU_DDRC_ECCCFG0_DIS_SCRUB                                                      0x1
+
+		ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
+		 use
+		PSU_DDRC_ECCCFG0_ECC_MODE                                                       0x0
+
+		ECC Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070070, 0x00000017U ,0x00000010U)  
+		RegMask = (DDRC_ECCCFG0_DIS_SCRUB_MASK | DDRC_ECCCFG0_ECC_MODE_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_ECCCFG0_DIS_SCRUB_SHIFT
+			| 0x00000000U << DDRC_ECCCFG0_ECC_MODE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ECCCFG0_OFFSET ,0x00000017U ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : ECCCFG1 @ 0XFD070074

+
+		Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
+		ng, if ECCCFG1.data_poison_en=1
+		PSU_DDRC_ECCCFG1_DATA_POISON_BIT                                                0x0
+
+		Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers
+		PSU_DDRC_ECCCFG1_DATA_POISON_EN                                                 0x0
+
+		ECC Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070074, 0x00000003U ,0x00000000U)  
+		RegMask = (DDRC_ECCCFG1_DATA_POISON_BIT_MASK | DDRC_ECCCFG1_DATA_POISON_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT
+			| 0x00000000U << DDRC_ECCCFG1_DATA_POISON_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ECCCFG1_OFFSET ,0x00000003U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : CRCPARCTL1 @ 0XFD0700C4

+
+		The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
+		the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY 
+		pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
+		L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
+		dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
+		e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks
+		PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT                                             0x10
+
+		After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
+		M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
+		the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
+		the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
+		RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
+		 handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
+		rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
+		ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in 
+		he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is 
+		one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in 
+		PR Page 1 should be treated as 'Don't care'.
+		PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW                                           0x1
+
+		- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
+		 CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
+		 disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)
+		PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE                                     0x0
+
+		CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
+		d to support DDR4.
+		PSU_DDRC_CRCPARCTL1_CRC_INC_DM                                                  0x0
+
+		CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
+		 CRC mode register setting in the DRAM.
+		PSU_DDRC_CRCPARCTL1_CRC_ENABLE                                                  0x0
+
+		C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of 
+		/A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
+		is register should be 1.
+		PSU_DDRC_CRCPARCTL1_PARITY_ENABLE                                               0x0
+
+		CRC Parity Control Register1
+		(OFFSET, MASK, VALUE)      (0XFD0700C4, 0x3F000391U ,0x10000200U)  
+		RegMask = (DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK | DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK | DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK | DDRC_CRCPARCTL1_CRC_INC_DM_MASK | DDRC_CRCPARCTL1_CRC_ENABLE_MASK | DDRC_CRCPARCTL1_PARITY_ENABLE_MASK |  0 );
+
+		RegVal = ((0x00000010U << DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT
+			| 0x00000001U << DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT
+			| 0x00000000U << DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT
+			| 0x00000000U << DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT
+			| 0x00000000U << DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT
+			| 0x00000000U << DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_CRCPARCTL1_OFFSET ,0x3F000391U ,0x10000200U);
+	/*############################################################################################################################ */
+
+		/*Register : CRCPARCTL2 @ 0XFD0700C8

+
+		Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
+		 - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
+		er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
+		PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX                                          0x40
+
+		Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
+		tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
+		value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
+		PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX                                          0x5
+
+		Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
+		ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
+		er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
+		les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
+		or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
+		ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
+		max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
+		bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
+		+ board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
+		ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The 
+		ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
+		to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
+		 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
+		PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
+		_FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
+		C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
+		e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
+		 bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
+		H-6 Values of 0, 1 and 2 are illegal.
+		PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4                                0x1f
+
+		CRC Parity Control Register2
+		(OFFSET, MASK, VALUE)      (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU)  
+		RegMask = (DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK |  0 );
+
+		RegVal = ((0x00000040U << DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT
+			| 0x00000005U << DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT
+			| 0x0000001FU << DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_CRCPARCTL2_OFFSET ,0x01FF1F3FU ,0x0040051FU);
+	/*############################################################################################################################ */
+
+		/*Register : INIT0 @ 0XFD0700D0

+
+		If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
+		 in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
+		ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
+		r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported 
+		or LPDDR4 in this version of the uMCTL2.
+		PSU_DDRC_INIT0_SKIP_DRAM_INIT                                                   0x0
+
+		Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires 
+		 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
+		grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
+		MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.
+		PSU_DDRC_INIT0_POST_CKE_X1024                                                   0x2
+
+		Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 
+		pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
+		tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
+		 to next integer value.
+		PSU_DDRC_INIT0_PRE_CKE_X1024                                                    0x106
+
+		SDRAM Initialization Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U)  
+		RegMask = (DDRC_INIT0_SKIP_DRAM_INIT_MASK | DDRC_INIT0_POST_CKE_X1024_MASK | DDRC_INIT0_PRE_CKE_X1024_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_INIT0_SKIP_DRAM_INIT_SHIFT
+			| 0x00000002U << DDRC_INIT0_POST_CKE_X1024_SHIFT
+			| 0x00000106U << DDRC_INIT0_PRE_CKE_X1024_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT0_OFFSET ,0xC3FF0FFFU ,0x00020106U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT1 @ 0XFD0700D4

+
+		Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
+		LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1
+		PSU_DDRC_INIT1_DRAM_RSTN_X1024                                                  0x2
+
+		Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
+		bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.
+		PSU_DDRC_INIT1_FINAL_WAIT_X32                                                   0x0
+
+		Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
+		. There is no known specific requirement for this; it may be set to zero.
+		PSU_DDRC_INIT1_PRE_OCD_X32                                                      0x0
+
+		SDRAM Initialization Register 1
+		(OFFSET, MASK, VALUE)      (0XFD0700D4, 0x01FF7F0FU ,0x00020000U)  
+		RegMask = (DDRC_INIT1_DRAM_RSTN_X1024_MASK | DDRC_INIT1_FINAL_WAIT_X32_MASK | DDRC_INIT1_PRE_OCD_X32_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_INIT1_DRAM_RSTN_X1024_SHIFT
+			| 0x00000000U << DDRC_INIT1_FINAL_WAIT_X32_SHIFT
+			| 0x00000000U << DDRC_INIT1_PRE_OCD_X32_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT1_OFFSET ,0x01FF7F0FU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT2 @ 0XFD0700D8

+
+		Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.
+		PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32                                             0x23
+
+		Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
+		e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.
+		PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1                                              0x5
+
+		SDRAM Initialization Register 2
+		(OFFSET, MASK, VALUE)      (0XFD0700D8, 0x0000FF0FU ,0x00002305U)  
+		RegMask = (DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK | DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK |  0 );
+
+		RegVal = ((0x00000023U << DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT
+			| 0x00000005U << DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT2_OFFSET ,0x0000FF0FU ,0x00002305U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT3 @ 0XFD0700DC

+
+		DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
+		 DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
+		register
+		PSU_DDRC_INIT3_MR                                                               0x930
+
+		DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
+		bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
+		 bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
+		lue to write to MR2 register
+		PSU_DDRC_INIT3_EMR                                                              0x301
+
+		SDRAM Initialization Register 3
+		(OFFSET, MASK, VALUE)      (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U)  
+		RegMask = (DDRC_INIT3_MR_MASK | DDRC_INIT3_EMR_MASK |  0 );
+
+		RegVal = ((0x00000930U << DDRC_INIT3_MR_SHIFT
+			| 0x00000301U << DDRC_INIT3_EMR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT3_OFFSET ,0xFFFFFFFFU ,0x09300301U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT4 @ 0XFD0700E0

+
+		DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 
+		egister mDDR: Unused
+		PSU_DDRC_INIT4_EMR2                                                             0x20
+
+		DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to 
+		rite to MR13 register
+		PSU_DDRC_INIT4_EMR3                                                             0x200
+
+		SDRAM Initialization Register 4
+		(OFFSET, MASK, VALUE)      (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U)  
+		RegMask = (DDRC_INIT4_EMR2_MASK | DDRC_INIT4_EMR3_MASK |  0 );
+
+		RegVal = ((0x00000020U << DDRC_INIT4_EMR2_SHIFT
+			| 0x00000200U << DDRC_INIT4_EMR3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT4_OFFSET ,0xFFFFFFFFU ,0x00200200U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT5 @ 0XFD0700E4

+
+		ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock 
+		ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.
+		PSU_DDRC_INIT5_DEV_ZQINIT_X32                                                   0x21
+
+		Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
+		3 typically requires 10 us.
+		PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024                                              0x4
+
+		SDRAM Initialization Register 5
+		(OFFSET, MASK, VALUE)      (0XFD0700E4, 0x00FF03FFU ,0x00210004U)  
+		RegMask = (DDRC_INIT5_DEV_ZQINIT_X32_MASK | DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK |  0 );
+
+		RegVal = ((0x00000021U << DDRC_INIT5_DEV_ZQINIT_X32_SHIFT
+			| 0x00000004U << DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT5_OFFSET ,0x00FF03FFU ,0x00210004U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT6 @ 0XFD0700E8

+
+		DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
+		PSU_DDRC_INIT6_MR4                                                              0x0
+
+		DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
+		PSU_DDRC_INIT6_MR5                                                              0x6c0
+
+		SDRAM Initialization Register 6
+		(OFFSET, MASK, VALUE)      (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U)  
+		RegMask = (DDRC_INIT6_MR4_MASK | DDRC_INIT6_MR5_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_INIT6_MR4_SHIFT
+			| 0x000006C0U << DDRC_INIT6_MR5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT6_OFFSET ,0xFFFFFFFFU ,0x000006C0U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT7 @ 0XFD0700EC

+
+		DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
+		PSU_DDRC_INIT7_MR6                                                              0x819
+
+		SDRAM Initialization Register 7
+		(OFFSET, MASK, VALUE)      (0XFD0700EC, 0xFFFF0000U ,0x08190000U)  
+		RegMask = (DDRC_INIT7_MR6_MASK |  0 );
+
+		RegVal = ((0x00000819U << DDRC_INIT7_MR6_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT7_OFFSET ,0xFFFF0000U ,0x08190000U);
+	/*############################################################################################################################ */
+
+		/*Register : DIMMCTL @ 0XFD0700F0

+
+		Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
+		ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
+		 address mirroring is enabled.
+		PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING                                          0x0
+
+		Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
+		 be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output 
+		nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
+		effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
+		led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled
+		PSU_DDRC_DIMMCTL_MRS_BG1_EN                                                     0x1
+
+		Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
+		 be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, 
+		his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address 
+		f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled
+		PSU_DDRC_DIMMCTL_MRS_A17_EN                                                     0x0
+
+		Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
+		which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, 
+		A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
+		lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. 
+		or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
+		 has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
+		ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.
+		PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN                                             0x0
+
+		Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
+		4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits 
+		re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
+		at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
+		sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
+		 swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
+		ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
+		or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
+		hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
+		ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
+		not implement address mirroring
+		PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN                                              0x0
+
+		Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
+		R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
+		CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
+		 each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses
+		PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN                                             0x0
+
+		DIMM Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0700F0, 0x0000003FU ,0x00000010U)  
+		RegMask = (DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK | DDRC_DIMMCTL_MRS_BG1_EN_MASK | DDRC_DIMMCTL_MRS_A17_EN_MASK | DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK | DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK | DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT
+			| 0x00000001U << DDRC_DIMMCTL_MRS_BG1_EN_SHIFT
+			| 0x00000000U << DDRC_DIMMCTL_MRS_A17_EN_SHIFT
+			| 0x00000000U << DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT
+			| 0x00000000U << DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT
+			| 0x00000000U << DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DIMMCTL_OFFSET ,0x0000003FU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : RANKCTL @ 0XFD0700F4

+
+		Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
+		e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
+		nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
+		ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
+		ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed 
+		n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
+		ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
+		or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
+		 to the next integer.
+		PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP                                               0x6
+
+		Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
+		e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
+		sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
+		p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
+		), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
+		requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
+		quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and 
+		ound it up to the next integer.
+		PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP                                               0x6
+
+		Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
+		nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
+		on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
+		-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
+		_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
+		om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
+		ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to 
+		llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
+		ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as 
+		ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
+		. FOR PERFORMANCE ONLY.
+		PSU_DDRC_RANKCTL_MAX_RANK_RD                                                    0xf
+
+		Rank Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0700F4, 0x00000FFFU ,0x0000066FU)  
+		RegMask = (DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK | DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK | DDRC_RANKCTL_MAX_RANK_RD_MASK |  0 );
+
+		RegVal = ((0x00000006U << DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT
+			| 0x00000006U << DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT
+			| 0x0000000FU << DDRC_RANKCTL_MAX_RANK_RD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_RANKCTL_OFFSET ,0x00000FFFU ,0x0000066FU);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG0 @ 0XFD070100

+
+		Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles 
+		 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
+		 value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
+		Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this 
+		arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
+		with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
+		PSU_DDRC_DRAMTMG0_WR2PRE                                                        0x11
+
+		tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
+		in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next 
+		nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks
+		PSU_DDRC_DRAMTMG0_T_FAW                                                         0xc
+
+		tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
+		imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
+		 No rounding up. Unit: Multiples of 1024 clocks.
+		PSU_DDRC_DRAMTMG0_T_RAS_MAX                                                     0x24
+
+		tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, 
+		rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
+		 (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
+		PSU_DDRC_DRAMTMG0_T_RAS_MIN                                                     0x12
+
+		SDRAM Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070100, 0x7F3F7F3FU ,0x110C2412U)  
+		RegMask = (DDRC_DRAMTMG0_WR2PRE_MASK | DDRC_DRAMTMG0_T_FAW_MASK | DDRC_DRAMTMG0_T_RAS_MAX_MASK | DDRC_DRAMTMG0_T_RAS_MIN_MASK |  0 );
+
+		RegVal = ((0x00000011U << DDRC_DRAMTMG0_WR2PRE_SHIFT
+			| 0x0000000CU << DDRC_DRAMTMG0_T_FAW_SHIFT
+			| 0x00000024U << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT
+			| 0x00000012U << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG0_OFFSET ,0x7F3F7F3FU ,0x110C2412U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG1 @ 0XFD070104

+
+		tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
+		 is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, 
+		rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks
+		PSU_DDRC_DRAMTMG1_T_XP                                                          0x4
+
+		tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
+		R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
+		S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
+		2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
+		gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
+		e. Unit: Clocks.
+		PSU_DDRC_DRAMTMG1_RD2PRE                                                        0x4
+
+		tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
+		 up to next integer value. Unit: Clocks.
+		PSU_DDRC_DRAMTMG1_T_RC                                                          0x19
+
+		SDRAM Timing Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070104, 0x001F1F7FU ,0x00040419U)  
+		RegMask = (DDRC_DRAMTMG1_T_XP_MASK | DDRC_DRAMTMG1_RD2PRE_MASK | DDRC_DRAMTMG1_T_RC_MASK |  0 );
+
+		RegVal = ((0x00000004U << DDRC_DRAMTMG1_T_XP_SHIFT
+			| 0x00000004U << DDRC_DRAMTMG1_RD2PRE_SHIFT
+			| 0x00000019U << DDRC_DRAMTMG1_T_RC_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG1_OFFSET ,0x001F1F7FU ,0x00040419U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG2 @ 0XFD070108

+
+		Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
+		t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
+		tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
+		equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
+		 is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
+		PSU_DDRC_DRAMTMG2_WRITE_LATENCY                                                 0x7
+
+		Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
+		using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For 
+		onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
+		er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
+		s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
+		PSU_DDRC_DRAMTMG2_READ_LATENCY                                                  0x8
+
+		DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL 
+		PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
+		/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
+		time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = 
+		urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
+		tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
+		DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
+		gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
+		PSU_DDRC_DRAMTMG2_RD2WR                                                         0x6
+
+		DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
+		k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
+		 per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
+		 length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
+		d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
+		 delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
+		ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
+		PSU_DDRC_DRAMTMG2_WR2RD                                                         0xe
+
+		SDRAM Timing Register 2
+		(OFFSET, MASK, VALUE)      (0XFD070108, 0x3F3F3F3FU ,0x0708060EU)  
+		RegMask = (DDRC_DRAMTMG2_WRITE_LATENCY_MASK | DDRC_DRAMTMG2_READ_LATENCY_MASK | DDRC_DRAMTMG2_RD2WR_MASK | DDRC_DRAMTMG2_WR2RD_MASK |  0 );
+
+		RegVal = ((0x00000007U << DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT
+			| 0x00000008U << DDRC_DRAMTMG2_READ_LATENCY_SHIFT
+			| 0x00000006U << DDRC_DRAMTMG2_RD2WR_SHIFT
+			| 0x0000000EU << DDRC_DRAMTMG2_WR2RD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG2_OFFSET ,0x3F3F3F3FU ,0x0708060EU);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG3 @ 0XFD07010C

+
+		Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
+		 LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW 
+		nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
+		 used for the time from a MRW/MRR to a MRW/MRR.
+		PSU_DDRC_DRAMTMG3_T_MRW                                                         0x5
+
+		tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time 
+		rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
+		nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
+		4 is used, set to tMRD_PAR(tMOD+PL) instead.
+		PSU_DDRC_DRAMTMG3_T_MRD                                                         0x4
+
+		tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
+		y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
+		 if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
+		 + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.
+		PSU_DDRC_DRAMTMG3_T_MOD                                                         0xc
+
+		SDRAM Timing Register 3
+		(OFFSET, MASK, VALUE)      (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU)  
+		RegMask = (DDRC_DRAMTMG3_T_MRW_MASK | DDRC_DRAMTMG3_T_MRD_MASK | DDRC_DRAMTMG3_T_MOD_MASK |  0 );
+
+		RegVal = ((0x00000005U << DDRC_DRAMTMG3_T_MRW_SHIFT
+			| 0x00000004U << DDRC_DRAMTMG3_T_MRD_SHIFT
+			| 0x0000000CU << DDRC_DRAMTMG3_T_MOD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG3_OFFSET ,0x3FF3F3FFU ,0x0050400CU);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG4 @ 0XFD070110

+
+		tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
+		am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
+		lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
+		PSU_DDRC_DRAMTMG4_T_RCD                                                         0x8
+
+		DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
+		time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
+		d it up to the next integer value. Unit: clocks.
+		PSU_DDRC_DRAMTMG4_T_CCD                                                         0x3
+
+		DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
+		 activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
+		it up to the next integer value. Unit: Clocks.
+		PSU_DDRC_DRAMTMG4_T_RRD                                                         0x3
+
+		tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
+		(tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
+		2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
+		PSU_DDRC_DRAMTMG4_T_RP                                                          0x9
+
+		SDRAM Timing Register 4
+		(OFFSET, MASK, VALUE)      (0XFD070110, 0x1F0F0F1FU ,0x08030309U)  
+		RegMask = (DDRC_DRAMTMG4_T_RCD_MASK | DDRC_DRAMTMG4_T_CCD_MASK | DDRC_DRAMTMG4_T_RRD_MASK | DDRC_DRAMTMG4_T_RP_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_DRAMTMG4_T_RCD_SHIFT
+			| 0x00000003U << DDRC_DRAMTMG4_T_CCD_SHIFT
+			| 0x00000003U << DDRC_DRAMTMG4_T_RRD_SHIFT
+			| 0x00000009U << DDRC_DRAMTMG4_T_RP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG4_OFFSET ,0x1F0F0F1FU ,0x08030309U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG5 @ 0XFD070114

+
+		This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
+		e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
+		tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
+		eger.
+		PSU_DDRC_DRAMTMG5_T_CKSRX                                                       0x6
+
+		This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
+		 SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: 
+		ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
+		to next integer.
+		PSU_DDRC_DRAMTMG5_T_CKSRE                                                       0x6
+
+		Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
+		tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE 
+		 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
+		.
+		PSU_DDRC_DRAMTMG5_T_CKESR                                                       0x4
+
+		Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of 
+		CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set 
+		his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
+		 next integer value. Unit: Clocks.
+		PSU_DDRC_DRAMTMG5_T_CKE                                                         0x3
+
+		SDRAM Timing Register 5
+		(OFFSET, MASK, VALUE)      (0XFD070114, 0x0F0F3F1FU ,0x06060403U)  
+		RegMask = (DDRC_DRAMTMG5_T_CKSRX_MASK | DDRC_DRAMTMG5_T_CKSRE_MASK | DDRC_DRAMTMG5_T_CKESR_MASK | DDRC_DRAMTMG5_T_CKE_MASK |  0 );
+
+		RegVal = ((0x00000006U << DDRC_DRAMTMG5_T_CKSRX_SHIFT
+			| 0x00000006U << DDRC_DRAMTMG5_T_CKSRE_SHIFT
+			| 0x00000004U << DDRC_DRAMTMG5_T_CKESR_SHIFT
+			| 0x00000003U << DDRC_DRAMTMG5_T_CKE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG5_OFFSET ,0x0F0F3F1FU ,0x06060403U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG6 @ 0XFD070118

+
+		This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after 
+		PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
+		ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
+		devices.
+		PSU_DDRC_DRAMTMG6_T_CKDPDE                                                      0x1
+
+		This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock 
+		table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
+		gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
+		R or LPDDR2 devices.
+		PSU_DDRC_DRAMTMG6_T_CKDPDX                                                      0x1
+
+		This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the 
+		lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
+		2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it 
+		p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_DRAMTMG6_T_CKCSX                                                       0x4
+
+		SDRAM Timing Register 6
+		(OFFSET, MASK, VALUE)      (0XFD070118, 0x0F0F000FU ,0x01010004U)  
+		RegMask = (DDRC_DRAMTMG6_T_CKDPDE_MASK | DDRC_DRAMTMG6_T_CKDPDX_MASK | DDRC_DRAMTMG6_T_CKCSX_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_DRAMTMG6_T_CKDPDE_SHIFT
+			| 0x00000001U << DDRC_DRAMTMG6_T_CKDPDX_SHIFT
+			| 0x00000004U << DDRC_DRAMTMG6_T_CKCSX_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG6_OFFSET ,0x0F0F000FU ,0x01010004U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG7 @ 0XFD07011C

+
+		This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. 
+		ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
+		is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
+		DDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_DRAMTMG7_T_CKPDE                                                       0x1
+
+		This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
+		time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
+		, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
+		g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_DRAMTMG7_T_CKPDX                                                       0x1
+
+		SDRAM Timing Register 7
+		(OFFSET, MASK, VALUE)      (0XFD07011C, 0x00000F0FU ,0x00000101U)  
+		RegMask = (DDRC_DRAMTMG7_T_CKPDE_MASK | DDRC_DRAMTMG7_T_CKPDX_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_DRAMTMG7_T_CKPDE_SHIFT
+			| 0x00000001U << DDRC_DRAMTMG7_T_CKPDX_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000101U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG8 @ 0XFD070120

+
+		tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
+		O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
+		 is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.
+		PSU_DDRC_DRAMTMG8_T_XS_FAST_X32                                                 0x4
+
+		tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
+		ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: 
+		nsure this is less than or equal to t_xs_x32.
+		PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32                                                0x4
+
+		tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the 
+		bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and 
+		DR4 SDRAMs.
+		PSU_DDRC_DRAMTMG8_T_XS_DLL_X32                                                  0xd
+
+		tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
+		above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
+		DDR4 SDRAMs.
+		PSU_DDRC_DRAMTMG8_T_XS_X32                                                      0x6
+
+		SDRAM Timing Register 8
+		(OFFSET, MASK, VALUE)      (0XFD070120, 0x7F7F7F7FU ,0x04040D06U)  
+		RegMask = (DDRC_DRAMTMG8_T_XS_FAST_X32_MASK | DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK | DDRC_DRAMTMG8_T_XS_DLL_X32_MASK | DDRC_DRAMTMG8_T_XS_X32_MASK |  0 );
+
+		RegVal = ((0x00000004U << DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT
+			| 0x00000004U << DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT
+			| 0x0000000DU << DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT
+			| 0x00000006U << DDRC_DRAMTMG8_T_XS_X32_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG8_OFFSET ,0x7F7F7F7FU ,0x04040D06U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG9 @ 0XFD070124

+
+		DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
+		PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE                                              0x0
+
+		tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' 
+		o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
+		nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.
+		PSU_DDRC_DRAMTMG9_T_CCD_S                                                       0x2
+
+		tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
+		ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
+		R4. Unit: Clocks.
+		PSU_DDRC_DRAMTMG9_T_RRD_S                                                       0x2
+
+		CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
+		round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
+		 Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
+		d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
+		is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using 
+		he above equation by 2, and round it up to next integer.
+		PSU_DDRC_DRAMTMG9_WR2RD_S                                                       0xb
+
+		SDRAM Timing Register 9
+		(OFFSET, MASK, VALUE)      (0XFD070124, 0x40070F3FU ,0x0002020BU)  
+		RegMask = (DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK | DDRC_DRAMTMG9_T_CCD_S_MASK | DDRC_DRAMTMG9_T_RRD_S_MASK | DDRC_DRAMTMG9_WR2RD_S_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT
+			| 0x00000002U << DDRC_DRAMTMG9_T_CCD_S_SHIFT
+			| 0x00000002U << DDRC_DRAMTMG9_T_RRD_S_SHIFT
+			| 0x0000000BU << DDRC_DRAMTMG9_WR2RD_S_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG9_OFFSET ,0x40070F3FU ,0x0002020BU);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG11 @ 0XFD07012C

+
+		tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
+		this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
+		ples of 32 clocks.
+		PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32                                            0x6f
+
+		tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
+		 RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.
+		PSU_DDRC_DRAMTMG11_T_MPX_LH                                                     0x7
+
+		tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
+		up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.
+		PSU_DDRC_DRAMTMG11_T_MPX_S                                                      0x1
+
+		tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
+		r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
+		teger.
+		PSU_DDRC_DRAMTMG11_T_CKMPE                                                      0xe
+
+		SDRAM Timing Register 11
+		(OFFSET, MASK, VALUE)      (0XFD07012C, 0x7F1F031FU ,0x6F07010EU)  
+		RegMask = (DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK | DDRC_DRAMTMG11_T_MPX_LH_MASK | DDRC_DRAMTMG11_T_MPX_S_MASK | DDRC_DRAMTMG11_T_CKMPE_MASK |  0 );
+
+		RegVal = ((0x0000006FU << DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT
+			| 0x00000007U << DDRC_DRAMTMG11_T_MPX_LH_SHIFT
+			| 0x00000001U << DDRC_DRAMTMG11_T_MPX_S_SHIFT
+			| 0x0000000EU << DDRC_DRAMTMG11_T_CKMPE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG11_OFFSET ,0x7F1F031FU ,0x6F07010EU);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG12 @ 0XFD070130

+
+		tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
+		REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.
+		PSU_DDRC_DRAMTMG12_T_CMDCKE                                                     0x2
+
+		tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
+		/2) and round it up to next integer value.
+		PSU_DDRC_DRAMTMG12_T_CKEHCMD                                                    0x6
+
+		tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
+		s to (tMRD_PDA/2) and round it up to next integer value.
+		PSU_DDRC_DRAMTMG12_T_MRD_PDA                                                    0x8
+
+		SDRAM Timing Register 12
+		(OFFSET, MASK, VALUE)      (0XFD070130, 0x00030F1FU ,0x00020608U)  
+		RegMask = (DDRC_DRAMTMG12_T_CMDCKE_MASK | DDRC_DRAMTMG12_T_CKEHCMD_MASK | DDRC_DRAMTMG12_T_MRD_PDA_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_DRAMTMG12_T_CMDCKE_SHIFT
+			| 0x00000006U << DDRC_DRAMTMG12_T_CKEHCMD_SHIFT
+			| 0x00000008U << DDRC_DRAMTMG12_T_MRD_PDA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG12_OFFSET ,0x00030F1FU ,0x00020608U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQCTL0 @ 0XFD070180

+
+		- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
+		ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
+		ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ                                                     0x1
+
+		- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
+		or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
+		own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
+		ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL                                                    0x0
+
+		- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
+		nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
+		rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED                                              0x0
+
+		- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable 
+		ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
+		gns supporting DDR4 devices.
+		PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL                                                  0x0
+
+		tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
+		on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
+		er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
+		ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for 
+		esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP                                                   0x100
+
+		tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
+		ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
+		e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
+		s.
+		PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP                                                  0x40
+
+		ZQ Control Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070180, 0xF7FF03FFU ,0x81000040U)  
+		RegMask = (DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK | DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK | DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK | DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK | DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK | DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT
+			| 0x00000000U << DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT
+			| 0x00000000U << DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT
+			| 0x00000000U << DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT
+			| 0x00000100U << DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT
+			| 0x00000040U << DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ZQCTL0_OFFSET ,0xF7FF03FFU ,0x81000040U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQCTL1 @ 0XFD070184

+
+		tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
+		ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is 
+		nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP                                                  0x20
+
+		Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
+		PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs 
+		upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024                                       0x19707
+
+		ZQ Control Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070184, 0x3FFFFFFFU ,0x02019707U)  
+		RegMask = (DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK | DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK |  0 );
+
+		RegVal = ((0x00000020U << DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT
+			| 0x00019707U << DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ZQCTL1_OFFSET ,0x3FFFFFFFU ,0x02019707U);
+	/*############################################################################################################################ */
+
+		/*Register : DFITMG0 @ 0XFD070190

+
+		Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
+		s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
+		, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
+		 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
+		PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY                                               0x4
+
+		Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
+		0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
+		fer to PHY specification for correct value.
+		PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR                                             0x1
+
+		Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
+		ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
+		, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
+		 latency through the RDIMM. Unit: Clocks
+		PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN                                                0xb
+
+		Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
+		.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
+		HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
+		e.
+		PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR                                             0x1
+
+		Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
+		 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
+		te, max supported value is 8. Unit: Clocks
+		PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA                                                0x2
+
+		Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
+		 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
+		 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
+		rough the RDIMM.
+		PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT                                                 0xb
+
+		DFI Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070190, 0x1FBFBF3FU ,0x048B820BU)  
+		RegMask = (DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK |  0 );
+
+		RegVal = ((0x00000004U << DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT
+			| 0x00000001U << DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT
+			| 0x0000000BU << DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT
+			| 0x00000001U << DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT
+			| 0x00000002U << DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT
+			| 0x0000000BU << DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFITMG0_OFFSET ,0x1FBFBF3FU ,0x048B820BU);
+	/*############################################################################################################################ */
+
+		/*Register : DFITMG1 @ 0XFD070194

+
+		Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. 
+		his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
+		the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
+		PSU_DDRC_DFITMG1_DFI_T_CMD_LAT                                                  0x0
+
+		Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
+		 is driven.
+		PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT                                                0x0
+
+		Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
+		nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
+		 correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to 
+		phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
+		RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
+		: Clocks
+		PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY                                             0x3
+
+		Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to 
+		he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase 
+		ligned, this timing parameter should be rounded up to the next integer value.
+		PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE                                         0x3
+
+		Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first 
+		alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
+		not phase aligned, this timing parameter should be rounded up to the next integer value.
+		PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE                                          0x4
+
+		DFI Timing Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070194, 0xF31F0F0FU ,0x00030304U)  
+		RegMask = (DDRC_DFITMG1_DFI_T_CMD_LAT_MASK | DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK | DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT
+			| 0x00000000U << DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT
+			| 0x00000003U << DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT
+			| 0x00000003U << DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT
+			| 0x00000004U << DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFITMG1_OFFSET ,0xF31F0F0FU ,0x00030304U);
+	/*############################################################################################################################ */
+
+		/*Register : DFILPCFG0 @ 0XFD070198

+
+		Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
+		g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.
+		PSU_DDRC_DFILPCFG0_DFI_TLP_RESP                                                 0x7
+
+		Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
+		cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
+		- 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 
+		31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
+		.
+		PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD                                            0x0
+
+		Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
+		nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.
+		PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD                                                0x0
+
+		Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
+		les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 
+		048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
+		72 cycles - 0xE - 262144 cycles - 0xF - Unlimited
+		PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR                                             0x0
+
+		Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
+		PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR                                                 0x1
+
+		Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
+		s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
+		8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
+		 cycles - 0xE - 262144 cycles - 0xF - Unlimited
+		PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD                                             0x4
+
+		Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
+		PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD                                                 0x1
+
+		DFI Low Power Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070198, 0x0FF1F1F1U ,0x07000141U)  
+		RegMask = (DDRC_DFILPCFG0_DFI_TLP_RESP_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK | DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK |  0 );
+
+		RegVal = ((0x00000007U << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
+			| 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT
+			| 0x00000000U << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
+			| 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
+			| 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
+			| 0x00000004U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
+			| 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000141U);
+	/*############################################################################################################################ */
+
+		/*Register : DFILPCFG1 @ 0XFD07019C

+
+		Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
+		- 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles 
+		 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
+		D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.
+		PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM                                           0x2
+
+		Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
+		only present for designs supporting DDR4 devices.
+		PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM                                               0x1
+
+		DFI Low Power Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD07019C, 0x000000F1U ,0x00000021U)  
+		RegMask = (DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK | DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT
+			| 0x00000001U << DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFILPCFG1_OFFSET ,0x000000F1U ,0x00000021U);
+	/*############################################################################################################################ */
+
+		/*Register : DFIUPD1 @ 0XFD0701A4

+
+		This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
+		). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
+		t read request when the uMCTL2 is idle. Unit: 1024 clocks
+		PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024                               0x41
+
+		This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; 
+		hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
+		idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
+		e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
+		Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
+		024. Unit: 1024 clocks
+		PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024                               0xe2
+
+		DFI Update Register 1
+		(OFFSET, MASK, VALUE)      (0XFD0701A4, 0x00FF00FFU ,0x004100E2U)  
+		RegMask = (DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK | DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK |  0 );
+
+		RegVal = ((0x00000041U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT
+			| 0x000000E2U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFIUPD1_OFFSET ,0x00FF00FFU ,0x004100E2U);
+	/*############################################################################################################################ */
+
+		/*Register : DFIMISC @ 0XFD0701B0

+
+		Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high
+		PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY                                           0x0
+
+		DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
+		in designs configured to support DDR4 and LPDDR4.
+		PSU_DDRC_DFIMISC_PHY_DBI_MODE                                                   0x0
+
+		PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
+		ion
+		PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN                                           0x0
+
+		DFI Miscellaneous Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0701B0, 0x00000007U ,0x00000000U)  
+		RegMask = (DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK | DDRC_DFIMISC_PHY_DBI_MODE_MASK | DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT
+			| 0x00000000U << DDRC_DFIMISC_PHY_DBI_MODE_SHIFT
+			| 0x00000000U << DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFIMISC_OFFSET ,0x00000007U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DFITMG2 @ 0XFD0701B4

+
+		>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
+		l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
+		PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT                                               0x9
+
+		Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
+		l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
+		PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT                                               0x6
+
+		DFI Timing Register 2
+		(OFFSET, MASK, VALUE)      (0XFD0701B4, 0x00003F3FU ,0x00000906U)  
+		RegMask = (DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK | DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK |  0 );
+
+		RegVal = ((0x00000009U << DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT
+			| 0x00000006U << DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFITMG2_OFFSET ,0x00003F3FU ,0x00000906U);
+	/*############################################################################################################################ */
+
+		/*Register : DBICTL @ 0XFD0701C0

+
+		Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
+		as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
+		PSU_DDRC_DBICTL_RD_DBI_EN                                                       0x0
+
+		Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
+		ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
+		PSU_DDRC_DBICTL_WR_DBI_EN                                                       0x0
+
+		DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
+		mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
+		: Set this to inverted value of MR13[5] which is opposite polarity from this signal
+		PSU_DDRC_DBICTL_DM_EN                                                           0x1
+
+		DM/DBI Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0701C0, 0x00000007U ,0x00000001U)  
+		RegMask = (DDRC_DBICTL_RD_DBI_EN_MASK | DDRC_DBICTL_WR_DBI_EN_MASK | DDRC_DBICTL_DM_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DBICTL_RD_DBI_EN_SHIFT
+			| 0x00000000U << DDRC_DBICTL_WR_DBI_EN_SHIFT
+			| 0x00000001U << DDRC_DBICTL_DM_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DBICTL_OFFSET ,0x00000007U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP0 @ 0XFD070200

+
+		Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
+		 bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+		PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0                                               0x1f
+
+		Address Map Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070200, 0x0000001FU ,0x0000001FU)  
+		RegMask = (DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK |  0 );
+
+		RegVal = ((0x0000001FU << DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP0_OFFSET ,0x0000001FU ,0x0000001FU);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP1 @ 0XFD070204

+
+		Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
+		bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.
+		PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2                                               0x1f
+
+		Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
+		r each of the bank address bits is determined by adding the internal base to the value of this field.
+		PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1                                               0xa
+
+		Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
+		r each of the bank address bits is determined by adding the internal base to the value of this field.
+		PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0                                               0xa
+
+		Address Map Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070204, 0x001F1F1FU ,0x001F0A0AU)  
+		RegMask = (DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK |  0 );
+
+		RegVal = ((0x0000001FU << DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT
+			| 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT
+			| 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP1_OFFSET ,0x001F1F1FU ,0x001F0A0AU);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP2 @ 0XFD070208

+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
+		 Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
+		 this field. If set to 15, this column address bit is set to 0.
+		PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
+		Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.
+		PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
+		Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
+		ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
+		 this case.
+		PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
+		Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
+		ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.
+		PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2                                                0x0
+
+		Address Map Register 2
+		(OFFSET, MASK, VALUE)      (0XFD070208, 0x0F0F0F0FU ,0x00000000U)  
+		RegMask = (DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP2_OFFSET ,0x0F0F0F0FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP3 @ 0XFD07020C

+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
+		column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
+		 determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: 
+		er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
+		ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
+		 hence column bit 10 is used.
+		PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
+		 LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
+		ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
+		cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
+		mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
+		.
+		PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
+		Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.
+		PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
+		Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.
+		PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6                                                0x0
+
+		Address Map Register 3
+		(OFFSET, MASK, VALUE)      (0XFD07020C, 0x0F0F0F0FU ,0x00000000U)  
+		RegMask = (DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP3_OFFSET ,0x0F0F0F0FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP4 @ 0XFD070210

+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
+		mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must 
+		e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
+		l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
+		n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
+		dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
+		PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11                                               0xf
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
+		mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
+		To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
+		termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
+		JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
+		bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
+		nce column bit 10 is used.
+		PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10                                               0xf
+
+		Address Map Register 4
+		(OFFSET, MASK, VALUE)      (0XFD070210, 0x00000F0FU ,0x00000F0FU)  
+		RegMask = (DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK | DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK |  0 );
+
+		RegVal = ((0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT
+			| 0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP4_OFFSET ,0x00000F0FU ,0x00000F0FU);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP5 @ 0XFD070214

+
+		Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.
+		PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11                                               0x8
+
+		Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
+		bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF 
+		ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value 
+		5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
+		PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10                                             0xf
+
+		Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field.
+		PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1                                                0x8
+
+		Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field.
+		PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0                                                0x8
+
+		Address Map Register 5
+		(OFFSET, MASK, VALUE)      (0XFD070214, 0x0F0F0F0FU ,0x080F0808U)  
+		RegMask = (DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT
+			| 0x0000000FU << DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP5_OFFSET ,0x0F0F0F0FU ,0x080F0808U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP6 @ 0XFD070218

+
+		Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
+		having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
+		y in designs configured to support LPDDR3.
+		PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB                                               0x0
+
+		Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.
+		PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15                                               0xf
+
+		Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.
+		PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14                                               0x8
+
+		Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.
+		PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13                                               0x8
+
+		Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.
+		PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12                                               0x8
+
+		Address Map Register 6
+		(OFFSET, MASK, VALUE)      (0XFD070218, 0x8F0F0F0FU ,0x0F080808U)  
+		RegMask = (DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT
+			| 0x0000000FU << DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP6_OFFSET ,0x8F0F0F0FU ,0x0F080808U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP7 @ 0XFD07021C

+
+		Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.
+		PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17                                               0xf
+
+		Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.
+		PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16                                               0xf
+
+		Address Map Register 7
+		(OFFSET, MASK, VALUE)      (0XFD07021C, 0x00000F0FU ,0x00000F0FU)  
+		RegMask = (DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK | DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK |  0 );
+
+		RegVal = ((0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT
+			| 0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP7_OFFSET ,0x00000F0FU ,0x00000F0FU);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP8 @ 0XFD070220

+
+		Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
+		address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If 
+		et to 31, bank group address bit 1 is set to 0.
+		PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1                                                 0x8
+
+		Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
+		bit for each of the bank group address bits is determined by adding the internal base to the value of this field.
+		PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0                                                 0x8
+
+		Address Map Register 8
+		(OFFSET, MASK, VALUE)      (0XFD070220, 0x00001F1FU ,0x00000808U)  
+		RegMask = (DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK | DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP8_OFFSET ,0x00001F1FU ,0x00000808U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP9 @ 0XFD070224

+
+		Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5                                                0x8
+
+		Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4                                                0x8
+
+		Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
+		d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3                                                0x8
+
+		Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
+		d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2                                                0x8
+
+		Address Map Register 9
+		(OFFSET, MASK, VALUE)      (0XFD070224, 0x0F0F0F0FU ,0x08080808U)  
+		RegMask = (DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP9_OFFSET ,0x0F0F0F0FU ,0x08080808U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP10 @ 0XFD070228

+
+		Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9                                               0x8
+
+		Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8                                               0x8
+
+		Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7                                               0x8
+
+		Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6                                               0x8
+
+		Address Map Register 10
+		(OFFSET, MASK, VALUE)      (0XFD070228, 0x0F0F0F0FU ,0x08080808U)  
+		RegMask = (DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP10_OFFSET ,0x0F0F0F0FU ,0x08080808U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP11 @ 0XFD07022C

+
+		Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit 
+		or each of the row address bits is determined by adding the internal base to the value of this field. This register field is 
+		sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10                                              0x8
+
+		Address Map Register 11
+		(OFFSET, MASK, VALUE)      (0XFD07022C, 0x0000000FU ,0x00000008U)  
+		RegMask = (DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP11_OFFSET ,0x0000000FU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : ODTCFG @ 0XFD070240

+
+		Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
+		67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - 
+		L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 
+		CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
+		PSU_DDRC_ODTCFG_WR_ODT_HOLD                                                     0x6
+
+		The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
+		remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
+		67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
+		 DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
+		PSU_DDRC_ODTCFG_WR_ODT_DELAY                                                    0x0
+
+		Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
+		 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
+		tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
+		)
+		PSU_DDRC_ODTCFG_RD_ODT_HOLD                                                     0x6
+
+		The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must 
+		emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
+		CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
+		L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
+		write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
+		uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
+		PSU_DDRC_ODTCFG_RD_ODT_DELAY                                                    0x0
+
+		ODT Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD070240, 0x0F1F0F7CU ,0x06000600U)  
+		RegMask = (DDRC_ODTCFG_WR_ODT_HOLD_MASK | DDRC_ODTCFG_WR_ODT_DELAY_MASK | DDRC_ODTCFG_RD_ODT_HOLD_MASK | DDRC_ODTCFG_RD_ODT_DELAY_MASK |  0 );
+
+		RegVal = ((0x00000006U << DDRC_ODTCFG_WR_ODT_HOLD_SHIFT
+			| 0x00000000U << DDRC_ODTCFG_WR_ODT_DELAY_SHIFT
+			| 0x00000006U << DDRC_ODTCFG_RD_ODT_HOLD_SHIFT
+			| 0x00000000U << DDRC_ODTCFG_RD_ODT_DELAY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ODTCFG_OFFSET ,0x0F1F0F7CU ,0x06000600U);
+	/*############################################################################################################################ */
+
+		/*Register : ODTMAP @ 0XFD070244

+
+		Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can 
+		e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
+		 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
+		PSU_DDRC_ODTMAP_RANK1_RD_ODT                                                    0x0
+
+		Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
+		 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
+		etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
+		PSU_DDRC_ODTMAP_RANK1_WR_ODT                                                    0x0
+
+		Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can 
+		e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
+		 etc. For each rank, set its bit to 1 to enable its ODT.
+		PSU_DDRC_ODTMAP_RANK0_RD_ODT                                                    0x0
+
+		Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
+		 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
+		etc. For each rank, set its bit to 1 to enable its ODT.
+		PSU_DDRC_ODTMAP_RANK0_WR_ODT                                                    0x1
+
+		ODT/Rank Map Register
+		(OFFSET, MASK, VALUE)      (0XFD070244, 0x00003333U ,0x00000001U)  
+		RegMask = (DDRC_ODTMAP_RANK1_RD_ODT_MASK | DDRC_ODTMAP_RANK1_WR_ODT_MASK | DDRC_ODTMAP_RANK0_RD_ODT_MASK | DDRC_ODTMAP_RANK0_WR_ODT_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_ODTMAP_RANK1_RD_ODT_SHIFT
+			| 0x00000000U << DDRC_ODTMAP_RANK1_WR_ODT_SHIFT
+			| 0x00000000U << DDRC_ODTMAP_RANK0_RD_ODT_SHIFT
+			| 0x00000001U << DDRC_ODTMAP_RANK0_WR_ODT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ODTMAP_OFFSET ,0x00003333U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : SCHED @ 0XFD070250

+
+		When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
+		non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
+		ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this 
+		egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. 
+		OR PERFORMANCE ONLY
+		PSU_DDRC_SCHED_RDWR_IDLE_GAP                                                    0x1
+
+		UNUSED
+		PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS                                           0x0
+
+		Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
+		 the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
+		to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
+		priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
+		 than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
+		sing out of single bit error correction RMW operation.
+		PSU_DDRC_SCHED_LPR_NUM_ENTRIES                                                  0x20
+
+		If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
+		e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this 
+		egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
+		es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed 
+		s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
+		ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open 
+		age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
+		ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.
+		PSU_DDRC_SCHED_PAGECLOSE                                                        0x0
+
+		If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
+		PSU_DDRC_SCHED_PREFER_WRITE                                                     0x0
+
+		Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
+		ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
+		e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
+		ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.
+		PSU_DDRC_SCHED_FORCE_LOW_PRI_N                                                  0x1
+
+		Scheduler Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070250, 0x7FFF3F07U ,0x01002001U)  
+		RegMask = (DDRC_SCHED_RDWR_IDLE_GAP_MASK | DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK | DDRC_SCHED_LPR_NUM_ENTRIES_MASK | DDRC_SCHED_PAGECLOSE_MASK | DDRC_SCHED_PREFER_WRITE_MASK | DDRC_SCHED_FORCE_LOW_PRI_N_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_SCHED_RDWR_IDLE_GAP_SHIFT
+			| 0x00000000U << DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT
+			| 0x00000020U << DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT
+			| 0x00000000U << DDRC_SCHED_PAGECLOSE_SHIFT
+			| 0x00000000U << DDRC_SCHED_PREFER_WRITE_SHIFT
+			| 0x00000001U << DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SCHED_OFFSET ,0x7FFF3F07U ,0x01002001U);
+	/*############################################################################################################################ */
+
+		/*Register : PERFLPR1 @ 0XFD070264

+
+		Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
+		 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH                                           0x8
+
+		Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
+		er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
+		be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PERFLPR1_LPR_MAX_STARVE                                                0x40
+
+		Low Priority Read CAM Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070264, 0xFF00FFFFU ,0x08000040U)  
+		RegMask = (DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK | DDRC_PERFLPR1_LPR_MAX_STARVE_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT
+			| 0x00000040U << DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PERFLPR1_OFFSET ,0xFF00FFFFU ,0x08000040U);
+	/*############################################################################################################################ */
+
+		/*Register : PERFWR1 @ 0XFD07026C

+
+		Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
+		transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH                                              0x8
+
+		Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
+		r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not 
+		e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PERFWR1_W_MAX_STARVE                                                   0x40
+
+		Write CAM Register 1
+		(OFFSET, MASK, VALUE)      (0XFD07026C, 0xFF00FFFFU ,0x08000040U)  
+		RegMask = (DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK | DDRC_PERFWR1_W_MAX_STARVE_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT
+			| 0x00000040U << DDRC_PERFWR1_W_MAX_STARVE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PERFWR1_OFFSET ,0xFF00FFFFU ,0x08000040U);
+	/*############################################################################################################################ */
+
+		/*Register : DQMAP5 @ 0XFD070294

+
+		All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
+		all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and 
+		wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
+		port DDR4.
+		PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP                                                0x1
+
+		DQ Map Register 5
+		(OFFSET, MASK, VALUE)      (0XFD070294, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DQMAP5_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : DBG0 @ 0XFD070300

+
+		When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
+		lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
+		s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.
+		PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT                                            0x0
+
+		When 1, disable write combine. FOR DEBUG ONLY
+		PSU_DDRC_DBG0_DIS_WC                                                            0x0
+
+		Debug Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070300, 0x00000011U ,0x00000000U)  
+		RegMask = (DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK | DDRC_DBG0_DIS_WC_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT
+			| 0x00000000U << DDRC_DBG0_DIS_WC_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DBG0_OFFSET ,0x00000011U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DBGCMD @ 0XFD07030C

+
+		Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
+		the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
+		register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
+		_refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
+		 and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).
+		PSU_DDRC_DBGCMD_HW_REF_ZQ_EN                                                    0x0
+
+		Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in 
+		he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
+		PSU_DDRC_DBGCMD_CTRLUPD                                                         0x0
+
+		Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to 
+		he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
+		en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
+		d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
+		de.
+		PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT                                                  0x0
+
+		Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
+		refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
+		be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
+		wn operating modes or Maximum Power Saving Mode.
+		PSU_DDRC_DBGCMD_RANK1_REFRESH                                                   0x0
+
+		Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
+		refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
+		be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
+		wn operating modes or Maximum Power Saving Mode.
+		PSU_DDRC_DBGCMD_RANK0_REFRESH                                                   0x0
+
+		Command Debug Register
+		(OFFSET, MASK, VALUE)      (0XFD07030C, 0x80000033U ,0x00000000U)  
+		RegMask = (DDRC_DBGCMD_HW_REF_ZQ_EN_MASK | DDRC_DBGCMD_CTRLUPD_MASK | DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK | DDRC_DBGCMD_RANK1_REFRESH_MASK | DDRC_DBGCMD_RANK0_REFRESH_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT
+			| 0x00000000U << DDRC_DBGCMD_CTRLUPD_SHIFT
+			| 0x00000000U << DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT
+			| 0x00000000U << DDRC_DBGCMD_RANK1_REFRESH_SHIFT
+			| 0x00000000U << DDRC_DBGCMD_RANK0_REFRESH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DBGCMD_OFFSET ,0x80000033U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : SWCTL @ 0XFD070320

+
+		Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back 
+		egister to 1 once programming is done.
+		PSU_DDRC_SWCTL_SW_DONE                                                          0x0
+
+		Software register programming control enable
+		(OFFSET, MASK, VALUE)      (0XFD070320, 0x00000001U ,0x00000000U)  
+		RegMask = (DDRC_SWCTL_SW_DONE_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_SWCTL_SW_DONE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SWCTL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : PCCFG @ 0XFD070400

+
+		Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
+		e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
+		h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
+		ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
+		_mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
+		ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
+		DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
+		only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
+		-AC is enabled
+		PSU_DDRC_PCCFG_BL_EXP_MODE                                                      0x0
+
+		Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
+		rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
+		ge DDRC transactions.
+		PSU_DDRC_PCCFG_PAGEMATCH_LIMIT                                                  0x0
+
+		If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based 
+		n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
+		_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
+		PSU_DDRC_PCCFG_GO2CRITICAL_EN                                                   0x1
+
+		Port Common Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD070400, 0x00000111U ,0x00000001U)  
+		RegMask = (DDRC_PCCFG_BL_EXP_MODE_MASK | DDRC_PCCFG_PAGEMATCH_LIMIT_MASK | DDRC_PCCFG_GO2CRITICAL_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCCFG_BL_EXP_MODE_SHIFT
+			| 0x00000000U << DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT
+			| 0x00000001U << DDRC_PCCFG_GO2CRITICAL_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCCFG_OFFSET ,0x00000111U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_0 @ 0XFD070404

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD070404, 0x000073FFU ,0x0000200FU)  
+		RegMask = (DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_0_OFFSET ,0x000073FFU ,0x0000200FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_0 @ 0XFD070408

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD070408, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_0_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_0 @ 0XFD070490

+
+		Enables port n.
+		PSU_DDRC_PCTRL_0_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070490, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_0_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_0_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_0_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_0 @ 0XFD070494

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1                                            0x2
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0                                            0x0
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1                                             0xb
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070494, 0x0033000FU ,0x0020000BU)  
+		RegMask = (DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT
+			| 0x0000000BU << DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_0_OFFSET ,0x0033000FU ,0x0020000BU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_0 @ 0XFD070498

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB                                           0x0
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070498, 0x07FF07FFU ,0x00000000U)  
+		RegMask = (DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_0_OFFSET ,0x07FF07FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_1 @ 0XFD0704B4

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD0704B4, 0x000073FFU ,0x0000200FU)  
+		RegMask = (DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_1_OFFSET ,0x000073FFU ,0x0000200FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_1 @ 0XFD0704B8

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD0704B8, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_1_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_1 @ 0XFD070540

+
+		Enables port n.
+		PSU_DDRC_PCTRL_1_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070540, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_1_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_1_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_1_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_1 @ 0XFD070544

+
+		This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 
+		ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 
+		s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2                                            0x2
+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1                                            0x0
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0                                            0x0
+
+		Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
+		el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
+		directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 
+		ust be set to distinct values.
+		PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2                                             0xb
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1                                             0x3
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070544, 0x03330F0FU ,0x02000B03U)  
+		RegMask = (DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT
+			| 0x0000000BU << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT
+			| 0x00000003U << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_1_OFFSET ,0x03330F0FU ,0x02000B03U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_1 @ 0XFD070548

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB                                           0x0
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070548, 0x07FF07FFU ,0x00000000U)  
+		RegMask = (DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_1_OFFSET ,0x07FF07FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_2 @ 0XFD070564

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD070564, 0x000073FFU ,0x0000200FU)  
+		RegMask = (DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_2_OFFSET ,0x000073FFU ,0x0000200FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_2 @ 0XFD070568

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD070568, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_2_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_2 @ 0XFD0705F0

+
+		Enables port n.
+		PSU_DDRC_PCTRL_2_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0705F0, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_2_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_2_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_2_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_2 @ 0XFD0705F4

+
+		This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 
+		ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 
+		s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2                                            0x2
+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1                                            0x0
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0                                            0x0
+
+		Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
+		el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
+		directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 
+		ust be set to distinct values.
+		PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2                                             0xb
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1                                             0x3
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0705F4, 0x03330F0FU ,0x02000B03U)  
+		RegMask = (DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT
+			| 0x0000000BU << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT
+			| 0x00000003U << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_2_OFFSET ,0x03330F0FU ,0x02000B03U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_2 @ 0XFD0705F8

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB                                           0x0
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD0705F8, 0x07FF07FFU ,0x00000000U)  
+		RegMask = (DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_2_OFFSET ,0x07FF07FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_3 @ 0XFD070614

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD070614, 0x000073FFU ,0x0000200FU)  
+		RegMask = (DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_3_OFFSET ,0x000073FFU ,0x0000200FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_3 @ 0XFD070618

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD070618, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_3_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_3 @ 0XFD0706A0

+
+		Enables port n.
+		PSU_DDRC_PCTRL_3_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0706A0, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_3_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_3_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_3_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_3 @ 0XFD0706A4

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1                                            0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0                                            0x0
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1                                             0x3
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0706A4, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_3_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_3 @ 0XFD0706A8

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB                                           0x4f
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD0706A8, 0x07FF07FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x0000004FU << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_3_OFFSET ,0x07FF07FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS0_3 @ 0XFD0706AC

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
+		PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1                                           0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
+		PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0                                           0x0
+
+		Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.
+		PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL                                             0x3
+
+		Port n Write QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0706AC, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS0_3_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS1_3 @ 0XFD0706B0

+
+		Specifies the timeout value for write transactions.
+		PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT                                           0x4f
+
+		Port n Write QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD0706B0, 0x000007FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK |  0 );
+
+		RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS1_3_OFFSET ,0x000007FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_4 @ 0XFD0706C4

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD0706C4, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_4_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_4 @ 0XFD0706C8

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD0706C8, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_4_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_4 @ 0XFD070750

+
+		Enables port n.
+		PSU_DDRC_PCTRL_4_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070750, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_4_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_4_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_4_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_4 @ 0XFD070754

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1                                            0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0                                            0x0
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1                                             0x3
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070754, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_4_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_4 @ 0XFD070758

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB                                           0x4f
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070758, 0x07FF07FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x0000004FU << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_4_OFFSET ,0x07FF07FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS0_4 @ 0XFD07075C

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
+		PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1                                           0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
+		PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0                                           0x0
+
+		Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.
+		PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL                                             0x3
+
+		Port n Write QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD07075C, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS0_4_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS1_4 @ 0XFD070760

+
+		Specifies the timeout value for write transactions.
+		PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT                                           0x4f
+
+		Port n Write QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070760, 0x000007FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK |  0 );
+
+		RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS1_4_OFFSET ,0x000007FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_5 @ 0XFD070774

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD070774, 0x000073FFU ,0x0000200FU)  
+		RegMask = (DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_5_OFFSET ,0x000073FFU ,0x0000200FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_5 @ 0XFD070778

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD070778, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_5_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_5 @ 0XFD070800

+
+		Enables port n.
+		PSU_DDRC_PCTRL_5_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070800, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_5_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_5_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_5_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_5 @ 0XFD070804

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1                                            0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0                                            0x0
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1                                             0x3
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070804, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_5_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_5 @ 0XFD070808

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB                                           0x4f
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070808, 0x07FF07FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x0000004FU << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_5_OFFSET ,0x07FF07FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS0_5 @ 0XFD07080C

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
+		PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1                                           0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
+		PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0                                           0x0
+
+		Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.
+		PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL                                             0x3
+
+		Port n Write QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD07080C, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS0_5_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS1_5 @ 0XFD070810

+
+		Specifies the timeout value for write transactions.
+		PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT                                           0x4f
+
+		Port n Write QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070810, 0x000007FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK |  0 );
+
+		RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS1_5_OFFSET ,0x000007FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : SARBASE0 @ 0XFD070F04

+
+		Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
+		 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
+		PSU_DDRC_SARBASE0_BASE_ADDR                                                     0x0
+
+		SAR Base Address Register n
+		(OFFSET, MASK, VALUE)      (0XFD070F04, 0x000001FFU ,0x00000000U)  
+		RegMask = (DDRC_SARBASE0_BASE_ADDR_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_SARBASE0_BASE_ADDR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SARBASE0_OFFSET ,0x000001FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : SARSIZE0 @ 0XFD070F08

+
+		Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
+		e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 
+		or example, if register is programmed to 0, region will have 1 block.
+		PSU_DDRC_SARSIZE0_NBLOCKS                                                       0x0
+
+		SAR Size Register n
+		(OFFSET, MASK, VALUE)      (0XFD070F08, 0x000000FFU ,0x00000000U)  
+		RegMask = (DDRC_SARSIZE0_NBLOCKS_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_SARSIZE0_NBLOCKS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SARSIZE0_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : SARBASE1 @ 0XFD070F0C

+
+		Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
+		 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
+		PSU_DDRC_SARBASE1_BASE_ADDR                                                     0x10
+
+		SAR Base Address Register n
+		(OFFSET, MASK, VALUE)      (0XFD070F0C, 0x000001FFU ,0x00000010U)  
+		RegMask = (DDRC_SARBASE1_BASE_ADDR_MASK |  0 );
+
+		RegVal = ((0x00000010U << DDRC_SARBASE1_BASE_ADDR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SARBASE1_OFFSET ,0x000001FFU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : SARSIZE1 @ 0XFD070F10

+
+		Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
+		e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 
+		or example, if register is programmed to 0, region will have 1 block.
+		PSU_DDRC_SARSIZE1_NBLOCKS                                                       0xf
+
+		SAR Size Register n
+		(OFFSET, MASK, VALUE)      (0XFD070F10, 0x000000FFU ,0x0000000FU)  
+		RegMask = (DDRC_SARSIZE1_NBLOCKS_MASK |  0 );
+
+		RegVal = ((0x0000000FU << DDRC_SARSIZE1_NBLOCKS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SARSIZE1_OFFSET ,0x000000FFU ,0x0000000FU);
+	/*############################################################################################################################ */
+
+		/*Register : DFITMG0_SHADOW @ 0XFD072190

+
+		Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
+		s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
+		, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
+		 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
+		PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY                                        0x7
+
+		Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
+		0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
+		fer to PHY specification for correct value.
+		PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR                                      0x1
+
+		Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
+		ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
+		, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
+		 latency through the RDIMM. Unit: Clocks
+		PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN                                         0x2
+
+		Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
+		.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
+		HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
+		e.
+		PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR                                      0x1
+
+		Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
+		 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
+		te, max supported value is 8. Unit: Clocks
+		PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA                                         0x0
+
+		Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
+		 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
+		 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
+		rough the RDIMM.
+		PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT                                          0x2
+
+		DFI Timing Shadow Register 0
+		(OFFSET, MASK, VALUE)      (0XFD072190, 0x1FBFBF3FU ,0x07828002U)  
+		RegMask = (DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK |  0 );
+
+		RegVal = ((0x00000007U << DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT
+			| 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT
+			| 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT
+			| 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT
+			| 0x00000000U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT
+			| 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFITMG0_SHADOW_OFFSET ,0x1FBFBF3FU ,0x07828002U);
+	/*############################################################################################################################ */
+
+		// : DDR CONTROLLER RESET
+		/*Register : RST_DDR_SS @ 0XFD1A0108

+
+		DDR block level reset inside of the DDR Sub System
+		PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X0
+
+		DDR sub system block level reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000000U)  
+		RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : DDR PHY
+		/*Register : PGCR0 @ 0XFD080010

+
+		Address Copy
+		PSU_DDR_PHY_PGCR0_ADCP                                                          0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_PGCR0_RESERVED_30_27                                                0x0
+
+		PHY FIFO Reset
+		PSU_DDR_PHY_PGCR0_PHYFRST                                                       0x1
+
+		Oscillator Mode Address/Command Delay Line Select
+		PSU_DDR_PHY_PGCR0_OSCACDL                                                       0x3
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_PGCR0_RESERVED_23_19                                                0x0
+
+		Digital Test Output Select
+		PSU_DDR_PHY_PGCR0_DTOSEL                                                        0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_PGCR0_RESERVED_13                                                   0x0
+
+		Oscillator Mode Division
+		PSU_DDR_PHY_PGCR0_OSCDIV                                                        0xf
+
+		Oscillator Enable
+		PSU_DDR_PHY_PGCR0_OSCEN                                                         0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_PGCR0_RESERVED_7_0                                                  0x0
+
+		PHY General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080010, 0xFFFFFFFFU ,0x07001E00U)  
+		RegMask = (DDR_PHY_PGCR0_ADCP_MASK | DDR_PHY_PGCR0_RESERVED_30_27_MASK | DDR_PHY_PGCR0_PHYFRST_MASK | DDR_PHY_PGCR0_OSCACDL_MASK | DDR_PHY_PGCR0_RESERVED_23_19_MASK | DDR_PHY_PGCR0_DTOSEL_MASK | DDR_PHY_PGCR0_RESERVED_13_MASK | DDR_PHY_PGCR0_OSCDIV_MASK | DDR_PHY_PGCR0_OSCEN_MASK | DDR_PHY_PGCR0_RESERVED_7_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_PGCR0_ADCP_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_RESERVED_30_27_SHIFT
+			| 0x00000001U << DDR_PHY_PGCR0_PHYFRST_SHIFT
+			| 0x00000003U << DDR_PHY_PGCR0_OSCACDL_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_RESERVED_23_19_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_DTOSEL_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_RESERVED_13_SHIFT
+			| 0x0000000FU << DDR_PHY_PGCR0_OSCDIV_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_OSCEN_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_RESERVED_7_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PGCR0_OFFSET ,0xFFFFFFFFU ,0x07001E00U);
+	/*############################################################################################################################ */
+
+		/*Register : PGCR2 @ 0XFD080018

+
+		Clear Training Status Registers
+		PSU_DDR_PHY_PGCR2_CLRTSTAT                                                      0x0
+
+		Clear Impedance Calibration
+		PSU_DDR_PHY_PGCR2_CLRZCAL                                                       0x0
+
+		Clear Parity Error
+		PSU_DDR_PHY_PGCR2_CLRPERR                                                       0x0
+
+		Initialization Complete Pin Configuration
+		PSU_DDR_PHY_PGCR2_ICPC                                                          0x0
+
+		Data Training PUB Mode Exit Timer
+		PSU_DDR_PHY_PGCR2_DTPMXTMR                                                      0xf
+
+		Initialization Bypass
+		PSU_DDR_PHY_PGCR2_INITFSMBYP                                                    0x0
+
+		PLL FSM Bypass
+		PSU_DDR_PHY_PGCR2_PLLFSMBYP                                                     0x0
+
+		Refresh Period
+		PSU_DDR_PHY_PGCR2_TREFPRD                                                       0x12302
+
+		PHY General Configuration Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080018, 0xFFFFFFFFU ,0x00F12302U)  
+		RegMask = (DDR_PHY_PGCR2_CLRTSTAT_MASK | DDR_PHY_PGCR2_CLRZCAL_MASK | DDR_PHY_PGCR2_CLRPERR_MASK | DDR_PHY_PGCR2_ICPC_MASK | DDR_PHY_PGCR2_DTPMXTMR_MASK | DDR_PHY_PGCR2_INITFSMBYP_MASK | DDR_PHY_PGCR2_PLLFSMBYP_MASK | DDR_PHY_PGCR2_TREFPRD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_PGCR2_CLRTSTAT_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR2_CLRZCAL_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR2_CLRPERR_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR2_ICPC_SHIFT
+			| 0x0000000FU << DDR_PHY_PGCR2_DTPMXTMR_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR2_INITFSMBYP_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
+			| 0x00012302U << DDR_PHY_PGCR2_TREFPRD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F12302U);
+	/*############################################################################################################################ */
+
+		/*Register : PGCR5 @ 0XFD080024

+
+		Frequency B Ratio Term
+		PSU_DDR_PHY_PGCR5_FRQBT                                                         0x1
+
+		Frequency A Ratio Term
+		PSU_DDR_PHY_PGCR5_FRQAT                                                         0x1
+
+		DFI Disconnect Time Period
+		PSU_DDR_PHY_PGCR5_DISCNPERIOD                                                   0x0
+
+		Receiver bias core side control
+		PSU_DDR_PHY_PGCR5_VREF_RBCTRL                                                   0xf
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_PGCR5_RESERVED_3                                                    0x0
+
+		Internal VREF generator REFSEL ragne select
+		PSU_DDR_PHY_PGCR5_DXREFISELRANGE                                                0x1
+
+		DDL Page Read Write select
+		PSU_DDR_PHY_PGCR5_DDLPGACT                                                      0x0
+
+		DDL Page Read Write select
+		PSU_DDR_PHY_PGCR5_DDLPGRW                                                       0x0
+
+		PHY General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080024, 0xFFFFFFFFU ,0x010100F4U)  
+		RegMask = (DDR_PHY_PGCR5_FRQBT_MASK | DDR_PHY_PGCR5_FRQAT_MASK | DDR_PHY_PGCR5_DISCNPERIOD_MASK | DDR_PHY_PGCR5_VREF_RBCTRL_MASK | DDR_PHY_PGCR5_RESERVED_3_MASK | DDR_PHY_PGCR5_DXREFISELRANGE_MASK | DDR_PHY_PGCR5_DDLPGACT_MASK | DDR_PHY_PGCR5_DDLPGRW_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDR_PHY_PGCR5_FRQBT_SHIFT
+			| 0x00000001U << DDR_PHY_PGCR5_FRQAT_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR5_DISCNPERIOD_SHIFT
+			| 0x0000000FU << DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR5_RESERVED_3_SHIFT
+			| 0x00000001U << DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR5_DDLPGACT_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR5_DDLPGRW_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PGCR5_OFFSET ,0xFFFFFFFFU ,0x010100F4U);
+	/*############################################################################################################################ */
+
+		/*Register : PTR0 @ 0XFD080040

+
+		PLL Power-Down Time
+		PSU_DDR_PHY_PTR0_TPLLPD                                                         0x2f0
+
+		PLL Gear Shift Time
+		PSU_DDR_PHY_PTR0_TPLLGS                                                         0x60
+
+		PHY Reset Time
+		PSU_DDR_PHY_PTR0_TPHYRST                                                        0x10
+
+		PHY Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080040, 0xFFFFFFFFU ,0x5E001810U)  
+		RegMask = (DDR_PHY_PTR0_TPLLPD_MASK | DDR_PHY_PTR0_TPLLGS_MASK | DDR_PHY_PTR0_TPHYRST_MASK |  0 );
+
+		RegVal = ((0x000002F0U << DDR_PHY_PTR0_TPLLPD_SHIFT
+			| 0x00000060U << DDR_PHY_PTR0_TPLLGS_SHIFT
+			| 0x00000010U << DDR_PHY_PTR0_TPHYRST_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PTR0_OFFSET ,0xFFFFFFFFU ,0x5E001810U);
+	/*############################################################################################################################ */
+
+		/*Register : PTR1 @ 0XFD080044

+
+		PLL Lock Time
+		PSU_DDR_PHY_PTR1_TPLLLOCK                                                       0x80
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_PTR1_RESERVED_15_13                                                 0x0
+
+		PLL Reset Time
+		PSU_DDR_PHY_PTR1_TPLLRST                                                        0x5f0
+
+		PHY Timing Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080044, 0xFFFFFFFFU ,0x008005F0U)  
+		RegMask = (DDR_PHY_PTR1_TPLLLOCK_MASK | DDR_PHY_PTR1_RESERVED_15_13_MASK | DDR_PHY_PTR1_TPLLRST_MASK |  0 );
+
+		RegVal = ((0x00000080U << DDR_PHY_PTR1_TPLLLOCK_SHIFT
+			| 0x00000000U << DDR_PHY_PTR1_RESERVED_15_13_SHIFT
+			| 0x000005F0U << DDR_PHY_PTR1_TPLLRST_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PTR1_OFFSET ,0xFFFFFFFFU ,0x008005F0U);
+	/*############################################################################################################################ */
+
+		/*Register : DSGCR @ 0XFD080090

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DSGCR_RESERVED_31_28                                                0x0
+
+		When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
+		fault calculation.
+		PSU_DDR_PHY_DSGCR_RDBICLSEL                                                     0x0
+
+		When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.
+		PSU_DDR_PHY_DSGCR_RDBICL                                                        0x2
+
+		PHY Impedance Update Enable
+		PSU_DDR_PHY_DSGCR_PHYZUEN                                                       0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DSGCR_RESERVED_22                                                   0x0
+
+		SDRAM Reset Output Enable
+		PSU_DDR_PHY_DSGCR_RSTOE                                                         0x1
+
+		Single Data Rate Mode
+		PSU_DDR_PHY_DSGCR_SDRMODE                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DSGCR_RESERVED_18                                                   0x0
+
+		ATO Analog Test Enable
+		PSU_DDR_PHY_DSGCR_ATOAE                                                         0x0
+
+		DTO Output Enable
+		PSU_DDR_PHY_DSGCR_DTOOE                                                         0x0
+
+		DTO I/O Mode
+		PSU_DDR_PHY_DSGCR_DTOIOM                                                        0x0
+
+		DTO Power Down Receiver
+		PSU_DDR_PHY_DSGCR_DTOPDR                                                        0x1
+
+		Reserved. Return zeroes on reads
+		PSU_DDR_PHY_DSGCR_RESERVED_13                                                   0x0
+
+		DTO On-Die Termination
+		PSU_DDR_PHY_DSGCR_DTOODT                                                        0x0
+
+		PHY Update Acknowledge Delay
+		PSU_DDR_PHY_DSGCR_PUAD                                                          0x4
+
+		Controller Update Acknowledge Enable
+		PSU_DDR_PHY_DSGCR_CUAEN                                                         0x1
+
+		Reserved. Return zeroes on reads
+		PSU_DDR_PHY_DSGCR_RESERVED_4_3                                                  0x0
+
+		Controller Impedance Update Enable
+		PSU_DDR_PHY_DSGCR_CTLZUEN                                                       0x0
+
+		Reserved. Return zeroes on reads
+		PSU_DDR_PHY_DSGCR_RESERVED_1                                                    0x0
+
+		PHY Update Request Enable
+		PSU_DDR_PHY_DSGCR_PUREN                                                         0x1
+
+		DDR System General Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD080090, 0xFFFFFFFFU ,0x02A04121U)  
+		RegMask = (DDR_PHY_DSGCR_RESERVED_31_28_MASK | DDR_PHY_DSGCR_RDBICLSEL_MASK | DDR_PHY_DSGCR_RDBICL_MASK | DDR_PHY_DSGCR_PHYZUEN_MASK | DDR_PHY_DSGCR_RESERVED_22_MASK | DDR_PHY_DSGCR_RSTOE_MASK | DDR_PHY_DSGCR_SDRMODE_MASK | DDR_PHY_DSGCR_RESERVED_18_MASK | DDR_PHY_DSGCR_ATOAE_MASK | DDR_PHY_DSGCR_DTOOE_MASK | DDR_PHY_DSGCR_DTOIOM_MASK | DDR_PHY_DSGCR_DTOPDR_MASK | DDR_PHY_DSGCR_RESERVED_13_MASK | DDR_PHY_DSGCR_DTOODT_MASK | DDR_PHY_DSGCR_PUAD_MASK | DDR_PHY_DSGCR_CUAEN_MASK | DDR_PHY_DSGCR_RESERVED_4_3_MASK | DDR_PHY_DSGCR_CTLZUEN_MASK | DDR_PHY_DSGCR_RESERVED_1_MASK | DDR_PHY_DSGCR_PUREN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DSGCR_RESERVED_31_28_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RDBICLSEL_SHIFT
+			| 0x00000002U << DDR_PHY_DSGCR_RDBICL_SHIFT
+			| 0x00000001U << DDR_PHY_DSGCR_PHYZUEN_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RESERVED_22_SHIFT
+			| 0x00000001U << DDR_PHY_DSGCR_RSTOE_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_SDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RESERVED_18_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_ATOAE_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_DTOOE_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_DTOIOM_SHIFT
+			| 0x00000001U << DDR_PHY_DSGCR_DTOPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RESERVED_13_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_DTOODT_SHIFT
+			| 0x00000004U << DDR_PHY_DSGCR_PUAD_SHIFT
+			| 0x00000001U << DDR_PHY_DSGCR_CUAEN_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RESERVED_4_3_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_CTLZUEN_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RESERVED_1_SHIFT
+			| 0x00000001U << DDR_PHY_DSGCR_PUREN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DSGCR_OFFSET ,0xFFFFFFFFU ,0x02A04121U);
+	/*############################################################################################################################ */
+
+		/*Register : DCR @ 0XFD080100

+
+		DDR4 Gear Down Timing.
+		PSU_DDR_PHY_DCR_GEARDN                                                          0x0
+
+		Un-used Bank Group
+		PSU_DDR_PHY_DCR_UBG                                                             0x0
+
+		Un-buffered DIMM Address Mirroring
+		PSU_DDR_PHY_DCR_UDIMM                                                           0x0
+
+		DDR 2T Timing
+		PSU_DDR_PHY_DCR_DDR2T                                                           0x0
+
+		No Simultaneous Rank Access
+		PSU_DDR_PHY_DCR_NOSRA                                                           0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DCR_RESERVED_26_18                                                  0x0
+
+		Byte Mask
+		PSU_DDR_PHY_DCR_BYTEMASK                                                        0x1
+
+		DDR Type
+		PSU_DDR_PHY_DCR_DDRTYPE                                                         0x0
+
+		Multi-Purpose Register (MPR) DQ (DDR3 Only)
+		PSU_DDR_PHY_DCR_MPRDQ                                                           0x0
+
+		Primary DQ (DDR3 Only)
+		PSU_DDR_PHY_DCR_PDQ                                                             0x0
+
+		DDR 8-Bank
+		PSU_DDR_PHY_DCR_DDR8BNK                                                         0x1
+
+		DDR Mode
+		PSU_DDR_PHY_DCR_DDRMD                                                           0x4
+
+		DRAM Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD080100, 0xFFFFFFFFU ,0x0800040CU)  
+		RegMask = (DDR_PHY_DCR_GEARDN_MASK | DDR_PHY_DCR_UBG_MASK | DDR_PHY_DCR_UDIMM_MASK | DDR_PHY_DCR_DDR2T_MASK | DDR_PHY_DCR_NOSRA_MASK | DDR_PHY_DCR_RESERVED_26_18_MASK | DDR_PHY_DCR_BYTEMASK_MASK | DDR_PHY_DCR_DDRTYPE_MASK | DDR_PHY_DCR_MPRDQ_MASK | DDR_PHY_DCR_PDQ_MASK | DDR_PHY_DCR_DDR8BNK_MASK | DDR_PHY_DCR_DDRMD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DCR_GEARDN_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_UBG_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_UDIMM_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_DDR2T_SHIFT
+			| 0x00000001U << DDR_PHY_DCR_NOSRA_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_RESERVED_26_18_SHIFT
+			| 0x00000001U << DDR_PHY_DCR_BYTEMASK_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_DDRTYPE_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_MPRDQ_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_PDQ_SHIFT
+			| 0x00000001U << DDR_PHY_DCR_DDR8BNK_SHIFT
+			| 0x00000004U << DDR_PHY_DCR_DDRMD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DCR_OFFSET ,0xFFFFFFFFU ,0x0800040CU);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR0 @ 0XFD080110

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR0_RESERVED_31_29                                                0x0
+
+		Activate to activate command delay (different banks)
+		PSU_DDR_PHY_DTPR0_TRRD                                                          0x6
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR0_RESERVED_23                                                   0x0
+
+		Activate to precharge command delay
+		PSU_DDR_PHY_DTPR0_TRAS                                                          0x24
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR0_RESERVED_15                                                   0x0
+
+		Precharge command period
+		PSU_DDR_PHY_DTPR0_TRP                                                           0x12
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR0_RESERVED_7_5                                                  0x0
+
+		Internal read to precharge command delay
+		PSU_DDR_PHY_DTPR0_TRTP                                                          0x8
+
+		DRAM Timing Parameters Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080110, 0xFFFFFFFFU ,0x06241208U)  
+		RegMask = (DDR_PHY_DTPR0_RESERVED_31_29_MASK | DDR_PHY_DTPR0_TRRD_MASK | DDR_PHY_DTPR0_RESERVED_23_MASK | DDR_PHY_DTPR0_TRAS_MASK | DDR_PHY_DTPR0_RESERVED_15_MASK | DDR_PHY_DTPR0_TRP_MASK | DDR_PHY_DTPR0_RESERVED_7_5_MASK | DDR_PHY_DTPR0_TRTP_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
+			| 0x00000006U << DDR_PHY_DTPR0_TRRD_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR0_RESERVED_23_SHIFT
+			| 0x00000024U << DDR_PHY_DTPR0_TRAS_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR0_RESERVED_15_SHIFT
+			| 0x00000012U << DDR_PHY_DTPR0_TRP_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
+			| 0x00000008U << DDR_PHY_DTPR0_TRTP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06241208U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR1 @ 0XFD080114

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR1_RESERVED_31                                                   0x0
+
+		Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.
+		PSU_DDR_PHY_DTPR1_TWLMRD                                                        0x28
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR1_RESERVED_23                                                   0x0
+
+		4-bank activate period
+		PSU_DDR_PHY_DTPR1_TFAW                                                          0x18
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR1_RESERVED_15_11                                                0x0
+
+		Load mode update delay (DDR4 and DDR3 only)
+		PSU_DDR_PHY_DTPR1_TMOD                                                          0x7
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR1_RESERVED_7_5                                                  0x0
+
+		Load mode cycle time
+		PSU_DDR_PHY_DTPR1_TMRD                                                          0x8
+
+		DRAM Timing Parameters Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080114, 0xFFFFFFFFU ,0x28180708U)  
+		RegMask = (DDR_PHY_DTPR1_RESERVED_31_MASK | DDR_PHY_DTPR1_TWLMRD_MASK | DDR_PHY_DTPR1_RESERVED_23_MASK | DDR_PHY_DTPR1_TFAW_MASK | DDR_PHY_DTPR1_RESERVED_15_11_MASK | DDR_PHY_DTPR1_TMOD_MASK | DDR_PHY_DTPR1_RESERVED_7_5_MASK | DDR_PHY_DTPR1_TMRD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR1_RESERVED_31_SHIFT
+			| 0x00000028U << DDR_PHY_DTPR1_TWLMRD_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR1_RESERVED_23_SHIFT
+			| 0x00000018U << DDR_PHY_DTPR1_TFAW_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR1_RESERVED_15_11_SHIFT
+			| 0x00000007U << DDR_PHY_DTPR1_TMOD_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR1_RESERVED_7_5_SHIFT
+			| 0x00000008U << DDR_PHY_DTPR1_TMRD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR1_OFFSET ,0xFFFFFFFFU ,0x28180708U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR2 @ 0XFD080118

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR2_RESERVED_31_29                                                0x0
+
+		Read to Write command delay. Valid values are
+		PSU_DDR_PHY_DTPR2_TRTW                                                          0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR2_RESERVED_27_25                                                0x0
+
+		Read to ODT delay (DDR3 only)
+		PSU_DDR_PHY_DTPR2_TRTODT                                                        0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR2_RESERVED_23_20                                                0x0
+
+		CKE minimum pulse width
+		PSU_DDR_PHY_DTPR2_TCKE                                                          0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR2_RESERVED_15_10                                                0x0
+
+		Self refresh exit delay
+		PSU_DDR_PHY_DTPR2_TXS                                                           0x200
+
+		DRAM Timing Parameters Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080118, 0xFFFFFFFFU ,0x00080200U)  
+		RegMask = (DDR_PHY_DTPR2_RESERVED_31_29_MASK | DDR_PHY_DTPR2_TRTW_MASK | DDR_PHY_DTPR2_RESERVED_27_25_MASK | DDR_PHY_DTPR2_TRTODT_MASK | DDR_PHY_DTPR2_RESERVED_23_20_MASK | DDR_PHY_DTPR2_TCKE_MASK | DDR_PHY_DTPR2_RESERVED_15_10_MASK | DDR_PHY_DTPR2_TXS_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR2_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR2_TRTW_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR2_RESERVED_27_25_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR2_TRTODT_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR2_RESERVED_23_20_SHIFT
+			| 0x00000008U << DDR_PHY_DTPR2_TCKE_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR2_RESERVED_15_10_SHIFT
+			| 0x00000200U << DDR_PHY_DTPR2_TXS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR2_OFFSET ,0xFFFFFFFFU ,0x00080200U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR3 @ 0XFD08011C

+
+		ODT turn-off delay extension
+		PSU_DDR_PHY_DTPR3_TOFDX                                                         0x4
+
+		Read to read and write to write command delay
+		PSU_DDR_PHY_DTPR3_TCCD                                                          0x0
+
+		DLL locking time
+		PSU_DDR_PHY_DTPR3_TDLLK                                                         0x300
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR3_RESERVED_15_12                                                0x0
+
+		Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
+		PSU_DDR_PHY_DTPR3_TDQSCKMAX                                                     0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR3_RESERVED_7_3                                                  0x0
+
+		DQS output access time from CK/CK# (LPDDR2/3 only)
+		PSU_DDR_PHY_DTPR3_TDQSCK                                                        0x4
+
+		DRAM Timing Parameters Register 3
+		(OFFSET, MASK, VALUE)      (0XFD08011C, 0xFFFFFFFFU ,0x83000804U)  
+		RegMask = (DDR_PHY_DTPR3_TOFDX_MASK | DDR_PHY_DTPR3_TCCD_MASK | DDR_PHY_DTPR3_TDLLK_MASK | DDR_PHY_DTPR3_RESERVED_15_12_MASK | DDR_PHY_DTPR3_TDQSCKMAX_MASK | DDR_PHY_DTPR3_RESERVED_7_3_MASK | DDR_PHY_DTPR3_TDQSCK_MASK |  0 );
+
+		RegVal = ((0x00000004U << DDR_PHY_DTPR3_TOFDX_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR3_TCCD_SHIFT
+			| 0x00000300U << DDR_PHY_DTPR3_TDLLK_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
+			| 0x00000008U << DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
+			| 0x00000004U << DDR_PHY_DTPR3_TDQSCK_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000804U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR4 @ 0XFD080120

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR4_RESERVED_31_30                                                0x0
+
+		ODT turn-on/turn-off delays (DDR2 only)
+		PSU_DDR_PHY_DTPR4_TAOND_TAOFD                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR4_RESERVED_27_26                                                0x0
+
+		Refresh-to-Refresh
+		PSU_DDR_PHY_DTPR4_TRFC                                                          0x116
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR4_RESERVED_15_14                                                0x0
+
+		Write leveling output delay
+		PSU_DDR_PHY_DTPR4_TWLO                                                          0x2b
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR4_RESERVED_7_5                                                  0x0
+
+		Power down exit delay
+		PSU_DDR_PHY_DTPR4_TXP                                                           0x8
+
+		DRAM Timing Parameters Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080120, 0xFFFFFFFFU ,0x01162B08U)  
+		RegMask = (DDR_PHY_DTPR4_RESERVED_31_30_MASK | DDR_PHY_DTPR4_TAOND_TAOFD_MASK | DDR_PHY_DTPR4_RESERVED_27_26_MASK | DDR_PHY_DTPR4_TRFC_MASK | DDR_PHY_DTPR4_RESERVED_15_14_MASK | DDR_PHY_DTPR4_TWLO_MASK | DDR_PHY_DTPR4_RESERVED_7_5_MASK | DDR_PHY_DTPR4_TXP_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR4_RESERVED_31_30_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR4_RESERVED_27_26_SHIFT
+			| 0x00000116U << DDR_PHY_DTPR4_TRFC_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR4_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DTPR4_TWLO_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR4_RESERVED_7_5_SHIFT
+			| 0x00000008U << DDR_PHY_DTPR4_TXP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR4_OFFSET ,0xFFFFFFFFU ,0x01162B08U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR5 @ 0XFD080124

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR5_RESERVED_31_24                                                0x0
+
+		Activate to activate command delay (same bank)
+		PSU_DDR_PHY_DTPR5_TRC                                                           0x32
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR5_RESERVED_15                                                   0x0
+
+		Activate to read or write delay
+		PSU_DDR_PHY_DTPR5_TRCD                                                          0xf
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR5_RESERVED_7_5                                                  0x0
+
+		Internal write to read command delay
+		PSU_DDR_PHY_DTPR5_TWTR                                                          0x9
+
+		DRAM Timing Parameters Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080124, 0xFFFFFFFFU ,0x00320F09U)  
+		RegMask = (DDR_PHY_DTPR5_RESERVED_31_24_MASK | DDR_PHY_DTPR5_TRC_MASK | DDR_PHY_DTPR5_RESERVED_15_MASK | DDR_PHY_DTPR5_TRCD_MASK | DDR_PHY_DTPR5_RESERVED_7_5_MASK | DDR_PHY_DTPR5_TWTR_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR5_RESERVED_31_24_SHIFT
+			| 0x00000032U << DDR_PHY_DTPR5_TRC_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR5_RESERVED_15_SHIFT
+			| 0x0000000FU << DDR_PHY_DTPR5_TRCD_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR5_RESERVED_7_5_SHIFT
+			| 0x00000009U << DDR_PHY_DTPR5_TWTR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR5_OFFSET ,0xFFFFFFFFU ,0x00320F09U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR6 @ 0XFD080128

+
+		PUB Write Latency Enable
+		PSU_DDR_PHY_DTPR6_PUBWLEN                                                       0x0
+
+		PUB Read Latency Enable
+		PSU_DDR_PHY_DTPR6_PUBRLEN                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR6_RESERVED_29_14                                                0x0
+
+		Write Latency
+		PSU_DDR_PHY_DTPR6_PUBWL                                                         0xe
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR6_RESERVED_7_6                                                  0x0
+
+		Read Latency
+		PSU_DDR_PHY_DTPR6_PUBRL                                                         0xf
+
+		DRAM Timing Parameters Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU)  
+		RegMask = (DDR_PHY_DTPR6_PUBWLEN_MASK | DDR_PHY_DTPR6_PUBRLEN_MASK | DDR_PHY_DTPR6_RESERVED_29_14_MASK | DDR_PHY_DTPR6_PUBWL_MASK | DDR_PHY_DTPR6_RESERVED_7_6_MASK | DDR_PHY_DTPR6_PUBRL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR6_PUBWLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR6_PUBRLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR6_RESERVED_29_14_SHIFT
+			| 0x0000000EU << DDR_PHY_DTPR6_PUBWL_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR6_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DTPR6_PUBRL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR6_OFFSET ,0xFFFFFFFFU ,0x00000E0FU);
+	/*############################################################################################################################ */
+
+		/*Register : RDIMMGCR0 @ 0XFD080140

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_31                                               0x0
+
+		RDMIMM Quad CS Enable
+		PSU_DDR_PHY_RDIMMGCR0_QCSEN                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28                                            0x0
+
+		RDIMM Outputs I/O Mode
+		PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM                                                  0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24                                            0x0
+
+		ERROUT# Output Enable
+		PSU_DDR_PHY_RDIMMGCR0_ERROUTOE                                                  0x0
+
+		ERROUT# I/O Mode
+		PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM                                                 0x1
+
+		ERROUT# Power Down Receiver
+		PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_20                                               0x0
+
+		ERROUT# On-Die Termination
+		PSU_DDR_PHY_RDIMMGCR0_ERROUTODT                                                 0x0
+
+		Load Reduced DIMM
+		PSU_DDR_PHY_RDIMMGCR0_LRDIMM                                                    0x0
+
+		PAR_IN I/O Mode
+		PSU_DDR_PHY_RDIMMGCR0_PARINIOM                                                  0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8                                             0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD                                             0x0
+
+		Rank Mirror Enable.
+		PSU_DDR_PHY_RDIMMGCR0_RNKMRREN                                                  0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_3                                                0x0
+
+		Stop on Parity Error
+		PSU_DDR_PHY_RDIMMGCR0_SOPERR                                                    0x0
+
+		Parity Error No Registering
+		PSU_DDR_PHY_RDIMMGCR0_ERRNOREG                                                  0x0
+
+		Registered DIMM
+		PSU_DDR_PHY_RDIMMGCR0_RDIMM                                                     0x0
+
+		RDIMM General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080140, 0xFFFFFFFFU ,0x08400020U)  
+		RegMask = (DDR_PHY_RDIMMGCR0_RESERVED_31_MASK | DDR_PHY_RDIMMGCR0_QCSEN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK | DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK | DDR_PHY_RDIMMGCR0_ERROUTOE_MASK | DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK | DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK | DDR_PHY_RDIMMGCR0_RESERVED_20_MASK | DDR_PHY_RDIMMGCR0_ERROUTODT_MASK | DDR_PHY_RDIMMGCR0_LRDIMM_MASK | DDR_PHY_RDIMMGCR0_PARINIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_3_MASK | DDR_PHY_RDIMMGCR0_SOPERR_MASK | DDR_PHY_RDIMMGCR0_ERRNOREG_MASK | DDR_PHY_RDIMMGCR0_RDIMM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_QCSEN_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT
+			| 0x00000001U << DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT
+			| 0x00000001U << DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT
+			| 0x00000002U << DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_SOPERR_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RDIMM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_RDIMMGCR0_OFFSET ,0xFFFFFFFFU ,0x08400020U);
+	/*############################################################################################################################ */
+
+		/*Register : RDIMMGCR1 @ 0XFD080144

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29                                            0x0
+
+		Address [17] B-side Inversion Disable
+		PSU_DDR_PHY_RDIMMGCR1_A17BID                                                    0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR1_RESERVED_27                                               0x0
+
+		Command word to command word programming delay
+		PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR1_RESERVED_23                                               0x0
+
+		Command word to command word programming delay
+		PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L                                                  0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR1_RESERVED_19                                               0x0
+
+		Command word to command word programming delay
+		PSU_DDR_PHY_RDIMMGCR1_TBCMRD                                                    0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14                                            0x0
+
+		Stabilization time
+		PSU_DDR_PHY_RDIMMGCR1_TBCSTAB                                                   0xc80
+
+		RDIMM General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080144, 0xFFFFFFFFU ,0x00000C80U)  
+		RegMask = (DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK | DDR_PHY_RDIMMGCR1_A17BID_MASK | DDR_PHY_RDIMMGCR1_RESERVED_27_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK | DDR_PHY_RDIMMGCR1_RESERVED_23_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK | DDR_PHY_RDIMMGCR1_RESERVED_19_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_MASK | DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK | DDR_PHY_RDIMMGCR1_TBCSTAB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_A17BID_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT
+			| 0x00000C80U << DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_RDIMMGCR1_OFFSET ,0xFFFFFFFFU ,0x00000C80U);
+	/*############################################################################################################################ */
+
+		/*Register : RDIMMCR1 @ 0XFD080154

+
+		Control Word 15
+		PSU_DDR_PHY_RDIMMCR1_RC15                                                       0x0
+
+		DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
+		PSU_DDR_PHY_RDIMMCR1_RC14                                                       0x0
+
+		DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
+		PSU_DDR_PHY_RDIMMCR1_RC13                                                       0x0
+
+		DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
+		PSU_DDR_PHY_RDIMMCR1_RC12                                                       0x0
+
+		DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
+		rol Word)
+		PSU_DDR_PHY_RDIMMCR1_RC11                                                       0x0
+
+		DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
+		PSU_DDR_PHY_RDIMMCR1_RC10                                                       0x2
+
+		DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
+		PSU_DDR_PHY_RDIMMCR1_RC9                                                        0x0
+
+		DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
+		Control Word)
+		PSU_DDR_PHY_RDIMMCR1_RC8                                                        0x0
+
+		RDIMM Control Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080154, 0xFFFFFFFFU ,0x00000200U)  
+		RegMask = (DDR_PHY_RDIMMCR1_RC15_MASK | DDR_PHY_RDIMMCR1_RC14_MASK | DDR_PHY_RDIMMCR1_RC13_MASK | DDR_PHY_RDIMMCR1_RC12_MASK | DDR_PHY_RDIMMCR1_RC11_MASK | DDR_PHY_RDIMMCR1_RC10_MASK | DDR_PHY_RDIMMCR1_RC9_MASK | DDR_PHY_RDIMMCR1_RC8_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_RDIMMCR1_RC15_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC14_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC13_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC12_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC11_SHIFT
+			| 0x00000002U << DDR_PHY_RDIMMCR1_RC10_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC9_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC8_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_RDIMMCR1_OFFSET ,0xFFFFFFFFU ,0x00000200U);
+	/*############################################################################################################################ */
+
+		/*Register : MR0 @ 0XFD080180

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR0_RESERVED_31_8                                                   0x8
+
+		CA Terminating Rank
+		PSU_DDR_PHY_MR0_CATR                                                            0x0
+
+		Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR0_RSVD_6_5                                                        0x1
+
+		Built-in Self-Test for RZQ
+		PSU_DDR_PHY_MR0_RZQI                                                            0x2
+
+		Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR0_RSVD_2_0                                                        0x0
+
+		LPDDR4 Mode Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080180, 0xFFFFFFFFU ,0x00000830U)  
+		RegMask = (DDR_PHY_MR0_RESERVED_31_8_MASK | DDR_PHY_MR0_CATR_MASK | DDR_PHY_MR0_RSVD_6_5_MASK | DDR_PHY_MR0_RZQI_MASK | DDR_PHY_MR0_RSVD_2_0_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDR_PHY_MR0_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR0_CATR_SHIFT
+			| 0x00000001U << DDR_PHY_MR0_RSVD_6_5_SHIFT
+			| 0x00000002U << DDR_PHY_MR0_RZQI_SHIFT
+			| 0x00000000U << DDR_PHY_MR0_RSVD_2_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR0_OFFSET ,0xFFFFFFFFU ,0x00000830U);
+	/*############################################################################################################################ */
+
+		/*Register : MR1 @ 0XFD080184

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR1_RESERVED_31_8                                                   0x3
+
+		Read Postamble Length
+		PSU_DDR_PHY_MR1_RDPST                                                           0x0
+
+		Write-recovery for auto-precharge command
+		PSU_DDR_PHY_MR1_NWR                                                             0x0
+
+		Read Preamble Length
+		PSU_DDR_PHY_MR1_RDPRE                                                           0x0
+
+		Write Preamble Length
+		PSU_DDR_PHY_MR1_WRPRE                                                           0x0
+
+		Burst Length
+		PSU_DDR_PHY_MR1_BL                                                              0x1
+
+		LPDDR4 Mode Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080184, 0xFFFFFFFFU ,0x00000301U)  
+		RegMask = (DDR_PHY_MR1_RESERVED_31_8_MASK | DDR_PHY_MR1_RDPST_MASK | DDR_PHY_MR1_NWR_MASK | DDR_PHY_MR1_RDPRE_MASK | DDR_PHY_MR1_WRPRE_MASK | DDR_PHY_MR1_BL_MASK |  0 );
+
+		RegVal = ((0x00000003U << DDR_PHY_MR1_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR1_RDPST_SHIFT
+			| 0x00000000U << DDR_PHY_MR1_NWR_SHIFT
+			| 0x00000000U << DDR_PHY_MR1_RDPRE_SHIFT
+			| 0x00000000U << DDR_PHY_MR1_WRPRE_SHIFT
+			| 0x00000001U << DDR_PHY_MR1_BL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR1_OFFSET ,0xFFFFFFFFU ,0x00000301U);
+	/*############################################################################################################################ */
+
+		/*Register : MR2 @ 0XFD080188

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR2_RESERVED_31_8                                                   0x0
+
+		Write Leveling
+		PSU_DDR_PHY_MR2_WRL                                                             0x0
+
+		Write Latency Set
+		PSU_DDR_PHY_MR2_WLS                                                             0x0
+
+		Write Latency
+		PSU_DDR_PHY_MR2_WL                                                              0x4
+
+		Read Latency
+		PSU_DDR_PHY_MR2_RL                                                              0x0
+
+		LPDDR4 Mode Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080188, 0xFFFFFFFFU ,0x00000020U)  
+		RegMask = (DDR_PHY_MR2_RESERVED_31_8_MASK | DDR_PHY_MR2_WRL_MASK | DDR_PHY_MR2_WLS_MASK | DDR_PHY_MR2_WL_MASK | DDR_PHY_MR2_RL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR2_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR2_WRL_SHIFT
+			| 0x00000000U << DDR_PHY_MR2_WLS_SHIFT
+			| 0x00000004U << DDR_PHY_MR2_WL_SHIFT
+			| 0x00000000U << DDR_PHY_MR2_RL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR2_OFFSET ,0xFFFFFFFFU ,0x00000020U);
+	/*############################################################################################################################ */
+
+		/*Register : MR3 @ 0XFD08018C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR3_RESERVED_31_8                                                   0x2
+
+		DBI-Write Enable
+		PSU_DDR_PHY_MR3_DBIWR                                                           0x0
+
+		DBI-Read Enable
+		PSU_DDR_PHY_MR3_DBIRD                                                           0x0
+
+		Pull-down Drive Strength
+		PSU_DDR_PHY_MR3_PDDS                                                            0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR3_RSVD                                                            0x0
+
+		Write Postamble Length
+		PSU_DDR_PHY_MR3_WRPST                                                           0x0
+
+		Pull-up Calibration Point
+		PSU_DDR_PHY_MR3_PUCAL                                                           0x0
+
+		LPDDR4 Mode Register 3
+		(OFFSET, MASK, VALUE)      (0XFD08018C, 0xFFFFFFFFU ,0x00000200U)  
+		RegMask = (DDR_PHY_MR3_RESERVED_31_8_MASK | DDR_PHY_MR3_DBIWR_MASK | DDR_PHY_MR3_DBIRD_MASK | DDR_PHY_MR3_PDDS_MASK | DDR_PHY_MR3_RSVD_MASK | DDR_PHY_MR3_WRPST_MASK | DDR_PHY_MR3_PUCAL_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDR_PHY_MR3_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_DBIWR_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_DBIRD_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_PDDS_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_RSVD_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_WRPST_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_PUCAL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR3_OFFSET ,0xFFFFFFFFU ,0x00000200U);
+	/*############################################################################################################################ */
+
+		/*Register : MR4 @ 0XFD080190

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR4_RESERVED_31_16                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR4_RSVD_15_13                                                      0x0
+
+		Write Preamble
+		PSU_DDR_PHY_MR4_WRP                                                             0x0
+
+		Read Preamble
+		PSU_DDR_PHY_MR4_RDP                                                             0x0
+
+		Read Preamble Training Mode
+		PSU_DDR_PHY_MR4_RPTM                                                            0x0
+
+		Self Refresh Abort
+		PSU_DDR_PHY_MR4_SRA                                                             0x0
+
+		CS to Command Latency Mode
+		PSU_DDR_PHY_MR4_CS2CMDL                                                         0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR4_RSVD1                                                           0x0
+
+		Internal VREF Monitor
+		PSU_DDR_PHY_MR4_IVM                                                             0x0
+
+		Temperature Controlled Refresh Mode
+		PSU_DDR_PHY_MR4_TCRM                                                            0x0
+
+		Temperature Controlled Refresh Range
+		PSU_DDR_PHY_MR4_TCRR                                                            0x0
+
+		Maximum Power Down Mode
+		PSU_DDR_PHY_MR4_MPDM                                                            0x0
+
+		This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR4_RSVD_0                                                          0x0
+
+		DDR4 Mode Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080190, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_MR4_RESERVED_31_16_MASK | DDR_PHY_MR4_RSVD_15_13_MASK | DDR_PHY_MR4_WRP_MASK | DDR_PHY_MR4_RDP_MASK | DDR_PHY_MR4_RPTM_MASK | DDR_PHY_MR4_SRA_MASK | DDR_PHY_MR4_CS2CMDL_MASK | DDR_PHY_MR4_RSVD1_MASK | DDR_PHY_MR4_IVM_MASK | DDR_PHY_MR4_TCRM_MASK | DDR_PHY_MR4_TCRR_MASK | DDR_PHY_MR4_MPDM_MASK | DDR_PHY_MR4_RSVD_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR4_RESERVED_31_16_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_RSVD_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_WRP_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_RDP_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_RPTM_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_SRA_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_CS2CMDL_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_RSVD1_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_IVM_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_TCRM_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_TCRR_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_MPDM_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_RSVD_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR4_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MR5 @ 0XFD080194

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR5_RESERVED_31_16                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR5_RSVD                                                            0x0
+
+		Read DBI
+		PSU_DDR_PHY_MR5_RDBI                                                            0x0
+
+		Write DBI
+		PSU_DDR_PHY_MR5_WDBI                                                            0x0
+
+		Data Mask
+		PSU_DDR_PHY_MR5_DM                                                              0x1
+
+		CA Parity Persistent Error
+		PSU_DDR_PHY_MR5_CAPPE                                                           0x1
+
+		RTT_PARK
+		PSU_DDR_PHY_MR5_RTTPARK                                                         0x3
+
+		ODT Input Buffer during Power Down mode
+		PSU_DDR_PHY_MR5_ODTIBPD                                                         0x0
+
+		C/A Parity Error Status
+		PSU_DDR_PHY_MR5_CAPES                                                           0x0
+
+		CRC Error Clear
+		PSU_DDR_PHY_MR5_CRCEC                                                           0x0
+
+		C/A Parity Latency Mode
+		PSU_DDR_PHY_MR5_CAPM                                                            0x0
+
+		DDR4 Mode Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080194, 0xFFFFFFFFU ,0x000006C0U)  
+		RegMask = (DDR_PHY_MR5_RESERVED_31_16_MASK | DDR_PHY_MR5_RSVD_MASK | DDR_PHY_MR5_RDBI_MASK | DDR_PHY_MR5_WDBI_MASK | DDR_PHY_MR5_DM_MASK | DDR_PHY_MR5_CAPPE_MASK | DDR_PHY_MR5_RTTPARK_MASK | DDR_PHY_MR5_ODTIBPD_MASK | DDR_PHY_MR5_CAPES_MASK | DDR_PHY_MR5_CRCEC_MASK | DDR_PHY_MR5_CAPM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR5_RESERVED_31_16_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_RSVD_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_WDBI_SHIFT
+			| 0x00000001U << DDR_PHY_MR5_DM_SHIFT
+			| 0x00000001U << DDR_PHY_MR5_CAPPE_SHIFT
+			| 0x00000003U << DDR_PHY_MR5_RTTPARK_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_ODTIBPD_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_CAPES_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_CRCEC_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_CAPM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR5_OFFSET ,0xFFFFFFFFU ,0x000006C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MR6 @ 0XFD080198

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR6_RESERVED_31_16                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR6_RSVD_15_13                                                      0x0
+
+		CAS_n to CAS_n command delay for same bank group (tCCD_L)
+		PSU_DDR_PHY_MR6_TCCDL                                                           0x2
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR6_RSVD_9_8                                                        0x0
+
+		VrefDQ Training Enable
+		PSU_DDR_PHY_MR6_VDDQTEN                                                         0x0
+
+		VrefDQ Training Range
+		PSU_DDR_PHY_MR6_VDQTRG                                                          0x0
+
+		VrefDQ Training Values
+		PSU_DDR_PHY_MR6_VDQTVAL                                                         0x19
+
+		DDR4 Mode Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080198, 0xFFFFFFFFU ,0x00000819U)  
+		RegMask = (DDR_PHY_MR6_RESERVED_31_16_MASK | DDR_PHY_MR6_RSVD_15_13_MASK | DDR_PHY_MR6_TCCDL_MASK | DDR_PHY_MR6_RSVD_9_8_MASK | DDR_PHY_MR6_VDDQTEN_MASK | DDR_PHY_MR6_VDQTRG_MASK | DDR_PHY_MR6_VDQTVAL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR6_RESERVED_31_16_SHIFT
+			| 0x00000000U << DDR_PHY_MR6_RSVD_15_13_SHIFT
+			| 0x00000002U << DDR_PHY_MR6_TCCDL_SHIFT
+			| 0x00000000U << DDR_PHY_MR6_RSVD_9_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR6_VDDQTEN_SHIFT
+			| 0x00000000U << DDR_PHY_MR6_VDQTRG_SHIFT
+			| 0x00000019U << DDR_PHY_MR6_VDQTVAL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR6_OFFSET ,0xFFFFFFFFU ,0x00000819U);
+	/*############################################################################################################################ */
+
+		/*Register : MR11 @ 0XFD0801AC

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR11_RESERVED_31_8                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR11_RSVD                                                           0x0
+
+		Power Down Control
+		PSU_DDR_PHY_MR11_PDCTL                                                          0x0
+
+		DQ Bus Receiver On-Die-Termination
+		PSU_DDR_PHY_MR11_DQODT                                                          0x0
+
+		LPDDR4 Mode Register 11
+		(OFFSET, MASK, VALUE)      (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_MR11_RESERVED_31_8_MASK | DDR_PHY_MR11_RSVD_MASK | DDR_PHY_MR11_PDCTL_MASK | DDR_PHY_MR11_DQODT_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR11_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR11_RSVD_SHIFT
+			| 0x00000000U << DDR_PHY_MR11_PDCTL_SHIFT
+			| 0x00000000U << DDR_PHY_MR11_DQODT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR11_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MR12 @ 0XFD0801B0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR12_RESERVED_31_8                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR12_RSVD                                                           0x0
+
+		VREF_CA Range Select.
+		PSU_DDR_PHY_MR12_VR_CA                                                          0x1
+
+		Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
+		PSU_DDR_PHY_MR12_VREF_CA                                                        0xd
+
+		LPDDR4 Mode Register 12
+		(OFFSET, MASK, VALUE)      (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU)  
+		RegMask = (DDR_PHY_MR12_RESERVED_31_8_MASK | DDR_PHY_MR12_RSVD_MASK | DDR_PHY_MR12_VR_CA_MASK | DDR_PHY_MR12_VREF_CA_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR12_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR12_RSVD_SHIFT
+			| 0x00000001U << DDR_PHY_MR12_VR_CA_SHIFT
+			| 0x0000000DU << DDR_PHY_MR12_VREF_CA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR12_OFFSET ,0xFFFFFFFFU ,0x0000004DU);
+	/*############################################################################################################################ */
+
+		/*Register : MR13 @ 0XFD0801B4

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR13_RESERVED_31_8                                                  0x0
+
+		Frequency Set Point Operation Mode
+		PSU_DDR_PHY_MR13_FSPOP                                                          0x0
+
+		Frequency Set Point Write Enable
+		PSU_DDR_PHY_MR13_FSPWR                                                          0x0
+
+		Data Mask Enable
+		PSU_DDR_PHY_MR13_DMD                                                            0x0
+
+		Refresh Rate Option
+		PSU_DDR_PHY_MR13_RRO                                                            0x0
+
+		VREF Current Generator
+		PSU_DDR_PHY_MR13_VRCG                                                           0x1
+
+		VREF Output
+		PSU_DDR_PHY_MR13_VRO                                                            0x0
+
+		Read Preamble Training Mode
+		PSU_DDR_PHY_MR13_RPT                                                            0x0
+
+		Command Bus Training
+		PSU_DDR_PHY_MR13_CBT                                                            0x0
+
+		LPDDR4 Mode Register 13
+		(OFFSET, MASK, VALUE)      (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U)  
+		RegMask = (DDR_PHY_MR13_RESERVED_31_8_MASK | DDR_PHY_MR13_FSPOP_MASK | DDR_PHY_MR13_FSPWR_MASK | DDR_PHY_MR13_DMD_MASK | DDR_PHY_MR13_RRO_MASK | DDR_PHY_MR13_VRCG_MASK | DDR_PHY_MR13_VRO_MASK | DDR_PHY_MR13_RPT_MASK | DDR_PHY_MR13_CBT_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR13_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_FSPOP_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_FSPWR_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_DMD_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_RRO_SHIFT
+			| 0x00000001U << DDR_PHY_MR13_VRCG_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_VRO_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_RPT_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_CBT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR13_OFFSET ,0xFFFFFFFFU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MR14 @ 0XFD0801B8

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR14_RESERVED_31_8                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR14_RSVD                                                           0x0
+
+		VREFDQ Range Selects.
+		PSU_DDR_PHY_MR14_VR_DQ                                                          0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR14_VREF_DQ                                                        0xd
+
+		LPDDR4 Mode Register 14
+		(OFFSET, MASK, VALUE)      (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU)  
+		RegMask = (DDR_PHY_MR14_RESERVED_31_8_MASK | DDR_PHY_MR14_RSVD_MASK | DDR_PHY_MR14_VR_DQ_MASK | DDR_PHY_MR14_VREF_DQ_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR14_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR14_RSVD_SHIFT
+			| 0x00000001U << DDR_PHY_MR14_VR_DQ_SHIFT
+			| 0x0000000DU << DDR_PHY_MR14_VREF_DQ_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR14_OFFSET ,0xFFFFFFFFU ,0x0000004DU);
+	/*############################################################################################################################ */
+
+		/*Register : MR22 @ 0XFD0801D8

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR22_RESERVED_31_8                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR22_RSVD                                                           0x0
+
+		CA ODT termination disable.
+		PSU_DDR_PHY_MR22_ODTD_CA                                                        0x0
+
+		ODT CS override.
+		PSU_DDR_PHY_MR22_ODTE_CS                                                        0x0
+
+		ODT CK override.
+		PSU_DDR_PHY_MR22_ODTE_CK                                                        0x0
+
+		Controller ODT value for VOH calibration.
+		PSU_DDR_PHY_MR22_CODT                                                           0x0
+
+		LPDDR4 Mode Register 22
+		(OFFSET, MASK, VALUE)      (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_MR22_RESERVED_31_8_MASK | DDR_PHY_MR22_RSVD_MASK | DDR_PHY_MR22_ODTD_CA_MASK | DDR_PHY_MR22_ODTE_CS_MASK | DDR_PHY_MR22_ODTE_CK_MASK | DDR_PHY_MR22_CODT_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR22_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR22_RSVD_SHIFT
+			| 0x00000000U << DDR_PHY_MR22_ODTD_CA_SHIFT
+			| 0x00000000U << DDR_PHY_MR22_ODTE_CS_SHIFT
+			| 0x00000000U << DDR_PHY_MR22_ODTE_CK_SHIFT
+			| 0x00000000U << DDR_PHY_MR22_CODT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR22_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DTCR0 @ 0XFD080200

+
+		Refresh During Training
+		PSU_DDR_PHY_DTCR0_RFSHDT                                                        0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR0_RESERVED_27_26                                                0x0
+
+		Data Training Debug Rank Select
+		PSU_DDR_PHY_DTCR0_DTDRS                                                         0x1
+
+		Data Training with Early/Extended Gate
+		PSU_DDR_PHY_DTCR0_DTEXG                                                         0x0
+
+		Data Training Extended Write DQS
+		PSU_DDR_PHY_DTCR0_DTEXD                                                         0x0
+
+		Data Training Debug Step
+		PSU_DDR_PHY_DTCR0_DTDSTP                                                        0x0
+
+		Data Training Debug Enable
+		PSU_DDR_PHY_DTCR0_DTDEN                                                         0x0
+
+		Data Training Debug Byte Select
+		PSU_DDR_PHY_DTCR0_DTDBS                                                         0x0
+
+		Data Training read DBI deskewing configuration
+		PSU_DDR_PHY_DTCR0_DTRDBITR                                                      0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR0_RESERVED_13                                                   0x0
+
+		Data Training Write Bit Deskew Data Mask
+		PSU_DDR_PHY_DTCR0_DTWBDDM                                                       0x1
+
+		Refreshes Issued During Entry to Training
+		PSU_DDR_PHY_DTCR0_RFSHEN                                                        0x1
+
+		Data Training Compare Data
+		PSU_DDR_PHY_DTCR0_DTCMPD                                                        0x1
+
+		Data Training Using MPR
+		PSU_DDR_PHY_DTCR0_DTMPR                                                         0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR0_RESERVED_5_4                                                  0x0
+
+		Data Training Repeat Number
+		PSU_DDR_PHY_DTCR0_DTRPTN                                                        0x7
+
+		Data Training Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080200, 0xFFFFFFFFU ,0x810011C7U)  
+		RegMask = (DDR_PHY_DTCR0_RFSHDT_MASK | DDR_PHY_DTCR0_RESERVED_27_26_MASK | DDR_PHY_DTCR0_DTDRS_MASK | DDR_PHY_DTCR0_DTEXG_MASK | DDR_PHY_DTCR0_DTEXD_MASK | DDR_PHY_DTCR0_DTDSTP_MASK | DDR_PHY_DTCR0_DTDEN_MASK | DDR_PHY_DTCR0_DTDBS_MASK | DDR_PHY_DTCR0_DTRDBITR_MASK | DDR_PHY_DTCR0_RESERVED_13_MASK | DDR_PHY_DTCR0_DTWBDDM_MASK | DDR_PHY_DTCR0_RFSHEN_MASK | DDR_PHY_DTCR0_DTCMPD_MASK | DDR_PHY_DTCR0_DTMPR_MASK | DDR_PHY_DTCR0_RESERVED_5_4_MASK | DDR_PHY_DTCR0_DTRPTN_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDR_PHY_DTCR0_RFSHDT_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR0_DTDRS_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTEXG_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTEXD_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTDSTP_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTDBS_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTRDBITR_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_RESERVED_13_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR0_DTWBDDM_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR0_RFSHEN_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR0_DTCMPD_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR0_DTMPR_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
+			| 0x00000007U << DDR_PHY_DTCR0_DTRPTN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x810011C7U);
+	/*############################################################################################################################ */
+
+		/*Register : DTCR1 @ 0XFD080204

+
+		Rank Enable.
+		PSU_DDR_PHY_DTCR1_RANKEN_RSVD                                                   0x0
+
+		Rank Enable.
+		PSU_DDR_PHY_DTCR1_RANKEN                                                        0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR1_RESERVED_15_14                                                0x0
+
+		Data Training Rank
+		PSU_DDR_PHY_DTCR1_DTRANK                                                        0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR1_RESERVED_11                                                   0x0
+
+		Read Leveling Gate Sampling Difference
+		PSU_DDR_PHY_DTCR1_RDLVLGDIFF                                                    0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR1_RESERVED_7                                                    0x0
+
+		Read Leveling Gate Shift
+		PSU_DDR_PHY_DTCR1_RDLVLGS                                                       0x3
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR1_RESERVED_3                                                    0x0
+
+		Read Preamble Training enable
+		PSU_DDR_PHY_DTCR1_RDPRMVL_TRN                                                   0x1
+
+		Read Leveling Enable
+		PSU_DDR_PHY_DTCR1_RDLVLEN                                                       0x1
+
+		Basic Gate Training Enable
+		PSU_DDR_PHY_DTCR1_BSTEN                                                         0x0
+
+		Data Training Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080204, 0xFFFFFFFFU ,0x00010236U)  
+		RegMask = (DDR_PHY_DTCR1_RANKEN_RSVD_MASK | DDR_PHY_DTCR1_RANKEN_MASK | DDR_PHY_DTCR1_RESERVED_15_14_MASK | DDR_PHY_DTCR1_DTRANK_MASK | DDR_PHY_DTCR1_RESERVED_11_MASK | DDR_PHY_DTCR1_RDLVLGDIFF_MASK | DDR_PHY_DTCR1_RESERVED_7_MASK | DDR_PHY_DTCR1_RDLVLGS_MASK | DDR_PHY_DTCR1_RESERVED_3_MASK | DDR_PHY_DTCR1_RDPRMVL_TRN_MASK | DDR_PHY_DTCR1_RDLVLEN_MASK | DDR_PHY_DTCR1_BSTEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR1_RANKEN_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_RESERVED_15_14_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_DTRANK_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_RESERVED_11_SHIFT
+			| 0x00000002U << DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_RESERVED_7_SHIFT
+			| 0x00000003U << DDR_PHY_DTCR1_RDLVLGS_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_RESERVED_3_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR1_RDLVLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_BSTEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTCR1_OFFSET ,0xFFFFFFFFU ,0x00010236U);
+	/*############################################################################################################################ */
+
+		/*Register : CATR0 @ 0XFD080240

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_CATR0_RESERVED_31_21                                                0x0
+
+		Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command
+		PSU_DDR_PHY_CATR0_CACD                                                          0x14
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_CATR0_RESERVED_15_13                                                0x0
+
+		Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
+		 been sent to the memory
+		PSU_DDR_PHY_CATR0_CAADR                                                         0x10
+
+		CA_1 Response Byte Lane 1
+		PSU_DDR_PHY_CATR0_CA1BYTE1                                                      0x5
+
+		CA_1 Response Byte Lane 0
+		PSU_DDR_PHY_CATR0_CA1BYTE0                                                      0x4
+
+		CA Training Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080240, 0xFFFFFFFFU ,0x00141054U)  
+		RegMask = (DDR_PHY_CATR0_RESERVED_31_21_MASK | DDR_PHY_CATR0_CACD_MASK | DDR_PHY_CATR0_RESERVED_15_13_MASK | DDR_PHY_CATR0_CAADR_MASK | DDR_PHY_CATR0_CA1BYTE1_MASK | DDR_PHY_CATR0_CA1BYTE0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_CATR0_RESERVED_31_21_SHIFT
+			| 0x00000014U << DDR_PHY_CATR0_CACD_SHIFT
+			| 0x00000000U << DDR_PHY_CATR0_RESERVED_15_13_SHIFT
+			| 0x00000010U << DDR_PHY_CATR0_CAADR_SHIFT
+			| 0x00000005U << DDR_PHY_CATR0_CA1BYTE1_SHIFT
+			| 0x00000004U << DDR_PHY_CATR0_CA1BYTE0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_CATR0_OFFSET ,0xFFFFFFFFU ,0x00141054U);
+	/*############################################################################################################################ */
+
+		/*Register : RIOCR5 @ 0XFD0804F4

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RIOCR5_RESERVED_31_16                                               0x0
+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD                                               0x0
+
+		SDRAM On-die Termination Output Enable (OE) Mode Selection.
+		PSU_DDR_PHY_RIOCR5_ODTOEMODE                                                    0x5
+
+		Rank I/O Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U)  
+		RegMask = (DDR_PHY_RIOCR5_RESERVED_31_16_MASK | DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK | DDR_PHY_RIOCR5_ODTOEMODE_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
+			| 0x00000000U << DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT
+			| 0x00000005U << DDR_PHY_RIOCR5_ODTOEMODE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_RIOCR5_OFFSET ,0xFFFFFFFFU ,0x00000005U);
+	/*############################################################################################################################ */
+
+		/*Register : ACIOCR0 @ 0XFD080500

+
+		Address/Command Slew Rate (D3F I/O Only)
+		PSU_DDR_PHY_ACIOCR0_ACSR                                                        0x0
+
+		SDRAM Reset I/O Mode
+		PSU_DDR_PHY_ACIOCR0_RSTIOM                                                      0x1
+
+		SDRAM Reset Power Down Receiver
+		PSU_DDR_PHY_ACIOCR0_RSTPDR                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACIOCR0_RESERVED_27                                                 0x0
+
+		SDRAM Reset On-Die Termination
+		PSU_DDR_PHY_ACIOCR0_RSTODT                                                      0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACIOCR0_RESERVED_25_10                                              0x0
+
+		CK Duty Cycle Correction
+		PSU_DDR_PHY_ACIOCR0_CKDCC                                                       0x0
+
+		AC Power Down Receiver Mode
+		PSU_DDR_PHY_ACIOCR0_ACPDRMODE                                                   0x2
+
+		AC On-die Termination Mode
+		PSU_DDR_PHY_ACIOCR0_ACODTMODE                                                   0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACIOCR0_RESERVED_1                                                  0x0
+
+		Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
+		PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL                                                0x0
+
+		AC I/O Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080500, 0xFFFFFFFFU ,0x30000028U)  
+		RegMask = (DDR_PHY_ACIOCR0_ACSR_MASK | DDR_PHY_ACIOCR0_RSTIOM_MASK | DDR_PHY_ACIOCR0_RSTPDR_MASK | DDR_PHY_ACIOCR0_RESERVED_27_MASK | DDR_PHY_ACIOCR0_RSTODT_MASK | DDR_PHY_ACIOCR0_RESERVED_25_10_MASK | DDR_PHY_ACIOCR0_CKDCC_MASK | DDR_PHY_ACIOCR0_ACPDRMODE_MASK | DDR_PHY_ACIOCR0_ACODTMODE_MASK | DDR_PHY_ACIOCR0_RESERVED_1_MASK | DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACIOCR0_ACSR_SHIFT
+			| 0x00000001U << DDR_PHY_ACIOCR0_RSTIOM_SHIFT
+			| 0x00000001U << DDR_PHY_ACIOCR0_RSTPDR_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_27_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_RSTODT_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_CKDCC_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR0_ACODTMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_1_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACIOCR0_OFFSET ,0xFFFFFFFFU ,0x30000028U);
+	/*############################################################################################################################ */
+
+		/*Register : ACIOCR2 @ 0XFD080508

+
+		Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice
+		PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE                                               0x0
+
+		Clock gating for Output Enable D slices [0]
+		PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0                                                0x0
+
+		Clock gating for Power Down Receiver D slices [0]
+		PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0                                               0x0
+
+		Clock gating for Termination Enable D slices [0]
+		PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0                                                0x0
+
+		Clock gating for CK# D slices [1:0]
+		PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0                                                 0x2
+
+		Clock gating for CK D slices [1:0]
+		PSU_DDR_PHY_ACIOCR2_CKCLKGATE0                                                  0x2
+
+		Clock gating for AC D slices [23:0]
+		PSU_DDR_PHY_ACIOCR2_ACCLKGATE0                                                  0x0
+
+		AC I/O Configuration Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080508, 0xFFFFFFFFU ,0x0A000000U)  
+		RegMask = (DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK | DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK | DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK | DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK | DDR_PHY_ACIOCR2_CKCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACCLKGATE0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACIOCR2_OFFSET ,0xFFFFFFFFU ,0x0A000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ACIOCR3 @ 0XFD08050C

+
+		SDRAM Parity Output Enable (OE) Mode Selection
+		PSU_DDR_PHY_ACIOCR3_PAROEMODE                                                   0x0
+
+		SDRAM Bank Group Output Enable (OE) Mode Selection
+		PSU_DDR_PHY_ACIOCR3_BGOEMODE                                                    0x0
+
+		SDRAM Bank Address Output Enable (OE) Mode Selection
+		PSU_DDR_PHY_ACIOCR3_BAOEMODE                                                    0x0
+
+		SDRAM A[17] Output Enable (OE) Mode Selection
+		PSU_DDR_PHY_ACIOCR3_A17OEMODE                                                   0x0
+
+		SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
+		PSU_DDR_PHY_ACIOCR3_A16OEMODE                                                   0x0
+
+		SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
+		PSU_DDR_PHY_ACIOCR3_ACTOEMODE                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACIOCR3_RESERVED_15_8                                               0x0
+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD                                               0x0
+
+		SDRAM CK Output Enable (OE) Mode Selection.
+		PSU_DDR_PHY_ACIOCR3_CKOEMODE                                                    0x9
+
+		AC I/O Configuration Register 3
+		(OFFSET, MASK, VALUE)      (0XFD08050C, 0xFFFFFFFFU ,0x00000009U)  
+		RegMask = (DDR_PHY_ACIOCR3_PAROEMODE_MASK | DDR_PHY_ACIOCR3_BGOEMODE_MASK | DDR_PHY_ACIOCR3_BAOEMODE_MASK | DDR_PHY_ACIOCR3_A17OEMODE_MASK | DDR_PHY_ACIOCR3_A16OEMODE_MASK | DDR_PHY_ACIOCR3_ACTOEMODE_MASK | DDR_PHY_ACIOCR3_RESERVED_15_8_MASK | DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK | DDR_PHY_ACIOCR3_CKOEMODE_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACIOCR3_PAROEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_BGOEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_BAOEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_A17OEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_A16OEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT
+			| 0x00000009U << DDR_PHY_ACIOCR3_CKOEMODE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACIOCR3_OFFSET ,0xFFFFFFFFU ,0x00000009U);
+	/*############################################################################################################################ */
+
+		/*Register : ACIOCR4 @ 0XFD080510

+
+		Clock gating for AC LB slices and loopback read valid slices
+		PSU_DDR_PHY_ACIOCR4_LBCLKGATE                                                   0x0
+
+		Clock gating for Output Enable D slices [1]
+		PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1                                                0x0
+
+		Clock gating for Power Down Receiver D slices [1]
+		PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1                                               0x0
+
+		Clock gating for Termination Enable D slices [1]
+		PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1                                                0x0
+
+		Clock gating for CK# D slices [3:2]
+		PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1                                                 0x2
+
+		Clock gating for CK D slices [3:2]
+		PSU_DDR_PHY_ACIOCR4_CKCLKGATE1                                                  0x2
+
+		Clock gating for AC D slices [47:24]
+		PSU_DDR_PHY_ACIOCR4_ACCLKGATE1                                                  0x0
+
+		AC I/O Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080510, 0xFFFFFFFFU ,0x0A000000U)  
+		RegMask = (DDR_PHY_ACIOCR4_LBCLKGATE_MASK | DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK | DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK | DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK | DDR_PHY_ACIOCR4_CKCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACCLKGATE1_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACIOCR4_OFFSET ,0xFFFFFFFFU ,0x0A000000U);
+	/*############################################################################################################################ */
+
+		/*Register : IOVCR0 @ 0XFD080520

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_IOVCR0_RESERVED_31_29                                               0x0
+
+		Address/command lane VREF Pad Enable
+		PSU_DDR_PHY_IOVCR0_ACREFPEN                                                     0x0
+
+		Address/command lane Internal VREF Enable
+		PSU_DDR_PHY_IOVCR0_ACREFEEN                                                     0x0
+
+		Address/command lane Single-End VREF Enable
+		PSU_DDR_PHY_IOVCR0_ACREFSEN                                                     0x1
+
+		Address/command lane Internal VREF Enable
+		PSU_DDR_PHY_IOVCR0_ACREFIEN                                                     0x1
+
+		External VREF generato REFSEL range select
+		PSU_DDR_PHY_IOVCR0_ACREFESELRANGE                                               0x0
+
+		Address/command lane External VREF Select
+		PSU_DDR_PHY_IOVCR0_ACREFESEL                                                    0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE                                               0x1
+
+		Address/command lane Single-End VREF Select
+		PSU_DDR_PHY_IOVCR0_ACREFSSEL                                                    0x30
+
+		Internal VREF generator REFSEL ragne select
+		PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE                                              0x1
+
+		REFSEL Control for internal AC IOs
+		PSU_DDR_PHY_IOVCR0_ACVREFISEL                                                   0x30
+
+		IO VREF Control Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U)  
+		RegMask = (DDR_PHY_IOVCR0_RESERVED_31_29_MASK | DDR_PHY_IOVCR0_ACREFPEN_MASK | DDR_PHY_IOVCR0_ACREFEEN_MASK | DDR_PHY_IOVCR0_ACREFSEN_MASK | DDR_PHY_IOVCR0_ACREFIEN_MASK | DDR_PHY_IOVCR0_ACREFESELRANGE_MASK | DDR_PHY_IOVCR0_ACREFESEL_MASK | DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK | DDR_PHY_IOVCR0_ACREFSSEL_MASK | DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK | DDR_PHY_IOVCR0_ACVREFISEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_IOVCR0_ACREFPEN_SHIFT
+			| 0x00000000U << DDR_PHY_IOVCR0_ACREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_IOVCR0_ACREFSEN_SHIFT
+			| 0x00000001U << DDR_PHY_IOVCR0_ACREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_IOVCR0_ACREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_IOVCR0_ACREFSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_IOVCR0_ACVREFISEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_IOVCR0_OFFSET ,0xFFFFFFFFU ,0x0300B0B0U);
+	/*############################################################################################################################ */
+
+		/*Register : VTCR0 @ 0XFD080528

+
+		Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training
+		PSU_DDR_PHY_VTCR0_TVREF                                                         0x7
+
+		DRM DQ VREF training Enable
+		PSU_DDR_PHY_VTCR0_DVEN                                                          0x1
+
+		Per Device Addressability Enable
+		PSU_DDR_PHY_VTCR0_PDAEN                                                         0x1
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_VTCR0_RESERVED_26                                                   0x0
+
+		VREF Word Count
+		PSU_DDR_PHY_VTCR0_VWCR                                                          0x4
+
+		DRAM DQ VREF step size used during DRAM VREF training
+		PSU_DDR_PHY_VTCR0_DVSS                                                          0x0
+
+		Maximum VREF limit value used during DRAM VREF training
+		PSU_DDR_PHY_VTCR0_DVMAX                                                         0x32
+
+		Minimum VREF limit value used during DRAM VREF training
+		PSU_DDR_PHY_VTCR0_DVMIN                                                         0x0
+
+		Initial DRAM DQ VREF value used during DRAM VREF training
+		PSU_DDR_PHY_VTCR0_DVINIT                                                        0x19
+
+		VREF Training Control Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080528, 0xFFFFFFFFU ,0xF9032019U)  
+		RegMask = (DDR_PHY_VTCR0_TVREF_MASK | DDR_PHY_VTCR0_DVEN_MASK | DDR_PHY_VTCR0_PDAEN_MASK | DDR_PHY_VTCR0_RESERVED_26_MASK | DDR_PHY_VTCR0_VWCR_MASK | DDR_PHY_VTCR0_DVSS_MASK | DDR_PHY_VTCR0_DVMAX_MASK | DDR_PHY_VTCR0_DVMIN_MASK | DDR_PHY_VTCR0_DVINIT_MASK |  0 );
+
+		RegVal = ((0x00000007U << DDR_PHY_VTCR0_TVREF_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR0_DVEN_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR0_PDAEN_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR0_RESERVED_26_SHIFT
+			| 0x00000004U << DDR_PHY_VTCR0_VWCR_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR0_DVSS_SHIFT
+			| 0x00000032U << DDR_PHY_VTCR0_DVMAX_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR0_DVMIN_SHIFT
+			| 0x00000019U << DDR_PHY_VTCR0_DVINIT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_VTCR0_OFFSET ,0xFFFFFFFFU ,0xF9032019U);
+	/*############################################################################################################################ */
+
+		/*Register : VTCR1 @ 0XFD08052C

+
+		Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)
+		PSU_DDR_PHY_VTCR1_HVSS                                                          0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_VTCR1_RESERVED_27                                                   0x0
+
+		Maximum VREF limit value used during DRAM VREF training.
+		PSU_DDR_PHY_VTCR1_HVMAX                                                         0x7f
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_VTCR1_RESERVED_19                                                   0x0
+
+		Minimum VREF limit value used during DRAM VREF training.
+		PSU_DDR_PHY_VTCR1_HVMIN                                                         0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_VTCR1_RESERVED_11                                                   0x0
+
+		Static Host Vref Rank Value
+		PSU_DDR_PHY_VTCR1_SHRNK                                                         0x0
+
+		Static Host Vref Rank Enable
+		PSU_DDR_PHY_VTCR1_SHREN                                                         0x1
+
+		Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
+		PSU_DDR_PHY_VTCR1_TVREFIO                                                       0x4
+
+		Eye LCDL Offset value for VREF training
+		PSU_DDR_PHY_VTCR1_EOFF                                                          0x1
+
+		Number of LCDL Eye points for which VREF training is repeated
+		PSU_DDR_PHY_VTCR1_ENUM                                                          0x1
+
+		HOST (IO) internal VREF training Enable
+		PSU_DDR_PHY_VTCR1_HVEN                                                          0x1
+
+		Host IO Type Control
+		PSU_DDR_PHY_VTCR1_HVIO                                                          0x1
+
+		VREF Training Control Register 1
+		(OFFSET, MASK, VALUE)      (0XFD08052C, 0xFFFFFFFFU ,0x07F0018FU)  
+		RegMask = (DDR_PHY_VTCR1_HVSS_MASK | DDR_PHY_VTCR1_RESERVED_27_MASK | DDR_PHY_VTCR1_HVMAX_MASK | DDR_PHY_VTCR1_RESERVED_19_MASK | DDR_PHY_VTCR1_HVMIN_MASK | DDR_PHY_VTCR1_RESERVED_11_MASK | DDR_PHY_VTCR1_SHRNK_MASK | DDR_PHY_VTCR1_SHREN_MASK | DDR_PHY_VTCR1_TVREFIO_MASK | DDR_PHY_VTCR1_EOFF_MASK | DDR_PHY_VTCR1_ENUM_MASK | DDR_PHY_VTCR1_HVEN_MASK | DDR_PHY_VTCR1_HVIO_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_VTCR1_HVSS_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR1_RESERVED_27_SHIFT
+			| 0x0000007FU << DDR_PHY_VTCR1_HVMAX_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR1_RESERVED_19_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR1_HVMIN_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR1_RESERVED_11_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR1_SHRNK_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR1_SHREN_SHIFT
+			| 0x00000004U << DDR_PHY_VTCR1_TVREFIO_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR1_EOFF_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR1_ENUM_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR1_HVEN_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR1_HVIO_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F0018FU);
+	/*############################################################################################################################ */
+
+		/*Register : ACBDLR6 @ 0XFD080558

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR6_RESERVED_31_30                                              0x0
+
+		Delay select for the BDL on Address A[3].
+		PSU_DDR_PHY_ACBDLR6_A03BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR6_RESERVED_23_22                                              0x0
+
+		Delay select for the BDL on Address A[2].
+		PSU_DDR_PHY_ACBDLR6_A02BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR6_RESERVED_15_14                                              0x0
+
+		Delay select for the BDL on Address A[1].
+		PSU_DDR_PHY_ACBDLR6_A01BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR6_RESERVED_7_6                                                0x0
+
+		Delay select for the BDL on Address A[0].
+		PSU_DDR_PHY_ACBDLR6_A00BD                                                       0x0
+
+		AC Bit Delay Line Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080558, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_ACBDLR6_RESERVED_31_30_MASK | DDR_PHY_ACBDLR6_A03BD_MASK | DDR_PHY_ACBDLR6_RESERVED_23_22_MASK | DDR_PHY_ACBDLR6_A02BD_MASK | DDR_PHY_ACBDLR6_RESERVED_15_14_MASK | DDR_PHY_ACBDLR6_A01BD_MASK | DDR_PHY_ACBDLR6_RESERVED_7_6_MASK | DDR_PHY_ACBDLR6_A00BD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_A03BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_A02BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_A01BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_A00BD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACBDLR6_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ACBDLR7 @ 0XFD08055C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR7_RESERVED_31_30                                              0x0
+
+		Delay select for the BDL on Address A[7].
+		PSU_DDR_PHY_ACBDLR7_A07BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR7_RESERVED_23_22                                              0x0
+
+		Delay select for the BDL on Address A[6].
+		PSU_DDR_PHY_ACBDLR7_A06BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR7_RESERVED_15_14                                              0x0
+
+		Delay select for the BDL on Address A[5].
+		PSU_DDR_PHY_ACBDLR7_A05BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR7_RESERVED_7_6                                                0x0
+
+		Delay select for the BDL on Address A[4].
+		PSU_DDR_PHY_ACBDLR7_A04BD                                                       0x0
+
+		AC Bit Delay Line Register 7
+		(OFFSET, MASK, VALUE)      (0XFD08055C, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_ACBDLR7_RESERVED_31_30_MASK | DDR_PHY_ACBDLR7_A07BD_MASK | DDR_PHY_ACBDLR7_RESERVED_23_22_MASK | DDR_PHY_ACBDLR7_A06BD_MASK | DDR_PHY_ACBDLR7_RESERVED_15_14_MASK | DDR_PHY_ACBDLR7_A05BD_MASK | DDR_PHY_ACBDLR7_RESERVED_7_6_MASK | DDR_PHY_ACBDLR7_A04BD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_A07BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_A06BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_A05BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_A04BD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACBDLR7_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ACBDLR8 @ 0XFD080560

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR8_RESERVED_31_30                                              0x0
+
+		Delay select for the BDL on Address A[11].
+		PSU_DDR_PHY_ACBDLR8_A11BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR8_RESERVED_23_22                                              0x0
+
+		Delay select for the BDL on Address A[10].
+		PSU_DDR_PHY_ACBDLR8_A10BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR8_RESERVED_15_14                                              0x0
+
+		Delay select for the BDL on Address A[9].
+		PSU_DDR_PHY_ACBDLR8_A09BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR8_RESERVED_7_6                                                0x0
+
+		Delay select for the BDL on Address A[8].
+		PSU_DDR_PHY_ACBDLR8_A08BD                                                       0x0
+
+		AC Bit Delay Line Register 8
+		(OFFSET, MASK, VALUE)      (0XFD080560, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_ACBDLR8_RESERVED_31_30_MASK | DDR_PHY_ACBDLR8_A11BD_MASK | DDR_PHY_ACBDLR8_RESERVED_23_22_MASK | DDR_PHY_ACBDLR8_A10BD_MASK | DDR_PHY_ACBDLR8_RESERVED_15_14_MASK | DDR_PHY_ACBDLR8_A09BD_MASK | DDR_PHY_ACBDLR8_RESERVED_7_6_MASK | DDR_PHY_ACBDLR8_A08BD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_A11BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_A10BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_A09BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_A08BD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACBDLR8_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQCR @ 0XFD080680

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ZQCR_RESERVED_31_26                                                 0x0
+
+		ZQ VREF Range
+		PSU_DDR_PHY_ZQCR_ZQREFISELRANGE                                                 0x0
+
+		Programmable Wait for Frequency B
+		PSU_DDR_PHY_ZQCR_PGWAIT_FRQB                                                    0x11
+
+		Programmable Wait for Frequency A
+		PSU_DDR_PHY_ZQCR_PGWAIT_FRQA                                                    0x11
+
+		ZQ VREF Pad Enable
+		PSU_DDR_PHY_ZQCR_ZQREFPEN                                                       0x0
+
+		ZQ Internal VREF Enable
+		PSU_DDR_PHY_ZQCR_ZQREFIEN                                                       0x1
+
+		Choice of termination mode
+		PSU_DDR_PHY_ZQCR_ODT_MODE                                                       0x1
+
+		Force ZCAL VT update
+		PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE                                           0x0
+
+		IO VT Drift Limit
+		PSU_DDR_PHY_ZQCR_IODLMT                                                         0x2
+
+		Averaging algorithm enable, if set, enables averaging algorithm
+		PSU_DDR_PHY_ZQCR_AVGEN                                                          0x1
+
+		Maximum number of averaging rounds to be used by averaging algorithm
+		PSU_DDR_PHY_ZQCR_AVGMAX                                                         0x2
+
+		ZQ Calibration Type
+		PSU_DDR_PHY_ZQCR_ZCALT                                                          0x0
+
+		ZQ Power Down
+		PSU_DDR_PHY_ZQCR_ZQPD                                                           0x0
+
+		ZQ Impedance Control Register
+		(OFFSET, MASK, VALUE)      (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U)  
+		RegMask = (DDR_PHY_ZQCR_RESERVED_31_26_MASK | DDR_PHY_ZQCR_ZQREFISELRANGE_MASK | DDR_PHY_ZQCR_PGWAIT_FRQB_MASK | DDR_PHY_ZQCR_PGWAIT_FRQA_MASK | DDR_PHY_ZQCR_ZQREFPEN_MASK | DDR_PHY_ZQCR_ZQREFIEN_MASK | DDR_PHY_ZQCR_ODT_MODE_MASK | DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK | DDR_PHY_ZQCR_IODLMT_MASK | DDR_PHY_ZQCR_AVGEN_MASK | DDR_PHY_ZQCR_AVGMAX_MASK | DDR_PHY_ZQCR_ZCALT_MASK | DDR_PHY_ZQCR_ZQPD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
+			| 0x00000000U << DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT
+			| 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT
+			| 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT
+			| 0x00000000U << DDR_PHY_ZQCR_ZQREFPEN_SHIFT
+			| 0x00000001U << DDR_PHY_ZQCR_ZQREFIEN_SHIFT
+			| 0x00000001U << DDR_PHY_ZQCR_ODT_MODE_SHIFT
+			| 0x00000000U << DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT
+			| 0x00000002U << DDR_PHY_ZQCR_IODLMT_SHIFT
+			| 0x00000001U << DDR_PHY_ZQCR_AVGEN_SHIFT
+			| 0x00000002U << DDR_PHY_ZQCR_AVGMAX_SHIFT
+			| 0x00000000U << DDR_PHY_ZQCR_ZCALT_SHIFT
+			| 0x00000000U << DDR_PHY_ZQCR_ZQPD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ZQCR_OFFSET ,0xFFFFFFFFU ,0x008A2A58U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQ0PR0 @ 0XFD080684

+
+		Pull-down drive strength ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN                                                  0x0
+
+		Pull-up drive strength ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN                                                  0x0
+
+		Pull-down termination ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN                                                  0x0
+
+		Pull-up termination ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN                                                  0x0
+
+		Calibration segment bypass
+		PSU_DDR_PHY_ZQ0PR0_ZSEGBYP                                                      0x0
+
+		VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
+		PSU_DDR_PHY_ZQ0PR0_ZLE_MODE                                                     0x0
+
+		Termination adjustment
+		PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST                                                   0x0
+
+		Pulldown drive strength adjustment
+		PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST                                                0x0
+
+		Pullup drive strength adjustment
+		PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST                                                0x0
+
+		DRAM Impedance Divide Ratio
+		PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT                                               0x7
+
+		HOST Impedance Divide Ratio
+		PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT                                               0x7
+
+		Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
+		PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD                                            0xd
+
+		Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
+		PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU                                            0xd
+
+		ZQ n Impedance Control Program Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080684, 0xFFFFFFFFU ,0x000077DDU)  
+		RegMask = (DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_ZSEGBYP_MASK | DDR_PHY_ZQ0PR0_ZLE_MODE_MASK | DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT
+			| 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT
+			| 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT
+			| 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT
+			| 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ZQ0PR0_OFFSET ,0xFFFFFFFFU ,0x000077DDU);
+	/*############################################################################################################################ */
+
+		/*Register : ZQ0OR0 @ 0XFD080694

+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26                                               0x0
+
+		Override value for the pull-up output impedance
+		PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD                                            0x1e1
+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10                                               0x0
+
+		Override value for the pull-down output impedance
+		PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD                                            0x210
+
+		ZQ n Impedance Control Override Data Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080694, 0xFFFFFFFFU ,0x01E10210U)  
+		RegMask = (DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK | DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT
+			| 0x000001E1U << DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT
+			| 0x00000210U << DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ZQ0OR0_OFFSET ,0xFFFFFFFFU ,0x01E10210U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQ0OR1 @ 0XFD080698

+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26                                               0x0
+
+		Override value for the pull-up termination
+		PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD                                            0x1e1
+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10                                               0x0
+
+		Override value for the pull-down termination
+		PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD                                            0x0
+
+		ZQ n Impedance Control Override Data Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080698, 0xFFFFFFFFU ,0x01E10000U)  
+		RegMask = (DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK | DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT
+			| 0x000001E1U << DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ZQ0OR1_OFFSET ,0xFFFFFFFFU ,0x01E10000U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQ1PR0 @ 0XFD0806A4

+
+		Pull-down drive strength ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN                                                  0x0
+
+		Pull-up drive strength ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN                                                  0x0
+
+		Pull-down termination ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN                                                  0x0
+
+		Pull-up termination ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN                                                  0x0
+
+		Calibration segment bypass
+		PSU_DDR_PHY_ZQ1PR0_ZSEGBYP                                                      0x0
+
+		VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
+		PSU_DDR_PHY_ZQ1PR0_ZLE_MODE                                                     0x0
+
+		Termination adjustment
+		PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST                                                   0x0
+
+		Pulldown drive strength adjustment
+		PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST                                                0x1
+
+		Pullup drive strength adjustment
+		PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST                                                0x0
+
+		DRAM Impedance Divide Ratio
+		PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT                                               0x7
+
+		HOST Impedance Divide Ratio
+		PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT                                               0xb
+
+		Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
+		PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD                                            0xd
+
+		Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
+		PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU                                            0xb
+
+		ZQ n Impedance Control Program Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU)  
+		RegMask = (DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_ZSEGBYP_MASK | DDR_PHY_ZQ1PR0_ZLE_MODE_MASK | DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT
+			| 0x00000001U << DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT
+			| 0x00000007U << DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT
+			| 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT
+			| 0x0000000DU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT
+			| 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ZQ1PR0_OFFSET ,0xFFFFFFFFU ,0x00087BDBU);
+	/*############################################################################################################################ */
+
+		/*Register : DX0GCR0 @ 0XFD080700

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX0GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX0GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX0GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX0GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX0GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX0GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX0GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX0GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX0GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX0GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX0GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX0GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX0GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX0GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080700, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX0GCR0_CALBYP_MASK | DDR_PHY_DX0GCR0_MDLEN_MASK | DDR_PHY_DX0GCR0_CODTSHFT_MASK | DDR_PHY_DX0GCR0_DQSDCC_MASK | DDR_PHY_DX0GCR0_RDDLY_MASK | DDR_PHY_DX0GCR0_RESERVED_19_14_MASK | DDR_PHY_DX0GCR0_DQSNSEPDR_MASK | DDR_PHY_DX0GCR0_DQSSEPDR_MASK | DDR_PHY_DX0GCR0_RTTOAL_MASK | DDR_PHY_DX0GCR0_RTTOH_MASK | DDR_PHY_DX0GCR0_CPDRSHFT_MASK | DDR_PHY_DX0GCR0_DQSRPD_MASK | DDR_PHY_DX0GCR0_DQSGPDR_MASK | DDR_PHY_DX0GCR0_RESERVED_4_MASK | DDR_PHY_DX0GCR0_DQSGODT_MASK | DDR_PHY_DX0GCR0_DQSGOE_MASK | DDR_PHY_DX0GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX0GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX0GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX0GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX0GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX0GCR4 @ 0XFD080710

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX0GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX0GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX0GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX0GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX0GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX0GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX0GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX0GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX0GCR4_RESERVED_31_29_MASK | DDR_PHY_DX0GCR4_DXREFPEN_MASK | DDR_PHY_DX0GCR4_DXREFEEN_MASK | DDR_PHY_DX0GCR4_DXREFSEN_MASK | DDR_PHY_DX0GCR4_RESERVED_24_MASK | DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFESEL_MASK | DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFSSEL_MASK | DDR_PHY_DX0GCR4_RESERVED_7_6_MASK | DDR_PHY_DX0GCR4_DXREFIEN_MASK | DDR_PHY_DX0GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX0GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX0GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX0GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX0GCR5 @ 0XFD080714

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX0GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX0GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX0GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX0GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080714, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX0GCR5_RESERVED_31_MASK | DDR_PHY_DX0GCR5_DXREFISELR3_MASK | DDR_PHY_DX0GCR5_RESERVED_23_MASK | DDR_PHY_DX0GCR5_DXREFISELR2_MASK | DDR_PHY_DX0GCR5_RESERVED_15_MASK | DDR_PHY_DX0GCR5_DXREFISELR1_MASK | DDR_PHY_DX0GCR5_RESERVED_7_MASK | DDR_PHY_DX0GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX0GCR6 @ 0XFD080718

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX0GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX0GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX0GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX0GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX0GCR6_RESERVED_31_30_MASK | DDR_PHY_DX0GCR6_DXDQVREFR3_MASK | DDR_PHY_DX0GCR6_RESERVED_23_22_MASK | DDR_PHY_DX0GCR6_DXDQVREFR2_MASK | DDR_PHY_DX0GCR6_RESERVED_15_14_MASK | DDR_PHY_DX0GCR6_DXDQVREFR1_MASK | DDR_PHY_DX0GCR6_RESERVED_7_6_MASK | DDR_PHY_DX0GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX0LCDLR2 @ 0XFD080788

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX0LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080788, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX0LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX0LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX0GTR0 @ 0XFD0807C0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX0GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX0GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX0GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX0GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX0GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX0GTR0_RESERVED_31_24_MASK | DDR_PHY_DX0GTR0_WDQSL_MASK | DDR_PHY_DX0GTR0_RESERVED_23_20_MASK | DDR_PHY_DX0GTR0_WLSL_MASK | DDR_PHY_DX0GTR0_RESERVED_15_13_MASK | DDR_PHY_DX0GTR0_RESERVED_12_8_MASK | DDR_PHY_DX0GTR0_RESERVED_7_5_MASK | DDR_PHY_DX0GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX0GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX1GCR0 @ 0XFD080800

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX1GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX1GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX1GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX1GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX1GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX1GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX1GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX1GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX1GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX1GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX1GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX1GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX1GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX1GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080800, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX1GCR0_CALBYP_MASK | DDR_PHY_DX1GCR0_MDLEN_MASK | DDR_PHY_DX1GCR0_CODTSHFT_MASK | DDR_PHY_DX1GCR0_DQSDCC_MASK | DDR_PHY_DX1GCR0_RDDLY_MASK | DDR_PHY_DX1GCR0_RESERVED_19_14_MASK | DDR_PHY_DX1GCR0_DQSNSEPDR_MASK | DDR_PHY_DX1GCR0_DQSSEPDR_MASK | DDR_PHY_DX1GCR0_RTTOAL_MASK | DDR_PHY_DX1GCR0_RTTOH_MASK | DDR_PHY_DX1GCR0_CPDRSHFT_MASK | DDR_PHY_DX1GCR0_DQSRPD_MASK | DDR_PHY_DX1GCR0_DQSGPDR_MASK | DDR_PHY_DX1GCR0_RESERVED_4_MASK | DDR_PHY_DX1GCR0_DQSGODT_MASK | DDR_PHY_DX1GCR0_DQSGOE_MASK | DDR_PHY_DX1GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX1GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX1GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX1GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX1GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX1GCR4 @ 0XFD080810

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX1GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX1GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX1GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX1GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX1GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX1GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX1GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX1GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX1GCR4_RESERVED_31_29_MASK | DDR_PHY_DX1GCR4_DXREFPEN_MASK | DDR_PHY_DX1GCR4_DXREFEEN_MASK | DDR_PHY_DX1GCR4_DXREFSEN_MASK | DDR_PHY_DX1GCR4_RESERVED_24_MASK | DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFESEL_MASK | DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFSSEL_MASK | DDR_PHY_DX1GCR4_RESERVED_7_6_MASK | DDR_PHY_DX1GCR4_DXREFIEN_MASK | DDR_PHY_DX1GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX1GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX1GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX1GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX1GCR5 @ 0XFD080814

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX1GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX1GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX1GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX1GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080814, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX1GCR5_RESERVED_31_MASK | DDR_PHY_DX1GCR5_DXREFISELR3_MASK | DDR_PHY_DX1GCR5_RESERVED_23_MASK | DDR_PHY_DX1GCR5_DXREFISELR2_MASK | DDR_PHY_DX1GCR5_RESERVED_15_MASK | DDR_PHY_DX1GCR5_DXREFISELR1_MASK | DDR_PHY_DX1GCR5_RESERVED_7_MASK | DDR_PHY_DX1GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX1GCR6 @ 0XFD080818

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX1GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX1GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX1GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX1GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX1GCR6_RESERVED_31_30_MASK | DDR_PHY_DX1GCR6_DXDQVREFR3_MASK | DDR_PHY_DX1GCR6_RESERVED_23_22_MASK | DDR_PHY_DX1GCR6_DXDQVREFR2_MASK | DDR_PHY_DX1GCR6_RESERVED_15_14_MASK | DDR_PHY_DX1GCR6_DXDQVREFR1_MASK | DDR_PHY_DX1GCR6_RESERVED_7_6_MASK | DDR_PHY_DX1GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX1LCDLR2 @ 0XFD080888

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX1LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080888, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX1LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX1LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX1GTR0 @ 0XFD0808C0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX1GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX1GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX1GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX1GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX1GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX1GTR0_RESERVED_31_24_MASK | DDR_PHY_DX1GTR0_WDQSL_MASK | DDR_PHY_DX1GTR0_RESERVED_23_20_MASK | DDR_PHY_DX1GTR0_WLSL_MASK | DDR_PHY_DX1GTR0_RESERVED_15_13_MASK | DDR_PHY_DX1GTR0_RESERVED_12_8_MASK | DDR_PHY_DX1GTR0_RESERVED_7_5_MASK | DDR_PHY_DX1GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX1GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GCR0 @ 0XFD080900

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX2GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX2GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX2GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX2GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX2GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX2GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX2GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX2GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX2GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX2GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX2GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX2GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX2GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX2GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080900, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX2GCR0_CALBYP_MASK | DDR_PHY_DX2GCR0_MDLEN_MASK | DDR_PHY_DX2GCR0_CODTSHFT_MASK | DDR_PHY_DX2GCR0_DQSDCC_MASK | DDR_PHY_DX2GCR0_RDDLY_MASK | DDR_PHY_DX2GCR0_RESERVED_19_14_MASK | DDR_PHY_DX2GCR0_DQSNSEPDR_MASK | DDR_PHY_DX2GCR0_DQSSEPDR_MASK | DDR_PHY_DX2GCR0_RTTOAL_MASK | DDR_PHY_DX2GCR0_RTTOH_MASK | DDR_PHY_DX2GCR0_CPDRSHFT_MASK | DDR_PHY_DX2GCR0_DQSRPD_MASK | DDR_PHY_DX2GCR0_DQSGPDR_MASK | DDR_PHY_DX2GCR0_RESERVED_4_MASK | DDR_PHY_DX2GCR0_DQSGODT_MASK | DDR_PHY_DX2GCR0_DQSGOE_MASK | DDR_PHY_DX2GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX2GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX2GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GCR1 @ 0XFD080904

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX2GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX2GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX2GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX2GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX2GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX2GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX2GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX2GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX2GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX2GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX2GCR1_DXPDRMODE_MASK | DDR_PHY_DX2GCR1_RESERVED_15_MASK | DDR_PHY_DX2GCR1_QSNSEL_MASK | DDR_PHY_DX2GCR1_QSSEL_MASK | DDR_PHY_DX2GCR1_OEEN_MASK | DDR_PHY_DX2GCR1_PDREN_MASK | DDR_PHY_DX2GCR1_TEEN_MASK | DDR_PHY_DX2GCR1_DSEN_MASK | DDR_PHY_DX2GCR1_DMEN_MASK | DDR_PHY_DX2GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX2GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GCR4 @ 0XFD080910

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX2GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX2GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX2GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX2GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX2GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX2GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX2GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX2GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX2GCR4_RESERVED_31_29_MASK | DDR_PHY_DX2GCR4_DXREFPEN_MASK | DDR_PHY_DX2GCR4_DXREFEEN_MASK | DDR_PHY_DX2GCR4_DXREFSEN_MASK | DDR_PHY_DX2GCR4_RESERVED_24_MASK | DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFESEL_MASK | DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFSSEL_MASK | DDR_PHY_DX2GCR4_RESERVED_7_6_MASK | DDR_PHY_DX2GCR4_DXREFIEN_MASK | DDR_PHY_DX2GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX2GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX2GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GCR5 @ 0XFD080914

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX2GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX2GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX2GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX2GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080914, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX2GCR5_RESERVED_31_MASK | DDR_PHY_DX2GCR5_DXREFISELR3_MASK | DDR_PHY_DX2GCR5_RESERVED_23_MASK | DDR_PHY_DX2GCR5_DXREFISELR2_MASK | DDR_PHY_DX2GCR5_RESERVED_15_MASK | DDR_PHY_DX2GCR5_DXREFISELR1_MASK | DDR_PHY_DX2GCR5_RESERVED_7_MASK | DDR_PHY_DX2GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GCR6 @ 0XFD080918

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX2GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX2GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX2GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX2GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX2GCR6_RESERVED_31_30_MASK | DDR_PHY_DX2GCR6_DXDQVREFR3_MASK | DDR_PHY_DX2GCR6_RESERVED_23_22_MASK | DDR_PHY_DX2GCR6_DXDQVREFR2_MASK | DDR_PHY_DX2GCR6_RESERVED_15_14_MASK | DDR_PHY_DX2GCR6_DXDQVREFR1_MASK | DDR_PHY_DX2GCR6_RESERVED_7_6_MASK | DDR_PHY_DX2GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX2LCDLR2 @ 0XFD080988

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX2LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080988, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX2LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX2LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GTR0 @ 0XFD0809C0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX2GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX2GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX2GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX2GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX2GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX2GTR0_RESERVED_31_24_MASK | DDR_PHY_DX2GTR0_WDQSL_MASK | DDR_PHY_DX2GTR0_RESERVED_23_20_MASK | DDR_PHY_DX2GTR0_WLSL_MASK | DDR_PHY_DX2GTR0_RESERVED_15_13_MASK | DDR_PHY_DX2GTR0_RESERVED_12_8_MASK | DDR_PHY_DX2GTR0_RESERVED_7_5_MASK | DDR_PHY_DX2GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX2GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GCR0 @ 0XFD080A00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX3GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX3GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX3GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX3GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX3GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX3GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX3GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX3GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX3GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX3GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX3GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX3GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX3GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX3GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080A00, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX3GCR0_CALBYP_MASK | DDR_PHY_DX3GCR0_MDLEN_MASK | DDR_PHY_DX3GCR0_CODTSHFT_MASK | DDR_PHY_DX3GCR0_DQSDCC_MASK | DDR_PHY_DX3GCR0_RDDLY_MASK | DDR_PHY_DX3GCR0_RESERVED_19_14_MASK | DDR_PHY_DX3GCR0_DQSNSEPDR_MASK | DDR_PHY_DX3GCR0_DQSSEPDR_MASK | DDR_PHY_DX3GCR0_RTTOAL_MASK | DDR_PHY_DX3GCR0_RTTOH_MASK | DDR_PHY_DX3GCR0_CPDRSHFT_MASK | DDR_PHY_DX3GCR0_DQSRPD_MASK | DDR_PHY_DX3GCR0_DQSGPDR_MASK | DDR_PHY_DX3GCR0_RESERVED_4_MASK | DDR_PHY_DX3GCR0_DQSGODT_MASK | DDR_PHY_DX3GCR0_DQSGOE_MASK | DDR_PHY_DX3GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX3GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX3GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GCR1 @ 0XFD080A04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX3GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX3GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX3GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX3GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX3GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX3GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX3GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX3GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX3GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX3GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX3GCR1_DXPDRMODE_MASK | DDR_PHY_DX3GCR1_RESERVED_15_MASK | DDR_PHY_DX3GCR1_QSNSEL_MASK | DDR_PHY_DX3GCR1_QSSEL_MASK | DDR_PHY_DX3GCR1_OEEN_MASK | DDR_PHY_DX3GCR1_PDREN_MASK | DDR_PHY_DX3GCR1_TEEN_MASK | DDR_PHY_DX3GCR1_DSEN_MASK | DDR_PHY_DX3GCR1_DMEN_MASK | DDR_PHY_DX3GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX3GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GCR4 @ 0XFD080A10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX3GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX3GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX3GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX3GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX3GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX3GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX3GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX3GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX3GCR4_RESERVED_31_29_MASK | DDR_PHY_DX3GCR4_DXREFPEN_MASK | DDR_PHY_DX3GCR4_DXREFEEN_MASK | DDR_PHY_DX3GCR4_DXREFSEN_MASK | DDR_PHY_DX3GCR4_RESERVED_24_MASK | DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFESEL_MASK | DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFSSEL_MASK | DDR_PHY_DX3GCR4_RESERVED_7_6_MASK | DDR_PHY_DX3GCR4_DXREFIEN_MASK | DDR_PHY_DX3GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX3GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX3GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GCR5 @ 0XFD080A14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX3GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX3GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX3GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX3GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080A14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX3GCR5_RESERVED_31_MASK | DDR_PHY_DX3GCR5_DXREFISELR3_MASK | DDR_PHY_DX3GCR5_RESERVED_23_MASK | DDR_PHY_DX3GCR5_DXREFISELR2_MASK | DDR_PHY_DX3GCR5_RESERVED_15_MASK | DDR_PHY_DX3GCR5_DXREFISELR1_MASK | DDR_PHY_DX3GCR5_RESERVED_7_MASK | DDR_PHY_DX3GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GCR6 @ 0XFD080A18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX3GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX3GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX3GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX3GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX3GCR6_RESERVED_31_30_MASK | DDR_PHY_DX3GCR6_DXDQVREFR3_MASK | DDR_PHY_DX3GCR6_RESERVED_23_22_MASK | DDR_PHY_DX3GCR6_DXDQVREFR2_MASK | DDR_PHY_DX3GCR6_RESERVED_15_14_MASK | DDR_PHY_DX3GCR6_DXDQVREFR1_MASK | DDR_PHY_DX3GCR6_RESERVED_7_6_MASK | DDR_PHY_DX3GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX3LCDLR2 @ 0XFD080A88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX3LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080A88, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX3LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX3LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GTR0 @ 0XFD080AC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX3GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX3GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX3GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX3GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX3GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX3GTR0_RESERVED_31_24_MASK | DDR_PHY_DX3GTR0_WDQSL_MASK | DDR_PHY_DX3GTR0_RESERVED_23_20_MASK | DDR_PHY_DX3GTR0_WLSL_MASK | DDR_PHY_DX3GTR0_RESERVED_15_13_MASK | DDR_PHY_DX3GTR0_RESERVED_12_8_MASK | DDR_PHY_DX3GTR0_RESERVED_7_5_MASK | DDR_PHY_DX3GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX3GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GCR0 @ 0XFD080B00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX4GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX4GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX4GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX4GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX4GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX4GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX4GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX4GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX4GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX4GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX4GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX4GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX4GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX4GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080B00, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX4GCR0_CALBYP_MASK | DDR_PHY_DX4GCR0_MDLEN_MASK | DDR_PHY_DX4GCR0_CODTSHFT_MASK | DDR_PHY_DX4GCR0_DQSDCC_MASK | DDR_PHY_DX4GCR0_RDDLY_MASK | DDR_PHY_DX4GCR0_RESERVED_19_14_MASK | DDR_PHY_DX4GCR0_DQSNSEPDR_MASK | DDR_PHY_DX4GCR0_DQSSEPDR_MASK | DDR_PHY_DX4GCR0_RTTOAL_MASK | DDR_PHY_DX4GCR0_RTTOH_MASK | DDR_PHY_DX4GCR0_CPDRSHFT_MASK | DDR_PHY_DX4GCR0_DQSRPD_MASK | DDR_PHY_DX4GCR0_DQSGPDR_MASK | DDR_PHY_DX4GCR0_RESERVED_4_MASK | DDR_PHY_DX4GCR0_DQSGODT_MASK | DDR_PHY_DX4GCR0_DQSGOE_MASK | DDR_PHY_DX4GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX4GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX4GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GCR1 @ 0XFD080B04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX4GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX4GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX4GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX4GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX4GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX4GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX4GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX4GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX4GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX4GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX4GCR1_DXPDRMODE_MASK | DDR_PHY_DX4GCR1_RESERVED_15_MASK | DDR_PHY_DX4GCR1_QSNSEL_MASK | DDR_PHY_DX4GCR1_QSSEL_MASK | DDR_PHY_DX4GCR1_OEEN_MASK | DDR_PHY_DX4GCR1_PDREN_MASK | DDR_PHY_DX4GCR1_TEEN_MASK | DDR_PHY_DX4GCR1_DSEN_MASK | DDR_PHY_DX4GCR1_DMEN_MASK | DDR_PHY_DX4GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX4GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GCR4 @ 0XFD080B10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX4GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX4GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX4GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX4GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX4GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX4GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX4GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX4GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX4GCR4_RESERVED_31_29_MASK | DDR_PHY_DX4GCR4_DXREFPEN_MASK | DDR_PHY_DX4GCR4_DXREFEEN_MASK | DDR_PHY_DX4GCR4_DXREFSEN_MASK | DDR_PHY_DX4GCR4_RESERVED_24_MASK | DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFESEL_MASK | DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFSSEL_MASK | DDR_PHY_DX4GCR4_RESERVED_7_6_MASK | DDR_PHY_DX4GCR4_DXREFIEN_MASK | DDR_PHY_DX4GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX4GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX4GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GCR5 @ 0XFD080B14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX4GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX4GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX4GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX4GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080B14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX4GCR5_RESERVED_31_MASK | DDR_PHY_DX4GCR5_DXREFISELR3_MASK | DDR_PHY_DX4GCR5_RESERVED_23_MASK | DDR_PHY_DX4GCR5_DXREFISELR2_MASK | DDR_PHY_DX4GCR5_RESERVED_15_MASK | DDR_PHY_DX4GCR5_DXREFISELR1_MASK | DDR_PHY_DX4GCR5_RESERVED_7_MASK | DDR_PHY_DX4GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GCR6 @ 0XFD080B18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX4GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX4GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX4GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX4GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX4GCR6_RESERVED_31_30_MASK | DDR_PHY_DX4GCR6_DXDQVREFR3_MASK | DDR_PHY_DX4GCR6_RESERVED_23_22_MASK | DDR_PHY_DX4GCR6_DXDQVREFR2_MASK | DDR_PHY_DX4GCR6_RESERVED_15_14_MASK | DDR_PHY_DX4GCR6_DXDQVREFR1_MASK | DDR_PHY_DX4GCR6_RESERVED_7_6_MASK | DDR_PHY_DX4GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX4LCDLR2 @ 0XFD080B88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX4LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080B88, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX4LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX4LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GTR0 @ 0XFD080BC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX4GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX4GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX4GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX4GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX4GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX4GTR0_RESERVED_31_24_MASK | DDR_PHY_DX4GTR0_WDQSL_MASK | DDR_PHY_DX4GTR0_RESERVED_23_20_MASK | DDR_PHY_DX4GTR0_WLSL_MASK | DDR_PHY_DX4GTR0_RESERVED_15_13_MASK | DDR_PHY_DX4GTR0_RESERVED_12_8_MASK | DDR_PHY_DX4GTR0_RESERVED_7_5_MASK | DDR_PHY_DX4GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX4GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GCR0 @ 0XFD080C00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX5GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX5GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX5GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX5GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX5GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX5GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX5GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX5GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX5GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX5GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX5GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX5GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX5GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX5GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080C00, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX5GCR0_CALBYP_MASK | DDR_PHY_DX5GCR0_MDLEN_MASK | DDR_PHY_DX5GCR0_CODTSHFT_MASK | DDR_PHY_DX5GCR0_DQSDCC_MASK | DDR_PHY_DX5GCR0_RDDLY_MASK | DDR_PHY_DX5GCR0_RESERVED_19_14_MASK | DDR_PHY_DX5GCR0_DQSNSEPDR_MASK | DDR_PHY_DX5GCR0_DQSSEPDR_MASK | DDR_PHY_DX5GCR0_RTTOAL_MASK | DDR_PHY_DX5GCR0_RTTOH_MASK | DDR_PHY_DX5GCR0_CPDRSHFT_MASK | DDR_PHY_DX5GCR0_DQSRPD_MASK | DDR_PHY_DX5GCR0_DQSGPDR_MASK | DDR_PHY_DX5GCR0_RESERVED_4_MASK | DDR_PHY_DX5GCR0_DQSGODT_MASK | DDR_PHY_DX5GCR0_DQSGOE_MASK | DDR_PHY_DX5GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX5GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX5GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GCR1 @ 0XFD080C04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX5GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX5GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX5GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX5GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX5GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX5GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX5GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX5GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX5GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX5GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX5GCR1_DXPDRMODE_MASK | DDR_PHY_DX5GCR1_RESERVED_15_MASK | DDR_PHY_DX5GCR1_QSNSEL_MASK | DDR_PHY_DX5GCR1_QSSEL_MASK | DDR_PHY_DX5GCR1_OEEN_MASK | DDR_PHY_DX5GCR1_PDREN_MASK | DDR_PHY_DX5GCR1_TEEN_MASK | DDR_PHY_DX5GCR1_DSEN_MASK | DDR_PHY_DX5GCR1_DMEN_MASK | DDR_PHY_DX5GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX5GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GCR4 @ 0XFD080C10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX5GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX5GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX5GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX5GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX5GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX5GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX5GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX5GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX5GCR4_RESERVED_31_29_MASK | DDR_PHY_DX5GCR4_DXREFPEN_MASK | DDR_PHY_DX5GCR4_DXREFEEN_MASK | DDR_PHY_DX5GCR4_DXREFSEN_MASK | DDR_PHY_DX5GCR4_RESERVED_24_MASK | DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFESEL_MASK | DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFSSEL_MASK | DDR_PHY_DX5GCR4_RESERVED_7_6_MASK | DDR_PHY_DX5GCR4_DXREFIEN_MASK | DDR_PHY_DX5GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX5GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX5GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GCR5 @ 0XFD080C14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX5GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX5GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX5GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX5GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080C14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX5GCR5_RESERVED_31_MASK | DDR_PHY_DX5GCR5_DXREFISELR3_MASK | DDR_PHY_DX5GCR5_RESERVED_23_MASK | DDR_PHY_DX5GCR5_DXREFISELR2_MASK | DDR_PHY_DX5GCR5_RESERVED_15_MASK | DDR_PHY_DX5GCR5_DXREFISELR1_MASK | DDR_PHY_DX5GCR5_RESERVED_7_MASK | DDR_PHY_DX5GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GCR6 @ 0XFD080C18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX5GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX5GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX5GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX5GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX5GCR6_RESERVED_31_30_MASK | DDR_PHY_DX5GCR6_DXDQVREFR3_MASK | DDR_PHY_DX5GCR6_RESERVED_23_22_MASK | DDR_PHY_DX5GCR6_DXDQVREFR2_MASK | DDR_PHY_DX5GCR6_RESERVED_15_14_MASK | DDR_PHY_DX5GCR6_DXDQVREFR1_MASK | DDR_PHY_DX5GCR6_RESERVED_7_6_MASK | DDR_PHY_DX5GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX5LCDLR2 @ 0XFD080C88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX5LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080C88, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX5LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX5LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GTR0 @ 0XFD080CC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX5GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX5GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX5GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX5GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX5GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX5GTR0_RESERVED_31_24_MASK | DDR_PHY_DX5GTR0_WDQSL_MASK | DDR_PHY_DX5GTR0_RESERVED_23_20_MASK | DDR_PHY_DX5GTR0_WLSL_MASK | DDR_PHY_DX5GTR0_RESERVED_15_13_MASK | DDR_PHY_DX5GTR0_RESERVED_12_8_MASK | DDR_PHY_DX5GTR0_RESERVED_7_5_MASK | DDR_PHY_DX5GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX5GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GCR0 @ 0XFD080D00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX6GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX6GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX6GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX6GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX6GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX6GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX6GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX6GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX6GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX6GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX6GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX6GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX6GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX6GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080D00, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX6GCR0_CALBYP_MASK | DDR_PHY_DX6GCR0_MDLEN_MASK | DDR_PHY_DX6GCR0_CODTSHFT_MASK | DDR_PHY_DX6GCR0_DQSDCC_MASK | DDR_PHY_DX6GCR0_RDDLY_MASK | DDR_PHY_DX6GCR0_RESERVED_19_14_MASK | DDR_PHY_DX6GCR0_DQSNSEPDR_MASK | DDR_PHY_DX6GCR0_DQSSEPDR_MASK | DDR_PHY_DX6GCR0_RTTOAL_MASK | DDR_PHY_DX6GCR0_RTTOH_MASK | DDR_PHY_DX6GCR0_CPDRSHFT_MASK | DDR_PHY_DX6GCR0_DQSRPD_MASK | DDR_PHY_DX6GCR0_DQSGPDR_MASK | DDR_PHY_DX6GCR0_RESERVED_4_MASK | DDR_PHY_DX6GCR0_DQSGODT_MASK | DDR_PHY_DX6GCR0_DQSGOE_MASK | DDR_PHY_DX6GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX6GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX6GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GCR1 @ 0XFD080D04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX6GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX6GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX6GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX6GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX6GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX6GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX6GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX6GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX6GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX6GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX6GCR1_DXPDRMODE_MASK | DDR_PHY_DX6GCR1_RESERVED_15_MASK | DDR_PHY_DX6GCR1_QSNSEL_MASK | DDR_PHY_DX6GCR1_QSSEL_MASK | DDR_PHY_DX6GCR1_OEEN_MASK | DDR_PHY_DX6GCR1_PDREN_MASK | DDR_PHY_DX6GCR1_TEEN_MASK | DDR_PHY_DX6GCR1_DSEN_MASK | DDR_PHY_DX6GCR1_DMEN_MASK | DDR_PHY_DX6GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX6GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GCR4 @ 0XFD080D10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX6GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX6GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX6GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX6GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX6GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX6GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX6GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX6GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX6GCR4_RESERVED_31_29_MASK | DDR_PHY_DX6GCR4_DXREFPEN_MASK | DDR_PHY_DX6GCR4_DXREFEEN_MASK | DDR_PHY_DX6GCR4_DXREFSEN_MASK | DDR_PHY_DX6GCR4_RESERVED_24_MASK | DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFESEL_MASK | DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFSSEL_MASK | DDR_PHY_DX6GCR4_RESERVED_7_6_MASK | DDR_PHY_DX6GCR4_DXREFIEN_MASK | DDR_PHY_DX6GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX6GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX6GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GCR5 @ 0XFD080D14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX6GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX6GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX6GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX6GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080D14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX6GCR5_RESERVED_31_MASK | DDR_PHY_DX6GCR5_DXREFISELR3_MASK | DDR_PHY_DX6GCR5_RESERVED_23_MASK | DDR_PHY_DX6GCR5_DXREFISELR2_MASK | DDR_PHY_DX6GCR5_RESERVED_15_MASK | DDR_PHY_DX6GCR5_DXREFISELR1_MASK | DDR_PHY_DX6GCR5_RESERVED_7_MASK | DDR_PHY_DX6GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GCR6 @ 0XFD080D18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX6GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX6GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX6GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX6GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX6GCR6_RESERVED_31_30_MASK | DDR_PHY_DX6GCR6_DXDQVREFR3_MASK | DDR_PHY_DX6GCR6_RESERVED_23_22_MASK | DDR_PHY_DX6GCR6_DXDQVREFR2_MASK | DDR_PHY_DX6GCR6_RESERVED_15_14_MASK | DDR_PHY_DX6GCR6_DXDQVREFR1_MASK | DDR_PHY_DX6GCR6_RESERVED_7_6_MASK | DDR_PHY_DX6GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX6LCDLR2 @ 0XFD080D88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX6LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080D88, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX6LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX6LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GTR0 @ 0XFD080DC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX6GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX6GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX6GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX6GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX6GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX6GTR0_RESERVED_31_24_MASK | DDR_PHY_DX6GTR0_WDQSL_MASK | DDR_PHY_DX6GTR0_RESERVED_23_20_MASK | DDR_PHY_DX6GTR0_WLSL_MASK | DDR_PHY_DX6GTR0_RESERVED_15_13_MASK | DDR_PHY_DX6GTR0_RESERVED_12_8_MASK | DDR_PHY_DX6GTR0_RESERVED_7_5_MASK | DDR_PHY_DX6GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX6GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GCR0 @ 0XFD080E00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX7GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX7GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX7GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX7GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX7GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX7GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX7GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX7GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX7GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX7GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX7GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX7GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX7GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX7GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080E00, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX7GCR0_CALBYP_MASK | DDR_PHY_DX7GCR0_MDLEN_MASK | DDR_PHY_DX7GCR0_CODTSHFT_MASK | DDR_PHY_DX7GCR0_DQSDCC_MASK | DDR_PHY_DX7GCR0_RDDLY_MASK | DDR_PHY_DX7GCR0_RESERVED_19_14_MASK | DDR_PHY_DX7GCR0_DQSNSEPDR_MASK | DDR_PHY_DX7GCR0_DQSSEPDR_MASK | DDR_PHY_DX7GCR0_RTTOAL_MASK | DDR_PHY_DX7GCR0_RTTOH_MASK | DDR_PHY_DX7GCR0_CPDRSHFT_MASK | DDR_PHY_DX7GCR0_DQSRPD_MASK | DDR_PHY_DX7GCR0_DQSGPDR_MASK | DDR_PHY_DX7GCR0_RESERVED_4_MASK | DDR_PHY_DX7GCR0_DQSGODT_MASK | DDR_PHY_DX7GCR0_DQSGOE_MASK | DDR_PHY_DX7GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX7GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX7GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GCR1 @ 0XFD080E04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX7GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX7GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX7GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX7GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX7GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX7GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX7GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX7GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX7GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX7GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX7GCR1_DXPDRMODE_MASK | DDR_PHY_DX7GCR1_RESERVED_15_MASK | DDR_PHY_DX7GCR1_QSNSEL_MASK | DDR_PHY_DX7GCR1_QSSEL_MASK | DDR_PHY_DX7GCR1_OEEN_MASK | DDR_PHY_DX7GCR1_PDREN_MASK | DDR_PHY_DX7GCR1_TEEN_MASK | DDR_PHY_DX7GCR1_DSEN_MASK | DDR_PHY_DX7GCR1_DMEN_MASK | DDR_PHY_DX7GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX7GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GCR4 @ 0XFD080E10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX7GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX7GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX7GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX7GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX7GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX7GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX7GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX7GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX7GCR4_RESERVED_31_29_MASK | DDR_PHY_DX7GCR4_DXREFPEN_MASK | DDR_PHY_DX7GCR4_DXREFEEN_MASK | DDR_PHY_DX7GCR4_DXREFSEN_MASK | DDR_PHY_DX7GCR4_RESERVED_24_MASK | DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFESEL_MASK | DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFSSEL_MASK | DDR_PHY_DX7GCR4_RESERVED_7_6_MASK | DDR_PHY_DX7GCR4_DXREFIEN_MASK | DDR_PHY_DX7GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX7GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX7GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GCR5 @ 0XFD080E14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX7GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX7GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX7GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX7GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080E14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX7GCR5_RESERVED_31_MASK | DDR_PHY_DX7GCR5_DXREFISELR3_MASK | DDR_PHY_DX7GCR5_RESERVED_23_MASK | DDR_PHY_DX7GCR5_DXREFISELR2_MASK | DDR_PHY_DX7GCR5_RESERVED_15_MASK | DDR_PHY_DX7GCR5_DXREFISELR1_MASK | DDR_PHY_DX7GCR5_RESERVED_7_MASK | DDR_PHY_DX7GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GCR6 @ 0XFD080E18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX7GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX7GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX7GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX7GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX7GCR6_RESERVED_31_30_MASK | DDR_PHY_DX7GCR6_DXDQVREFR3_MASK | DDR_PHY_DX7GCR6_RESERVED_23_22_MASK | DDR_PHY_DX7GCR6_DXDQVREFR2_MASK | DDR_PHY_DX7GCR6_RESERVED_15_14_MASK | DDR_PHY_DX7GCR6_DXDQVREFR1_MASK | DDR_PHY_DX7GCR6_RESERVED_7_6_MASK | DDR_PHY_DX7GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX7LCDLR2 @ 0XFD080E88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX7LCDLR2_DQSGD                                                     0xa
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU)  
+		RegMask = (DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX7LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT
+			| 0x0000000AU << DDR_PHY_DX7LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7LCDLR2_OFFSET ,0xFFFFFFFFU ,0x0000000AU);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GTR0 @ 0XFD080EC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX7GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX7GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX7GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX7GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX7GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX7GTR0_RESERVED_31_24_MASK | DDR_PHY_DX7GTR0_WDQSL_MASK | DDR_PHY_DX7GTR0_RESERVED_23_20_MASK | DDR_PHY_DX7GTR0_WLSL_MASK | DDR_PHY_DX7GTR0_RESERVED_15_13_MASK | DDR_PHY_DX7GTR0_RESERVED_12_8_MASK | DDR_PHY_DX7GTR0_RESERVED_7_5_MASK | DDR_PHY_DX7GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX7GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GCR0 @ 0XFD080F00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX8GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX8GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX8GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX8GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX8GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX8GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX8GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX8GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX8GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX8GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX8GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX8GCR0_DQSGPDR                                                     0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX8GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX8GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080F00, 0xFFFFFFFFU ,0x40800624U)  
+		RegMask = (DDR_PHY_DX8GCR0_CALBYP_MASK | DDR_PHY_DX8GCR0_MDLEN_MASK | DDR_PHY_DX8GCR0_CODTSHFT_MASK | DDR_PHY_DX8GCR0_DQSDCC_MASK | DDR_PHY_DX8GCR0_RDDLY_MASK | DDR_PHY_DX8GCR0_RESERVED_19_14_MASK | DDR_PHY_DX8GCR0_DQSNSEPDR_MASK | DDR_PHY_DX8GCR0_DQSSEPDR_MASK | DDR_PHY_DX8GCR0_RTTOAL_MASK | DDR_PHY_DX8GCR0_RTTOH_MASK | DDR_PHY_DX8GCR0_CPDRSHFT_MASK | DDR_PHY_DX8GCR0_DQSRPD_MASK | DDR_PHY_DX8GCR0_DQSGPDR_MASK | DDR_PHY_DX8GCR0_RESERVED_4_MASK | DDR_PHY_DX8GCR0_DQSGODT_MASK | DDR_PHY_DX8GCR0_DQSGOE_MASK | DDR_PHY_DX8GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX8GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX8GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_DQSRPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GCR0_OFFSET ,0xFFFFFFFFU ,0x40800624U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GCR1 @ 0XFD080F04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX8GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX8GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX8GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX8GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX8GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX8GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX8GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX8GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX8GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX8GCR1_DQEN                                                        0x0
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U)  
+		RegMask = (DDR_PHY_DX8GCR1_DXPDRMODE_MASK | DDR_PHY_DX8GCR1_RESERVED_15_MASK | DDR_PHY_DX8GCR1_QSNSEL_MASK | DDR_PHY_DX8GCR1_QSSEL_MASK | DDR_PHY_DX8GCR1_OEEN_MASK | DDR_PHY_DX8GCR1_PDREN_MASK | DDR_PHY_DX8GCR1_TEEN_MASK | DDR_PHY_DX8GCR1_DSEN_MASK | DDR_PHY_DX8GCR1_DMEN_MASK | DDR_PHY_DX8GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_DMEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GCR1_OFFSET ,0xFFFFFFFFU ,0x00007F00U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GCR4 @ 0XFD080F10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX8GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX8GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX8GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX8GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX8GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX8GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX8GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX8GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX8GCR4_RESERVED_31_29_MASK | DDR_PHY_DX8GCR4_DXREFPEN_MASK | DDR_PHY_DX8GCR4_DXREFEEN_MASK | DDR_PHY_DX8GCR4_DXREFSEN_MASK | DDR_PHY_DX8GCR4_RESERVED_24_MASK | DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFESEL_MASK | DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFSSEL_MASK | DDR_PHY_DX8GCR4_RESERVED_7_6_MASK | DDR_PHY_DX8GCR4_DXREFIEN_MASK | DDR_PHY_DX8GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX8GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX8GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GCR5 @ 0XFD080F14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX8GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX8GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX8GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX8GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080F14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX8GCR5_RESERVED_31_MASK | DDR_PHY_DX8GCR5_DXREFISELR3_MASK | DDR_PHY_DX8GCR5_RESERVED_23_MASK | DDR_PHY_DX8GCR5_DXREFISELR2_MASK | DDR_PHY_DX8GCR5_RESERVED_15_MASK | DDR_PHY_DX8GCR5_DXREFISELR1_MASK | DDR_PHY_DX8GCR5_RESERVED_7_MASK | DDR_PHY_DX8GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GCR6 @ 0XFD080F18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX8GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX8GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX8GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX8GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX8GCR6_RESERVED_31_30_MASK | DDR_PHY_DX8GCR6_DXDQVREFR3_MASK | DDR_PHY_DX8GCR6_RESERVED_23_22_MASK | DDR_PHY_DX8GCR6_DXDQVREFR2_MASK | DDR_PHY_DX8GCR6_RESERVED_15_14_MASK | DDR_PHY_DX8GCR6_DXDQVREFR1_MASK | DDR_PHY_DX8GCR6_RESERVED_7_6_MASK | DDR_PHY_DX8GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX8LCDLR2 @ 0XFD080F88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX8LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080F88, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX8LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX8LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GTR0 @ 0XFD080FC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX8GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX8GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX8GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX8GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX8GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX8GTR0_RESERVED_31_24_MASK | DDR_PHY_DX8GTR0_WDQSL_MASK | DDR_PHY_DX8GTR0_RESERVED_23_20_MASK | DDR_PHY_DX8GTR0_WLSL_MASK | DDR_PHY_DX8GTR0_RESERVED_15_13_MASK | DDR_PHY_DX8GTR0_RESERVED_12_8_MASK | DDR_PHY_DX8GTR0_RESERVED_7_5_MASK | DDR_PHY_DX8GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX8GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL0DQSCTL @ 0XFD08141C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SL0DQSCTL_DXSR                                                   0x3
+
+		DQS_N Resistor
+		PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-1 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD08141C, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL0DQSCTL_DXSR_MASK | DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL0DXCTL2 @ 0XFD08142C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24                                         0x0
+
+		Configurable Read Data Enable
+		PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN                                                  0x0
+
+		OX Extension during Post-amble
+		PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX                                                 0x0
+
+		OE Extension during Pre-amble
+		PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17                                            0x0
+
+		I/O Assisted Gate Select
+		PSU_DDR_PHY_DX8SL0DXCTL2_IOAG                                                   0x0
+
+		I/O Loopback Select
+		PSU_DDR_PHY_DX8SL0DXCTL2_IOLB                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13                                         0x0
+
+		Low Power Wakeup Threshold
+		PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		Read Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL0DXCTL2_RDBI                                                   0x0
+
+		Write Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL0DXCTL2_WDBI                                                   0x0
+
+		PUB Read FIFO Bypass
+		PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP                                                 0x0
+
+		DATX8 Receive FIFO Read Mode
+		PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE                                                 0x0
+
+		Disables the Read FIFO Reset
+		PSU_DDR_PHY_DX8SL0DXCTL2_DISRST                                                 0x0
+
+		Read DQS Gate I/O Loopback
+		PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0                                             0x0
+
+		DATX8 0-1 DX Control Register 2
+		(OFFSET, MASK, VALUE)      (0XFD08142C, 0xFFFFFFFFU ,0x00001800U)  
+		RegMask = (DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL0DXCTL2_IOAG_MASK | DDR_PHY_DX8SL0DXCTL2_IOLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL0DXCTL2_RDBI_MASK | DDR_PHY_DX8SL0DXCTL2_WDBI_MASK | DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL0DXCTL2_DISRST_MASK | DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL0IOCR @ 0XFD081430

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31                                              0x0
+
+		PVREF_DAC REFSEL range select
+		PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE                                               0x7
+
+		IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM                                                0x0
+
+		DX IO Mode
+		PSU_DDR_PHY_DX8SL0IOCR_DXIOM                                                    0x2
+
+		DX IO Transmitter Mode
+		PSU_DDR_PHY_DX8SL0IOCR_DXTXM                                                    0x0
+
+		DX IO Receiver Mode
+		PSU_DDR_PHY_DX8SL0IOCR_DXRXM                                                    0x0
+
+		DATX8 0-1 I/O Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD081430, 0xFFFFFFFFU ,0x70800000U)  
+		RegMask = (DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL0IOCR_DXIOM_MASK | DDR_PHY_DX8SL0IOCR_DXTXM_MASK | DDR_PHY_DX8SL0IOCR_DXRXM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT
+			| 0x00000007U << DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT
+			| 0x00000002U << DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL0IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL1DQSCTL @ 0XFD08145C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SL1DQSCTL_DXSR                                                   0x3
+
+		DQS_N Resistor
+		PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-1 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD08145C, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL1DQSCTL_DXSR_MASK | DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL1DXCTL2 @ 0XFD08146C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24                                         0x0
+
+		Configurable Read Data Enable
+		PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN                                                  0x0
+
+		OX Extension during Post-amble
+		PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX                                                 0x0
+
+		OE Extension during Pre-amble
+		PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17                                            0x0
+
+		I/O Assisted Gate Select
+		PSU_DDR_PHY_DX8SL1DXCTL2_IOAG                                                   0x0
+
+		I/O Loopback Select
+		PSU_DDR_PHY_DX8SL1DXCTL2_IOLB                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13                                         0x0
+
+		Low Power Wakeup Threshold
+		PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		Read Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL1DXCTL2_RDBI                                                   0x0
+
+		Write Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL1DXCTL2_WDBI                                                   0x0
+
+		PUB Read FIFO Bypass
+		PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP                                                 0x0
+
+		DATX8 Receive FIFO Read Mode
+		PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE                                                 0x0
+
+		Disables the Read FIFO Reset
+		PSU_DDR_PHY_DX8SL1DXCTL2_DISRST                                                 0x0
+
+		Read DQS Gate I/O Loopback
+		PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0                                             0x0
+
+		DATX8 0-1 DX Control Register 2
+		(OFFSET, MASK, VALUE)      (0XFD08146C, 0xFFFFFFFFU ,0x00001800U)  
+		RegMask = (DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL1DXCTL2_IOAG_MASK | DDR_PHY_DX8SL1DXCTL2_IOLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL1DXCTL2_RDBI_MASK | DDR_PHY_DX8SL1DXCTL2_WDBI_MASK | DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL1DXCTL2_DISRST_MASK | DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL1IOCR @ 0XFD081470

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31                                              0x0
+
+		PVREF_DAC REFSEL range select
+		PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE                                               0x7
+
+		IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM                                                0x0
+
+		DX IO Mode
+		PSU_DDR_PHY_DX8SL1IOCR_DXIOM                                                    0x2
+
+		DX IO Transmitter Mode
+		PSU_DDR_PHY_DX8SL1IOCR_DXTXM                                                    0x0
+
+		DX IO Receiver Mode
+		PSU_DDR_PHY_DX8SL1IOCR_DXRXM                                                    0x0
+
+		DATX8 0-1 I/O Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD081470, 0xFFFFFFFFU ,0x70800000U)  
+		RegMask = (DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL1IOCR_DXIOM_MASK | DDR_PHY_DX8SL1IOCR_DXTXM_MASK | DDR_PHY_DX8SL1IOCR_DXRXM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT
+			| 0x00000007U << DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT
+			| 0x00000002U << DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL1IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL2DQSCTL @ 0XFD08149C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SL2DQSCTL_DXSR                                                   0x3
+
+		DQS_N Resistor
+		PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-1 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD08149C, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL2DQSCTL_DXSR_MASK | DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL2DXCTL2 @ 0XFD0814AC

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24                                         0x0
+
+		Configurable Read Data Enable
+		PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN                                                  0x0
+
+		OX Extension during Post-amble
+		PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX                                                 0x0
+
+		OE Extension during Pre-amble
+		PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17                                            0x0
+
+		I/O Assisted Gate Select
+		PSU_DDR_PHY_DX8SL2DXCTL2_IOAG                                                   0x0
+
+		I/O Loopback Select
+		PSU_DDR_PHY_DX8SL2DXCTL2_IOLB                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13                                         0x0
+
+		Low Power Wakeup Threshold
+		PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		Read Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL2DXCTL2_RDBI                                                   0x0
+
+		Write Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL2DXCTL2_WDBI                                                   0x0
+
+		PUB Read FIFO Bypass
+		PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP                                                 0x0
+
+		DATX8 Receive FIFO Read Mode
+		PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE                                                 0x0
+
+		Disables the Read FIFO Reset
+		PSU_DDR_PHY_DX8SL2DXCTL2_DISRST                                                 0x0
+
+		Read DQS Gate I/O Loopback
+		PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0                                             0x0
+
+		DATX8 0-1 DX Control Register 2
+		(OFFSET, MASK, VALUE)      (0XFD0814AC, 0xFFFFFFFFU ,0x00001800U)  
+		RegMask = (DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL2DXCTL2_IOAG_MASK | DDR_PHY_DX8SL2DXCTL2_IOLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL2DXCTL2_RDBI_MASK | DDR_PHY_DX8SL2DXCTL2_WDBI_MASK | DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL2DXCTL2_DISRST_MASK | DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL2IOCR @ 0XFD0814B0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31                                              0x0
+
+		PVREF_DAC REFSEL range select
+		PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE                                               0x7
+
+		IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM                                                0x0
+
+		DX IO Mode
+		PSU_DDR_PHY_DX8SL2IOCR_DXIOM                                                    0x2
+
+		DX IO Transmitter Mode
+		PSU_DDR_PHY_DX8SL2IOCR_DXTXM                                                    0x0
+
+		DX IO Receiver Mode
+		PSU_DDR_PHY_DX8SL2IOCR_DXRXM                                                    0x0
+
+		DATX8 0-1 I/O Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U)  
+		RegMask = (DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL2IOCR_DXIOM_MASK | DDR_PHY_DX8SL2IOCR_DXTXM_MASK | DDR_PHY_DX8SL2IOCR_DXRXM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT
+			| 0x00000007U << DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT
+			| 0x00000002U << DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL2IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL3DQSCTL @ 0XFD0814DC

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SL3DQSCTL_DXSR                                                   0x3
+
+		DQS_N Resistor
+		PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-1 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0814DC, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL3DQSCTL_DXSR_MASK | DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL3DXCTL2 @ 0XFD0814EC

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24                                         0x0
+
+		Configurable Read Data Enable
+		PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN                                                  0x0
+
+		OX Extension during Post-amble
+		PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX                                                 0x0
+
+		OE Extension during Pre-amble
+		PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17                                            0x0
+
+		I/O Assisted Gate Select
+		PSU_DDR_PHY_DX8SL3DXCTL2_IOAG                                                   0x0
+
+		I/O Loopback Select
+		PSU_DDR_PHY_DX8SL3DXCTL2_IOLB                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13                                         0x0
+
+		Low Power Wakeup Threshold
+		PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		Read Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL3DXCTL2_RDBI                                                   0x0
+
+		Write Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL3DXCTL2_WDBI                                                   0x0
+
+		PUB Read FIFO Bypass
+		PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP                                                 0x0
+
+		DATX8 Receive FIFO Read Mode
+		PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE                                                 0x0
+
+		Disables the Read FIFO Reset
+		PSU_DDR_PHY_DX8SL3DXCTL2_DISRST                                                 0x0
+
+		Read DQS Gate I/O Loopback
+		PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0                                             0x0
+
+		DATX8 0-1 DX Control Register 2
+		(OFFSET, MASK, VALUE)      (0XFD0814EC, 0xFFFFFFFFU ,0x00001800U)  
+		RegMask = (DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL3DXCTL2_IOAG_MASK | DDR_PHY_DX8SL3DXCTL2_IOLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL3DXCTL2_RDBI_MASK | DDR_PHY_DX8SL3DXCTL2_WDBI_MASK | DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL3DXCTL2_DISRST_MASK | DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL3IOCR @ 0XFD0814F0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31                                              0x0
+
+		PVREF_DAC REFSEL range select
+		PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE                                               0x7
+
+		IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM                                                0x0
+
+		DX IO Mode
+		PSU_DDR_PHY_DX8SL3IOCR_DXIOM                                                    0x2
+
+		DX IO Transmitter Mode
+		PSU_DDR_PHY_DX8SL3IOCR_DXTXM                                                    0x0
+
+		DX IO Receiver Mode
+		PSU_DDR_PHY_DX8SL3IOCR_DXRXM                                                    0x0
+
+		DATX8 0-1 I/O Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U)  
+		RegMask = (DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL3IOCR_DXIOM_MASK | DDR_PHY_DX8SL3IOCR_DXTXM_MASK | DDR_PHY_DX8SL3IOCR_DXRXM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT
+			| 0x00000007U << DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT
+			| 0x00000002U << DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL3IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL4DQSCTL @ 0XFD08151C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SL4DQSCTL_DXSR                                                   0x3
+
+		DQS_N Resistor
+		PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-1 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD08151C, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL4DQSCTL_DXSR_MASK | DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL4DXCTL2 @ 0XFD08152C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24                                         0x0
+
+		Configurable Read Data Enable
+		PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN                                                  0x0
+
+		OX Extension during Post-amble
+		PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX                                                 0x0
+
+		OE Extension during Pre-amble
+		PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17                                            0x0
+
+		I/O Assisted Gate Select
+		PSU_DDR_PHY_DX8SL4DXCTL2_IOAG                                                   0x0
+
+		I/O Loopback Select
+		PSU_DDR_PHY_DX8SL4DXCTL2_IOLB                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13                                         0x0
+
+		Low Power Wakeup Threshold
+		PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		Read Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL4DXCTL2_RDBI                                                   0x0
+
+		Write Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL4DXCTL2_WDBI                                                   0x0
+
+		PUB Read FIFO Bypass
+		PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP                                                 0x0
+
+		DATX8 Receive FIFO Read Mode
+		PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE                                                 0x0
+
+		Disables the Read FIFO Reset
+		PSU_DDR_PHY_DX8SL4DXCTL2_DISRST                                                 0x0
+
+		Read DQS Gate I/O Loopback
+		PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0                                             0x0
+
+		DATX8 0-1 DX Control Register 2
+		(OFFSET, MASK, VALUE)      (0XFD08152C, 0xFFFFFFFFU ,0x00001800U)  
+		RegMask = (DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL4DXCTL2_IOAG_MASK | DDR_PHY_DX8SL4DXCTL2_IOLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL4DXCTL2_RDBI_MASK | DDR_PHY_DX8SL4DXCTL2_WDBI_MASK | DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL4DXCTL2_DISRST_MASK | DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL4IOCR @ 0XFD081530

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31                                              0x0
+
+		PVREF_DAC REFSEL range select
+		PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE                                               0x7
+
+		IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM                                                0x0
+
+		DX IO Mode
+		PSU_DDR_PHY_DX8SL4IOCR_DXIOM                                                    0x2
+
+		DX IO Transmitter Mode
+		PSU_DDR_PHY_DX8SL4IOCR_DXTXM                                                    0x0
+
+		DX IO Receiver Mode
+		PSU_DDR_PHY_DX8SL4IOCR_DXRXM                                                    0x0
+
+		DATX8 0-1 I/O Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD081530, 0xFFFFFFFFU ,0x70800000U)  
+		RegMask = (DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL4IOCR_DXIOM_MASK | DDR_PHY_DX8SL4IOCR_DXTXM_MASK | DDR_PHY_DX8SL4IOCR_DXRXM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT
+			| 0x00000007U << DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT
+			| 0x00000002U << DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL4IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SLbDQSCTL @ 0XFD0817DC

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SLBDQSCTL_DXSR                                                   0x3
+
+		DQS# Resistor
+		PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-8 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK | DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SLBDQSCTL_DXSR_MASK | DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK | DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SLBDQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : PIR @ 0XFD080004

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_PIR_RESERVED_31                                                     0x0
+
+		Impedance Calibration Bypass
+		PSU_DDR_PHY_PIR_ZCALBYP                                                         0x0
+
+		Digital Delay Line (DDL) Calibration Pause
+		PSU_DDR_PHY_PIR_DCALPSE                                                         0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_PIR_RESERVED_28_21                                                  0x0
+
+		Write DQS2DQ Training
+		PSU_DDR_PHY_PIR_DQS2DQ                                                          0x0
+
+		RDIMM Initialization
+		PSU_DDR_PHY_PIR_RDIMMINIT                                                       0x0
+
+		Controller DRAM Initialization
+		PSU_DDR_PHY_PIR_CTLDINIT                                                        0x1
+
+		VREF Training
+		PSU_DDR_PHY_PIR_VREF                                                            0x0
+
+		Static Read Training
+		PSU_DDR_PHY_PIR_SRD                                                             0x0
+
+		Write Data Eye Training
+		PSU_DDR_PHY_PIR_WREYE                                                           0x0
+
+		Read Data Eye Training
+		PSU_DDR_PHY_PIR_RDEYE                                                           0x0
+
+		Write Data Bit Deskew
+		PSU_DDR_PHY_PIR_WRDSKW                                                          0x0
+
+		Read Data Bit Deskew
+		PSU_DDR_PHY_PIR_RDDSKW                                                          0x0
+
+		Write Leveling Adjust
+		PSU_DDR_PHY_PIR_WLADJ                                                           0x0
+
+		Read DQS Gate Training
+		PSU_DDR_PHY_PIR_QSGATE                                                          0x0
+
+		Write Leveling
+		PSU_DDR_PHY_PIR_WL                                                              0x0
+
+		DRAM Initialization
+		PSU_DDR_PHY_PIR_DRAMINIT                                                        0x0
+
+		DRAM Reset (DDR3/DDR4/LPDDR4 Only)
+		PSU_DDR_PHY_PIR_DRAMRST                                                         0x0
+
+		PHY Reset
+		PSU_DDR_PHY_PIR_PHYRST                                                          0x1
+
+		Digital Delay Line (DDL) Calibration
+		PSU_DDR_PHY_PIR_DCAL                                                            0x1
+
+		PLL Initialiazation
+		PSU_DDR_PHY_PIR_PLLINIT                                                         0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_PIR_RESERVED_3                                                      0x0
+
+		CA Training
+		PSU_DDR_PHY_PIR_CA                                                              0x0
+
+		Impedance Calibration
+		PSU_DDR_PHY_PIR_ZCAL                                                            0x1
+
+		Initialization Trigger
+		PSU_DDR_PHY_PIR_INIT                                                            0x1
+
+		PHY Initialization Register
+		(OFFSET, MASK, VALUE)      (0XFD080004, 0xFFFFFFFFU ,0x00040073U)  
+		RegMask = (DDR_PHY_PIR_RESERVED_31_MASK | DDR_PHY_PIR_ZCALBYP_MASK | DDR_PHY_PIR_DCALPSE_MASK | DDR_PHY_PIR_RESERVED_28_21_MASK | DDR_PHY_PIR_DQS2DQ_MASK | DDR_PHY_PIR_RDIMMINIT_MASK | DDR_PHY_PIR_CTLDINIT_MASK | DDR_PHY_PIR_VREF_MASK | DDR_PHY_PIR_SRD_MASK | DDR_PHY_PIR_WREYE_MASK | DDR_PHY_PIR_RDEYE_MASK | DDR_PHY_PIR_WRDSKW_MASK | DDR_PHY_PIR_RDDSKW_MASK | DDR_PHY_PIR_WLADJ_MASK | DDR_PHY_PIR_QSGATE_MASK | DDR_PHY_PIR_WL_MASK | DDR_PHY_PIR_DRAMINIT_MASK | DDR_PHY_PIR_DRAMRST_MASK | DDR_PHY_PIR_PHYRST_MASK | DDR_PHY_PIR_DCAL_MASK | DDR_PHY_PIR_PLLINIT_MASK | DDR_PHY_PIR_RESERVED_3_MASK | DDR_PHY_PIR_CA_MASK | DDR_PHY_PIR_ZCAL_MASK | DDR_PHY_PIR_INIT_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_PIR_RESERVED_31_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_ZCALBYP_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_DCALPSE_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_RESERVED_28_21_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_DQS2DQ_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_RDIMMINIT_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_CTLDINIT_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_VREF_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_SRD_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_WREYE_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_RDEYE_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_WRDSKW_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_RDDSKW_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_WLADJ_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_QSGATE_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_WL_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_DRAMINIT_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_DRAMRST_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_PHYRST_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_DCAL_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_PLLINIT_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_RESERVED_3_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_CA_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_ZCAL_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_INIT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PIR_OFFSET ,0xFFFFFFFFU ,0x00040073U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_mio_init_data() {
+		// : MIO PROGRAMMING
+		/*Register : MIO_PIN_0 @ 0XFF180000

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_0_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_0_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[0]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_0_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_0_L3_SEL                                                   0
+
+		Configures MIO Pin 0 peripheral interface mapping. S
+		(OFFSET, MASK, VALUE)      (0XFF180000, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_0_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_1 @ 0XFF180004

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
+		us)
+		PSU_IOU_SLCR_MIO_PIN_1_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_1_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[1]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_1_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)
+		PSU_IOU_SLCR_MIO_PIN_1_L3_SEL                                                   0
+
+		Configures MIO Pin 1 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180004, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_1_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_2 @ 0XFF180008

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
+		PSU_IOU_SLCR_MIO_PIN_2_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_2_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[2]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_2_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_2_L3_SEL                                                   0
+
+		Configures MIO Pin 2 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180008, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_2_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_3 @ 0XFF18000C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
+		PSU_IOU_SLCR_MIO_PIN_3_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_3_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[3]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_3_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_3_L3_SEL                                                   0
+
+		Configures MIO Pin 3 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18000C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_3_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_4 @ 0XFF180010

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
+		us)
+		PSU_IOU_SLCR_MIO_PIN_4_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_4_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[4]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_4_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_4_L3_SEL                                                   0
+
+		Configures MIO Pin 4 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180010, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_4_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_5 @ 0XFF180014

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)
+		PSU_IOU_SLCR_MIO_PIN_5_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_5_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[5]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_5_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_5_L3_SEL                                                   0
+
+		Configures MIO Pin 5 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180014, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_5_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_6 @ 0XFF180018

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
+		PSU_IOU_SLCR_MIO_PIN_6_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_6_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[6]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_6_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
+		sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
+		Output, tracedq[4]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_6_L3_SEL                                                   0
+
+		Configures MIO Pin 6 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180018, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_6_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_7 @ 0XFF18001C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)
+		PSU_IOU_SLCR_MIO_PIN_7_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_7_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[7]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_7_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= 
+		tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, 
+		racedq[5]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_7_L3_SEL                                                   0
+
+		Configures MIO Pin 7 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18001C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_7_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_8 @ 0XFF180020

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[0]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_8_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_8_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[8]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_8_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
+		, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
+		ce Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_8_L3_SEL                                                   0
+
+		Configures MIO Pin 8 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180020, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_8_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_9 @ 0XFF180024

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[1]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_9_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_9_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[9]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_9_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, 
+		utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
+		RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_9_L3_SEL                                                   0
+
+		Configures MIO Pin 9 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180024, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_9_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_10 @ 0XFF180028

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[2]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_10_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_10_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[10]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_10_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_10_L3_SEL                                                  0
+
+		Configures MIO Pin 10 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180028, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_10_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_11 @ 0XFF18002C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[3]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_11_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_11_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[11]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_11_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_11_L3_SEL                                                  0
+
+		Configures MIO Pin 11 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18002C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_11_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_12 @ 0XFF180030

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
+		PSU_IOU_SLCR_MIO_PIN_12_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		
+		PSU_IOU_SLCR_MIO_PIN_12_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[12]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_12_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
+		ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
+		dq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_12_L3_SEL                                                  0
+
+		Configures MIO Pin 12 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180030, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_12_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_13 @ 0XFF180034

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_13_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_13_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_13_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
+		out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
+		bus)
+		PSU_IOU_SLCR_MIO_PIN_13_L3_SEL                                                  0
+
+		Configures MIO Pin 13 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180034, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_13_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_14 @ 0XFF180038

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_14_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)
+		PSU_IOU_SLCR_MIO_PIN_14_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_14_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
+		n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_14_L3_SEL                                                  2
+
+		Configures MIO Pin 14 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180038, 0x000000FEU ,0x00000040U)  
+		RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_14_OFFSET ,0x000000FEU ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_15 @ 0XFF18003C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_15_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)
+		PSU_IOU_SLCR_MIO_PIN_15_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_15_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
+		0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
+		l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_15_L3_SEL                                                  2
+
+		Configures MIO Pin 15 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18003C, 0x000000FEU ,0x00000040U)  
+		RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_15_OFFSET ,0x000000FEU ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_16 @ 0XFF180040

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_16_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_16_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_16_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_16_L3_SEL                                                  2
+
+		Configures MIO Pin 16 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180040, 0x000000FEU ,0x00000040U)  
+		RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_16_OFFSET ,0x000000FEU ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_17 @ 0XFF180044

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_17_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_17_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_17_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_17_L3_SEL                                                  2
+
+		Configures MIO Pin 17 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180044, 0x000000FEU ,0x00000040U)  
+		RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_17_OFFSET ,0x000000FEU ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_18 @ 0XFF180048

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_18_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_18_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_18_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_18_L3_SEL                                                  6
+
+		Configures MIO Pin 18 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180048, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_18_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_19 @ 0XFF18004C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_19_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_19_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_19_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_19_L3_SEL                                                  6
+
+		Configures MIO Pin 19 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18004C, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_19_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_20 @ 0XFF180050

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_20_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_20_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_20_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
+		c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_20_L3_SEL                                                  6
+
+		Configures MIO Pin 20 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180050, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_20_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_21 @ 0XFF180054

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_21_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_21_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 
+		= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_21_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- 
+		UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_21_L3_SEL                                                  6
+
+		Configures MIO Pin 21 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180054, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_21_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_22 @ 0XFF180058

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_22_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)
+		PSU_IOU_SLCR_MIO_PIN_22_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
+		(Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_22_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed
+		PSU_IOU_SLCR_MIO_PIN_22_L3_SEL                                                  0
+
+		Configures MIO Pin 22 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180058, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_22_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_23 @ 0XFF18005C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_23_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_23_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
+		23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
+		
+		PSU_IOU_SLCR_MIO_PIN_23_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_23_L3_SEL                                                  0
+
+		Configures MIO Pin 23 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18005C, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_23_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_24 @ 0XFF180060

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_24_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_24_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
+		scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
+		 Tamper)
+		PSU_IOU_SLCR_MIO_PIN_24_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
+		Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_24_L3_SEL                                                  1
+
+		Configures MIO Pin 24 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180060, 0x000000FEU ,0x00000020U)  
+		RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_24_OFFSET ,0x000000FEU ,0x00000020U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_25 @ 0XFF180064

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_25_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)
+		PSU_IOU_SLCR_MIO_PIN_25_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
+		test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
+		U Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_25_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform 
+		lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_25_L3_SEL                                                  1
+
+		Configures MIO Pin 25 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180064, 0x000000FEU ,0x00000020U)  
+		RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_25_OFFSET ,0x000000FEU ,0x00000020U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_26 @ 0XFF180068

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_26_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_26_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_26_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_26_L3_SEL                                                  0
+
+		Configures MIO Pin 26 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180068, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_27 @ 0XFF18006C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_27_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_27_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_27_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)
+		PSU_IOU_SLCR_MIO_PIN_27_L3_SEL                                                  0
+
+		Configures MIO Pin 27 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18006C, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_28 @ 0XFF180070

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_28_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_28_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_28_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_28_L3_SEL                                                  0
+
+		Configures MIO Pin 28 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180070, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_29 @ 0XFF180074

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_29_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_29_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_29_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_29_L3_SEL                                                  0
+
+		Configures MIO Pin 29 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180074, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_30 @ 0XFF180078

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_30_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_30_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_30_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
+		 (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
+		 tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_30_L3_SEL                                                  0
+
+		Configures MIO Pin 30 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180078, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_31 @ 0XFF18007C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_31_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_31_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_31_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
+		_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
+		ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_31_L3_SEL                                                  0
+
+		Configures MIO Pin 31 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18007C, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_31_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_32 @ 0XFF180080

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_32_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		
+		PSU_IOU_SLCR_MIO_PIN_32_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
+		an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_32_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
+		_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= 
+		race, Output, tracedq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_32_L3_SEL                                                  0
+
+		Configures MIO Pin 32 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180080, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_32_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_33 @ 0XFF180084

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_33_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_33_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
+		an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_33_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
+		c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
+		[11]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_33_L3_SEL                                                  0
+
+		Configures MIO Pin 33 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180084, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_33_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_34 @ 0XFF180088

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_34_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_34_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
+		an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
+		ut, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_34_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
+		 Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
+		rt Databus)
+		PSU_IOU_SLCR_MIO_PIN_34_L3_SEL                                                  0
+
+		Configures MIO Pin 34 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180088, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_34_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_35 @ 0XFF18008C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_35_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_35_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
+		an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_35_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
+		Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- 
+		UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_35_L3_SEL                                                  0
+
+		Configures MIO Pin 35 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18008C, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_35_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_36 @ 0XFF180090

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_36_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_36_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
+		an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
+		ut, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_36_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_36_L3_SEL                                                  0
+
+		Configures MIO Pin 36 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180090, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_36_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_37 @ 0XFF180094

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_37_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_37_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
+		an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_37_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_37_L3_SEL                                                  0
+
+		Configures MIO Pin 37 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180094, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_37_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_38 @ 0XFF180098

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_38_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_38_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_38_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
+		k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
+		(Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_38_L3_SEL                                                  0
+
+		Configures MIO Pin 38 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180098, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_38_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_39 @ 0XFF18009C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_39_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_39_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
+		[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_39_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
+		_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
+		Control Signal)
+		PSU_IOU_SLCR_MIO_PIN_39_L3_SEL                                                  0
+
+		Configures MIO Pin 39 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18009C, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_39_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_40 @ 0XFF1800A0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_40_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_40_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_40_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
+		in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_40_L3_SEL                                                  0
+
+		Configures MIO Pin 40 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A0, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_40_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_41 @ 0XFF1800A4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_41_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_41_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_41_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
+		]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
+		ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_41_L3_SEL                                                  0
+
+		Configures MIO Pin 41 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A4, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_41_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_42 @ 0XFF1800A8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_42_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_42_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_42_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_42_L3_SEL                                                  0
+
+		Configures MIO Pin 42 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A8, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_42_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_43 @ 0XFF1800AC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_43_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_43_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_43_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
+		i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_43_L3_SEL                                                  0
+
+		Configures MIO Pin 43 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800AC, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_43_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_44 @ 0XFF1800B0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_44_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
+		i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L3_SEL                                                  0
+
+		Configures MIO Pin 44 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B0, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_44_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_45 @ 0XFF1800B4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_45_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L3_SEL                                                  0
+
+		Configures MIO Pin 45 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B4, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_45_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_46 @ 0XFF1800B8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_46_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
+		0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L3_SEL                                                  0
+
+		Configures MIO Pin 46 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B8, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_46_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_47 @ 0XFF1800BC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_47_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L3_SEL                                                  0
+
+		Configures MIO Pin 47 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800BC, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_47_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_48 @ 0XFF1800C0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_48_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_48_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_48_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
+		ed
+		PSU_IOU_SLCR_MIO_PIN_48_L3_SEL                                                  0
+
+		Configures MIO Pin 48 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C0, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_48_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_49 @ 0XFF1800C4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_49_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
+		bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L3_SEL                                                  0
+
+		Configures MIO Pin 49 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C4, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_49_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_50 @ 0XFF1800C8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+		PSU_IOU_SLCR_MIO_PIN_50_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
+		d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
+		clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L3_SEL                                                  0
+
+		Configures MIO Pin 50 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C8, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_50_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_51 @ 0XFF1800CC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+		PSU_IOU_SLCR_MIO_PIN_51_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
+		t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
+		serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L3_SEL                                                  0
+
+		Configures MIO Pin 51 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800CC, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_51_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_52 @ 0XFF1800D0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_52_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L3_SEL                                                  0
+
+		Configures MIO Pin 52 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D0, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_52_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_53 @ 0XFF1800D4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_53_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
+		PSU_IOU_SLCR_MIO_PIN_53_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_53_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)
+		PSU_IOU_SLCR_MIO_PIN_53_L3_SEL                                                  0
+
+		Configures MIO Pin 53 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D4, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_53_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_54 @ 0XFF1800D8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_54_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[2]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_54_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_54_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_54_L3_SEL                                                  0
+
+		Configures MIO Pin 54 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D8, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_54_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_55 @ 0XFF1800DC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_55_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
+		PSU_IOU_SLCR_MIO_PIN_55_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_55_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_55_L3_SEL                                                  0
+
+		Configures MIO Pin 55 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800DC, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_55_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_56 @ 0XFF1800E0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_56_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[0]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_56_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_56_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_56_L3_SEL                                                  0
+
+		Configures MIO Pin 56 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E0, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_56_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_57 @ 0XFF1800E4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_57_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[1]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_57_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_57_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_57_L3_SEL                                                  0
+
+		Configures MIO Pin 57 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E4, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_57_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_58 @ 0XFF1800E8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_58_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
+		PSU_IOU_SLCR_MIO_PIN_58_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_58_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_58_L3_SEL                                                  0
+
+		Configures MIO Pin 58 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E8, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_58_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_59 @ 0XFF1800EC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_59_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[3]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_59_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_59_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)
+		PSU_IOU_SLCR_MIO_PIN_59_L3_SEL                                                  0
+
+		Configures MIO Pin 59 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800EC, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_59_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_60 @ 0XFF1800F0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_60_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[4]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_60_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_60_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_60_L3_SEL                                                  0
+
+		Configures MIO Pin 60 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F0, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_60_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_61 @ 0XFF1800F4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_61_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[5]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_61_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_61_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_61_L3_SEL                                                  0
+
+		Configures MIO Pin 61 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F4, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_61_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_62 @ 0XFF1800F8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_62_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[6]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_62_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_62_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_62_L3_SEL                                                  0
+
+		Configures MIO Pin 62 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F8, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_62_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_63 @ 0XFF1800FC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_63_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[7]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_63_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_63_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_63_L3_SEL                                                  0
+
+		Configures MIO Pin 63 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800FC, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_63_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_64 @ 0XFF180100

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_64_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_64_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_64_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
+		i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 trace, Output, tracedq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_64_L3_SEL                                                  0
+
+		Configures MIO Pin 64 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180100, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_64_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_65 @ 0XFF180104

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_65_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
+		PSU_IOU_SLCR_MIO_PIN_65_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_65_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
+		dq[11]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_65_L3_SEL                                                  0
+
+		Configures MIO Pin 65 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180104, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_65_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_66 @ 0XFF180108

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_66_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[2]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_66_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_66_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
+		2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
+		Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_66_L3_SEL                                                  0
+
+		Configures MIO Pin 66 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180108, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_66_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_67 @ 0XFF18010C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_67_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
+		PSU_IOU_SLCR_MIO_PIN_67_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_67_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_67_L3_SEL                                                  0
+
+		Configures MIO Pin 67 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18010C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_67_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_68 @ 0XFF180110

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_68_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[0]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_68_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_68_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_68_L3_SEL                                                  0
+
+		Configures MIO Pin 68 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180110, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_68_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_69 @ 0XFF180114

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_69_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[1]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_69_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_69_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_69_L3_SEL                                                  0
+
+		Configures MIO Pin 69 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180114, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_69_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_70 @ 0XFF180118

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_70_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
+		PSU_IOU_SLCR_MIO_PIN_70_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_70_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed
+		PSU_IOU_SLCR_MIO_PIN_70_L3_SEL                                                  0
+
+		Configures MIO Pin 70 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180118, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_70_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_71 @ 0XFF18011C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_71_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[3]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_71_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_71_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_71_L3_SEL                                                  0
+
+		Configures MIO Pin 71 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18011C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_71_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_72 @ 0XFF180120

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_72_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[4]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_72_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_72_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
+		t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_72_L3_SEL                                                  0
+
+		Configures MIO Pin 72 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180120, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_72_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_73 @ 0XFF180124

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_73_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[5]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_73_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_73_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_73_L3_SEL                                                  0
+
+		Configures MIO Pin 73 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180124, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_73_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_74 @ 0XFF180128

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_74_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[6]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_74_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_74_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_74_L3_SEL                                                  0
+
+		Configures MIO Pin 74 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180128, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_74_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_75 @ 0XFF18012C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_75_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[7]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_75_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
+		d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_75_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_75_L3_SEL                                                  0
+
+		Configures MIO Pin 75 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18012C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_75_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_76 @ 0XFF180130

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
+		_clk_out- (SDSDIO clock) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
+		 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L3_SEL                                                  6
+
+		Configures MIO Pin 76 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180130, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_76_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_77 @ 0XFF180134

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
+		O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
+		t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L3_SEL                                                  6
+
+		Configures MIO Pin 77 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180134, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_77_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI0 @ 0XFF180204

+
+		Master Tri-state Enable for pin 0, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI                                            0
+
+		Master Tri-state Enable for pin 1, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI                                            0
+
+		Master Tri-state Enable for pin 2, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI                                            0
+
+		Master Tri-state Enable for pin 3, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI                                            0
+
+		Master Tri-state Enable for pin 4, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI                                            0
+
+		Master Tri-state Enable for pin 5, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI                                            0
+
+		Master Tri-state Enable for pin 6, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI                                            0
+
+		Master Tri-state Enable for pin 7, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI                                            0
+
+		Master Tri-state Enable for pin 8, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI                                            0
+
+		Master Tri-state Enable for pin 9, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI                                            0
+
+		Master Tri-state Enable for pin 10, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI                                            0
+
+		Master Tri-state Enable for pin 11, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI                                            0
+
+		Master Tri-state Enable for pin 12, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI                                            0
+
+		Master Tri-state Enable for pin 13, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI                                            0
+
+		Master Tri-state Enable for pin 14, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI                                            0
+
+		Master Tri-state Enable for pin 15, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI                                            0
+
+		Master Tri-state Enable for pin 16, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI                                            0
+
+		Master Tri-state Enable for pin 17, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI                                            0
+
+		Master Tri-state Enable for pin 18, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI                                            1
+
+		Master Tri-state Enable for pin 19, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI                                            0
+
+		Master Tri-state Enable for pin 20, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI                                            0
+
+		Master Tri-state Enable for pin 21, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI                                            1
+
+		Master Tri-state Enable for pin 22, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI                                            0
+
+		Master Tri-state Enable for pin 23, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI                                            0
+
+		Master Tri-state Enable for pin 24, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI                                            0
+
+		Master Tri-state Enable for pin 25, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI                                            1
+
+		Master Tri-state Enable for pin 26, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI                                            1
+
+		Master Tri-state Enable for pin 27, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI                                            0
+
+		Master Tri-state Enable for pin 28, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI                                            0
+
+		Master Tri-state Enable for pin 29, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI                                            0
+
+		Master Tri-state Enable for pin 30, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI                                            0
+
+		Master Tri-state Enable for pin 31, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI                                            0
+
+		MIO pin Tri-state Enables, 31:0
+		(OFFSET, MASK, VALUE)      (0XFF180204, 0xFFFFFFFFU ,0x06240000U)  
+		RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x06240000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI1 @ 0XFF180208

+
+		Master Tri-state Enable for pin 32, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI                                            0
+
+		Master Tri-state Enable for pin 33, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI                                            0
+
+		Master Tri-state Enable for pin 34, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI                                            0
+
+		Master Tri-state Enable for pin 35, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI                                            0
+
+		Master Tri-state Enable for pin 36, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI                                            0
+
+		Master Tri-state Enable for pin 37, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI                                            0
+
+		Master Tri-state Enable for pin 38, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI                                            0
+
+		Master Tri-state Enable for pin 39, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI                                            0
+
+		Master Tri-state Enable for pin 40, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI                                            0
+
+		Master Tri-state Enable for pin 41, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI                                            0
+
+		Master Tri-state Enable for pin 42, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI                                            0
+
+		Master Tri-state Enable for pin 43, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI                                            0
+
+		Master Tri-state Enable for pin 44, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI                                            1
+
+		Master Tri-state Enable for pin 45, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI                                            1
+
+		Master Tri-state Enable for pin 46, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI                                            0
+
+		Master Tri-state Enable for pin 47, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI                                            0
+
+		Master Tri-state Enable for pin 48, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI                                            0
+
+		Master Tri-state Enable for pin 49, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI                                            0
+
+		Master Tri-state Enable for pin 50, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI                                            0
+
+		Master Tri-state Enable for pin 51, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI                                            0
+
+		Master Tri-state Enable for pin 52, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI                                            1
+
+		Master Tri-state Enable for pin 53, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI                                            1
+
+		Master Tri-state Enable for pin 54, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI                                            0
+
+		Master Tri-state Enable for pin 55, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI                                            1
+
+		Master Tri-state Enable for pin 56, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI                                            0
+
+		Master Tri-state Enable for pin 57, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI                                            0
+
+		Master Tri-state Enable for pin 58, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI                                            0
+
+		Master Tri-state Enable for pin 59, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI                                            0
+
+		Master Tri-state Enable for pin 60, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI                                            0
+
+		Master Tri-state Enable for pin 61, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI                                            0
+
+		Master Tri-state Enable for pin 62, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI                                            0
+
+		Master Tri-state Enable for pin 63, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI                                            0
+
+		MIO pin Tri-state Enables, 63:32
+		(OFFSET, MASK, VALUE)      (0XFF180208, 0xFFFFFFFFU ,0x00B03000U)  
+		RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI1_OFFSET ,0xFFFFFFFFU ,0x00B03000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI2 @ 0XFF18020C

+
+		Master Tri-state Enable for pin 64, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI                                            0
+
+		Master Tri-state Enable for pin 65, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI                                            0
+
+		Master Tri-state Enable for pin 66, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI                                            0
+
+		Master Tri-state Enable for pin 67, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI                                            0
+
+		Master Tri-state Enable for pin 68, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI                                            0
+
+		Master Tri-state Enable for pin 69, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI                                            0
+
+		Master Tri-state Enable for pin 70, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI                                            1
+
+		Master Tri-state Enable for pin 71, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI                                            1
+
+		Master Tri-state Enable for pin 72, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI                                            1
+
+		Master Tri-state Enable for pin 73, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI                                            1
+
+		Master Tri-state Enable for pin 74, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI                                            1
+
+		Master Tri-state Enable for pin 75, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI                                            1
+
+		Master Tri-state Enable for pin 76, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI                                            0
+
+		Master Tri-state Enable for pin 77, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI                                            0
+
+		MIO pin Tri-state Enables, 77:64
+		(OFFSET, MASK, VALUE)      (0XFF18020C, 0x00003FFFU ,0x00000FC0U)  
+		RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI2_OFFSET ,0x00003FFFU ,0x00000FC0U);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl0 @ 0XFF180138

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25                                          1
+
+		Drive0 control to MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl1 @ 0XFF18013C

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25                                          1
+
+		Drive1 control to MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl3 @ 0XFF180140

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
+
+		Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF180140, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl4 @ 0XFF180144

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
+
+		When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl5 @ 0XFF180148

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25                                     1
+
+		When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl6 @ 0XFF18014C

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
+
+		Slew rate control to MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF18014C, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl0 @ 0XFF180154

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25                                          1
+
+		Drive0 control to MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl1 @ 0XFF180158

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25                                          1
+
+		Drive1 control to MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl3 @ 0XFF18015C

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
+
+		Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF18015C, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl4 @ 0XFF180160

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
+
+		When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl5 @ 0XFF180164

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25                                     1
+
+		When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl6 @ 0XFF180168

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
+
+		Slew rate control to MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF180168, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl0 @ 0XFF180170

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25                                          1
+
+		Drive0 control to MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl1 @ 0XFF180174

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25                                          1
+
+		Drive1 control to MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl3 @ 0XFF180178

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
+
+		Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF180178, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl4 @ 0XFF18017C

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
+
+		When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl5 @ 0XFF180180

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25                                     1
+
+		When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl6 @ 0XFF180184

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
+
+		Slew rate control to MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF180184, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : LOOPBACK
+		/*Register : MIO_LOOPBACK @ 0XFF180200

+
+		I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
+		ts to I2C 0 inputs.
+		PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1                                        0
+
+		CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
+		.
+		PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1                                        0
+
+		UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
+		outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.
+		PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1                                          0
+
+		SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
+		ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.
+		PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1                                        0
+
+		Loopback function within MIO
+		(OFFSET, MASK, VALUE)      (0XFF180200, 0x0000000FU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_LOOPBACK_OFFSET ,0x0000000FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_peripherals_init_data() {
+		// : RESET BLOCKS
+		// : ENET
+		/*Register : RST_LPD_IOU0 @ 0XFF5E0230

+
+		GEM 3 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0
+
+		Software controlled reset for the GEMs
+		(OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : QSPI
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000001U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : NAND
+		// : USB
+		/*Register : RST_LPD_TOP @ 0XFF5E023C

+
+		USB 0 reset for control registers
+		PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0
+
+		USB 0 sleep circuit reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0
+
+		USB 0 reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0
+
+		Software control register for the LPD block.
+		(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : FPD RESET
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		PCIE config reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0
+
+		PCIE control block level reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0
+
+		PCIE bridge block level reset (AXI interface)
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0
+
+		Display Port block level reset (includes DPDMA)
+		PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0
+
+		FPD WDT reset
+		PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET                                              0
+
+		GDMA block level reset
+		PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET                                              0
+
+		Pixel Processor (submodule of GPU) block level reset
+		PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET                                           0
+
+		Pixel Processor (submodule of GPU) block level reset
+		PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET                                           0
+
+		GPU block level reset
+		PSU_CRF_APB_RST_FPD_TOP_GPU_RESET                                               0
+
+		GT block level reset
+		PSU_CRF_APB_RST_FPD_TOP_GT_RESET                                                0
+
+		Sata block level reset
+		PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000F807EU ,0x00000000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | CRF_APB_RST_FPD_TOP_DP_RESET_MASK | CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK | CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_RESET_MASK | CRF_APB_RST_FPD_TOP_GT_RESET_MASK | CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000F807EU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : SD
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET                                            0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000040U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000040U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : CTRL_REG_SD @ 0XFF180310

+
+		SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
+		PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL                                           0
+
+		SD eMMC selection
+		(OFFSET, MASK, VALUE)      (0XFF180310, 0x00008000U ,0x00000000U)  
+		RegMask = (IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_CTRL_REG_SD_OFFSET ,0x00008000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : SD_CONFIG_REG2 @ 0XFF180320

+
+		Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE                                        0
+
+		1.8V Support 1: 1.8V supported 0: 1.8V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V                                            0
+
+		3.0V Support 1: 3.0V supported 0: 3.0V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V                                            0
+
+		3.3V Support 1: 3.3V supported 0: 3.3V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V                                            1
+
+		SD Config Register 2
+		(OFFSET, MASK, VALUE)      (0XFF180320, 0x33800000U ,0x00800000U)  
+		RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
+			| 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
+			| 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
+			| 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG2_OFFSET ,0x33800000U ,0x00800000U);
+	/*############################################################################################################################ */
+
+		// : SD1 BASE CLOCK
+		/*Register : SD_CONFIG_REG1 @ 0XFF18031C

+
+		Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
+		PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK                                         0xc7
+
+		SD Config Register 1
+		(OFFSET, MASK, VALUE)      (0XFF18031C, 0x7F800000U ,0x63800000U)  
+		RegMask = (IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK |  0 );
+
+		RegVal = ((0x000000C7U << IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG1_OFFSET ,0x7F800000U ,0x63800000U);
+	/*############################################################################################################################ */
+
+		// : CAN
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000100U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000100U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : I2C
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000600U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000600U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : SWDT
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00008000U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00008000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : SPI
+		// : TTC
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00007800U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00007800U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : UART
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET                                            0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET                                            0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000006U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000006U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : UART BAUD RATE
+		/*Register : Baud_rate_divider_reg0 @ 0XFF000034

+
+		Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+		PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
+
+		Baud Rate Divider Register
+		(OFFSET, MASK, VALUE)      (0XFF000034, 0x000000FFU ,0x00000005U)  
+		RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
+
+		RegVal = ((0x00000005U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U);
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_gen_reg0 @ 0XFF000018

+
+		Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+		PSU_UART0_BAUD_RATE_GEN_REG0_CD                                                 0x8f
+
+		Baud Rate Generator Register.
+		(OFFSET, MASK, VALUE)      (0XFF000018, 0x0000FFFFU ,0x0000008FU)  
+		RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
+
+		RegVal = ((0x0000008FU << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART0_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU);
+	/*############################################################################################################################ */
+
+		/*Register : Control_reg0 @ 0XFF000000

+
+		Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+		PSU_UART0_CONTROL_REG0_STPBRK                                                   0x0
+
+		Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+		PSU_UART0_CONTROL_REG0_STTBRK                                                   0x0
+
+		Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.
+		PSU_UART0_CONTROL_REG0_RSTTO                                                    0x0
+
+		Transmit disable: 0: enable transmitter 1: disable transmitter
+		PSU_UART0_CONTROL_REG0_TXDIS                                                    0x0
+
+		Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+		PSU_UART0_CONTROL_REG0_TXEN                                                     0x1
+
+		Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+		PSU_UART0_CONTROL_REG0_RXDIS                                                    0x0
+
+		Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+		PSU_UART0_CONTROL_REG0_RXEN                                                     0x1
+
+		Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.
+		PSU_UART0_CONTROL_REG0_TXRES                                                    0x1
+
+		Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.
+		PSU_UART0_CONTROL_REG0_RXRES                                                    0x1
+
+		UART Control Register
+		(OFFSET, MASK, VALUE)      (0XFF000000, 0x000001FFU ,0x00000017U)  
+		RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART0_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U);
+	/*############################################################################################################################ */
+
+		/*Register : mode_reg0 @ 0XFF000004

+
+		Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+		PSU_UART0_MODE_REG0_CHMODE                                                      0x0
+
+		Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved
+		PSU_UART0_MODE_REG0_NBSTOP                                                      0x0
+
+		Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+		PSU_UART0_MODE_REG0_PAR                                                         0x4
+
+		Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+		PSU_UART0_MODE_REG0_CHRL                                                        0x0
+
+		Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8
+		PSU_UART0_MODE_REG0_CLKS                                                        0x0
+
+		UART Mode Register
+		(OFFSET, MASK, VALUE)      (0XFF000004, 0x000003FFU ,0x00000020U)  
+		RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK |  0 );
+
+		RegVal = ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT
+			| 0x00000004U << UART0_MODE_REG0_PAR_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART0_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U);
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_divider_reg0 @ 0XFF010034

+
+		Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+		PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
+
+		Baud Rate Divider Register
+		(OFFSET, MASK, VALUE)      (0XFF010034, 0x000000FFU ,0x00000005U)  
+		RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
+
+		RegVal = ((0x00000005U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U);
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_gen_reg0 @ 0XFF010018

+
+		Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+		PSU_UART1_BAUD_RATE_GEN_REG0_CD                                                 0x8f
+
+		Baud Rate Generator Register.
+		(OFFSET, MASK, VALUE)      (0XFF010018, 0x0000FFFFU ,0x0000008FU)  
+		RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
+
+		RegVal = ((0x0000008FU << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART1_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU);
+	/*############################################################################################################################ */
+
+		/*Register : Control_reg0 @ 0XFF010000

+
+		Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+		PSU_UART1_CONTROL_REG0_STPBRK                                                   0x0
+
+		Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+		PSU_UART1_CONTROL_REG0_STTBRK                                                   0x0
+
+		Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.
+		PSU_UART1_CONTROL_REG0_RSTTO                                                    0x0
+
+		Transmit disable: 0: enable transmitter 1: disable transmitter
+		PSU_UART1_CONTROL_REG0_TXDIS                                                    0x0
+
+		Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+		PSU_UART1_CONTROL_REG0_TXEN                                                     0x1
+
+		Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+		PSU_UART1_CONTROL_REG0_RXDIS                                                    0x0
+
+		Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+		PSU_UART1_CONTROL_REG0_RXEN                                                     0x1
+
+		Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.
+		PSU_UART1_CONTROL_REG0_TXRES                                                    0x1
+
+		Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.
+		PSU_UART1_CONTROL_REG0_RXRES                                                    0x1
+
+		UART Control Register
+		(OFFSET, MASK, VALUE)      (0XFF010000, 0x000001FFU ,0x00000017U)  
+		RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART1_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U);
+	/*############################################################################################################################ */
+
+		/*Register : mode_reg0 @ 0XFF010004

+
+		Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+		PSU_UART1_MODE_REG0_CHMODE                                                      0x0
+
+		Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved
+		PSU_UART1_MODE_REG0_NBSTOP                                                      0x0
+
+		Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+		PSU_UART1_MODE_REG0_PAR                                                         0x4
+
+		Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+		PSU_UART1_MODE_REG0_CHRL                                                        0x0
+
+		Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8
+		PSU_UART1_MODE_REG0_CLKS                                                        0x0
+
+		UART Mode Register
+		(OFFSET, MASK, VALUE)      (0XFF010004, 0x000003FFU ,0x00000020U)  
+		RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK |  0 );
+
+		RegVal = ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT
+			| 0x00000004U << UART1_MODE_REG0_PAR_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART1_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U);
+	/*############################################################################################################################ */
+
+		// : GPIO
+		// : ADMA TZ
+		/*Register : slcr_adma @ 0XFF4B0024

+
+		TrustZone Classification for ADMA
+		PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ                                                0XFF
+
+		RPU TrustZone settings
+		(OFFSET, MASK, VALUE)      (0XFF4B0024, 0x000000FFU ,0x000000FFU)  
+		RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK |  0 );
+
+		RegVal = ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET ,0x000000FFU ,0x000000FFU);
+	/*############################################################################################################################ */
+
+		// : CSU TAMPERING
+		// : CSU TAMPER STATUS
+		/*Register : tamper_status @ 0XFFCA5000

+
+		CSU regsiter
+		PSU_CSU_TAMPER_STATUS_TAMPER_0                                                  0
+
+		External MIO
+		PSU_CSU_TAMPER_STATUS_TAMPER_1                                                  0
+
+		JTAG toggle detect
+		PSU_CSU_TAMPER_STATUS_TAMPER_2                                                  0
+
+		PL SEU error
+		PSU_CSU_TAMPER_STATUS_TAMPER_3                                                  0
+
+		AMS over temperature alarm for LPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_4                                                  0
+
+		AMS over temperature alarm for APU
+		PSU_CSU_TAMPER_STATUS_TAMPER_5                                                  0
+
+		AMS voltage alarm for VCCPINT_FPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_6                                                  0
+
+		AMS voltage alarm for VCCPINT_LPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_7                                                  0
+
+		AMS voltage alarm for VCCPAUX
+		PSU_CSU_TAMPER_STATUS_TAMPER_8                                                  0
+
+		AMS voltage alarm for DDRPHY
+		PSU_CSU_TAMPER_STATUS_TAMPER_9                                                  0
+
+		AMS voltage alarm for PSIO bank 0/1/2
+		PSU_CSU_TAMPER_STATUS_TAMPER_10                                                 0
+
+		AMS voltage alarm for PSIO bank 3 (dedicated pins)
+		PSU_CSU_TAMPER_STATUS_TAMPER_11                                                 0
+
+		AMS voltaage alarm for GT
+		PSU_CSU_TAMPER_STATUS_TAMPER_12                                                 0
+
+		Tamper Response Status
+		(OFFSET, MASK, VALUE)      (0XFFCA5000, 0x00001FFFU ,0x00000000U)  
+		RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK |  0 );
+
+		RegVal = ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CSU_TAMPER_STATUS_OFFSET ,0x00001FFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CSU TAMPER RESPONSE
+		// : AFIFM INTERFACE WIDTH
+		// : CPU QOS DEFAULT
+		/*Register : ACE_CTRL @ 0XFD5C0060

+
+		Set ACE outgoing AWQOS value
+		PSU_APU_ACE_CTRL_AWQOS                                                          0X0
+
+		Set ACE outgoing ARQOS value
+		PSU_APU_ACE_CTRL_ARQOS                                                          0X0
+
+		ACE Control Register
+		(OFFSET, MASK, VALUE)      (0XFD5C0060, 0x000F000FU ,0x00000000U)  
+		RegMask = (APU_ACE_CTRL_AWQOS_MASK | APU_ACE_CTRL_ARQOS_MASK |  0 );
+
+		RegVal = ((0x00000000U << APU_ACE_CTRL_AWQOS_SHIFT
+			| 0x00000000U << APU_ACE_CTRL_ARQOS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (APU_ACE_CTRL_OFFSET ,0x000F000FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE
+		/*Register : CONTROL @ 0XFFA60040

+
+		Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from 
+		he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
+		pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
+		g a 0 to this bit.
+		PSU_RTC_CONTROL_BATTERY_DISABLE                                                 0X1
+
+		This register controls various functionalities within the RTC
+		(OFFSET, MASK, VALUE)      (0XFFA60040, 0x80000000U ,0x80000000U)  
+		RegMask = (RTC_CONTROL_BATTERY_DISABLE_MASK |  0 );
+
+		RegVal = ((0x00000001U << RTC_CONTROL_BATTERY_DISABLE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (RTC_CONTROL_OFFSET ,0x80000000U ,0x80000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_post_config_data() {
+		// : POST_CONFIG
+
+  return 1;
+}
+unsigned long psu_peripherals_powerdwn_data() {
+		// : POWER DOWN REQUEST INTERRUPT ENABLE
+		// : POWER DOWN TRIGGER
+
+  return 1;
+}
+unsigned long psu_serdes_init_data() {
+		// : SERDES INITIALIZATION
+		// : GT REFERENCE CLOCK SOURCE SELECTION
+		/*Register : PLL_REF_SEL0 @ 0XFD410000

+
+		PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0                                              0xD
+
+		PLL0 Reference Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD410000, 0x0000001FU ,0x0000000DU)  
+		RegMask = (SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK |  0 );
+
+		RegVal = ((0x0000000DU << SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_PLL_REF_SEL0_OFFSET ,0x0000001FU ,0x0000000DU);
+	/*############################################################################################################################ */
+
+		/*Register : PLL_REF_SEL1 @ 0XFD410004

+
+		PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1                                              0x9
+
+		PLL1 Reference Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD410004, 0x0000001FU ,0x00000009U)  
+		RegMask = (SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK |  0 );
+
+		RegVal = ((0x00000009U << SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_PLL_REF_SEL1_OFFSET ,0x0000001FU ,0x00000009U);
+	/*############################################################################################################################ */
+
+		/*Register : PLL_REF_SEL2 @ 0XFD410008

+
+		PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2                                              0x8
+
+		PLL2 Reference Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD410008, 0x0000001FU ,0x00000008U)  
+		RegMask = (SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK |  0 );
+
+		RegVal = ((0x00000008U << SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_PLL_REF_SEL2_OFFSET ,0x0000001FU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : PLL_REF_SEL3 @ 0XFD41000C

+
+		PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3                                              0xF
+
+		PLL3 Reference Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD41000C, 0x0000001FU ,0x0000000FU)  
+		RegMask = (SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK |  0 );
+
+		RegVal = ((0x0000000FU << SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_PLL_REF_SEL3_OFFSET ,0x0000001FU ,0x0000000FU);
+	/*############################################################################################################################ */
+
+		// : GT REFERENCE CLOCK FREQUENCY SELECTION
+		/*Register : L0_L0_REF_CLK_SEL @ 0XFD402860

+
+		Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.
+		PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL                                 0x1
+
+		Lane0 Ref Clock Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD402860, 0x00000080U ,0x00000080U)  
+		RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
+	/*############################################################################################################################ */
+
+		/*Register : L0_L1_REF_CLK_SEL @ 0XFD402864

+
+		Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.
+		PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL                                 0x0
+
+		Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network
+		PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3                                   0x1
+
+		Lane1 Ref Clock Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD402864, 0x00000088U ,0x00000008U)  
+		RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
+			| 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : L0_L2_REF_CLK_SEL @ 0XFD402868

+
+		Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.
+		PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL                                 0x1
+
+		Lane2 Ref Clock Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD402868, 0x00000080U ,0x00000080U)  
+		RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
+	/*############################################################################################################################ */
+
+		/*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C

+
+		Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.
+		PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL                                 0x0
+
+		Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network
+		PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1                                   0x1
+
+		Lane3 Ref Clock Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD40286C, 0x00000082U ,0x00000002U)  
+		RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
+			| 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U);
+	/*############################################################################################################################ */
+
+		// : ENABLE SPREAD SPECTRUM
+		/*Register : L2_TM_PLL_DIG_37 @ 0XFD40A094

+
+		Enable/Disable coarse code satureation limiting logic
+		PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION                         0x1
+
+		Test mode register 37
+		(OFFSET, MASK, VALUE)      (0XFD40A094, 0x00000010U ,0x00000010U)  
+		RegMask = (SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_TM_PLL_DIG_37_OFFSET ,0x00000010U ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368

+
+		Spread Spectrum No of Steps [7:0]
+		PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x38
+
+		Spread Spectrum No of Steps bits 7:0
+		(OFFSET, MASK, VALUE)      (0XFD40A368, 0x000000FFU ,0x00000038U)  
+		RegMask = (SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
+
+		RegVal = ((0x00000038U << SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000038U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C

+
+		Spread Spectrum No of Steps [10:8]
+		PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x03
+
+		Spread Spectrum No of Steps bits 10:8
+		(OFFSET, MASK, VALUE)      (0XFD40A36C, 0x00000007U ,0x00000003U)  
+		RegMask = (SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
+
+		RegVal = ((0x00000003U << SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368

+
+		Spread Spectrum No of Steps [7:0]
+		PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x0
+
+		Spread Spectrum No of Steps bits 7:0
+		(OFFSET, MASK, VALUE)      (0XFD40E368, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C

+
+		Spread Spectrum No of Steps [10:8]
+		PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x0
+
+		Spread Spectrum No of Steps bits 10:8
+		(OFFSET, MASK, VALUE)      (0XFD40E36C, 0x00000007U ,0x00000000U)  
+		RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368

+
+		Spread Spectrum No of Steps [7:0]
+		PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x0
+
+		Spread Spectrum No of Steps bits 7:0
+		(OFFSET, MASK, VALUE)      (0XFD406368, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C

+
+		Spread Spectrum No of Steps [10:8]
+		PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x0
+
+		Spread Spectrum No of Steps bits 10:8
+		(OFFSET, MASK, VALUE)      (0XFD40636C, 0x00000007U ,0x00000000U)  
+		RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370

+
+		Step Size for Spread Spectrum [7:0]
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0x0
+
+		Step Size for Spread Spectrum LSB
+		(OFFSET, MASK, VALUE)      (0XFD406370, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374

+
+		Step Size for Spread Spectrum [15:8]
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x0
+
+		Step Size for Spread Spectrum 1
+		(OFFSET, MASK, VALUE)      (0XFD406374, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378

+
+		Step Size for Spread Spectrum [23:16]
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x0
+
+		Step Size for Spread Spectrum 2
+		(OFFSET, MASK, VALUE)      (0XFD406378, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C

+
+		Step Size for Spread Spectrum [25:24]
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
+
+		Enable/Disable test mode force on SS step size
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
+
+		Enable/Disable test mode force on SS no of steps
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
+
+		Enable force on enable Spread Spectrum
+		(OFFSET, MASK, VALUE)      (0XFD40637C, 0x00000033U ,0x00000030U)  
+		RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+			| 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+			| 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370

+
+		Step Size for Spread Spectrum [7:0]
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0xF4
+
+		Step Size for Spread Spectrum LSB
+		(OFFSET, MASK, VALUE)      (0XFD40A370, 0x000000FFU ,0x000000F4U)  
+		RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
+
+		RegVal = ((0x000000F4U << SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000F4U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374

+
+		Step Size for Spread Spectrum [15:8]
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x31
+
+		Step Size for Spread Spectrum 1
+		(OFFSET, MASK, VALUE)      (0XFD40A374, 0x000000FFU ,0x00000031U)  
+		RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
+
+		RegVal = ((0x00000031U << SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000031U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378

+
+		Step Size for Spread Spectrum [23:16]
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x2
+
+		Step Size for Spread Spectrum 2
+		(OFFSET, MASK, VALUE)      (0XFD40A378, 0x000000FFU ,0x00000002U)  
+		RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
+
+		RegVal = ((0x00000002U << SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C

+
+		Step Size for Spread Spectrum [25:24]
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
+
+		Enable/Disable test mode force on SS step size
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
+
+		Enable/Disable test mode force on SS no of steps
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
+
+		Enable force on enable Spread Spectrum
+		(OFFSET, MASK, VALUE)      (0XFD40A37C, 0x00000033U ,0x00000030U)  
+		RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+			| 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+			| 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370

+
+		Step Size for Spread Spectrum [7:0]
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0x0
+
+		Step Size for Spread Spectrum LSB
+		(OFFSET, MASK, VALUE)      (0XFD40E370, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374

+
+		Step Size for Spread Spectrum [15:8]
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x0
+
+		Step Size for Spread Spectrum 1
+		(OFFSET, MASK, VALUE)      (0XFD40E374, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378

+
+		Step Size for Spread Spectrum [23:16]
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x0
+
+		Step Size for Spread Spectrum 2
+		(OFFSET, MASK, VALUE)      (0XFD40E378, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C

+
+		Step Size for Spread Spectrum [25:24]
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
+
+		Enable/Disable test mode force on SS step size
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
+
+		Enable/Disable test mode force on SS no of steps
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
+
+		Enable test mode forcing on enable Spread Spectrum
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS                             0x1
+
+		Enable force on enable Spread Spectrum
+		(OFFSET, MASK, VALUE)      (0XFD40E37C, 0x000000B3U ,0x000000B0U)  
+		RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+			| 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+			| 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+			| 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x000000B3U ,0x000000B0U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_TM_DIG_6 @ 0XFD40906C

+
+		Bypass Descrambler
+		PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM                                           0x1
+
+		Enable Bypass for <1> TM_DIG_CTRL_6
+		PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
+
+		Data path test modes in decoder and descram
+		(OFFSET, MASK, VALUE)      (0XFD40906C, 0x00000003U ,0x00000003U)  
+		RegMask = (SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
+			| 0x00000001U << SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_TM_DIG_6_OFFSET ,0x00000003U ,0x00000003U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_TX_DIG_TM_61 @ 0XFD4080F4

+
+		Bypass scrambler signal
+		PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
+
+		Enable/disable scrambler bypass signal
+		PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
+
+		MPHY PLL Gear and bypass scrambler
+		(OFFSET, MASK, VALUE)      (0XFD4080F4, 0x00000003U ,0x00000003U)  
+		RegMask = (SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
+			| 0x00000001U << SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_TX_DIG_TM_61_OFFSET ,0x00000003U ,0x00000003U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360

+
+		Enable test mode force on fractional mode enable
+		PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC                             0x1
+
+		Fractional feedback division control and fractional value for feedback division bits 26:24
+		(OFFSET, MASK, VALUE)      (0XFD40E360, 0x00000040U ,0x00000040U)  
+		RegMask = (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET ,0x00000040U ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_TM_DIG_6 @ 0XFD40D06C

+
+		Bypass 8b10b decoder
+		PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER                                           0x1
+
+		Enable Bypass for <3> TM_DIG_CTRL_6
+		PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC                                         0x1
+
+		Bypass Descrambler
+		PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM                                           0x1
+
+		Enable Bypass for <1> TM_DIG_CTRL_6
+		PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
+
+		Data path test modes in decoder and descram
+		(OFFSET, MASK, VALUE)      (0XFD40D06C, 0x0000000FU ,0x0000000FU)  
+		RegMask = (SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK | SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
+			| 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
+			| 0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
+			| 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_TM_DIG_6_OFFSET ,0x0000000FU ,0x0000000FU);
+	/*############################################################################################################################ */
+
+		/*Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4

+
+		Enable/disable encoder bypass signal
+		PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC                                           0x1
+
+		Bypass scrambler signal
+		PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
+
+		Enable/disable scrambler bypass signal
+		PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
+
+		MPHY PLL Gear and bypass scrambler
+		(OFFSET, MASK, VALUE)      (0XFD40C0F4, 0x0000000BU ,0x0000000BU)  
+		RegMask = (SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK | SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
+			| 0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
+			| 0x00000001U << SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_TX_DIG_TM_61_OFFSET ,0x0000000BU ,0x0000000BU);
+	/*############################################################################################################################ */
+
+		/*Register : L3_TXPMA_ST_0 @ 0XFD40CB00

+
+		PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY
+		PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE                                            0x21
+
+		Opmode Info
+		(OFFSET, MASK, VALUE)      (0XFD40CB00, 0x000000F0U ,0x000000F0U)  
+		RegMask = (SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK |  0 );
+
+		RegVal = ((0x00000021U << SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U);
+	/*############################################################################################################################ */
+
+		// : GT LANE SETTINGS
+		/*Register : ICM_CFG0 @ 0XFD410010

+
+		Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
+		, 7 - Unused
+		PSU_SERDES_ICM_CFG0_L0_ICM_CFG                                                  1
+
+		Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
+		 7 - Unused
+		PSU_SERDES_ICM_CFG0_L1_ICM_CFG                                                  4
+
+		ICM Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD410010, 0x00000077U ,0x00000041U)  
+		RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
+			| 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000041U);
+	/*############################################################################################################################ */
+
+		/*Register : ICM_CFG1 @ 0XFD410014

+
+		Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
+		 7 - Unused
+		PSU_SERDES_ICM_CFG1_L2_ICM_CFG                                                  3
+
+		Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
+		 7 - Unused
+		PSU_SERDES_ICM_CFG1_L3_ICM_CFG                                                  2
+
+		ICM Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD410014, 0x00000077U ,0x00000023U)  
+		RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK |  0 );
+
+		RegVal = ((0x00000003U << SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
+			| 0x00000002U << SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_ICM_CFG1_OFFSET ,0x00000077U ,0x00000023U);
+	/*############################################################################################################################ */
+
+		// : CHECKING PLL LOCK
+		// : ENABLE SERIAL DATA MUX DEEMPH
+		/*Register : L1_TXPMD_TM_45 @ 0XFD404CB4

+
+		Enable/disable DP post2 path
+		PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH                         0x1
+
+		Override enable/disable of DP post2 path
+		PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH                    0x1
+
+		Override enable/disable of DP post1 path
+		PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH                    0x1
+
+		Enable/disable DP main path
+		PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH                          0x1
+
+		Override enable/disable of DP main path
+		PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH                     0x1
+
+		Post or pre or main DP path selection
+		(OFFSET, MASK, VALUE)      (0XFD404CB4, 0x00000037U ,0x00000037U)  
+		RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
+			| 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
+			| 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
+			| 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
+			| 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8

+
+		Test register force for enabling/disablign TX deemphasis bits <17:0>
+		PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0                                0x1
+
+		Enable Override of TX deemphasis
+		(OFFSET, MASK, VALUE)      (0XFD4041D8, 0x00000001U ,0x00000001U)  
+		RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : ENABLE PRE EMPHAIS AND VOLTAGE SWING
+		/*Register : L1_TXPMD_TM_48 @ 0XFD404CC0

+
+		Margining factor value
+		PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR                         0
+
+		Margining factor
+		(OFFSET, MASK, VALUE)      (0XFD404CC0, 0x0000001FU ,0x00000000U)  
+		RegMask = (SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_TX_ANA_TM_18 @ 0XFD404048

+
+		pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
+		PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0                                   0
+
+		Override for PIPE TX de-emphasis
+		(OFFSET, MASK, VALUE)      (0XFD404048, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_resetout_init_data() {
+		// : TAKING SERDES PERIPHERAL OUT OF RESET RESET
+		// : PUTTING USB0 IN RESET
+		/*Register : RST_LPD_TOP @ 0XFF5E023C

+
+		USB 0 reset for control registers
+		PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X0
+
+		Software control register for the LPD block.
+		(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000400U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000400U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : USB0 PIPE POWER PRESENT
+		/*Register : fpd_power_prsnt @ 0XFF9D0080

+
+		This bit is used to choose between PIPE power present and 1'b1
+		PSU_USB3_0_FPD_POWER_PRSNT_OPTION                                               0X1
+
+		fpd_power_prsnt
+		(OFFSET, MASK, VALUE)      (0XFF9D0080, 0x00000001U ,0x00000001U)  
+		RegMask = (USB3_0_FPD_POWER_PRSNT_OPTION_MASK |  0 );
+
+		RegVal = ((0x00000001U << USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : 
+		/*Register : RST_LPD_TOP @ 0XFF5E023C

+
+		USB 0 sleep circuit reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X0
+
+		USB 0 reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X0
+
+		Software control register for the LPD block.
+		(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000140U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000140U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : PUTTING GEM0 IN RESET
+		/*Register : RST_LPD_IOU0 @ 0XFF5E0230

+
+		GEM 3 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X0
+
+		Software controlled reset for the GEMs
+		(OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : PUTTING SATA IN RESET
+		/*Register : sata_misc_ctrl @ 0XFD3D0100

+
+		Sata PM clock control select
+		PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL                                         0x3
+
+		Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled)
+		(OFFSET, MASK, VALUE)      (0XFD3D0100, 0x00000003U ,0x00000003U)  
+		RegMask = (SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK |  0 );
+
+		RegVal = ((0x00000003U << SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SIOU_SATA_MISC_CTRL_OFFSET ,0x00000003U ,0x00000003U);
+	/*############################################################################################################################ */
+
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		Sata block level reset
+		PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X0
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : PUTTING PCIE IN RESET
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		PCIE config reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0X0
+
+		PCIE control block level reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0X0
+
+		PCIE bridge block level reset (AXI interface)
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0X0
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000E0000U ,0x00000000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : PUTTING DP IN RESET
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		Display Port block level reset (includes DPDMA)
+		PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X0
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00000000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DP_PHY_RESET @ 0XFD4A0200

+
+		Set to '1' to hold the GT in reset. Clear to release.
+		PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X0
+
+		Reset the transmitter PHY.
+		(OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000000U)  
+		RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << DP_DP_PHY_RESET_GT_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

+
+		Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 
+		ane0 Bits [3:2] - lane 1
+		PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0X0
+
+		Control PHY Power down
+		(OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x00000000U)  
+		RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : USB0 GFLADJ
+		/*Register : GUSB2PHYCFG @ 0XFE20C200

+
+		USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to 
+		he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
+		C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
+		. The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
+		UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger 
+		alue. Note: This field is valid only in device mode.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM                                           0X9
+
+		Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
+		 of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
+		time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
+		ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
+		off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
+		ng hibernation. - This bit is valid only in device mode.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY                                             0X0
+
+		Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
+		_n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
+		 to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. 
+		ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
+		n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
+		d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
+		d.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM                                            0X0
+
+		USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
+		Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - 
+		'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
+		 in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
+		 active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL                                              0X0
+
+		Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
+		figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
+		ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
+		r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
+		t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
+		g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
+		 when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20                                        0X1
+
+		Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
+		full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with 
+		ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
+		B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF                                              0X0
+
+		ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
+		e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
+		ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
+		lected through DWC_USB3_HSPHY_INTERFACE.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL                                       0X1
+
+		PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
+		 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same 
+		lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
+		 ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
+		 any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF                                               0X0
+
+		HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
+		a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for 
+		dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
+		e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
+		The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this 
+		ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
+		 clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
+		60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL                                             0X7
+
+		Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either 
+		he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
+		ented.
+		(OFFSET, MASK, VALUE)      (0XFE20C200, 0x00003FFFU ,0x00002457U)  
+		RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK |  0 );
+
+		RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
+			| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
+			| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
+			| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
+			| 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
+			| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
+			| 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
+			| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
+			| 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FFFU ,0x00002457U);
+	/*############################################################################################################################ */
+
+		/*Register : GFLADJ @ 0XFE20C630

+
+		This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register 
+		alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
+		_SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
+		TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
+		riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
+		cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
+		uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
+		((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
+		RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
+		PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ                                      0X0
+
+		Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
+		ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
+		 to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely 
+		rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
+		(OFFSET, MASK, VALUE)      (0XFE20C630, 0x003FFF00U ,0x00000000U)  
+		RegMask = (USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK |  0 );
+
+		RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL LOCK FOR LANE0
+		/*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4

+
+		Status Read value of PLL Lock
+		PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+		(OFFSET, MASK, VALUE)      (0XFD4023E4, 0x00000010U ,0x00000010U)  */
+		mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL LOCK FOR LANE1
+		/*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4

+
+		Status Read value of PLL Lock
+		PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+		(OFFSET, MASK, VALUE)      (0XFD4063E4, 0x00000010U ,0x00000010U)  */
+		mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL LOCK FOR LANE2
+		/*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4

+
+		Status Read value of PLL Lock
+		PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+		(OFFSET, MASK, VALUE)      (0XFD40A3E4, 0x00000010U ,0x00000010U)  */
+		mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL LOCK FOR LANE3
+		/*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4

+
+		Status Read value of PLL Lock
+		PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+		(OFFSET, MASK, VALUE)      (0XFD40E3E4, 0x00000010U ,0x00000010U)  */
+		mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+	/*############################################################################################################################ */
+
+		// : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
+		/*Register : ATTR_37 @ 0XFD480094

+
+		Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
+		gister.; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY                          0X1
+
+		ATTR_37
+		(OFFSET, MASK, VALUE)      (0XFD480094, 0x00004000U ,0x00004000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004000U ,0x00004000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_25 @ 0XFD480064

+
+		If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
+		ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED                      0X1
+
+		ATTR_25
+		(OFFSET, MASK, VALUE)      (0XFD480064, 0x00000200U ,0x00000200U)  
+		RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x00000200U ,0x00000200U);
+	/*############################################################################################################################ */
+
+		// : PCIE SETTINGS
+		/*Register : ATTR_7 @ 0XFD48001C

+
+		Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
+		ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
+		Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
+		erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 
+		set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
+		re size in bytes.; EP=0x0004; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0                                                0x0
+
+		ATTR_7
+		(OFFSET, MASK, VALUE)      (0XFD48001C, 0x0000FFFFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_7_OFFSET ,0x0000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_8 @ 0XFD480020

+
+		Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
+		ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
+		Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
+		erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 
+		set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
+		re size in bytes.; EP=0xFFF0; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0                                                0x0
+
+		ATTR_8
+		(OFFSET, MASK, VALUE)      (0XFD480020, 0x0000FFFFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_8_OFFSET ,0x0000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_9 @ 0XFD480024

+
+		Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 
+		AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
+		 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 
+		o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
+		32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 
+		'7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
+		ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1                                                0x0
+
+		ATTR_9
+		(OFFSET, MASK, VALUE)      (0XFD480024, 0x0000FFFFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_9_OFFSET ,0x0000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_10 @ 0XFD480028

+
+		Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 
+		AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
+		 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 
+		o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
+		32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 
+		'7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
+		ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1                                               0x0
+
+		ATTR_10
+		(OFFSET, MASK, VALUE)      (0XFD480028, 0x0000FFFFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_10_OFFSET ,0x0000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_11 @ 0XFD48002C

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
+		AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF
+		PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2                                               0xFFFF
+
+		ATTR_11
+		(OFFSET, MASK, VALUE)      (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU)  
+		RegMask = (PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK |  0 );
+
+		RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_11_OFFSET ,0x0000FFFFU ,0x0000FFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_12 @ 0XFD480030

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
+		AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF
+		PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2                                               0xFF
+
+		ATTR_12
+		(OFFSET, MASK, VALUE)      (0XFD480030, 0x0000FFFFU ,0x000000FFU)  
+		RegMask = (PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK |  0 );
+
+		RegVal = ((0x000000FFU << PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_12_OFFSET ,0x0000FFFFU ,0x000000FFU);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_13 @ 0XFD480034

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
+		AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
+		 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
+		t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
+		t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
+		if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 
+		f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
+		 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3                                               0x0
+
+		ATTR_13
+		(OFFSET, MASK, VALUE)      (0XFD480034, 0x0000FFFFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_13_OFFSET ,0x0000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_14 @ 0XFD480038

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
+		AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
+		 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
+		t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
+		t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
+		if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 
+		f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
+		 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF
+		PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3                                               0xFFFF
+
+		ATTR_14
+		(OFFSET, MASK, VALUE)      (0XFD480038, 0x0000FFFFU ,0x0000FFFFU)  
+		RegMask = (PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK |  0 );
+
+		RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_14_OFFSET ,0x0000FFFFU ,0x0000FFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_15 @ 0XFD48003C

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
+		AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0
+		PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4                                               0xFFF0
+
+		ATTR_15
+		(OFFSET, MASK, VALUE)      (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U)  
+		RegMask = (PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK |  0 );
+
+		RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_15_OFFSET ,0x0000FFFFU ,0x0000FFF0U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_16 @ 0XFD480040

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
+		AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0
+		PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4                                               0xFFF0
+
+		ATTR_16
+		(OFFSET, MASK, VALUE)      (0XFD480040, 0x0000FFFFU ,0x0000FFF0U)  
+		RegMask = (PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK |  0 );
+
+		RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_16_OFFSET ,0x0000FFFFU ,0x0000FFF0U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_17 @ 0XFD480044

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
+		AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
+		Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 
+		refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
+		R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 
+		refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 
+		ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
+		permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
+		PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5                                               0xFFF1
+
+		ATTR_17
+		(OFFSET, MASK, VALUE)      (0XFD480044, 0x0000FFFFU ,0x0000FFF1U)  
+		RegMask = (PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK |  0 );
+
+		RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_17_OFFSET ,0x0000FFFFU ,0x0000FFF1U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_18 @ 0XFD480048

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
+		AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
+		Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 
+		refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
+		R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 
+		refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 
+		ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
+		permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
+		PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5                                               0xFFF1
+
+		ATTR_18
+		(OFFSET, MASK, VALUE)      (0XFD480048, 0x0000FFFFU ,0x0000FFF1U)  
+		RegMask = (PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK |  0 );
+
+		RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_18_OFFSET ,0x0000FFFFU ,0x0000FFF1U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_27 @ 0XFD48006C

+
+		Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
+		to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED                      1
+
+		Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
+		state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
+		 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY                        0x0
+
+		ATTR_27
+		(OFFSET, MASK, VALUE)      (0XFD48006C, 0x00000738U ,0x00000100U)  
+		RegMask = (PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK | PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_27_OFFSET ,0x00000738U ,0x00000100U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_50 @ 0XFD4800C8

+
+		Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
+		00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
+		tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
+		gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004
+		PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE                          4
+
+		PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
+		lity.; EP=0x009C; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR                                   0
+
+		ATTR_50
+		(OFFSET, MASK, VALUE)      (0XFD4800C8, 0x0000FFF0U ,0x00000040U)  
+		RegMask = (PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK | PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK |  0 );
+
+		RegVal = ((0x00000004U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_50_OFFSET ,0x0000FFF0U ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_105 @ 0XFD4801A4

+
+		Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
+		ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
+		PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD                              0xCD
+
+		ATTR_105
+		(OFFSET, MASK, VALUE)      (0XFD4801A4, 0x000007FFU ,0x000000CDU)  
+		RegMask = (PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK |  0 );
+
+		RegVal = ((0x000000CDU << PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_105_OFFSET ,0x000007FFU ,0x000000CDU);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_106 @ 0XFD4801A8

+
+		Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non 
+		osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024
+		PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH                              0x24
+
+		Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
+		a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
+		completion header credits must be <= 80; EP=0x0004; RP=0x000C
+		PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH                             0xC
+
+		ATTR_106
+		(OFFSET, MASK, VALUE)      (0XFD4801A8, 0x00003FFFU ,0x00000624U)  
+		RegMask = (PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK | PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK |  0 );
+
+		RegVal = ((0x00000024U << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT
+			| 0x0000000CU << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_106_OFFSET ,0x00003FFFU ,0x00000624U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_107 @ 0XFD4801AC

+
+		Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data 
+		redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
+		d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
+		less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
+		PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD                             0x18
+
+		ATTR_107
+		(OFFSET, MASK, VALUE)      (0XFD4801AC, 0x000007FFU ,0x00000018U)  
+		RegMask = (PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK |  0 );
+
+		RegVal = ((0x00000018U << PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_107_OFFSET ,0x000007FFU ,0x00000018U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_108 @ 0XFD4801B0

+
+		Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less 
+		han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
+		PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD                              0xB5
+
+		ATTR_108
+		(OFFSET, MASK, VALUE)      (0XFD4801B0, 0x000007FFU ,0x000000B5U)  
+		RegMask = (PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK |  0 );
+
+		RegVal = ((0x000000B5U << PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_108_OFFSET ,0x000007FFU ,0x000000B5U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_109 @ 0XFD4801B4

+
+		Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
+		0
+		PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV                                      0x0
+
+		Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM                                    0x1
+
+		Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
+		cap structure; EP=0x0003; RP=0x0003
+		PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK                                         0x3
+
+		Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
+		mber of brams configured for transmit; EP=0x001C; RP=0x001C
+		PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET                                 0x1c
+
+		Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
+		d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020
+		PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH                              0x20
+
+		ATTR_109
+		(OFFSET, MASK, VALUE)      (0XFD4801B4, 0x0000FFFFU ,0x00007E20U)  
+		RegMask = (PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT
+			| 0x00000001U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT
+			| 0x00000003U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT
+			| 0x0000001CU << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT
+			| 0x00000020U << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_109_OFFSET ,0x0000FFFFU ,0x00007E20U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_34 @ 0XFD480088

+
+		Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
+		0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE                                        0x1
+
+		ATTR_34
+		(OFFSET, MASK, VALUE)      (0XFD480088, 0x000000FFU ,0x00000001U)  
+		RegMask = (PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_34_OFFSET ,0x000000FFU ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_53 @ 0XFD4800D4

+
+		PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
+		ty.; EP=0x0048; RP=0x0060
+		PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR                                     0x60
+
+		ATTR_53
+		(OFFSET, MASK, VALUE)      (0XFD4800D4, 0x000000FFU ,0x00000060U)  
+		RegMask = (PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK |  0 );
+
+		RegVal = ((0x00000060U << PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_53_OFFSET ,0x000000FFU ,0x00000060U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_41 @ 0XFD4800A4

+
+		MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
+		 to Cap structure; EP=0x0000; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE                 0x0
+
+		Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 
+		he management port.; EP=0x0001; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON                                         0
+
+		MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
+		ity.; EP=0x0060; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR                                    0x0
+
+		Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 
+		he management port.; EP=0x0001; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON                                         0
+
+		ATTR_41
+		(OFFSET, MASK, VALUE)      (0XFD4800A4, 0x000003FFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_41_OFFSET ,0x000003FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_97 @ 0XFD480184

+
+		Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004
+		PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH                            0x1
+
+		Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
+		4; RP=0x0004
+		PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH                               0x1
+
+		ATTR_97
+		(OFFSET, MASK, VALUE)      (0XFD480184, 0x00000FFFU ,0x00000041U)  
+		RegMask = (PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK | PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT
+			| 0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_97_OFFSET ,0x00000FFFU ,0x00000041U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_100 @ 0XFD480190

+
+		TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING                                   0x0
+
+		ATTR_100
+		(OFFSET, MASK, VALUE)      (0XFD480190, 0x00000040U ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_100_OFFSET ,0x00000040U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_101 @ 0XFD480194

+
+		Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message 
+		LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
+		Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
+		EP=0x0000; RP=0x07FF
+		PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE                                  0x7FF
+
+		Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING                             0x1
+
+		ATTR_101
+		(OFFSET, MASK, VALUE)      (0XFD480194, 0x0000FFE2U ,0x0000FFE2U)  
+		RegMask = (PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK | PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK |  0 );
+
+		RegVal = ((0x000007FFU << PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT
+			| 0x00000001U << PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_101_OFFSET ,0x0000FFE2U ,0x0000FFE2U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_37 @ 0XFD480094

+
+		Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
+		Required for Root.; EP=0x0000; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP           0x1
+
+		ATTR_37
+		(OFFSET, MASK, VALUE)      (0XFD480094, 0x00000200U ,0x00000200U)  
+		RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00000200U ,0x00000200U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_93 @ 0XFD480174

+
+		Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
+		_REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN                               0x1
+
+		Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
+		TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
+		4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT                                  0x1000
+
+		ATTR_93
+		(OFFSET, MASK, VALUE)      (0XFD480174, 0x0000FFFFU ,0x00009000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK | PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT
+			| 0x00001000U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_93_OFFSET ,0x0000FFFFU ,0x00009000U);
+	/*############################################################################################################################ */
+
+		/*Register : ID @ 0XFD480200

+
+		Device ID for the the PCIe Cap Structure Device ID field
+		PSU_PCIE_ATTRIB_ID_CFG_DEV_ID                                                   0xd021
+
+		Vendor ID for the PCIe Cap Structure Vendor ID field
+		PSU_PCIE_ATTRIB_ID_CFG_VEND_ID                                                  0x10ee
+
+		ID
+		(OFFSET, MASK, VALUE)      (0XFD480200, 0xFFFFFFFFU ,0x10EED021U)  
+		RegMask = (PCIE_ATTRIB_ID_CFG_DEV_ID_MASK | PCIE_ATTRIB_ID_CFG_VEND_ID_MASK |  0 );
+
+		RegVal = ((0x0000D021U << PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT
+			| 0x000010EEU << PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ID_OFFSET ,0xFFFFFFFFU ,0x10EED021U);
+	/*############################################################################################################################ */
+
+		/*Register : SUBSYS_ID @ 0XFD480204

+
+		Subsystem ID for the the PCIe Cap Structure Subsystem ID field
+		PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID                                         0x7
+
+		Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
+		PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID                                    0x10ee
+
+		SUBSYS_ID
+		(OFFSET, MASK, VALUE)      (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U)  
+		RegMask = (PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK | PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK |  0 );
+
+		RegVal = ((0x00000007U << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT
+			| 0x000010EEU << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_SUBSYS_ID_OFFSET ,0xFFFFFFFFU ,0x10EE0007U);
+	/*############################################################################################################################ */
+
+		/*Register : REV_ID @ 0XFD480208

+
+		Revision ID for the the PCIe Cap Structure
+		PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID                                               0x0
+
+		REV_ID
+		(OFFSET, MASK, VALUE)      (0XFD480208, 0x000000FFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_REV_ID_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_24 @ 0XFD480060

+
+		Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
+		8000; RP=0x8000
+		PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE                                         0x400
+
+		ATTR_24
+		(OFFSET, MASK, VALUE)      (0XFD480060, 0x0000FFFFU ,0x00000400U)  
+		RegMask = (PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK |  0 );
+
+		RegVal = ((0x00000400U << PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_24_OFFSET ,0x0000FFFFU ,0x00000400U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_25 @ 0XFD480064

+
+		Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
+		0005; RP=0x0006
+		PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE                                         0x6
+
+		INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED                               0
+
+		ATTR_25
+		(OFFSET, MASK, VALUE)      (0XFD480064, 0x000001FFU ,0x00000006U)  
+		RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK | PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK |  0 );
+
+		RegVal = ((0x00000006U << PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x000001FFU ,0x00000006U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_4 @ 0XFD480010

+
+		Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 
+		he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
+		ges are sent if an error is detected).; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON                                          0
+
+		Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 
+		he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
+		ges are sent if an error is detected).; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON                                          0
+
+		ATTR_4
+		(OFFSET, MASK, VALUE)      (0XFD480010, 0x00001000U ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_4_OFFSET ,0x00001000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_89 @ 0XFD480164

+
+		VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
+		0x0140; RP=0x0140
+		PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR                                   0
+
+		ATTR_89
+		(OFFSET, MASK, VALUE)      (0XFD480164, 0x00001FFEU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_89_OFFSET ,0x00001FFEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_79 @ 0XFD48013C

+
+		CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY                         1
+
+		ATTR_79
+		(OFFSET, MASK, VALUE)      (0XFD48013C, 0x00000020U ,0x00000020U)  
+		RegMask = (PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_79_OFFSET ,0x00000020U ,0x00000020U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_43 @ 0XFD4800AC

+
+		Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
+		 the management port.; EP=0x0001; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON                                        0
+
+		ATTR_43
+		(OFFSET, MASK, VALUE)      (0XFD4800AC, 0x00000100U ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_43_OFFSET ,0x00000100U ,0x00000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_resetin_init_data() {
+		// : PUTTING SERDES PERIPHERAL IN RESET
+		// : PUTTING USB0 IN RESET
+		/*Register : RST_LPD_TOP @ 0XFF5E023C

+
+		USB 0 reset for control registers
+		PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X1
+
+		USB 0 sleep circuit reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X1
+
+		USB 0 reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X1
+
+		Software control register for the LPD block.
+		(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000540U)  
+		RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+			| 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+			| 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000540U);
+	/*############################################################################################################################ */
+
+		// : PUTTING GEM0 IN RESET
+		/*Register : RST_LPD_IOU0 @ 0XFF5E0230

+
+		GEM 3 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X1
+
+		Software controlled reset for the GEMs
+		(OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000008U)  
+		RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : PUTTING SATA IN RESET
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		Sata block level reset
+		PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X1
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000002U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000002U);
+	/*############################################################################################################################ */
+
+		// : PUTTING PCIE IN RESET
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		PCIE config reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0X1
+
+		PCIE control block level reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0X1
+
+		PCIE bridge block level reset (AXI interface)
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0X1
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000E0000U ,0x000E0000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
+			| 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
+			| 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x000E0000U);
+	/*############################################################################################################################ */
+
+		// : PUTTING DP IN RESET
+		/*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

+
+		Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 
+		ane0 Bits [3:2] - lane 1
+		PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0XA
+
+		Control PHY Power down
+		(OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x0000000AU)  
+		RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK |  0 );
+
+		RegVal = ((0x0000000AU << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x0000000AU);
+	/*############################################################################################################################ */
+
+		/*Register : DP_PHY_RESET @ 0XFD4A0200

+
+		Set to '1' to hold the GT in reset. Clear to release.
+		PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X1
+
+		Reset the transmitter PHY.
+		(OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000002U)  
+		RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << DP_DP_PHY_RESET_GT_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		Display Port block level reset (includes DPDMA)
+		PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X1
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00010000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00010000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_ps_pl_isolation_removal_data() {
+		// : PS-PL POWER UP REQUEST
+		/*Register : REQ_PWRUP_INT_EN @ 0XFFD80118

+
+		Power-up Request Interrupt Enable for PL
+		PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL                                              1
+
+		Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt.
+		(OFFSET, MASK, VALUE)      (0XFFD80118, 0x00800000U ,0x00800000U)  
+		RegMask = (PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK |  0 );
+
+		RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET ,0x00800000U ,0x00800000U);
+	/*############################################################################################################################ */
+
+		/*Register : REQ_PWRUP_TRIG @ 0XFFD80120

+
+		Power-up Request Trigger for PL
+		PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL                                                1
+
+		Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU.
+		(OFFSET, MASK, VALUE)      (0XFFD80120, 0x00800000U ,0x00800000U)  
+		RegMask = (PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK |  0 );
+
+		RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET ,0x00800000U ,0x00800000U);
+	/*############################################################################################################################ */
+
+		// : POLL ON PL POWER STATUS
+		/*Register : REQ_PWRUP_STATUS @ 0XFFD80110

+
+		Power-up Request Status for PL
+		PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL                                              1
+		(OFFSET, MASK, VALUE)      (0XFFD80110, 0x00800000U ,0x00000000U)  */
+		mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET,0x00800000U,0x00000000U);
+
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_ps_pl_reset_config_data() {
+		// : PS PL RESET SEQUENCE
+		// : FABRIC RESET USING EMIO
+		/*Register : MASK_DATA_5_MSW @ 0XFF0A002C

+
+		Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
+		PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW                                             0x8000
+
+		Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits)
+		(OFFSET, MASK, VALUE)      (0XFF0A002C, 0xFFFF0000U ,0x80000000U)  
+		RegMask = (GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK |  0 );
+
+		RegVal = ((0x00008000U << GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_MASK_DATA_5_MSW_OFFSET ,0xFFFF0000U ,0x80000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DIRM_5 @ 0XFF0A0344

+
+		Operation is the same as DIRM_0[DIRECTION_0]
+		PSU_GPIO_DIRM_5_DIRECTION_5                                                     0x80000000
+
+		Direction mode (GPIO Bank5, EMIO)
+		(OFFSET, MASK, VALUE)      (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U)  
+		RegMask = (GPIO_DIRM_5_DIRECTION_5_MASK |  0 );
+
+		RegVal = ((0x80000000U << GPIO_DIRM_5_DIRECTION_5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_DIRM_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
+	/*############################################################################################################################ */
+
+		/*Register : OEN_5 @ 0XFF0A0348

+
+		Operation is the same as OEN_0[OP_ENABLE_0]
+		PSU_GPIO_OEN_5_OP_ENABLE_5                                                      0x80000000
+
+		Output enable (GPIO Bank5, EMIO)
+		(OFFSET, MASK, VALUE)      (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U)  
+		RegMask = (GPIO_OEN_5_OP_ENABLE_5_MASK |  0 );
+
+		RegVal = ((0x80000000U << GPIO_OEN_5_OP_ENABLE_5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_OEN_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DATA_5 @ 0XFF0A0054

+
+		Output Data
+		PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
+
+		Output Data (GPIO Bank5, EMIO)
+		(OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)  
+		RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
+
+		RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
+	/*############################################################################################################################ */
+
+		mask_delay(1);
+
+	/*############################################################################################################################ */
+
+		// : FABRIC RESET USING DATA_5 TOGGLE
+		/*Register : DATA_5 @ 0XFF0A0054

+
+		Output Data
+		PSU_GPIO_DATA_5_DATA_5                                                          0X00000000
+
+		Output Data (GPIO Bank5, EMIO)
+		(OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
+
+		RegVal = ((0x00000000U << GPIO_DATA_5_DATA_5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		mask_delay(1);
+
+	/*############################################################################################################################ */
+
+		// : FABRIC RESET USING DATA_5 TOGGLE
+		/*Register : DATA_5 @ 0XFF0A0054

+
+		Output Data
+		PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
+
+		Output Data (GPIO Bank5, EMIO)
+		(OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)  
+		RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
+
+		RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+
+unsigned long psu_ddr_phybringup_data() {
+
+
+		unsigned int regval = 0;
+	Xil_Out32(0xFD090000U, 0x0000A845U);
+	Xil_Out32(0xFD090004U, 0x003FFFFFU);
+	Xil_Out32(0xFD09000CU, 0x00000010U);
+	Xil_Out32(0xFD090010U, 0x00000010U);
+	// PHY BRINGUP SEQ
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000000FU);
+	prog_reg (0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+	//poll for PHY initialization to complete 
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU);
+	
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U);
+	prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	 Xil_Out32(0xFD080004, 0x0004FE01); //PUB_PIR  
+	  regval = Xil_In32(0xFD080030); //PUB_PGSR0
+	  while(regval != 0x80000FFF){   
+	     regval = Xil_In32(0xFD080030); //PUB_PGSR0 
+	  } 
+
+	
+ // Run Vref training in static read mode  
+	Xil_Out32(0xFD080200U, 0x110011C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EF2U);
+	Xil_Out32(0xFD08001CU, 0x55AA0098U);
+	Xil_Out32(0xFD08142CU, 0x00001830U);
+	Xil_Out32(0xFD08146CU, 0x00001830U);
+	Xil_Out32(0xFD0814ACU, 0x00001830U);
+	Xil_Out32(0xFD0814ECU, 0x00001830U);
+	Xil_Out32(0xFD08152CU, 0x00001830U);
+	 
+
+	 Xil_Out32(0xFD080004, 0x00060001); //PUB_PIR  
+	  regval = Xil_In32(0xFD080030); //PUB_PGSR0
+	  while((regval & 0x80004001) != 0x80004001){   
+	     regval = Xil_In32(0xFD080030); //PUB_PGSR0 
+	  } 
+
+	 // Vref training is complete, disabling static read mode 
+	Xil_Out32(0xFD080200U, 0x810011C7U);
+	Xil_Out32(0xFD080018U, 0x00F12302U);
+	Xil_Out32(0xFD08001CU, 0x55AA0080U);
+	Xil_Out32(0xFD08142CU, 0x00001800U);
+	Xil_Out32(0xFD08146CU, 0x00001800U);
+	Xil_Out32(0xFD0814ACU, 0x00001800U);
+	Xil_Out32(0xFD0814ECU, 0x00001800U);
+	Xil_Out32(0xFD08152CU, 0x00001800U);
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+return 1; 
+}
+
+/**
+ * CRL_APB Base Address
+ */
+#define CRL_APB_BASEADDR      0XFF5E0000U
+#define CRL_APB_RST_LPD_IOU0    ( ( CRL_APB_BASEADDR ) + 0X00000230U )
+#define CRL_APB_RST_LPD_IOU1    ( ( CRL_APB_BASEADDR ) + 0X00000234U )
+#define CRL_APB_RST_LPD_IOU2    ( ( CRL_APB_BASEADDR ) + 0X00000238U )
+#define CRL_APB_RST_LPD_TOP    ( ( CRL_APB_BASEADDR ) + 0X0000023CU )
+#define CRL_APB_IOU_SWITCH_CTRL    ( ( CRL_APB_BASEADDR ) + 0X0000009CU )
+
+/**
+ * CRF_APB Base Address
+ */
+#define CRF_APB_BASEADDR      0XFD1A0000U
+
+#define CRF_APB_RST_FPD_TOP    ( ( CRF_APB_BASEADDR ) + 0X00000100U )
+#define CRF_APB_GPU_REF_CTRL    ( ( CRF_APB_BASEADDR ) + 0X00000084U )
+#define CRF_APB_RST_DDR_SS    ( ( CRF_APB_BASEADDR ) + 0X00000108U )
+#define PSU_MASK_POLL_TIME 1100000
+
+
+int mask_pollOnValue(u32 add , u32 mask, u32 value ) {
+	volatile u32 *addr = (volatile u32*) add;
+	int i = 0;
+	while ((*addr & mask)!= value) {
+		if (i == PSU_MASK_POLL_TIME) {
+			return 0;
+		}
+		i++;
+	}
+	return 1;   
+	//xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+int mask_poll(u32 add , u32 mask) {
+	volatile u32 *addr = (volatile u32*) add;
+	int i = 0;
+	while (!(*addr & mask)) {
+		if (i == PSU_MASK_POLL_TIME) {
+			return 0;
+		}
+		i++;
+	}
+	return 1;   
+	//xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+void mask_delay(u32 delay) {
+    usleep (delay);
+}
+
+u32 mask_read(u32 add , u32 mask ) {
+        volatile u32 *addr = (volatile u32*) add;
+        u32 val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+//Following SERDES programming sequences that a user need to follow to work around the known limitation with SERDES. 
+//These sequences should done before STEP 1 and STEP 2 as described in previous section. These programming steps are
+//required for current silicon version and are likely to undergo further changes with subsequent silicon versions.
+
+
+
+int serdes_fixcal_code() {
+	int MaskStatus = 1;
+
+   // L3_TM_CALIB_DIG19
+   Xil_Out32(0xFD40EC4C,0x00000020);
+   //ICM_CFG0
+   Xil_Out32(0xFD410010,0x00000001);
+
+   //is calibration done, polling on L3_CALIB_DONE_STATUS
+   MaskStatus = mask_poll(0xFD40EF14, 0x2);
+   
+   if (MaskStatus == 0)
+   {
+        xil_printf("SERDES initialization timed out\n\r");
+   }
+ 
+   unsigned int tmp_0_1; 
+   tmp_0_1 = mask_read(0xFD400B0C, 0x3F);
+   
+   unsigned int tmp_0_2 = tmp_0_1 & (0x7); 
+   unsigned int tmp_0_3 = tmp_0_1 & (0x38);
+   //Configure ICM for de-asserting CMN_Resetn
+   Xil_Out32(0xFD410010,0x00000000);
+   Xil_Out32(0xFD410014,0x00000000);
+   
+   unsigned int tmp_0_2_mod = (tmp_0_2 <<1) | (0x1); 
+   tmp_0_2_mod = (tmp_0_2_mod <<4); 
+   
+   tmp_0_3 = tmp_0_3 >>3;
+   Xil_Out32(0xFD40EC4C,tmp_0_3);
+
+   //L3_TM_CALIB_DIG18
+   Xil_Out32(0xFD40EC48,tmp_0_2_mod);
+   return MaskStatus;
+
+
+}
+
+int serdes_enb_coarse_saturation() {
+  //Enable PLL Coarse Code saturation Logic
+   Xil_Out32(0xFD402094,0x00000010); 
+   Xil_Out32(0xFD406094,0x00000010); 
+   Xil_Out32(0xFD40A094,0x00000010); 
+   Xil_Out32(0xFD40E094,0x00000010);
+   return 1;
+}
+
+int init_serdes() {
+	int status = 1;
+	status &=  psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+    status &=  psu_serdes_init_data();
+	status &=  psu_resetout_init_data();
+
+	return status;
+}
+
+
+
+
+
+
+void init_peripheral()
+{
+	unsigned int RegValue;
+
+	/* Turn on IOU Clock */
+	//Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500);
+
+	/* Release all resets in the IOU */
+	Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000);
+	Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000);
+	Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000);
+
+	/* Activate GPU clocks */
+	//Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500);
+
+	/* Take LPD out of reset except R5 */
+	RegValue = Xil_In32(CRL_APB_RST_LPD_TOP);
+	RegValue &= 0x7;
+	Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue);
+
+	/* Take most of FPD out of reset */
+	Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000);
+
+	/* Making DPDMA as secure */
+  unsigned int tmp_regval; 
+  tmp_regval = Xil_In32(0xFD690040);
+  tmp_regval &= ~0x00000001;
+  Xil_Out32(0xFD690040, tmp_regval);
+
+	/* Making PCIe as secure */
+  tmp_regval = Xil_In32(0xFD690030);
+  tmp_regval &= ~0x00000001;
+  Xil_Out32(0xFD690030, tmp_regval);
+}
+int
+psu_init() 
+{
+	int status = 1; 
+	status &= psu_mio_init_data ();
+	status &=   psu_pll_init_data ();
+	status &=   psu_clock_init_data ();
+
+	status &=  psu_ddr_init_data ();
+	status &=  psu_ddr_phybringup_data ();
+	status &=  psu_peripherals_init_data ();
+
+	status &=  init_serdes();
+	init_peripheral ();
+
+	status &=  psu_peripherals_powerdwn_data ();
+   
+	if (status == 0) {
+		return 1;
+	}
+	return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h
new file mode 100644
index 000000000..97a2ae16d
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.h
@@ -0,0 +1,26160 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+* XILINX CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+/****************************************************************************/
+/**
+*
+* @file psu_init.h
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+
+#undef CRL_APB_RPLL_CFG_OFFSET 
+#define CRL_APB_RPLL_CFG_OFFSET                                                    0XFF5E0034
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 
+#define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET                                            0XFF5E0048
+#undef CRL_APB_RPLL_FRAC_CFG_OFFSET 
+#define CRL_APB_RPLL_FRAC_CFG_OFFSET                                               0XFF5E0038
+#undef CRL_APB_IOPLL_CFG_OFFSET 
+#define CRL_APB_IOPLL_CFG_OFFSET                                                   0XFF5E0024
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 
+#define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET                                           0XFF5E0044
+#undef CRL_APB_IOPLL_FRAC_CFG_OFFSET 
+#define CRL_APB_IOPLL_FRAC_CFG_OFFSET                                              0XFF5E0028
+#undef CRF_APB_APLL_CFG_OFFSET 
+#define CRF_APB_APLL_CFG_OFFSET                                                    0XFD1A0024
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_APLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0048
+#undef CRF_APB_APLL_FRAC_CFG_OFFSET 
+#define CRF_APB_APLL_FRAC_CFG_OFFSET                                               0XFD1A0028
+#undef CRF_APB_DPLL_CFG_OFFSET 
+#define CRF_APB_DPLL_CFG_OFFSET                                                    0XFD1A0030
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A004C
+#undef CRF_APB_DPLL_FRAC_CFG_OFFSET 
+#define CRF_APB_DPLL_FRAC_CFG_OFFSET                                               0XFD1A0034
+#undef CRF_APB_VPLL_CFG_OFFSET 
+#define CRF_APB_VPLL_CFG_OFFSET                                                    0XFD1A003C
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0050
+#undef CRF_APB_VPLL_FRAC_CFG_OFFSET 
+#define CRF_APB_VPLL_FRAC_CFG_OFFSET                                               0XFD1A0040
+
+/*PLL loop filter resistor control*/
+#undef CRL_APB_RPLL_CFG_RES_DEFVAL 
+#undef CRL_APB_RPLL_CFG_RES_SHIFT 
+#undef CRL_APB_RPLL_CFG_RES_MASK 
+#define CRL_APB_RPLL_CFG_RES_DEFVAL                                                0x00000000
+#define CRL_APB_RPLL_CFG_RES_SHIFT                                                 0
+#define CRL_APB_RPLL_CFG_RES_MASK                                                  0x0000000FU
+
+/*PLL charge pump control*/
+#undef CRL_APB_RPLL_CFG_CP_DEFVAL 
+#undef CRL_APB_RPLL_CFG_CP_SHIFT 
+#undef CRL_APB_RPLL_CFG_CP_MASK 
+#define CRL_APB_RPLL_CFG_CP_DEFVAL                                                 0x00000000
+#define CRL_APB_RPLL_CFG_CP_SHIFT                                                  5
+#define CRL_APB_RPLL_CFG_CP_MASK                                                   0x000001E0U
+
+/*PLL loop filter high frequency capacitor control*/
+#undef CRL_APB_RPLL_CFG_LFHF_DEFVAL 
+#undef CRL_APB_RPLL_CFG_LFHF_SHIFT 
+#undef CRL_APB_RPLL_CFG_LFHF_MASK 
+#define CRL_APB_RPLL_CFG_LFHF_DEFVAL                                               0x00000000
+#define CRL_APB_RPLL_CFG_LFHF_SHIFT                                                10
+#define CRL_APB_RPLL_CFG_LFHF_MASK                                                 0x00000C00U
+
+/*Lock circuit counter setting*/
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK 
+#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
+#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT                                            13
+#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
+
+/*Lock circuit configuration settings for lock windowsize*/
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK 
+#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
+#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT                                            25
+#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
+
+/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK 
+#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL                                           0x00012C09
+#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT                                            20
+#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT 
+#undef CRL_APB_RPLL_CTRL_FBDIV_MASK 
+#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRL_APB_RPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT 
+#undef CRL_APB_RPLL_CTRL_DIV2_MASK 
+#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL                                              0x00012C09
+#define CRL_APB_RPLL_CTRL_DIV2_SHIFT                                               16
+#define CRL_APB_RPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
+#define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
+#define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*RPLL is locked*/
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL                                        0x00000018
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT                                         1
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK                                          0x00000002U
+#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
+#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL 
+#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 
+#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK 
+#define CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
+#define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT                                        31
+#define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
+
+/*Fractional value for the Feedback value.*/
+#undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL 
+#undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 
+#undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK 
+#define CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
+#define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT                                           0
+#define CRL_APB_RPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
+
+/*PLL loop filter resistor control*/
+#undef CRL_APB_IOPLL_CFG_RES_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_RES_SHIFT 
+#undef CRL_APB_IOPLL_CFG_RES_MASK 
+#define CRL_APB_IOPLL_CFG_RES_DEFVAL                                               0x00000000
+#define CRL_APB_IOPLL_CFG_RES_SHIFT                                                0
+#define CRL_APB_IOPLL_CFG_RES_MASK                                                 0x0000000FU
+
+/*PLL charge pump control*/
+#undef CRL_APB_IOPLL_CFG_CP_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_CP_SHIFT 
+#undef CRL_APB_IOPLL_CFG_CP_MASK 
+#define CRL_APB_IOPLL_CFG_CP_DEFVAL                                                0x00000000
+#define CRL_APB_IOPLL_CFG_CP_SHIFT                                                 5
+#define CRL_APB_IOPLL_CFG_CP_MASK                                                  0x000001E0U
+
+/*PLL loop filter high frequency capacitor control*/
+#undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_LFHF_SHIFT 
+#undef CRL_APB_IOPLL_CFG_LFHF_MASK 
+#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL                                              0x00000000
+#define CRL_APB_IOPLL_CFG_LFHF_SHIFT                                               10
+#define CRL_APB_IOPLL_CFG_LFHF_MASK                                                0x00000C00U
+
+/*Lock circuit counter setting*/
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 
+#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL                                          0x00000000
+#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT                                           13
+#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK                                            0x007FE000U
+
+/*Lock circuit configuration settings for lock windowsize*/
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 
+#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL                                          0x00000000
+#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT                                           25
+#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK                                            0xFE000000U
+
+/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 
+#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL                                          0x00012C09
+#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT                                           20
+#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK                                            0x00700000U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK 
+#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT                                             8
+#define CRL_APB_IOPLL_CTRL_FBDIV_MASK                                              0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_DIV2_MASK 
+#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL                                             0x00012C09
+#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT                                              16
+#define CRL_APB_IOPLL_CTRL_DIV2_MASK                                               0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
+#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
+#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
+#define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
+#define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
+
+/*IOPLL is locked*/
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL                                       0x00000018
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT                                        0
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK                                         0x00000001U
+#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
+#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
+#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                  0x00000400
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                   8
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
+#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL 
+#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 
+#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK 
+#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL                                      0x00000000
+#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT                                       31
+#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK                                        0x80000000U
+
+/*Fractional value for the Feedback value.*/
+#undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL 
+#undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 
+#undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK 
+#define CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL                                         0x00000000
+#define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT                                          0
+#define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK                                           0x0000FFFFU
+
+/*PLL loop filter resistor control*/
+#undef CRF_APB_APLL_CFG_RES_DEFVAL 
+#undef CRF_APB_APLL_CFG_RES_SHIFT 
+#undef CRF_APB_APLL_CFG_RES_MASK 
+#define CRF_APB_APLL_CFG_RES_DEFVAL                                                0x00000000
+#define CRF_APB_APLL_CFG_RES_SHIFT                                                 0
+#define CRF_APB_APLL_CFG_RES_MASK                                                  0x0000000FU
+
+/*PLL charge pump control*/
+#undef CRF_APB_APLL_CFG_CP_DEFVAL 
+#undef CRF_APB_APLL_CFG_CP_SHIFT 
+#undef CRF_APB_APLL_CFG_CP_MASK 
+#define CRF_APB_APLL_CFG_CP_DEFVAL                                                 0x00000000
+#define CRF_APB_APLL_CFG_CP_SHIFT                                                  5
+#define CRF_APB_APLL_CFG_CP_MASK                                                   0x000001E0U
+
+/*PLL loop filter high frequency capacitor control*/
+#undef CRF_APB_APLL_CFG_LFHF_DEFVAL 
+#undef CRF_APB_APLL_CFG_LFHF_SHIFT 
+#undef CRF_APB_APLL_CFG_LFHF_MASK 
+#define CRF_APB_APLL_CFG_LFHF_DEFVAL                                               0x00000000
+#define CRF_APB_APLL_CFG_LFHF_SHIFT                                                10
+#define CRF_APB_APLL_CFG_LFHF_MASK                                                 0x00000C00U
+
+/*Lock circuit counter setting*/
+#undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 
+#undef CRF_APB_APLL_CFG_LOCK_CNT_MASK 
+#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
+#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT                                            13
+#define CRF_APB_APLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
+
+/*Lock circuit configuration settings for lock windowsize*/
+#undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 
+#undef CRF_APB_APLL_CFG_LOCK_DLY_MASK 
+#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
+#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT                                            25
+#define CRF_APB_APLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
+
+/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
+#undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 
+#undef CRF_APB_APLL_CTRL_PRE_SRC_MASK 
+#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL                                           0x00012C09
+#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT                                            20
+#define CRF_APB_APLL_CTRL_PRE_SRC_MASK                                             0x00700000U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_APLL_CTRL_FBDIV_MASK 
+#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_APLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_APLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_APLL_CTRL_DIV2_MASK 
+#define CRF_APB_APLL_CTRL_DIV2_DEFVAL                                              0x00012C09
+#define CRF_APB_APLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_APLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*APLL is locked*/
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT                                         0
+#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK                                          0x00000001U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
+#undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL 
+#undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 
+#undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK 
+#define CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
+#define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT                                        31
+#define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
+
+/*Fractional value for the Feedback value.*/
+#undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL 
+#undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 
+#undef CRF_APB_APLL_FRAC_CFG_DATA_MASK 
+#define CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
+#define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT                                           0
+#define CRF_APB_APLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
+
+/*PLL loop filter resistor control*/
+#undef CRF_APB_DPLL_CFG_RES_DEFVAL 
+#undef CRF_APB_DPLL_CFG_RES_SHIFT 
+#undef CRF_APB_DPLL_CFG_RES_MASK 
+#define CRF_APB_DPLL_CFG_RES_DEFVAL                                                0x00000000
+#define CRF_APB_DPLL_CFG_RES_SHIFT                                                 0
+#define CRF_APB_DPLL_CFG_RES_MASK                                                  0x0000000FU
+
+/*PLL charge pump control*/
+#undef CRF_APB_DPLL_CFG_CP_DEFVAL 
+#undef CRF_APB_DPLL_CFG_CP_SHIFT 
+#undef CRF_APB_DPLL_CFG_CP_MASK 
+#define CRF_APB_DPLL_CFG_CP_DEFVAL                                                 0x00000000
+#define CRF_APB_DPLL_CFG_CP_SHIFT                                                  5
+#define CRF_APB_DPLL_CFG_CP_MASK                                                   0x000001E0U
+
+/*PLL loop filter high frequency capacitor control*/
+#undef CRF_APB_DPLL_CFG_LFHF_DEFVAL 
+#undef CRF_APB_DPLL_CFG_LFHF_SHIFT 
+#undef CRF_APB_DPLL_CFG_LFHF_MASK 
+#define CRF_APB_DPLL_CFG_LFHF_DEFVAL                                               0x00000000
+#define CRF_APB_DPLL_CFG_LFHF_SHIFT                                                10
+#define CRF_APB_DPLL_CFG_LFHF_MASK                                                 0x00000C00U
+
+/*Lock circuit counter setting*/
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK 
+#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
+#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT                                            13
+#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
+
+/*Lock circuit configuration settings for lock windowsize*/
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK 
+#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
+#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT                                            25
+#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
+
+/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK 
+#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL                                           0x00002C09
+#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT                                            20
+#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_DPLL_CTRL_FBDIV_MASK 
+#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_DPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_DPLL_CTRL_DIV2_MASK 
+#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL                                              0x00002C09
+#define CRF_APB_DPLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_DPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
+#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*DPLL is locked*/
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT                                         1
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK                                          0x00000002U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
+#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
+#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL 
+#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 
+#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK 
+#define CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
+#define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT                                        31
+#define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
+
+/*Fractional value for the Feedback value.*/
+#undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL 
+#undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 
+#undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK 
+#define CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
+#define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT                                           0
+#define CRF_APB_DPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
+
+/*PLL loop filter resistor control*/
+#undef CRF_APB_VPLL_CFG_RES_DEFVAL 
+#undef CRF_APB_VPLL_CFG_RES_SHIFT 
+#undef CRF_APB_VPLL_CFG_RES_MASK 
+#define CRF_APB_VPLL_CFG_RES_DEFVAL                                                0x00000000
+#define CRF_APB_VPLL_CFG_RES_SHIFT                                                 0
+#define CRF_APB_VPLL_CFG_RES_MASK                                                  0x0000000FU
+
+/*PLL charge pump control*/
+#undef CRF_APB_VPLL_CFG_CP_DEFVAL 
+#undef CRF_APB_VPLL_CFG_CP_SHIFT 
+#undef CRF_APB_VPLL_CFG_CP_MASK 
+#define CRF_APB_VPLL_CFG_CP_DEFVAL                                                 0x00000000
+#define CRF_APB_VPLL_CFG_CP_SHIFT                                                  5
+#define CRF_APB_VPLL_CFG_CP_MASK                                                   0x000001E0U
+
+/*PLL loop filter high frequency capacitor control*/
+#undef CRF_APB_VPLL_CFG_LFHF_DEFVAL 
+#undef CRF_APB_VPLL_CFG_LFHF_SHIFT 
+#undef CRF_APB_VPLL_CFG_LFHF_MASK 
+#define CRF_APB_VPLL_CFG_LFHF_DEFVAL                                               0x00000000
+#define CRF_APB_VPLL_CFG_LFHF_SHIFT                                                10
+#define CRF_APB_VPLL_CFG_LFHF_MASK                                                 0x00000C00U
+
+/*Lock circuit counter setting*/
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK 
+#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
+#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT                                            13
+#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
+
+/*Lock circuit configuration settings for lock windowsize*/
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK 
+#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
+#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT                                            25
+#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
+
+/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK 
+#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL                                           0x00012809
+#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT                                            20
+#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_VPLL_CTRL_FBDIV_MASK 
+#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_VPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_VPLL_CTRL_DIV2_MASK 
+#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL                                              0x00012809
+#define CRF_APB_VPLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_VPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
+#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*VPLL is locked*/
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT                                         2
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK                                          0x00000004U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
+#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
+#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL 
+#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 
+#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK 
+#define CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
+#define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT                                        31
+#define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
+
+/*Fractional value for the Feedback value.*/
+#undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 
+#undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 
+#undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK 
+#define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
+#define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT                                           0
+#define CRF_APB_VPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
+#undef CRL_APB_GEM0_REF_CTRL_OFFSET 
+#define CRL_APB_GEM0_REF_CTRL_OFFSET                                               0XFF5E0050
+#undef CRL_APB_GEM1_REF_CTRL_OFFSET 
+#define CRL_APB_GEM1_REF_CTRL_OFFSET                                               0XFF5E0054
+#undef CRL_APB_GEM2_REF_CTRL_OFFSET 
+#define CRL_APB_GEM2_REF_CTRL_OFFSET                                               0XFF5E0058
+#undef CRL_APB_GEM3_REF_CTRL_OFFSET 
+#define CRL_APB_GEM3_REF_CTRL_OFFSET                                               0XFF5E005C
+#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET 
+#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET                                            0XFF5E0100
+#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET 
+#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET                                           0XFF5E0060
+#undef CRL_APB_USB1_BUS_REF_CTRL_OFFSET 
+#define CRL_APB_USB1_BUS_REF_CTRL_OFFSET                                           0XFF5E0064
+#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 
+#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET                                          0XFF5E004C
+#undef CRL_APB_QSPI_REF_CTRL_OFFSET 
+#define CRL_APB_QSPI_REF_CTRL_OFFSET                                               0XFF5E0068
+#undef CRL_APB_SDIO0_REF_CTRL_OFFSET 
+#define CRL_APB_SDIO0_REF_CTRL_OFFSET                                              0XFF5E006C
+#undef CRL_APB_SDIO1_REF_CTRL_OFFSET 
+#define CRL_APB_SDIO1_REF_CTRL_OFFSET                                              0XFF5E0070
+#undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET 
+#define IOU_SLCR_SDIO_CLK_CTRL_OFFSET                                              0XFF18030C
+#undef CRL_APB_UART0_REF_CTRL_OFFSET 
+#define CRL_APB_UART0_REF_CTRL_OFFSET                                              0XFF5E0074
+#undef CRL_APB_UART1_REF_CTRL_OFFSET 
+#define CRL_APB_UART1_REF_CTRL_OFFSET                                              0XFF5E0078
+#undef CRL_APB_I2C0_REF_CTRL_OFFSET 
+#define CRL_APB_I2C0_REF_CTRL_OFFSET                                               0XFF5E0120
+#undef CRL_APB_I2C1_REF_CTRL_OFFSET 
+#define CRL_APB_I2C1_REF_CTRL_OFFSET                                               0XFF5E0124
+#undef CRL_APB_SPI0_REF_CTRL_OFFSET 
+#define CRL_APB_SPI0_REF_CTRL_OFFSET                                               0XFF5E007C
+#undef CRL_APB_SPI1_REF_CTRL_OFFSET 
+#define CRL_APB_SPI1_REF_CTRL_OFFSET                                               0XFF5E0080
+#undef CRL_APB_CAN0_REF_CTRL_OFFSET 
+#define CRL_APB_CAN0_REF_CTRL_OFFSET                                               0XFF5E0084
+#undef CRL_APB_CAN1_REF_CTRL_OFFSET 
+#define CRL_APB_CAN1_REF_CTRL_OFFSET                                               0XFF5E0088
+#undef CRL_APB_CPU_R5_CTRL_OFFSET 
+#define CRL_APB_CPU_R5_CTRL_OFFSET                                                 0XFF5E0090
+#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET 
+#define CRL_APB_IOU_SWITCH_CTRL_OFFSET                                             0XFF5E009C
+#undef CRL_APB_CSU_PLL_CTRL_OFFSET 
+#define CRL_APB_CSU_PLL_CTRL_OFFSET                                                0XFF5E00A0
+#undef CRL_APB_PCAP_CTRL_OFFSET 
+#define CRL_APB_PCAP_CTRL_OFFSET                                                   0XFF5E00A4
+#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET 
+#define CRL_APB_LPD_SWITCH_CTRL_OFFSET                                             0XFF5E00A8
+#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET 
+#define CRL_APB_LPD_LSBUS_CTRL_OFFSET                                              0XFF5E00AC
+#undef CRL_APB_DBG_LPD_CTRL_OFFSET 
+#define CRL_APB_DBG_LPD_CTRL_OFFSET                                                0XFF5E00B0
+#undef CRL_APB_NAND_REF_CTRL_OFFSET 
+#define CRL_APB_NAND_REF_CTRL_OFFSET                                               0XFF5E00B4
+#undef CRL_APB_ADMA_REF_CTRL_OFFSET 
+#define CRL_APB_ADMA_REF_CTRL_OFFSET                                               0XFF5E00B8
+#undef CRL_APB_PL0_REF_CTRL_OFFSET 
+#define CRL_APB_PL0_REF_CTRL_OFFSET                                                0XFF5E00C0
+#undef CRL_APB_PL1_REF_CTRL_OFFSET 
+#define CRL_APB_PL1_REF_CTRL_OFFSET                                                0XFF5E00C4
+#undef CRL_APB_PL2_REF_CTRL_OFFSET 
+#define CRL_APB_PL2_REF_CTRL_OFFSET                                                0XFF5E00C8
+#undef CRL_APB_PL3_REF_CTRL_OFFSET 
+#define CRL_APB_PL3_REF_CTRL_OFFSET                                                0XFF5E00CC
+#undef CRL_APB_AMS_REF_CTRL_OFFSET 
+#define CRL_APB_AMS_REF_CTRL_OFFSET                                                0XFF5E0108
+#undef CRL_APB_DLL_REF_CTRL_OFFSET 
+#define CRL_APB_DLL_REF_CTRL_OFFSET                                                0XFF5E0104
+#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 
+#define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET                                          0XFF5E0128
+#undef CRF_APB_SATA_REF_CTRL_OFFSET 
+#define CRF_APB_SATA_REF_CTRL_OFFSET                                               0XFD1A00A0
+#undef CRF_APB_PCIE_REF_CTRL_OFFSET 
+#define CRF_APB_PCIE_REF_CTRL_OFFSET                                               0XFD1A00B4
+#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 
+#define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET                                           0XFD1A0070
+#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 
+#define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET                                           0XFD1A0074
+#undef CRF_APB_DP_STC_REF_CTRL_OFFSET 
+#define CRF_APB_DP_STC_REF_CTRL_OFFSET                                             0XFD1A007C
+#undef CRF_APB_ACPU_CTRL_OFFSET 
+#define CRF_APB_ACPU_CTRL_OFFSET                                                   0XFD1A0060
+#undef CRF_APB_DBG_TRACE_CTRL_OFFSET 
+#define CRF_APB_DBG_TRACE_CTRL_OFFSET                                              0XFD1A0064
+#undef CRF_APB_DBG_FPD_CTRL_OFFSET 
+#define CRF_APB_DBG_FPD_CTRL_OFFSET                                                0XFD1A0068
+#undef CRF_APB_DDR_CTRL_OFFSET 
+#define CRF_APB_DDR_CTRL_OFFSET                                                    0XFD1A0080
+#undef CRF_APB_GPU_REF_CTRL_OFFSET 
+#define CRF_APB_GPU_REF_CTRL_OFFSET                                                0XFD1A0084
+#undef CRF_APB_GDMA_REF_CTRL_OFFSET 
+#define CRF_APB_GDMA_REF_CTRL_OFFSET                                               0XFD1A00B8
+#undef CRF_APB_DPDMA_REF_CTRL_OFFSET 
+#define CRF_APB_DPDMA_REF_CTRL_OFFSET                                              0XFD1A00BC
+#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET 
+#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET                                             0XFD1A00C0
+#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 
+#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET                                            0XFD1A00C4
+#undef CRF_APB_GTGREF0_REF_CTRL_OFFSET 
+#define CRF_APB_GTGREF0_REF_CTRL_OFFSET                                            0XFD1A00C8
+#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET 
+#define CRF_APB_DBG_TSTMP_CTRL_OFFSET                                              0XFD1A00F8
+#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 
+#define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET                                            0XFF180380
+#undef FPD_SLCR_WDT_CLK_SEL_OFFSET 
+#define FPD_SLCR_WDT_CLK_SEL_OFFSET                                                0XFD610100
+#undef IOU_SLCR_WDT_CLK_SEL_OFFSET 
+#define IOU_SLCR_WDT_CLK_SEL_OFFSET                                                0XFF180300
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET                                         0XFF410050
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL                                   0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT                                    8
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL                                     0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT                                      0
+#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK                                       0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL                                   0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT                                    16
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK                                     0x003F0000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL                                     0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT                                      24
+#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK                                       0x01000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL                                    0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT                                     25
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK                                      0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL                                  0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL                                  0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL                                    0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL                                    0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT                                     25
+#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK                                      0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL                                  0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL                                  0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL                                    0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL                                   0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT                                    25
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK                                     0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL                                 0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT                                  16
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK                                   0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL                                 0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT                                  8
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL                                   0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT                                    0
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK                                     0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL                                        0x01000800
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000800
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000800
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL                                        0x01000800
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]*/
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 
+#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL                             0x00000000
+#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT                              17
+#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK                               0x00020000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
+		d lead to system hang*/
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK 
+#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL                                          0x03000600
+#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT                                           24
+#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK                                            0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL                                        0x03000600
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT                                         8
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK                                          0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL                                          0x03000600
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT                                           0
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK                                            0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL                                      0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT                                       24
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT                                       0
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CSU_PLL_CTRL_CLKACT_MASK 
+#define CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL                                         0x01001500
+#define CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_CSU_PLL_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL                                       0x01001500
+#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK 
+#define CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL                                         0x01001500
+#define CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PCAP_CTRL_CLKACT_MASK 
+#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL                                            0x00001500
+#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT                                             24
+#define CRL_APB_PCAP_CTRL_CLKACT_MASK                                              0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL                                          0x00001500
+#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT                                           8
+#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK                                            0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK 
+#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL                                            0x00001500
+#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT                                             0
+#define CRL_APB_PCAP_CTRL_SRCSEL_MASK                                              0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL                                      0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT                                       24
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT                                       0
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL                                         0x01002000
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL                                       0x01002000
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL                                         0x01002000
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL                                        0x00052000
+#define CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_NAND_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL                                      0x00052000
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL                                      0x00052000
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL                                        0x00052000
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL                                        0x00002000
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002000
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL                                        0x00002000
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
+#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
+#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
+#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
+#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
+#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
+#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
+#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
+#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
+#define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_PL2_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
+#define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
+#define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
+#define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
+#define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_PL3_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
+#define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
+#define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
+#define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL                                       0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL                                       0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL                                         0x01001800
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL                                         0x01001800
+#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
+		is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL                                         0x00000000
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL                                 0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT                                  8
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
+
+/*1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 
+		 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL                                   0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT                                    0
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK                                     0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL                                   0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT                                    24
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK                                     0x01000000U
+
+/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL                                        0x01001600
+#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL                                        0x01001600
+#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001600
+#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
+		es of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL                                        0x00001500
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL                                        0x00001500
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL                                      0x00001500
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 
+		ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL                                    0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL                                    0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT                                     24
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK                                      0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 
+		ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL                                    0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL                                    0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT                                     24
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK                                      0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL                                    0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT                                     16
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK                                      0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL                                    0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT                                     8
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
+		e new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL                                      0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT                                       0
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL                                      0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT                                       24
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK 
+#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL                                          0x03000400
+#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT                                           8
+#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK                                            0x00003F00U
+
+/*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK 
+#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL                                            0x03000400
+#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT                                             0
+#define CRF_APB_ACPU_CTRL_SRCSEL_MASK                                              0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL                                       0x03000400
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT                                        25
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK                                         0x02000000U
+
+/*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
+		 to the entire APU*/
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL                                       0x03000400
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT                                        24
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL                                     0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL                                       0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL                                       0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT                                        24
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL                                       0x01002500
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT                                        8
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL                                         0x01002500
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT                                          0
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL                                         0x01002500
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT                                          24
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL                                           0x01000500
+#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT                                            8
+#define CRF_APB_DDR_CTRL_DIVISOR0_MASK                                             0x00003F00U
+
+/*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This 
+		s not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DDR_CTRL_SRCSEL_MASK 
+#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL                                             0x01000500
+#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT                                              0
+#define CRF_APB_DDR_CTRL_SRCSEL_MASK                                               0x00000007U
+
+/*6 bit divider*/
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL                                       0x00001500
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL                                         0x00001500
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).*/
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL                                         0x00001500
+#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL                                     0x00001500
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT                                      25
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK                                       0x02000000U
+
+/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL                                     0x00001500
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT                                      26
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK                                       0x04000000U
+
+/*6 bit divider*/
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL                                       0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL                                       0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL                                    0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT                                     8
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL                                      0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT                                       0
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL                                      0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT                                       24
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL                                   0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL                                     0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT                                      0
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK                                       0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL                                     0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT                                      24
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK                                       0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL                                   0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL                                     0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT                                      0
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK                                       0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL                                     0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT                                      24
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK                                       0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL                                     0x00000A00
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL                                       0x00000A00
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
+		0" = Select the R5 clock for the APB interface of TTC0*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT                                    0
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK                                     0x00000003U
+
+/*00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
+		0" = Select the R5 clock for the APB interface of TTC1*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT                                    2
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK                                     0x0000000CU
+
+/*00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
+		0" = Select the R5 clock for the APB interface of TTC2*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT                                    4
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK                                     0x00000030U
+
+/*00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
+		0" = Select the R5 clock for the APB interface of TTC3*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT                                    6
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK                                     0x000000C0U
+
+/*System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)*/
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 
+#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                                         0x00000000
+#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT                                          0
+#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK                                           0x00000001U
+
+/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout 
+		ia MIO*/
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 
+#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                                         0x00000000
+#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT                                          0
+#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK                                           0x00000001U
+
+/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk*/
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL                                  0x00000000
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT                                   0
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK                                    0x00000001U
+#undef CRF_APB_RST_DDR_SS_OFFSET 
+#define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
+#undef DDRC_MSTR_OFFSET 
+#define DDRC_MSTR_OFFSET                                                           0XFD070000
+#undef DDRC_MRCTRL0_OFFSET 
+#define DDRC_MRCTRL0_OFFSET                                                        0XFD070010
+#undef DDRC_DERATEEN_OFFSET 
+#define DDRC_DERATEEN_OFFSET                                                       0XFD070020
+#undef DDRC_DERATEINT_OFFSET 
+#define DDRC_DERATEINT_OFFSET                                                      0XFD070024
+#undef DDRC_PWRCTL_OFFSET 
+#define DDRC_PWRCTL_OFFSET                                                         0XFD070030
+#undef DDRC_PWRTMG_OFFSET 
+#define DDRC_PWRTMG_OFFSET                                                         0XFD070034
+#undef DDRC_RFSHCTL0_OFFSET 
+#define DDRC_RFSHCTL0_OFFSET                                                       0XFD070050
+#undef DDRC_RFSHCTL3_OFFSET 
+#define DDRC_RFSHCTL3_OFFSET                                                       0XFD070060
+#undef DDRC_RFSHTMG_OFFSET 
+#define DDRC_RFSHTMG_OFFSET                                                        0XFD070064
+#undef DDRC_ECCCFG0_OFFSET 
+#define DDRC_ECCCFG0_OFFSET                                                        0XFD070070
+#undef DDRC_ECCCFG1_OFFSET 
+#define DDRC_ECCCFG1_OFFSET                                                        0XFD070074
+#undef DDRC_CRCPARCTL1_OFFSET 
+#define DDRC_CRCPARCTL1_OFFSET                                                     0XFD0700C4
+#undef DDRC_CRCPARCTL2_OFFSET 
+#define DDRC_CRCPARCTL2_OFFSET                                                     0XFD0700C8
+#undef DDRC_INIT0_OFFSET 
+#define DDRC_INIT0_OFFSET                                                          0XFD0700D0
+#undef DDRC_INIT1_OFFSET 
+#define DDRC_INIT1_OFFSET                                                          0XFD0700D4
+#undef DDRC_INIT2_OFFSET 
+#define DDRC_INIT2_OFFSET                                                          0XFD0700D8
+#undef DDRC_INIT3_OFFSET 
+#define DDRC_INIT3_OFFSET                                                          0XFD0700DC
+#undef DDRC_INIT4_OFFSET 
+#define DDRC_INIT4_OFFSET                                                          0XFD0700E0
+#undef DDRC_INIT5_OFFSET 
+#define DDRC_INIT5_OFFSET                                                          0XFD0700E4
+#undef DDRC_INIT6_OFFSET 
+#define DDRC_INIT6_OFFSET                                                          0XFD0700E8
+#undef DDRC_INIT7_OFFSET 
+#define DDRC_INIT7_OFFSET                                                          0XFD0700EC
+#undef DDRC_DIMMCTL_OFFSET 
+#define DDRC_DIMMCTL_OFFSET                                                        0XFD0700F0
+#undef DDRC_RANKCTL_OFFSET 
+#define DDRC_RANKCTL_OFFSET                                                        0XFD0700F4
+#undef DDRC_DRAMTMG0_OFFSET 
+#define DDRC_DRAMTMG0_OFFSET                                                       0XFD070100
+#undef DDRC_DRAMTMG1_OFFSET 
+#define DDRC_DRAMTMG1_OFFSET                                                       0XFD070104
+#undef DDRC_DRAMTMG2_OFFSET 
+#define DDRC_DRAMTMG2_OFFSET                                                       0XFD070108
+#undef DDRC_DRAMTMG3_OFFSET 
+#define DDRC_DRAMTMG3_OFFSET                                                       0XFD07010C
+#undef DDRC_DRAMTMG4_OFFSET 
+#define DDRC_DRAMTMG4_OFFSET                                                       0XFD070110
+#undef DDRC_DRAMTMG5_OFFSET 
+#define DDRC_DRAMTMG5_OFFSET                                                       0XFD070114
+#undef DDRC_DRAMTMG6_OFFSET 
+#define DDRC_DRAMTMG6_OFFSET                                                       0XFD070118
+#undef DDRC_DRAMTMG7_OFFSET 
+#define DDRC_DRAMTMG7_OFFSET                                                       0XFD07011C
+#undef DDRC_DRAMTMG8_OFFSET 
+#define DDRC_DRAMTMG8_OFFSET                                                       0XFD070120
+#undef DDRC_DRAMTMG9_OFFSET 
+#define DDRC_DRAMTMG9_OFFSET                                                       0XFD070124
+#undef DDRC_DRAMTMG11_OFFSET 
+#define DDRC_DRAMTMG11_OFFSET                                                      0XFD07012C
+#undef DDRC_DRAMTMG12_OFFSET 
+#define DDRC_DRAMTMG12_OFFSET                                                      0XFD070130
+#undef DDRC_ZQCTL0_OFFSET 
+#define DDRC_ZQCTL0_OFFSET                                                         0XFD070180
+#undef DDRC_ZQCTL1_OFFSET 
+#define DDRC_ZQCTL1_OFFSET                                                         0XFD070184
+#undef DDRC_DFITMG0_OFFSET 
+#define DDRC_DFITMG0_OFFSET                                                        0XFD070190
+#undef DDRC_DFITMG1_OFFSET 
+#define DDRC_DFITMG1_OFFSET                                                        0XFD070194
+#undef DDRC_DFILPCFG0_OFFSET 
+#define DDRC_DFILPCFG0_OFFSET                                                      0XFD070198
+#undef DDRC_DFILPCFG1_OFFSET 
+#define DDRC_DFILPCFG1_OFFSET                                                      0XFD07019C
+#undef DDRC_DFIUPD1_OFFSET 
+#define DDRC_DFIUPD1_OFFSET                                                        0XFD0701A4
+#undef DDRC_DFIMISC_OFFSET 
+#define DDRC_DFIMISC_OFFSET                                                        0XFD0701B0
+#undef DDRC_DFITMG2_OFFSET 
+#define DDRC_DFITMG2_OFFSET                                                        0XFD0701B4
+#undef DDRC_DBICTL_OFFSET 
+#define DDRC_DBICTL_OFFSET                                                         0XFD0701C0
+#undef DDRC_ADDRMAP0_OFFSET 
+#define DDRC_ADDRMAP0_OFFSET                                                       0XFD070200
+#undef DDRC_ADDRMAP1_OFFSET 
+#define DDRC_ADDRMAP1_OFFSET                                                       0XFD070204
+#undef DDRC_ADDRMAP2_OFFSET 
+#define DDRC_ADDRMAP2_OFFSET                                                       0XFD070208
+#undef DDRC_ADDRMAP3_OFFSET 
+#define DDRC_ADDRMAP3_OFFSET                                                       0XFD07020C
+#undef DDRC_ADDRMAP4_OFFSET 
+#define DDRC_ADDRMAP4_OFFSET                                                       0XFD070210
+#undef DDRC_ADDRMAP5_OFFSET 
+#define DDRC_ADDRMAP5_OFFSET                                                       0XFD070214
+#undef DDRC_ADDRMAP6_OFFSET 
+#define DDRC_ADDRMAP6_OFFSET                                                       0XFD070218
+#undef DDRC_ADDRMAP7_OFFSET 
+#define DDRC_ADDRMAP7_OFFSET                                                       0XFD07021C
+#undef DDRC_ADDRMAP8_OFFSET 
+#define DDRC_ADDRMAP8_OFFSET                                                       0XFD070220
+#undef DDRC_ADDRMAP9_OFFSET 
+#define DDRC_ADDRMAP9_OFFSET                                                       0XFD070224
+#undef DDRC_ADDRMAP10_OFFSET 
+#define DDRC_ADDRMAP10_OFFSET                                                      0XFD070228
+#undef DDRC_ADDRMAP11_OFFSET 
+#define DDRC_ADDRMAP11_OFFSET                                                      0XFD07022C
+#undef DDRC_ODTCFG_OFFSET 
+#define DDRC_ODTCFG_OFFSET                                                         0XFD070240
+#undef DDRC_ODTMAP_OFFSET 
+#define DDRC_ODTMAP_OFFSET                                                         0XFD070244
+#undef DDRC_SCHED_OFFSET 
+#define DDRC_SCHED_OFFSET                                                          0XFD070250
+#undef DDRC_PERFLPR1_OFFSET 
+#define DDRC_PERFLPR1_OFFSET                                                       0XFD070264
+#undef DDRC_PERFWR1_OFFSET 
+#define DDRC_PERFWR1_OFFSET                                                        0XFD07026C
+#undef DDRC_DQMAP5_OFFSET 
+#define DDRC_DQMAP5_OFFSET                                                         0XFD070294
+#undef DDRC_DBG0_OFFSET 
+#define DDRC_DBG0_OFFSET                                                           0XFD070300
+#undef DDRC_DBGCMD_OFFSET 
+#define DDRC_DBGCMD_OFFSET                                                         0XFD07030C
+#undef DDRC_SWCTL_OFFSET 
+#define DDRC_SWCTL_OFFSET                                                          0XFD070320
+#undef DDRC_PCCFG_OFFSET 
+#define DDRC_PCCFG_OFFSET                                                          0XFD070400
+#undef DDRC_PCFGR_0_OFFSET 
+#define DDRC_PCFGR_0_OFFSET                                                        0XFD070404
+#undef DDRC_PCFGW_0_OFFSET 
+#define DDRC_PCFGW_0_OFFSET                                                        0XFD070408
+#undef DDRC_PCTRL_0_OFFSET 
+#define DDRC_PCTRL_0_OFFSET                                                        0XFD070490
+#undef DDRC_PCFGQOS0_0_OFFSET 
+#define DDRC_PCFGQOS0_0_OFFSET                                                     0XFD070494
+#undef DDRC_PCFGQOS1_0_OFFSET 
+#define DDRC_PCFGQOS1_0_OFFSET                                                     0XFD070498
+#undef DDRC_PCFGR_1_OFFSET 
+#define DDRC_PCFGR_1_OFFSET                                                        0XFD0704B4
+#undef DDRC_PCFGW_1_OFFSET 
+#define DDRC_PCFGW_1_OFFSET                                                        0XFD0704B8
+#undef DDRC_PCTRL_1_OFFSET 
+#define DDRC_PCTRL_1_OFFSET                                                        0XFD070540
+#undef DDRC_PCFGQOS0_1_OFFSET 
+#define DDRC_PCFGQOS0_1_OFFSET                                                     0XFD070544
+#undef DDRC_PCFGQOS1_1_OFFSET 
+#define DDRC_PCFGQOS1_1_OFFSET                                                     0XFD070548
+#undef DDRC_PCFGR_2_OFFSET 
+#define DDRC_PCFGR_2_OFFSET                                                        0XFD070564
+#undef DDRC_PCFGW_2_OFFSET 
+#define DDRC_PCFGW_2_OFFSET                                                        0XFD070568
+#undef DDRC_PCTRL_2_OFFSET 
+#define DDRC_PCTRL_2_OFFSET                                                        0XFD0705F0
+#undef DDRC_PCFGQOS0_2_OFFSET 
+#define DDRC_PCFGQOS0_2_OFFSET                                                     0XFD0705F4
+#undef DDRC_PCFGQOS1_2_OFFSET 
+#define DDRC_PCFGQOS1_2_OFFSET                                                     0XFD0705F8
+#undef DDRC_PCFGR_3_OFFSET 
+#define DDRC_PCFGR_3_OFFSET                                                        0XFD070614
+#undef DDRC_PCFGW_3_OFFSET 
+#define DDRC_PCFGW_3_OFFSET                                                        0XFD070618
+#undef DDRC_PCTRL_3_OFFSET 
+#define DDRC_PCTRL_3_OFFSET                                                        0XFD0706A0
+#undef DDRC_PCFGQOS0_3_OFFSET 
+#define DDRC_PCFGQOS0_3_OFFSET                                                     0XFD0706A4
+#undef DDRC_PCFGQOS1_3_OFFSET 
+#define DDRC_PCFGQOS1_3_OFFSET                                                     0XFD0706A8
+#undef DDRC_PCFGWQOS0_3_OFFSET 
+#define DDRC_PCFGWQOS0_3_OFFSET                                                    0XFD0706AC
+#undef DDRC_PCFGWQOS1_3_OFFSET 
+#define DDRC_PCFGWQOS1_3_OFFSET                                                    0XFD0706B0
+#undef DDRC_PCFGR_4_OFFSET 
+#define DDRC_PCFGR_4_OFFSET                                                        0XFD0706C4
+#undef DDRC_PCFGW_4_OFFSET 
+#define DDRC_PCFGW_4_OFFSET                                                        0XFD0706C8
+#undef DDRC_PCTRL_4_OFFSET 
+#define DDRC_PCTRL_4_OFFSET                                                        0XFD070750
+#undef DDRC_PCFGQOS0_4_OFFSET 
+#define DDRC_PCFGQOS0_4_OFFSET                                                     0XFD070754
+#undef DDRC_PCFGQOS1_4_OFFSET 
+#define DDRC_PCFGQOS1_4_OFFSET                                                     0XFD070758
+#undef DDRC_PCFGWQOS0_4_OFFSET 
+#define DDRC_PCFGWQOS0_4_OFFSET                                                    0XFD07075C
+#undef DDRC_PCFGWQOS1_4_OFFSET 
+#define DDRC_PCFGWQOS1_4_OFFSET                                                    0XFD070760
+#undef DDRC_PCFGR_5_OFFSET 
+#define DDRC_PCFGR_5_OFFSET                                                        0XFD070774
+#undef DDRC_PCFGW_5_OFFSET 
+#define DDRC_PCFGW_5_OFFSET                                                        0XFD070778
+#undef DDRC_PCTRL_5_OFFSET 
+#define DDRC_PCTRL_5_OFFSET                                                        0XFD070800
+#undef DDRC_PCFGQOS0_5_OFFSET 
+#define DDRC_PCFGQOS0_5_OFFSET                                                     0XFD070804
+#undef DDRC_PCFGQOS1_5_OFFSET 
+#define DDRC_PCFGQOS1_5_OFFSET                                                     0XFD070808
+#undef DDRC_PCFGWQOS0_5_OFFSET 
+#define DDRC_PCFGWQOS0_5_OFFSET                                                    0XFD07080C
+#undef DDRC_PCFGWQOS1_5_OFFSET 
+#define DDRC_PCFGWQOS1_5_OFFSET                                                    0XFD070810
+#undef DDRC_SARBASE0_OFFSET 
+#define DDRC_SARBASE0_OFFSET                                                       0XFD070F04
+#undef DDRC_SARSIZE0_OFFSET 
+#define DDRC_SARSIZE0_OFFSET                                                       0XFD070F08
+#undef DDRC_SARBASE1_OFFSET 
+#define DDRC_SARBASE1_OFFSET                                                       0XFD070F0C
+#undef DDRC_SARSIZE1_OFFSET 
+#define DDRC_SARSIZE1_OFFSET                                                       0XFD070F10
+#undef DDRC_DFITMG0_SHADOW_OFFSET 
+#define DDRC_DFITMG0_SHADOW_OFFSET                                                 0XFD072190
+#undef CRF_APB_RST_DDR_SS_OFFSET 
+#define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
+#undef DDR_PHY_PGCR0_OFFSET 
+#define DDR_PHY_PGCR0_OFFSET                                                       0XFD080010
+#undef DDR_PHY_PGCR2_OFFSET 
+#define DDR_PHY_PGCR2_OFFSET                                                       0XFD080018
+#undef DDR_PHY_PGCR5_OFFSET 
+#define DDR_PHY_PGCR5_OFFSET                                                       0XFD080024
+#undef DDR_PHY_PTR0_OFFSET 
+#define DDR_PHY_PTR0_OFFSET                                                        0XFD080040
+#undef DDR_PHY_PTR1_OFFSET 
+#define DDR_PHY_PTR1_OFFSET                                                        0XFD080044
+#undef DDR_PHY_DSGCR_OFFSET 
+#define DDR_PHY_DSGCR_OFFSET                                                       0XFD080090
+#undef DDR_PHY_DCR_OFFSET 
+#define DDR_PHY_DCR_OFFSET                                                         0XFD080100
+#undef DDR_PHY_DTPR0_OFFSET 
+#define DDR_PHY_DTPR0_OFFSET                                                       0XFD080110
+#undef DDR_PHY_DTPR1_OFFSET 
+#define DDR_PHY_DTPR1_OFFSET                                                       0XFD080114
+#undef DDR_PHY_DTPR2_OFFSET 
+#define DDR_PHY_DTPR2_OFFSET                                                       0XFD080118
+#undef DDR_PHY_DTPR3_OFFSET 
+#define DDR_PHY_DTPR3_OFFSET                                                       0XFD08011C
+#undef DDR_PHY_DTPR4_OFFSET 
+#define DDR_PHY_DTPR4_OFFSET                                                       0XFD080120
+#undef DDR_PHY_DTPR5_OFFSET 
+#define DDR_PHY_DTPR5_OFFSET                                                       0XFD080124
+#undef DDR_PHY_DTPR6_OFFSET 
+#define DDR_PHY_DTPR6_OFFSET                                                       0XFD080128
+#undef DDR_PHY_RDIMMGCR0_OFFSET 
+#define DDR_PHY_RDIMMGCR0_OFFSET                                                   0XFD080140
+#undef DDR_PHY_RDIMMGCR1_OFFSET 
+#define DDR_PHY_RDIMMGCR1_OFFSET                                                   0XFD080144
+#undef DDR_PHY_RDIMMCR1_OFFSET 
+#define DDR_PHY_RDIMMCR1_OFFSET                                                    0XFD080154
+#undef DDR_PHY_MR0_OFFSET 
+#define DDR_PHY_MR0_OFFSET                                                         0XFD080180
+#undef DDR_PHY_MR1_OFFSET 
+#define DDR_PHY_MR1_OFFSET                                                         0XFD080184
+#undef DDR_PHY_MR2_OFFSET 
+#define DDR_PHY_MR2_OFFSET                                                         0XFD080188
+#undef DDR_PHY_MR3_OFFSET 
+#define DDR_PHY_MR3_OFFSET                                                         0XFD08018C
+#undef DDR_PHY_MR4_OFFSET 
+#define DDR_PHY_MR4_OFFSET                                                         0XFD080190
+#undef DDR_PHY_MR5_OFFSET 
+#define DDR_PHY_MR5_OFFSET                                                         0XFD080194
+#undef DDR_PHY_MR6_OFFSET 
+#define DDR_PHY_MR6_OFFSET                                                         0XFD080198
+#undef DDR_PHY_MR11_OFFSET 
+#define DDR_PHY_MR11_OFFSET                                                        0XFD0801AC
+#undef DDR_PHY_MR12_OFFSET 
+#define DDR_PHY_MR12_OFFSET                                                        0XFD0801B0
+#undef DDR_PHY_MR13_OFFSET 
+#define DDR_PHY_MR13_OFFSET                                                        0XFD0801B4
+#undef DDR_PHY_MR14_OFFSET 
+#define DDR_PHY_MR14_OFFSET                                                        0XFD0801B8
+#undef DDR_PHY_MR22_OFFSET 
+#define DDR_PHY_MR22_OFFSET                                                        0XFD0801D8
+#undef DDR_PHY_DTCR0_OFFSET 
+#define DDR_PHY_DTCR0_OFFSET                                                       0XFD080200
+#undef DDR_PHY_DTCR1_OFFSET 
+#define DDR_PHY_DTCR1_OFFSET                                                       0XFD080204
+#undef DDR_PHY_CATR0_OFFSET 
+#define DDR_PHY_CATR0_OFFSET                                                       0XFD080240
+#undef DDR_PHY_RIOCR5_OFFSET 
+#define DDR_PHY_RIOCR5_OFFSET                                                      0XFD0804F4
+#undef DDR_PHY_ACIOCR0_OFFSET 
+#define DDR_PHY_ACIOCR0_OFFSET                                                     0XFD080500
+#undef DDR_PHY_ACIOCR2_OFFSET 
+#define DDR_PHY_ACIOCR2_OFFSET                                                     0XFD080508
+#undef DDR_PHY_ACIOCR3_OFFSET 
+#define DDR_PHY_ACIOCR3_OFFSET                                                     0XFD08050C
+#undef DDR_PHY_ACIOCR4_OFFSET 
+#define DDR_PHY_ACIOCR4_OFFSET                                                     0XFD080510
+#undef DDR_PHY_IOVCR0_OFFSET 
+#define DDR_PHY_IOVCR0_OFFSET                                                      0XFD080520
+#undef DDR_PHY_VTCR0_OFFSET 
+#define DDR_PHY_VTCR0_OFFSET                                                       0XFD080528
+#undef DDR_PHY_VTCR1_OFFSET 
+#define DDR_PHY_VTCR1_OFFSET                                                       0XFD08052C
+#undef DDR_PHY_ACBDLR6_OFFSET 
+#define DDR_PHY_ACBDLR6_OFFSET                                                     0XFD080558
+#undef DDR_PHY_ACBDLR7_OFFSET 
+#define DDR_PHY_ACBDLR7_OFFSET                                                     0XFD08055C
+#undef DDR_PHY_ACBDLR8_OFFSET 
+#define DDR_PHY_ACBDLR8_OFFSET                                                     0XFD080560
+#undef DDR_PHY_ZQCR_OFFSET 
+#define DDR_PHY_ZQCR_OFFSET                                                        0XFD080680
+#undef DDR_PHY_ZQ0PR0_OFFSET 
+#define DDR_PHY_ZQ0PR0_OFFSET                                                      0XFD080684
+#undef DDR_PHY_ZQ0OR0_OFFSET 
+#define DDR_PHY_ZQ0OR0_OFFSET                                                      0XFD080694
+#undef DDR_PHY_ZQ0OR1_OFFSET 
+#define DDR_PHY_ZQ0OR1_OFFSET                                                      0XFD080698
+#undef DDR_PHY_ZQ1PR0_OFFSET 
+#define DDR_PHY_ZQ1PR0_OFFSET                                                      0XFD0806A4
+#undef DDR_PHY_DX0GCR0_OFFSET 
+#define DDR_PHY_DX0GCR0_OFFSET                                                     0XFD080700
+#undef DDR_PHY_DX0GCR4_OFFSET 
+#define DDR_PHY_DX0GCR4_OFFSET                                                     0XFD080710
+#undef DDR_PHY_DX0GCR5_OFFSET 
+#define DDR_PHY_DX0GCR5_OFFSET                                                     0XFD080714
+#undef DDR_PHY_DX0GCR6_OFFSET 
+#define DDR_PHY_DX0GCR6_OFFSET                                                     0XFD080718
+#undef DDR_PHY_DX0LCDLR2_OFFSET 
+#define DDR_PHY_DX0LCDLR2_OFFSET                                                   0XFD080788
+#undef DDR_PHY_DX0GTR0_OFFSET 
+#define DDR_PHY_DX0GTR0_OFFSET                                                     0XFD0807C0
+#undef DDR_PHY_DX1GCR0_OFFSET 
+#define DDR_PHY_DX1GCR0_OFFSET                                                     0XFD080800
+#undef DDR_PHY_DX1GCR4_OFFSET 
+#define DDR_PHY_DX1GCR4_OFFSET                                                     0XFD080810
+#undef DDR_PHY_DX1GCR5_OFFSET 
+#define DDR_PHY_DX1GCR5_OFFSET                                                     0XFD080814
+#undef DDR_PHY_DX1GCR6_OFFSET 
+#define DDR_PHY_DX1GCR6_OFFSET                                                     0XFD080818
+#undef DDR_PHY_DX1LCDLR2_OFFSET 
+#define DDR_PHY_DX1LCDLR2_OFFSET                                                   0XFD080888
+#undef DDR_PHY_DX1GTR0_OFFSET 
+#define DDR_PHY_DX1GTR0_OFFSET                                                     0XFD0808C0
+#undef DDR_PHY_DX2GCR0_OFFSET 
+#define DDR_PHY_DX2GCR0_OFFSET                                                     0XFD080900
+#undef DDR_PHY_DX2GCR1_OFFSET 
+#define DDR_PHY_DX2GCR1_OFFSET                                                     0XFD080904
+#undef DDR_PHY_DX2GCR4_OFFSET 
+#define DDR_PHY_DX2GCR4_OFFSET                                                     0XFD080910
+#undef DDR_PHY_DX2GCR5_OFFSET 
+#define DDR_PHY_DX2GCR5_OFFSET                                                     0XFD080914
+#undef DDR_PHY_DX2GCR6_OFFSET 
+#define DDR_PHY_DX2GCR6_OFFSET                                                     0XFD080918
+#undef DDR_PHY_DX2LCDLR2_OFFSET 
+#define DDR_PHY_DX2LCDLR2_OFFSET                                                   0XFD080988
+#undef DDR_PHY_DX2GTR0_OFFSET 
+#define DDR_PHY_DX2GTR0_OFFSET                                                     0XFD0809C0
+#undef DDR_PHY_DX3GCR0_OFFSET 
+#define DDR_PHY_DX3GCR0_OFFSET                                                     0XFD080A00
+#undef DDR_PHY_DX3GCR1_OFFSET 
+#define DDR_PHY_DX3GCR1_OFFSET                                                     0XFD080A04
+#undef DDR_PHY_DX3GCR4_OFFSET 
+#define DDR_PHY_DX3GCR4_OFFSET                                                     0XFD080A10
+#undef DDR_PHY_DX3GCR5_OFFSET 
+#define DDR_PHY_DX3GCR5_OFFSET                                                     0XFD080A14
+#undef DDR_PHY_DX3GCR6_OFFSET 
+#define DDR_PHY_DX3GCR6_OFFSET                                                     0XFD080A18
+#undef DDR_PHY_DX3LCDLR2_OFFSET 
+#define DDR_PHY_DX3LCDLR2_OFFSET                                                   0XFD080A88
+#undef DDR_PHY_DX3GTR0_OFFSET 
+#define DDR_PHY_DX3GTR0_OFFSET                                                     0XFD080AC0
+#undef DDR_PHY_DX4GCR0_OFFSET 
+#define DDR_PHY_DX4GCR0_OFFSET                                                     0XFD080B00
+#undef DDR_PHY_DX4GCR1_OFFSET 
+#define DDR_PHY_DX4GCR1_OFFSET                                                     0XFD080B04
+#undef DDR_PHY_DX4GCR4_OFFSET 
+#define DDR_PHY_DX4GCR4_OFFSET                                                     0XFD080B10
+#undef DDR_PHY_DX4GCR5_OFFSET 
+#define DDR_PHY_DX4GCR5_OFFSET                                                     0XFD080B14
+#undef DDR_PHY_DX4GCR6_OFFSET 
+#define DDR_PHY_DX4GCR6_OFFSET                                                     0XFD080B18
+#undef DDR_PHY_DX4LCDLR2_OFFSET 
+#define DDR_PHY_DX4LCDLR2_OFFSET                                                   0XFD080B88
+#undef DDR_PHY_DX4GTR0_OFFSET 
+#define DDR_PHY_DX4GTR0_OFFSET                                                     0XFD080BC0
+#undef DDR_PHY_DX5GCR0_OFFSET 
+#define DDR_PHY_DX5GCR0_OFFSET                                                     0XFD080C00
+#undef DDR_PHY_DX5GCR1_OFFSET 
+#define DDR_PHY_DX5GCR1_OFFSET                                                     0XFD080C04
+#undef DDR_PHY_DX5GCR4_OFFSET 
+#define DDR_PHY_DX5GCR4_OFFSET                                                     0XFD080C10
+#undef DDR_PHY_DX5GCR5_OFFSET 
+#define DDR_PHY_DX5GCR5_OFFSET                                                     0XFD080C14
+#undef DDR_PHY_DX5GCR6_OFFSET 
+#define DDR_PHY_DX5GCR6_OFFSET                                                     0XFD080C18
+#undef DDR_PHY_DX5LCDLR2_OFFSET 
+#define DDR_PHY_DX5LCDLR2_OFFSET                                                   0XFD080C88
+#undef DDR_PHY_DX5GTR0_OFFSET 
+#define DDR_PHY_DX5GTR0_OFFSET                                                     0XFD080CC0
+#undef DDR_PHY_DX6GCR0_OFFSET 
+#define DDR_PHY_DX6GCR0_OFFSET                                                     0XFD080D00
+#undef DDR_PHY_DX6GCR1_OFFSET 
+#define DDR_PHY_DX6GCR1_OFFSET                                                     0XFD080D04
+#undef DDR_PHY_DX6GCR4_OFFSET 
+#define DDR_PHY_DX6GCR4_OFFSET                                                     0XFD080D10
+#undef DDR_PHY_DX6GCR5_OFFSET 
+#define DDR_PHY_DX6GCR5_OFFSET                                                     0XFD080D14
+#undef DDR_PHY_DX6GCR6_OFFSET 
+#define DDR_PHY_DX6GCR6_OFFSET                                                     0XFD080D18
+#undef DDR_PHY_DX6LCDLR2_OFFSET 
+#define DDR_PHY_DX6LCDLR2_OFFSET                                                   0XFD080D88
+#undef DDR_PHY_DX6GTR0_OFFSET 
+#define DDR_PHY_DX6GTR0_OFFSET                                                     0XFD080DC0
+#undef DDR_PHY_DX7GCR0_OFFSET 
+#define DDR_PHY_DX7GCR0_OFFSET                                                     0XFD080E00
+#undef DDR_PHY_DX7GCR1_OFFSET 
+#define DDR_PHY_DX7GCR1_OFFSET                                                     0XFD080E04
+#undef DDR_PHY_DX7GCR4_OFFSET 
+#define DDR_PHY_DX7GCR4_OFFSET                                                     0XFD080E10
+#undef DDR_PHY_DX7GCR5_OFFSET 
+#define DDR_PHY_DX7GCR5_OFFSET                                                     0XFD080E14
+#undef DDR_PHY_DX7GCR6_OFFSET 
+#define DDR_PHY_DX7GCR6_OFFSET                                                     0XFD080E18
+#undef DDR_PHY_DX7LCDLR2_OFFSET 
+#define DDR_PHY_DX7LCDLR2_OFFSET                                                   0XFD080E88
+#undef DDR_PHY_DX7GTR0_OFFSET 
+#define DDR_PHY_DX7GTR0_OFFSET                                                     0XFD080EC0
+#undef DDR_PHY_DX8GCR0_OFFSET 
+#define DDR_PHY_DX8GCR0_OFFSET                                                     0XFD080F00
+#undef DDR_PHY_DX8GCR1_OFFSET 
+#define DDR_PHY_DX8GCR1_OFFSET                                                     0XFD080F04
+#undef DDR_PHY_DX8GCR4_OFFSET 
+#define DDR_PHY_DX8GCR4_OFFSET                                                     0XFD080F10
+#undef DDR_PHY_DX8GCR5_OFFSET 
+#define DDR_PHY_DX8GCR5_OFFSET                                                     0XFD080F14
+#undef DDR_PHY_DX8GCR6_OFFSET 
+#define DDR_PHY_DX8GCR6_OFFSET                                                     0XFD080F18
+#undef DDR_PHY_DX8LCDLR2_OFFSET 
+#define DDR_PHY_DX8LCDLR2_OFFSET                                                   0XFD080F88
+#undef DDR_PHY_DX8GTR0_OFFSET 
+#define DDR_PHY_DX8GTR0_OFFSET                                                     0XFD080FC0
+#undef DDR_PHY_DX8SL0DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL0DQSCTL_OFFSET                                                0XFD08141C
+#undef DDR_PHY_DX8SL0DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL0DXCTL2_OFFSET                                                0XFD08142C
+#undef DDR_PHY_DX8SL0IOCR_OFFSET 
+#define DDR_PHY_DX8SL0IOCR_OFFSET                                                  0XFD081430
+#undef DDR_PHY_DX8SL1DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL1DQSCTL_OFFSET                                                0XFD08145C
+#undef DDR_PHY_DX8SL1DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL1DXCTL2_OFFSET                                                0XFD08146C
+#undef DDR_PHY_DX8SL1IOCR_OFFSET 
+#define DDR_PHY_DX8SL1IOCR_OFFSET                                                  0XFD081470
+#undef DDR_PHY_DX8SL2DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL2DQSCTL_OFFSET                                                0XFD08149C
+#undef DDR_PHY_DX8SL2DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL2DXCTL2_OFFSET                                                0XFD0814AC
+#undef DDR_PHY_DX8SL2IOCR_OFFSET 
+#define DDR_PHY_DX8SL2IOCR_OFFSET                                                  0XFD0814B0
+#undef DDR_PHY_DX8SL3DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL3DQSCTL_OFFSET                                                0XFD0814DC
+#undef DDR_PHY_DX8SL3DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL3DXCTL2_OFFSET                                                0XFD0814EC
+#undef DDR_PHY_DX8SL3IOCR_OFFSET 
+#define DDR_PHY_DX8SL3IOCR_OFFSET                                                  0XFD0814F0
+#undef DDR_PHY_DX8SL4DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL4DQSCTL_OFFSET                                                0XFD08151C
+#undef DDR_PHY_DX8SL4DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL4DXCTL2_OFFSET                                                0XFD08152C
+#undef DDR_PHY_DX8SL4IOCR_OFFSET 
+#define DDR_PHY_DX8SL4IOCR_OFFSET                                                  0XFD081530
+#undef DDR_PHY_DX8SLBDQSCTL_OFFSET 
+#define DDR_PHY_DX8SLBDQSCTL_OFFSET                                                0XFD0817DC
+#undef DDR_PHY_PIR_OFFSET 
+#define DDR_PHY_PIR_OFFSET                                                         0XFD080004
+
+/*DDR block level reset inside of the DDR Sub System*/
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 
+#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                                        0x0000000F
+#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                                         3
+#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                                          0x00000008U
+
+/*Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 
+		evice*/
+#undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL 
+#undef DDRC_MSTR_DEVICE_CONFIG_SHIFT 
+#undef DDRC_MSTR_DEVICE_CONFIG_MASK 
+#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL                                             0x03040001
+#define DDRC_MSTR_DEVICE_CONFIG_SHIFT                                              30
+#define DDRC_MSTR_DEVICE_CONFIG_MASK                                               0xC0000000U
+
+/*Choose which registers are used. - 0 - Original registers - 1 - Shadow registers*/
+#undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL 
+#undef DDRC_MSTR_FREQUENCY_MODE_SHIFT 
+#undef DDRC_MSTR_FREQUENCY_MODE_MASK 
+#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL                                            0x03040001
+#define DDRC_MSTR_FREQUENCY_MODE_SHIFT                                             29
+#define DDRC_MSTR_FREQUENCY_MODE_MASK                                              0x20000000U
+
+/*Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
+		esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - 
+		ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
+		ks - 1111 - Four ranks*/
+#undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL 
+#undef DDRC_MSTR_ACTIVE_RANKS_SHIFT 
+#undef DDRC_MSTR_ACTIVE_RANKS_MASK 
+#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL                                              0x03040001
+#define DDRC_MSTR_ACTIVE_RANKS_SHIFT                                               24
+#define DDRC_MSTR_ACTIVE_RANKS_MASK                                                0x03000000U
+
+/*SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
+		 of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls 
+		he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
+		-fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
+		 is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1*/
+#undef DDRC_MSTR_BURST_RDWR_DEFVAL 
+#undef DDRC_MSTR_BURST_RDWR_SHIFT 
+#undef DDRC_MSTR_BURST_RDWR_MASK 
+#define DDRC_MSTR_BURST_RDWR_DEFVAL                                                0x03040001
+#define DDRC_MSTR_BURST_RDWR_SHIFT                                                 16
+#define DDRC_MSTR_BURST_RDWR_MASK                                                  0x000F0000U
+
+/*Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM 
+		n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
+		l_off_mode is not supported, and this bit must be set to '0'.*/
+#undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL 
+#undef DDRC_MSTR_DLL_OFF_MODE_SHIFT 
+#undef DDRC_MSTR_DLL_OFF_MODE_MASK 
+#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL                                              0x03040001
+#define DDRC_MSTR_DLL_OFF_MODE_SHIFT                                               15
+#define DDRC_MSTR_DLL_OFF_MODE_MASK                                                0x00008000U
+
+/*Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
+		AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
+		dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
+		figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).*/
+#undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 
+#undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 
+#undef DDRC_MSTR_DATA_BUS_WIDTH_MASK 
+#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL                                            0x03040001
+#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT                                             12
+#define DDRC_MSTR_DATA_BUS_WIDTH_MASK                                              0x00003000U
+
+/*1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
+		 only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode 
+		s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set*/
+#undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL 
+#undef DDRC_MSTR_GEARDOWN_MODE_SHIFT 
+#undef DDRC_MSTR_GEARDOWN_MODE_MASK 
+#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL                                             0x03040001
+#define DDRC_MSTR_GEARDOWN_MODE_SHIFT                                              11
+#define DDRC_MSTR_GEARDOWN_MODE_MASK                                               0x00000800U
+
+/*If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held 
+		or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in 
+		PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
+		ing is not supported in DDR4 geardown mode.*/
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK 
+#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL                                         0x03040001
+#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT                                          10
+#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK                                           0x00000400U
+
+/*When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
+		t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
+		 (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
+		_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'*/
+#undef DDRC_MSTR_BURSTCHOP_DEFVAL 
+#undef DDRC_MSTR_BURSTCHOP_SHIFT 
+#undef DDRC_MSTR_BURSTCHOP_MASK 
+#define DDRC_MSTR_BURSTCHOP_DEFVAL                                                 0x03040001
+#define DDRC_MSTR_BURSTCHOP_SHIFT                                                  9
+#define DDRC_MSTR_BURSTCHOP_MASK                                                   0x00000200U
+
+/*Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
+		port LPDDR4.*/
+#undef DDRC_MSTR_LPDDR4_DEFVAL 
+#undef DDRC_MSTR_LPDDR4_SHIFT 
+#undef DDRC_MSTR_LPDDR4_MASK 
+#define DDRC_MSTR_LPDDR4_DEFVAL                                                    0x03040001
+#define DDRC_MSTR_LPDDR4_SHIFT                                                     5
+#define DDRC_MSTR_LPDDR4_MASK                                                      0x00000020U
+
+/*Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support 
+		DR4.*/
+#undef DDRC_MSTR_DDR4_DEFVAL 
+#undef DDRC_MSTR_DDR4_SHIFT 
+#undef DDRC_MSTR_DDR4_MASK 
+#define DDRC_MSTR_DDR4_DEFVAL                                                      0x03040001
+#define DDRC_MSTR_DDR4_SHIFT                                                       4
+#define DDRC_MSTR_DDR4_MASK                                                        0x00000010U
+
+/*Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
+		port LPDDR3.*/
+#undef DDRC_MSTR_LPDDR3_DEFVAL 
+#undef DDRC_MSTR_LPDDR3_SHIFT 
+#undef DDRC_MSTR_LPDDR3_MASK 
+#define DDRC_MSTR_LPDDR3_DEFVAL                                                    0x03040001
+#define DDRC_MSTR_LPDDR3_SHIFT                                                     3
+#define DDRC_MSTR_LPDDR3_MASK                                                      0x00000008U
+
+/*Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
+		port LPDDR2.*/
+#undef DDRC_MSTR_LPDDR2_DEFVAL 
+#undef DDRC_MSTR_LPDDR2_SHIFT 
+#undef DDRC_MSTR_LPDDR2_MASK 
+#define DDRC_MSTR_LPDDR2_DEFVAL                                                    0x03040001
+#define DDRC_MSTR_LPDDR2_SHIFT                                                     2
+#define DDRC_MSTR_LPDDR2_MASK                                                      0x00000004U
+
+/*Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
+		*/
+#undef DDRC_MSTR_DDR3_DEFVAL 
+#undef DDRC_MSTR_DDR3_SHIFT 
+#undef DDRC_MSTR_DDR3_MASK 
+#define DDRC_MSTR_DDR3_DEFVAL                                                      0x03040001
+#define DDRC_MSTR_DDR3_SHIFT                                                       0
+#define DDRC_MSTR_DDR3_MASK                                                        0x00000001U
+
+/*Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
+		 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
+		re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.*/
+#undef DDRC_MRCTRL0_MR_WR_DEFVAL 
+#undef DDRC_MRCTRL0_MR_WR_SHIFT 
+#undef DDRC_MRCTRL0_MR_WR_MASK 
+#define DDRC_MRCTRL0_MR_WR_DEFVAL                                                  0x00000030
+#define DDRC_MRCTRL0_MR_WR_SHIFT                                                   31
+#define DDRC_MRCTRL0_MR_WR_MASK                                                    0x80000000U
+
+/*Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
+		 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
+		R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
+		dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well 
+		s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
+		put Inversion of RDIMMs.*/
+#undef DDRC_MRCTRL0_MR_ADDR_DEFVAL 
+#undef DDRC_MRCTRL0_MR_ADDR_SHIFT 
+#undef DDRC_MRCTRL0_MR_ADDR_MASK 
+#define DDRC_MRCTRL0_MR_ADDR_DEFVAL                                                0x00000030
+#define DDRC_MRCTRL0_MR_ADDR_SHIFT                                                 12
+#define DDRC_MRCTRL0_MR_ADDR_MASK                                                  0x0000F000U
+
+/*Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
+		 However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
+		amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks 
+		 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3*/
+#undef DDRC_MRCTRL0_MR_RANK_DEFVAL 
+#undef DDRC_MRCTRL0_MR_RANK_SHIFT 
+#undef DDRC_MRCTRL0_MR_RANK_MASK 
+#define DDRC_MRCTRL0_MR_RANK_DEFVAL                                                0x00000030
+#define DDRC_MRCTRL0_MR_RANK_SHIFT                                                 4
+#define DDRC_MRCTRL0_MR_RANK_MASK                                                  0x00000030U
+
+/*Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. 
+		or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
+		 be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared 
+		o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
+		n is not allowed - 1 - Software intervention is allowed*/
+#undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 
+#undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT 
+#undef DDRC_MRCTRL0_SW_INIT_INT_MASK 
+#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL                                            0x00000030
+#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT                                             3
+#define DDRC_MRCTRL0_SW_INIT_INT_MASK                                              0x00000008U
+
+/*Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode*/
+#undef DDRC_MRCTRL0_PDA_EN_DEFVAL 
+#undef DDRC_MRCTRL0_PDA_EN_SHIFT 
+#undef DDRC_MRCTRL0_PDA_EN_MASK 
+#define DDRC_MRCTRL0_PDA_EN_DEFVAL                                                 0x00000030
+#define DDRC_MRCTRL0_PDA_EN_SHIFT                                                  2
+#define DDRC_MRCTRL0_PDA_EN_MASK                                                   0x00000004U
+
+/*Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR*/
+#undef DDRC_MRCTRL0_MPR_EN_DEFVAL 
+#undef DDRC_MRCTRL0_MPR_EN_SHIFT 
+#undef DDRC_MRCTRL0_MPR_EN_MASK 
+#define DDRC_MRCTRL0_MPR_EN_DEFVAL                                                 0x00000030
+#define DDRC_MRCTRL0_MPR_EN_SHIFT                                                  1
+#define DDRC_MRCTRL0_MPR_EN_MASK                                                   0x00000002U
+
+/*Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
+		d*/
+#undef DDRC_MRCTRL0_MR_TYPE_DEFVAL 
+#undef DDRC_MRCTRL0_MR_TYPE_SHIFT 
+#undef DDRC_MRCTRL0_MR_TYPE_MASK 
+#define DDRC_MRCTRL0_MR_TYPE_DEFVAL                                                0x00000030
+#define DDRC_MRCTRL0_MR_TYPE_SHIFT                                                 0
+#define DDRC_MRCTRL0_MR_TYPE_MASK                                                  0x00000001U
+
+/*Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
+		 Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
+		g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.*/
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK 
+#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL                                       0x00000000
+#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT                                        8
+#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK                                         0x00000300U
+
+/*Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
+		r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.*/
+#undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL 
+#undef DDRC_DERATEEN_DERATE_BYTE_SHIFT 
+#undef DDRC_DERATEEN_DERATE_BYTE_MASK 
+#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL                                           0x00000000
+#define DDRC_DERATEEN_DERATE_BYTE_SHIFT                                            4
+#define DDRC_DERATEEN_DERATE_BYTE_MASK                                             0x000000F0U
+
+/*Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
+		4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
+		for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.*/
+#undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL 
+#undef DDRC_DERATEEN_DERATE_VALUE_SHIFT 
+#undef DDRC_DERATEEN_DERATE_VALUE_MASK 
+#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL                                          0x00000000
+#define DDRC_DERATEEN_DERATE_VALUE_SHIFT                                           1
+#define DDRC_DERATEEN_DERATE_VALUE_MASK                                            0x00000002U
+
+/*Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
+		Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
+		mode.*/
+#undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 
+#undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT 
+#undef DDRC_DERATEEN_DERATE_ENABLE_MASK 
+#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL                                         0x00000000
+#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT                                          0
+#define DDRC_DERATEEN_DERATE_ENABLE_MASK                                           0x00000001U
+
+/*Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
+		DR3/LPDDR4. This register must not be set to zero*/
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL 
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 
+#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL                                    
+#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT                                     0
+#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK                                      0xFFFFFFFFU
+
+/*Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
+		r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 
+		 - Allow transition from Self refresh state*/
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK 
+#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL                                         0x00000000
+#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT                                          6
+#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK                                           0x00000040U
+
+/*A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
+		M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
+		are Exit from Self Refresh*/
+#undef DDRC_PWRCTL_SELFREF_SW_DEFVAL 
+#undef DDRC_PWRCTL_SELFREF_SW_SHIFT 
+#undef DDRC_PWRCTL_SELFREF_SW_MASK 
+#define DDRC_PWRCTL_SELFREF_SW_DEFVAL                                              0x00000000
+#define DDRC_PWRCTL_SELFREF_SW_SHIFT                                               5
+#define DDRC_PWRCTL_SELFREF_SW_MASK                                                0x00000020U
+
+/*When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
+		st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For 
+		on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
+		DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PWRCTL_MPSM_EN_DEFVAL 
+#undef DDRC_PWRCTL_MPSM_EN_SHIFT 
+#undef DDRC_PWRCTL_MPSM_EN_MASK 
+#define DDRC_PWRCTL_MPSM_EN_DEFVAL                                                 0x00000000
+#define DDRC_PWRCTL_MPSM_EN_SHIFT                                                  4
+#define DDRC_PWRCTL_MPSM_EN_MASK                                                   0x00000010U
+
+/*Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
+		is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
+		4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in 
+		ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
+		rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)*/
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 
+#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL                                 0x00000000
+#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT                                  3
+#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK                                   0x00000008U
+
+/*When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
+		et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down 
+		xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
+		 should not be set to 1. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 
+#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL                                        0x00000000
+#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT                                         2
+#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK                                          0x00000004U
+
+/*If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
+		RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.*/
+#undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 
+#undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT 
+#undef DDRC_PWRCTL_POWERDOWN_EN_MASK 
+#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL                                            0x00000000
+#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT                                             1
+#define DDRC_PWRCTL_POWERDOWN_EN_MASK                                              0x00000002U
+
+/*If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
+		f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.*/
+#undef DDRC_PWRCTL_SELFREF_EN_DEFVAL 
+#undef DDRC_PWRCTL_SELFREF_EN_SHIFT 
+#undef DDRC_PWRCTL_SELFREF_EN_MASK 
+#define DDRC_PWRCTL_SELFREF_EN_DEFVAL                                              0x00000000
+#define DDRC_PWRCTL_SELFREF_EN_SHIFT                                               0
+#define DDRC_PWRCTL_SELFREF_EN_MASK                                                0x00000001U
+
+/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in 
+		he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 
+#undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 
+#undef DDRC_PWRTMG_SELFREF_TO_X32_MASK 
+#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL                                          0x00402010
+#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT                                           16
+#define DDRC_PWRTMG_SELFREF_TO_X32_MASK                                            0x00FF0000U
+
+/*Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
+		ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
+		iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL 
+#undef DDRC_PWRTMG_T_DPD_X4096_SHIFT 
+#undef DDRC_PWRTMG_T_DPD_X4096_MASK 
+#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL                                             0x00402010
+#define DDRC_PWRTMG_T_DPD_X4096_SHIFT                                              8
+#define DDRC_PWRTMG_T_DPD_X4096_MASK                                               0x0000FF00U
+
+/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
+		 PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.*/
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 
+#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL                                        0x00402010
+#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT                                         0
+#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK                                          0x0000001FU
+
+/*Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
+		d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
+		 It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
+		may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
+		om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.*/
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 
+#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL                                        0x00210000
+#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT                                         20
+#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK                                          0x00F00000U
+
+/*If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
+		1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
+		 would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
+		HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
+		formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
+		ued to the uMCTL2. FOR PERFORMANCE ONLY.*/
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 
+#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL                                        0x00210000
+#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT                                         12
+#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK                                          0x0001F000U
+
+/*The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
+		reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
+		reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
+		RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
+		. - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
+		tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
+		fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
+		ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
+		tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
+		d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
+		initiated update is complete.*/
+#undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 
+#undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 
+#undef DDRC_RFSHCTL0_REFRESH_BURST_MASK 
+#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL                                         0x00210000
+#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT                                          4
+#define DDRC_RFSHCTL0_REFRESH_BURST_MASK                                           0x000001F0U
+
+/*- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
+		t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
+		support LPDDR2/LPDDR3/LPDDR4*/
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 
+#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL                                      0x00210000
+#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT                                       2
+#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK                                        0x00000004U
+
+/*Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
+		ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
+		orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
+		self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in 
+		uture version of the uMCTL2.*/
+#undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 
+#undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 
+#undef DDRC_RFSHCTL3_REFRESH_MODE_MASK 
+#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL                                          0x00000000
+#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT                                           4
+#define DDRC_RFSHCTL3_REFRESH_MODE_MASK                                            0x00000070U
+
+/*Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value 
+		s automatically updated when exiting reset, so it does not need to be toggled initially.*/
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 
+#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL                                  0x00000000
+#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT                                   1
+#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK                                    0x00000002U
+
+/*When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
+		ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
+		auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
+		is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. 
+		his register field is changeable on the fly.*/
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 
+#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL                                      0x00000000
+#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT                                       0
+#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK                                        0x00000001U
+
+/*tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
+		 for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
+		, this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should 
+		e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
+		ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
+		programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
+		TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.*/
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 
+#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL                                          0x0062008C
+#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT                                           16
+#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK                                            0x0FFF0000U
+
+/*Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the 
+		REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
+		 - 0 - tREFBW parameter not used - 1 - tREFBW parameter used*/
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 
+#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL                                       0x0062008C
+#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT                                        15
+#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK                                         0x00008000U
+
+/*tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
+		 RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
+		DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
+		 per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
+		equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
+		opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.*/
+#undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 
+#undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT 
+#undef DDRC_RFSHTMG_T_RFC_MIN_MASK 
+#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL                                              0x0062008C
+#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT                                               0
+#define DDRC_RFSHTMG_T_RFC_MIN_MASK                                                0x000003FFU
+
+/*Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined*/
+#undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 
+#undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT 
+#undef DDRC_ECCCFG0_DIS_SCRUB_MASK 
+#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL                                              0x00000000
+#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT                                               4
+#define DDRC_ECCCFG0_DIS_SCRUB_MASK                                                0x00000010U
+
+/*ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
+		 use*/
+#undef DDRC_ECCCFG0_ECC_MODE_DEFVAL 
+#undef DDRC_ECCCFG0_ECC_MODE_SHIFT 
+#undef DDRC_ECCCFG0_ECC_MODE_MASK 
+#define DDRC_ECCCFG0_ECC_MODE_DEFVAL                                               0x00000000
+#define DDRC_ECCCFG0_ECC_MODE_SHIFT                                                0
+#define DDRC_ECCCFG0_ECC_MODE_MASK                                                 0x00000007U
+
+/*Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
+		ng, if ECCCFG1.data_poison_en=1*/
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK 
+#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL                                        0x00000000
+#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT                                         1
+#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK                                          0x00000002U
+
+/*Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers*/
+#undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 
+#undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 
+#undef DDRC_ECCCFG1_DATA_POISON_EN_MASK 
+#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL                                         0x00000000
+#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT                                          0
+#define DDRC_ECCCFG1_DATA_POISON_EN_MASK                                           0x00000001U
+
+/*The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
+		the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY 
+		pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
+		L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
+		dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
+		e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks*/
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 
+#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL                                     0x10000200
+#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT                                      24
+#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK                                       0x3F000000U
+
+/*After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
+		M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
+		the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
+		the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
+		RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
+		 handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
+		rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
+		ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in 
+		he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is 
+		one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in 
+		PR Page 1 should be treated as 'Don't care'.*/
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 
+#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL                                   0x10000200
+#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT                                    9
+#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK                                     0x00000200U
+
+/*- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
+		 CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
+		 disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)*/
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 
+#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL                             0x10000200
+#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT                              8
+#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK                               0x00000100U
+
+/*CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
+		d to support DDR4.*/
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK 
+#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL                                          0x10000200
+#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT                                           7
+#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK                                            0x00000080U
+
+/*CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
+		 CRC mode register setting in the DRAM.*/
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK 
+#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL                                          0x10000200
+#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT                                           4
+#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK                                            0x00000010U
+
+/*C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of 
+		/A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
+		is register should be 1.*/
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 
+#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL                                       0x10000200
+#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT                                        0
+#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK                                         0x00000001U
+
+/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
+		 - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
+		er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.*/
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 
+#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL                                  0x0030050C
+#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT                                   16
+#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK                                    0x01FF0000U
+
+/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
+		tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
+		value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.*/
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 
+#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL                                  0x0030050C
+#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT                                   8
+#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK                                    0x00001F00U
+
+/*Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
+		ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
+		er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
+		les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
+		or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
+		ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
+		max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
+		bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
+		+ board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
+		ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The 
+		ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
+		to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
+		 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
+		PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
+		_FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
+		C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
+		e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
+		 bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
+		H-6 Values of 0, 1 and 2 are illegal.*/
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 
+#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL                        0x0030050C
+#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT                         0
+#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK                          0x0000003FU
+
+/*If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
+		 in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
+		ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
+		r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported 
+		or LPDDR4 in this version of the uMCTL2.*/
+#undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 
+#undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 
+#undef DDRC_INIT0_SKIP_DRAM_INIT_MASK 
+#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL                                           0x0002004E
+#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT                                            30
+#define DDRC_INIT0_SKIP_DRAM_INIT_MASK                                             0xC0000000U
+
+/*Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires 
+		 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
+		grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
+		MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.*/
+#undef DDRC_INIT0_POST_CKE_X1024_DEFVAL 
+#undef DDRC_INIT0_POST_CKE_X1024_SHIFT 
+#undef DDRC_INIT0_POST_CKE_X1024_MASK 
+#define DDRC_INIT0_POST_CKE_X1024_DEFVAL                                           0x0002004E
+#define DDRC_INIT0_POST_CKE_X1024_SHIFT                                            16
+#define DDRC_INIT0_POST_CKE_X1024_MASK                                             0x03FF0000U
+
+/*Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 
+		pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
+		tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
+		 to next integer value.*/
+#undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL 
+#undef DDRC_INIT0_PRE_CKE_X1024_SHIFT 
+#undef DDRC_INIT0_PRE_CKE_X1024_MASK 
+#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL                                            0x0002004E
+#define DDRC_INIT0_PRE_CKE_X1024_SHIFT                                             0
+#define DDRC_INIT0_PRE_CKE_X1024_MASK                                              0x00000FFFU
+
+/*Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
+		LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1*/
+#undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 
+#undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 
+#undef DDRC_INIT1_DRAM_RSTN_X1024_MASK 
+#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL                                          0x00000000
+#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT                                           16
+#define DDRC_INIT1_DRAM_RSTN_X1024_MASK                                            0x01FF0000U
+
+/*Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
+		bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.*/
+#undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 
+#undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT 
+#undef DDRC_INIT1_FINAL_WAIT_X32_MASK 
+#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL                                           0x00000000
+#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT                                            8
+#define DDRC_INIT1_FINAL_WAIT_X32_MASK                                             0x00007F00U
+
+/*Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
+		. There is no known specific requirement for this; it may be set to zero.*/
+#undef DDRC_INIT1_PRE_OCD_X32_DEFVAL 
+#undef DDRC_INIT1_PRE_OCD_X32_SHIFT 
+#undef DDRC_INIT1_PRE_OCD_X32_MASK 
+#define DDRC_INIT1_PRE_OCD_X32_DEFVAL                                              0x00000000
+#define DDRC_INIT1_PRE_OCD_X32_SHIFT                                               0
+#define DDRC_INIT1_PRE_OCD_X32_MASK                                                0x0000000FU
+
+/*Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.*/
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 
+#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL                                     0x00000D05
+#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT                                      8
+#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK                                       0x0000FF00U
+
+/*Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
+		e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.*/
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 
+#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL                                      0x00000D05
+#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT                                       0
+#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK                                        0x0000000FU
+
+/*DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
+		 DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
+		register*/
+#undef DDRC_INIT3_MR_DEFVAL 
+#undef DDRC_INIT3_MR_SHIFT 
+#undef DDRC_INIT3_MR_MASK 
+#define DDRC_INIT3_MR_DEFVAL                                                       0x00000510
+#define DDRC_INIT3_MR_SHIFT                                                        16
+#define DDRC_INIT3_MR_MASK                                                         0xFFFF0000U
+
+/*DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
+		bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
+		 bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
+		lue to write to MR2 register*/
+#undef DDRC_INIT3_EMR_DEFVAL 
+#undef DDRC_INIT3_EMR_SHIFT 
+#undef DDRC_INIT3_EMR_MASK 
+#define DDRC_INIT3_EMR_DEFVAL                                                      0x00000510
+#define DDRC_INIT3_EMR_SHIFT                                                       0
+#define DDRC_INIT3_EMR_MASK                                                        0x0000FFFFU
+
+/*DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 
+		egister mDDR: Unused*/
+#undef DDRC_INIT4_EMR2_DEFVAL 
+#undef DDRC_INIT4_EMR2_SHIFT 
+#undef DDRC_INIT4_EMR2_MASK 
+#define DDRC_INIT4_EMR2_DEFVAL                                                     0x00000000
+#define DDRC_INIT4_EMR2_SHIFT                                                      16
+#define DDRC_INIT4_EMR2_MASK                                                       0xFFFF0000U
+
+/*DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to 
+		rite to MR13 register*/
+#undef DDRC_INIT4_EMR3_DEFVAL 
+#undef DDRC_INIT4_EMR3_SHIFT 
+#undef DDRC_INIT4_EMR3_MASK 
+#define DDRC_INIT4_EMR3_DEFVAL                                                     0x00000000
+#define DDRC_INIT4_EMR3_SHIFT                                                      0
+#define DDRC_INIT4_EMR3_MASK                                                       0x0000FFFFU
+
+/*ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock 
+		ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.*/
+#undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 
+#undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 
+#undef DDRC_INIT5_DEV_ZQINIT_X32_MASK 
+#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL                                           0x00100004
+#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT                                            16
+#define DDRC_INIT5_DEV_ZQINIT_X32_MASK                                             0x00FF0000U
+
+/*Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
+		3 typically requires 10 us.*/
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 
+#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL                                      0x00100004
+#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT                                       0
+#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK                                        0x000003FFU
+
+/*DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.*/
+#undef DDRC_INIT6_MR4_DEFVAL 
+#undef DDRC_INIT6_MR4_SHIFT 
+#undef DDRC_INIT6_MR4_MASK 
+#define DDRC_INIT6_MR4_DEFVAL                                                      0x00000000
+#define DDRC_INIT6_MR4_SHIFT                                                       16
+#define DDRC_INIT6_MR4_MASK                                                        0xFFFF0000U
+
+/*DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.*/
+#undef DDRC_INIT6_MR5_DEFVAL 
+#undef DDRC_INIT6_MR5_SHIFT 
+#undef DDRC_INIT6_MR5_MASK 
+#define DDRC_INIT6_MR5_DEFVAL                                                      0x00000000
+#define DDRC_INIT6_MR5_SHIFT                                                       0
+#define DDRC_INIT6_MR5_MASK                                                        0x0000FFFFU
+
+/*DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.*/
+#undef DDRC_INIT7_MR6_DEFVAL 
+#undef DDRC_INIT7_MR6_SHIFT 
+#undef DDRC_INIT7_MR6_MASK 
+#define DDRC_INIT7_MR6_DEFVAL                                                      
+#define DDRC_INIT7_MR6_SHIFT                                                       16
+#define DDRC_INIT7_MR6_MASK                                                        0xFFFF0000U
+
+/*Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
+		ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
+		 address mirroring is enabled.*/
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 
+#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL                                  0x00000000
+#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT                                   5
+#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK                                    0x00000020U
+
+/*Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
+		 be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output 
+		nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
+		effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
+		led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled*/
+#undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 
+#undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 
+#undef DDRC_DIMMCTL_MRS_BG1_EN_MASK 
+#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL                                             0x00000000
+#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT                                              4
+#define DDRC_DIMMCTL_MRS_BG1_EN_MASK                                               0x00000010U
+
+/*Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
+		 be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, 
+		his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address 
+		f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled*/
+#undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 
+#undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT 
+#undef DDRC_DIMMCTL_MRS_A17_EN_MASK 
+#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL                                             0x00000000
+#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT                                              3
+#define DDRC_DIMMCTL_MRS_A17_EN_MASK                                               0x00000008U
+
+/*Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
+		which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, 
+		A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
+		lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. 
+		or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
+		 has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
+		ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.*/
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 
+#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL                                     0x00000000
+#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT                                      2
+#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK                                       0x00000004U
+
+/*Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
+		4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits 
+		re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
+		at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
+		sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
+		 swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
+		ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
+		or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
+		hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
+		ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
+		not implement address mirroring*/
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 
+#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL                                      0x00000000
+#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT                                       1
+#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK                                        0x00000002U
+
+/*Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
+		R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
+		CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
+		 each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses*/
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 
+#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL                                     0x00000000
+#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT                                      0
+#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK                                       0x00000001U
+
+/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
+		e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
+		nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
+		ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
+		ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed 
+		n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
+		ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
+		or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
+		 to the next integer.*/
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 
+#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL                                       0x0000066F
+#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT                                        8
+#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK                                         0x00000F00U
+
+/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
+		e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
+		sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
+		p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
+		), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
+		requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
+		quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and 
+		ound it up to the next integer.*/
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 
+#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL                                       0x0000066F
+#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT                                        4
+#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK                                         0x000000F0U
+
+/*Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
+		nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
+		on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
+		-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
+		_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
+		om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
+		ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to 
+		llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
+		ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as 
+		ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
+		. FOR PERFORMANCE ONLY.*/
+#undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 
+#undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT 
+#undef DDRC_RANKCTL_MAX_RANK_RD_MASK 
+#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL                                            0x0000066F
+#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT                                             0
+#define DDRC_RANKCTL_MAX_RANK_RD_MASK                                              0x0000000FU
+
+/*Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles 
+		 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
+		 value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
+		Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this 
+		arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
+		with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.*/
+#undef DDRC_DRAMTMG0_WR2PRE_DEFVAL 
+#undef DDRC_DRAMTMG0_WR2PRE_SHIFT 
+#undef DDRC_DRAMTMG0_WR2PRE_MASK 
+#define DDRC_DRAMTMG0_WR2PRE_DEFVAL                                                0x0F101B0F
+#define DDRC_DRAMTMG0_WR2PRE_SHIFT                                                 24
+#define DDRC_DRAMTMG0_WR2PRE_MASK                                                  0x7F000000U
+
+/*tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
+		in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next 
+		nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks*/
+#undef DDRC_DRAMTMG0_T_FAW_DEFVAL 
+#undef DDRC_DRAMTMG0_T_FAW_SHIFT 
+#undef DDRC_DRAMTMG0_T_FAW_MASK 
+#define DDRC_DRAMTMG0_T_FAW_DEFVAL                                                 0x0F101B0F
+#define DDRC_DRAMTMG0_T_FAW_SHIFT                                                  16
+#define DDRC_DRAMTMG0_T_FAW_MASK                                                   0x003F0000U
+
+/*tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
+		imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
+		 No rounding up. Unit: Multiples of 1024 clocks.*/
+#undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 
+#undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 
+#undef DDRC_DRAMTMG0_T_RAS_MAX_MASK 
+#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL                                             0x0F101B0F
+#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT                                              8
+#define DDRC_DRAMTMG0_T_RAS_MAX_MASK                                               0x00007F00U
+
+/*tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, 
+		rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
+		 (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks*/
+#undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 
+#undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 
+#undef DDRC_DRAMTMG0_T_RAS_MIN_MASK 
+#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL                                             0x0F101B0F
+#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT                                              0
+#define DDRC_DRAMTMG0_T_RAS_MIN_MASK                                               0x0000003FU
+
+/*tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
+		 is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, 
+		rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks*/
+#undef DDRC_DRAMTMG1_T_XP_DEFVAL 
+#undef DDRC_DRAMTMG1_T_XP_SHIFT 
+#undef DDRC_DRAMTMG1_T_XP_MASK 
+#define DDRC_DRAMTMG1_T_XP_DEFVAL                                                  0x00080414
+#define DDRC_DRAMTMG1_T_XP_SHIFT                                                   16
+#define DDRC_DRAMTMG1_T_XP_MASK                                                    0x001F0000U
+
+/*tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
+		R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
+		S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
+		2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
+		gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
+		e. Unit: Clocks.*/
+#undef DDRC_DRAMTMG1_RD2PRE_DEFVAL 
+#undef DDRC_DRAMTMG1_RD2PRE_SHIFT 
+#undef DDRC_DRAMTMG1_RD2PRE_MASK 
+#define DDRC_DRAMTMG1_RD2PRE_DEFVAL                                                0x00080414
+#define DDRC_DRAMTMG1_RD2PRE_SHIFT                                                 8
+#define DDRC_DRAMTMG1_RD2PRE_MASK                                                  0x00001F00U
+
+/*tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
+		 up to next integer value. Unit: Clocks.*/
+#undef DDRC_DRAMTMG1_T_RC_DEFVAL 
+#undef DDRC_DRAMTMG1_T_RC_SHIFT 
+#undef DDRC_DRAMTMG1_T_RC_MASK 
+#define DDRC_DRAMTMG1_T_RC_DEFVAL                                                  0x00080414
+#define DDRC_DRAMTMG1_T_RC_SHIFT                                                   0
+#define DDRC_DRAMTMG1_T_RC_MASK                                                    0x0000007FU
+
+/*Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
+		t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
+		tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
+		equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
+		 is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK 
+#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL                                         0x0305060D
+#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT                                          24
+#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK                                           0x3F000000U
+
+/*Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
+		using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For 
+		onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
+		er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
+		s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/
+#undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 
+#undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT 
+#undef DDRC_DRAMTMG2_READ_LATENCY_MASK 
+#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL                                          0x0305060D
+#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT                                           16
+#define DDRC_DRAMTMG2_READ_LATENCY_MASK                                            0x003F0000U
+
+/*DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL 
+		PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
+		/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
+		time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = 
+		urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
+		tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
+		DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
+		gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/
+#undef DDRC_DRAMTMG2_RD2WR_DEFVAL 
+#undef DDRC_DRAMTMG2_RD2WR_SHIFT 
+#undef DDRC_DRAMTMG2_RD2WR_MASK 
+#define DDRC_DRAMTMG2_RD2WR_DEFVAL                                                 0x0305060D
+#define DDRC_DRAMTMG2_RD2WR_SHIFT                                                  8
+#define DDRC_DRAMTMG2_RD2WR_MASK                                                   0x00003F00U
+
+/*DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
+		k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
+		 per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
+		 length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
+		d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
+		 delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
+		ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/
+#undef DDRC_DRAMTMG2_WR2RD_DEFVAL 
+#undef DDRC_DRAMTMG2_WR2RD_SHIFT 
+#undef DDRC_DRAMTMG2_WR2RD_MASK 
+#define DDRC_DRAMTMG2_WR2RD_DEFVAL                                                 0x0305060D
+#define DDRC_DRAMTMG2_WR2RD_SHIFT                                                  0
+#define DDRC_DRAMTMG2_WR2RD_MASK                                                   0x0000003FU
+
+/*Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
+		 LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW 
+		nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
+		 used for the time from a MRW/MRR to a MRW/MRR.*/
+#undef DDRC_DRAMTMG3_T_MRW_DEFVAL 
+#undef DDRC_DRAMTMG3_T_MRW_SHIFT 
+#undef DDRC_DRAMTMG3_T_MRW_MASK 
+#define DDRC_DRAMTMG3_T_MRW_DEFVAL                                                 0x0050400C
+#define DDRC_DRAMTMG3_T_MRW_SHIFT                                                  20
+#define DDRC_DRAMTMG3_T_MRW_MASK                                                   0x3FF00000U
+
+/*tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time 
+		rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
+		nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
+		4 is used, set to tMRD_PAR(tMOD+PL) instead.*/
+#undef DDRC_DRAMTMG3_T_MRD_DEFVAL 
+#undef DDRC_DRAMTMG3_T_MRD_SHIFT 
+#undef DDRC_DRAMTMG3_T_MRD_MASK 
+#define DDRC_DRAMTMG3_T_MRD_DEFVAL                                                 0x0050400C
+#define DDRC_DRAMTMG3_T_MRD_SHIFT                                                  12
+#define DDRC_DRAMTMG3_T_MRD_MASK                                                   0x0003F000U
+
+/*tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
+		y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
+		 if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
+		 + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.*/
+#undef DDRC_DRAMTMG3_T_MOD_DEFVAL 
+#undef DDRC_DRAMTMG3_T_MOD_SHIFT 
+#undef DDRC_DRAMTMG3_T_MOD_MASK 
+#define DDRC_DRAMTMG3_T_MOD_DEFVAL                                                 0x0050400C
+#define DDRC_DRAMTMG3_T_MOD_SHIFT                                                  0
+#define DDRC_DRAMTMG3_T_MOD_MASK                                                   0x000003FFU
+
+/*tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
+		am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
+		lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.*/
+#undef DDRC_DRAMTMG4_T_RCD_DEFVAL 
+#undef DDRC_DRAMTMG4_T_RCD_SHIFT 
+#undef DDRC_DRAMTMG4_T_RCD_MASK 
+#define DDRC_DRAMTMG4_T_RCD_DEFVAL                                                 0x05040405
+#define DDRC_DRAMTMG4_T_RCD_SHIFT                                                  24
+#define DDRC_DRAMTMG4_T_RCD_MASK                                                   0x1F000000U
+
+/*DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
+		time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
+		d it up to the next integer value. Unit: clocks.*/
+#undef DDRC_DRAMTMG4_T_CCD_DEFVAL 
+#undef DDRC_DRAMTMG4_T_CCD_SHIFT 
+#undef DDRC_DRAMTMG4_T_CCD_MASK 
+#define DDRC_DRAMTMG4_T_CCD_DEFVAL                                                 0x05040405
+#define DDRC_DRAMTMG4_T_CCD_SHIFT                                                  16
+#define DDRC_DRAMTMG4_T_CCD_MASK                                                   0x000F0000U
+
+/*DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
+		 activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
+		it up to the next integer value. Unit: Clocks.*/
+#undef DDRC_DRAMTMG4_T_RRD_DEFVAL 
+#undef DDRC_DRAMTMG4_T_RRD_SHIFT 
+#undef DDRC_DRAMTMG4_T_RRD_MASK 
+#define DDRC_DRAMTMG4_T_RRD_DEFVAL                                                 0x05040405
+#define DDRC_DRAMTMG4_T_RRD_SHIFT                                                  8
+#define DDRC_DRAMTMG4_T_RRD_MASK                                                   0x00000F00U
+
+/*tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
+		(tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
+		2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.*/
+#undef DDRC_DRAMTMG4_T_RP_DEFVAL 
+#undef DDRC_DRAMTMG4_T_RP_SHIFT 
+#undef DDRC_DRAMTMG4_T_RP_MASK 
+#define DDRC_DRAMTMG4_T_RP_DEFVAL                                                  0x05040405
+#define DDRC_DRAMTMG4_T_RP_SHIFT                                                   0
+#define DDRC_DRAMTMG4_T_RP_MASK                                                    0x0000001FU
+
+/*This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
+		e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
+		tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
+		eger.*/
+#undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKSRX_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKSRX_MASK 
+#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL                                               0x05050403
+#define DDRC_DRAMTMG5_T_CKSRX_SHIFT                                                24
+#define DDRC_DRAMTMG5_T_CKSRX_MASK                                                 0x0F000000U
+
+/*This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
+		 SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: 
+		ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
+		to next integer.*/
+#undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKSRE_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKSRE_MASK 
+#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL                                               0x05050403
+#define DDRC_DRAMTMG5_T_CKSRE_SHIFT                                                16
+#define DDRC_DRAMTMG5_T_CKSRE_MASK                                                 0x000F0000U
+
+/*Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
+		tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE 
+		 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
+		.*/
+#undef DDRC_DRAMTMG5_T_CKESR_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKESR_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKESR_MASK 
+#define DDRC_DRAMTMG5_T_CKESR_DEFVAL                                               0x05050403
+#define DDRC_DRAMTMG5_T_CKESR_SHIFT                                                8
+#define DDRC_DRAMTMG5_T_CKESR_MASK                                                 0x00003F00U
+
+/*Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of 
+		CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set 
+		his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
+		 next integer value. Unit: Clocks.*/
+#undef DDRC_DRAMTMG5_T_CKE_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKE_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKE_MASK 
+#define DDRC_DRAMTMG5_T_CKE_DEFVAL                                                 0x05050403
+#define DDRC_DRAMTMG5_T_CKE_SHIFT                                                  0
+#define DDRC_DRAMTMG5_T_CKE_MASK                                                   0x0000001FU
+
+/*This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after 
+		PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
+		ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
+		devices.*/
+#undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 
+#undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT 
+#undef DDRC_DRAMTMG6_T_CKDPDE_MASK 
+#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL                                              0x02020005
+#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT                                               24
+#define DDRC_DRAMTMG6_T_CKDPDE_MASK                                                0x0F000000U
+
+/*This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock 
+		table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
+		gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
+		R or LPDDR2 devices.*/
+#undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 
+#undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT 
+#undef DDRC_DRAMTMG6_T_CKDPDX_MASK 
+#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL                                              0x02020005
+#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT                                               16
+#define DDRC_DRAMTMG6_T_CKDPDX_MASK                                                0x000F0000U
+
+/*This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the 
+		lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
+		2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it 
+		p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL 
+#undef DDRC_DRAMTMG6_T_CKCSX_SHIFT 
+#undef DDRC_DRAMTMG6_T_CKCSX_MASK 
+#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL                                               0x02020005
+#define DDRC_DRAMTMG6_T_CKCSX_SHIFT                                                0
+#define DDRC_DRAMTMG6_T_CKCSX_MASK                                                 0x0000000FU
+
+/*This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. 
+		ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
+		is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
+		DDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL 
+#undef DDRC_DRAMTMG7_T_CKPDE_SHIFT 
+#undef DDRC_DRAMTMG7_T_CKPDE_MASK 
+#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL                                               0x00000202
+#define DDRC_DRAMTMG7_T_CKPDE_SHIFT                                                8
+#define DDRC_DRAMTMG7_T_CKPDE_MASK                                                 0x00000F00U
+
+/*This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
+		time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
+		, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
+		g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL 
+#undef DDRC_DRAMTMG7_T_CKPDX_SHIFT 
+#undef DDRC_DRAMTMG7_T_CKPDX_MASK 
+#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL                                               0x00000202
+#define DDRC_DRAMTMG7_T_CKPDX_SHIFT                                                0
+#define DDRC_DRAMTMG7_T_CKPDX_MASK                                                 0x0000000FU
+
+/*tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
+		O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
+		 is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.*/
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL                                         0x03034405
+#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT                                          24
+#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK                                           0x7F000000U
+
+/*tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
+		ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: 
+		nsure this is less than or equal to t_xs_x32.*/
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL                                        0x03034405
+#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT                                         16
+#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK                                          0x007F0000U
+
+/*tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the 
+		bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and 
+		DR4 SDRAMs.*/
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL                                          0x03034405
+#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT                                           8
+#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK                                            0x00007F00U
+
+/*tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
+		above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
+		DDR4 SDRAMs.*/
+#undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL                                              0x03034405
+#define DDRC_DRAMTMG8_T_XS_X32_SHIFT                                               0
+#define DDRC_DRAMTMG8_T_XS_X32_MASK                                                0x0000007FU
+
+/*DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2*/
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 
+#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL                                      0x0004040D
+#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT                                       30
+#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK                                        0x40000000U
+
+/*tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' 
+		o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
+		nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.*/
+#undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL 
+#undef DDRC_DRAMTMG9_T_CCD_S_SHIFT 
+#undef DDRC_DRAMTMG9_T_CCD_S_MASK 
+#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL                                               0x0004040D
+#define DDRC_DRAMTMG9_T_CCD_S_SHIFT                                                16
+#define DDRC_DRAMTMG9_T_CCD_S_MASK                                                 0x00070000U
+
+/*tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
+		ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
+		R4. Unit: Clocks.*/
+#undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL 
+#undef DDRC_DRAMTMG9_T_RRD_S_SHIFT 
+#undef DDRC_DRAMTMG9_T_RRD_S_MASK 
+#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL                                               0x0004040D
+#define DDRC_DRAMTMG9_T_RRD_S_SHIFT                                                8
+#define DDRC_DRAMTMG9_T_RRD_S_MASK                                                 0x00000F00U
+
+/*CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
+		round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
+		 Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
+		d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
+		is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using 
+		he above equation by 2, and round it up to next integer.*/
+#undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL 
+#undef DDRC_DRAMTMG9_WR2RD_S_SHIFT 
+#undef DDRC_DRAMTMG9_WR2RD_S_MASK 
+#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL                                               0x0004040D
+#define DDRC_DRAMTMG9_WR2RD_S_SHIFT                                                0
+#define DDRC_DRAMTMG9_WR2RD_S_MASK                                                 0x0000003FU
+
+/*tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
+		this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
+		ples of 32 clocks.*/
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 
+#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL                                    0x440C021C
+#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT                                     24
+#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK                                      0x7F000000U
+
+/*tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
+		 RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.*/
+#undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 
+#undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT 
+#undef DDRC_DRAMTMG11_T_MPX_LH_MASK 
+#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL                                             0x440C021C
+#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT                                              16
+#define DDRC_DRAMTMG11_T_MPX_LH_MASK                                               0x001F0000U
+
+/*tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
+		up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.*/
+#undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL 
+#undef DDRC_DRAMTMG11_T_MPX_S_SHIFT 
+#undef DDRC_DRAMTMG11_T_MPX_S_MASK 
+#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL                                              0x440C021C
+#define DDRC_DRAMTMG11_T_MPX_S_SHIFT                                               8
+#define DDRC_DRAMTMG11_T_MPX_S_MASK                                                0x00000300U
+
+/*tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
+		r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
+		teger.*/
+#undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL 
+#undef DDRC_DRAMTMG11_T_CKMPE_SHIFT 
+#undef DDRC_DRAMTMG11_T_CKMPE_MASK 
+#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL                                              0x440C021C
+#define DDRC_DRAMTMG11_T_CKMPE_SHIFT                                               0
+#define DDRC_DRAMTMG11_T_CKMPE_MASK                                                0x0000001FU
+
+/*tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
+		REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.*/
+#undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 
+#undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT 
+#undef DDRC_DRAMTMG12_T_CMDCKE_MASK 
+#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL                                             0x00020610
+#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT                                              16
+#define DDRC_DRAMTMG12_T_CMDCKE_MASK                                               0x00030000U
+
+/*tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
+		/2) and round it up to next integer value.*/
+#undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 
+#undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 
+#undef DDRC_DRAMTMG12_T_CKEHCMD_MASK 
+#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL                                            0x00020610
+#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT                                             8
+#define DDRC_DRAMTMG12_T_CKEHCMD_MASK                                              0x00000F00U
+
+/*tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
+		s to (tMRD_PDA/2) and round it up to next integer value.*/
+#undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 
+#undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 
+#undef DDRC_DRAMTMG12_T_MRD_PDA_MASK 
+#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL                                            0x00020610
+#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT                                             0
+#define DDRC_DRAMTMG12_T_MRD_PDA_MASK                                              0x0000001FU
+
+/*- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
+		ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
+		ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 
+#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL                                             0x02000040
+#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT                                              31
+#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK                                               0x80000000U
+
+/*- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
+		or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
+		own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
+		ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 
+#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL                                            0x02000040
+#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT                                             30
+#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK                                              0x40000000U
+
+/*- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
+		nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
+		rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 
+#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL                                      0x02000040
+#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT                                       29
+#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK                                        0x20000000U
+
+/*- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable 
+		ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
+		gns supporting DDR4 devices.*/
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 
+#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL                                          0x02000040
+#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT                                           28
+#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK                                            0x10000000U
+
+/*tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
+		on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
+		er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
+		ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for 
+		esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 
+#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL                                           0x02000040
+#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT                                            16
+#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK                                             0x07FF0000U
+
+/*tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
+		ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
+		e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
+		s.*/
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 
+#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL                                          0x02000040
+#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT                                           0
+#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK                                            0x000003FFU
+
+/*tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
+		ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is 
+		nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 
+#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL                                          0x02000100
+#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT                                           20
+#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK                                            0x3FF00000U
+
+/*Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
+		PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs 
+		upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 
+#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL                               0x02000100
+#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT                                0
+#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK                                 0x000FFFFFU
+
+/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
+		s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
+		, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
+		 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 
+#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL                                       0x07020002
+#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT                                        24
+#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK                                         0x1F000000U
+
+/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
+		0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
+		fer to PHY specification for correct value.*/
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL                                     0x07020002
+#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT                                      23
+#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK                                       0x00800000U
+
+/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
+		ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
+		, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
+		 latency through the RDIMM. Unit: Clocks*/
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 
+#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL                                        0x07020002
+#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT                                         16
+#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK                                          0x003F0000U
+
+/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
+		.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
+		HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
+		e.*/
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL                                     0x07020002
+#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT                                      15
+#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK                                       0x00008000U
+
+/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
+		 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
+		te, max supported value is 8. Unit: Clocks*/
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 
+#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL                                        0x07020002
+#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT                                         8
+#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK                                          0x00003F00U
+
+/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
+		 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
+		 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
+		rough the RDIMM.*/
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 
+#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL                                         0x07020002
+#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT                                          0
+#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK                                           0x0000003FU
+
+/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. 
+		his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
+		the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8*/
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 
+#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL                                          0x00000404
+#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT                                           28
+#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK                                            0xF0000000U
+
+/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
+		 is driven.*/
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 
+#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL                                        0x00000404
+#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT                                         24
+#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK                                          0x03000000U
+
+/*Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
+		nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
+		 correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to 
+		phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
+		RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
+		: Clocks*/
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 
+#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL                                     0x00000404
+#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT                                      16
+#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK                                       0x001F0000U
+
+/*Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to 
+		he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase 
+		ligned, this timing parameter should be rounded up to the next integer value.*/
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL                                 0x00000404
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT                                  8
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK                                   0x00000F00U
+
+/*Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first 
+		alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
+		not phase aligned, this timing parameter should be rounded up to the next integer value.*/
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL                                  0x00000404
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT                                   0
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK                                    0x0000000FU
+
+/*Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
+		g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.*/
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 
+#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL                                         0x07000000
+#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT                                          24
+#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK                                           0x0F000000U
+
+/*Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
+		cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
+		- 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 
+		31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
+		.*/
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL                                    0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT                                     20
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK                                      0x00F00000U
+
+/*Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
+		nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.*/
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL                                        0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT                                         16
+#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK                                          0x00010000U
+
+/*Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
+		les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 
+		048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
+		72 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL                                     0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT                                      12
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK                                       0x0000F000U
+
+/*Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled*/
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL                                         0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT                                          8
+#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK                                           0x00000100U
+
+/*Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
+		s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
+		8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
+		 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL                                     0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT                                      4
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK                                       0x000000F0U
+
+/*Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled*/
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL                                         0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT                                          0
+#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK                                           0x00000001U
+
+/*Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
+		- 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles 
+		 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
+		D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.*/
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 
+#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL                                   0x00000000
+#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT                                    4
+#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK                                     0x000000F0U
+
+/*Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
+		only present for designs supporting DDR4 devices.*/
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 
+#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL                                       0x00000000
+#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT                                        0
+#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK                                         0x00000001U
+
+/*This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
+		). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
+		t read request when the uMCTL2 is idle. Unit: 1024 clocks*/
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL                       0x00000000
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT                        16
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK                         0x00FF0000U
+
+/*This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; 
+		hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
+		idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
+		e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
+		Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
+		024. Unit: 1024 clocks*/
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL                       0x00000000
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT                        0
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK                         0x000000FFU
+
+/*Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high*/
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 
+#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL                                   0x00000001
+#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT                                    2
+#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK                                     0x00000004U
+
+/*DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
+		in designs configured to support DDR4 and LPDDR4.*/
+#undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 
+#undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 
+#undef DDRC_DFIMISC_PHY_DBI_MODE_MASK 
+#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL                                           0x00000001
+#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT                                            1
+#define DDRC_DFIMISC_PHY_DBI_MODE_MASK                                             0x00000002U
+
+/*PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
+		ion*/
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 
+#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL                                   0x00000001
+#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT                                    0
+#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK                                     0x00000001U
+
+/*>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
+		l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.*/
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 
+#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL                                       0x00000202
+#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT                                        8
+#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK                                         0x00003F00U
+
+/*Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
+		l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.*/
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 
+#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL                                       0x00000202
+#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT                                        0
+#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK                                         0x0000003FU
+
+/*Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
+		as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]*/
+#undef DDRC_DBICTL_RD_DBI_EN_DEFVAL 
+#undef DDRC_DBICTL_RD_DBI_EN_SHIFT 
+#undef DDRC_DBICTL_RD_DBI_EN_MASK 
+#define DDRC_DBICTL_RD_DBI_EN_DEFVAL                                               0x00000001
+#define DDRC_DBICTL_RD_DBI_EN_SHIFT                                                2
+#define DDRC_DBICTL_RD_DBI_EN_MASK                                                 0x00000004U
+
+/*Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
+		ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]*/
+#undef DDRC_DBICTL_WR_DBI_EN_DEFVAL 
+#undef DDRC_DBICTL_WR_DBI_EN_SHIFT 
+#undef DDRC_DBICTL_WR_DBI_EN_MASK 
+#define DDRC_DBICTL_WR_DBI_EN_DEFVAL                                               0x00000001
+#define DDRC_DBICTL_WR_DBI_EN_SHIFT                                                1
+#define DDRC_DBICTL_WR_DBI_EN_MASK                                                 0x00000002U
+
+/*DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
+		mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
+		: Set this to inverted value of MR13[5] which is opposite polarity from this signal*/
+#undef DDRC_DBICTL_DM_EN_DEFVAL 
+#undef DDRC_DBICTL_DM_EN_SHIFT 
+#undef DDRC_DBICTL_DM_EN_MASK 
+#define DDRC_DBICTL_DM_EN_DEFVAL                                                   0x00000001
+#define DDRC_DBICTL_DM_EN_SHIFT                                                    0
+#define DDRC_DBICTL_DM_EN_MASK                                                     0x00000001U
+
+/*Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
+		 bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.*/
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL 
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 
+#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL                                       
+#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT                                        0
+#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK                                         0x0000001FU
+
+/*Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
+		bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.*/
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT                                        16
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK                                         0x001F0000U
+
+/*Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
+		r each of the bank address bits is determined by adding the internal base to the value of this field.*/
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT                                        8
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK                                         0x00001F00U
+
+/*Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
+		r each of the bank address bits is determined by adding the internal base to the value of this field.*/
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT                                        0
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK                                         0x0000001FU
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
+		 Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
+		 this field. If set to 15, this column address bit is set to 0.*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT                                         24
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK                                          0x0F000000U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
+		Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT                                         16
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK                                          0x000F0000U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
+		Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
+		ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
+		 this case.*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT                                         8
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK                                          0x00000F00U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
+		Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
+		ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT                                         0
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK                                          0x0000000FU
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
+		column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
+		 determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: 
+		er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
+		ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
+		 hence column bit 10 is used.*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT                                         24
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK                                          0x0F000000U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
+		 LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
+		ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
+		cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
+		mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
+		.*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT                                         16
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK                                          0x000F0000U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
+		Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT                                         8
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK                                          0x00000F00U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
+		Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT                                         0
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK                                          0x0000000FU
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
+		mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must 
+		e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
+		l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
+		n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
+		dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.*/
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT                                        8
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK                                         0x00000F00U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
+		mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
+		To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
+		termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
+		JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
+		bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
+		nce column bit 10 is used.*/
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT                                        0
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK                                         0x0000000FU
+
+/*Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT                                        24
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK                                         0x0F000000U
+
+/*Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
+		bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF 
+		ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value 
+		5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL                                     0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT                                      16
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK                                       0x000F0000U
+
+/*Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field.*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT                                         8
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK                                          0x00000F00U
+
+/*Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field.*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT                                         0
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK                                          0x0000000FU
+
+/*Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
+		having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
+		y in designs configured to support LPDDR3.*/
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 
+#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT                                        31
+#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK                                         0x80000000U
+
+/*Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT                                        24
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK                                         0x0F000000U
+
+/*Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT                                        16
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK                                         0x000F0000U
+
+/*Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT                                        8
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK                                         0x00000F00U
+
+/*Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT                                        0
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK                                         0x0000000FU
+
+/*Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.*/
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT                                        8
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK                                         0x00000F00U
+
+/*Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.*/
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT                                        0
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK                                         0x0000000FU
+
+/*Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
+		address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If 
+		et to 31, bank group address bit 1 is set to 0.*/
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL                                         0x00000000
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT                                          8
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK                                           0x00001F00U
+
+/*Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
+		bit for each of the bank group address bits is determined by adding the internal base to the value of this field.*/
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL                                         0x00000000
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT                                          0
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK                                           0x0000001FU
+
+/*Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT                                         24
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK                                          0x0F000000U
+
+/*Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT                                         16
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK                                          0x000F0000U
+
+/*Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
+		d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT                                         8
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK                                          0x00000F00U
+
+/*Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
+		d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT                                         0
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK                                          0x0000000FU
+
+/*Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT                                        24
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK                                         0x0F000000U
+
+/*Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT                                        16
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK                                         0x000F0000U
+
+/*Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT                                        8
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK                                         0x00000F00U
+
+/*Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT                                        0
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK                                         0x0000000FU
+
+/*Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit 
+		or each of the row address bits is determined by adding the internal base to the value of this field. This register field is 
+		sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL 
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 
+#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL                                      
+#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT                                       0
+#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK                                        0x0000000FU
+
+/*Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
+		67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - 
+		L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 
+		CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)*/
+#undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 
+#undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 
+#undef DDRC_ODTCFG_WR_ODT_HOLD_MASK 
+#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL                                             0x04000400
+#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT                                              24
+#define DDRC_ODTCFG_WR_ODT_HOLD_MASK                                               0x0F000000U
+
+/*The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
+		remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
+		67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
+		 DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))*/
+#undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 
+#undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 
+#undef DDRC_ODTCFG_WR_ODT_DELAY_MASK 
+#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL                                            0x04000400
+#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT                                             16
+#define DDRC_ODTCFG_WR_ODT_DELAY_MASK                                              0x001F0000U
+
+/*Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
+		 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
+		tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
+		)*/
+#undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 
+#undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 
+#undef DDRC_ODTCFG_RD_ODT_HOLD_MASK 
+#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL                                             0x04000400
+#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT                                              8
+#define DDRC_ODTCFG_RD_ODT_HOLD_MASK                                               0x00000F00U
+
+/*The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must 
+		emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
+		CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
+		L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
+		write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
+		uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)*/
+#undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 
+#undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 
+#undef DDRC_ODTCFG_RD_ODT_DELAY_MASK 
+#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL                                            0x04000400
+#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT                                             2
+#define DDRC_ODTCFG_RD_ODT_DELAY_MASK                                              0x0000007CU
+
+/*Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can 
+		e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
+		 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/
+#undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK1_RD_ODT_MASK 
+#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL                                            0x00002211
+#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT                                             12
+#define DDRC_ODTMAP_RANK1_RD_ODT_MASK                                              0x00003000U
+
+/*Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
+		 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
+		etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/
+#undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK1_WR_ODT_MASK 
+#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL                                            0x00002211
+#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT                                             8
+#define DDRC_ODTMAP_RANK1_WR_ODT_MASK                                              0x00000300U
+
+/*Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can 
+		e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
+		 etc. For each rank, set its bit to 1 to enable its ODT.*/
+#undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK0_RD_ODT_MASK 
+#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL                                            0x00002211
+#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT                                             4
+#define DDRC_ODTMAP_RANK0_RD_ODT_MASK                                              0x00000030U
+
+/*Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
+		 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
+		etc. For each rank, set its bit to 1 to enable its ODT.*/
+#undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK0_WR_ODT_MASK 
+#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL                                            0x00002211
+#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT                                             0
+#define DDRC_ODTMAP_RANK0_WR_ODT_MASK                                              0x00000003U
+
+/*When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
+		non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
+		ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this 
+		egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. 
+		OR PERFORMANCE ONLY*/
+#undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 
+#undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 
+#undef DDRC_SCHED_RDWR_IDLE_GAP_MASK 
+#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL                                            0x00002005
+#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT                                             24
+#define DDRC_SCHED_RDWR_IDLE_GAP_MASK                                              0x7F000000U
+
+/*UNUSED*/
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 
+#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL                                   0x00002005
+#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT                                    16
+#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK                                     0x00FF0000U
+
+/*Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
+		 the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
+		to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
+		priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
+		 than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
+		sing out of single bit error correction RMW operation.*/
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK 
+#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL                                          0x00002005
+#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT                                           8
+#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK                                            0x00003F00U
+
+/*If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
+		e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this 
+		egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
+		es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed 
+		s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
+		ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open 
+		age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
+		ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.*/
+#undef DDRC_SCHED_PAGECLOSE_DEFVAL 
+#undef DDRC_SCHED_PAGECLOSE_SHIFT 
+#undef DDRC_SCHED_PAGECLOSE_MASK 
+#define DDRC_SCHED_PAGECLOSE_DEFVAL                                                0x00002005
+#define DDRC_SCHED_PAGECLOSE_SHIFT                                                 2
+#define DDRC_SCHED_PAGECLOSE_MASK                                                  0x00000004U
+
+/*If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.*/
+#undef DDRC_SCHED_PREFER_WRITE_DEFVAL 
+#undef DDRC_SCHED_PREFER_WRITE_SHIFT 
+#undef DDRC_SCHED_PREFER_WRITE_MASK 
+#define DDRC_SCHED_PREFER_WRITE_DEFVAL                                             0x00002005
+#define DDRC_SCHED_PREFER_WRITE_SHIFT                                              1
+#define DDRC_SCHED_PREFER_WRITE_MASK                                               0x00000002U
+
+/*Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
+		ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
+		e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
+		ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.*/
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK 
+#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL                                          0x00002005
+#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT                                           0
+#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK                                            0x00000001U
+
+/*Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
+		 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 
+#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL                                   0x0F00007F
+#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT                                    24
+#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK                                     0xFF000000U
+
+/*Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
+		er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
+		be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 
+#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL                                        0x0F00007F
+#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT                                         0
+#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK                                          0x0000FFFFU
+
+/*Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
+		transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 
+#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL                                      0x0F00007F
+#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT                                       24
+#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK                                        0xFF000000U
+
+/*Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
+		r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not 
+		e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 
+#undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT 
+#undef DDRC_PERFWR1_W_MAX_STARVE_MASK 
+#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL                                           0x0F00007F
+#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT                                            0
+#define DDRC_PERFWR1_W_MAX_STARVE_MASK                                             0x0000FFFFU
+
+/*All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
+		all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and 
+		wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
+		port DDR4.*/
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL 
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 
+#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL                                        
+#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT                                         0
+#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK                                          0x00000001U
+
+/*When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
+		lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
+		s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.*/
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 
+#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL                                    0x00000000
+#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT                                     4
+#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK                                      0x00000010U
+
+/*When 1, disable write combine. FOR DEBUG ONLY*/
+#undef DDRC_DBG0_DIS_WC_DEFVAL 
+#undef DDRC_DBG0_DIS_WC_SHIFT 
+#undef DDRC_DBG0_DIS_WC_MASK 
+#define DDRC_DBG0_DIS_WC_DEFVAL                                                    0x00000000
+#define DDRC_DBG0_DIS_WC_SHIFT                                                     0
+#define DDRC_DBG0_DIS_WC_MASK                                                      0x00000001U
+
+/*Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
+		the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
+		register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
+		_refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
+		 and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).*/
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 
+#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL                                            0x00000000
+#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT                                             31
+#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK                                              0x80000000U
+
+/*Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in 
+		he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.*/
+#undef DDRC_DBGCMD_CTRLUPD_DEFVAL 
+#undef DDRC_DBGCMD_CTRLUPD_SHIFT 
+#undef DDRC_DBGCMD_CTRLUPD_MASK 
+#define DDRC_DBGCMD_CTRLUPD_DEFVAL                                                 0x00000000
+#define DDRC_DBGCMD_CTRLUPD_SHIFT                                                  5
+#define DDRC_DBGCMD_CTRLUPD_MASK                                                   0x00000020U
+
+/*Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to 
+		he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
+		en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
+		d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
+		de.*/
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 
+#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL                                          0x00000000
+#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT                                           4
+#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK                                            0x00000010U
+
+/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
+		refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
+		be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
+		wn operating modes or Maximum Power Saving Mode.*/
+#undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 
+#undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT 
+#undef DDRC_DBGCMD_RANK1_REFRESH_MASK 
+#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL                                           0x00000000
+#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT                                            1
+#define DDRC_DBGCMD_RANK1_REFRESH_MASK                                             0x00000002U
+
+/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
+		refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
+		be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
+		wn operating modes or Maximum Power Saving Mode.*/
+#undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 
+#undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT 
+#undef DDRC_DBGCMD_RANK0_REFRESH_MASK 
+#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL                                           0x00000000
+#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT                                            0
+#define DDRC_DBGCMD_RANK0_REFRESH_MASK                                             0x00000001U
+
+/*Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back 
+		egister to 1 once programming is done.*/
+#undef DDRC_SWCTL_SW_DONE_DEFVAL 
+#undef DDRC_SWCTL_SW_DONE_SHIFT 
+#undef DDRC_SWCTL_SW_DONE_MASK 
+#define DDRC_SWCTL_SW_DONE_DEFVAL                                                  
+#define DDRC_SWCTL_SW_DONE_SHIFT                                                   0
+#define DDRC_SWCTL_SW_DONE_MASK                                                    0x00000001U
+
+/*Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
+		e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
+		h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
+		ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
+		_mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
+		ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
+		DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
+		only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
+		-AC is enabled*/
+#undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL 
+#undef DDRC_PCCFG_BL_EXP_MODE_SHIFT 
+#undef DDRC_PCCFG_BL_EXP_MODE_MASK 
+#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL                                              0x00000000
+#define DDRC_PCCFG_BL_EXP_MODE_SHIFT                                               8
+#define DDRC_PCCFG_BL_EXP_MODE_MASK                                                0x00000100U
+
+/*Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
+		rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
+		ge DDRC transactions.*/
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 
+#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL                                          0x00000000
+#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT                                           4
+#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK                                            0x00000010U
+
+/*If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based 
+		n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
+		_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.*/
+#undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 
+#undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 
+#undef DDRC_PCCFG_GO2CRITICAL_EN_MASK 
+#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL                                           0x00000000
+#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT                                            0
+#define DDRC_PCCFG_GO2CRITICAL_EN_MASK                                             0x00000001U
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_0_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_0_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_0_PORT_EN_MASK 
+#define DDRC_PCTRL_0_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_0_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_0_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
+#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_1_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_1_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_1_PORT_EN_MASK 
+#define DDRC_PCTRL_1_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_1_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_1_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 
+		ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 
+		s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT                                     24
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK                                      0x03000000U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
+		el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
+		directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 
+		ust be set to distinct values.*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL                                     0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT                                      8
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK                                       0x00000F00U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL                                     0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_2_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_2_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_2_PORT_EN_MASK 
+#define DDRC_PCTRL_2_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_2_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_2_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 
+		ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 
+		s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT                                     24
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK                                      0x03000000U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
+		el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
+		directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 
+		ust be set to distinct values.*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL                                     0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT                                      8
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK                                       0x00000F00U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL                                     0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_3_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_3_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_3_PORT_EN_MASK 
+#define DDRC_PCTRL_3_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_3_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_3_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
+#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT                                    20
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK                                     0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT                                    16
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK                                     0x00030000U
+
+/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.*/
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT                                      0
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for write transactions.*/
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL 
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 
+#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL                                   
+#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT                                    0
+#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_4_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_4_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_4_PORT_EN_MASK 
+#define DDRC_PCTRL_4_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_4_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_4_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
+#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT                                    20
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK                                     0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT                                    16
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK                                     0x00030000U
+
+/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.*/
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT                                      0
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for write transactions.*/
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL 
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 
+#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL                                   
+#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT                                    0
+#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_5_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_5_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_5_PORT_EN_MASK 
+#define DDRC_PCTRL_5_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_5_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_5_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
+#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT                                    20
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK                                     0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT                                    16
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK                                     0x00030000U
+
+/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.*/
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT                                      0
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for write transactions.*/
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL 
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 
+#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL                                   
+#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT                                    0
+#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
+
+/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
+		 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/
+#undef DDRC_SARBASE0_BASE_ADDR_DEFVAL 
+#undef DDRC_SARBASE0_BASE_ADDR_SHIFT 
+#undef DDRC_SARBASE0_BASE_ADDR_MASK 
+#define DDRC_SARBASE0_BASE_ADDR_DEFVAL                                             
+#define DDRC_SARBASE0_BASE_ADDR_SHIFT                                              0
+#define DDRC_SARBASE0_BASE_ADDR_MASK                                               0x000001FFU
+
+/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
+		e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 
+		or example, if register is programmed to 0, region will have 1 block.*/
+#undef DDRC_SARSIZE0_NBLOCKS_DEFVAL 
+#undef DDRC_SARSIZE0_NBLOCKS_SHIFT 
+#undef DDRC_SARSIZE0_NBLOCKS_MASK 
+#define DDRC_SARSIZE0_NBLOCKS_DEFVAL                                               
+#define DDRC_SARSIZE0_NBLOCKS_SHIFT                                                0
+#define DDRC_SARSIZE0_NBLOCKS_MASK                                                 0x000000FFU
+
+/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
+		 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/
+#undef DDRC_SARBASE1_BASE_ADDR_DEFVAL 
+#undef DDRC_SARBASE1_BASE_ADDR_SHIFT 
+#undef DDRC_SARBASE1_BASE_ADDR_MASK 
+#define DDRC_SARBASE1_BASE_ADDR_DEFVAL                                             
+#define DDRC_SARBASE1_BASE_ADDR_SHIFT                                              0
+#define DDRC_SARBASE1_BASE_ADDR_MASK                                               0x000001FFU
+
+/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
+		e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 
+		or example, if register is programmed to 0, region will have 1 block.*/
+#undef DDRC_SARSIZE1_NBLOCKS_DEFVAL 
+#undef DDRC_SARSIZE1_NBLOCKS_SHIFT 
+#undef DDRC_SARSIZE1_NBLOCKS_MASK 
+#define DDRC_SARSIZE1_NBLOCKS_DEFVAL                                               
+#define DDRC_SARSIZE1_NBLOCKS_SHIFT                                                0
+#define DDRC_SARSIZE1_NBLOCKS_MASK                                                 0x000000FFU
+
+/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
+		s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
+		, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
+		 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL                                0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT                                 24
+#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK                                  0x1F000000U
+
+/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
+		0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
+		fer to PHY specification for correct value.*/
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL                              0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT                               23
+#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK                                0x00800000U
+
+/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
+		ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
+		, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
+		 latency through the RDIMM. Unit: Clocks*/
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL                                 0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT                                  16
+#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK                                   0x003F0000U
+
+/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
+		.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
+		HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
+		e.*/
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL                              0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT                               15
+#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK                                0x00008000U
+
+/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
+		 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
+		te, max supported value is 8. Unit: Clocks*/
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL                                 0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT                                  8
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK                                   0x00003F00U
+
+/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
+		 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
+		 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
+		rough the RDIMM.*/
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL                                  0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT                                   0
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK                                    0x0000003FU
+
+/*DDR block level reset inside of the DDR Sub System*/
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 
+#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                                        0x0000000F
+#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                                         3
+#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                                          0x00000008U
+
+/*Address Copy*/
+#undef DDR_PHY_PGCR0_ADCP_DEFVAL 
+#undef DDR_PHY_PGCR0_ADCP_SHIFT 
+#undef DDR_PHY_PGCR0_ADCP_MASK 
+#define DDR_PHY_PGCR0_ADCP_DEFVAL                                                  0x07001E00
+#define DDR_PHY_PGCR0_ADCP_SHIFT                                                   31
+#define DDR_PHY_PGCR0_ADCP_MASK                                                    0x80000000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_30_27_MASK 
+#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL                                        0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT                                         27
+#define DDR_PHY_PGCR0_RESERVED_30_27_MASK                                          0x78000000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_PGCR0_PHYFRST_DEFVAL 
+#undef DDR_PHY_PGCR0_PHYFRST_SHIFT 
+#undef DDR_PHY_PGCR0_PHYFRST_MASK 
+#define DDR_PHY_PGCR0_PHYFRST_DEFVAL                                               0x07001E00
+#define DDR_PHY_PGCR0_PHYFRST_SHIFT                                                26
+#define DDR_PHY_PGCR0_PHYFRST_MASK                                                 0x04000000U
+
+/*Oscillator Mode Address/Command Delay Line Select*/
+#undef DDR_PHY_PGCR0_OSCACDL_DEFVAL 
+#undef DDR_PHY_PGCR0_OSCACDL_SHIFT 
+#undef DDR_PHY_PGCR0_OSCACDL_MASK 
+#define DDR_PHY_PGCR0_OSCACDL_DEFVAL                                               0x07001E00
+#define DDR_PHY_PGCR0_OSCACDL_SHIFT                                                24
+#define DDR_PHY_PGCR0_OSCACDL_MASK                                                 0x03000000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_23_19_MASK 
+#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL                                        0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT                                         19
+#define DDR_PHY_PGCR0_RESERVED_23_19_MASK                                          0x00F80000U
+
+/*Digital Test Output Select*/
+#undef DDR_PHY_PGCR0_DTOSEL_DEFVAL 
+#undef DDR_PHY_PGCR0_DTOSEL_SHIFT 
+#undef DDR_PHY_PGCR0_DTOSEL_MASK 
+#define DDR_PHY_PGCR0_DTOSEL_DEFVAL                                                0x07001E00
+#define DDR_PHY_PGCR0_DTOSEL_SHIFT                                                 14
+#define DDR_PHY_PGCR0_DTOSEL_MASK                                                  0x0007C000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_13_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_13_MASK 
+#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL                                           0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_13_SHIFT                                            13
+#define DDR_PHY_PGCR0_RESERVED_13_MASK                                             0x00002000U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_PGCR0_OSCDIV_DEFVAL 
+#undef DDR_PHY_PGCR0_OSCDIV_SHIFT 
+#undef DDR_PHY_PGCR0_OSCDIV_MASK 
+#define DDR_PHY_PGCR0_OSCDIV_DEFVAL                                                0x07001E00
+#define DDR_PHY_PGCR0_OSCDIV_SHIFT                                                 9
+#define DDR_PHY_PGCR0_OSCDIV_MASK                                                  0x00001E00U
+
+/*Oscillator Enable*/
+#undef DDR_PHY_PGCR0_OSCEN_DEFVAL 
+#undef DDR_PHY_PGCR0_OSCEN_SHIFT 
+#undef DDR_PHY_PGCR0_OSCEN_MASK 
+#define DDR_PHY_PGCR0_OSCEN_DEFVAL                                                 0x07001E00
+#define DDR_PHY_PGCR0_OSCEN_SHIFT                                                  8
+#define DDR_PHY_PGCR0_OSCEN_MASK                                                   0x00000100U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_7_0_MASK 
+#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL                                          0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT                                           0
+#define DDR_PHY_PGCR0_RESERVED_7_0_MASK                                            0x000000FFU
+
+/*Clear Training Status Registers*/
+#undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 
+#undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT 
+#undef DDR_PHY_PGCR2_CLRTSTAT_MASK 
+#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL                                              0x00F12480
+#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT                                               31
+#define DDR_PHY_PGCR2_CLRTSTAT_MASK                                                0x80000000U
+
+/*Clear Impedance Calibration*/
+#undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL 
+#undef DDR_PHY_PGCR2_CLRZCAL_SHIFT 
+#undef DDR_PHY_PGCR2_CLRZCAL_MASK 
+#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL                                               0x00F12480
+#define DDR_PHY_PGCR2_CLRZCAL_SHIFT                                                30
+#define DDR_PHY_PGCR2_CLRZCAL_MASK                                                 0x40000000U
+
+/*Clear Parity Error*/
+#undef DDR_PHY_PGCR2_CLRPERR_DEFVAL 
+#undef DDR_PHY_PGCR2_CLRPERR_SHIFT 
+#undef DDR_PHY_PGCR2_CLRPERR_MASK 
+#define DDR_PHY_PGCR2_CLRPERR_DEFVAL                                               0x00F12480
+#define DDR_PHY_PGCR2_CLRPERR_SHIFT                                                29
+#define DDR_PHY_PGCR2_CLRPERR_MASK                                                 0x20000000U
+
+/*Initialization Complete Pin Configuration*/
+#undef DDR_PHY_PGCR2_ICPC_DEFVAL 
+#undef DDR_PHY_PGCR2_ICPC_SHIFT 
+#undef DDR_PHY_PGCR2_ICPC_MASK 
+#define DDR_PHY_PGCR2_ICPC_DEFVAL                                                  0x00F12480
+#define DDR_PHY_PGCR2_ICPC_SHIFT                                                   28
+#define DDR_PHY_PGCR2_ICPC_MASK                                                    0x10000000U
+
+/*Data Training PUB Mode Exit Timer*/
+#undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 
+#undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT 
+#undef DDR_PHY_PGCR2_DTPMXTMR_MASK 
+#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL                                              0x00F12480
+#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT                                               20
+#define DDR_PHY_PGCR2_DTPMXTMR_MASK                                                0x0FF00000U
+
+/*Initialization Bypass*/
+#undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 
+#undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT 
+#undef DDR_PHY_PGCR2_INITFSMBYP_MASK 
+#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL                                            0x00F12480
+#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT                                             19
+#define DDR_PHY_PGCR2_INITFSMBYP_MASK                                              0x00080000U
+
+/*PLL FSM Bypass*/
+#undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 
+#undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 
+#undef DDR_PHY_PGCR2_PLLFSMBYP_MASK 
+#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL                                             0x00F12480
+#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT                                              18
+#define DDR_PHY_PGCR2_PLLFSMBYP_MASK                                               0x00040000U
+
+/*Refresh Period*/
+#undef DDR_PHY_PGCR2_TREFPRD_DEFVAL 
+#undef DDR_PHY_PGCR2_TREFPRD_SHIFT 
+#undef DDR_PHY_PGCR2_TREFPRD_MASK 
+#define DDR_PHY_PGCR2_TREFPRD_DEFVAL                                               0x00F12480
+#define DDR_PHY_PGCR2_TREFPRD_SHIFT                                                0
+#define DDR_PHY_PGCR2_TREFPRD_MASK                                                 0x0003FFFFU
+
+/*Frequency B Ratio Term*/
+#undef DDR_PHY_PGCR5_FRQBT_DEFVAL 
+#undef DDR_PHY_PGCR5_FRQBT_SHIFT 
+#undef DDR_PHY_PGCR5_FRQBT_MASK 
+#define DDR_PHY_PGCR5_FRQBT_DEFVAL                                                 0x01010000
+#define DDR_PHY_PGCR5_FRQBT_SHIFT                                                  24
+#define DDR_PHY_PGCR5_FRQBT_MASK                                                   0xFF000000U
+
+/*Frequency A Ratio Term*/
+#undef DDR_PHY_PGCR5_FRQAT_DEFVAL 
+#undef DDR_PHY_PGCR5_FRQAT_SHIFT 
+#undef DDR_PHY_PGCR5_FRQAT_MASK 
+#define DDR_PHY_PGCR5_FRQAT_DEFVAL                                                 0x01010000
+#define DDR_PHY_PGCR5_FRQAT_SHIFT                                                  16
+#define DDR_PHY_PGCR5_FRQAT_MASK                                                   0x00FF0000U
+
+/*DFI Disconnect Time Period*/
+#undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 
+#undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 
+#undef DDR_PHY_PGCR5_DISCNPERIOD_MASK 
+#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL                                           0x01010000
+#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT                                            8
+#define DDR_PHY_PGCR5_DISCNPERIOD_MASK                                             0x0000FF00U
+
+/*Receiver bias core side control*/
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK 
+#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL                                           0x01010000
+#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT                                            4
+#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK                                             0x000000F0U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL 
+#undef DDR_PHY_PGCR5_RESERVED_3_SHIFT 
+#undef DDR_PHY_PGCR5_RESERVED_3_MASK 
+#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL                                            0x01010000
+#define DDR_PHY_PGCR5_RESERVED_3_SHIFT                                             3
+#define DDR_PHY_PGCR5_RESERVED_3_MASK                                              0x00000008U
+
+/*Internal VREF generator REFSEL ragne select*/
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK 
+#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL                                        0x01010000
+#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT                                         2
+#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK                                          0x00000004U
+
+/*DDL Page Read Write select*/
+#undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL 
+#undef DDR_PHY_PGCR5_DDLPGACT_SHIFT 
+#undef DDR_PHY_PGCR5_DDLPGACT_MASK 
+#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL                                              0x01010000
+#define DDR_PHY_PGCR5_DDLPGACT_SHIFT                                               1
+#define DDR_PHY_PGCR5_DDLPGACT_MASK                                                0x00000002U
+
+/*DDL Page Read Write select*/
+#undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL 
+#undef DDR_PHY_PGCR5_DDLPGRW_SHIFT 
+#undef DDR_PHY_PGCR5_DDLPGRW_MASK 
+#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL                                               0x01010000
+#define DDR_PHY_PGCR5_DDLPGRW_SHIFT                                                0
+#define DDR_PHY_PGCR5_DDLPGRW_MASK                                                 0x00000001U
+
+/*PLL Power-Down Time*/
+#undef DDR_PHY_PTR0_TPLLPD_DEFVAL 
+#undef DDR_PHY_PTR0_TPLLPD_SHIFT 
+#undef DDR_PHY_PTR0_TPLLPD_MASK 
+#define DDR_PHY_PTR0_TPLLPD_DEFVAL                                                 0x42C21590
+#define DDR_PHY_PTR0_TPLLPD_SHIFT                                                  21
+#define DDR_PHY_PTR0_TPLLPD_MASK                                                   0xFFE00000U
+
+/*PLL Gear Shift Time*/
+#undef DDR_PHY_PTR0_TPLLGS_DEFVAL 
+#undef DDR_PHY_PTR0_TPLLGS_SHIFT 
+#undef DDR_PHY_PTR0_TPLLGS_MASK 
+#define DDR_PHY_PTR0_TPLLGS_DEFVAL                                                 0x42C21590
+#define DDR_PHY_PTR0_TPLLGS_SHIFT                                                  6
+#define DDR_PHY_PTR0_TPLLGS_MASK                                                   0x001FFFC0U
+
+/*PHY Reset Time*/
+#undef DDR_PHY_PTR0_TPHYRST_DEFVAL 
+#undef DDR_PHY_PTR0_TPHYRST_SHIFT 
+#undef DDR_PHY_PTR0_TPHYRST_MASK 
+#define DDR_PHY_PTR0_TPHYRST_DEFVAL                                                0x42C21590
+#define DDR_PHY_PTR0_TPHYRST_SHIFT                                                 0
+#define DDR_PHY_PTR0_TPHYRST_MASK                                                  0x0000003FU
+
+/*PLL Lock Time*/
+#undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL 
+#undef DDR_PHY_PTR1_TPLLLOCK_SHIFT 
+#undef DDR_PHY_PTR1_TPLLLOCK_MASK 
+#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL                                               0xD05612C0
+#define DDR_PHY_PTR1_TPLLLOCK_SHIFT                                                16
+#define DDR_PHY_PTR1_TPLLLOCK_MASK                                                 0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_PTR1_RESERVED_15_13_MASK 
+#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL                                         0xD05612C0
+#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT                                          13
+#define DDR_PHY_PTR1_RESERVED_15_13_MASK                                           0x0000E000U
+
+/*PLL Reset Time*/
+#undef DDR_PHY_PTR1_TPLLRST_DEFVAL 
+#undef DDR_PHY_PTR1_TPLLRST_SHIFT 
+#undef DDR_PHY_PTR1_TPLLRST_MASK 
+#define DDR_PHY_PTR1_TPLLRST_DEFVAL                                                0xD05612C0
+#define DDR_PHY_PTR1_TPLLRST_SHIFT                                                 0
+#define DDR_PHY_PTR1_TPLLRST_MASK                                                  0x00001FFFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_31_28_MASK 
+#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL                                        0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT                                         28
+#define DDR_PHY_DSGCR_RESERVED_31_28_MASK                                          0xF0000000U
+
+/*When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
+		fault calculation.*/
+#undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 
+#undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT 
+#undef DDR_PHY_DSGCR_RDBICLSEL_MASK 
+#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL                                             0x02A04101
+#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT                                              27
+#define DDR_PHY_DSGCR_RDBICLSEL_MASK                                               0x08000000U
+
+/*When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.*/
+#undef DDR_PHY_DSGCR_RDBICL_DEFVAL 
+#undef DDR_PHY_DSGCR_RDBICL_SHIFT 
+#undef DDR_PHY_DSGCR_RDBICL_MASK 
+#define DDR_PHY_DSGCR_RDBICL_DEFVAL                                                0x02A04101
+#define DDR_PHY_DSGCR_RDBICL_SHIFT                                                 24
+#define DDR_PHY_DSGCR_RDBICL_MASK                                                  0x07000000U
+
+/*PHY Impedance Update Enable*/
+#undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL 
+#undef DDR_PHY_DSGCR_PHYZUEN_SHIFT 
+#undef DDR_PHY_DSGCR_PHYZUEN_MASK 
+#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL                                               0x02A04101
+#define DDR_PHY_DSGCR_PHYZUEN_SHIFT                                                23
+#define DDR_PHY_DSGCR_PHYZUEN_MASK                                                 0x00800000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_22_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_22_MASK 
+#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL                                           0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_22_SHIFT                                            22
+#define DDR_PHY_DSGCR_RESERVED_22_MASK                                             0x00400000U
+
+/*SDRAM Reset Output Enable*/
+#undef DDR_PHY_DSGCR_RSTOE_DEFVAL 
+#undef DDR_PHY_DSGCR_RSTOE_SHIFT 
+#undef DDR_PHY_DSGCR_RSTOE_MASK 
+#define DDR_PHY_DSGCR_RSTOE_DEFVAL                                                 0x02A04101
+#define DDR_PHY_DSGCR_RSTOE_SHIFT                                                  21
+#define DDR_PHY_DSGCR_RSTOE_MASK                                                   0x00200000U
+
+/*Single Data Rate Mode*/
+#undef DDR_PHY_DSGCR_SDRMODE_DEFVAL 
+#undef DDR_PHY_DSGCR_SDRMODE_SHIFT 
+#undef DDR_PHY_DSGCR_SDRMODE_MASK 
+#define DDR_PHY_DSGCR_SDRMODE_DEFVAL                                               0x02A04101
+#define DDR_PHY_DSGCR_SDRMODE_SHIFT                                                19
+#define DDR_PHY_DSGCR_SDRMODE_MASK                                                 0x00180000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_18_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_18_MASK 
+#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL                                           0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_18_SHIFT                                            18
+#define DDR_PHY_DSGCR_RESERVED_18_MASK                                             0x00040000U
+
+/*ATO Analog Test Enable*/
+#undef DDR_PHY_DSGCR_ATOAE_DEFVAL 
+#undef DDR_PHY_DSGCR_ATOAE_SHIFT 
+#undef DDR_PHY_DSGCR_ATOAE_MASK 
+#define DDR_PHY_DSGCR_ATOAE_DEFVAL                                                 0x02A04101
+#define DDR_PHY_DSGCR_ATOAE_SHIFT                                                  17
+#define DDR_PHY_DSGCR_ATOAE_MASK                                                   0x00020000U
+
+/*DTO Output Enable*/
+#undef DDR_PHY_DSGCR_DTOOE_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOOE_SHIFT 
+#undef DDR_PHY_DSGCR_DTOOE_MASK 
+#define DDR_PHY_DSGCR_DTOOE_DEFVAL                                                 0x02A04101
+#define DDR_PHY_DSGCR_DTOOE_SHIFT                                                  16
+#define DDR_PHY_DSGCR_DTOOE_MASK                                                   0x00010000U
+
+/*DTO I/O Mode*/
+#undef DDR_PHY_DSGCR_DTOIOM_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOIOM_SHIFT 
+#undef DDR_PHY_DSGCR_DTOIOM_MASK 
+#define DDR_PHY_DSGCR_DTOIOM_DEFVAL                                                0x02A04101
+#define DDR_PHY_DSGCR_DTOIOM_SHIFT                                                 15
+#define DDR_PHY_DSGCR_DTOIOM_MASK                                                  0x00008000U
+
+/*DTO Power Down Receiver*/
+#undef DDR_PHY_DSGCR_DTOPDR_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOPDR_SHIFT 
+#undef DDR_PHY_DSGCR_DTOPDR_MASK 
+#define DDR_PHY_DSGCR_DTOPDR_DEFVAL                                                0x02A04101
+#define DDR_PHY_DSGCR_DTOPDR_SHIFT                                                 14
+#define DDR_PHY_DSGCR_DTOPDR_MASK                                                  0x00004000U
+
+/*Reserved. Return zeroes on reads*/
+#undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_13_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_13_MASK 
+#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL                                           0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_13_SHIFT                                            13
+#define DDR_PHY_DSGCR_RESERVED_13_MASK                                             0x00002000U
+
+/*DTO On-Die Termination*/
+#undef DDR_PHY_DSGCR_DTOODT_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOODT_SHIFT 
+#undef DDR_PHY_DSGCR_DTOODT_MASK 
+#define DDR_PHY_DSGCR_DTOODT_DEFVAL                                                0x02A04101
+#define DDR_PHY_DSGCR_DTOODT_SHIFT                                                 12
+#define DDR_PHY_DSGCR_DTOODT_MASK                                                  0x00001000U
+
+/*PHY Update Acknowledge Delay*/
+#undef DDR_PHY_DSGCR_PUAD_DEFVAL 
+#undef DDR_PHY_DSGCR_PUAD_SHIFT 
+#undef DDR_PHY_DSGCR_PUAD_MASK 
+#define DDR_PHY_DSGCR_PUAD_DEFVAL                                                  0x02A04101
+#define DDR_PHY_DSGCR_PUAD_SHIFT                                                   6
+#define DDR_PHY_DSGCR_PUAD_MASK                                                    0x00000FC0U
+
+/*Controller Update Acknowledge Enable*/
+#undef DDR_PHY_DSGCR_CUAEN_DEFVAL 
+#undef DDR_PHY_DSGCR_CUAEN_SHIFT 
+#undef DDR_PHY_DSGCR_CUAEN_MASK 
+#define DDR_PHY_DSGCR_CUAEN_DEFVAL                                                 0x02A04101
+#define DDR_PHY_DSGCR_CUAEN_SHIFT                                                  5
+#define DDR_PHY_DSGCR_CUAEN_MASK                                                   0x00000020U
+
+/*Reserved. Return zeroes on reads*/
+#undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_4_3_MASK 
+#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL                                          0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT                                           3
+#define DDR_PHY_DSGCR_RESERVED_4_3_MASK                                            0x00000018U
+
+/*Controller Impedance Update Enable*/
+#undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL 
+#undef DDR_PHY_DSGCR_CTLZUEN_SHIFT 
+#undef DDR_PHY_DSGCR_CTLZUEN_MASK 
+#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL                                               0x02A04101
+#define DDR_PHY_DSGCR_CTLZUEN_SHIFT                                                2
+#define DDR_PHY_DSGCR_CTLZUEN_MASK                                                 0x00000004U
+
+/*Reserved. Return zeroes on reads*/
+#undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_1_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_1_MASK 
+#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL                                            0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_1_SHIFT                                             1
+#define DDR_PHY_DSGCR_RESERVED_1_MASK                                              0x00000002U
+
+/*PHY Update Request Enable*/
+#undef DDR_PHY_DSGCR_PUREN_DEFVAL 
+#undef DDR_PHY_DSGCR_PUREN_SHIFT 
+#undef DDR_PHY_DSGCR_PUREN_MASK 
+#define DDR_PHY_DSGCR_PUREN_DEFVAL                                                 0x02A04101
+#define DDR_PHY_DSGCR_PUREN_SHIFT                                                  0
+#define DDR_PHY_DSGCR_PUREN_MASK                                                   0x00000001U
+
+/*DDR4 Gear Down Timing.*/
+#undef DDR_PHY_DCR_GEARDN_DEFVAL 
+#undef DDR_PHY_DCR_GEARDN_SHIFT 
+#undef DDR_PHY_DCR_GEARDN_MASK 
+#define DDR_PHY_DCR_GEARDN_DEFVAL                                                  0x0000040D
+#define DDR_PHY_DCR_GEARDN_SHIFT                                                   31
+#define DDR_PHY_DCR_GEARDN_MASK                                                    0x80000000U
+
+/*Un-used Bank Group*/
+#undef DDR_PHY_DCR_UBG_DEFVAL 
+#undef DDR_PHY_DCR_UBG_SHIFT 
+#undef DDR_PHY_DCR_UBG_MASK 
+#define DDR_PHY_DCR_UBG_DEFVAL                                                     0x0000040D
+#define DDR_PHY_DCR_UBG_SHIFT                                                      30
+#define DDR_PHY_DCR_UBG_MASK                                                       0x40000000U
+
+/*Un-buffered DIMM Address Mirroring*/
+#undef DDR_PHY_DCR_UDIMM_DEFVAL 
+#undef DDR_PHY_DCR_UDIMM_SHIFT 
+#undef DDR_PHY_DCR_UDIMM_MASK 
+#define DDR_PHY_DCR_UDIMM_DEFVAL                                                   0x0000040D
+#define DDR_PHY_DCR_UDIMM_SHIFT                                                    29
+#define DDR_PHY_DCR_UDIMM_MASK                                                     0x20000000U
+
+/*DDR 2T Timing*/
+#undef DDR_PHY_DCR_DDR2T_DEFVAL 
+#undef DDR_PHY_DCR_DDR2T_SHIFT 
+#undef DDR_PHY_DCR_DDR2T_MASK 
+#define DDR_PHY_DCR_DDR2T_DEFVAL                                                   0x0000040D
+#define DDR_PHY_DCR_DDR2T_SHIFT                                                    28
+#define DDR_PHY_DCR_DDR2T_MASK                                                     0x10000000U
+
+/*No Simultaneous Rank Access*/
+#undef DDR_PHY_DCR_NOSRA_DEFVAL 
+#undef DDR_PHY_DCR_NOSRA_SHIFT 
+#undef DDR_PHY_DCR_NOSRA_MASK 
+#define DDR_PHY_DCR_NOSRA_DEFVAL                                                   0x0000040D
+#define DDR_PHY_DCR_NOSRA_SHIFT                                                    27
+#define DDR_PHY_DCR_NOSRA_MASK                                                     0x08000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL 
+#undef DDR_PHY_DCR_RESERVED_26_18_SHIFT 
+#undef DDR_PHY_DCR_RESERVED_26_18_MASK 
+#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL                                          0x0000040D
+#define DDR_PHY_DCR_RESERVED_26_18_SHIFT                                           18
+#define DDR_PHY_DCR_RESERVED_26_18_MASK                                            0x07FC0000U
+
+/*Byte Mask*/
+#undef DDR_PHY_DCR_BYTEMASK_DEFVAL 
+#undef DDR_PHY_DCR_BYTEMASK_SHIFT 
+#undef DDR_PHY_DCR_BYTEMASK_MASK 
+#define DDR_PHY_DCR_BYTEMASK_DEFVAL                                                0x0000040D
+#define DDR_PHY_DCR_BYTEMASK_SHIFT                                                 10
+#define DDR_PHY_DCR_BYTEMASK_MASK                                                  0x0003FC00U
+
+/*DDR Type*/
+#undef DDR_PHY_DCR_DDRTYPE_DEFVAL 
+#undef DDR_PHY_DCR_DDRTYPE_SHIFT 
+#undef DDR_PHY_DCR_DDRTYPE_MASK 
+#define DDR_PHY_DCR_DDRTYPE_DEFVAL                                                 0x0000040D
+#define DDR_PHY_DCR_DDRTYPE_SHIFT                                                  8
+#define DDR_PHY_DCR_DDRTYPE_MASK                                                   0x00000300U
+
+/*Multi-Purpose Register (MPR) DQ (DDR3 Only)*/
+#undef DDR_PHY_DCR_MPRDQ_DEFVAL 
+#undef DDR_PHY_DCR_MPRDQ_SHIFT 
+#undef DDR_PHY_DCR_MPRDQ_MASK 
+#define DDR_PHY_DCR_MPRDQ_DEFVAL                                                   0x0000040D
+#define DDR_PHY_DCR_MPRDQ_SHIFT                                                    7
+#define DDR_PHY_DCR_MPRDQ_MASK                                                     0x00000080U
+
+/*Primary DQ (DDR3 Only)*/
+#undef DDR_PHY_DCR_PDQ_DEFVAL 
+#undef DDR_PHY_DCR_PDQ_SHIFT 
+#undef DDR_PHY_DCR_PDQ_MASK 
+#define DDR_PHY_DCR_PDQ_DEFVAL                                                     0x0000040D
+#define DDR_PHY_DCR_PDQ_SHIFT                                                      4
+#define DDR_PHY_DCR_PDQ_MASK                                                       0x00000070U
+
+/*DDR 8-Bank*/
+#undef DDR_PHY_DCR_DDR8BNK_DEFVAL 
+#undef DDR_PHY_DCR_DDR8BNK_SHIFT 
+#undef DDR_PHY_DCR_DDR8BNK_MASK 
+#define DDR_PHY_DCR_DDR8BNK_DEFVAL                                                 0x0000040D
+#define DDR_PHY_DCR_DDR8BNK_SHIFT                                                  3
+#define DDR_PHY_DCR_DDR8BNK_MASK                                                   0x00000008U
+
+/*DDR Mode*/
+#undef DDR_PHY_DCR_DDRMD_DEFVAL 
+#undef DDR_PHY_DCR_DDRMD_SHIFT 
+#undef DDR_PHY_DCR_DDRMD_MASK 
+#define DDR_PHY_DCR_DDRMD_DEFVAL                                                   0x0000040D
+#define DDR_PHY_DCR_DDRMD_SHIFT                                                    0
+#define DDR_PHY_DCR_DDRMD_MASK                                                     0x00000007U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_31_29_MASK 
+#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL                                        0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT                                         29
+#define DDR_PHY_DTPR0_RESERVED_31_29_MASK                                          0xE0000000U
+
+/*Activate to activate command delay (different banks)*/
+#undef DDR_PHY_DTPR0_TRRD_DEFVAL 
+#undef DDR_PHY_DTPR0_TRRD_SHIFT 
+#undef DDR_PHY_DTPR0_TRRD_MASK 
+#define DDR_PHY_DTPR0_TRRD_DEFVAL                                                  0x105A2D08
+#define DDR_PHY_DTPR0_TRRD_SHIFT                                                   24
+#define DDR_PHY_DTPR0_TRRD_MASK                                                    0x1F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_23_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_23_MASK 
+#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL                                           0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_23_SHIFT                                            23
+#define DDR_PHY_DTPR0_RESERVED_23_MASK                                             0x00800000U
+
+/*Activate to precharge command delay*/
+#undef DDR_PHY_DTPR0_TRAS_DEFVAL 
+#undef DDR_PHY_DTPR0_TRAS_SHIFT 
+#undef DDR_PHY_DTPR0_TRAS_MASK 
+#define DDR_PHY_DTPR0_TRAS_DEFVAL                                                  0x105A2D08
+#define DDR_PHY_DTPR0_TRAS_SHIFT                                                   16
+#define DDR_PHY_DTPR0_TRAS_MASK                                                    0x007F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_15_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_15_MASK 
+#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL                                           0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_15_SHIFT                                            15
+#define DDR_PHY_DTPR0_RESERVED_15_MASK                                             0x00008000U
+
+/*Precharge command period*/
+#undef DDR_PHY_DTPR0_TRP_DEFVAL 
+#undef DDR_PHY_DTPR0_TRP_SHIFT 
+#undef DDR_PHY_DTPR0_TRP_MASK 
+#define DDR_PHY_DTPR0_TRP_DEFVAL                                                   0x105A2D08
+#define DDR_PHY_DTPR0_TRP_SHIFT                                                    8
+#define DDR_PHY_DTPR0_TRP_MASK                                                     0x00007F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL                                          0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT                                           5
+#define DDR_PHY_DTPR0_RESERVED_7_5_MASK                                            0x000000E0U
+
+/*Internal read to precharge command delay*/
+#undef DDR_PHY_DTPR0_TRTP_DEFVAL 
+#undef DDR_PHY_DTPR0_TRTP_SHIFT 
+#undef DDR_PHY_DTPR0_TRTP_MASK 
+#define DDR_PHY_DTPR0_TRTP_DEFVAL                                                  0x105A2D08
+#define DDR_PHY_DTPR0_TRTP_SHIFT                                                   0
+#define DDR_PHY_DTPR0_TRTP_MASK                                                    0x0000001FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_31_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_31_MASK 
+#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL                                           0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_31_SHIFT                                            31
+#define DDR_PHY_DTPR1_RESERVED_31_MASK                                             0x80000000U
+
+/*Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.*/
+#undef DDR_PHY_DTPR1_TWLMRD_DEFVAL 
+#undef DDR_PHY_DTPR1_TWLMRD_SHIFT 
+#undef DDR_PHY_DTPR1_TWLMRD_MASK 
+#define DDR_PHY_DTPR1_TWLMRD_DEFVAL                                                0x5656041E
+#define DDR_PHY_DTPR1_TWLMRD_SHIFT                                                 24
+#define DDR_PHY_DTPR1_TWLMRD_MASK                                                  0x7F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_23_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_23_MASK 
+#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL                                           0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_23_SHIFT                                            23
+#define DDR_PHY_DTPR1_RESERVED_23_MASK                                             0x00800000U
+
+/*4-bank activate period*/
+#undef DDR_PHY_DTPR1_TFAW_DEFVAL 
+#undef DDR_PHY_DTPR1_TFAW_SHIFT 
+#undef DDR_PHY_DTPR1_TFAW_MASK 
+#define DDR_PHY_DTPR1_TFAW_DEFVAL                                                  0x5656041E
+#define DDR_PHY_DTPR1_TFAW_SHIFT                                                   16
+#define DDR_PHY_DTPR1_TFAW_MASK                                                    0x007F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_15_11_MASK 
+#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL                                        0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT                                         11
+#define DDR_PHY_DTPR1_RESERVED_15_11_MASK                                          0x0000F800U
+
+/*Load mode update delay (DDR4 and DDR3 only)*/
+#undef DDR_PHY_DTPR1_TMOD_DEFVAL 
+#undef DDR_PHY_DTPR1_TMOD_SHIFT 
+#undef DDR_PHY_DTPR1_TMOD_MASK 
+#define DDR_PHY_DTPR1_TMOD_DEFVAL                                                  0x5656041E
+#define DDR_PHY_DTPR1_TMOD_SHIFT                                                   8
+#define DDR_PHY_DTPR1_TMOD_MASK                                                    0x00000700U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL                                          0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT                                           5
+#define DDR_PHY_DTPR1_RESERVED_7_5_MASK                                            0x000000E0U
+
+/*Load mode cycle time*/
+#undef DDR_PHY_DTPR1_TMRD_DEFVAL 
+#undef DDR_PHY_DTPR1_TMRD_SHIFT 
+#undef DDR_PHY_DTPR1_TMRD_MASK 
+#define DDR_PHY_DTPR1_TMRD_DEFVAL                                                  0x5656041E
+#define DDR_PHY_DTPR1_TMRD_SHIFT                                                   0
+#define DDR_PHY_DTPR1_TMRD_MASK                                                    0x0000001FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_31_29_MASK 
+#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL                                        0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT                                         29
+#define DDR_PHY_DTPR2_RESERVED_31_29_MASK                                          0xE0000000U
+
+/*Read to Write command delay. Valid values are*/
+#undef DDR_PHY_DTPR2_TRTW_DEFVAL 
+#undef DDR_PHY_DTPR2_TRTW_SHIFT 
+#undef DDR_PHY_DTPR2_TRTW_MASK 
+#define DDR_PHY_DTPR2_TRTW_DEFVAL                                                  0x000B01D0
+#define DDR_PHY_DTPR2_TRTW_SHIFT                                                   28
+#define DDR_PHY_DTPR2_TRTW_MASK                                                    0x10000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_27_25_MASK 
+#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL                                        0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT                                         25
+#define DDR_PHY_DTPR2_RESERVED_27_25_MASK                                          0x0E000000U
+
+/*Read to ODT delay (DDR3 only)*/
+#undef DDR_PHY_DTPR2_TRTODT_DEFVAL 
+#undef DDR_PHY_DTPR2_TRTODT_SHIFT 
+#undef DDR_PHY_DTPR2_TRTODT_MASK 
+#define DDR_PHY_DTPR2_TRTODT_DEFVAL                                                0x000B01D0
+#define DDR_PHY_DTPR2_TRTODT_SHIFT                                                 24
+#define DDR_PHY_DTPR2_TRTODT_MASK                                                  0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_23_20_MASK 
+#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL                                        0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT                                         20
+#define DDR_PHY_DTPR2_RESERVED_23_20_MASK                                          0x00F00000U
+
+/*CKE minimum pulse width*/
+#undef DDR_PHY_DTPR2_TCKE_DEFVAL 
+#undef DDR_PHY_DTPR2_TCKE_SHIFT 
+#undef DDR_PHY_DTPR2_TCKE_MASK 
+#define DDR_PHY_DTPR2_TCKE_DEFVAL                                                  0x000B01D0
+#define DDR_PHY_DTPR2_TCKE_SHIFT                                                   16
+#define DDR_PHY_DTPR2_TCKE_MASK                                                    0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_15_10_MASK 
+#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL                                        0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT                                         10
+#define DDR_PHY_DTPR2_RESERVED_15_10_MASK                                          0x0000FC00U
+
+/*Self refresh exit delay*/
+#undef DDR_PHY_DTPR2_TXS_DEFVAL 
+#undef DDR_PHY_DTPR2_TXS_SHIFT 
+#undef DDR_PHY_DTPR2_TXS_MASK 
+#define DDR_PHY_DTPR2_TXS_DEFVAL                                                   0x000B01D0
+#define DDR_PHY_DTPR2_TXS_SHIFT                                                    0
+#define DDR_PHY_DTPR2_TXS_MASK                                                     0x000003FFU
+
+/*ODT turn-off delay extension*/
+#undef DDR_PHY_DTPR3_TOFDX_DEFVAL 
+#undef DDR_PHY_DTPR3_TOFDX_SHIFT 
+#undef DDR_PHY_DTPR3_TOFDX_MASK 
+#define DDR_PHY_DTPR3_TOFDX_DEFVAL                                                 0x02000804
+#define DDR_PHY_DTPR3_TOFDX_SHIFT                                                  29
+#define DDR_PHY_DTPR3_TOFDX_MASK                                                   0xE0000000U
+
+/*Read to read and write to write command delay*/
+#undef DDR_PHY_DTPR3_TCCD_DEFVAL 
+#undef DDR_PHY_DTPR3_TCCD_SHIFT 
+#undef DDR_PHY_DTPR3_TCCD_MASK 
+#define DDR_PHY_DTPR3_TCCD_DEFVAL                                                  0x02000804
+#define DDR_PHY_DTPR3_TCCD_SHIFT                                                   26
+#define DDR_PHY_DTPR3_TCCD_MASK                                                    0x1C000000U
+
+/*DLL locking time*/
+#undef DDR_PHY_DTPR3_TDLLK_DEFVAL 
+#undef DDR_PHY_DTPR3_TDLLK_SHIFT 
+#undef DDR_PHY_DTPR3_TDLLK_MASK 
+#define DDR_PHY_DTPR3_TDLLK_DEFVAL                                                 0x02000804
+#define DDR_PHY_DTPR3_TDLLK_SHIFT                                                  16
+#define DDR_PHY_DTPR3_TDLLK_MASK                                                   0x03FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 
+#undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 
+#undef DDR_PHY_DTPR3_RESERVED_15_12_MASK 
+#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL                                        0x02000804
+#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT                                         12
+#define DDR_PHY_DTPR3_RESERVED_15_12_MASK                                          0x0000F000U
+
+/*Maximum DQS output access time from CK/CK# (LPDDR2/3 only)*/
+#undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 
+#undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 
+#undef DDR_PHY_DTPR3_TDQSCKMAX_MASK 
+#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL                                             0x02000804
+#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT                                              8
+#define DDR_PHY_DTPR3_TDQSCKMAX_MASK                                               0x00000F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 
+#undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 
+#undef DDR_PHY_DTPR3_RESERVED_7_3_MASK 
+#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL                                          0x02000804
+#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT                                           3
+#define DDR_PHY_DTPR3_RESERVED_7_3_MASK                                            0x000000F8U
+
+/*DQS output access time from CK/CK# (LPDDR2/3 only)*/
+#undef DDR_PHY_DTPR3_TDQSCK_DEFVAL 
+#undef DDR_PHY_DTPR3_TDQSCK_SHIFT 
+#undef DDR_PHY_DTPR3_TDQSCK_MASK 
+#define DDR_PHY_DTPR3_TDQSCK_DEFVAL                                                0x02000804
+#define DDR_PHY_DTPR3_TDQSCK_SHIFT                                                 0
+#define DDR_PHY_DTPR3_TDQSCK_MASK                                                  0x00000007U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_31_30_MASK 
+#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL                                        0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT                                         30
+#define DDR_PHY_DTPR4_RESERVED_31_30_MASK                                          0xC0000000U
+
+/*ODT turn-on/turn-off delays (DDR2 only)*/
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK 
+#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL                                           0x01C02B10
+#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT                                            28
+#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK                                             0x30000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_27_26_MASK 
+#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL                                        0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT                                         26
+#define DDR_PHY_DTPR4_RESERVED_27_26_MASK                                          0x0C000000U
+
+/*Refresh-to-Refresh*/
+#undef DDR_PHY_DTPR4_TRFC_DEFVAL 
+#undef DDR_PHY_DTPR4_TRFC_SHIFT 
+#undef DDR_PHY_DTPR4_TRFC_MASK 
+#define DDR_PHY_DTPR4_TRFC_DEFVAL                                                  0x01C02B10
+#define DDR_PHY_DTPR4_TRFC_SHIFT                                                   16
+#define DDR_PHY_DTPR4_TRFC_MASK                                                    0x03FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_15_14_MASK 
+#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL                                        0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT                                         14
+#define DDR_PHY_DTPR4_RESERVED_15_14_MASK                                          0x0000C000U
+
+/*Write leveling output delay*/
+#undef DDR_PHY_DTPR4_TWLO_DEFVAL 
+#undef DDR_PHY_DTPR4_TWLO_SHIFT 
+#undef DDR_PHY_DTPR4_TWLO_MASK 
+#define DDR_PHY_DTPR4_TWLO_DEFVAL                                                  0x01C02B10
+#define DDR_PHY_DTPR4_TWLO_SHIFT                                                   8
+#define DDR_PHY_DTPR4_TWLO_MASK                                                    0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL                                          0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT                                           5
+#define DDR_PHY_DTPR4_RESERVED_7_5_MASK                                            0x000000E0U
+
+/*Power down exit delay*/
+#undef DDR_PHY_DTPR4_TXP_DEFVAL 
+#undef DDR_PHY_DTPR4_TXP_SHIFT 
+#undef DDR_PHY_DTPR4_TXP_MASK 
+#define DDR_PHY_DTPR4_TXP_DEFVAL                                                   0x01C02B10
+#define DDR_PHY_DTPR4_TXP_SHIFT                                                    0
+#define DDR_PHY_DTPR4_TXP_MASK                                                     0x0000001FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DTPR5_RESERVED_31_24_MASK 
+#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL                                        0x00872716
+#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT                                         24
+#define DDR_PHY_DTPR5_RESERVED_31_24_MASK                                          0xFF000000U
+
+/*Activate to activate command delay (same bank)*/
+#undef DDR_PHY_DTPR5_TRC_DEFVAL 
+#undef DDR_PHY_DTPR5_TRC_SHIFT 
+#undef DDR_PHY_DTPR5_TRC_MASK 
+#define DDR_PHY_DTPR5_TRC_DEFVAL                                                   0x00872716
+#define DDR_PHY_DTPR5_TRC_SHIFT                                                    16
+#define DDR_PHY_DTPR5_TRC_MASK                                                     0x00FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DTPR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DTPR5_RESERVED_15_MASK 
+#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL                                           0x00872716
+#define DDR_PHY_DTPR5_RESERVED_15_SHIFT                                            15
+#define DDR_PHY_DTPR5_RESERVED_15_MASK                                             0x00008000U
+
+/*Activate to read or write delay*/
+#undef DDR_PHY_DTPR5_TRCD_DEFVAL 
+#undef DDR_PHY_DTPR5_TRCD_SHIFT 
+#undef DDR_PHY_DTPR5_TRCD_MASK 
+#define DDR_PHY_DTPR5_TRCD_DEFVAL                                                  0x00872716
+#define DDR_PHY_DTPR5_TRCD_SHIFT                                                   8
+#define DDR_PHY_DTPR5_TRCD_MASK                                                    0x00007F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR5_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL                                          0x00872716
+#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT                                           5
+#define DDR_PHY_DTPR5_RESERVED_7_5_MASK                                            0x000000E0U
+
+/*Internal write to read command delay*/
+#undef DDR_PHY_DTPR5_TWTR_DEFVAL 
+#undef DDR_PHY_DTPR5_TWTR_SHIFT 
+#undef DDR_PHY_DTPR5_TWTR_MASK 
+#define DDR_PHY_DTPR5_TWTR_DEFVAL                                                  0x00872716
+#define DDR_PHY_DTPR5_TWTR_SHIFT                                                   0
+#define DDR_PHY_DTPR5_TWTR_MASK                                                    0x0000001FU
+
+/*PUB Write Latency Enable*/
+#undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBWLEN_SHIFT 
+#undef DDR_PHY_DTPR6_PUBWLEN_MASK 
+#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL                                               0x00000505
+#define DDR_PHY_DTPR6_PUBWLEN_SHIFT                                                31
+#define DDR_PHY_DTPR6_PUBWLEN_MASK                                                 0x80000000U
+
+/*PUB Read Latency Enable*/
+#undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBRLEN_SHIFT 
+#undef DDR_PHY_DTPR6_PUBRLEN_MASK 
+#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL                                               0x00000505
+#define DDR_PHY_DTPR6_PUBRLEN_SHIFT                                                30
+#define DDR_PHY_DTPR6_PUBRLEN_MASK                                                 0x40000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 
+#undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 
+#undef DDR_PHY_DTPR6_RESERVED_29_14_MASK 
+#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL                                        0x00000505
+#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT                                         14
+#define DDR_PHY_DTPR6_RESERVED_29_14_MASK                                          0x3FFFC000U
+
+/*Write Latency*/
+#undef DDR_PHY_DTPR6_PUBWL_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBWL_SHIFT 
+#undef DDR_PHY_DTPR6_PUBWL_MASK 
+#define DDR_PHY_DTPR6_PUBWL_DEFVAL                                                 0x00000505
+#define DDR_PHY_DTPR6_PUBWL_SHIFT                                                  8
+#define DDR_PHY_DTPR6_PUBWL_MASK                                                   0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DTPR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL                                          0x00000505
+#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT                                           6
+#define DDR_PHY_DTPR6_RESERVED_7_6_MASK                                            0x000000C0U
+
+/*Read Latency*/
+#undef DDR_PHY_DTPR6_PUBRL_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBRL_SHIFT 
+#undef DDR_PHY_DTPR6_PUBRL_MASK 
+#define DDR_PHY_DTPR6_PUBRL_DEFVAL                                                 0x00000505
+#define DDR_PHY_DTPR6_PUBRL_SHIFT                                                  0
+#define DDR_PHY_DTPR6_PUBRL_MASK                                                   0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL                                       0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT                                        31
+#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK                                         0x80000000U
+
+/*RDMIMM Quad CS Enable*/
+#undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_QCSEN_MASK 
+#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL                                             0x08400020
+#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT                                              30
+#define DDR_PHY_RDIMMGCR0_QCSEN_MASK                                               0x40000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL                                    0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT                                     28
+#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK                                      0x30000000U
+
+/*RDIMM Outputs I/O Mode*/
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 
+#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL                                          0x08400020
+#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT                                           27
+#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK                                            0x08000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL                                    0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT                                     24
+#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK                                      0x07000000U
+
+/*ERROUT# Output Enable*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL                                          0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT                                           23
+#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK                                            0x00800000U
+
+/*ERROUT# I/O Mode*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL                                         0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT                                          22
+#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK                                           0x00400000U
+
+/*ERROUT# Power Down Receiver*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL                                         0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT                                          21
+#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK                                           0x00200000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL                                       0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT                                        20
+#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK                                         0x00100000U
+
+/*ERROUT# On-Die Termination*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL                                         0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT                                          19
+#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK                                           0x00080000U
+
+/*Load Reduced DIMM*/
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK 
+#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL                                            0x08400020
+#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT                                             18
+#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK                                              0x00040000U
+
+/*PAR_IN I/O Mode*/
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK 
+#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL                                          0x08400020
+#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT                                           17
+#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK                                            0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL                                     0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT                                      8
+#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK                                       0x0001FF00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL                                     0x08400020
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT                                      6
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK                                       0x000000C0U
+
+/*Rank Mirror Enable.*/
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL                                          0x08400020
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT                                           4
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK                                            0x00000030U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL                                        0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT                                         3
+#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK                                          0x00000008U
+
+/*Stop on Parity Error*/
+#undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_SOPERR_MASK 
+#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL                                            0x08400020
+#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT                                             2
+#define DDR_PHY_RDIMMGCR0_SOPERR_MASK                                              0x00000004U
+
+/*Parity Error No Registering*/
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 
+#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL                                          0x08400020
+#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT                                           1
+#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK                                            0x00000002U
+
+/*Registered DIMM*/
+#undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RDIMM_MASK 
+#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL                                             0x08400020
+#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT                                              0
+#define DDR_PHY_RDIMMGCR0_RDIMM_MASK                                               0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL                                    0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT                                     29
+#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK                                      0xE0000000U
+
+/*Address [17] B-side Inversion Disable*/
+#undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_A17BID_MASK 
+#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL                                            0x00000C80
+#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT                                             28
+#define DDR_PHY_RDIMMGCR1_A17BID_MASK                                              0x10000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL                                       0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT                                        27
+#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK                                         0x08000000U
+
+/*Command word to command word programming delay*/
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL                                         0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT                                          24
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK                                           0x07000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL                                       0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT                                        23
+#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK                                         0x00800000U
+
+/*Command word to command word programming delay*/
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL                                          0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT                                           20
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK                                            0x00700000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL                                       0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT                                        19
+#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK                                         0x00080000U
+
+/*Command word to command word programming delay*/
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL                                            0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT                                             16
+#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK                                              0x00070000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL                                    0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT                                     14
+#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK                                      0x0000C000U
+
+/*Stabilization time*/
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL                                           0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT                                            0
+#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK                                             0x00003FFFU
+
+/*Control Word 15*/
+#undef DDR_PHY_RDIMMCR1_RC15_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC15_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC15_MASK 
+#define DDR_PHY_RDIMMCR1_RC15_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC15_SHIFT                                                28
+#define DDR_PHY_RDIMMCR1_RC15_MASK                                                 0xF0000000U
+
+/*DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved*/
+#undef DDR_PHY_RDIMMCR1_RC14_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC14_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC14_MASK 
+#define DDR_PHY_RDIMMCR1_RC14_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC14_SHIFT                                                24
+#define DDR_PHY_RDIMMCR1_RC14_MASK                                                 0x0F000000U
+
+/*DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved*/
+#undef DDR_PHY_RDIMMCR1_RC13_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC13_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC13_MASK 
+#define DDR_PHY_RDIMMCR1_RC13_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC13_SHIFT                                                20
+#define DDR_PHY_RDIMMCR1_RC13_MASK                                                 0x00F00000U
+
+/*DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved*/
+#undef DDR_PHY_RDIMMCR1_RC12_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC12_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC12_MASK 
+#define DDR_PHY_RDIMMCR1_RC12_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC12_SHIFT                                                16
+#define DDR_PHY_RDIMMCR1_RC12_MASK                                                 0x000F0000U
+
+/*DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
+		rol Word)*/
+#undef DDR_PHY_RDIMMCR1_RC11_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC11_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC11_MASK 
+#define DDR_PHY_RDIMMCR1_RC11_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC11_SHIFT                                                12
+#define DDR_PHY_RDIMMCR1_RC11_MASK                                                 0x0000F000U
+
+/*DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)*/
+#undef DDR_PHY_RDIMMCR1_RC10_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC10_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC10_MASK 
+#define DDR_PHY_RDIMMCR1_RC10_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC10_SHIFT                                                8
+#define DDR_PHY_RDIMMCR1_RC10_MASK                                                 0x00000F00U
+
+/*DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)*/
+#undef DDR_PHY_RDIMMCR1_RC9_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC9_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC9_MASK 
+#define DDR_PHY_RDIMMCR1_RC9_DEFVAL                                                0x00000000
+#define DDR_PHY_RDIMMCR1_RC9_SHIFT                                                 4
+#define DDR_PHY_RDIMMCR1_RC9_MASK                                                  0x000000F0U
+
+/*DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
+		Control Word)*/
+#undef DDR_PHY_RDIMMCR1_RC8_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC8_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC8_MASK 
+#define DDR_PHY_RDIMMCR1_RC8_DEFVAL                                                0x00000000
+#define DDR_PHY_RDIMMCR1_RC8_SHIFT                                                 0
+#define DDR_PHY_RDIMMCR1_RC8_MASK                                                  0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR0_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR0_RESERVED_31_8_MASK 
+#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL                                           0x00000052
+#define DDR_PHY_MR0_RESERVED_31_8_SHIFT                                            8
+#define DDR_PHY_MR0_RESERVED_31_8_MASK                                             0xFFFFFF00U
+
+/*CA Terminating Rank*/
+#undef DDR_PHY_MR0_CATR_DEFVAL 
+#undef DDR_PHY_MR0_CATR_SHIFT 
+#undef DDR_PHY_MR0_CATR_MASK 
+#define DDR_PHY_MR0_CATR_DEFVAL                                                    0x00000052
+#define DDR_PHY_MR0_CATR_SHIFT                                                     7
+#define DDR_PHY_MR0_CATR_MASK                                                      0x00000080U
+
+/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR0_RSVD_6_5_DEFVAL 
+#undef DDR_PHY_MR0_RSVD_6_5_SHIFT 
+#undef DDR_PHY_MR0_RSVD_6_5_MASK 
+#define DDR_PHY_MR0_RSVD_6_5_DEFVAL                                                0x00000052
+#define DDR_PHY_MR0_RSVD_6_5_SHIFT                                                 5
+#define DDR_PHY_MR0_RSVD_6_5_MASK                                                  0x00000060U
+
+/*Built-in Self-Test for RZQ*/
+#undef DDR_PHY_MR0_RZQI_DEFVAL 
+#undef DDR_PHY_MR0_RZQI_SHIFT 
+#undef DDR_PHY_MR0_RZQI_MASK 
+#define DDR_PHY_MR0_RZQI_DEFVAL                                                    0x00000052
+#define DDR_PHY_MR0_RZQI_SHIFT                                                     3
+#define DDR_PHY_MR0_RZQI_MASK                                                      0x00000018U
+
+/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR0_RSVD_2_0_DEFVAL 
+#undef DDR_PHY_MR0_RSVD_2_0_SHIFT 
+#undef DDR_PHY_MR0_RSVD_2_0_MASK 
+#define DDR_PHY_MR0_RSVD_2_0_DEFVAL                                                0x00000052
+#define DDR_PHY_MR0_RSVD_2_0_SHIFT                                                 0
+#define DDR_PHY_MR0_RSVD_2_0_MASK                                                  0x00000007U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR1_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR1_RESERVED_31_8_MASK 
+#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL                                           0x00000004
+#define DDR_PHY_MR1_RESERVED_31_8_SHIFT                                            8
+#define DDR_PHY_MR1_RESERVED_31_8_MASK                                             0xFFFFFF00U
+
+/*Read Postamble Length*/
+#undef DDR_PHY_MR1_RDPST_DEFVAL 
+#undef DDR_PHY_MR1_RDPST_SHIFT 
+#undef DDR_PHY_MR1_RDPST_MASK 
+#define DDR_PHY_MR1_RDPST_DEFVAL                                                   0x00000004
+#define DDR_PHY_MR1_RDPST_SHIFT                                                    7
+#define DDR_PHY_MR1_RDPST_MASK                                                     0x00000080U
+
+/*Write-recovery for auto-precharge command*/
+#undef DDR_PHY_MR1_NWR_DEFVAL 
+#undef DDR_PHY_MR1_NWR_SHIFT 
+#undef DDR_PHY_MR1_NWR_MASK 
+#define DDR_PHY_MR1_NWR_DEFVAL                                                     0x00000004
+#define DDR_PHY_MR1_NWR_SHIFT                                                      4
+#define DDR_PHY_MR1_NWR_MASK                                                       0x00000070U
+
+/*Read Preamble Length*/
+#undef DDR_PHY_MR1_RDPRE_DEFVAL 
+#undef DDR_PHY_MR1_RDPRE_SHIFT 
+#undef DDR_PHY_MR1_RDPRE_MASK 
+#define DDR_PHY_MR1_RDPRE_DEFVAL                                                   0x00000004
+#define DDR_PHY_MR1_RDPRE_SHIFT                                                    3
+#define DDR_PHY_MR1_RDPRE_MASK                                                     0x00000008U
+
+/*Write Preamble Length*/
+#undef DDR_PHY_MR1_WRPRE_DEFVAL 
+#undef DDR_PHY_MR1_WRPRE_SHIFT 
+#undef DDR_PHY_MR1_WRPRE_MASK 
+#define DDR_PHY_MR1_WRPRE_DEFVAL                                                   0x00000004
+#define DDR_PHY_MR1_WRPRE_SHIFT                                                    2
+#define DDR_PHY_MR1_WRPRE_MASK                                                     0x00000004U
+
+/*Burst Length*/
+#undef DDR_PHY_MR1_BL_DEFVAL 
+#undef DDR_PHY_MR1_BL_SHIFT 
+#undef DDR_PHY_MR1_BL_MASK 
+#define DDR_PHY_MR1_BL_DEFVAL                                                      0x00000004
+#define DDR_PHY_MR1_BL_SHIFT                                                       0
+#define DDR_PHY_MR1_BL_MASK                                                        0x00000003U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR2_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR2_RESERVED_31_8_MASK 
+#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL                                           0x00000000
+#define DDR_PHY_MR2_RESERVED_31_8_SHIFT                                            8
+#define DDR_PHY_MR2_RESERVED_31_8_MASK                                             0xFFFFFF00U
+
+/*Write Leveling*/
+#undef DDR_PHY_MR2_WRL_DEFVAL 
+#undef DDR_PHY_MR2_WRL_SHIFT 
+#undef DDR_PHY_MR2_WRL_MASK 
+#define DDR_PHY_MR2_WRL_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR2_WRL_SHIFT                                                      7
+#define DDR_PHY_MR2_WRL_MASK                                                       0x00000080U
+
+/*Write Latency Set*/
+#undef DDR_PHY_MR2_WLS_DEFVAL 
+#undef DDR_PHY_MR2_WLS_SHIFT 
+#undef DDR_PHY_MR2_WLS_MASK 
+#define DDR_PHY_MR2_WLS_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR2_WLS_SHIFT                                                      6
+#define DDR_PHY_MR2_WLS_MASK                                                       0x00000040U
+
+/*Write Latency*/
+#undef DDR_PHY_MR2_WL_DEFVAL 
+#undef DDR_PHY_MR2_WL_SHIFT 
+#undef DDR_PHY_MR2_WL_MASK 
+#define DDR_PHY_MR2_WL_DEFVAL                                                      0x00000000
+#define DDR_PHY_MR2_WL_SHIFT                                                       3
+#define DDR_PHY_MR2_WL_MASK                                                        0x00000038U
+
+/*Read Latency*/
+#undef DDR_PHY_MR2_RL_DEFVAL 
+#undef DDR_PHY_MR2_RL_SHIFT 
+#undef DDR_PHY_MR2_RL_MASK 
+#define DDR_PHY_MR2_RL_DEFVAL                                                      0x00000000
+#define DDR_PHY_MR2_RL_SHIFT                                                       0
+#define DDR_PHY_MR2_RL_MASK                                                        0x00000007U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR3_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR3_RESERVED_31_8_MASK 
+#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL                                           0x00000031
+#define DDR_PHY_MR3_RESERVED_31_8_SHIFT                                            8
+#define DDR_PHY_MR3_RESERVED_31_8_MASK                                             0xFFFFFF00U
+
+/*DBI-Write Enable*/
+#undef DDR_PHY_MR3_DBIWR_DEFVAL 
+#undef DDR_PHY_MR3_DBIWR_SHIFT 
+#undef DDR_PHY_MR3_DBIWR_MASK 
+#define DDR_PHY_MR3_DBIWR_DEFVAL                                                   0x00000031
+#define DDR_PHY_MR3_DBIWR_SHIFT                                                    7
+#define DDR_PHY_MR3_DBIWR_MASK                                                     0x00000080U
+
+/*DBI-Read Enable*/
+#undef DDR_PHY_MR3_DBIRD_DEFVAL 
+#undef DDR_PHY_MR3_DBIRD_SHIFT 
+#undef DDR_PHY_MR3_DBIRD_MASK 
+#define DDR_PHY_MR3_DBIRD_DEFVAL                                                   0x00000031
+#define DDR_PHY_MR3_DBIRD_SHIFT                                                    6
+#define DDR_PHY_MR3_DBIRD_MASK                                                     0x00000040U
+
+/*Pull-down Drive Strength*/
+#undef DDR_PHY_MR3_PDDS_DEFVAL 
+#undef DDR_PHY_MR3_PDDS_SHIFT 
+#undef DDR_PHY_MR3_PDDS_MASK 
+#define DDR_PHY_MR3_PDDS_DEFVAL                                                    0x00000031
+#define DDR_PHY_MR3_PDDS_SHIFT                                                     3
+#define DDR_PHY_MR3_PDDS_MASK                                                      0x00000038U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR3_RSVD_DEFVAL 
+#undef DDR_PHY_MR3_RSVD_SHIFT 
+#undef DDR_PHY_MR3_RSVD_MASK 
+#define DDR_PHY_MR3_RSVD_DEFVAL                                                    0x00000031
+#define DDR_PHY_MR3_RSVD_SHIFT                                                     2
+#define DDR_PHY_MR3_RSVD_MASK                                                      0x00000004U
+
+/*Write Postamble Length*/
+#undef DDR_PHY_MR3_WRPST_DEFVAL 
+#undef DDR_PHY_MR3_WRPST_SHIFT 
+#undef DDR_PHY_MR3_WRPST_MASK 
+#define DDR_PHY_MR3_WRPST_DEFVAL                                                   0x00000031
+#define DDR_PHY_MR3_WRPST_SHIFT                                                    1
+#define DDR_PHY_MR3_WRPST_MASK                                                     0x00000002U
+
+/*Pull-up Calibration Point*/
+#undef DDR_PHY_MR3_PUCAL_DEFVAL 
+#undef DDR_PHY_MR3_PUCAL_SHIFT 
+#undef DDR_PHY_MR3_PUCAL_MASK 
+#define DDR_PHY_MR3_PUCAL_DEFVAL                                                   0x00000031
+#define DDR_PHY_MR3_PUCAL_SHIFT                                                    0
+#define DDR_PHY_MR3_PUCAL_MASK                                                     0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_MR4_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_MR4_RESERVED_31_16_MASK 
+#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL                                          0x00000000
+#define DDR_PHY_MR4_RESERVED_31_16_SHIFT                                           16
+#define DDR_PHY_MR4_RESERVED_31_16_MASK                                            0xFFFF0000U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR4_RSVD_15_13_DEFVAL 
+#undef DDR_PHY_MR4_RSVD_15_13_SHIFT 
+#undef DDR_PHY_MR4_RSVD_15_13_MASK 
+#define DDR_PHY_MR4_RSVD_15_13_DEFVAL                                              0x00000000
+#define DDR_PHY_MR4_RSVD_15_13_SHIFT                                               13
+#define DDR_PHY_MR4_RSVD_15_13_MASK                                                0x0000E000U
+
+/*Write Preamble*/
+#undef DDR_PHY_MR4_WRP_DEFVAL 
+#undef DDR_PHY_MR4_WRP_SHIFT 
+#undef DDR_PHY_MR4_WRP_MASK 
+#define DDR_PHY_MR4_WRP_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR4_WRP_SHIFT                                                      12
+#define DDR_PHY_MR4_WRP_MASK                                                       0x00001000U
+
+/*Read Preamble*/
+#undef DDR_PHY_MR4_RDP_DEFVAL 
+#undef DDR_PHY_MR4_RDP_SHIFT 
+#undef DDR_PHY_MR4_RDP_MASK 
+#define DDR_PHY_MR4_RDP_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR4_RDP_SHIFT                                                      11
+#define DDR_PHY_MR4_RDP_MASK                                                       0x00000800U
+
+/*Read Preamble Training Mode*/
+#undef DDR_PHY_MR4_RPTM_DEFVAL 
+#undef DDR_PHY_MR4_RPTM_SHIFT 
+#undef DDR_PHY_MR4_RPTM_MASK 
+#define DDR_PHY_MR4_RPTM_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR4_RPTM_SHIFT                                                     10
+#define DDR_PHY_MR4_RPTM_MASK                                                      0x00000400U
+
+/*Self Refresh Abort*/
+#undef DDR_PHY_MR4_SRA_DEFVAL 
+#undef DDR_PHY_MR4_SRA_SHIFT 
+#undef DDR_PHY_MR4_SRA_MASK 
+#define DDR_PHY_MR4_SRA_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR4_SRA_SHIFT                                                      9
+#define DDR_PHY_MR4_SRA_MASK                                                       0x00000200U
+
+/*CS to Command Latency Mode*/
+#undef DDR_PHY_MR4_CS2CMDL_DEFVAL 
+#undef DDR_PHY_MR4_CS2CMDL_SHIFT 
+#undef DDR_PHY_MR4_CS2CMDL_MASK 
+#define DDR_PHY_MR4_CS2CMDL_DEFVAL                                                 0x00000000
+#define DDR_PHY_MR4_CS2CMDL_SHIFT                                                  6
+#define DDR_PHY_MR4_CS2CMDL_MASK                                                   0x000001C0U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR4_RSVD1_DEFVAL 
+#undef DDR_PHY_MR4_RSVD1_SHIFT 
+#undef DDR_PHY_MR4_RSVD1_MASK 
+#define DDR_PHY_MR4_RSVD1_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR4_RSVD1_SHIFT                                                    5
+#define DDR_PHY_MR4_RSVD1_MASK                                                     0x00000020U
+
+/*Internal VREF Monitor*/
+#undef DDR_PHY_MR4_IVM_DEFVAL 
+#undef DDR_PHY_MR4_IVM_SHIFT 
+#undef DDR_PHY_MR4_IVM_MASK 
+#define DDR_PHY_MR4_IVM_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR4_IVM_SHIFT                                                      4
+#define DDR_PHY_MR4_IVM_MASK                                                       0x00000010U
+
+/*Temperature Controlled Refresh Mode*/
+#undef DDR_PHY_MR4_TCRM_DEFVAL 
+#undef DDR_PHY_MR4_TCRM_SHIFT 
+#undef DDR_PHY_MR4_TCRM_MASK 
+#define DDR_PHY_MR4_TCRM_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR4_TCRM_SHIFT                                                     3
+#define DDR_PHY_MR4_TCRM_MASK                                                      0x00000008U
+
+/*Temperature Controlled Refresh Range*/
+#undef DDR_PHY_MR4_TCRR_DEFVAL 
+#undef DDR_PHY_MR4_TCRR_SHIFT 
+#undef DDR_PHY_MR4_TCRR_MASK 
+#define DDR_PHY_MR4_TCRR_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR4_TCRR_SHIFT                                                     2
+#define DDR_PHY_MR4_TCRR_MASK                                                      0x00000004U
+
+/*Maximum Power Down Mode*/
+#undef DDR_PHY_MR4_MPDM_DEFVAL 
+#undef DDR_PHY_MR4_MPDM_SHIFT 
+#undef DDR_PHY_MR4_MPDM_MASK 
+#define DDR_PHY_MR4_MPDM_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR4_MPDM_SHIFT                                                     1
+#define DDR_PHY_MR4_MPDM_MASK                                                      0x00000002U
+
+/*This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR4_RSVD_0_DEFVAL 
+#undef DDR_PHY_MR4_RSVD_0_SHIFT 
+#undef DDR_PHY_MR4_RSVD_0_MASK 
+#define DDR_PHY_MR4_RSVD_0_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR4_RSVD_0_SHIFT                                                   0
+#define DDR_PHY_MR4_RSVD_0_MASK                                                    0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_MR5_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_MR5_RESERVED_31_16_MASK 
+#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL                                          0x00000000
+#define DDR_PHY_MR5_RESERVED_31_16_SHIFT                                           16
+#define DDR_PHY_MR5_RESERVED_31_16_MASK                                            0xFFFF0000U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR5_RSVD_DEFVAL 
+#undef DDR_PHY_MR5_RSVD_SHIFT 
+#undef DDR_PHY_MR5_RSVD_MASK 
+#define DDR_PHY_MR5_RSVD_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR5_RSVD_SHIFT                                                     13
+#define DDR_PHY_MR5_RSVD_MASK                                                      0x0000E000U
+
+/*Read DBI*/
+#undef DDR_PHY_MR5_RDBI_DEFVAL 
+#undef DDR_PHY_MR5_RDBI_SHIFT 
+#undef DDR_PHY_MR5_RDBI_MASK 
+#define DDR_PHY_MR5_RDBI_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR5_RDBI_SHIFT                                                     12
+#define DDR_PHY_MR5_RDBI_MASK                                                      0x00001000U
+
+/*Write DBI*/
+#undef DDR_PHY_MR5_WDBI_DEFVAL 
+#undef DDR_PHY_MR5_WDBI_SHIFT 
+#undef DDR_PHY_MR5_WDBI_MASK 
+#define DDR_PHY_MR5_WDBI_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR5_WDBI_SHIFT                                                     11
+#define DDR_PHY_MR5_WDBI_MASK                                                      0x00000800U
+
+/*Data Mask*/
+#undef DDR_PHY_MR5_DM_DEFVAL 
+#undef DDR_PHY_MR5_DM_SHIFT 
+#undef DDR_PHY_MR5_DM_MASK 
+#define DDR_PHY_MR5_DM_DEFVAL                                                      0x00000000
+#define DDR_PHY_MR5_DM_SHIFT                                                       10
+#define DDR_PHY_MR5_DM_MASK                                                        0x00000400U
+
+/*CA Parity Persistent Error*/
+#undef DDR_PHY_MR5_CAPPE_DEFVAL 
+#undef DDR_PHY_MR5_CAPPE_SHIFT 
+#undef DDR_PHY_MR5_CAPPE_MASK 
+#define DDR_PHY_MR5_CAPPE_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR5_CAPPE_SHIFT                                                    9
+#define DDR_PHY_MR5_CAPPE_MASK                                                     0x00000200U
+
+/*RTT_PARK*/
+#undef DDR_PHY_MR5_RTTPARK_DEFVAL 
+#undef DDR_PHY_MR5_RTTPARK_SHIFT 
+#undef DDR_PHY_MR5_RTTPARK_MASK 
+#define DDR_PHY_MR5_RTTPARK_DEFVAL                                                 0x00000000
+#define DDR_PHY_MR5_RTTPARK_SHIFT                                                  6
+#define DDR_PHY_MR5_RTTPARK_MASK                                                   0x000001C0U
+
+/*ODT Input Buffer during Power Down mode*/
+#undef DDR_PHY_MR5_ODTIBPD_DEFVAL 
+#undef DDR_PHY_MR5_ODTIBPD_SHIFT 
+#undef DDR_PHY_MR5_ODTIBPD_MASK 
+#define DDR_PHY_MR5_ODTIBPD_DEFVAL                                                 0x00000000
+#define DDR_PHY_MR5_ODTIBPD_SHIFT                                                  5
+#define DDR_PHY_MR5_ODTIBPD_MASK                                                   0x00000020U
+
+/*C/A Parity Error Status*/
+#undef DDR_PHY_MR5_CAPES_DEFVAL 
+#undef DDR_PHY_MR5_CAPES_SHIFT 
+#undef DDR_PHY_MR5_CAPES_MASK 
+#define DDR_PHY_MR5_CAPES_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR5_CAPES_SHIFT                                                    4
+#define DDR_PHY_MR5_CAPES_MASK                                                     0x00000010U
+
+/*CRC Error Clear*/
+#undef DDR_PHY_MR5_CRCEC_DEFVAL 
+#undef DDR_PHY_MR5_CRCEC_SHIFT 
+#undef DDR_PHY_MR5_CRCEC_MASK 
+#define DDR_PHY_MR5_CRCEC_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR5_CRCEC_SHIFT                                                    3
+#define DDR_PHY_MR5_CRCEC_MASK                                                     0x00000008U
+
+/*C/A Parity Latency Mode*/
+#undef DDR_PHY_MR5_CAPM_DEFVAL 
+#undef DDR_PHY_MR5_CAPM_SHIFT 
+#undef DDR_PHY_MR5_CAPM_MASK 
+#define DDR_PHY_MR5_CAPM_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR5_CAPM_SHIFT                                                     0
+#define DDR_PHY_MR5_CAPM_MASK                                                      0x00000007U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_MR6_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_MR6_RESERVED_31_16_MASK 
+#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL                                          0x00000000
+#define DDR_PHY_MR6_RESERVED_31_16_SHIFT                                           16
+#define DDR_PHY_MR6_RESERVED_31_16_MASK                                            0xFFFF0000U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR6_RSVD_15_13_DEFVAL 
+#undef DDR_PHY_MR6_RSVD_15_13_SHIFT 
+#undef DDR_PHY_MR6_RSVD_15_13_MASK 
+#define DDR_PHY_MR6_RSVD_15_13_DEFVAL                                              0x00000000
+#define DDR_PHY_MR6_RSVD_15_13_SHIFT                                               13
+#define DDR_PHY_MR6_RSVD_15_13_MASK                                                0x0000E000U
+
+/*CAS_n to CAS_n command delay for same bank group (tCCD_L)*/
+#undef DDR_PHY_MR6_TCCDL_DEFVAL 
+#undef DDR_PHY_MR6_TCCDL_SHIFT 
+#undef DDR_PHY_MR6_TCCDL_MASK 
+#define DDR_PHY_MR6_TCCDL_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR6_TCCDL_SHIFT                                                    10
+#define DDR_PHY_MR6_TCCDL_MASK                                                     0x00001C00U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR6_RSVD_9_8_DEFVAL 
+#undef DDR_PHY_MR6_RSVD_9_8_SHIFT 
+#undef DDR_PHY_MR6_RSVD_9_8_MASK 
+#define DDR_PHY_MR6_RSVD_9_8_DEFVAL                                                0x00000000
+#define DDR_PHY_MR6_RSVD_9_8_SHIFT                                                 8
+#define DDR_PHY_MR6_RSVD_9_8_MASK                                                  0x00000300U
+
+/*VrefDQ Training Enable*/
+#undef DDR_PHY_MR6_VDDQTEN_DEFVAL 
+#undef DDR_PHY_MR6_VDDQTEN_SHIFT 
+#undef DDR_PHY_MR6_VDDQTEN_MASK 
+#define DDR_PHY_MR6_VDDQTEN_DEFVAL                                                 0x00000000
+#define DDR_PHY_MR6_VDDQTEN_SHIFT                                                  7
+#define DDR_PHY_MR6_VDDQTEN_MASK                                                   0x00000080U
+
+/*VrefDQ Training Range*/
+#undef DDR_PHY_MR6_VDQTRG_DEFVAL 
+#undef DDR_PHY_MR6_VDQTRG_SHIFT 
+#undef DDR_PHY_MR6_VDQTRG_MASK 
+#define DDR_PHY_MR6_VDQTRG_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR6_VDQTRG_SHIFT                                                   6
+#define DDR_PHY_MR6_VDQTRG_MASK                                                    0x00000040U
+
+/*VrefDQ Training Values*/
+#undef DDR_PHY_MR6_VDQTVAL_DEFVAL 
+#undef DDR_PHY_MR6_VDQTVAL_SHIFT 
+#undef DDR_PHY_MR6_VDQTVAL_MASK 
+#define DDR_PHY_MR6_VDQTVAL_DEFVAL                                                 0x00000000
+#define DDR_PHY_MR6_VDQTVAL_SHIFT                                                  0
+#define DDR_PHY_MR6_VDQTVAL_MASK                                                   0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR11_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR11_RESERVED_31_8_MASK 
+#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL                                          0x00000000
+#define DDR_PHY_MR11_RESERVED_31_8_SHIFT                                           8
+#define DDR_PHY_MR11_RESERVED_31_8_MASK                                            0xFFFFFF00U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR11_RSVD_DEFVAL 
+#undef DDR_PHY_MR11_RSVD_SHIFT 
+#undef DDR_PHY_MR11_RSVD_MASK 
+#define DDR_PHY_MR11_RSVD_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR11_RSVD_SHIFT                                                    3
+#define DDR_PHY_MR11_RSVD_MASK                                                     0x000000F8U
+
+/*Power Down Control*/
+#undef DDR_PHY_MR11_PDCTL_DEFVAL 
+#undef DDR_PHY_MR11_PDCTL_SHIFT 
+#undef DDR_PHY_MR11_PDCTL_MASK 
+#define DDR_PHY_MR11_PDCTL_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR11_PDCTL_SHIFT                                                   2
+#define DDR_PHY_MR11_PDCTL_MASK                                                    0x00000004U
+
+/*DQ Bus Receiver On-Die-Termination*/
+#undef DDR_PHY_MR11_DQODT_DEFVAL 
+#undef DDR_PHY_MR11_DQODT_SHIFT 
+#undef DDR_PHY_MR11_DQODT_MASK 
+#define DDR_PHY_MR11_DQODT_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR11_DQODT_SHIFT                                                   0
+#define DDR_PHY_MR11_DQODT_MASK                                                    0x00000003U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR12_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR12_RESERVED_31_8_MASK 
+#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL                                          0x0000004D
+#define DDR_PHY_MR12_RESERVED_31_8_SHIFT                                           8
+#define DDR_PHY_MR12_RESERVED_31_8_MASK                                            0xFFFFFF00U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR12_RSVD_DEFVAL 
+#undef DDR_PHY_MR12_RSVD_SHIFT 
+#undef DDR_PHY_MR12_RSVD_MASK 
+#define DDR_PHY_MR12_RSVD_DEFVAL                                                   0x0000004D
+#define DDR_PHY_MR12_RSVD_SHIFT                                                    7
+#define DDR_PHY_MR12_RSVD_MASK                                                     0x00000080U
+
+/*VREF_CA Range Select.*/
+#undef DDR_PHY_MR12_VR_CA_DEFVAL 
+#undef DDR_PHY_MR12_VR_CA_SHIFT 
+#undef DDR_PHY_MR12_VR_CA_MASK 
+#define DDR_PHY_MR12_VR_CA_DEFVAL                                                  0x0000004D
+#define DDR_PHY_MR12_VR_CA_SHIFT                                                   6
+#define DDR_PHY_MR12_VR_CA_MASK                                                    0x00000040U
+
+/*Controls the VREF(ca) levels for Frequency-Set-Point[1:0].*/
+#undef DDR_PHY_MR12_VREF_CA_DEFVAL 
+#undef DDR_PHY_MR12_VREF_CA_SHIFT 
+#undef DDR_PHY_MR12_VREF_CA_MASK 
+#define DDR_PHY_MR12_VREF_CA_DEFVAL                                                0x0000004D
+#define DDR_PHY_MR12_VREF_CA_SHIFT                                                 0
+#define DDR_PHY_MR12_VREF_CA_MASK                                                  0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR13_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR13_RESERVED_31_8_MASK 
+#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL                                          0x00000000
+#define DDR_PHY_MR13_RESERVED_31_8_SHIFT                                           8
+#define DDR_PHY_MR13_RESERVED_31_8_MASK                                            0xFFFFFF00U
+
+/*Frequency Set Point Operation Mode*/
+#undef DDR_PHY_MR13_FSPOP_DEFVAL 
+#undef DDR_PHY_MR13_FSPOP_SHIFT 
+#undef DDR_PHY_MR13_FSPOP_MASK 
+#define DDR_PHY_MR13_FSPOP_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR13_FSPOP_SHIFT                                                   7
+#define DDR_PHY_MR13_FSPOP_MASK                                                    0x00000080U
+
+/*Frequency Set Point Write Enable*/
+#undef DDR_PHY_MR13_FSPWR_DEFVAL 
+#undef DDR_PHY_MR13_FSPWR_SHIFT 
+#undef DDR_PHY_MR13_FSPWR_MASK 
+#define DDR_PHY_MR13_FSPWR_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR13_FSPWR_SHIFT                                                   6
+#define DDR_PHY_MR13_FSPWR_MASK                                                    0x00000040U
+
+/*Data Mask Enable*/
+#undef DDR_PHY_MR13_DMD_DEFVAL 
+#undef DDR_PHY_MR13_DMD_SHIFT 
+#undef DDR_PHY_MR13_DMD_MASK 
+#define DDR_PHY_MR13_DMD_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR13_DMD_SHIFT                                                     5
+#define DDR_PHY_MR13_DMD_MASK                                                      0x00000020U
+
+/*Refresh Rate Option*/
+#undef DDR_PHY_MR13_RRO_DEFVAL 
+#undef DDR_PHY_MR13_RRO_SHIFT 
+#undef DDR_PHY_MR13_RRO_MASK 
+#define DDR_PHY_MR13_RRO_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR13_RRO_SHIFT                                                     4
+#define DDR_PHY_MR13_RRO_MASK                                                      0x00000010U
+
+/*VREF Current Generator*/
+#undef DDR_PHY_MR13_VRCG_DEFVAL 
+#undef DDR_PHY_MR13_VRCG_SHIFT 
+#undef DDR_PHY_MR13_VRCG_MASK 
+#define DDR_PHY_MR13_VRCG_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR13_VRCG_SHIFT                                                    3
+#define DDR_PHY_MR13_VRCG_MASK                                                     0x00000008U
+
+/*VREF Output*/
+#undef DDR_PHY_MR13_VRO_DEFVAL 
+#undef DDR_PHY_MR13_VRO_SHIFT 
+#undef DDR_PHY_MR13_VRO_MASK 
+#define DDR_PHY_MR13_VRO_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR13_VRO_SHIFT                                                     2
+#define DDR_PHY_MR13_VRO_MASK                                                      0x00000004U
+
+/*Read Preamble Training Mode*/
+#undef DDR_PHY_MR13_RPT_DEFVAL 
+#undef DDR_PHY_MR13_RPT_SHIFT 
+#undef DDR_PHY_MR13_RPT_MASK 
+#define DDR_PHY_MR13_RPT_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR13_RPT_SHIFT                                                     1
+#define DDR_PHY_MR13_RPT_MASK                                                      0x00000002U
+
+/*Command Bus Training*/
+#undef DDR_PHY_MR13_CBT_DEFVAL 
+#undef DDR_PHY_MR13_CBT_SHIFT 
+#undef DDR_PHY_MR13_CBT_MASK 
+#define DDR_PHY_MR13_CBT_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR13_CBT_SHIFT                                                     0
+#define DDR_PHY_MR13_CBT_MASK                                                      0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR14_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR14_RESERVED_31_8_MASK 
+#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL                                          0x0000004D
+#define DDR_PHY_MR14_RESERVED_31_8_SHIFT                                           8
+#define DDR_PHY_MR14_RESERVED_31_8_MASK                                            0xFFFFFF00U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR14_RSVD_DEFVAL 
+#undef DDR_PHY_MR14_RSVD_SHIFT 
+#undef DDR_PHY_MR14_RSVD_MASK 
+#define DDR_PHY_MR14_RSVD_DEFVAL                                                   0x0000004D
+#define DDR_PHY_MR14_RSVD_SHIFT                                                    7
+#define DDR_PHY_MR14_RSVD_MASK                                                     0x00000080U
+
+/*VREFDQ Range Selects.*/
+#undef DDR_PHY_MR14_VR_DQ_DEFVAL 
+#undef DDR_PHY_MR14_VR_DQ_SHIFT 
+#undef DDR_PHY_MR14_VR_DQ_MASK 
+#define DDR_PHY_MR14_VR_DQ_DEFVAL                                                  0x0000004D
+#define DDR_PHY_MR14_VR_DQ_SHIFT                                                   6
+#define DDR_PHY_MR14_VR_DQ_MASK                                                    0x00000040U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR14_VREF_DQ_DEFVAL 
+#undef DDR_PHY_MR14_VREF_DQ_SHIFT 
+#undef DDR_PHY_MR14_VREF_DQ_MASK 
+#define DDR_PHY_MR14_VREF_DQ_DEFVAL                                                0x0000004D
+#define DDR_PHY_MR14_VREF_DQ_SHIFT                                                 0
+#define DDR_PHY_MR14_VREF_DQ_MASK                                                  0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR22_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR22_RESERVED_31_8_MASK 
+#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL                                          0x00000000
+#define DDR_PHY_MR22_RESERVED_31_8_SHIFT                                           8
+#define DDR_PHY_MR22_RESERVED_31_8_MASK                                            0xFFFFFF00U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR22_RSVD_DEFVAL 
+#undef DDR_PHY_MR22_RSVD_SHIFT 
+#undef DDR_PHY_MR22_RSVD_MASK 
+#define DDR_PHY_MR22_RSVD_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR22_RSVD_SHIFT                                                    6
+#define DDR_PHY_MR22_RSVD_MASK                                                     0x000000C0U
+
+/*CA ODT termination disable.*/
+#undef DDR_PHY_MR22_ODTD_CA_DEFVAL 
+#undef DDR_PHY_MR22_ODTD_CA_SHIFT 
+#undef DDR_PHY_MR22_ODTD_CA_MASK 
+#define DDR_PHY_MR22_ODTD_CA_DEFVAL                                                0x00000000
+#define DDR_PHY_MR22_ODTD_CA_SHIFT                                                 5
+#define DDR_PHY_MR22_ODTD_CA_MASK                                                  0x00000020U
+
+/*ODT CS override.*/
+#undef DDR_PHY_MR22_ODTE_CS_DEFVAL 
+#undef DDR_PHY_MR22_ODTE_CS_SHIFT 
+#undef DDR_PHY_MR22_ODTE_CS_MASK 
+#define DDR_PHY_MR22_ODTE_CS_DEFVAL                                                0x00000000
+#define DDR_PHY_MR22_ODTE_CS_SHIFT                                                 4
+#define DDR_PHY_MR22_ODTE_CS_MASK                                                  0x00000010U
+
+/*ODT CK override.*/
+#undef DDR_PHY_MR22_ODTE_CK_DEFVAL 
+#undef DDR_PHY_MR22_ODTE_CK_SHIFT 
+#undef DDR_PHY_MR22_ODTE_CK_MASK 
+#define DDR_PHY_MR22_ODTE_CK_DEFVAL                                                0x00000000
+#define DDR_PHY_MR22_ODTE_CK_SHIFT                                                 3
+#define DDR_PHY_MR22_ODTE_CK_MASK                                                  0x00000008U
+
+/*Controller ODT value for VOH calibration.*/
+#undef DDR_PHY_MR22_CODT_DEFVAL 
+#undef DDR_PHY_MR22_CODT_SHIFT 
+#undef DDR_PHY_MR22_CODT_MASK 
+#define DDR_PHY_MR22_CODT_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR22_CODT_SHIFT                                                    0
+#define DDR_PHY_MR22_CODT_MASK                                                     0x00000007U
+
+/*Refresh During Training*/
+#undef DDR_PHY_DTCR0_RFSHDT_DEFVAL 
+#undef DDR_PHY_DTCR0_RFSHDT_SHIFT 
+#undef DDR_PHY_DTCR0_RFSHDT_MASK 
+#define DDR_PHY_DTCR0_RFSHDT_DEFVAL                                                0x800091C7
+#define DDR_PHY_DTCR0_RFSHDT_SHIFT                                                 28
+#define DDR_PHY_DTCR0_RFSHDT_MASK                                                  0xF0000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 
+#undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 
+#undef DDR_PHY_DTCR0_RESERVED_27_26_MASK 
+#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL                                        0x800091C7
+#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT                                         26
+#define DDR_PHY_DTCR0_RESERVED_27_26_MASK                                          0x0C000000U
+
+/*Data Training Debug Rank Select*/
+#undef DDR_PHY_DTCR0_DTDRS_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDRS_SHIFT 
+#undef DDR_PHY_DTCR0_DTDRS_MASK 
+#define DDR_PHY_DTCR0_DTDRS_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTDRS_SHIFT                                                  24
+#define DDR_PHY_DTCR0_DTDRS_MASK                                                   0x03000000U
+
+/*Data Training with Early/Extended Gate*/
+#undef DDR_PHY_DTCR0_DTEXG_DEFVAL 
+#undef DDR_PHY_DTCR0_DTEXG_SHIFT 
+#undef DDR_PHY_DTCR0_DTEXG_MASK 
+#define DDR_PHY_DTCR0_DTEXG_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTEXG_SHIFT                                                  23
+#define DDR_PHY_DTCR0_DTEXG_MASK                                                   0x00800000U
+
+/*Data Training Extended Write DQS*/
+#undef DDR_PHY_DTCR0_DTEXD_DEFVAL 
+#undef DDR_PHY_DTCR0_DTEXD_SHIFT 
+#undef DDR_PHY_DTCR0_DTEXD_MASK 
+#define DDR_PHY_DTCR0_DTEXD_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTEXD_SHIFT                                                  22
+#define DDR_PHY_DTCR0_DTEXD_MASK                                                   0x00400000U
+
+/*Data Training Debug Step*/
+#undef DDR_PHY_DTCR0_DTDSTP_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDSTP_SHIFT 
+#undef DDR_PHY_DTCR0_DTDSTP_MASK 
+#define DDR_PHY_DTCR0_DTDSTP_DEFVAL                                                0x800091C7
+#define DDR_PHY_DTCR0_DTDSTP_SHIFT                                                 21
+#define DDR_PHY_DTCR0_DTDSTP_MASK                                                  0x00200000U
+
+/*Data Training Debug Enable*/
+#undef DDR_PHY_DTCR0_DTDEN_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDEN_SHIFT 
+#undef DDR_PHY_DTCR0_DTDEN_MASK 
+#define DDR_PHY_DTCR0_DTDEN_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTDEN_SHIFT                                                  20
+#define DDR_PHY_DTCR0_DTDEN_MASK                                                   0x00100000U
+
+/*Data Training Debug Byte Select*/
+#undef DDR_PHY_DTCR0_DTDBS_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDBS_SHIFT 
+#undef DDR_PHY_DTCR0_DTDBS_MASK 
+#define DDR_PHY_DTCR0_DTDBS_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTDBS_SHIFT                                                  16
+#define DDR_PHY_DTCR0_DTDBS_MASK                                                   0x000F0000U
+
+/*Data Training read DBI deskewing configuration*/
+#undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL 
+#undef DDR_PHY_DTCR0_DTRDBITR_SHIFT 
+#undef DDR_PHY_DTCR0_DTRDBITR_MASK 
+#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL                                              0x800091C7
+#define DDR_PHY_DTCR0_DTRDBITR_SHIFT                                               14
+#define DDR_PHY_DTCR0_DTRDBITR_MASK                                                0x0000C000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL 
+#undef DDR_PHY_DTCR0_RESERVED_13_SHIFT 
+#undef DDR_PHY_DTCR0_RESERVED_13_MASK 
+#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL                                           0x800091C7
+#define DDR_PHY_DTCR0_RESERVED_13_SHIFT                                            13
+#define DDR_PHY_DTCR0_RESERVED_13_MASK                                             0x00002000U
+
+/*Data Training Write Bit Deskew Data Mask*/
+#undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL 
+#undef DDR_PHY_DTCR0_DTWBDDM_SHIFT 
+#undef DDR_PHY_DTCR0_DTWBDDM_MASK 
+#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL                                               0x800091C7
+#define DDR_PHY_DTCR0_DTWBDDM_SHIFT                                                12
+#define DDR_PHY_DTCR0_DTWBDDM_MASK                                                 0x00001000U
+
+/*Refreshes Issued During Entry to Training*/
+#undef DDR_PHY_DTCR0_RFSHEN_DEFVAL 
+#undef DDR_PHY_DTCR0_RFSHEN_SHIFT 
+#undef DDR_PHY_DTCR0_RFSHEN_MASK 
+#define DDR_PHY_DTCR0_RFSHEN_DEFVAL                                                0x800091C7
+#define DDR_PHY_DTCR0_RFSHEN_SHIFT                                                 8
+#define DDR_PHY_DTCR0_RFSHEN_MASK                                                  0x00000F00U
+
+/*Data Training Compare Data*/
+#undef DDR_PHY_DTCR0_DTCMPD_DEFVAL 
+#undef DDR_PHY_DTCR0_DTCMPD_SHIFT 
+#undef DDR_PHY_DTCR0_DTCMPD_MASK 
+#define DDR_PHY_DTCR0_DTCMPD_DEFVAL                                                0x800091C7
+#define DDR_PHY_DTCR0_DTCMPD_SHIFT                                                 7
+#define DDR_PHY_DTCR0_DTCMPD_MASK                                                  0x00000080U
+
+/*Data Training Using MPR*/
+#undef DDR_PHY_DTCR0_DTMPR_DEFVAL 
+#undef DDR_PHY_DTCR0_DTMPR_SHIFT 
+#undef DDR_PHY_DTCR0_DTMPR_MASK 
+#define DDR_PHY_DTCR0_DTMPR_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTMPR_SHIFT                                                  6
+#define DDR_PHY_DTCR0_DTMPR_MASK                                                   0x00000040U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 
+#undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 
+#undef DDR_PHY_DTCR0_RESERVED_5_4_MASK 
+#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL                                          0x800091C7
+#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT                                           4
+#define DDR_PHY_DTCR0_RESERVED_5_4_MASK                                            0x00000030U
+
+/*Data Training Repeat Number*/
+#undef DDR_PHY_DTCR0_DTRPTN_DEFVAL 
+#undef DDR_PHY_DTCR0_DTRPTN_SHIFT 
+#undef DDR_PHY_DTCR0_DTRPTN_MASK 
+#define DDR_PHY_DTCR0_DTRPTN_DEFVAL                                                0x800091C7
+#define DDR_PHY_DTCR0_DTRPTN_SHIFT                                                 0
+#define DDR_PHY_DTCR0_DTRPTN_MASK                                                  0x0000000FU
+
+/*Rank Enable.*/
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK 
+#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL                                           0x00030237
+#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT                                            18
+#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK                                             0xFFFC0000U
+
+/*Rank Enable.*/
+#undef DDR_PHY_DTCR1_RANKEN_DEFVAL 
+#undef DDR_PHY_DTCR1_RANKEN_SHIFT 
+#undef DDR_PHY_DTCR1_RANKEN_MASK 
+#define DDR_PHY_DTCR1_RANKEN_DEFVAL                                                0x00030237
+#define DDR_PHY_DTCR1_RANKEN_SHIFT                                                 16
+#define DDR_PHY_DTCR1_RANKEN_MASK                                                  0x00030000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_15_14_MASK 
+#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL                                        0x00030237
+#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT                                         14
+#define DDR_PHY_DTCR1_RESERVED_15_14_MASK                                          0x0000C000U
+
+/*Data Training Rank*/
+#undef DDR_PHY_DTCR1_DTRANK_DEFVAL 
+#undef DDR_PHY_DTCR1_DTRANK_SHIFT 
+#undef DDR_PHY_DTCR1_DTRANK_MASK 
+#define DDR_PHY_DTCR1_DTRANK_DEFVAL                                                0x00030237
+#define DDR_PHY_DTCR1_DTRANK_SHIFT                                                 12
+#define DDR_PHY_DTCR1_DTRANK_MASK                                                  0x00003000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_11_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_11_MASK 
+#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL                                           0x00030237
+#define DDR_PHY_DTCR1_RESERVED_11_SHIFT                                            11
+#define DDR_PHY_DTCR1_RESERVED_11_MASK                                             0x00000800U
+
+/*Read Leveling Gate Sampling Difference*/
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK 
+#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL                                            0x00030237
+#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT                                             8
+#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK                                              0x00000700U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_7_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_7_MASK 
+#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL                                            0x00030237
+#define DDR_PHY_DTCR1_RESERVED_7_SHIFT                                             7
+#define DDR_PHY_DTCR1_RESERVED_7_MASK                                              0x00000080U
+
+/*Read Leveling Gate Shift*/
+#undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL 
+#undef DDR_PHY_DTCR1_RDLVLGS_SHIFT 
+#undef DDR_PHY_DTCR1_RDLVLGS_MASK 
+#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL                                               0x00030237
+#define DDR_PHY_DTCR1_RDLVLGS_SHIFT                                                4
+#define DDR_PHY_DTCR1_RDLVLGS_MASK                                                 0x00000070U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_3_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_3_MASK 
+#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL                                            0x00030237
+#define DDR_PHY_DTCR1_RESERVED_3_SHIFT                                             3
+#define DDR_PHY_DTCR1_RESERVED_3_MASK                                              0x00000008U
+
+/*Read Preamble Training enable*/
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 
+#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL                                           0x00030237
+#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT                                            2
+#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK                                             0x00000004U
+
+/*Read Leveling Enable*/
+#undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL 
+#undef DDR_PHY_DTCR1_RDLVLEN_SHIFT 
+#undef DDR_PHY_DTCR1_RDLVLEN_MASK 
+#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL                                               0x00030237
+#define DDR_PHY_DTCR1_RDLVLEN_SHIFT                                                1
+#define DDR_PHY_DTCR1_RDLVLEN_MASK                                                 0x00000002U
+
+/*Basic Gate Training Enable*/
+#undef DDR_PHY_DTCR1_BSTEN_DEFVAL 
+#undef DDR_PHY_DTCR1_BSTEN_SHIFT 
+#undef DDR_PHY_DTCR1_BSTEN_MASK 
+#define DDR_PHY_DTCR1_BSTEN_DEFVAL                                                 0x00030237
+#define DDR_PHY_DTCR1_BSTEN_SHIFT                                                  0
+#define DDR_PHY_DTCR1_BSTEN_MASK                                                   0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 
+#undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT 
+#undef DDR_PHY_CATR0_RESERVED_31_21_MASK 
+#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL                                        0x00141054
+#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT                                         21
+#define DDR_PHY_CATR0_RESERVED_31_21_MASK                                          0xFFE00000U
+
+/*Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command*/
+#undef DDR_PHY_CATR0_CACD_DEFVAL 
+#undef DDR_PHY_CATR0_CACD_SHIFT 
+#undef DDR_PHY_CATR0_CACD_MASK 
+#define DDR_PHY_CATR0_CACD_DEFVAL                                                  0x00141054
+#define DDR_PHY_CATR0_CACD_SHIFT                                                   16
+#define DDR_PHY_CATR0_CACD_MASK                                                    0x001F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_CATR0_RESERVED_15_13_MASK 
+#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL                                        0x00141054
+#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT                                         13
+#define DDR_PHY_CATR0_RESERVED_15_13_MASK                                          0x0000E000U
+
+/*Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
+		 been sent to the memory*/
+#undef DDR_PHY_CATR0_CAADR_DEFVAL 
+#undef DDR_PHY_CATR0_CAADR_SHIFT 
+#undef DDR_PHY_CATR0_CAADR_MASK 
+#define DDR_PHY_CATR0_CAADR_DEFVAL                                                 0x00141054
+#define DDR_PHY_CATR0_CAADR_SHIFT                                                  8
+#define DDR_PHY_CATR0_CAADR_MASK                                                   0x00001F00U
+
+/*CA_1 Response Byte Lane 1*/
+#undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL 
+#undef DDR_PHY_CATR0_CA1BYTE1_SHIFT 
+#undef DDR_PHY_CATR0_CA1BYTE1_MASK 
+#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL                                              0x00141054
+#define DDR_PHY_CATR0_CA1BYTE1_SHIFT                                               4
+#define DDR_PHY_CATR0_CA1BYTE1_MASK                                                0x000000F0U
+
+/*CA_1 Response Byte Lane 0*/
+#undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL 
+#undef DDR_PHY_CATR0_CA1BYTE0_SHIFT 
+#undef DDR_PHY_CATR0_CA1BYTE0_MASK 
+#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL                                              0x00141054
+#define DDR_PHY_CATR0_CA1BYTE0_SHIFT                                               0
+#define DDR_PHY_CATR0_CA1BYTE0_MASK                                                0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK 
+#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL                                       0x00000005
+#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT                                        16
+#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK                                         0xFFFF0000U
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 
+#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL                                       0x00000005
+#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT                                        4
+#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK                                         0x0000FFF0U
+
+/*SDRAM On-die Termination Output Enable (OE) Mode Selection.*/
+#undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_MASK 
+#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL                                            0x00000005
+#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT                                             0
+#define DDR_PHY_RIOCR5_ODTOEMODE_MASK                                              0x0000000FU
+
+/*Address/Command Slew Rate (D3F I/O Only)*/
+#undef DDR_PHY_ACIOCR0_ACSR_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACSR_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACSR_MASK 
+#define DDR_PHY_ACIOCR0_ACSR_DEFVAL                                                0x30000000
+#define DDR_PHY_ACIOCR0_ACSR_SHIFT                                                 30
+#define DDR_PHY_ACIOCR0_ACSR_MASK                                                  0xC0000000U
+
+/*SDRAM Reset I/O Mode*/
+#undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT 
+#undef DDR_PHY_ACIOCR0_RSTIOM_MASK 
+#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL                                              0x30000000
+#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT                                               29
+#define DDR_PHY_ACIOCR0_RSTIOM_MASK                                                0x20000000U
+
+/*SDRAM Reset Power Down Receiver*/
+#undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT 
+#undef DDR_PHY_ACIOCR0_RSTPDR_MASK 
+#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL                                              0x30000000
+#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT                                               28
+#define DDR_PHY_ACIOCR0_RSTPDR_MASK                                                0x10000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 
+#undef DDR_PHY_ACIOCR0_RESERVED_27_MASK 
+#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL                                         0x30000000
+#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT                                          27
+#define DDR_PHY_ACIOCR0_RESERVED_27_MASK                                           0x08000000U
+
+/*SDRAM Reset On-Die Termination*/
+#undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RSTODT_SHIFT 
+#undef DDR_PHY_ACIOCR0_RSTODT_MASK 
+#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL                                              0x30000000
+#define DDR_PHY_ACIOCR0_RSTODT_SHIFT                                               26
+#define DDR_PHY_ACIOCR0_RSTODT_MASK                                                0x04000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 
+#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL                                      0x30000000
+#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT                                       10
+#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK                                        0x03FFFC00U
+
+/*CK Duty Cycle Correction*/
+#undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL 
+#undef DDR_PHY_ACIOCR0_CKDCC_SHIFT 
+#undef DDR_PHY_ACIOCR0_CKDCC_MASK 
+#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL                                               0x30000000
+#define DDR_PHY_ACIOCR0_CKDCC_SHIFT                                                6
+#define DDR_PHY_ACIOCR0_CKDCC_MASK                                                 0x000003C0U
+
+/*AC Power Down Receiver Mode*/
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK 
+#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL                                           0x30000000
+#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT                                            4
+#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK                                             0x00000030U
+
+/*AC On-die Termination Mode*/
+#undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACODTMODE_MASK 
+#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL                                           0x30000000
+#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT                                            2
+#define DDR_PHY_ACIOCR0_ACODTMODE_MASK                                             0x0000000CU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 
+#undef DDR_PHY_ACIOCR0_RESERVED_1_MASK 
+#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL                                          0x30000000
+#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT                                           1
+#define DDR_PHY_ACIOCR0_RESERVED_1_MASK                                            0x00000002U
+
+/*Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.*/
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 
+#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL                                        0x30000000
+#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT                                         0
+#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK                                          0x00000001U
+
+/*Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice*/
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 
+#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL                                       0x00000000
+#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT                                        31
+#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK                                         0x80000000U
+
+/*Clock gating for Output Enable D slices [0]*/
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL                                        0x00000000
+#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT                                         30
+#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK                                          0x40000000U
+
+/*Clock gating for Power Down Receiver D slices [0]*/
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL                                       0x00000000
+#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT                                        29
+#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK                                         0x20000000U
+
+/*Clock gating for Termination Enable D slices [0]*/
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL                                        0x00000000
+#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT                                         28
+#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK                                          0x10000000U
+
+/*Clock gating for CK# D slices [1:0]*/
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL                                         0x00000000
+#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT                                          26
+#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK                                           0x0C000000U
+
+/*Clock gating for CK D slices [1:0]*/
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL                                          0x00000000
+#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT                                           24
+#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK                                            0x03000000U
+
+/*Clock gating for AC D slices [23:0]*/
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL                                          0x00000000
+#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT                                           0
+#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK                                            0x00FFFFFFU
+
+/*SDRAM Parity Output Enable (OE) Mode Selection*/
+#undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_PAROEMODE_MASK 
+#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL                                           0x00000005
+#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT                                            30
+#define DDR_PHY_ACIOCR3_PAROEMODE_MASK                                             0xC0000000U
+
+/*SDRAM Bank Group Output Enable (OE) Mode Selection*/
+#undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_BGOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL                                            0x00000005
+#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT                                             26
+#define DDR_PHY_ACIOCR3_BGOEMODE_MASK                                              0x3C000000U
+
+/*SDRAM Bank Address Output Enable (OE) Mode Selection*/
+#undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_BAOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL                                            0x00000005
+#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT                                             22
+#define DDR_PHY_ACIOCR3_BAOEMODE_MASK                                              0x03C00000U
+
+/*SDRAM A[17] Output Enable (OE) Mode Selection*/
+#undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_A17OEMODE_MASK 
+#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL                                           0x00000005
+#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT                                            20
+#define DDR_PHY_ACIOCR3_A17OEMODE_MASK                                             0x00300000U
+
+/*SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection*/
+#undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_A16OEMODE_MASK 
+#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL                                           0x00000005
+#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT                                            18
+#define DDR_PHY_ACIOCR3_A16OEMODE_MASK                                             0x000C0000U
+
+/*SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)*/
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL                                           0x00000005
+#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT                                            16
+#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK                                             0x00030000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 
+#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL                                       0x00000005
+#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT                                        8
+#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK                                         0x0000FF00U
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 
+#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL                                       0x00000005
+#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT                                        4
+#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK                                         0x000000F0U
+
+/*SDRAM CK Output Enable (OE) Mode Selection.*/
+#undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL                                            0x00000005
+#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT                                             0
+#define DDR_PHY_ACIOCR3_CKOEMODE_MASK                                              0x0000000FU
+
+/*Clock gating for AC LB slices and loopback read valid slices*/
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK 
+#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL                                           0x00000000
+#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT                                            31
+#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK                                             0x80000000U
+
+/*Clock gating for Output Enable D slices [1]*/
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL                                        0x00000000
+#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT                                         30
+#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK                                          0x40000000U
+
+/*Clock gating for Power Down Receiver D slices [1]*/
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL                                       0x00000000
+#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT                                        29
+#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK                                         0x20000000U
+
+/*Clock gating for Termination Enable D slices [1]*/
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL                                        0x00000000
+#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT                                         28
+#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK                                          0x10000000U
+
+/*Clock gating for CK# D slices [3:2]*/
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL                                         0x00000000
+#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT                                          26
+#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK                                           0x0C000000U
+
+/*Clock gating for CK D slices [3:2]*/
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL                                          0x00000000
+#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT                                           24
+#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK                                            0x03000000U
+
+/*Clock gating for AC D slices [47:24]*/
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL                                          0x00000000
+#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT                                           0
+#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK                                            0x00FFFFFFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK 
+#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL                                       0x0F000000
+#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT                                        29
+#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK                                         0xE0000000U
+
+/*Address/command lane VREF Pad Enable*/
+#undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFPEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL                                             0x0F000000
+#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT                                              28
+#define DDR_PHY_IOVCR0_ACREFPEN_MASK                                               0x10000000U
+
+/*Address/command lane Internal VREF Enable*/
+#undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFEEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL                                             0x0F000000
+#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT                                              26
+#define DDR_PHY_IOVCR0_ACREFEEN_MASK                                               0x0C000000U
+
+/*Address/command lane Single-End VREF Enable*/
+#undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFSEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL                                             0x0F000000
+#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT                                              25
+#define DDR_PHY_IOVCR0_ACREFSEN_MASK                                               0x02000000U
+
+/*Address/command lane Internal VREF Enable*/
+#undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFIEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL                                             0x0F000000
+#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT                                              24
+#define DDR_PHY_IOVCR0_ACREFIEN_MASK                                               0x01000000U
+
+/*External VREF generato REFSEL range select*/
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 
+#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL                                       0x0F000000
+#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT                                        23
+#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK                                         0x00800000U
+
+/*Address/command lane External VREF Select*/
+#undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFESEL_MASK 
+#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL                                            0x0F000000
+#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT                                             16
+#define DDR_PHY_IOVCR0_ACREFESEL_MASK                                              0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 
+#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL                                       0x0F000000
+#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT                                        15
+#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK                                         0x00008000U
+
+/*Address/command lane Single-End VREF Select*/
+#undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFSSEL_MASK 
+#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL                                            0x0F000000
+#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT                                             8
+#define DDR_PHY_IOVCR0_ACREFSSEL_MASK                                              0x00007F00U
+
+/*Internal VREF generator REFSEL ragne select*/
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 
+#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL                                      0x0F000000
+#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT                                       7
+#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK                                        0x00000080U
+
+/*REFSEL Control for internal AC IOs*/
+#undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 
+#undef DDR_PHY_IOVCR0_ACVREFISEL_MASK 
+#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL                                           0x0F000000
+#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT                                            0
+#define DDR_PHY_IOVCR0_ACVREFISEL_MASK                                             0x0000007FU
+
+/*Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training*/
+#undef DDR_PHY_VTCR0_TVREF_DEFVAL 
+#undef DDR_PHY_VTCR0_TVREF_SHIFT 
+#undef DDR_PHY_VTCR0_TVREF_MASK 
+#define DDR_PHY_VTCR0_TVREF_DEFVAL                                                 0x70032019
+#define DDR_PHY_VTCR0_TVREF_SHIFT                                                  29
+#define DDR_PHY_VTCR0_TVREF_MASK                                                   0xE0000000U
+
+/*DRM DQ VREF training Enable*/
+#undef DDR_PHY_VTCR0_DVEN_DEFVAL 
+#undef DDR_PHY_VTCR0_DVEN_SHIFT 
+#undef DDR_PHY_VTCR0_DVEN_MASK 
+#define DDR_PHY_VTCR0_DVEN_DEFVAL                                                  0x70032019
+#define DDR_PHY_VTCR0_DVEN_SHIFT                                                   28
+#define DDR_PHY_VTCR0_DVEN_MASK                                                    0x10000000U
+
+/*Per Device Addressability Enable*/
+#undef DDR_PHY_VTCR0_PDAEN_DEFVAL 
+#undef DDR_PHY_VTCR0_PDAEN_SHIFT 
+#undef DDR_PHY_VTCR0_PDAEN_MASK 
+#define DDR_PHY_VTCR0_PDAEN_DEFVAL                                                 0x70032019
+#define DDR_PHY_VTCR0_PDAEN_SHIFT                                                  27
+#define DDR_PHY_VTCR0_PDAEN_MASK                                                   0x08000000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL 
+#undef DDR_PHY_VTCR0_RESERVED_26_SHIFT 
+#undef DDR_PHY_VTCR0_RESERVED_26_MASK 
+#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL                                           0x70032019
+#define DDR_PHY_VTCR0_RESERVED_26_SHIFT                                            26
+#define DDR_PHY_VTCR0_RESERVED_26_MASK                                             0x04000000U
+
+/*VREF Word Count*/
+#undef DDR_PHY_VTCR0_VWCR_DEFVAL 
+#undef DDR_PHY_VTCR0_VWCR_SHIFT 
+#undef DDR_PHY_VTCR0_VWCR_MASK 
+#define DDR_PHY_VTCR0_VWCR_DEFVAL                                                  0x70032019
+#define DDR_PHY_VTCR0_VWCR_SHIFT                                                   22
+#define DDR_PHY_VTCR0_VWCR_MASK                                                    0x03C00000U
+
+/*DRAM DQ VREF step size used during DRAM VREF training*/
+#undef DDR_PHY_VTCR0_DVSS_DEFVAL 
+#undef DDR_PHY_VTCR0_DVSS_SHIFT 
+#undef DDR_PHY_VTCR0_DVSS_MASK 
+#define DDR_PHY_VTCR0_DVSS_DEFVAL                                                  0x70032019
+#define DDR_PHY_VTCR0_DVSS_SHIFT                                                   18
+#define DDR_PHY_VTCR0_DVSS_MASK                                                    0x003C0000U
+
+/*Maximum VREF limit value used during DRAM VREF training*/
+#undef DDR_PHY_VTCR0_DVMAX_DEFVAL 
+#undef DDR_PHY_VTCR0_DVMAX_SHIFT 
+#undef DDR_PHY_VTCR0_DVMAX_MASK 
+#define DDR_PHY_VTCR0_DVMAX_DEFVAL                                                 0x70032019
+#define DDR_PHY_VTCR0_DVMAX_SHIFT                                                  12
+#define DDR_PHY_VTCR0_DVMAX_MASK                                                   0x0003F000U
+
+/*Minimum VREF limit value used during DRAM VREF training*/
+#undef DDR_PHY_VTCR0_DVMIN_DEFVAL 
+#undef DDR_PHY_VTCR0_DVMIN_SHIFT 
+#undef DDR_PHY_VTCR0_DVMIN_MASK 
+#define DDR_PHY_VTCR0_DVMIN_DEFVAL                                                 0x70032019
+#define DDR_PHY_VTCR0_DVMIN_SHIFT                                                  6
+#define DDR_PHY_VTCR0_DVMIN_MASK                                                   0x00000FC0U
+
+/*Initial DRAM DQ VREF value used during DRAM VREF training*/
+#undef DDR_PHY_VTCR0_DVINIT_DEFVAL 
+#undef DDR_PHY_VTCR0_DVINIT_SHIFT 
+#undef DDR_PHY_VTCR0_DVINIT_MASK 
+#define DDR_PHY_VTCR0_DVINIT_DEFVAL                                                0x70032019
+#define DDR_PHY_VTCR0_DVINIT_SHIFT                                                 0
+#define DDR_PHY_VTCR0_DVINIT_MASK                                                  0x0000003FU
+
+/*Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)*/
+#undef DDR_PHY_VTCR1_HVSS_DEFVAL 
+#undef DDR_PHY_VTCR1_HVSS_SHIFT 
+#undef DDR_PHY_VTCR1_HVSS_MASK 
+#define DDR_PHY_VTCR1_HVSS_DEFVAL                                                  0x07F00072
+#define DDR_PHY_VTCR1_HVSS_SHIFT                                                   28
+#define DDR_PHY_VTCR1_HVSS_MASK                                                    0xF0000000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL 
+#undef DDR_PHY_VTCR1_RESERVED_27_SHIFT 
+#undef DDR_PHY_VTCR1_RESERVED_27_MASK 
+#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL                                           0x07F00072
+#define DDR_PHY_VTCR1_RESERVED_27_SHIFT                                            27
+#define DDR_PHY_VTCR1_RESERVED_27_MASK                                             0x08000000U
+
+/*Maximum VREF limit value used during DRAM VREF training.*/
+#undef DDR_PHY_VTCR1_HVMAX_DEFVAL 
+#undef DDR_PHY_VTCR1_HVMAX_SHIFT 
+#undef DDR_PHY_VTCR1_HVMAX_MASK 
+#define DDR_PHY_VTCR1_HVMAX_DEFVAL                                                 0x07F00072
+#define DDR_PHY_VTCR1_HVMAX_SHIFT                                                  20
+#define DDR_PHY_VTCR1_HVMAX_MASK                                                   0x07F00000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL 
+#undef DDR_PHY_VTCR1_RESERVED_19_SHIFT 
+#undef DDR_PHY_VTCR1_RESERVED_19_MASK 
+#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL                                           0x07F00072
+#define DDR_PHY_VTCR1_RESERVED_19_SHIFT                                            19
+#define DDR_PHY_VTCR1_RESERVED_19_MASK                                             0x00080000U
+
+/*Minimum VREF limit value used during DRAM VREF training.*/
+#undef DDR_PHY_VTCR1_HVMIN_DEFVAL 
+#undef DDR_PHY_VTCR1_HVMIN_SHIFT 
+#undef DDR_PHY_VTCR1_HVMIN_MASK 
+#define DDR_PHY_VTCR1_HVMIN_DEFVAL                                                 0x07F00072
+#define DDR_PHY_VTCR1_HVMIN_SHIFT                                                  12
+#define DDR_PHY_VTCR1_HVMIN_MASK                                                   0x0007F000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL 
+#undef DDR_PHY_VTCR1_RESERVED_11_SHIFT 
+#undef DDR_PHY_VTCR1_RESERVED_11_MASK 
+#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL                                           0x07F00072
+#define DDR_PHY_VTCR1_RESERVED_11_SHIFT                                            11
+#define DDR_PHY_VTCR1_RESERVED_11_MASK                                             0x00000800U
+
+/*Static Host Vref Rank Value*/
+#undef DDR_PHY_VTCR1_SHRNK_DEFVAL 
+#undef DDR_PHY_VTCR1_SHRNK_SHIFT 
+#undef DDR_PHY_VTCR1_SHRNK_MASK 
+#define DDR_PHY_VTCR1_SHRNK_DEFVAL                                                 0x07F00072
+#define DDR_PHY_VTCR1_SHRNK_SHIFT                                                  9
+#define DDR_PHY_VTCR1_SHRNK_MASK                                                   0x00000600U
+
+/*Static Host Vref Rank Enable*/
+#undef DDR_PHY_VTCR1_SHREN_DEFVAL 
+#undef DDR_PHY_VTCR1_SHREN_SHIFT 
+#undef DDR_PHY_VTCR1_SHREN_MASK 
+#define DDR_PHY_VTCR1_SHREN_DEFVAL                                                 0x07F00072
+#define DDR_PHY_VTCR1_SHREN_SHIFT                                                  8
+#define DDR_PHY_VTCR1_SHREN_MASK                                                   0x00000100U
+
+/*Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training*/
+#undef DDR_PHY_VTCR1_TVREFIO_DEFVAL 
+#undef DDR_PHY_VTCR1_TVREFIO_SHIFT 
+#undef DDR_PHY_VTCR1_TVREFIO_MASK 
+#define DDR_PHY_VTCR1_TVREFIO_DEFVAL                                               0x07F00072
+#define DDR_PHY_VTCR1_TVREFIO_SHIFT                                                5
+#define DDR_PHY_VTCR1_TVREFIO_MASK                                                 0x000000E0U
+
+/*Eye LCDL Offset value for VREF training*/
+#undef DDR_PHY_VTCR1_EOFF_DEFVAL 
+#undef DDR_PHY_VTCR1_EOFF_SHIFT 
+#undef DDR_PHY_VTCR1_EOFF_MASK 
+#define DDR_PHY_VTCR1_EOFF_DEFVAL                                                  0x07F00072
+#define DDR_PHY_VTCR1_EOFF_SHIFT                                                   3
+#define DDR_PHY_VTCR1_EOFF_MASK                                                    0x00000018U
+
+/*Number of LCDL Eye points for which VREF training is repeated*/
+#undef DDR_PHY_VTCR1_ENUM_DEFVAL 
+#undef DDR_PHY_VTCR1_ENUM_SHIFT 
+#undef DDR_PHY_VTCR1_ENUM_MASK 
+#define DDR_PHY_VTCR1_ENUM_DEFVAL                                                  0x07F00072
+#define DDR_PHY_VTCR1_ENUM_SHIFT                                                   2
+#define DDR_PHY_VTCR1_ENUM_MASK                                                    0x00000004U
+
+/*HOST (IO) internal VREF training Enable*/
+#undef DDR_PHY_VTCR1_HVEN_DEFVAL 
+#undef DDR_PHY_VTCR1_HVEN_SHIFT 
+#undef DDR_PHY_VTCR1_HVEN_MASK 
+#define DDR_PHY_VTCR1_HVEN_DEFVAL                                                  0x07F00072
+#define DDR_PHY_VTCR1_HVEN_SHIFT                                                   1
+#define DDR_PHY_VTCR1_HVEN_MASK                                                    0x00000002U
+
+/*Host IO Type Control*/
+#undef DDR_PHY_VTCR1_HVIO_DEFVAL 
+#undef DDR_PHY_VTCR1_HVIO_SHIFT 
+#undef DDR_PHY_VTCR1_HVIO_MASK 
+#define DDR_PHY_VTCR1_HVIO_DEFVAL                                                  0x07F00072
+#define DDR_PHY_VTCR1_HVIO_SHIFT                                                   0
+#define DDR_PHY_VTCR1_HVIO_MASK                                                    0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*Delay select for the BDL on Address A[3].*/
+#undef DDR_PHY_ACBDLR6_A03BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A03BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A03BD_MASK 
+#define DDR_PHY_ACBDLR6_A03BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR6_A03BD_SHIFT                                                24
+#define DDR_PHY_ACBDLR6_A03BD_MASK                                                 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*Delay select for the BDL on Address A[2].*/
+#undef DDR_PHY_ACBDLR6_A02BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A02BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A02BD_MASK 
+#define DDR_PHY_ACBDLR6_A02BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR6_A02BD_SHIFT                                                16
+#define DDR_PHY_ACBDLR6_A02BD_MASK                                                 0x003F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*Delay select for the BDL on Address A[1].*/
+#undef DDR_PHY_ACBDLR6_A01BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A01BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A01BD_MASK 
+#define DDR_PHY_ACBDLR6_A01BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR6_A01BD_SHIFT                                                8
+#define DDR_PHY_ACBDLR6_A01BD_MASK                                                 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL                                        0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*Delay select for the BDL on Address A[0].*/
+#undef DDR_PHY_ACBDLR6_A00BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A00BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A00BD_MASK 
+#define DDR_PHY_ACBDLR6_A00BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR6_A00BD_SHIFT                                                0
+#define DDR_PHY_ACBDLR6_A00BD_MASK                                                 0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*Delay select for the BDL on Address A[7].*/
+#undef DDR_PHY_ACBDLR7_A07BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A07BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A07BD_MASK 
+#define DDR_PHY_ACBDLR7_A07BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR7_A07BD_SHIFT                                                24
+#define DDR_PHY_ACBDLR7_A07BD_MASK                                                 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*Delay select for the BDL on Address A[6].*/
+#undef DDR_PHY_ACBDLR7_A06BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A06BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A06BD_MASK 
+#define DDR_PHY_ACBDLR7_A06BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR7_A06BD_SHIFT                                                16
+#define DDR_PHY_ACBDLR7_A06BD_MASK                                                 0x003F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*Delay select for the BDL on Address A[5].*/
+#undef DDR_PHY_ACBDLR7_A05BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A05BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A05BD_MASK 
+#define DDR_PHY_ACBDLR7_A05BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR7_A05BD_SHIFT                                                8
+#define DDR_PHY_ACBDLR7_A05BD_MASK                                                 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL                                        0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*Delay select for the BDL on Address A[4].*/
+#undef DDR_PHY_ACBDLR7_A04BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A04BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A04BD_MASK 
+#define DDR_PHY_ACBDLR7_A04BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR7_A04BD_SHIFT                                                0
+#define DDR_PHY_ACBDLR7_A04BD_MASK                                                 0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*Delay select for the BDL on Address A[11].*/
+#undef DDR_PHY_ACBDLR8_A11BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A11BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A11BD_MASK 
+#define DDR_PHY_ACBDLR8_A11BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR8_A11BD_SHIFT                                                24
+#define DDR_PHY_ACBDLR8_A11BD_MASK                                                 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*Delay select for the BDL on Address A[10].*/
+#undef DDR_PHY_ACBDLR8_A10BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A10BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A10BD_MASK 
+#define DDR_PHY_ACBDLR8_A10BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR8_A10BD_SHIFT                                                16
+#define DDR_PHY_ACBDLR8_A10BD_MASK                                                 0x003F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*Delay select for the BDL on Address A[9].*/
+#undef DDR_PHY_ACBDLR8_A09BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A09BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A09BD_MASK 
+#define DDR_PHY_ACBDLR8_A09BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR8_A09BD_SHIFT                                                8
+#define DDR_PHY_ACBDLR8_A09BD_MASK                                                 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL                                        0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*Delay select for the BDL on Address A[8].*/
+#undef DDR_PHY_ACBDLR8_A08BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A08BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A08BD_MASK 
+#define DDR_PHY_ACBDLR8_A08BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR8_A08BD_SHIFT                                                0
+#define DDR_PHY_ACBDLR8_A08BD_MASK                                                 0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 
+#undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 
+#undef DDR_PHY_ZQCR_RESERVED_31_26_MASK 
+#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL                                         0x008A2858
+#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT                                          26
+#define DDR_PHY_ZQCR_RESERVED_31_26_MASK                                           0xFC000000U
+
+/*ZQ VREF Range*/
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 
+#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL                                         0x008A2858
+#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT                                          25
+#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK                                           0x02000000U
+
+/*Programmable Wait for Frequency B*/
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 
+#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL                                            0x008A2858
+#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT                                             19
+#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK                                              0x01F80000U
+
+/*Programmable Wait for Frequency A*/
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 
+#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL                                            0x008A2858
+#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT                                             13
+#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK                                              0x0007E000U
+
+/*ZQ VREF Pad Enable*/
+#undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT 
+#undef DDR_PHY_ZQCR_ZQREFPEN_MASK 
+#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL                                               0x008A2858
+#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT                                                12
+#define DDR_PHY_ZQCR_ZQREFPEN_MASK                                                 0x00001000U
+
+/*ZQ Internal VREF Enable*/
+#undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT 
+#undef DDR_PHY_ZQCR_ZQREFIEN_MASK 
+#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL                                               0x008A2858
+#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT                                                11
+#define DDR_PHY_ZQCR_ZQREFIEN_MASK                                                 0x00000800U
+
+/*Choice of termination mode*/
+#undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL 
+#undef DDR_PHY_ZQCR_ODT_MODE_SHIFT 
+#undef DDR_PHY_ZQCR_ODT_MODE_MASK 
+#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL                                               0x008A2858
+#define DDR_PHY_ZQCR_ODT_MODE_SHIFT                                                9
+#define DDR_PHY_ZQCR_ODT_MODE_MASK                                                 0x00000600U
+
+/*Force ZCAL VT update*/
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 
+#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL                                   0x008A2858
+#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT                                    8
+#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK                                     0x00000100U
+
+/*IO VT Drift Limit*/
+#undef DDR_PHY_ZQCR_IODLMT_DEFVAL 
+#undef DDR_PHY_ZQCR_IODLMT_SHIFT 
+#undef DDR_PHY_ZQCR_IODLMT_MASK 
+#define DDR_PHY_ZQCR_IODLMT_DEFVAL                                                 0x008A2858
+#define DDR_PHY_ZQCR_IODLMT_SHIFT                                                  5
+#define DDR_PHY_ZQCR_IODLMT_MASK                                                   0x000000E0U
+
+/*Averaging algorithm enable, if set, enables averaging algorithm*/
+#undef DDR_PHY_ZQCR_AVGEN_DEFVAL 
+#undef DDR_PHY_ZQCR_AVGEN_SHIFT 
+#undef DDR_PHY_ZQCR_AVGEN_MASK 
+#define DDR_PHY_ZQCR_AVGEN_DEFVAL                                                  0x008A2858
+#define DDR_PHY_ZQCR_AVGEN_SHIFT                                                   4
+#define DDR_PHY_ZQCR_AVGEN_MASK                                                    0x00000010U
+
+/*Maximum number of averaging rounds to be used by averaging algorithm*/
+#undef DDR_PHY_ZQCR_AVGMAX_DEFVAL 
+#undef DDR_PHY_ZQCR_AVGMAX_SHIFT 
+#undef DDR_PHY_ZQCR_AVGMAX_MASK 
+#define DDR_PHY_ZQCR_AVGMAX_DEFVAL                                                 0x008A2858
+#define DDR_PHY_ZQCR_AVGMAX_SHIFT                                                  2
+#define DDR_PHY_ZQCR_AVGMAX_MASK                                                   0x0000000CU
+
+/*ZQ Calibration Type*/
+#undef DDR_PHY_ZQCR_ZCALT_DEFVAL 
+#undef DDR_PHY_ZQCR_ZCALT_SHIFT 
+#undef DDR_PHY_ZQCR_ZCALT_MASK 
+#define DDR_PHY_ZQCR_ZCALT_DEFVAL                                                  0x008A2858
+#define DDR_PHY_ZQCR_ZCALT_SHIFT                                                   1
+#define DDR_PHY_ZQCR_ZCALT_MASK                                                    0x00000002U
+
+/*ZQ Power Down*/
+#undef DDR_PHY_ZQCR_ZQPD_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQPD_SHIFT 
+#undef DDR_PHY_ZQCR_ZQPD_MASK 
+#define DDR_PHY_ZQCR_ZQPD_DEFVAL                                                   0x008A2858
+#define DDR_PHY_ZQCR_ZQPD_SHIFT                                                    0
+#define DDR_PHY_ZQCR_ZQPD_MASK                                                     0x00000001U
+
+/*Pull-down drive strength ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT                                           31
+#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK                                            0x80000000U
+
+/*Pull-up drive strength ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT                                           30
+#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK                                            0x40000000U
+
+/*Pull-down termination ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT                                           29
+#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK                                            0x20000000U
+
+/*Pull-up termination ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT                                           28
+#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK                                            0x10000000U
+
+/*Calibration segment bypass*/
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 
+#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL                                              0x000077BB
+#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT                                               27
+#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK                                                0x08000000U
+
+/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 
+#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL                                             0x000077BB
+#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT                                              25
+#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK                                               0x06000000U
+
+/*Termination adjustment*/
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 
+#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL                                           0x000077BB
+#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT                                            22
+#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK                                             0x01C00000U
+
+/*Pulldown drive strength adjustment*/
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL                                        0x000077BB
+#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT                                         19
+#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK                                          0x00380000U
+
+/*Pullup drive strength adjustment*/
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL                                        0x000077BB
+#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT                                         16
+#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK                                          0x00070000U
+
+/*DRAM Impedance Divide Ratio*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL                                       0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT                                        12
+#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK                                         0x0000F000U
+
+/*HOST Impedance Divide Ratio*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL                                       0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT                                        8
+#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK                                         0x00000F00U
+
+/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL                                    0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT                                     4
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK                                      0x000000F0U
+
+/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL                                    0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT                                     0
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK                                      0x0000000FU
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 
+#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL                                       0x00000000
+#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT                                        26
+#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK                                         0xFC000000U
+
+/*Override value for the pull-up output impedance*/
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 
+#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL                                    0x00000000
+#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT                                     16
+#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK                                      0x03FF0000U
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 
+#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL                                       0x00000000
+#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT                                        10
+#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK                                         0x0000FC00U
+
+/*Override value for the pull-down output impedance*/
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 
+#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL                                    0x00000000
+#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT                                     0
+#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK                                      0x000003FFU
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 
+#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL                                       0x00000000
+#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT                                        26
+#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK                                         0xFC000000U
+
+/*Override value for the pull-up termination*/
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 
+#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL                                    0x00000000
+#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT                                     16
+#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK                                      0x03FF0000U
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 
+#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL                                       0x00000000
+#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT                                        10
+#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK                                         0x0000FC00U
+
+/*Override value for the pull-down termination*/
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 
+#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL                                    0x00000000
+#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT                                     0
+#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK                                      0x000003FFU
+
+/*Pull-down drive strength ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT                                           31
+#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK                                            0x80000000U
+
+/*Pull-up drive strength ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT                                           30
+#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK                                            0x40000000U
+
+/*Pull-down termination ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT                                           29
+#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK                                            0x20000000U
+
+/*Pull-up termination ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT                                           28
+#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK                                            0x10000000U
+
+/*Calibration segment bypass*/
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 
+#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL                                              0x000077BB
+#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT                                               27
+#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK                                                0x08000000U
+
+/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 
+#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL                                             0x000077BB
+#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT                                              25
+#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK                                               0x06000000U
+
+/*Termination adjustment*/
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 
+#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL                                           0x000077BB
+#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT                                            22
+#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK                                             0x01C00000U
+
+/*Pulldown drive strength adjustment*/
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL                                        0x000077BB
+#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT                                         19
+#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK                                          0x00380000U
+
+/*Pullup drive strength adjustment*/
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL                                        0x000077BB
+#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT                                         16
+#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK                                          0x00070000U
+
+/*DRAM Impedance Divide Ratio*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL                                       0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT                                        12
+#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK                                         0x0000F000U
+
+/*HOST Impedance Divide Ratio*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL                                       0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT                                        8
+#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK                                         0x00000F00U
+
+/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL                                    0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT                                     4
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK                                      0x000000F0U
+
+/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL                                    0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT                                     0
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK                                      0x0000000FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX0GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX0GCR0_CALBYP_MASK 
+#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX0GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX0GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX0GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX0GCR0_MDLEN_MASK 
+#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX0GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX0GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX0GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX0GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX0GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX0GCR0_RDDLY_MASK 
+#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX0GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX0GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX0GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX0GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX0GCR0_RTTOH_MASK 
+#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX0GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX0GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX0GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX0GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX0GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX0GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX0GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX0GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX0GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX0GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX0GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX0GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX0GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX0GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX0GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX0GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX0GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX0GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX0GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX0GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX0LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX0LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX0LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX0LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX0GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX0GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX0GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX0GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX0GTR0_WDQSL_MASK 
+#define DDR_PHY_DX0GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX0GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX0GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX0GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX0GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX0GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX0GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX0GTR0_WLSL_MASK 
+#define DDR_PHY_DX0GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX0GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX0GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX0GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX0GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX0GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX0GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX0GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX0GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX0GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX0GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX0GTR0_DGSL_MASK 
+#define DDR_PHY_DX0GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX0GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX0GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX1GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX1GCR0_CALBYP_MASK 
+#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX1GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX1GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX1GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX1GCR0_MDLEN_MASK 
+#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX1GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX1GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX1GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX1GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX1GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX1GCR0_RDDLY_MASK 
+#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX1GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX1GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX1GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX1GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX1GCR0_RTTOH_MASK 
+#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX1GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX1GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX1GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX1GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX1GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX1GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX1GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX1GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX1GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX1GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX1GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX1GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX1GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX1GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX1GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX1GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX1GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX1GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX1GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX1GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX1LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX1LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX1LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX1LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX1GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX1GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX1GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX1GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX1GTR0_WDQSL_MASK 
+#define DDR_PHY_DX1GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX1GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX1GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX1GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX1GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX1GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX1GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX1GTR0_WLSL_MASK 
+#define DDR_PHY_DX1GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX1GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX1GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX1GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX1GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX1GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX1GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX1GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX1GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX1GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX1GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX1GTR0_DGSL_MASK 
+#define DDR_PHY_DX1GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX1GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX1GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX2GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX2GCR0_CALBYP_MASK 
+#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX2GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX2GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX2GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX2GCR0_MDLEN_MASK 
+#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX2GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX2GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX2GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX2GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX2GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX2GCR0_RDDLY_MASK 
+#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX2GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX2GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX2GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX2GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX2GCR0_RTTOH_MASK 
+#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX2GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX2GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX2GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX2GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX2GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX2GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX2GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX2GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX2GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX2GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX2GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX2GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX2GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX2GCR1_QSSEL_MASK 
+#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX2GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX2GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX2GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_OEEN_MASK 
+#define DDR_PHY_DX2GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX2GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX2GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX2GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX2GCR1_PDREN_MASK 
+#define DDR_PHY_DX2GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX2GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX2GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX2GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_TEEN_MASK 
+#define DDR_PHY_DX2GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX2GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX2GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX2GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_DSEN_MASK 
+#define DDR_PHY_DX2GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX2GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX2GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX2GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_DMEN_MASK 
+#define DDR_PHY_DX2GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX2GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX2GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX2GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_DQEN_MASK 
+#define DDR_PHY_DX2GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX2GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX2GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX2GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX2GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX2GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX2GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX2GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX2GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX2GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX2GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX2GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX2GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX2GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX2GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX2LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX2LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX2LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX2LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX2GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX2GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX2GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX2GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX2GTR0_WDQSL_MASK 
+#define DDR_PHY_DX2GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX2GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX2GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX2GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX2GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX2GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX2GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX2GTR0_WLSL_MASK 
+#define DDR_PHY_DX2GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX2GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX2GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX2GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX2GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX2GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX2GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX2GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX2GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX2GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX2GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX2GTR0_DGSL_MASK 
+#define DDR_PHY_DX2GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX2GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX2GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX3GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX3GCR0_CALBYP_MASK 
+#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX3GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX3GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX3GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX3GCR0_MDLEN_MASK 
+#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX3GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX3GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX3GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX3GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX3GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX3GCR0_RDDLY_MASK 
+#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX3GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX3GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX3GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX3GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX3GCR0_RTTOH_MASK 
+#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX3GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX3GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX3GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX3GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX3GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX3GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX3GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX3GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX3GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX3GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX3GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX3GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX3GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX3GCR1_QSSEL_MASK 
+#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX3GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX3GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX3GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_OEEN_MASK 
+#define DDR_PHY_DX3GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX3GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX3GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX3GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX3GCR1_PDREN_MASK 
+#define DDR_PHY_DX3GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX3GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX3GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX3GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_TEEN_MASK 
+#define DDR_PHY_DX3GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX3GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX3GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX3GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_DSEN_MASK 
+#define DDR_PHY_DX3GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX3GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX3GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX3GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_DMEN_MASK 
+#define DDR_PHY_DX3GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX3GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX3GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX3GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_DQEN_MASK 
+#define DDR_PHY_DX3GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX3GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX3GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX3GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX3GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX3GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX3GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX3GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX3GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX3GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX3GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX3GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX3GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX3GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX3GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX3LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX3LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX3LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX3LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX3GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX3GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX3GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX3GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX3GTR0_WDQSL_MASK 
+#define DDR_PHY_DX3GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX3GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX3GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX3GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX3GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX3GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX3GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX3GTR0_WLSL_MASK 
+#define DDR_PHY_DX3GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX3GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX3GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX3GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX3GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX3GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX3GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX3GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX3GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX3GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX3GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX3GTR0_DGSL_MASK 
+#define DDR_PHY_DX3GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX3GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX3GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX4GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX4GCR0_CALBYP_MASK 
+#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX4GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX4GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX4GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX4GCR0_MDLEN_MASK 
+#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX4GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX4GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX4GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX4GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX4GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX4GCR0_RDDLY_MASK 
+#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX4GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX4GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX4GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX4GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX4GCR0_RTTOH_MASK 
+#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX4GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX4GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX4GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX4GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX4GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX4GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX4GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX4GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX4GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX4GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX4GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX4GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX4GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX4GCR1_QSSEL_MASK 
+#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX4GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX4GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX4GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_OEEN_MASK 
+#define DDR_PHY_DX4GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX4GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX4GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX4GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX4GCR1_PDREN_MASK 
+#define DDR_PHY_DX4GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX4GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX4GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX4GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_TEEN_MASK 
+#define DDR_PHY_DX4GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX4GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX4GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX4GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_DSEN_MASK 
+#define DDR_PHY_DX4GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX4GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX4GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX4GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_DMEN_MASK 
+#define DDR_PHY_DX4GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX4GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX4GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX4GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_DQEN_MASK 
+#define DDR_PHY_DX4GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX4GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX4GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX4GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX4GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX4GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX4GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX4GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX4GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX4GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX4GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX4GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX4GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX4GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX4GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX4LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX4LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX4LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX4LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX4GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX4GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX4GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX4GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX4GTR0_WDQSL_MASK 
+#define DDR_PHY_DX4GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX4GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX4GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX4GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX4GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX4GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX4GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX4GTR0_WLSL_MASK 
+#define DDR_PHY_DX4GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX4GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX4GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX4GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX4GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX4GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX4GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX4GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX4GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX4GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX4GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX4GTR0_DGSL_MASK 
+#define DDR_PHY_DX4GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX4GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX4GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX5GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX5GCR0_CALBYP_MASK 
+#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX5GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX5GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX5GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX5GCR0_MDLEN_MASK 
+#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX5GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX5GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX5GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX5GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX5GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX5GCR0_RDDLY_MASK 
+#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX5GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX5GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX5GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX5GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX5GCR0_RTTOH_MASK 
+#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX5GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX5GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX5GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX5GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX5GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX5GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX5GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX5GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX5GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX5GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX5GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX5GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX5GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX5GCR1_QSSEL_MASK 
+#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX5GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX5GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX5GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_OEEN_MASK 
+#define DDR_PHY_DX5GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX5GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX5GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX5GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX5GCR1_PDREN_MASK 
+#define DDR_PHY_DX5GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX5GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX5GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX5GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_TEEN_MASK 
+#define DDR_PHY_DX5GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX5GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX5GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX5GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_DSEN_MASK 
+#define DDR_PHY_DX5GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX5GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX5GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX5GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_DMEN_MASK 
+#define DDR_PHY_DX5GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX5GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX5GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX5GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_DQEN_MASK 
+#define DDR_PHY_DX5GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX5GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX5GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX5GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX5GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX5GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX5GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX5GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX5GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX5GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX5GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX5GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX5GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX5GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX5GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX5LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX5LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX5LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX5LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX5GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX5GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX5GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX5GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX5GTR0_WDQSL_MASK 
+#define DDR_PHY_DX5GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX5GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX5GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX5GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX5GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX5GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX5GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX5GTR0_WLSL_MASK 
+#define DDR_PHY_DX5GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX5GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX5GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX5GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX5GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX5GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX5GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX5GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX5GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX5GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX5GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX5GTR0_DGSL_MASK 
+#define DDR_PHY_DX5GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX5GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX5GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX6GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX6GCR0_CALBYP_MASK 
+#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX6GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX6GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX6GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX6GCR0_MDLEN_MASK 
+#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX6GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX6GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX6GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX6GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX6GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX6GCR0_RDDLY_MASK 
+#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX6GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX6GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX6GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX6GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX6GCR0_RTTOH_MASK 
+#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX6GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX6GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX6GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX6GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX6GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX6GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX6GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX6GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX6GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX6GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX6GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX6GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX6GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX6GCR1_QSSEL_MASK 
+#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX6GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX6GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX6GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_OEEN_MASK 
+#define DDR_PHY_DX6GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX6GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX6GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX6GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX6GCR1_PDREN_MASK 
+#define DDR_PHY_DX6GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX6GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX6GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX6GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_TEEN_MASK 
+#define DDR_PHY_DX6GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX6GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX6GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX6GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_DSEN_MASK 
+#define DDR_PHY_DX6GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX6GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX6GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX6GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_DMEN_MASK 
+#define DDR_PHY_DX6GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX6GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX6GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX6GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_DQEN_MASK 
+#define DDR_PHY_DX6GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX6GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX6GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX6GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX6GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX6GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX6GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX6GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX6GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX6GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX6GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX6GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX6GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX6GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX6GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX6LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX6LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX6LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX6LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX6GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX6GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX6GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX6GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX6GTR0_WDQSL_MASK 
+#define DDR_PHY_DX6GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX6GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX6GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX6GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX6GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX6GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX6GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX6GTR0_WLSL_MASK 
+#define DDR_PHY_DX6GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX6GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX6GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX6GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX6GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX6GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX6GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX6GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX6GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX6GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX6GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX6GTR0_DGSL_MASK 
+#define DDR_PHY_DX6GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX6GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX6GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX7GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX7GCR0_CALBYP_MASK 
+#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX7GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX7GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX7GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX7GCR0_MDLEN_MASK 
+#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX7GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX7GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX7GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX7GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX7GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX7GCR0_RDDLY_MASK 
+#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX7GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX7GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX7GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX7GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX7GCR0_RTTOH_MASK 
+#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX7GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX7GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX7GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX7GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX7GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX7GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX7GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX7GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX7GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX7GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX7GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX7GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX7GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX7GCR1_QSSEL_MASK 
+#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX7GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX7GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX7GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_OEEN_MASK 
+#define DDR_PHY_DX7GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX7GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX7GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX7GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX7GCR1_PDREN_MASK 
+#define DDR_PHY_DX7GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX7GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX7GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX7GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_TEEN_MASK 
+#define DDR_PHY_DX7GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX7GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX7GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX7GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_DSEN_MASK 
+#define DDR_PHY_DX7GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX7GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX7GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX7GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_DMEN_MASK 
+#define DDR_PHY_DX7GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX7GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX7GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX7GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_DQEN_MASK 
+#define DDR_PHY_DX7GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX7GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX7GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX7GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX7GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX7GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX7GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX7GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX7GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX7GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX7GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX7GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX7GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX7GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX7GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX7LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX7LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX7LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX7LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX7GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX7GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX7GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX7GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX7GTR0_WDQSL_MASK 
+#define DDR_PHY_DX7GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX7GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX7GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX7GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX7GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX7GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX7GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX7GTR0_WLSL_MASK 
+#define DDR_PHY_DX7GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX7GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX7GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX7GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX7GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX7GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX7GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX7GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX7GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX7GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX7GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX7GTR0_DGSL_MASK 
+#define DDR_PHY_DX7GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX7GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX7GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX8GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX8GCR0_CALBYP_MASK 
+#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX8GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX8GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX8GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX8GCR0_MDLEN_MASK 
+#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX8GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX8GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX8GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX8GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX8GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX8GCR0_RDDLY_MASK 
+#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX8GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX8GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX8GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX8GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX8GCR0_RTTOH_MASK 
+#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX8GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX8GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX8GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX8GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX8GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX8GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX8GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX8GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX8GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX8GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX8GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX8GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX8GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX8GCR1_QSSEL_MASK 
+#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX8GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX8GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX8GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_OEEN_MASK 
+#define DDR_PHY_DX8GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX8GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX8GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX8GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX8GCR1_PDREN_MASK 
+#define DDR_PHY_DX8GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX8GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX8GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX8GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_TEEN_MASK 
+#define DDR_PHY_DX8GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX8GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX8GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX8GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_DSEN_MASK 
+#define DDR_PHY_DX8GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX8GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX8GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX8GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_DMEN_MASK 
+#define DDR_PHY_DX8GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX8GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX8GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX8GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_DQEN_MASK 
+#define DDR_PHY_DX8GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX8GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX8GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX8GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX8GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX8GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX8GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX8GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX8GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX8GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX8GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX8GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX8GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX8GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX8GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX8LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX8LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX8LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX8LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX8GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX8GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX8GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX8GTR0_WDQSL_MASK 
+#define DDR_PHY_DX8GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX8GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX8GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX8GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX8GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX8GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX8GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX8GTR0_WLSL_MASK 
+#define DDR_PHY_DX8GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX8GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX8GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX8GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX8GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX8GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX8GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX8GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX8GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX8GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX8GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX8GTR0_DGSL_MASK 
+#define DDR_PHY_DX8GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX8GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX8GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL                                          0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL                                           0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS_N Resistor*/
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT                                  24
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
+
+/*Configurable Read Data Enable*/
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL                                          0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT                                           23
+#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK                                            0x00800000U
+
+/*OX Extension during Post-amble*/
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT                                          20
+#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK                                           0x00700000U
+
+/*OE Extension during Pre-amble*/
+#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT                                          18
+#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK                                           0x000C0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT                                     17
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK                                      0x00020000U
+
+/*I/O Assisted Gate Select*/
+#undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT                                            16
+#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK                                             0x00010000U
+
+/*I/O Loopback Select*/
+#undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT                                            15
+#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK                                             0x00008000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT                                  13
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
+
+/*Low Power Wakeup Threshold*/
+#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
+#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
+
+/*Read Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT                                            8
+#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK                                             0x00000100U
+
+/*Write Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT                                            7
+#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK                                             0x00000080U
+
+/*PUB Read FIFO Bypass*/
+#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT                                          6
+#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK                                           0x00000040U
+
+/*DATX8 Receive FIFO Read Mode*/
+#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT                                          4
+#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK                                           0x00000030U
+
+/*Disables the Read FIFO Reset*/
+#undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT                                          3
+#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK                                           0x00000008U
+
+/*Read DQS Gate I/O Loopback*/
+#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT                                          1
+#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK                                           0x00000006U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT                                      0
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK                                       0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 
+#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL                                      0x00000000
+#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT                                       31
+#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK                                        0x80000000U
+
+/*PVREF_DAC REFSEL range select*/
+#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 
+#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL                                       0x00000000
+#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT                                        28
+#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK                                         0x70000000U
+
+/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
+#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 
+#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT                                         25
+#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK                                          0x0E000000U
+
+/*DX IO Mode*/
+#undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK 
+#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT                                             22
+#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK                                              0x01C00000U
+
+/*DX IO Transmitter Mode*/
+#undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK 
+#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT                                             11
+#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK                                              0x003FF800U
+
+/*DX IO Receiver Mode*/
+#undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK 
+#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT                                             0
+#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK                                              0x000007FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL                                          0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL                                           0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS_N Resistor*/
+#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT                                  24
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
+
+/*Configurable Read Data Enable*/
+#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL                                          0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT                                           23
+#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK                                            0x00800000U
+
+/*OX Extension during Post-amble*/
+#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT                                          20
+#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK                                           0x00700000U
+
+/*OE Extension during Pre-amble*/
+#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT                                          18
+#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK                                           0x000C0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT                                     17
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK                                      0x00020000U
+
+/*I/O Assisted Gate Select*/
+#undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT                                            16
+#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK                                             0x00010000U
+
+/*I/O Loopback Select*/
+#undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT                                            15
+#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK                                             0x00008000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT                                  13
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
+
+/*Low Power Wakeup Threshold*/
+#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
+#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
+
+/*Read Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT                                            8
+#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK                                             0x00000100U
+
+/*Write Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT                                            7
+#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK                                             0x00000080U
+
+/*PUB Read FIFO Bypass*/
+#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT                                          6
+#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK                                           0x00000040U
+
+/*DATX8 Receive FIFO Read Mode*/
+#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT                                          4
+#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK                                           0x00000030U
+
+/*Disables the Read FIFO Reset*/
+#undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT                                          3
+#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK                                           0x00000008U
+
+/*Read DQS Gate I/O Loopback*/
+#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT                                          1
+#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK                                           0x00000006U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT                                      0
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK                                       0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 
+#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL                                      0x00000000
+#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT                                       31
+#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK                                        0x80000000U
+
+/*PVREF_DAC REFSEL range select*/
+#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 
+#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL                                       0x00000000
+#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT                                        28
+#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK                                         0x70000000U
+
+/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
+#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 
+#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT                                         25
+#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK                                          0x0E000000U
+
+/*DX IO Mode*/
+#undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK 
+#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT                                             22
+#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK                                              0x01C00000U
+
+/*DX IO Transmitter Mode*/
+#undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK 
+#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT                                             11
+#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK                                              0x003FF800U
+
+/*DX IO Receiver Mode*/
+#undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK 
+#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT                                             0
+#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK                                              0x000007FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL                                          0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL                                           0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS_N Resistor*/
+#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT                                  24
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
+
+/*Configurable Read Data Enable*/
+#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL                                          0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT                                           23
+#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK                                            0x00800000U
+
+/*OX Extension during Post-amble*/
+#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT                                          20
+#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK                                           0x00700000U
+
+/*OE Extension during Pre-amble*/
+#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT                                          18
+#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK                                           0x000C0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT                                     17
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK                                      0x00020000U
+
+/*I/O Assisted Gate Select*/
+#undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT                                            16
+#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK                                             0x00010000U
+
+/*I/O Loopback Select*/
+#undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT                                            15
+#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK                                             0x00008000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT                                  13
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
+
+/*Low Power Wakeup Threshold*/
+#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
+#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
+
+/*Read Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT                                            8
+#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK                                             0x00000100U
+
+/*Write Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT                                            7
+#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK                                             0x00000080U
+
+/*PUB Read FIFO Bypass*/
+#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT                                          6
+#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK                                           0x00000040U
+
+/*DATX8 Receive FIFO Read Mode*/
+#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT                                          4
+#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK                                           0x00000030U
+
+/*Disables the Read FIFO Reset*/
+#undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT                                          3
+#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK                                           0x00000008U
+
+/*Read DQS Gate I/O Loopback*/
+#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT                                          1
+#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK                                           0x00000006U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT                                      0
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK                                       0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 
+#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL                                      0x00000000
+#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT                                       31
+#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK                                        0x80000000U
+
+/*PVREF_DAC REFSEL range select*/
+#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 
+#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL                                       0x00000000
+#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT                                        28
+#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK                                         0x70000000U
+
+/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
+#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 
+#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT                                         25
+#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK                                          0x0E000000U
+
+/*DX IO Mode*/
+#undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK 
+#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT                                             22
+#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK                                              0x01C00000U
+
+/*DX IO Transmitter Mode*/
+#undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK 
+#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT                                             11
+#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK                                              0x003FF800U
+
+/*DX IO Receiver Mode*/
+#undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK 
+#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT                                             0
+#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK                                              0x000007FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL                                          0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL                                           0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS_N Resistor*/
+#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT                                  24
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
+
+/*Configurable Read Data Enable*/
+#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL                                          0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT                                           23
+#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK                                            0x00800000U
+
+/*OX Extension during Post-amble*/
+#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT                                          20
+#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK                                           0x00700000U
+
+/*OE Extension during Pre-amble*/
+#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT                                          18
+#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK                                           0x000C0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT                                     17
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK                                      0x00020000U
+
+/*I/O Assisted Gate Select*/
+#undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT                                            16
+#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK                                             0x00010000U
+
+/*I/O Loopback Select*/
+#undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT                                            15
+#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK                                             0x00008000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT                                  13
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
+
+/*Low Power Wakeup Threshold*/
+#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
+#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
+
+/*Read Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT                                            8
+#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK                                             0x00000100U
+
+/*Write Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT                                            7
+#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK                                             0x00000080U
+
+/*PUB Read FIFO Bypass*/
+#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT                                          6
+#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK                                           0x00000040U
+
+/*DATX8 Receive FIFO Read Mode*/
+#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT                                          4
+#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK                                           0x00000030U
+
+/*Disables the Read FIFO Reset*/
+#undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT                                          3
+#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK                                           0x00000008U
+
+/*Read DQS Gate I/O Loopback*/
+#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT                                          1
+#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK                                           0x00000006U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT                                      0
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK                                       0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 
+#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL                                      0x00000000
+#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT                                       31
+#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK                                        0x80000000U
+
+/*PVREF_DAC REFSEL range select*/
+#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 
+#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL                                       0x00000000
+#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT                                        28
+#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK                                         0x70000000U
+
+/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
+#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 
+#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT                                         25
+#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK                                          0x0E000000U
+
+/*DX IO Mode*/
+#undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK 
+#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT                                             22
+#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK                                              0x01C00000U
+
+/*DX IO Transmitter Mode*/
+#undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK 
+#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT                                             11
+#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK                                              0x003FF800U
+
+/*DX IO Receiver Mode*/
+#undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK 
+#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT                                             0
+#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK                                              0x000007FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL                                          0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL                                           0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS_N Resistor*/
+#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT                                  24
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
+
+/*Configurable Read Data Enable*/
+#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL                                          0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT                                           23
+#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK                                            0x00800000U
+
+/*OX Extension during Post-amble*/
+#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT                                          20
+#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK                                           0x00700000U
+
+/*OE Extension during Pre-amble*/
+#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT                                          18
+#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK                                           0x000C0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT                                     17
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK                                      0x00020000U
+
+/*I/O Assisted Gate Select*/
+#undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT                                            16
+#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK                                             0x00010000U
+
+/*I/O Loopback Select*/
+#undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT                                            15
+#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK                                             0x00008000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT                                  13
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
+
+/*Low Power Wakeup Threshold*/
+#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
+#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
+
+/*Read Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT                                            8
+#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK                                             0x00000100U
+
+/*Write Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT                                            7
+#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK                                             0x00000080U
+
+/*PUB Read FIFO Bypass*/
+#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT                                          6
+#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK                                           0x00000040U
+
+/*DATX8 Receive FIFO Read Mode*/
+#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT                                          4
+#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK                                           0x00000030U
+
+/*Disables the Read FIFO Reset*/
+#undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT                                          3
+#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK                                           0x00000008U
+
+/*Read DQS Gate I/O Loopback*/
+#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT                                          1
+#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK                                           0x00000006U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT                                      0
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK                                       0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 
+#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL                                      0x00000000
+#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT                                       31
+#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK                                        0x80000000U
+
+/*PVREF_DAC REFSEL range select*/
+#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 
+#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL                                       0x00000000
+#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT                                        28
+#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK                                         0x70000000U
+
+/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
+#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 
+#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT                                         25
+#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK                                          0x0E000000U
+
+/*DX IO Mode*/
+#undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK 
+#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT                                             22
+#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK                                              0x01C00000U
+
+/*DX IO Transmitter Mode*/
+#undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK 
+#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT                                             11
+#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK                                              0x003FF800U
+
+/*DX IO Receiver Mode*/
+#undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK 
+#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT                                             0
+#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK                                              0x000007FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL                                 0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL                                 0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL                                          0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL                                         0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL                                 0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL                                         0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL                                 0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL                                           0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS# Resistor*/
+#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL                                         0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PIR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_PIR_RESERVED_31_SHIFT 
+#undef DDR_PHY_PIR_RESERVED_31_MASK 
+#define DDR_PHY_PIR_RESERVED_31_DEFVAL                                             0x00000000
+#define DDR_PHY_PIR_RESERVED_31_SHIFT                                              31
+#define DDR_PHY_PIR_RESERVED_31_MASK                                               0x80000000U
+
+/*Impedance Calibration Bypass*/
+#undef DDR_PHY_PIR_ZCALBYP_DEFVAL 
+#undef DDR_PHY_PIR_ZCALBYP_SHIFT 
+#undef DDR_PHY_PIR_ZCALBYP_MASK 
+#define DDR_PHY_PIR_ZCALBYP_DEFVAL                                                 0x00000000
+#define DDR_PHY_PIR_ZCALBYP_SHIFT                                                  30
+#define DDR_PHY_PIR_ZCALBYP_MASK                                                   0x40000000U
+
+/*Digital Delay Line (DDL) Calibration Pause*/
+#undef DDR_PHY_PIR_DCALPSE_DEFVAL 
+#undef DDR_PHY_PIR_DCALPSE_SHIFT 
+#undef DDR_PHY_PIR_DCALPSE_MASK 
+#define DDR_PHY_PIR_DCALPSE_DEFVAL                                                 0x00000000
+#define DDR_PHY_PIR_DCALPSE_SHIFT                                                  29
+#define DDR_PHY_PIR_DCALPSE_MASK                                                   0x20000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PIR_RESERVED_28_21_DEFVAL 
+#undef DDR_PHY_PIR_RESERVED_28_21_SHIFT 
+#undef DDR_PHY_PIR_RESERVED_28_21_MASK 
+#define DDR_PHY_PIR_RESERVED_28_21_DEFVAL                                          0x00000000
+#define DDR_PHY_PIR_RESERVED_28_21_SHIFT                                           21
+#define DDR_PHY_PIR_RESERVED_28_21_MASK                                            0x1FE00000U
+
+/*Write DQS2DQ Training*/
+#undef DDR_PHY_PIR_DQS2DQ_DEFVAL 
+#undef DDR_PHY_PIR_DQS2DQ_SHIFT 
+#undef DDR_PHY_PIR_DQS2DQ_MASK 
+#define DDR_PHY_PIR_DQS2DQ_DEFVAL                                                  0x00000000
+#define DDR_PHY_PIR_DQS2DQ_SHIFT                                                   20
+#define DDR_PHY_PIR_DQS2DQ_MASK                                                    0x00100000U
+
+/*RDIMM Initialization*/
+#undef DDR_PHY_PIR_RDIMMINIT_DEFVAL 
+#undef DDR_PHY_PIR_RDIMMINIT_SHIFT 
+#undef DDR_PHY_PIR_RDIMMINIT_MASK 
+#define DDR_PHY_PIR_RDIMMINIT_DEFVAL                                               0x00000000
+#define DDR_PHY_PIR_RDIMMINIT_SHIFT                                                19
+#define DDR_PHY_PIR_RDIMMINIT_MASK                                                 0x00080000U
+
+/*Controller DRAM Initialization*/
+#undef DDR_PHY_PIR_CTLDINIT_DEFVAL 
+#undef DDR_PHY_PIR_CTLDINIT_SHIFT 
+#undef DDR_PHY_PIR_CTLDINIT_MASK 
+#define DDR_PHY_PIR_CTLDINIT_DEFVAL                                                0x00000000
+#define DDR_PHY_PIR_CTLDINIT_SHIFT                                                 18
+#define DDR_PHY_PIR_CTLDINIT_MASK                                                  0x00040000U
+
+/*VREF Training*/
+#undef DDR_PHY_PIR_VREF_DEFVAL 
+#undef DDR_PHY_PIR_VREF_SHIFT 
+#undef DDR_PHY_PIR_VREF_MASK 
+#define DDR_PHY_PIR_VREF_DEFVAL                                                    0x00000000
+#define DDR_PHY_PIR_VREF_SHIFT                                                     17
+#define DDR_PHY_PIR_VREF_MASK                                                      0x00020000U
+
+/*Static Read Training*/
+#undef DDR_PHY_PIR_SRD_DEFVAL 
+#undef DDR_PHY_PIR_SRD_SHIFT 
+#undef DDR_PHY_PIR_SRD_MASK 
+#define DDR_PHY_PIR_SRD_DEFVAL                                                     0x00000000
+#define DDR_PHY_PIR_SRD_SHIFT                                                      16
+#define DDR_PHY_PIR_SRD_MASK                                                       0x00010000U
+
+/*Write Data Eye Training*/
+#undef DDR_PHY_PIR_WREYE_DEFVAL 
+#undef DDR_PHY_PIR_WREYE_SHIFT 
+#undef DDR_PHY_PIR_WREYE_MASK 
+#define DDR_PHY_PIR_WREYE_DEFVAL                                                   0x00000000
+#define DDR_PHY_PIR_WREYE_SHIFT                                                    15
+#define DDR_PHY_PIR_WREYE_MASK                                                     0x00008000U
+
+/*Read Data Eye Training*/
+#undef DDR_PHY_PIR_RDEYE_DEFVAL 
+#undef DDR_PHY_PIR_RDEYE_SHIFT 
+#undef DDR_PHY_PIR_RDEYE_MASK 
+#define DDR_PHY_PIR_RDEYE_DEFVAL                                                   0x00000000
+#define DDR_PHY_PIR_RDEYE_SHIFT                                                    14
+#define DDR_PHY_PIR_RDEYE_MASK                                                     0x00004000U
+
+/*Write Data Bit Deskew*/
+#undef DDR_PHY_PIR_WRDSKW_DEFVAL 
+#undef DDR_PHY_PIR_WRDSKW_SHIFT 
+#undef DDR_PHY_PIR_WRDSKW_MASK 
+#define DDR_PHY_PIR_WRDSKW_DEFVAL                                                  0x00000000
+#define DDR_PHY_PIR_WRDSKW_SHIFT                                                   13
+#define DDR_PHY_PIR_WRDSKW_MASK                                                    0x00002000U
+
+/*Read Data Bit Deskew*/
+#undef DDR_PHY_PIR_RDDSKW_DEFVAL 
+#undef DDR_PHY_PIR_RDDSKW_SHIFT 
+#undef DDR_PHY_PIR_RDDSKW_MASK 
+#define DDR_PHY_PIR_RDDSKW_DEFVAL                                                  0x00000000
+#define DDR_PHY_PIR_RDDSKW_SHIFT                                                   12
+#define DDR_PHY_PIR_RDDSKW_MASK                                                    0x00001000U
+
+/*Write Leveling Adjust*/
+#undef DDR_PHY_PIR_WLADJ_DEFVAL 
+#undef DDR_PHY_PIR_WLADJ_SHIFT 
+#undef DDR_PHY_PIR_WLADJ_MASK 
+#define DDR_PHY_PIR_WLADJ_DEFVAL                                                   0x00000000
+#define DDR_PHY_PIR_WLADJ_SHIFT                                                    11
+#define DDR_PHY_PIR_WLADJ_MASK                                                     0x00000800U
+
+/*Read DQS Gate Training*/
+#undef DDR_PHY_PIR_QSGATE_DEFVAL 
+#undef DDR_PHY_PIR_QSGATE_SHIFT 
+#undef DDR_PHY_PIR_QSGATE_MASK 
+#define DDR_PHY_PIR_QSGATE_DEFVAL                                                  0x00000000
+#define DDR_PHY_PIR_QSGATE_SHIFT                                                   10
+#define DDR_PHY_PIR_QSGATE_MASK                                                    0x00000400U
+
+/*Write Leveling*/
+#undef DDR_PHY_PIR_WL_DEFVAL 
+#undef DDR_PHY_PIR_WL_SHIFT 
+#undef DDR_PHY_PIR_WL_MASK 
+#define DDR_PHY_PIR_WL_DEFVAL                                                      0x00000000
+#define DDR_PHY_PIR_WL_SHIFT                                                       9
+#define DDR_PHY_PIR_WL_MASK                                                        0x00000200U
+
+/*DRAM Initialization*/
+#undef DDR_PHY_PIR_DRAMINIT_DEFVAL 
+#undef DDR_PHY_PIR_DRAMINIT_SHIFT 
+#undef DDR_PHY_PIR_DRAMINIT_MASK 
+#define DDR_PHY_PIR_DRAMINIT_DEFVAL                                                0x00000000
+#define DDR_PHY_PIR_DRAMINIT_SHIFT                                                 8
+#define DDR_PHY_PIR_DRAMINIT_MASK                                                  0x00000100U
+
+/*DRAM Reset (DDR3/DDR4/LPDDR4 Only)*/
+#undef DDR_PHY_PIR_DRAMRST_DEFVAL 
+#undef DDR_PHY_PIR_DRAMRST_SHIFT 
+#undef DDR_PHY_PIR_DRAMRST_MASK 
+#define DDR_PHY_PIR_DRAMRST_DEFVAL                                                 0x00000000
+#define DDR_PHY_PIR_DRAMRST_SHIFT                                                  7
+#define DDR_PHY_PIR_DRAMRST_MASK                                                   0x00000080U
+
+/*PHY Reset*/
+#undef DDR_PHY_PIR_PHYRST_DEFVAL 
+#undef DDR_PHY_PIR_PHYRST_SHIFT 
+#undef DDR_PHY_PIR_PHYRST_MASK 
+#define DDR_PHY_PIR_PHYRST_DEFVAL                                                  0x00000000
+#define DDR_PHY_PIR_PHYRST_SHIFT                                                   6
+#define DDR_PHY_PIR_PHYRST_MASK                                                    0x00000040U
+
+/*Digital Delay Line (DDL) Calibration*/
+#undef DDR_PHY_PIR_DCAL_DEFVAL 
+#undef DDR_PHY_PIR_DCAL_SHIFT 
+#undef DDR_PHY_PIR_DCAL_MASK 
+#define DDR_PHY_PIR_DCAL_DEFVAL                                                    0x00000000
+#define DDR_PHY_PIR_DCAL_SHIFT                                                     5
+#define DDR_PHY_PIR_DCAL_MASK                                                      0x00000020U
+
+/*PLL Initialiazation*/
+#undef DDR_PHY_PIR_PLLINIT_DEFVAL 
+#undef DDR_PHY_PIR_PLLINIT_SHIFT 
+#undef DDR_PHY_PIR_PLLINIT_MASK 
+#define DDR_PHY_PIR_PLLINIT_DEFVAL                                                 0x00000000
+#define DDR_PHY_PIR_PLLINIT_SHIFT                                                  4
+#define DDR_PHY_PIR_PLLINIT_MASK                                                   0x00000010U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PIR_RESERVED_3_DEFVAL 
+#undef DDR_PHY_PIR_RESERVED_3_SHIFT 
+#undef DDR_PHY_PIR_RESERVED_3_MASK 
+#define DDR_PHY_PIR_RESERVED_3_DEFVAL                                              0x00000000
+#define DDR_PHY_PIR_RESERVED_3_SHIFT                                               3
+#define DDR_PHY_PIR_RESERVED_3_MASK                                                0x00000008U
+
+/*CA Training*/
+#undef DDR_PHY_PIR_CA_DEFVAL 
+#undef DDR_PHY_PIR_CA_SHIFT 
+#undef DDR_PHY_PIR_CA_MASK 
+#define DDR_PHY_PIR_CA_DEFVAL                                                      0x00000000
+#define DDR_PHY_PIR_CA_SHIFT                                                       2
+#define DDR_PHY_PIR_CA_MASK                                                        0x00000004U
+
+/*Impedance Calibration*/
+#undef DDR_PHY_PIR_ZCAL_DEFVAL 
+#undef DDR_PHY_PIR_ZCAL_SHIFT 
+#undef DDR_PHY_PIR_ZCAL_MASK 
+#define DDR_PHY_PIR_ZCAL_DEFVAL                                                    0x00000000
+#define DDR_PHY_PIR_ZCAL_SHIFT                                                     1
+#define DDR_PHY_PIR_ZCAL_MASK                                                      0x00000002U
+
+/*Initialization Trigger*/
+#undef DDR_PHY_PIR_INIT_DEFVAL 
+#undef DDR_PHY_PIR_INIT_SHIFT 
+#undef DDR_PHY_PIR_INIT_MASK 
+#define DDR_PHY_PIR_INIT_DEFVAL                                                    0x00000000
+#define DDR_PHY_PIR_INIT_SHIFT                                                     0
+#define DDR_PHY_PIR_INIT_MASK                                                      0x00000001U
+#undef IOU_SLCR_MIO_PIN_0_OFFSET 
+#define IOU_SLCR_MIO_PIN_0_OFFSET                                                  0XFF180000
+#undef IOU_SLCR_MIO_PIN_1_OFFSET 
+#define IOU_SLCR_MIO_PIN_1_OFFSET                                                  0XFF180004
+#undef IOU_SLCR_MIO_PIN_2_OFFSET 
+#define IOU_SLCR_MIO_PIN_2_OFFSET                                                  0XFF180008
+#undef IOU_SLCR_MIO_PIN_3_OFFSET 
+#define IOU_SLCR_MIO_PIN_3_OFFSET                                                  0XFF18000C
+#undef IOU_SLCR_MIO_PIN_4_OFFSET 
+#define IOU_SLCR_MIO_PIN_4_OFFSET                                                  0XFF180010
+#undef IOU_SLCR_MIO_PIN_5_OFFSET 
+#define IOU_SLCR_MIO_PIN_5_OFFSET                                                  0XFF180014
+#undef IOU_SLCR_MIO_PIN_6_OFFSET 
+#define IOU_SLCR_MIO_PIN_6_OFFSET                                                  0XFF180018
+#undef IOU_SLCR_MIO_PIN_7_OFFSET 
+#define IOU_SLCR_MIO_PIN_7_OFFSET                                                  0XFF18001C
+#undef IOU_SLCR_MIO_PIN_8_OFFSET 
+#define IOU_SLCR_MIO_PIN_8_OFFSET                                                  0XFF180020
+#undef IOU_SLCR_MIO_PIN_9_OFFSET 
+#define IOU_SLCR_MIO_PIN_9_OFFSET                                                  0XFF180024
+#undef IOU_SLCR_MIO_PIN_10_OFFSET 
+#define IOU_SLCR_MIO_PIN_10_OFFSET                                                 0XFF180028
+#undef IOU_SLCR_MIO_PIN_11_OFFSET 
+#define IOU_SLCR_MIO_PIN_11_OFFSET                                                 0XFF18002C
+#undef IOU_SLCR_MIO_PIN_12_OFFSET 
+#define IOU_SLCR_MIO_PIN_12_OFFSET                                                 0XFF180030
+#undef IOU_SLCR_MIO_PIN_13_OFFSET 
+#define IOU_SLCR_MIO_PIN_13_OFFSET                                                 0XFF180034
+#undef IOU_SLCR_MIO_PIN_14_OFFSET 
+#define IOU_SLCR_MIO_PIN_14_OFFSET                                                 0XFF180038
+#undef IOU_SLCR_MIO_PIN_15_OFFSET 
+#define IOU_SLCR_MIO_PIN_15_OFFSET                                                 0XFF18003C
+#undef IOU_SLCR_MIO_PIN_16_OFFSET 
+#define IOU_SLCR_MIO_PIN_16_OFFSET                                                 0XFF180040
+#undef IOU_SLCR_MIO_PIN_17_OFFSET 
+#define IOU_SLCR_MIO_PIN_17_OFFSET                                                 0XFF180044
+#undef IOU_SLCR_MIO_PIN_18_OFFSET 
+#define IOU_SLCR_MIO_PIN_18_OFFSET                                                 0XFF180048
+#undef IOU_SLCR_MIO_PIN_19_OFFSET 
+#define IOU_SLCR_MIO_PIN_19_OFFSET                                                 0XFF18004C
+#undef IOU_SLCR_MIO_PIN_20_OFFSET 
+#define IOU_SLCR_MIO_PIN_20_OFFSET                                                 0XFF180050
+#undef IOU_SLCR_MIO_PIN_21_OFFSET 
+#define IOU_SLCR_MIO_PIN_21_OFFSET                                                 0XFF180054
+#undef IOU_SLCR_MIO_PIN_22_OFFSET 
+#define IOU_SLCR_MIO_PIN_22_OFFSET                                                 0XFF180058
+#undef IOU_SLCR_MIO_PIN_23_OFFSET 
+#define IOU_SLCR_MIO_PIN_23_OFFSET                                                 0XFF18005C
+#undef IOU_SLCR_MIO_PIN_24_OFFSET 
+#define IOU_SLCR_MIO_PIN_24_OFFSET                                                 0XFF180060
+#undef IOU_SLCR_MIO_PIN_25_OFFSET 
+#define IOU_SLCR_MIO_PIN_25_OFFSET                                                 0XFF180064
+#undef IOU_SLCR_MIO_PIN_26_OFFSET 
+#define IOU_SLCR_MIO_PIN_26_OFFSET                                                 0XFF180068
+#undef IOU_SLCR_MIO_PIN_27_OFFSET 
+#define IOU_SLCR_MIO_PIN_27_OFFSET                                                 0XFF18006C
+#undef IOU_SLCR_MIO_PIN_28_OFFSET 
+#define IOU_SLCR_MIO_PIN_28_OFFSET                                                 0XFF180070
+#undef IOU_SLCR_MIO_PIN_29_OFFSET 
+#define IOU_SLCR_MIO_PIN_29_OFFSET                                                 0XFF180074
+#undef IOU_SLCR_MIO_PIN_30_OFFSET 
+#define IOU_SLCR_MIO_PIN_30_OFFSET                                                 0XFF180078
+#undef IOU_SLCR_MIO_PIN_31_OFFSET 
+#define IOU_SLCR_MIO_PIN_31_OFFSET                                                 0XFF18007C
+#undef IOU_SLCR_MIO_PIN_32_OFFSET 
+#define IOU_SLCR_MIO_PIN_32_OFFSET                                                 0XFF180080
+#undef IOU_SLCR_MIO_PIN_33_OFFSET 
+#define IOU_SLCR_MIO_PIN_33_OFFSET                                                 0XFF180084
+#undef IOU_SLCR_MIO_PIN_34_OFFSET 
+#define IOU_SLCR_MIO_PIN_34_OFFSET                                                 0XFF180088
+#undef IOU_SLCR_MIO_PIN_35_OFFSET 
+#define IOU_SLCR_MIO_PIN_35_OFFSET                                                 0XFF18008C
+#undef IOU_SLCR_MIO_PIN_36_OFFSET 
+#define IOU_SLCR_MIO_PIN_36_OFFSET                                                 0XFF180090
+#undef IOU_SLCR_MIO_PIN_37_OFFSET 
+#define IOU_SLCR_MIO_PIN_37_OFFSET                                                 0XFF180094
+#undef IOU_SLCR_MIO_PIN_38_OFFSET 
+#define IOU_SLCR_MIO_PIN_38_OFFSET                                                 0XFF180098
+#undef IOU_SLCR_MIO_PIN_39_OFFSET 
+#define IOU_SLCR_MIO_PIN_39_OFFSET                                                 0XFF18009C
+#undef IOU_SLCR_MIO_PIN_40_OFFSET 
+#define IOU_SLCR_MIO_PIN_40_OFFSET                                                 0XFF1800A0
+#undef IOU_SLCR_MIO_PIN_41_OFFSET 
+#define IOU_SLCR_MIO_PIN_41_OFFSET                                                 0XFF1800A4
+#undef IOU_SLCR_MIO_PIN_42_OFFSET 
+#define IOU_SLCR_MIO_PIN_42_OFFSET                                                 0XFF1800A8
+#undef IOU_SLCR_MIO_PIN_43_OFFSET 
+#define IOU_SLCR_MIO_PIN_43_OFFSET                                                 0XFF1800AC
+#undef IOU_SLCR_MIO_PIN_44_OFFSET 
+#define IOU_SLCR_MIO_PIN_44_OFFSET                                                 0XFF1800B0
+#undef IOU_SLCR_MIO_PIN_45_OFFSET 
+#define IOU_SLCR_MIO_PIN_45_OFFSET                                                 0XFF1800B4
+#undef IOU_SLCR_MIO_PIN_46_OFFSET 
+#define IOU_SLCR_MIO_PIN_46_OFFSET                                                 0XFF1800B8
+#undef IOU_SLCR_MIO_PIN_47_OFFSET 
+#define IOU_SLCR_MIO_PIN_47_OFFSET                                                 0XFF1800BC
+#undef IOU_SLCR_MIO_PIN_48_OFFSET 
+#define IOU_SLCR_MIO_PIN_48_OFFSET                                                 0XFF1800C0
+#undef IOU_SLCR_MIO_PIN_49_OFFSET 
+#define IOU_SLCR_MIO_PIN_49_OFFSET                                                 0XFF1800C4
+#undef IOU_SLCR_MIO_PIN_50_OFFSET 
+#define IOU_SLCR_MIO_PIN_50_OFFSET                                                 0XFF1800C8
+#undef IOU_SLCR_MIO_PIN_51_OFFSET 
+#define IOU_SLCR_MIO_PIN_51_OFFSET                                                 0XFF1800CC
+#undef IOU_SLCR_MIO_PIN_52_OFFSET 
+#define IOU_SLCR_MIO_PIN_52_OFFSET                                                 0XFF1800D0
+#undef IOU_SLCR_MIO_PIN_53_OFFSET 
+#define IOU_SLCR_MIO_PIN_53_OFFSET                                                 0XFF1800D4
+#undef IOU_SLCR_MIO_PIN_54_OFFSET 
+#define IOU_SLCR_MIO_PIN_54_OFFSET                                                 0XFF1800D8
+#undef IOU_SLCR_MIO_PIN_55_OFFSET 
+#define IOU_SLCR_MIO_PIN_55_OFFSET                                                 0XFF1800DC
+#undef IOU_SLCR_MIO_PIN_56_OFFSET 
+#define IOU_SLCR_MIO_PIN_56_OFFSET                                                 0XFF1800E0
+#undef IOU_SLCR_MIO_PIN_57_OFFSET 
+#define IOU_SLCR_MIO_PIN_57_OFFSET                                                 0XFF1800E4
+#undef IOU_SLCR_MIO_PIN_58_OFFSET 
+#define IOU_SLCR_MIO_PIN_58_OFFSET                                                 0XFF1800E8
+#undef IOU_SLCR_MIO_PIN_59_OFFSET 
+#define IOU_SLCR_MIO_PIN_59_OFFSET                                                 0XFF1800EC
+#undef IOU_SLCR_MIO_PIN_60_OFFSET 
+#define IOU_SLCR_MIO_PIN_60_OFFSET                                                 0XFF1800F0
+#undef IOU_SLCR_MIO_PIN_61_OFFSET 
+#define IOU_SLCR_MIO_PIN_61_OFFSET                                                 0XFF1800F4
+#undef IOU_SLCR_MIO_PIN_62_OFFSET 
+#define IOU_SLCR_MIO_PIN_62_OFFSET                                                 0XFF1800F8
+#undef IOU_SLCR_MIO_PIN_63_OFFSET 
+#define IOU_SLCR_MIO_PIN_63_OFFSET                                                 0XFF1800FC
+#undef IOU_SLCR_MIO_PIN_64_OFFSET 
+#define IOU_SLCR_MIO_PIN_64_OFFSET                                                 0XFF180100
+#undef IOU_SLCR_MIO_PIN_65_OFFSET 
+#define IOU_SLCR_MIO_PIN_65_OFFSET                                                 0XFF180104
+#undef IOU_SLCR_MIO_PIN_66_OFFSET 
+#define IOU_SLCR_MIO_PIN_66_OFFSET                                                 0XFF180108
+#undef IOU_SLCR_MIO_PIN_67_OFFSET 
+#define IOU_SLCR_MIO_PIN_67_OFFSET                                                 0XFF18010C
+#undef IOU_SLCR_MIO_PIN_68_OFFSET 
+#define IOU_SLCR_MIO_PIN_68_OFFSET                                                 0XFF180110
+#undef IOU_SLCR_MIO_PIN_69_OFFSET 
+#define IOU_SLCR_MIO_PIN_69_OFFSET                                                 0XFF180114
+#undef IOU_SLCR_MIO_PIN_70_OFFSET 
+#define IOU_SLCR_MIO_PIN_70_OFFSET                                                 0XFF180118
+#undef IOU_SLCR_MIO_PIN_71_OFFSET 
+#define IOU_SLCR_MIO_PIN_71_OFFSET                                                 0XFF18011C
+#undef IOU_SLCR_MIO_PIN_72_OFFSET 
+#define IOU_SLCR_MIO_PIN_72_OFFSET                                                 0XFF180120
+#undef IOU_SLCR_MIO_PIN_73_OFFSET 
+#define IOU_SLCR_MIO_PIN_73_OFFSET                                                 0XFF180124
+#undef IOU_SLCR_MIO_PIN_74_OFFSET 
+#define IOU_SLCR_MIO_PIN_74_OFFSET                                                 0XFF180128
+#undef IOU_SLCR_MIO_PIN_75_OFFSET 
+#define IOU_SLCR_MIO_PIN_75_OFFSET                                                 0XFF18012C
+#undef IOU_SLCR_MIO_PIN_76_OFFSET 
+#define IOU_SLCR_MIO_PIN_76_OFFSET                                                 0XFF180130
+#undef IOU_SLCR_MIO_PIN_77_OFFSET 
+#define IOU_SLCR_MIO_PIN_77_OFFSET                                                 0XFF180134
+#undef IOU_SLCR_MIO_MST_TRI0_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI0_OFFSET                                               0XFF180204
+#undef IOU_SLCR_MIO_MST_TRI1_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI1_OFFSET                                               0XFF180208
+#undef IOU_SLCR_MIO_MST_TRI2_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI2_OFFSET                                               0XFF18020C
+#undef IOU_SLCR_BANK0_CTRL0_OFFSET 
+#define IOU_SLCR_BANK0_CTRL0_OFFSET                                                0XFF180138
+#undef IOU_SLCR_BANK0_CTRL1_OFFSET 
+#define IOU_SLCR_BANK0_CTRL1_OFFSET                                                0XFF18013C
+#undef IOU_SLCR_BANK0_CTRL3_OFFSET 
+#define IOU_SLCR_BANK0_CTRL3_OFFSET                                                0XFF180140
+#undef IOU_SLCR_BANK0_CTRL4_OFFSET 
+#define IOU_SLCR_BANK0_CTRL4_OFFSET                                                0XFF180144
+#undef IOU_SLCR_BANK0_CTRL5_OFFSET 
+#define IOU_SLCR_BANK0_CTRL5_OFFSET                                                0XFF180148
+#undef IOU_SLCR_BANK0_CTRL6_OFFSET 
+#define IOU_SLCR_BANK0_CTRL6_OFFSET                                                0XFF18014C
+#undef IOU_SLCR_BANK1_CTRL0_OFFSET 
+#define IOU_SLCR_BANK1_CTRL0_OFFSET                                                0XFF180154
+#undef IOU_SLCR_BANK1_CTRL1_OFFSET 
+#define IOU_SLCR_BANK1_CTRL1_OFFSET                                                0XFF180158
+#undef IOU_SLCR_BANK1_CTRL3_OFFSET 
+#define IOU_SLCR_BANK1_CTRL3_OFFSET                                                0XFF18015C
+#undef IOU_SLCR_BANK1_CTRL4_OFFSET 
+#define IOU_SLCR_BANK1_CTRL4_OFFSET                                                0XFF180160
+#undef IOU_SLCR_BANK1_CTRL5_OFFSET 
+#define IOU_SLCR_BANK1_CTRL5_OFFSET                                                0XFF180164
+#undef IOU_SLCR_BANK1_CTRL6_OFFSET 
+#define IOU_SLCR_BANK1_CTRL6_OFFSET                                                0XFF180168
+#undef IOU_SLCR_BANK2_CTRL0_OFFSET 
+#define IOU_SLCR_BANK2_CTRL0_OFFSET                                                0XFF180170
+#undef IOU_SLCR_BANK2_CTRL1_OFFSET 
+#define IOU_SLCR_BANK2_CTRL1_OFFSET                                                0XFF180174
+#undef IOU_SLCR_BANK2_CTRL3_OFFSET 
+#define IOU_SLCR_BANK2_CTRL3_OFFSET                                                0XFF180178
+#undef IOU_SLCR_BANK2_CTRL4_OFFSET 
+#define IOU_SLCR_BANK2_CTRL4_OFFSET                                                0XFF18017C
+#undef IOU_SLCR_BANK2_CTRL5_OFFSET 
+#define IOU_SLCR_BANK2_CTRL5_OFFSET                                                0XFF180180
+#undef IOU_SLCR_BANK2_CTRL6_OFFSET 
+#define IOU_SLCR_BANK2_CTRL6_OFFSET                                                0XFF180184
+#undef IOU_SLCR_MIO_LOOPBACK_OFFSET 
+#define IOU_SLCR_MIO_LOOPBACK_OFFSET                                               0XFF180200
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
+		us)*/
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)*/
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
+		us)*/
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
+		sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
+		Output, tracedq[4]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= 
+		tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, 
+		racedq[5]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[0]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
+		, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
+		ce Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[1]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, 
+		utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
+		RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[2]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[3]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		*/
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
+		ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
+		dq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
+		out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
+		bus)*/
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
+		n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
+		0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
+		l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
+		c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 
+		= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- 
+		UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
+		(Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed*/
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
+		23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
+		*/
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
+		scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
+		 Tamper)*/
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
+		Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
+		test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
+		U Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform 
+		lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)*/
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
+		 (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
+		 tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
+		_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
+		ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		*/
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
+		an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
+		_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= 
+		race, Output, tracedq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
+		an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
+		c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
+		[11]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
+		an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
+		ut, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
+		 Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
+		rt Databus)*/
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
+		an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
+		Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- 
+		UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
+		an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
+		ut, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
+		an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
+		k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
+		(Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
+		[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
+		_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
+		Control Signal)*/
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
+		in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
+		]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
+		ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
+		i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
+		i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
+		0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
+		ed*/
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
+		bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
+		d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
+		clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
+		t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
+		serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)*/
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[2]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[0]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[1]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[3]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)*/
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[4]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[5]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[6]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[7]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
+		i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 trace, Output, tracedq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
+		dq[11]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[2]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
+		2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
+		Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[0]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[1]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed*/
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[3]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[4]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
+		t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[5]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[6]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[7]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
+		d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
+		_clk_out- (SDSDIO clock) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
+		 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
+		O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
+		t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK                                            0x000000E0U
+
+/*Master Tri-state Enable for pin 0, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 1, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 2, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 3, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 4, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 5, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 6, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 7, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 8, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 9, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 10, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 11, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 12, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 13, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK                                      0x00002000U
+
+/*Master Tri-state Enable for pin 14, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT                                     14
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK                                      0x00004000U
+
+/*Master Tri-state Enable for pin 15, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT                                     15
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK                                      0x00008000U
+
+/*Master Tri-state Enable for pin 16, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT                                     16
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK                                      0x00010000U
+
+/*Master Tri-state Enable for pin 17, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT                                     17
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK                                      0x00020000U
+
+/*Master Tri-state Enable for pin 18, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT                                     18
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK                                      0x00040000U
+
+/*Master Tri-state Enable for pin 19, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT                                     19
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK                                      0x00080000U
+
+/*Master Tri-state Enable for pin 20, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT                                     20
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK                                      0x00100000U
+
+/*Master Tri-state Enable for pin 21, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT                                     21
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK                                      0x00200000U
+
+/*Master Tri-state Enable for pin 22, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT                                     22
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK                                      0x00400000U
+
+/*Master Tri-state Enable for pin 23, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT                                     23
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK                                      0x00800000U
+
+/*Master Tri-state Enable for pin 24, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT                                     24
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK                                      0x01000000U
+
+/*Master Tri-state Enable for pin 25, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT                                     25
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK                                      0x02000000U
+
+/*Master Tri-state Enable for pin 26, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT                                     26
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK                                      0x04000000U
+
+/*Master Tri-state Enable for pin 27, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT                                     27
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK                                      0x08000000U
+
+/*Master Tri-state Enable for pin 28, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT                                     28
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK                                      0x10000000U
+
+/*Master Tri-state Enable for pin 29, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT                                     29
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK                                      0x20000000U
+
+/*Master Tri-state Enable for pin 30, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT                                     30
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK                                      0x40000000U
+
+/*Master Tri-state Enable for pin 31, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT                                     31
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK                                      0x80000000U
+
+/*Master Tri-state Enable for pin 32, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 33, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 34, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 35, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 36, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 37, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 38, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 39, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 40, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 41, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 42, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 43, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 44, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 45, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK                                      0x00002000U
+
+/*Master Tri-state Enable for pin 46, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT                                     14
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK                                      0x00004000U
+
+/*Master Tri-state Enable for pin 47, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT                                     15
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK                                      0x00008000U
+
+/*Master Tri-state Enable for pin 48, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT                                     16
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK                                      0x00010000U
+
+/*Master Tri-state Enable for pin 49, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT                                     17
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK                                      0x00020000U
+
+/*Master Tri-state Enable for pin 50, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT                                     18
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK                                      0x00040000U
+
+/*Master Tri-state Enable for pin 51, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT                                     19
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK                                      0x00080000U
+
+/*Master Tri-state Enable for pin 52, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT                                     20
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK                                      0x00100000U
+
+/*Master Tri-state Enable for pin 53, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT                                     21
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK                                      0x00200000U
+
+/*Master Tri-state Enable for pin 54, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT                                     22
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK                                      0x00400000U
+
+/*Master Tri-state Enable for pin 55, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT                                     23
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK                                      0x00800000U
+
+/*Master Tri-state Enable for pin 56, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT                                     24
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK                                      0x01000000U
+
+/*Master Tri-state Enable for pin 57, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT                                     25
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK                                      0x02000000U
+
+/*Master Tri-state Enable for pin 58, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT                                     26
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK                                      0x04000000U
+
+/*Master Tri-state Enable for pin 59, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT                                     27
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK                                      0x08000000U
+
+/*Master Tri-state Enable for pin 60, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT                                     28
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK                                      0x10000000U
+
+/*Master Tri-state Enable for pin 61, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT                                     29
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK                                      0x20000000U
+
+/*Master Tri-state Enable for pin 62, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT                                     30
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK                                      0x40000000U
+
+/*Master Tri-state Enable for pin 63, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT                                     31
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK                                      0x80000000U
+
+/*Master Tri-state Enable for pin 64, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 65, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 66, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 67, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 68, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 69, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 70, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 71, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 72, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 73, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 74, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 75, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 76, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 77, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK                                      0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               0
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               1
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               2
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               3
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               4
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               5
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               6
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               7
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               8
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               9
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              10
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              11
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              12
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              13
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              14
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              15
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              16
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              17
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              18
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              19
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              20
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              21
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              22
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              23
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              24
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              25
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               0
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               1
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               2
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               3
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               4
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               5
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               6
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               7
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               8
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               9
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              10
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              11
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              12
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              13
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              14
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              15
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              16
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              17
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              18
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              19
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              20
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              21
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              22
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              23
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              24
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              25
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               0
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               1
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               2
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               3
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               4
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               5
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               6
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               7
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               8
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               9
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              10
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              11
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              12
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              13
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              14
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              15
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              16
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              17
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              18
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              19
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              20
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              21
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              22
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              23
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              24
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              25
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
+
+/*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
+		ts to I2C 0 inputs.*/
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT                                 3
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK                                  0x00000008U
+
+/*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
+		.*/
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT                                 2
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK                                  0x00000004U
+
+/*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
+		outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL                                  0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT                                   1
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK                                    0x00000002U
+
+/*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
+		ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT                                 0
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK                                  0x00000001U
+#undef CRL_APB_RST_LPD_IOU0_OFFSET 
+#define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef IOU_SLCR_CTRL_REG_SD_OFFSET 
+#define IOU_SLCR_CTRL_REG_SD_OFFSET                                                0XFF180310
+#undef IOU_SLCR_SD_CONFIG_REG2_OFFSET 
+#define IOU_SLCR_SD_CONFIG_REG2_OFFSET                                             0XFF180320
+#undef IOU_SLCR_SD_CONFIG_REG1_OFFSET 
+#define IOU_SLCR_SD_CONFIG_REG1_OFFSET                                             0XFF18031C
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 
+#define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF000034
+#undef UART0_BAUD_RATE_GEN_REG0_OFFSET 
+#define UART0_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF000018
+#undef UART0_CONTROL_REG0_OFFSET 
+#define UART0_CONTROL_REG0_OFFSET                                                  0XFF000000
+#undef UART0_MODE_REG0_OFFSET 
+#define UART0_MODE_REG0_OFFSET                                                     0XFF000004
+#undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 
+#define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF010034
+#undef UART1_BAUD_RATE_GEN_REG0_OFFSET 
+#define UART1_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF010018
+#undef UART1_CONTROL_REG0_OFFSET 
+#define UART1_CONTROL_REG0_OFFSET                                                  0XFF010000
+#undef UART1_MODE_REG0_OFFSET 
+#define UART1_MODE_REG0_OFFSET                                                     0XFF010004
+#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 
+#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET                                           0XFF4B0024
+#undef CSU_TAMPER_STATUS_OFFSET 
+#define CSU_TAMPER_STATUS_OFFSET                                                   0XFFCA5000
+#undef APU_ACE_CTRL_OFFSET 
+#define APU_ACE_CTRL_OFFSET                                                        0XFD5C0060
+#undef RTC_CONTROL_OFFSET 
+#define RTC_CONTROL_OFFSET                                                         0XFFA60040
+
+/*GEM 3 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT                                      0
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK                                       0x00000001U
+
+/*USB 0 reset for control registers*/
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
+
+/*USB 0 sleep circuit reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
+
+/*USB 0 reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
+
+/*PCIE config reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL                                  0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT                                   19
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                                    0x00080000U
+
+/*PCIE control block level reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL                                 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT                                  17
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK                                   0x00020000U
+
+/*PCIE bridge block level reset (AXI interface)*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL                               0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT                                18
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK                                 0x00040000U
+
+/*Display Port block level reset (includes DPDMA)*/
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
+#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
+
+/*FPD WDT reset*/
+#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL                                      0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT                                       15
+#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK                                        0x00008000U
+
+/*GDMA block level reset*/
+#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL                                      0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT                                       6
+#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK                                        0x00000040U
+
+/*Pixel Processor (submodule of GPU) block level reset*/
+#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL                                   0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT                                    4
+#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK                                     0x00000010U
+
+/*Pixel Processor (submodule of GPU) block level reset*/
+#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL                                   0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT                                    5
+#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK                                     0x00000020U
+
+/*GPU block level reset*/
+#undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL                                       0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT                                        3
+#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK                                         0x00000008U
+
+/*GT block level reset*/
+#undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL                                        0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT                                         2
+#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK                                          0x00000004U
+
+/*Sata block level reset*/
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT                                     6
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK                                      0x00000040U
+
+/*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT                                    15
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK                                     0x00008000U
+
+/*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL                                0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT                                 28
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK                                  0x30000000U
+
+/*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT                                     25
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK                                      0x02000000U
+
+/*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT                                     24
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK                                      0x01000000U
+
+/*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT                                     23
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK                                      0x00800000U
+
+/*Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.*/
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 
+#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL                                 0x32403240
+#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT                                  23
+#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK                                   0x7F800000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT                                      8
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK                                       0x00000100U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT                                      9
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK                                       0x00000200U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT                                      10
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK                                       0x00000400U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT                                      15
+#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK                                       0x00008000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT                                      11
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK                                       0x00000800U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT                                      12
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK                                       0x00001000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT                                      13
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK                                       0x00002000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT                                      14
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK                                       0x00004000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT                                     1
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK                                      0x00000002U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT                                     2
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK                                      0x00000004U
+
+/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
+
+/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
+#undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 
+#undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 
+#undef UART0_BAUD_RATE_GEN_REG0_CD_MASK 
+#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
+#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
+#define UART0_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
+
+/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
+#undef UART0_CONTROL_REG0_STPBRK_DEFVAL 
+#undef UART0_CONTROL_REG0_STPBRK_SHIFT 
+#undef UART0_CONTROL_REG0_STPBRK_MASK 
+#define UART0_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
+#define UART0_CONTROL_REG0_STPBRK_SHIFT                                            8
+#define UART0_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
+
+/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
+#undef UART0_CONTROL_REG0_STTBRK_DEFVAL 
+#undef UART0_CONTROL_REG0_STTBRK_SHIFT 
+#undef UART0_CONTROL_REG0_STTBRK_MASK 
+#define UART0_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
+#define UART0_CONTROL_REG0_STTBRK_SHIFT                                            7
+#define UART0_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
+
+/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.*/
+#undef UART0_CONTROL_REG0_RSTTO_DEFVAL 
+#undef UART0_CONTROL_REG0_RSTTO_SHIFT 
+#undef UART0_CONTROL_REG0_RSTTO_MASK 
+#define UART0_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RSTTO_SHIFT                                             6
+#define UART0_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
+
+/*Transmit disable: 0: enable transmitter 1: disable transmitter*/
+#undef UART0_CONTROL_REG0_TXDIS_DEFVAL 
+#undef UART0_CONTROL_REG0_TXDIS_SHIFT 
+#undef UART0_CONTROL_REG0_TXDIS_MASK 
+#define UART0_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_TXDIS_SHIFT                                             5
+#define UART0_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
+
+/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
+#undef UART0_CONTROL_REG0_TXEN_DEFVAL 
+#undef UART0_CONTROL_REG0_TXEN_SHIFT 
+#undef UART0_CONTROL_REG0_TXEN_MASK 
+#define UART0_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
+#define UART0_CONTROL_REG0_TXEN_SHIFT                                              4
+#define UART0_CONTROL_REG0_TXEN_MASK                                               0x00000010U
+
+/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
+#undef UART0_CONTROL_REG0_RXDIS_DEFVAL 
+#undef UART0_CONTROL_REG0_RXDIS_SHIFT 
+#undef UART0_CONTROL_REG0_RXDIS_MASK 
+#define UART0_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RXDIS_SHIFT                                             3
+#define UART0_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
+
+/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
+#undef UART0_CONTROL_REG0_RXEN_DEFVAL 
+#undef UART0_CONTROL_REG0_RXEN_SHIFT 
+#undef UART0_CONTROL_REG0_RXEN_MASK 
+#define UART0_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
+#define UART0_CONTROL_REG0_RXEN_SHIFT                                              2
+#define UART0_CONTROL_REG0_RXEN_MASK                                               0x00000004U
+
+/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.*/
+#undef UART0_CONTROL_REG0_TXRES_DEFVAL 
+#undef UART0_CONTROL_REG0_TXRES_SHIFT 
+#undef UART0_CONTROL_REG0_TXRES_MASK 
+#define UART0_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_TXRES_SHIFT                                             1
+#define UART0_CONTROL_REG0_TXRES_MASK                                              0x00000002U
+
+/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.*/
+#undef UART0_CONTROL_REG0_RXRES_DEFVAL 
+#undef UART0_CONTROL_REG0_RXRES_SHIFT 
+#undef UART0_CONTROL_REG0_RXRES_MASK 
+#define UART0_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RXRES_SHIFT                                             0
+#define UART0_CONTROL_REG0_RXRES_MASK                                              0x00000001U
+
+/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
+#undef UART0_MODE_REG0_CHMODE_DEFVAL 
+#undef UART0_MODE_REG0_CHMODE_SHIFT 
+#undef UART0_MODE_REG0_CHMODE_MASK 
+#define UART0_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
+#define UART0_MODE_REG0_CHMODE_SHIFT                                               8
+#define UART0_MODE_REG0_CHMODE_MASK                                                0x00000300U
+
+/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved*/
+#undef UART0_MODE_REG0_NBSTOP_DEFVAL 
+#undef UART0_MODE_REG0_NBSTOP_SHIFT 
+#undef UART0_MODE_REG0_NBSTOP_MASK 
+#define UART0_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
+#define UART0_MODE_REG0_NBSTOP_SHIFT                                               6
+#define UART0_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
+
+/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
+#undef UART0_MODE_REG0_PAR_DEFVAL 
+#undef UART0_MODE_REG0_PAR_SHIFT 
+#undef UART0_MODE_REG0_PAR_MASK 
+#define UART0_MODE_REG0_PAR_DEFVAL                                                 0x00000000
+#define UART0_MODE_REG0_PAR_SHIFT                                                  3
+#define UART0_MODE_REG0_PAR_MASK                                                   0x00000038U
+
+/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
+#undef UART0_MODE_REG0_CHRL_DEFVAL 
+#undef UART0_MODE_REG0_CHRL_SHIFT 
+#undef UART0_MODE_REG0_CHRL_MASK 
+#define UART0_MODE_REG0_CHRL_DEFVAL                                                0x00000000
+#define UART0_MODE_REG0_CHRL_SHIFT                                                 1
+#define UART0_MODE_REG0_CHRL_MASK                                                  0x00000006U
+
+/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
+#undef UART0_MODE_REG0_CLKS_DEFVAL 
+#undef UART0_MODE_REG0_CLKS_SHIFT 
+#undef UART0_MODE_REG0_CLKS_MASK 
+#define UART0_MODE_REG0_CLKS_DEFVAL                                                0x00000000
+#define UART0_MODE_REG0_CLKS_SHIFT                                                 0
+#define UART0_MODE_REG0_CLKS_MASK                                                  0x00000001U
+
+/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
+
+/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
+#undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 
+#undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 
+#undef UART1_BAUD_RATE_GEN_REG0_CD_MASK 
+#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
+#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
+#define UART1_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
+
+/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
+#undef UART1_CONTROL_REG0_STPBRK_DEFVAL 
+#undef UART1_CONTROL_REG0_STPBRK_SHIFT 
+#undef UART1_CONTROL_REG0_STPBRK_MASK 
+#define UART1_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
+#define UART1_CONTROL_REG0_STPBRK_SHIFT                                            8
+#define UART1_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
+
+/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
+#undef UART1_CONTROL_REG0_STTBRK_DEFVAL 
+#undef UART1_CONTROL_REG0_STTBRK_SHIFT 
+#undef UART1_CONTROL_REG0_STTBRK_MASK 
+#define UART1_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
+#define UART1_CONTROL_REG0_STTBRK_SHIFT                                            7
+#define UART1_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
+
+/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.*/
+#undef UART1_CONTROL_REG0_RSTTO_DEFVAL 
+#undef UART1_CONTROL_REG0_RSTTO_SHIFT 
+#undef UART1_CONTROL_REG0_RSTTO_MASK 
+#define UART1_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RSTTO_SHIFT                                             6
+#define UART1_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
+
+/*Transmit disable: 0: enable transmitter 1: disable transmitter*/
+#undef UART1_CONTROL_REG0_TXDIS_DEFVAL 
+#undef UART1_CONTROL_REG0_TXDIS_SHIFT 
+#undef UART1_CONTROL_REG0_TXDIS_MASK 
+#define UART1_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_TXDIS_SHIFT                                             5
+#define UART1_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
+
+/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
+#undef UART1_CONTROL_REG0_TXEN_DEFVAL 
+#undef UART1_CONTROL_REG0_TXEN_SHIFT 
+#undef UART1_CONTROL_REG0_TXEN_MASK 
+#define UART1_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
+#define UART1_CONTROL_REG0_TXEN_SHIFT                                              4
+#define UART1_CONTROL_REG0_TXEN_MASK                                               0x00000010U
+
+/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
+#undef UART1_CONTROL_REG0_RXDIS_DEFVAL 
+#undef UART1_CONTROL_REG0_RXDIS_SHIFT 
+#undef UART1_CONTROL_REG0_RXDIS_MASK 
+#define UART1_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RXDIS_SHIFT                                             3
+#define UART1_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
+
+/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
+#undef UART1_CONTROL_REG0_RXEN_DEFVAL 
+#undef UART1_CONTROL_REG0_RXEN_SHIFT 
+#undef UART1_CONTROL_REG0_RXEN_MASK 
+#define UART1_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
+#define UART1_CONTROL_REG0_RXEN_SHIFT                                              2
+#define UART1_CONTROL_REG0_RXEN_MASK                                               0x00000004U
+
+/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.*/
+#undef UART1_CONTROL_REG0_TXRES_DEFVAL 
+#undef UART1_CONTROL_REG0_TXRES_SHIFT 
+#undef UART1_CONTROL_REG0_TXRES_MASK 
+#define UART1_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_TXRES_SHIFT                                             1
+#define UART1_CONTROL_REG0_TXRES_MASK                                              0x00000002U
+
+/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.*/
+#undef UART1_CONTROL_REG0_RXRES_DEFVAL 
+#undef UART1_CONTROL_REG0_RXRES_SHIFT 
+#undef UART1_CONTROL_REG0_RXRES_MASK 
+#define UART1_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RXRES_SHIFT                                             0
+#define UART1_CONTROL_REG0_RXRES_MASK                                              0x00000001U
+
+/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
+#undef UART1_MODE_REG0_CHMODE_DEFVAL 
+#undef UART1_MODE_REG0_CHMODE_SHIFT 
+#undef UART1_MODE_REG0_CHMODE_MASK 
+#define UART1_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
+#define UART1_MODE_REG0_CHMODE_SHIFT                                               8
+#define UART1_MODE_REG0_CHMODE_MASK                                                0x00000300U
+
+/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved*/
+#undef UART1_MODE_REG0_NBSTOP_DEFVAL 
+#undef UART1_MODE_REG0_NBSTOP_SHIFT 
+#undef UART1_MODE_REG0_NBSTOP_MASK 
+#define UART1_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
+#define UART1_MODE_REG0_NBSTOP_SHIFT                                               6
+#define UART1_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
+
+/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
+#undef UART1_MODE_REG0_PAR_DEFVAL 
+#undef UART1_MODE_REG0_PAR_SHIFT 
+#undef UART1_MODE_REG0_PAR_MASK 
+#define UART1_MODE_REG0_PAR_DEFVAL                                                 0x00000000
+#define UART1_MODE_REG0_PAR_SHIFT                                                  3
+#define UART1_MODE_REG0_PAR_MASK                                                   0x00000038U
+
+/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
+#undef UART1_MODE_REG0_CHRL_DEFVAL 
+#undef UART1_MODE_REG0_CHRL_SHIFT 
+#undef UART1_MODE_REG0_CHRL_MASK 
+#define UART1_MODE_REG0_CHRL_DEFVAL                                                0x00000000
+#define UART1_MODE_REG0_CHRL_SHIFT                                                 1
+#define UART1_MODE_REG0_CHRL_MASK                                                  0x00000006U
+
+/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
+#undef UART1_MODE_REG0_CLKS_DEFVAL 
+#undef UART1_MODE_REG0_CLKS_SHIFT 
+#undef UART1_MODE_REG0_CLKS_MASK 
+#define UART1_MODE_REG0_CLKS_DEFVAL                                                0x00000000
+#define UART1_MODE_REG0_CLKS_SHIFT                                                 0
+#define UART1_MODE_REG0_CLKS_MASK                                                  0x00000001U
+
+/*TrustZone Classification for ADMA*/
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL 
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL                                        
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT                                         0
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK                                          0x000000FFU
+
+/*CSU regsiter*/
+#undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_0_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT                                           0
+#define CSU_TAMPER_STATUS_TAMPER_0_MASK                                            0x00000001U
+
+/*External MIO*/
+#undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_1_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT                                           1
+#define CSU_TAMPER_STATUS_TAMPER_1_MASK                                            0x00000002U
+
+/*JTAG toggle detect*/
+#undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_2_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT                                           2
+#define CSU_TAMPER_STATUS_TAMPER_2_MASK                                            0x00000004U
+
+/*PL SEU error*/
+#undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_3_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT                                           3
+#define CSU_TAMPER_STATUS_TAMPER_3_MASK                                            0x00000008U
+
+/*AMS over temperature alarm for LPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_4_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT                                           4
+#define CSU_TAMPER_STATUS_TAMPER_4_MASK                                            0x00000010U
+
+/*AMS over temperature alarm for APU*/
+#undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_5_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT                                           5
+#define CSU_TAMPER_STATUS_TAMPER_5_MASK                                            0x00000020U
+
+/*AMS voltage alarm for VCCPINT_FPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_6_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT                                           6
+#define CSU_TAMPER_STATUS_TAMPER_6_MASK                                            0x00000040U
+
+/*AMS voltage alarm for VCCPINT_LPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_7_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT                                           7
+#define CSU_TAMPER_STATUS_TAMPER_7_MASK                                            0x00000080U
+
+/*AMS voltage alarm for VCCPAUX*/
+#undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_8_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT                                           8
+#define CSU_TAMPER_STATUS_TAMPER_8_MASK                                            0x00000100U
+
+/*AMS voltage alarm for DDRPHY*/
+#undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_9_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT                                           9
+#define CSU_TAMPER_STATUS_TAMPER_9_MASK                                            0x00000200U
+
+/*AMS voltage alarm for PSIO bank 0/1/2*/
+#undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_10_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT                                          10
+#define CSU_TAMPER_STATUS_TAMPER_10_MASK                                           0x00000400U
+
+/*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/
+#undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_11_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT                                          11
+#define CSU_TAMPER_STATUS_TAMPER_11_MASK                                           0x00000800U
+
+/*AMS voltaage alarm for GT*/
+#undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_12_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT                                          12
+#define CSU_TAMPER_STATUS_TAMPER_12_MASK                                           0x00001000U
+
+/*Set ACE outgoing AWQOS value*/
+#undef APU_ACE_CTRL_AWQOS_DEFVAL 
+#undef APU_ACE_CTRL_AWQOS_SHIFT 
+#undef APU_ACE_CTRL_AWQOS_MASK 
+#define APU_ACE_CTRL_AWQOS_DEFVAL                                                  0x000F000F
+#define APU_ACE_CTRL_AWQOS_SHIFT                                                   16
+#define APU_ACE_CTRL_AWQOS_MASK                                                    0x000F0000U
+
+/*Set ACE outgoing ARQOS value*/
+#undef APU_ACE_CTRL_ARQOS_DEFVAL 
+#undef APU_ACE_CTRL_ARQOS_SHIFT 
+#undef APU_ACE_CTRL_ARQOS_MASK 
+#define APU_ACE_CTRL_ARQOS_DEFVAL                                                  0x000F000F
+#define APU_ACE_CTRL_ARQOS_SHIFT                                                   0
+#define APU_ACE_CTRL_ARQOS_MASK                                                    0x0000000FU
+
+/*Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from 
+		he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
+		pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
+		g a 0 to this bit.*/
+#undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL 
+#undef RTC_CONTROL_BATTERY_DISABLE_SHIFT 
+#undef RTC_CONTROL_BATTERY_DISABLE_MASK 
+#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL                                         0x01000000
+#define RTC_CONTROL_BATTERY_DISABLE_SHIFT                                          31
+#define RTC_CONTROL_BATTERY_DISABLE_MASK                                           0x80000000U
+#undef SERDES_PLL_REF_SEL0_OFFSET 
+#define SERDES_PLL_REF_SEL0_OFFSET                                                 0XFD410000
+#undef SERDES_PLL_REF_SEL1_OFFSET 
+#define SERDES_PLL_REF_SEL1_OFFSET                                                 0XFD410004
+#undef SERDES_PLL_REF_SEL2_OFFSET 
+#define SERDES_PLL_REF_SEL2_OFFSET                                                 0XFD410008
+#undef SERDES_PLL_REF_SEL3_OFFSET 
+#define SERDES_PLL_REF_SEL3_OFFSET                                                 0XFD41000C
+#undef SERDES_L0_L0_REF_CLK_SEL_OFFSET 
+#define SERDES_L0_L0_REF_CLK_SEL_OFFSET                                            0XFD402860
+#undef SERDES_L0_L1_REF_CLK_SEL_OFFSET 
+#define SERDES_L0_L1_REF_CLK_SEL_OFFSET                                            0XFD402864
+#undef SERDES_L0_L2_REF_CLK_SEL_OFFSET 
+#define SERDES_L0_L2_REF_CLK_SEL_OFFSET                                            0XFD402868
+#undef SERDES_L0_L3_REF_CLK_SEL_OFFSET 
+#define SERDES_L0_L3_REF_CLK_SEL_OFFSET                                            0XFD40286C
+#undef SERDES_L2_TM_PLL_DIG_37_OFFSET 
+#define SERDES_L2_TM_PLL_DIG_37_OFFSET                                             0XFD40A094
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET 
+#define SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40A368
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET 
+#define SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40A36C
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET 
+#define SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40E368
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET 
+#define SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40E36C
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET 
+#define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD406368
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET 
+#define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40636C
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
+#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD406370
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET 
+#define SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD406374
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET 
+#define SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD406378
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40637C
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
+#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40A370
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET 
+#define SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40A374
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET 
+#define SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40A378
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40A37C
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
+#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40E370
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET 
+#define SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40E374
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET 
+#define SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40E378
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40E37C
+#undef SERDES_L2_TM_DIG_6_OFFSET 
+#define SERDES_L2_TM_DIG_6_OFFSET                                                  0XFD40906C
+#undef SERDES_L2_TX_DIG_TM_61_OFFSET 
+#define SERDES_L2_TX_DIG_TM_61_OFFSET                                              0XFD4080F4
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET 
+#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET                                      0XFD40E360
+#undef SERDES_L3_TM_DIG_6_OFFSET 
+#define SERDES_L3_TM_DIG_6_OFFSET                                                  0XFD40D06C
+#undef SERDES_L3_TX_DIG_TM_61_OFFSET 
+#define SERDES_L3_TX_DIG_TM_61_OFFSET                                              0XFD40C0F4
+#undef SERDES_L3_TXPMA_ST_0_OFFSET 
+#define SERDES_L3_TXPMA_ST_0_OFFSET                                                0XFD40CB00
+#undef SERDES_ICM_CFG0_OFFSET 
+#define SERDES_ICM_CFG0_OFFSET                                                     0XFD410010
+#undef SERDES_ICM_CFG1_OFFSET 
+#define SERDES_ICM_CFG1_OFFSET                                                     0XFD410014
+#undef SERDES_L1_TXPMD_TM_45_OFFSET 
+#define SERDES_L1_TXPMD_TM_45_OFFSET                                               0XFD404CB4
+#undef SERDES_L1_TX_ANA_TM_118_OFFSET 
+#define SERDES_L1_TX_ANA_TM_118_OFFSET                                             0XFD4041D8
+#undef SERDES_L1_TXPMD_TM_48_OFFSET 
+#define SERDES_L1_TXPMD_TM_48_OFFSET                                               0XFD404CC0
+#undef SERDES_L1_TX_ANA_TM_18_OFFSET 
+#define SERDES_L1_TX_ANA_TM_18_OFFSET                                              0XFD404048
+
+/*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
+#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 
+#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 
+#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 
+#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL                                      0x0000000D
+#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT                                       0
+#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK                                        0x0000001FU
+
+/*PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
+#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 
+#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 
+#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 
+#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL                                      0x00000008
+#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT                                       0
+#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK                                        0x0000001FU
+
+/*PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
+#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 
+#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 
+#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 
+#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL                                      0x0000000F
+#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT                                       0
+#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK                                        0x0000001FU
+
+/*PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
+#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 
+#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 
+#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 
+#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL                                      0x0000000E
+#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT                                       0
+#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK                                        0x0000001FU
+
+/*Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.*/
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 
+#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
+#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT                          7
+#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK                           0x00000080U
+
+/*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT                          7
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK                           0x00000080U
+
+/*Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL                           0x00000080
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT                            3
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK                             0x00000008U
+
+/*Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.*/
+#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 
+#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 
+#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 
+#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
+#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT                          7
+#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK                           0x00000080U
+
+/*Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.*/
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT                          7
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK                           0x00000080U
+
+/*Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network*/
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL                           0x00000080
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT                            1
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK                             0x00000002U
+
+/*Enable/Disable coarse code satureation limiting logic*/
+#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 
+#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 
+#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 
+#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL                 0x00000000
+#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT                  4
+#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK                   0x00000010U
+
+/*Spread Spectrum No of Steps [7:0]*/
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
+#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
+#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
+#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
+
+/*Spread Spectrum No of Steps [10:8]*/
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
+#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
+#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
+#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
+
+/*Spread Spectrum No of Steps [7:0]*/
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
+#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
+#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
+#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
+
+/*Spread Spectrum No of Steps [10:8]*/
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
+#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
+#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
+#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
+
+/*Spread Spectrum No of Steps [7:0]*/
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
+#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
+#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
+#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
+
+/*Spread Spectrum No of Steps [10:8]*/
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
+#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
+#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
+#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
+
+/*Step Size for Spread Spectrum [7:0]*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
+#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
+
+/*Step Size for Spread Spectrum [15:8]*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
+#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [23:16]*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
+#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [25:24]*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
+
+/*Enable/Disable test mode force on SS step size*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
+
+/*Enable/Disable test mode force on SS no of steps*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
+
+/*Step Size for Spread Spectrum [7:0]*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
+#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
+
+/*Step Size for Spread Spectrum [15:8]*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
+#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [23:16]*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
+#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [25:24]*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
+
+/*Enable/Disable test mode force on SS step size*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
+
+/*Enable/Disable test mode force on SS no of steps*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
+
+/*Step Size for Spread Spectrum [7:0]*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
+#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
+
+/*Step Size for Spread Spectrum [15:8]*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
+#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [23:16]*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
+#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [25:24]*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
+
+/*Enable/Disable test mode force on SS step size*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
+
+/*Enable/Disable test mode force on SS no of steps*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
+
+/*Enable test mode forcing on enable Spread Spectrum*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL                     0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT                      7
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK                       0x00000080U
+
+/*Bypass Descrambler*/
+#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 
+#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 
+#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 
+#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL                                   0x00000000
+#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT                                    1
+#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK                                     0x00000002U
+
+/*Enable Bypass for <1> TM_DIG_CTRL_6*/
+#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 
+#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 
+#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 
+#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL                             0x00000000
+#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT                              0
+#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK                               0x00000001U
+
+/*Bypass scrambler signal*/
+#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 
+#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 
+#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 
+#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL                                 0x00000000
+#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT                                  1
+#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK                                   0x00000002U
+
+/*Enable/disable scrambler bypass signal*/
+#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 
+#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 
+#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 
+#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL                           0x00000000
+#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT                            0
+#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK                             0x00000001U
+
+/*Enable test mode force on fractional mode enable*/
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 
+#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL                     0x00000000
+#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT                      6
+#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK                       0x00000040U
+
+/*Bypass 8b10b decoder*/
+#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 
+#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 
+#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 
+#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL                                   0x00000000
+#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT                                    3
+#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK                                     0x00000008U
+
+/*Enable Bypass for <3> TM_DIG_CTRL_6*/
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL                                 0x00000000
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT                                  2
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK                                   0x00000004U
+
+/*Bypass Descrambler*/
+#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 
+#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 
+#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 
+#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL                                   0x00000000
+#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT                                    1
+#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK                                     0x00000002U
+
+/*Enable Bypass for <1> TM_DIG_CTRL_6*/
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL                             0x00000000
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT                              0
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK                               0x00000001U
+
+/*Enable/disable encoder bypass signal*/
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL                                   0x00000000
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT                                    3
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK                                     0x00000008U
+
+/*Bypass scrambler signal*/
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL                                 0x00000000
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT                                  1
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK                                   0x00000002U
+
+/*Enable/disable scrambler bypass signal*/
+#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 
+#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 
+#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 
+#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL                           0x00000000
+#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT                            0
+#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK                             0x00000001U
+
+/*PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY*/
+#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL 
+#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT 
+#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK 
+#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL                                    0x00000001
+#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT                                     4
+#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK                                      0x000000F0U
+
+/*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
+		, 7 - Unused*/
+#undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 
+#undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 
+#undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK 
+#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL                                          0x00000000
+#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT                                           0
+#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK                                            0x00000007U
+
+/*Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
+		 7 - Unused*/
+#undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 
+#undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 
+#undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK 
+#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL                                          0x00000000
+#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT                                           4
+#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK                                            0x00000070U
+
+/*Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
+		 7 - Unused*/
+#undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 
+#undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 
+#undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK 
+#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL                                          0x00000000
+#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT                                           0
+#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK                                            0x00000007U
+
+/*Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
+		 7 - Unused*/
+#undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 
+#undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 
+#undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK 
+#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL                                          0x00000000
+#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT                                           4
+#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK                                            0x00000070U
+
+/*Enable/disable DP post2 path*/
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL                 0x00000000
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT                  5
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK                   0x00000020U
+
+/*Override enable/disable of DP post2 path*/
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL            0x00000000
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT             4
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK              0x00000010U
+
+/*Override enable/disable of DP post1 path*/
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL            0x00000000
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT             2
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK              0x00000004U
+
+/*Enable/disable DP main path*/
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL                  0x00000000
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT                   1
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK                    0x00000002U
+
+/*Override enable/disable of DP main path*/
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL             0x00000000
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT              0
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK               0x00000001U
+
+/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
+#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 
+#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 
+#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 
+#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL                        0x00000000
+#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT                         0
+#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK                          0x00000001U
+
+/*Margining factor value*/
+#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 
+#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 
+#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL                 0x00000000
+#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT                  0
+#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK                   0x0000001FU
+
+/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
+#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 
+#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 
+#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 
+#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL                           0x00000002
+#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT                            0
+#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK                             0x000000FFU
+#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
+#undef USB3_0_FPD_POWER_PRSNT_OFFSET 
+#define USB3_0_FPD_POWER_PRSNT_OFFSET                                              0XFF9D0080
+#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
+#undef CRL_APB_RST_LPD_IOU0_OFFSET 
+#define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
+#undef SIOU_SATA_MISC_CTRL_OFFSET 
+#define SIOU_SATA_MISC_CTRL_OFFSET                                                 0XFD3D0100
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef DP_DP_PHY_RESET_OFFSET 
+#define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
+#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET 
+#define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
+#undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET 
+#define USB3_0_XHCI_GUSB2PHYCFG_OFFSET                                             0XFE20C200
+#undef USB3_0_XHCI_GFLADJ_OFFSET 
+#define USB3_0_XHCI_GFLADJ_OFFSET                                                  0XFE20C630
+#undef PCIE_ATTRIB_ATTR_37_OFFSET 
+#define PCIE_ATTRIB_ATTR_37_OFFSET                                                 0XFD480094
+#undef PCIE_ATTRIB_ATTR_25_OFFSET 
+#define PCIE_ATTRIB_ATTR_25_OFFSET                                                 0XFD480064
+#undef PCIE_ATTRIB_ATTR_7_OFFSET 
+#define PCIE_ATTRIB_ATTR_7_OFFSET                                                  0XFD48001C
+#undef PCIE_ATTRIB_ATTR_8_OFFSET 
+#define PCIE_ATTRIB_ATTR_8_OFFSET                                                  0XFD480020
+#undef PCIE_ATTRIB_ATTR_9_OFFSET 
+#define PCIE_ATTRIB_ATTR_9_OFFSET                                                  0XFD480024
+#undef PCIE_ATTRIB_ATTR_10_OFFSET 
+#define PCIE_ATTRIB_ATTR_10_OFFSET                                                 0XFD480028
+#undef PCIE_ATTRIB_ATTR_11_OFFSET 
+#define PCIE_ATTRIB_ATTR_11_OFFSET                                                 0XFD48002C
+#undef PCIE_ATTRIB_ATTR_12_OFFSET 
+#define PCIE_ATTRIB_ATTR_12_OFFSET                                                 0XFD480030
+#undef PCIE_ATTRIB_ATTR_13_OFFSET 
+#define PCIE_ATTRIB_ATTR_13_OFFSET                                                 0XFD480034
+#undef PCIE_ATTRIB_ATTR_14_OFFSET 
+#define PCIE_ATTRIB_ATTR_14_OFFSET                                                 0XFD480038
+#undef PCIE_ATTRIB_ATTR_15_OFFSET 
+#define PCIE_ATTRIB_ATTR_15_OFFSET                                                 0XFD48003C
+#undef PCIE_ATTRIB_ATTR_16_OFFSET 
+#define PCIE_ATTRIB_ATTR_16_OFFSET                                                 0XFD480040
+#undef PCIE_ATTRIB_ATTR_17_OFFSET 
+#define PCIE_ATTRIB_ATTR_17_OFFSET                                                 0XFD480044
+#undef PCIE_ATTRIB_ATTR_18_OFFSET 
+#define PCIE_ATTRIB_ATTR_18_OFFSET                                                 0XFD480048
+#undef PCIE_ATTRIB_ATTR_27_OFFSET 
+#define PCIE_ATTRIB_ATTR_27_OFFSET                                                 0XFD48006C
+#undef PCIE_ATTRIB_ATTR_50_OFFSET 
+#define PCIE_ATTRIB_ATTR_50_OFFSET                                                 0XFD4800C8
+#undef PCIE_ATTRIB_ATTR_105_OFFSET 
+#define PCIE_ATTRIB_ATTR_105_OFFSET                                                0XFD4801A4
+#undef PCIE_ATTRIB_ATTR_106_OFFSET 
+#define PCIE_ATTRIB_ATTR_106_OFFSET                                                0XFD4801A8
+#undef PCIE_ATTRIB_ATTR_107_OFFSET 
+#define PCIE_ATTRIB_ATTR_107_OFFSET                                                0XFD4801AC
+#undef PCIE_ATTRIB_ATTR_108_OFFSET 
+#define PCIE_ATTRIB_ATTR_108_OFFSET                                                0XFD4801B0
+#undef PCIE_ATTRIB_ATTR_109_OFFSET 
+#define PCIE_ATTRIB_ATTR_109_OFFSET                                                0XFD4801B4
+#undef PCIE_ATTRIB_ATTR_34_OFFSET 
+#define PCIE_ATTRIB_ATTR_34_OFFSET                                                 0XFD480088
+#undef PCIE_ATTRIB_ATTR_53_OFFSET 
+#define PCIE_ATTRIB_ATTR_53_OFFSET                                                 0XFD4800D4
+#undef PCIE_ATTRIB_ATTR_41_OFFSET 
+#define PCIE_ATTRIB_ATTR_41_OFFSET                                                 0XFD4800A4
+#undef PCIE_ATTRIB_ATTR_97_OFFSET 
+#define PCIE_ATTRIB_ATTR_97_OFFSET                                                 0XFD480184
+#undef PCIE_ATTRIB_ATTR_100_OFFSET 
+#define PCIE_ATTRIB_ATTR_100_OFFSET                                                0XFD480190
+#undef PCIE_ATTRIB_ATTR_101_OFFSET 
+#define PCIE_ATTRIB_ATTR_101_OFFSET                                                0XFD480194
+#undef PCIE_ATTRIB_ATTR_37_OFFSET 
+#define PCIE_ATTRIB_ATTR_37_OFFSET                                                 0XFD480094
+#undef PCIE_ATTRIB_ATTR_93_OFFSET 
+#define PCIE_ATTRIB_ATTR_93_OFFSET                                                 0XFD480174
+#undef PCIE_ATTRIB_ID_OFFSET 
+#define PCIE_ATTRIB_ID_OFFSET                                                      0XFD480200
+#undef PCIE_ATTRIB_SUBSYS_ID_OFFSET 
+#define PCIE_ATTRIB_SUBSYS_ID_OFFSET                                               0XFD480204
+#undef PCIE_ATTRIB_REV_ID_OFFSET 
+#define PCIE_ATTRIB_REV_ID_OFFSET                                                  0XFD480208
+#undef PCIE_ATTRIB_ATTR_24_OFFSET 
+#define PCIE_ATTRIB_ATTR_24_OFFSET                                                 0XFD480060
+#undef PCIE_ATTRIB_ATTR_25_OFFSET 
+#define PCIE_ATTRIB_ATTR_25_OFFSET                                                 0XFD480064
+#undef PCIE_ATTRIB_ATTR_4_OFFSET 
+#define PCIE_ATTRIB_ATTR_4_OFFSET                                                  0XFD480010
+#undef PCIE_ATTRIB_ATTR_89_OFFSET 
+#define PCIE_ATTRIB_ATTR_89_OFFSET                                                 0XFD480164
+#undef PCIE_ATTRIB_ATTR_79_OFFSET 
+#define PCIE_ATTRIB_ATTR_79_OFFSET                                                 0XFD48013C
+#undef PCIE_ATTRIB_ATTR_43_OFFSET 
+#define PCIE_ATTRIB_ATTR_43_OFFSET                                                 0XFD4800AC
+
+/*USB 0 reset for control registers*/
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
+
+/*This bit is used to choose between PIPE power present and 1'b1*/
+#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL 
+#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 
+#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK 
+#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL                                       
+#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT                                        0
+#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK                                         0x00000001U
+
+/*USB 0 sleep circuit reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
+
+/*USB 0 reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
+
+/*GEM 3 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
+
+/*Sata PM clock control select*/
+#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL 
+#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 
+#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 
+#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL                                 
+#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT                                  0
+#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK                                   0x00000003U
+
+/*Sata block level reset*/
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
+
+/*PCIE config reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL                                  0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT                                   19
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                                    0x00080000U
+
+/*PCIE control block level reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL                                 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT                                  17
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK                                   0x00020000U
+
+/*PCIE bridge block level reset (AXI interface)*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL                               0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT                                18
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK                                 0x00040000U
+
+/*Display Port block level reset (includes DPDMA)*/
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
+#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
+
+/*Set to '1' to hold the GT in reset. Clear to release.*/
+#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL 
+#undef DP_DP_PHY_RESET_GT_RESET_SHIFT 
+#undef DP_DP_PHY_RESET_GT_RESET_MASK 
+#define DP_DP_PHY_RESET_GT_RESET_DEFVAL                                            0x00010003
+#define DP_DP_PHY_RESET_GT_RESET_SHIFT                                             1
+#define DP_DP_PHY_RESET_GT_RESET_MASK                                              0x00000002U
+
+/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 
+		ane0 Bits [3:2] - lane 1*/
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL                                   0x00000000
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                                    0
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                                     0x0000000FU
+
+/*USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to 
+		he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
+		C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
+		. The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
+		UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger 
+		alue. Note: This field is valid only in device mode.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL                                   0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT                                    10
+#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK                                     0x00003C00U
+
+/*Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
+		 of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
+		time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
+		ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
+		off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
+		ng hibernation. - This bit is valid only in device mode.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL                                     0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT                                      9
+#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK                                       0x00000200U
+
+/*Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
+		_n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
+		 to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. 
+		ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
+		n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
+		d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
+		d.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL                                    0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT                                     8
+#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK                                      0x00000100U
+
+/*USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
+		Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - 
+		'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
+		 in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
+		 active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL                                      0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT                                       7
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK                                        0x00000080U
+
+/*Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
+		figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
+		ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
+		r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
+		t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
+		g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
+		 when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL                                0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT                                 6
+#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK                                  0x00000040U
+
+/*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
+		full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with 
+		ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
+		B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL                                      0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT                                       5
+#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK                                        0x00000020U
+
+/*ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
+		e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
+		ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
+		lected through DWC_USB3_HSPHY_INTERFACE.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL                               0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT                                4
+#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK                                 0x00000010U
+
+/*PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
+		 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same 
+		lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
+		 ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
+		 any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL                                       0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT                                        3
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK                                         0x00000008U
+
+/*HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
+		a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for 
+		dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
+		e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
+		The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this 
+		ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
+		 clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
+		60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL                                     0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT                                      0
+#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK                                       0x00000007U
+
+/*This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register 
+		alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
+		_SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
+		TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
+		riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
+		cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
+		uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
+		((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
+		RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)*/
+#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 
+#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 
+#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 
+#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL                              0x00000000
+#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT                               8
+#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK                                0x003FFF00U
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
+#define SERDES_L0_PLL_STATUS_READ_1_OFFSET                                         0XFD4023E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
+#define SERDES_L1_PLL_STATUS_READ_1_OFFSET                                         0XFD4063E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
+#define SERDES_L2_PLL_STATUS_READ_1_OFFSET                                         0XFD40A3E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
+#define SERDES_L3_PLL_STATUS_READ_1_OFFSET                                         0XFD40E3E4
+
+/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
+		gister.; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL                  0x000009FF
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT                   14
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK                    0x00004000U
+
+/*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
+		ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 
+#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL              0x00000905
+#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT               9
+#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK                0x00000200U
+
+/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
+		ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
+		Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
+		erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 
+		set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
+		re size in bytes.; EP=0x0004; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 
+#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 
+#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL                                        
+#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT                                         0
+#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK                                          0x0000FFFFU
+
+/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
+		ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
+		Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
+		erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 
+		set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
+		re size in bytes.; EP=0xFFF0; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 
+#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 
+#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL                                        
+#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT                                         0
+#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK                                          0x0000FFFFU
+
+/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 
+		AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
+		 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 
+		o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
+		32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 
+		'7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
+		ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 
+#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 
+#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL                                        
+#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT                                         0
+#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK                                          0x0000FFFFU
+
+/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 
+		AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
+		 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 
+		o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
+		32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 
+		'7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
+		ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 
+#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 
+#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
+		AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF*/
+#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 
+#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 
+#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
+		AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF*/
+#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 
+#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 
+#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
+		AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
+		 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
+		t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
+		t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
+		if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 
+		f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
+		 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 
+#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 
+#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
+		AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
+		 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
+		t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
+		t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
+		if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 
+		f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
+		 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF*/
+#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 
+#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 
+#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
+		AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0*/
+#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 
+#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 
+#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
+		AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0*/
+#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 
+#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 
+#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
+		AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
+		Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 
+		refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
+		R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 
+		refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 
+		ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
+		permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/
+#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 
+#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 
+#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
+		AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
+		Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 
+		refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
+		R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 
+		refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 
+		ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
+		permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/
+#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 
+#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 
+#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK                                         0x0000FFFFU
+
+/*Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
+		to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL              0x00002138
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT               8
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK                0x00000700U
+
+/*Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
+		state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
+		 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL                0x00002138
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT                 3
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK                  0x00000038U
+
+/*Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
+		00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
+		tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
+		gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004*/
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL                  0x00009C02
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT                   4
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK                    0x000000F0U
+
+/*PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
+		lity.; EP=0x009C; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL                           0x00009C02
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT                            8
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK                             0x0000FF00U
+
+/*Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
+		ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD*/
+#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 
+#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 
+#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL                      
+#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT                       0
+#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK                        0x000007FFU
+
+/*Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non 
+		osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024*/
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL                      0x00000248
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT                       0
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK                        0x0000007FU
+
+/*Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
+		a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
+		completion header credits must be <= 80; EP=0x0004; RP=0x000C*/
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL                     0x00000248
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT                      7
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK                       0x00003F80U
+
+/*Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data 
+		redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
+		d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
+		less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018*/
+#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 
+#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 
+#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL                     
+#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT                      0
+#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK                       0x000007FFU
+
+/*Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less 
+		han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5*/
+#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 
+#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 
+#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL                      
+#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT                       0
+#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK                        0x000007FFU
+
+/*Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
+		0*/
+#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 
+#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL                              0x00007E04
+#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT                               15
+#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK                                0x00008000U
+
+/*Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL                            0x00007E04
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT                             14
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK                              0x00004000U
+
+/*Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
+		cap structure; EP=0x0003; RP=0x0003*/
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL                                 0x00007E04
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT                                  12
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK                                   0x00003000U
+
+/*Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
+		mber of brams configured for transmit; EP=0x001C; RP=0x001C*/
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL                         0x00007E04
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT                          7
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK                           0x00000F80U
+
+/*Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
+		d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020*/
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL                      0x00007E04
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT                       0
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK                        0x0000007FU
+
+/*Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
+		0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 
+#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL                                0x00000100
+#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT                                 0
+#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK                                  0x000000FFU
+
+/*PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
+		ty.; EP=0x0048; RP=0x0060*/
+#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 
+#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 
+#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL                             0x00003D48
+#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT                              0
+#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK                               0x000000FFU
+
+/*MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
+		 to Cap structure; EP=0x0000; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL         0x00000160
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT          9
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK           0x00000200U
+
+/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 
+		he management port.; EP=0x0001; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL                                 0x00000160
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT                                  8
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK                                   0x00000100U
+
+/*MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
+		ity.; EP=0x0060; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL                            0x00000160
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT                             0
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK                              0x000000FFU
+
+/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 
+		he management port.; EP=0x0001; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL                                 0x00000160
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT                                  8
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK                                   0x00000100U
+
+/*Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004*/
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 
+#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL                    0x00000104
+#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT                     0
+#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK                      0x0000003FU
+
+/*Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
+		4; RP=0x0004*/
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 
+#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL                       0x00000104
+#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT                        6
+#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK                         0x00000FC0U
+
+/*TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 
+#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 
+#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL                           0x000000F0
+#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT                            6
+#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK                             0x00000040U
+
+/*Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message 
+		LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
+		Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
+		EP=0x0000; RP=0x07FF*/
+#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 
+#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL                          0x00000000
+#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT                           5
+#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK                            0x0000FFE0U
+
+/*Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 
+#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 
+#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL                     0x00000000
+#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT                      1
+#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK                       0x00000002U
+
+/*Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
+		Required for Root.; EP=0x0000; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL   0x000009FF
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT    9
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK     0x00000200U
+
+/*Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
+		_REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL                       0x00000000
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT                        15
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK                         0x00008000U
+
+/*Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
+		TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
+		4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL                          0x00000000
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT                           0
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK                            0x00007FFFU
+
+/*Device ID for the the PCIe Cap Structure Device ID field*/
+#undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 
+#undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 
+#undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 
+#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL                                           0x10EE7024
+#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT                                            0
+#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK                                             0x0000FFFFU
+
+/*Vendor ID for the PCIe Cap Structure Vendor ID field*/
+#undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 
+#undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 
+#undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 
+#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL                                          0x10EE7024
+#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT                                           16
+#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK                                            0xFFFF0000U
+
+/*Subsystem ID for the the PCIe Cap Structure Subsystem ID field*/
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL                                 0x10EE0007
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT                                  0
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK                                   0x0000FFFFU
+
+/*Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field*/
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL                            0x10EE0007
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT                             16
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK                              0xFFFF0000U
+
+/*Revision ID for the the PCIe Cap Structure*/
+#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL 
+#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 
+#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 
+#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL                                       
+#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT                                        0
+#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK                                         0x000000FFU
+
+/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
+		8000; RP=0x8000*/
+#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 
+#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL                                 
+#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT                                  0
+#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK                                   0x0000FFFFU
+
+/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
+		0005; RP=0x0006*/
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 
+#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL                                 0x00000905
+#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT                                  0
+#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK                                   0x000000FFU
+
+/*INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 
+#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL                       0x00000905
+#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT                        8
+#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK                         0x00000100U
+
+/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 
+		he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
+		ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL                                  0x00001000
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT                                   12
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK                                    0x00001000U
+
+/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 
+		he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
+		ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL                                  0x00001000
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT                                   12
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK                                    0x00001000U
+
+/*VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
+		0x0140; RP=0x0140*/
+#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 
+#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 
+#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL                           0x00002281
+#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT                            1
+#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK                             0x00001FFEU
+
+/*CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 
+#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 
+#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL                 0x00000000
+#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT                  5
+#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK                   0x00000020U
+
+/*Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
+		 the management port.; EP=0x0001; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 
+#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 
+#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL                                0x00000100
+#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT                                 8
+#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK                                  0x00000100U
+#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
+#undef CRL_APB_RST_LPD_IOU0_OFFSET 
+#define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET 
+#define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
+#undef DP_DP_PHY_RESET_OFFSET 
+#define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+
+/*USB 0 reset for control registers*/
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
+
+/*USB 0 sleep circuit reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
+
+/*USB 0 reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
+
+/*GEM 3 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
+
+/*Sata block level reset*/
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
+
+/*PCIE config reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL                                  0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT                                   19
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                                    0x00080000U
+
+/*PCIE control block level reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL                                 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT                                  17
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK                                   0x00020000U
+
+/*PCIE bridge block level reset (AXI interface)*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL                               0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT                                18
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK                                 0x00040000U
+
+/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 
+		ane0 Bits [3:2] - lane 1*/
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL                                   0x00000000
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                                    0
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                                     0x0000000FU
+
+/*Set to '1' to hold the GT in reset. Clear to release.*/
+#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL 
+#undef DP_DP_PHY_RESET_GT_RESET_SHIFT 
+#undef DP_DP_PHY_RESET_GT_RESET_MASK 
+#define DP_DP_PHY_RESET_GT_RESET_DEFVAL                                            0x00010003
+#define DP_DP_PHY_RESET_GT_RESET_SHIFT                                             1
+#define DP_DP_PHY_RESET_GT_RESET_MASK                                              0x00000002U
+
+/*Display Port block level reset (includes DPDMA)*/
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
+#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 
+#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET                                         0XFFD80118
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 
+#define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET                                           0XFFD80120
+
+/*Power-up Request Interrupt Enable for PL*/
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 
+#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL                                      0x00000000
+#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT                                       23
+#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK                                        0x00800000U
+
+/*Power-up Request Trigger for PL*/
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 
+#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL                                        0x00000000
+#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT                                         23
+#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK                                          0x00800000U
+
+/*Power-up Request Status for PL*/
+#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 
+#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 
+#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 
+#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL                                      0x00000000
+#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT                                       23
+#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK                                        0x00800000U
+#define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET                                         0XFFD80110
+#undef GPIO_MASK_DATA_5_MSW_OFFSET 
+#define GPIO_MASK_DATA_5_MSW_OFFSET                                                0XFF0A002C
+#undef GPIO_DIRM_5_OFFSET 
+#define GPIO_DIRM_5_OFFSET                                                         0XFF0A0344
+#undef GPIO_OEN_5_OFFSET 
+#define GPIO_OEN_5_OFFSET                                                          0XFF0A0348
+#undef GPIO_DATA_5_OFFSET 
+#define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
+#undef GPIO_DATA_5_OFFSET 
+#define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
+#undef GPIO_DATA_5_OFFSET 
+#define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
+
+/*Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]*/
+#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 
+#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 
+#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 
+#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL                                     0x00000000
+#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT                                      16
+#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK                                       0xFFFF0000U
+
+/*Operation is the same as DIRM_0[DIRECTION_0]*/
+#undef GPIO_DIRM_5_DIRECTION_5_DEFVAL 
+#undef GPIO_DIRM_5_DIRECTION_5_SHIFT 
+#undef GPIO_DIRM_5_DIRECTION_5_MASK 
+#define GPIO_DIRM_5_DIRECTION_5_DEFVAL                                             
+#define GPIO_DIRM_5_DIRECTION_5_SHIFT                                              0
+#define GPIO_DIRM_5_DIRECTION_5_MASK                                               0xFFFFFFFFU
+
+/*Operation is the same as OEN_0[OP_ENABLE_0]*/
+#undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL 
+#undef GPIO_OEN_5_OP_ENABLE_5_SHIFT 
+#undef GPIO_OEN_5_OP_ENABLE_5_MASK 
+#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL                                              
+#define GPIO_OEN_5_OP_ENABLE_5_SHIFT                                               0
+#define GPIO_OEN_5_OP_ENABLE_5_MASK                                                0xFFFFFFFFU
+
+/*Output Data*/
+#undef GPIO_DATA_5_DATA_5_DEFVAL 
+#undef GPIO_DATA_5_DATA_5_SHIFT 
+#undef GPIO_DATA_5_DATA_5_MASK 
+#define GPIO_DATA_5_DATA_5_DEFVAL                                                  
+#define GPIO_DATA_5_DATA_5_SHIFT                                                   0
+#define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
+
+/*Output Data*/
+#undef GPIO_DATA_5_DATA_5_DEFVAL 
+#undef GPIO_DATA_5_DATA_5_SHIFT 
+#undef GPIO_DATA_5_DATA_5_MASK 
+#define GPIO_DATA_5_DATA_5_DEFVAL                                                  
+#define GPIO_DATA_5_DATA_5_SHIFT                                                   0
+#define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
+
+/*Output Data*/
+#undef GPIO_DATA_5_DATA_5_DEFVAL 
+#undef GPIO_DATA_5_DATA_5_SHIFT 
+#undef GPIO_DATA_5_DATA_5_MASK 
+#define GPIO_DATA_5_DATA_5_DEFVAL                                                  
+#define GPIO_DATA_5_DATA_5_SHIFT                                                   0
+#define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
+#ifdef __cplusplus
+extern "C" {
+#endif
+ int psu_init (); 
+ unsigned long psu_ps_pl_isolation_removal_data(); 
+ unsigned long psu_ps_pl_reset_config_data(); 
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl
new file mode 100644
index 000000000..ce5a46e85
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init.tcl
@@ -0,0 +1,13537 @@
+#****************************************************************************
+###
+#
+# @file psu_init.tcl
+#
+# This file is automatically generated
+#
+#****************************************************************************
+set psu_pll_init_data {
+		# : RPLL INIT
+		# Register : RPLL_CFG @ 0XFF5E0034

+
+		# PLL loop filter resistor control
+		# PSU_CRL_APB_RPLL_CFG_RES                                                        0x2
+
+		# PLL charge pump control
+		# PSU_CRL_APB_RPLL_CFG_CP                                                         0x3
+
+		# PLL loop filter high frequency capacitor control
+		# PSU_CRL_APB_RPLL_CFG_LFHF                                                       0x3
+
+		# Lock circuit counter setting
+		# PSU_CRL_APB_RPLL_CFG_LOCK_CNT                                                   0x258
+
+		# Lock circuit configuration settings for lock windowsize
+		# PSU_CRL_APB_RPLL_CFG_LOCK_DLY                                                   0x3f
+
+		# Helper data. Values are to be looked up in a table from Data Sheet
+		#(OFFSET, MASK, VALUE)      (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U)  */
+    mask_write 0XFF5E0034 0xFE7FEDEF 0x7E4B0C62
+		# : UPDATE FB_DIV
+		# Register : RPLL_CTRL @ 0XFF5E0030

+
+		# Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		# ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		# PSU_CRL_APB_RPLL_CTRL_PRE_SRC                                                   0x0
+
+		# The integer portion of the feedback divider to the PLL
+		# PSU_CRL_APB_RPLL_CTRL_FBDIV                                                     0x48
+
+		# This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		# PSU_CRL_APB_RPLL_CTRL_DIV2                                                      0x1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00717F00U ,0x00014800U)  */
+    mask_write 0XFF5E0030 0x00717F00 0x00014800
+		# : BY PASS PLL
+		# Register : RPLL_CTRL @ 0XFF5E0030

+
+		# Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		# cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000008U)  */
+    mask_write 0XFF5E0030 0x00000008 0x00000008
+		# : ASSERT RESET
+		# Register : RPLL_CTRL @ 0XFF5E0030

+
+		# Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		# PSU_CRL_APB_RPLL_CTRL_RESET                                                     1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFF5E0030 0x00000001 0x00000001
+		# : DEASSERT RESET
+		# Register : RPLL_CTRL @ 0XFF5E0030

+
+		# Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		# PSU_CRL_APB_RPLL_CTRL_RESET                                                     0
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000000U)  */
+    mask_write 0XFF5E0030 0x00000001 0x00000000
+		# : CHECK PLL STATUS
+		# Register : PLL_STATUS @ 0XFF5E0040

+
+		# RPLL is locked
+		# PSU_CRL_APB_PLL_STATUS_RPLL_LOCK                                                1
+    mask_poll 0XFF5E0040 0x00000002
+		# : REMOVE PLL BY PASS
+		# Register : RPLL_CTRL @ 0XFF5E0030

+
+		# Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		# cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    0
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000000U)  */
+    mask_write 0XFF5E0030 0x00000008 0x00000000
+		# Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048

+
+		# Divisor value for this clock.
+		# PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0                                           0x3
+
+		# Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		#(OFFSET, MASK, VALUE)      (0XFF5E0048, 0x00003F00U ,0x00000300U)  */
+    mask_write 0XFF5E0048 0x00003F00 0x00000300
+		# : RPLL FRAC CFG
+		# Register : RPLL_FRAC_CFG @ 0XFF5E0038

+
+		# Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		#  mode and uses DATA of this register for the fractional portion of the feedback divider.
+		# PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED                                               0x0
+
+		# Fractional value for the Feedback value.
+		# PSU_CRL_APB_RPLL_FRAC_CFG_DATA                                                  0x0
+
+		# Fractional control for the PLL
+		#(OFFSET, MASK, VALUE)      (0XFF5E0038, 0x8000FFFFU ,0x00000000U)  */
+    mask_write 0XFF5E0038 0x8000FFFF 0x00000000
+		# : IOPLL INIT
+		# Register : IOPLL_CFG @ 0XFF5E0024

+
+		# PLL loop filter resistor control
+		# PSU_CRL_APB_IOPLL_CFG_RES                                                       0xc
+
+		# PLL charge pump control
+		# PSU_CRL_APB_IOPLL_CFG_CP                                                        0x3
+
+		# PLL loop filter high frequency capacitor control
+		# PSU_CRL_APB_IOPLL_CFG_LFHF                                                      0x3
+
+		# Lock circuit counter setting
+		# PSU_CRL_APB_IOPLL_CFG_LOCK_CNT                                                  0x339
+
+		# Lock circuit configuration settings for lock windowsize
+		# PSU_CRL_APB_IOPLL_CFG_LOCK_DLY                                                  0x3f
+
+		# Helper data. Values are to be looked up in a table from Data Sheet
+		#(OFFSET, MASK, VALUE)      (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU)  */
+    mask_write 0XFF5E0024 0xFE7FEDEF 0x7E672C6C
+		# : UPDATE FB_DIV
+		# Register : IOPLL_CTRL @ 0XFF5E0020

+
+		# Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		# ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		# PSU_CRL_APB_IOPLL_CTRL_PRE_SRC                                                  0x0
+
+		# The integer portion of the feedback divider to the PLL
+		# PSU_CRL_APB_IOPLL_CTRL_FBDIV                                                    0x2d
+
+		# This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		# PSU_CRL_APB_IOPLL_CTRL_DIV2                                                     0x0
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00717F00U ,0x00002D00U)  */
+    mask_write 0XFF5E0020 0x00717F00 0x00002D00
+		# : BY PASS PLL
+		# Register : IOPLL_CTRL @ 0XFF5E0020

+
+		# Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		# cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000008U)  */
+    mask_write 0XFF5E0020 0x00000008 0x00000008
+		# : ASSERT RESET
+		# Register : IOPLL_CTRL @ 0XFF5E0020

+
+		# Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		# PSU_CRL_APB_IOPLL_CTRL_RESET                                                    1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFF5E0020 0x00000001 0x00000001
+		# : DEASSERT RESET
+		# Register : IOPLL_CTRL @ 0XFF5E0020

+
+		# Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		# PSU_CRL_APB_IOPLL_CTRL_RESET                                                    0
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000000U)  */
+    mask_write 0XFF5E0020 0x00000001 0x00000000
+		# : CHECK PLL STATUS
+		# Register : PLL_STATUS @ 0XFF5E0040

+
+		# IOPLL is locked
+		# PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK                                               1
+    mask_poll 0XFF5E0040 0x00000001
+		# : REMOVE PLL BY PASS
+		# Register : IOPLL_CTRL @ 0XFF5E0020

+
+		# Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		# cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   0
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000000U)  */
+    mask_write 0XFF5E0020 0x00000008 0x00000000
+		# Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044

+
+		# Divisor value for this clock.
+		# PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0                                          0x3
+
+		# Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		#(OFFSET, MASK, VALUE)      (0XFF5E0044, 0x00003F00U ,0x00000300U)  */
+    mask_write 0XFF5E0044 0x00003F00 0x00000300
+		# : IOPLL FRAC CFG
+		# Register : IOPLL_FRAC_CFG @ 0XFF5E0028

+
+		# Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		#  mode and uses DATA of this register for the fractional portion of the feedback divider.
+		# PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED                                              0x0
+
+		# Fractional value for the Feedback value.
+		# PSU_CRL_APB_IOPLL_FRAC_CFG_DATA                                                 0x0
+
+		# Fractional control for the PLL
+		#(OFFSET, MASK, VALUE)      (0XFF5E0028, 0x8000FFFFU ,0x00000000U)  */
+    mask_write 0XFF5E0028 0x8000FFFF 0x00000000
+		# : APU_PLL INIT
+		# Register : APLL_CFG @ 0XFD1A0024

+
+		# PLL loop filter resistor control
+		# PSU_CRF_APB_APLL_CFG_RES                                                        0x2
+
+		# PLL charge pump control
+		# PSU_CRF_APB_APLL_CFG_CP                                                         0x3
+
+		# PLL loop filter high frequency capacitor control
+		# PSU_CRF_APB_APLL_CFG_LFHF                                                       0x3
+
+		# Lock circuit counter setting
+		# PSU_CRF_APB_APLL_CFG_LOCK_CNT                                                   0x258
+
+		# Lock circuit configuration settings for lock windowsize
+		# PSU_CRF_APB_APLL_CFG_LOCK_DLY                                                   0x3f
+
+		# Helper data. Values are to be looked up in a table from Data Sheet
+		#(OFFSET, MASK, VALUE)      (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U)  */
+    mask_write 0XFD1A0024 0xFE7FEDEF 0x7E4B0C62
+		# : UPDATE FB_DIV
+		# Register : APLL_CTRL @ 0XFD1A0020

+
+		# Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		# ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		# PSU_CRF_APB_APLL_CTRL_PRE_SRC                                                   0x0
+
+		# The integer portion of the feedback divider to the PLL
+		# PSU_CRF_APB_APLL_CTRL_FBDIV                                                     0x42
+
+		# This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		# PSU_CRF_APB_APLL_CTRL_DIV2                                                      0x1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00717F00U ,0x00014200U)  */
+    mask_write 0XFD1A0020 0x00717F00 0x00014200
+		# : BY PASS PLL
+		# Register : APLL_CTRL @ 0XFD1A0020

+
+		# Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		# cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_APLL_CTRL_BYPASS                                                    1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000008U)  */
+    mask_write 0XFD1A0020 0x00000008 0x00000008
+		# : ASSERT RESET
+		# Register : APLL_CTRL @ 0XFD1A0020

+
+		# Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		# PSU_CRF_APB_APLL_CTRL_RESET                                                     1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFD1A0020 0x00000001 0x00000001
+		# : DEASSERT RESET
+		# Register : APLL_CTRL @ 0XFD1A0020

+
+		# Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		# PSU_CRF_APB_APLL_CTRL_RESET                                                     0
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000000U)  */
+    mask_write 0XFD1A0020 0x00000001 0x00000000
+		# : CHECK PLL STATUS
+		# Register : PLL_STATUS @ 0XFD1A0044

+
+		# APLL is locked
+		# PSU_CRF_APB_PLL_STATUS_APLL_LOCK                                                1
+    mask_poll 0XFD1A0044 0x00000001
+		# : REMOVE PLL BY PASS
+		# Register : APLL_CTRL @ 0XFD1A0020

+
+		# Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		# cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_APLL_CTRL_BYPASS                                                    0
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000000U)  */
+    mask_write 0XFD1A0020 0x00000008 0x00000000
+		# Register : APLL_TO_LPD_CTRL @ 0XFD1A0048

+
+		# Divisor value for this clock.
+		# PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0                                           0x3
+
+		# Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
+		#(OFFSET, MASK, VALUE)      (0XFD1A0048, 0x00003F00U ,0x00000300U)  */
+    mask_write 0XFD1A0048 0x00003F00 0x00000300
+		# : APLL FRAC CFG
+		# Register : APLL_FRAC_CFG @ 0XFD1A0028

+
+		# Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		#  mode and uses DATA of this register for the fractional portion of the feedback divider.
+		# PSU_CRF_APB_APLL_FRAC_CFG_ENABLED                                               0x0
+
+		# Fractional value for the Feedback value.
+		# PSU_CRF_APB_APLL_FRAC_CFG_DATA                                                  0x0
+
+		# Fractional control for the PLL
+		#(OFFSET, MASK, VALUE)      (0XFD1A0028, 0x8000FFFFU ,0x00000000U)  */
+    mask_write 0XFD1A0028 0x8000FFFF 0x00000000
+		# : DDR_PLL INIT
+		# Register : DPLL_CFG @ 0XFD1A0030

+
+		# PLL loop filter resistor control
+		# PSU_CRF_APB_DPLL_CFG_RES                                                        0x2
+
+		# PLL charge pump control
+		# PSU_CRF_APB_DPLL_CFG_CP                                                         0x3
+
+		# PLL loop filter high frequency capacitor control
+		# PSU_CRF_APB_DPLL_CFG_LFHF                                                       0x3
+
+		# Lock circuit counter setting
+		# PSU_CRF_APB_DPLL_CFG_LOCK_CNT                                                   0x258
+
+		# Lock circuit configuration settings for lock windowsize
+		# PSU_CRF_APB_DPLL_CFG_LOCK_DLY                                                   0x3f
+
+		# Helper data. Values are to be looked up in a table from Data Sheet
+		#(OFFSET, MASK, VALUE)      (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U)  */
+    mask_write 0XFD1A0030 0xFE7FEDEF 0x7E4B0C62
+		# : UPDATE FB_DIV
+		# Register : DPLL_CTRL @ 0XFD1A002C

+
+		# Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		# ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		# PSU_CRF_APB_DPLL_CTRL_PRE_SRC                                                   0x0
+
+		# The integer portion of the feedback divider to the PLL
+		# PSU_CRF_APB_DPLL_CTRL_FBDIV                                                     0x40
+
+		# This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		# PSU_CRF_APB_DPLL_CTRL_DIV2                                                      0x1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00717F00U ,0x00014000U)  */
+    mask_write 0XFD1A002C 0x00717F00 0x00014000
+		# : BY PASS PLL
+		# Register : DPLL_CTRL @ 0XFD1A002C

+
+		# Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		# cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000008U)  */
+    mask_write 0XFD1A002C 0x00000008 0x00000008
+		# : ASSERT RESET
+		# Register : DPLL_CTRL @ 0XFD1A002C

+
+		# Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		# PSU_CRF_APB_DPLL_CTRL_RESET                                                     1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFD1A002C 0x00000001 0x00000001
+		# : DEASSERT RESET
+		# Register : DPLL_CTRL @ 0XFD1A002C

+
+		# Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		# PSU_CRF_APB_DPLL_CTRL_RESET                                                     0
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000000U)  */
+    mask_write 0XFD1A002C 0x00000001 0x00000000
+		# : CHECK PLL STATUS
+		# Register : PLL_STATUS @ 0XFD1A0044

+
+		# DPLL is locked
+		# PSU_CRF_APB_PLL_STATUS_DPLL_LOCK                                                1
+    mask_poll 0XFD1A0044 0x00000002
+		# : REMOVE PLL BY PASS
+		# Register : DPLL_CTRL @ 0XFD1A002C

+
+		# Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		# cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    0
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000000U)  */
+    mask_write 0XFD1A002C 0x00000008 0x00000000
+		# Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C

+
+		# Divisor value for this clock.
+		# PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
+
+		# Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
+		#(OFFSET, MASK, VALUE)      (0XFD1A004C, 0x00003F00U ,0x00000300U)  */
+    mask_write 0XFD1A004C 0x00003F00 0x00000300
+		# : DPLL FRAC CFG
+		# Register : DPLL_FRAC_CFG @ 0XFD1A0034

+
+		# Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		#  mode and uses DATA of this register for the fractional portion of the feedback divider.
+		# PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED                                               0x0
+
+		# Fractional value for the Feedback value.
+		# PSU_CRF_APB_DPLL_FRAC_CFG_DATA                                                  0x0
+
+		# Fractional control for the PLL
+		#(OFFSET, MASK, VALUE)      (0XFD1A0034, 0x8000FFFFU ,0x00000000U)  */
+    mask_write 0XFD1A0034 0x8000FFFF 0x00000000
+		# : VIDEO_PLL INIT
+		# Register : VPLL_CFG @ 0XFD1A003C

+
+		# PLL loop filter resistor control
+		# PSU_CRF_APB_VPLL_CFG_RES                                                        0x2
+
+		# PLL charge pump control
+		# PSU_CRF_APB_VPLL_CFG_CP                                                         0x3
+
+		# PLL loop filter high frequency capacitor control
+		# PSU_CRF_APB_VPLL_CFG_LFHF                                                       0x3
+
+		# Lock circuit counter setting
+		# PSU_CRF_APB_VPLL_CFG_LOCK_CNT                                                   0x28a
+
+		# Lock circuit configuration settings for lock windowsize
+		# PSU_CRF_APB_VPLL_CFG_LOCK_DLY                                                   0x3f
+
+		# Helper data. Values are to be looked up in a table from Data Sheet
+		#(OFFSET, MASK, VALUE)      (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U)  */
+    mask_write 0XFD1A003C 0xFE7FEDEF 0x7E514C62
+		# : UPDATE FB_DIV
+		# Register : VPLL_CTRL @ 0XFD1A0038

+
+		# Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		# ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		# PSU_CRF_APB_VPLL_CTRL_PRE_SRC                                                   0x0
+
+		# The integer portion of the feedback divider to the PLL
+		# PSU_CRF_APB_VPLL_CTRL_FBDIV                                                     0x39
+
+		# This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		# PSU_CRF_APB_VPLL_CTRL_DIV2                                                      0x1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00717F00U ,0x00013900U)  */
+    mask_write 0XFD1A0038 0x00717F00 0x00013900
+		# : BY PASS PLL
+		# Register : VPLL_CTRL @ 0XFD1A0038

+
+		# Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		# cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000008U)  */
+    mask_write 0XFD1A0038 0x00000008 0x00000008
+		# : ASSERT RESET
+		# Register : VPLL_CTRL @ 0XFD1A0038

+
+		# Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		# PSU_CRF_APB_VPLL_CTRL_RESET                                                     1
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFD1A0038 0x00000001 0x00000001
+		# : DEASSERT RESET
+		# Register : VPLL_CTRL @ 0XFD1A0038

+
+		# Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		# PSU_CRF_APB_VPLL_CTRL_RESET                                                     0
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000000U)  */
+    mask_write 0XFD1A0038 0x00000001 0x00000000
+		# : CHECK PLL STATUS
+		# Register : PLL_STATUS @ 0XFD1A0044

+
+		# VPLL is locked
+		# PSU_CRF_APB_PLL_STATUS_VPLL_LOCK                                                1
+    mask_poll 0XFD1A0044 0x00000004
+		# : REMOVE PLL BY PASS
+		# Register : VPLL_CTRL @ 0XFD1A0038

+
+		# Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		# cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    0
+
+		# PLL Basic Control
+		#(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000000U)  */
+    mask_write 0XFD1A0038 0x00000008 0x00000000
+		# Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050

+
+		# Divisor value for this clock.
+		# PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
+
+		# Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
+		#(OFFSET, MASK, VALUE)      (0XFD1A0050, 0x00003F00U ,0x00000300U)  */
+    mask_write 0XFD1A0050 0x00003F00 0x00000300
+		# : VIDEO FRAC CFG
+		# Register : VPLL_FRAC_CFG @ 0XFD1A0040

+
+		# Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		#  mode and uses DATA of this register for the fractional portion of the feedback divider.
+		# PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED                                               0x1
+
+		# Fractional value for the Feedback value.
+		# PSU_CRF_APB_VPLL_FRAC_CFG_DATA                                                  0x820c
+
+		# Fractional control for the PLL
+		#(OFFSET, MASK, VALUE)      (0XFD1A0040, 0x8000FFFFU ,0x8000820CU)  */
+    mask_write 0XFD1A0040 0x8000FFFF 0x8000820C
+}
+
+set psu_clock_init_data {
+		# : CLOCK CONTROL SLCR REGISTER
+		# Register : GEM0_REF_CTRL @ 0XFF5E0050

+
+		# Clock active for the RX channel
+		# PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT                                             0x1
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_GEM0_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0                                              0x8
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL                                                0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0050, 0x063F3F07U ,0x06010800U)  */
+    mask_write 0XFF5E0050 0x063F3F07 0x06010800
+		# Register : GEM1_REF_CTRL @ 0XFF5E0054

+
+		# Clock active for the RX channel
+		# PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT                                             0x1
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_GEM1_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0                                              0x8
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL                                                0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0054, 0x063F3F07U ,0x06010800U)  */
+    mask_write 0XFF5E0054 0x063F3F07 0x06010800
+		# Register : GEM2_REF_CTRL @ 0XFF5E0058

+
+		# Clock active for the RX channel
+		# PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT                                             0x1
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_GEM2_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0                                              0x8
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL                                                0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0058, 0x063F3F07U ,0x06010800U)  */
+    mask_write 0XFF5E0058 0x063F3F07 0x06010800
+		# Register : GEM3_REF_CTRL @ 0XFF5E005C

+
+		# Clock active for the RX channel
+		# PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT                                             0x1
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_GEM3_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0                                              0xc
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL                                                0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E005C, 0x063F3F07U ,0x06010C00U)  */
+    mask_write 0XFF5E005C 0x063F3F07 0x06010C00
+		# Register : GEM_TSU_REF_CTRL @ 0XFF5E0100

+
+		# 6 bit divider
+		# PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0                                           0x6
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL                                             0x2
+
+		# 6 bit divider
+		# PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1                                           0x1
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT                                             0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0100, 0x013F3F07U ,0x01010602U)  */
+    mask_write 0XFF5E0100 0x013F3F07 0x01010602
+		# Register : USB0_BUS_REF_CTRL @ 0XFF5E0060

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT                                            0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1                                          0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0                                          0x6
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL                                            0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0060, 0x023F3F07U ,0x02010600U)  */
+    mask_write 0XFF5E0060 0x023F3F07 0x02010600
+		# Register : USB1_BUS_REF_CTRL @ 0XFF5E0064

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_USB1_BUS_REF_CTRL_CLKACT                                            0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1                                          0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0                                          0x4
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_USB1_BUS_REF_CTRL_SRCSEL                                            0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0064, 0x023F3F07U ,0x02010400U)  */
+    mask_write 0XFF5E0064 0x023F3F07 0x02010400
+		# Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT                                           0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1                                         0xf
+
+		# 6 bit divider
+		# PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0                                         0x5
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL                                           0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E004C, 0x023F3F07U ,0x020F0500U)  */
+    mask_write 0XFF5E004C 0x023F3F07 0x020F0500
+		# Register : QSPI_REF_CTRL @ 0XFF5E0068

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_QSPI_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                                              0xc
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                                                0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010C00U)  */
+    mask_write 0XFF5E0068 0x013F3F07 0x01010C00
+		# Register : SDIO0_REF_CTRL @ 0XFF5E006C

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT                                               0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1                                             0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0                                             0x7
+
+		# 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL                                               0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E006C, 0x013F3F07U ,0x01010702U)  */
+    mask_write 0XFF5E006C 0x013F3F07 0x01010702
+		# Register : SDIO1_REF_CTRL @ 0XFF5E0070

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT                                               0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1                                             0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0                                             0x6
+
+		# 000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL                                               0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0070, 0x013F3F07U ,0x01010602U)  */
+    mask_write 0XFF5E0070 0x013F3F07 0x01010602
+		# Register : SDIO_CLK_CTRL @ 0XFF18030C

+
+		# MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]
+		# PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL                                     0
+
+		# SoC Debug Clock Control
+		#(OFFSET, MASK, VALUE)      (0XFF18030C, 0x00020000U ,0x00000000U)  */
+    mask_write 0XFF18030C 0x00020000 0x00000000
+		# Register : UART0_REF_CTRL @ 0XFF5E0074

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_UART0_REF_CTRL_CLKACT                                               0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1                                             0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0                                             0xf
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_UART0_REF_CTRL_SRCSEL                                               0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0074, 0x013F3F07U ,0x01010F00U)  */
+    mask_write 0XFF5E0074 0x013F3F07 0x01010F00
+		# Register : UART1_REF_CTRL @ 0XFF5E0078

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_UART1_REF_CTRL_CLKACT                                               0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1                                             0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0                                             0xf
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_UART1_REF_CTRL_SRCSEL                                               0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0078, 0x013F3F07U ,0x01010F00U)  */
+    mask_write 0XFF5E0078 0x013F3F07 0x01010F00
+		# Register : I2C0_REF_CTRL @ 0XFF5E0120

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_I2C0_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0                                              0xf
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL                                                0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0120, 0x013F3F07U ,0x01010F00U)  */
+    mask_write 0XFF5E0120 0x013F3F07 0x01010F00
+		# Register : I2C1_REF_CTRL @ 0XFF5E0124

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_I2C1_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0                                              0xf
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL                                                0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0124, 0x013F3F07U ,0x01010F00U)  */
+    mask_write 0XFF5E0124 0x013F3F07 0x01010F00
+		# Register : SPI0_REF_CTRL @ 0XFF5E007C

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_SPI0_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0                                              0x7
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL                                                0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E007C, 0x013F3F07U ,0x01010702U)  */
+    mask_write 0XFF5E007C 0x013F3F07 0x01010702
+		# Register : SPI1_REF_CTRL @ 0XFF5E0080

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_SPI1_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0                                              0x7
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL                                                0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0080, 0x013F3F07U ,0x01010702U)  */
+    mask_write 0XFF5E0080 0x013F3F07 0x01010702
+		# Register : CAN0_REF_CTRL @ 0XFF5E0084

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_CAN0_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0                                              0xa
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL                                                0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0084, 0x013F3F07U ,0x01010A00U)  */
+    mask_write 0XFF5E0084 0x013F3F07 0x01010A00
+		# Register : CAN1_REF_CTRL @ 0XFF5E0088

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_CAN1_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0                                              0xf
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL                                                0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0088, 0x013F3F07U ,0x01010F00U)  */
+    mask_write 0XFF5E0088 0x013F3F07 0x01010F00
+		# Register : CPU_R5_CTRL @ 0XFF5E0090

+
+		# Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
+		# d lead to system hang
+		# PSU_CRL_APB_CPU_R5_CTRL_CLKACT                                                  0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0                                                0x3
+
+		# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_CPU_R5_CTRL_SRCSEL                                                  0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0090, 0x01003F07U ,0x01000302U)  */
+    mask_write 0XFF5E0090 0x01003F07 0x01000302
+		# Register : IOU_SWITCH_CTRL @ 0XFF5E009C

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0                                            0x6
+
+		# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL                                              0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E009C, 0x01003F07U ,0x01000602U)  */
+    mask_write 0XFF5E009C 0x01003F07 0x01000602
+		# Register : CSU_PLL_CTRL @ 0XFF5E00A0

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_CSU_PLL_CTRL_CLKACT                                                 0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_CSU_PLL_CTRL_DIVISOR0                                               0x3
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_CSU_PLL_CTRL_SRCSEL                                                 0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E00A0, 0x01003F07U ,0x01000302U)  */
+    mask_write 0XFF5E00A0 0x01003F07 0x01000302
+		# Register : PCAP_CTRL @ 0XFF5E00A4

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_PCAP_CTRL_CLKACT                                                    0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_PCAP_CTRL_DIVISOR0                                                  0x6
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_PCAP_CTRL_SRCSEL                                                    0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E00A4, 0x01003F07U ,0x01000602U)  */
+    mask_write 0XFF5E00A4 0x01003F07 0x01000602
+		# Register : LPD_SWITCH_CTRL @ 0XFF5E00A8

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0                                            0x3
+
+		# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL                                              0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E00A8, 0x01003F07U ,0x01000302U)  */
+    mask_write 0XFF5E00A8 0x01003F07 0x01000302
+		# Register : LPD_LSBUS_CTRL @ 0XFF5E00AC

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT                                               0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0                                             0xf
+
+		# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL                                               0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E00AC, 0x01003F07U ,0x01000F02U)  */
+    mask_write 0XFF5E00AC 0x01003F07 0x01000F02
+		# Register : DBG_LPD_CTRL @ 0XFF5E00B0

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_DBG_LPD_CTRL_CLKACT                                                 0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0                                               0x6
+
+		# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL                                                 0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E00B0, 0x01003F07U ,0x01000602U)  */
+    mask_write 0XFF5E00B0 0x01003F07 0x01000602
+		# Register : NAND_REF_CTRL @ 0XFF5E00B4

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_NAND_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1                                              0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0                                              0xa
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_NAND_REF_CTRL_SRCSEL                                                0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E00B4, 0x013F3F07U ,0x01010A00U)  */
+    mask_write 0XFF5E00B4 0x013F3F07 0x01010A00
+		# Register : ADMA_REF_CTRL @ 0XFF5E00B8

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_ADMA_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0                                              0x3
+
+		# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL                                                0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E00B8, 0x01003F07U ,0x01000302U)  */
+    mask_write 0XFF5E00B8 0x01003F07 0x01000302
+		# Register : PL0_REF_CTRL @ 0XFF5E00C0

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_PL0_REF_CTRL_CLKACT                                                 0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1                                               0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0                                               0xf
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_PL0_REF_CTRL_SRCSEL                                                 0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E00C0, 0x013F3F07U ,0x01010F00U)  */
+    mask_write 0XFF5E00C0 0x013F3F07 0x01010F00
+		# Register : PL1_REF_CTRL @ 0XFF5E00C4

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_PL1_REF_CTRL_CLKACT                                                 0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1                                               0x4
+
+		# 6 bit divider
+		# PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0                                               0xf
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_PL1_REF_CTRL_SRCSEL                                                 0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E00C4, 0x013F3F07U ,0x01040F00U)  */
+    mask_write 0XFF5E00C4 0x013F3F07 0x01040F00
+		# Register : PL2_REF_CTRL @ 0XFF5E00C8

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_PL2_REF_CTRL_CLKACT                                                 0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1                                               0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0                                               0x4
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_PL2_REF_CTRL_SRCSEL                                                 0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E00C8, 0x013F3F07U ,0x01010402U)  */
+    mask_write 0XFF5E00C8 0x013F3F07 0x01010402
+		# Register : PL3_REF_CTRL @ 0XFF5E00CC

+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_PL3_REF_CTRL_CLKACT                                                 0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1                                               0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0                                               0x3
+
+		# 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_PL3_REF_CTRL_SRCSEL                                                 0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E00CC, 0x013F3F07U ,0x01010302U)  */
+    mask_write 0XFF5E00CC 0x013F3F07 0x01010302
+		# Register : AMS_REF_CTRL @ 0XFF5E0108

+
+		# 6 bit divider
+		# PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1                                               0x1
+
+		# 6 bit divider
+		# PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0                                               0x1d
+
+		# 000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		# clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_AMS_REF_CTRL_SRCSEL                                                 0x2
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_AMS_REF_CTRL_CLKACT                                                 0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0108, 0x013F3F07U ,0x01011D02U)  */
+    mask_write 0XFF5E0108 0x013F3F07 0x01011D02
+		# Register : DLL_REF_CTRL @ 0XFF5E0104

+
+		# 000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
+		# is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_DLL_REF_CTRL_SRCSEL                                                 0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0104, 0x00000007U ,0x00000000U)  */
+    mask_write 0XFF5E0104 0x00000007 0x00000000
+		# Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128

+
+		# 6 bit divider
+		# PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0                                         0xf
+
+		# 1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 
+		#  cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL                                           0x0
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT                                           0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFF5E0128, 0x01003F07U ,0x01000F00U)  */
+    mask_write 0XFF5E0128 0x01003F07 0x01000F00
+		# Register : SATA_REF_CTRL @ 0XFD1A00A0

+
+		# 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		# he new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_SATA_REF_CTRL_SRCSEL                                                0x0
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_SATA_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0                                              0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A00A0, 0x01003F07U ,0x01000200U)  */
+    mask_write 0XFD1A00A0 0x01003F07 0x01000200
+		# Register : PCIE_REF_CTRL @ 0XFD1A00B4

+
+		# 000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
+		# es of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL                                                0x0
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_PCIE_REF_CTRL_CLKACT                                                0x1
+
+		# 6 bit divider
+		# PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0                                              0x2
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A00B4, 0x01003F07U ,0x01000200U)  */
+    mask_write 0XFD1A00B4 0x01003F07 0x01000200
+		# Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070

+
+		# 6 bit divider
+		# PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1                                          0x1
+
+		# 6 bit divider
+		# PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0                                          0x3
+
+		# 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 
+		# ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL                                            0x3
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT                                            0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A0070, 0x013F3F07U ,0x01010303U)  */
+    mask_write 0XFD1A0070 0x013F3F07 0x01010303
+		# Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074

+
+		# 6 bit divider
+		# PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1                                          0x1
+
+		# 6 bit divider
+		# PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0                                          0x27
+
+		# 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 
+		# ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL                                            0x0
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT                                            0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A0074, 0x013F3F07U ,0x01012700U)  */
+    mask_write 0XFD1A0074 0x013F3F07 0x01012700
+		# Register : DP_STC_REF_CTRL @ 0XFD1A007C

+
+		# 6 bit divider
+		# PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1                                            0x1
+
+		# 6 bit divider
+		# PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0                                            0x11
+
+		# 000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
+		# e new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL                                              0x3
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT                                              0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A007C, 0x013F3F07U ,0x01011103U)  */
+    mask_write 0XFD1A007C 0x013F3F07 0x01011103
+		# Register : ACPU_CTRL @ 0XFD1A0060

+
+		# 6 bit divider
+		# PSU_CRF_APB_ACPU_CTRL_DIVISOR0                                                  0x1
+
+		# 000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		# lock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_ACPU_CTRL_SRCSEL                                                    0x0
+
+		# Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock
+		# PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF                                               0x1
+
+		# Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
+		#  to the entire APU
+		# PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL                                               0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A0060, 0x03003F07U ,0x03000100U)  */
+    mask_write 0XFD1A0060 0x03003F07 0x03000100
+		# Register : DBG_TRACE_CTRL @ 0XFD1A0064

+
+		# 6 bit divider
+		# PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0                                             0x2
+
+		# 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		# he new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL                                               0x0
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT                                               0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A0064, 0x01003F07U ,0x01000200U)  */
+    mask_write 0XFD1A0064 0x01003F07 0x01000200
+		# Register : DBG_FPD_CTRL @ 0XFD1A0068

+
+		# 6 bit divider
+		# PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0                                               0x2
+
+		# 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		# he new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL                                                 0x0
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_DBG_FPD_CTRL_CLKACT                                                 0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A0068, 0x01003F07U ,0x01000200U)  */
+    mask_write 0XFD1A0068 0x01003F07 0x01000200
+		# Register : DDR_CTRL @ 0XFD1A0080

+
+		# 6 bit divider
+		# PSU_CRF_APB_DDR_CTRL_DIVISOR0                                                   0x2
+
+		# 000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This 
+		# s not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_DDR_CTRL_SRCSEL                                                     0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A0080, 0x00003F07U ,0x00000200U)  */
+    mask_write 0XFD1A0080 0x00003F07 0x00000200
+		# Register : GPU_REF_CTRL @ 0XFD1A0084

+
+		# 6 bit divider
+		# PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0                                               0x1
+
+		# 000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		# he new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_GPU_REF_CTRL_SRCSEL                                                 0x0
+
+		# Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).
+		# PSU_CRF_APB_GPU_REF_CTRL_CLKACT                                                 0x1
+
+		# Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
+		# PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT                                             0x1
+
+		# Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
+		# PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT                                             0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A0084, 0x07003F07U ,0x07000100U)  */
+    mask_write 0XFD1A0084 0x07003F07 0x07000100
+		# Register : GDMA_REF_CTRL @ 0XFD1A00B8

+
+		# 6 bit divider
+		# PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0                                              0x2
+
+		# 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		# lock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL                                                0x0
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_GDMA_REF_CTRL_CLKACT                                                0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A00B8, 0x01003F07U ,0x01000200U)  */
+    mask_write 0XFD1A00B8 0x01003F07 0x01000200
+		# Register : DPDMA_REF_CTRL @ 0XFD1A00BC

+
+		# 6 bit divider
+		# PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0                                             0x2
+
+		# 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		# lock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL                                               0x0
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT                                               0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A00BC, 0x01003F07U ,0x01000200U)  */
+    mask_write 0XFD1A00BC 0x01003F07 0x01000200
+		# Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0

+
+		# 6 bit divider
+		# PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0                                            0x2
+
+		# 000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		# lock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL                                              0x2
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT                                              0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A00C0, 0x01003F07U ,0x01000202U)  */
+    mask_write 0XFD1A00C0 0x01003F07 0x01000202
+		# Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4

+
+		# 6 bit divider
+		# PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0                                           0x5
+
+		# 000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		# he new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL                                             0x2
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT                                             0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A00C4, 0x01003F07U ,0x01000502U)  */
+    mask_write 0XFD1A00C4 0x01003F07 0x01000502
+		# Register : GTGREF0_REF_CTRL @ 0XFD1A00C8

+
+		# 6 bit divider
+		# PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0                                           0x4
+
+		# 000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		# he new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL                                             0x0
+
+		# Clock active signal. Switch to 0 to disable the clock
+		# PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT                                             0x1
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A00C8, 0x01003F07U ,0x01000400U)  */
+    mask_write 0XFD1A00C8 0x01003F07 0x01000400
+		# Register : DBG_TSTMP_CTRL @ 0XFD1A00F8

+
+		# 6 bit divider
+		# PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0                                             0x2
+
+		# 000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		# he new clock. This is not usually an issue, but designers must be aware.)
+		# PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL                                               0x0
+
+		# This register controls this reference clock
+		#(OFFSET, MASK, VALUE)      (0XFD1A00F8, 0x00003F07U ,0x00000200U)  */
+    mask_write 0XFD1A00F8 0x00003F07 0x00000200
+		# Register : IOU_TTC_APB_CLK @ 0XFF180380

+
+		# 00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
+		# 0" = Select the R5 clock for the APB interface of TTC0
+		# PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL                                           0
+
+		# 00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
+		# 0" = Select the R5 clock for the APB interface of TTC1
+		# PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL                                           0
+
+		# 00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
+		# 0" = Select the R5 clock for the APB interface of TTC2
+		# PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL                                           0
+
+		# 00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
+		# 0" = Select the R5 clock for the APB interface of TTC3
+		# PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL                                           0
+
+		# TTC APB clock select
+		#(OFFSET, MASK, VALUE)      (0XFF180380, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFF180380 0x000000FF 0x00000000
+		# Register : WDT_CLK_SEL @ 0XFD610100

+
+		# System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)
+		# PSU_FPD_SLCR_WDT_CLK_SEL_SELECT                                                 0
+
+		# SWDT clock source select
+		#(OFFSET, MASK, VALUE)      (0XFD610100, 0x00000001U ,0x00000000U)  */
+    mask_write 0XFD610100 0x00000001 0x00000000
+		# Register : WDT_CLK_SEL @ 0XFF180300

+
+		# System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout 
+		# ia MIO
+		# PSU_IOU_SLCR_WDT_CLK_SEL_SELECT                                                 0
+
+		# SWDT clock source select
+		#(OFFSET, MASK, VALUE)      (0XFF180300, 0x00000001U ,0x00000000U)  */
+    mask_write 0XFF180300 0x00000001 0x00000000
+		# Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050

+
+		# System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk
+		# PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT                                          0
+
+		# SWDT clock source select
+		#(OFFSET, MASK, VALUE)      (0XFF410050, 0x00000001U ,0x00000000U)  */
+    mask_write 0XFF410050 0x00000001 0x00000000
+}
+
+set psu_ddr_init_data {
+		# : DDR INITIALIZATION
+		# : DDR CONTROLLER RESET
+		# Register : RST_DDR_SS @ 0XFD1A0108

+
+		# DDR block level reset inside of the DDR Sub System
+		# PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X1
+
+		# DDR sub system block level reset
+		#(OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000008U)  */
+    mask_write 0XFD1A0108 0x00000008 0x00000008
+		# Register : MSTR @ 0XFD070000

+
+		# Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 
+		# evice
+		# PSU_DDRC_MSTR_DEVICE_CONFIG                                                     0x1
+
+		# Choose which registers are used. - 0 - Original registers - 1 - Shadow registers
+		# PSU_DDRC_MSTR_FREQUENCY_MODE                                                    0x0
+
+		# Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
+		# esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - 
+		# ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
+		# ks - 1111 - Four ranks
+		# PSU_DDRC_MSTR_ACTIVE_RANKS                                                      0x1
+
+		# SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
+		#  of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls 
+		# he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
+		# -fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
+		#  is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
+		# PSU_DDRC_MSTR_BURST_RDWR                                                        0x4
+
+		# Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM 
+		# n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
+		# l_off_mode is not supported, and this bit must be set to '0'.
+		# PSU_DDRC_MSTR_DLL_OFF_MODE                                                      0x0
+
+		# Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
+		# AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
+		# dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
+		# figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).
+		# PSU_DDRC_MSTR_DATA_BUS_WIDTH                                                    0x0
+
+		# 1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
+		#  only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode 
+		# s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set
+		# PSU_DDRC_MSTR_GEARDOWN_MODE                                                     0x0
+
+		# If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held 
+		# or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in 
+		# PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
+		# ing is not supported in DDR4 geardown mode.
+		# PSU_DDRC_MSTR_EN_2T_TIMING_MODE                                                 0x0
+
+		# When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
+		# t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
+		#  (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
+		# _parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'
+		# PSU_DDRC_MSTR_BURSTCHOP                                                         0x0
+
+		# Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
+		# port LPDDR4.
+		# PSU_DDRC_MSTR_LPDDR4                                                            0x0
+
+		# Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support 
+		# DR4.
+		# PSU_DDRC_MSTR_DDR4                                                              0x1
+
+		# Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
+		# port LPDDR3.
+		# PSU_DDRC_MSTR_LPDDR3                                                            0x0
+
+		# Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
+		# port LPDDR2.
+		# PSU_DDRC_MSTR_LPDDR2                                                            0x0
+
+		# Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
+		# 
+		# PSU_DDRC_MSTR_DDR3                                                              0x0
+
+		# Master Register
+		#(OFFSET, MASK, VALUE)      (0XFD070000, 0xE30FBE3DU ,0x41040010U)  */
+    mask_write 0XFD070000 0xE30FBE3D 0x41040010
+		# Register : MRCTRL0 @ 0XFD070010

+
+		# Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
+		#  automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
+		# re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
+		# PSU_DDRC_MRCTRL0_MR_WR                                                          0x0
+
+		# Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
+		#  - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
+		# R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
+		# dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well 
+		# s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
+		# put Inversion of RDIMMs.
+		# PSU_DDRC_MRCTRL0_MR_ADDR                                                        0x0
+
+		# Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
+		#  However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
+		# amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks 
+		#  and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3
+		# PSU_DDRC_MRCTRL0_MR_RANK                                                        0x3
+
+		# Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. 
+		# or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
+		#  be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared 
+		# o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
+		# n is not allowed - 1 - Software intervention is allowed
+		# PSU_DDRC_MRCTRL0_SW_INIT_INT                                                    0x0
+
+		# Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
+		# PSU_DDRC_MRCTRL0_PDA_EN                                                         0x0
+
+		# Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
+		# PSU_DDRC_MRCTRL0_MPR_EN                                                         0x0
+
+		# Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
+		# d
+		# PSU_DDRC_MRCTRL0_MR_TYPE                                                        0x0
+
+		# Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i
+		# it_int - pda_en - mpr_en
+		#(OFFSET, MASK, VALUE)      (0XFD070010, 0x8000F03FU ,0x00000030U)  */
+    mask_write 0XFD070010 0x8000F03F 0x00000030
+		# Register : DERATEEN @ 0XFD070020

+
+		# Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
+		#  Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
+		# g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.
+		# PSU_DDRC_DERATEEN_RC_DERATE_VALUE                                               0x3
+
+		# Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
+		# r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
+		# PSU_DDRC_DERATEEN_DERATE_BYTE                                                   0x0
+
+		# Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
+		# 4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
+		# for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.
+		# PSU_DDRC_DERATEEN_DERATE_VALUE                                                  0x0
+
+		# Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
+		# Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
+		# mode.
+		# PSU_DDRC_DERATEEN_DERATE_ENABLE                                                 0x0
+
+		# Temperature Derate Enable Register
+		#(OFFSET, MASK, VALUE)      (0XFD070020, 0x000003F3U ,0x00000300U)  */
+    mask_write 0XFD070020 0x000003F3 0x00000300
+		# Register : DERATEINT @ 0XFD070024

+
+		# Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
+		# DR3/LPDDR4. This register must not be set to zero
+		# PSU_DDRC_DERATEINT_MR4_READ_INTERVAL                                            0x800000
+
+		# Temperature Derate Interval Register
+		#(OFFSET, MASK, VALUE)      (0XFD070024, 0xFFFFFFFFU ,0x00800000U)  */
+    mask_write 0XFD070024 0xFFFFFFFF 0x00800000
+		# Register : PWRCTL @ 0XFD070030

+
+		# Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
+		# r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 
+		#  - Allow transition from Self refresh state
+		# PSU_DDRC_PWRCTL_STAY_IN_SELFREF                                                 0x0
+
+		# A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
+		# M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
+		# are Exit from Self Refresh
+		# PSU_DDRC_PWRCTL_SELFREF_SW                                                      0x0
+
+		# When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
+		# st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For 
+		# on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
+		# DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
+		# PSU_DDRC_PWRCTL_MPSM_EN                                                         0x0
+
+		# Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
+		# is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
+		# 4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in 
+		# ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
+		# rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)
+		# PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE                                         0x0
+
+		# When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
+		# et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down 
+		# xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
+		#  should not be set to 1. FOR PERFORMANCE ONLY.
+		# PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN                                                0x0
+
+		# If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
+		# RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.
+		# PSU_DDRC_PWRCTL_POWERDOWN_EN                                                    0x0
+
+		# If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
+		# f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.
+		# PSU_DDRC_PWRCTL_SELFREF_EN                                                      0x0
+
+		# Low Power Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD070030, 0x0000007FU ,0x00000000U)  */
+    mask_write 0XFD070030 0x0000007F 0x00000000
+		# Register : PWRTMG @ 0XFD070034

+
+		# After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in 
+		# he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
+		# PSU_DDRC_PWRTMG_SELFREF_TO_X32                                                  0x40
+
+		# Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
+		# ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
+		# iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.
+		# PSU_DDRC_PWRTMG_T_DPD_X4096                                                     0x84
+
+		# After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
+		#  PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
+		# PSU_DDRC_PWRTMG_POWERDOWN_TO_X32                                                0x10
+
+		# Low Power Timing Register
+		#(OFFSET, MASK, VALUE)      (0XFD070034, 0x00FFFF1FU ,0x00408410U)  */
+    mask_write 0XFD070034 0x00FFFF1F 0x00408410
+		# Register : RFSHCTL0 @ 0XFD070050

+
+		# Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
+		# d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
+		#  It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
+		# may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
+		# om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.
+		# PSU_DDRC_RFSHCTL0_REFRESH_MARGIN                                                0x2
+
+		# If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
+		# 1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
+		#  would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
+		# HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
+		# formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
+		# ued to the uMCTL2. FOR PERFORMANCE ONLY.
+		# PSU_DDRC_RFSHCTL0_REFRESH_TO_X32                                                0x10
+
+		# The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
+		# reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
+		# reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
+		# RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
+		# . - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
+		# tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
+		# fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
+		# ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
+		# tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
+		# d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
+		# initiated update is complete.
+		# PSU_DDRC_RFSHCTL0_REFRESH_BURST                                                 0x0
+
+		# - 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
+		# t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
+		# support LPDDR2/LPDDR3/LPDDR4
+		# PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH                                              0x0
+
+		# Refresh Control Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070050, 0x00F1F1F4U ,0x00210000U)  */
+    mask_write 0XFD070050 0x00F1F1F4 0x00210000
+		# Register : RFSHCTL3 @ 0XFD070060

+
+		# Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
+		# ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
+		# orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
+		# self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in 
+		# uture version of the uMCTL2.
+		# PSU_DDRC_RFSHCTL3_REFRESH_MODE                                                  0x0
+
+		# Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value 
+		# s automatically updated when exiting reset, so it does not need to be toggled initially.
+		# PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL                                          0x0
+
+		# When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
+		# ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
+		# auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
+		# is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. 
+		# his register field is changeable on the fly.
+		# PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH                                              0x1
+
+		# Refresh Control Register 3
+		#(OFFSET, MASK, VALUE)      (0XFD070060, 0x00000073U ,0x00000001U)  */
+    mask_write 0XFD070060 0x00000073 0x00000001
+		# Register : RFSHTMG @ 0XFD070064

+
+		# tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
+		#  for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
+		# , this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should 
+		# e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
+		# ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
+		# programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
+		# TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.
+		# PSU_DDRC_RFSHTMG_T_RFC_NOM_X32                                                  0x82
+
+		# Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the 
+		# REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
+		#  - 0 - tREFBW parameter not used - 1 - tREFBW parameter used
+		# PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN                                               0x1
+
+		# tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
+		#  RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
+		# DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
+		#  per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
+		# equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
+		# opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.
+		# PSU_DDRC_RFSHTMG_T_RFC_MIN                                                      0x8b
+
+		# Refresh Timing Register
+		#(OFFSET, MASK, VALUE)      (0XFD070064, 0x0FFF83FFU ,0x0082808BU)  */
+    mask_write 0XFD070064 0x0FFF83FF 0x0082808B
+		# Register : ECCCFG0 @ 0XFD070070

+
+		# Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined
+		# PSU_DDRC_ECCCFG0_DIS_SCRUB                                                      0x1
+
+		# ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
+		#  use
+		# PSU_DDRC_ECCCFG0_ECC_MODE                                                       0x0
+
+		# ECC Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070070, 0x00000017U ,0x00000010U)  */
+    mask_write 0XFD070070 0x00000017 0x00000010
+		# Register : ECCCFG1 @ 0XFD070074

+
+		# Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
+		# ng, if ECCCFG1.data_poison_en=1
+		# PSU_DDRC_ECCCFG1_DATA_POISON_BIT                                                0x0
+
+		# Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers
+		# PSU_DDRC_ECCCFG1_DATA_POISON_EN                                                 0x0
+
+		# ECC Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070074, 0x00000003U ,0x00000000U)  */
+    mask_write 0XFD070074 0x00000003 0x00000000
+		# Register : CRCPARCTL1 @ 0XFD0700C4

+
+		# The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
+		# the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY 
+		# pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
+		# L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
+		# dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
+		# e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks
+		# PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT                                             0x10
+
+		# After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
+		# M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
+		# the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
+		# the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
+		# RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
+		#  handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
+		# rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
+		# ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in 
+		# he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is 
+		# one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in 
+		# PR Page 1 should be treated as 'Don't care'.
+		# PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW                                           0x1
+
+		# - 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
+		#  CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
+		#  disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)
+		# PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE                                     0x0
+
+		# CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
+		# d to support DDR4.
+		# PSU_DDRC_CRCPARCTL1_CRC_INC_DM                                                  0x0
+
+		# CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
+		#  CRC mode register setting in the DRAM.
+		# PSU_DDRC_CRCPARCTL1_CRC_ENABLE                                                  0x0
+
+		# C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of 
+		# /A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
+		# is register should be 1.
+		# PSU_DDRC_CRCPARCTL1_PARITY_ENABLE                                               0x0
+
+		# CRC Parity Control Register1
+		#(OFFSET, MASK, VALUE)      (0XFD0700C4, 0x3F000391U ,0x10000200U)  */
+    mask_write 0XFD0700C4 0x3F000391 0x10000200
+		# Register : CRCPARCTL2 @ 0XFD0700C8

+
+		# Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
+		#  - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
+		# er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
+		# PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX                                          0x40
+
+		# Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
+		# tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
+		# value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
+		# PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX                                          0x5
+
+		# Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
+		# ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
+		# er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
+		# les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
+		# or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
+		# ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
+		# max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
+		# bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
+		# + board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
+		# ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The 
+		# ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
+		# to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
+		#  Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
+		# PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
+		# _FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
+		# C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
+		# e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
+		#  bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
+		# H-6 Values of 0, 1 and 2 are illegal.
+		# PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4                                0x1f
+
+		# CRC Parity Control Register2
+		#(OFFSET, MASK, VALUE)      (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU)  */
+    mask_write 0XFD0700C8 0x01FF1F3F 0x0040051F
+		# Register : INIT0 @ 0XFD0700D0

+
+		# If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
+		#  in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
+		# ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
+		# r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported 
+		# or LPDDR4 in this version of the uMCTL2.
+		# PSU_DDRC_INIT0_SKIP_DRAM_INIT                                                   0x0
+
+		# Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires 
+		#  400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
+		# grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
+		# MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.
+		# PSU_DDRC_INIT0_POST_CKE_X1024                                                   0x2
+
+		# Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 
+		# pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
+		# tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
+		#  to next integer value.
+		# PSU_DDRC_INIT0_PRE_CKE_X1024                                                    0x106
+
+		# SDRAM Initialization Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U)  */
+    mask_write 0XFD0700D0 0xC3FF0FFF 0x00020106
+		# Register : INIT1 @ 0XFD0700D4

+
+		# Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
+		# LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1
+		# PSU_DDRC_INIT1_DRAM_RSTN_X1024                                                  0x2
+
+		# Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
+		# bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.
+		# PSU_DDRC_INIT1_FINAL_WAIT_X32                                                   0x0
+
+		# Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
+		# . There is no known specific requirement for this; it may be set to zero.
+		# PSU_DDRC_INIT1_PRE_OCD_X32                                                      0x0
+
+		# SDRAM Initialization Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD0700D4, 0x01FF7F0FU ,0x00020000U)  */
+    mask_write 0XFD0700D4 0x01FF7F0F 0x00020000
+		# Register : INIT2 @ 0XFD0700D8

+
+		# Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.
+		# PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32                                             0x23
+
+		# Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
+		# e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.
+		# PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1                                              0x5
+
+		# SDRAM Initialization Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD0700D8, 0x0000FF0FU ,0x00002305U)  */
+    mask_write 0XFD0700D8 0x0000FF0F 0x00002305
+		# Register : INIT3 @ 0XFD0700DC

+
+		# DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
+		#  DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
+		# register
+		# PSU_DDRC_INIT3_MR                                                               0x930
+
+		# DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
+		# bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
+		#  bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
+		# lue to write to MR2 register
+		# PSU_DDRC_INIT3_EMR                                                              0x301
+
+		# SDRAM Initialization Register 3
+		#(OFFSET, MASK, VALUE)      (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U)  */
+    mask_write 0XFD0700DC 0xFFFFFFFF 0x09300301
+		# Register : INIT4 @ 0XFD0700E0

+
+		# DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 
+		# egister mDDR: Unused
+		# PSU_DDRC_INIT4_EMR2                                                             0x20
+
+		# DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to 
+		# rite to MR13 register
+		# PSU_DDRC_INIT4_EMR3                                                             0x200
+
+		# SDRAM Initialization Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U)  */
+    mask_write 0XFD0700E0 0xFFFFFFFF 0x00200200
+		# Register : INIT5 @ 0XFD0700E4

+
+		# ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock 
+		# ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.
+		# PSU_DDRC_INIT5_DEV_ZQINIT_X32                                                   0x21
+
+		# Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
+		# 3 typically requires 10 us.
+		# PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024                                              0x4
+
+		# SDRAM Initialization Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD0700E4, 0x00FF03FFU ,0x00210004U)  */
+    mask_write 0XFD0700E4 0x00FF03FF 0x00210004
+		# Register : INIT6 @ 0XFD0700E8

+
+		# DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
+		# PSU_DDRC_INIT6_MR4                                                              0x0
+
+		# DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
+		# PSU_DDRC_INIT6_MR5                                                              0x6c0
+
+		# SDRAM Initialization Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U)  */
+    mask_write 0XFD0700E8 0xFFFFFFFF 0x000006C0
+		# Register : INIT7 @ 0XFD0700EC

+
+		# DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
+		# PSU_DDRC_INIT7_MR6                                                              0x819
+
+		# SDRAM Initialization Register 7
+		#(OFFSET, MASK, VALUE)      (0XFD0700EC, 0xFFFF0000U ,0x08190000U)  */
+    mask_write 0XFD0700EC 0xFFFF0000 0x08190000
+		# Register : DIMMCTL @ 0XFD0700F0

+
+		# Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
+		# ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
+		#  address mirroring is enabled.
+		# PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING                                          0x0
+
+		# Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
+		#  be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output 
+		# nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
+		# effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
+		# led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled
+		# PSU_DDRC_DIMMCTL_MRS_BG1_EN                                                     0x1
+
+		# Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
+		#  be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, 
+		# his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address 
+		# f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled
+		# PSU_DDRC_DIMMCTL_MRS_A17_EN                                                     0x0
+
+		# Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
+		# which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, 
+		# A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
+		# lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. 
+		# or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
+		#  has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
+		# ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.
+		# PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN                                             0x0
+
+		# Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
+		# 4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits 
+		# re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
+		# at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
+		# sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
+		#  swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
+		# ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
+		# or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
+		# hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
+		# ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
+		# not implement address mirroring
+		# PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN                                              0x0
+
+		# Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
+		# R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
+		# CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
+		#  each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses
+		# PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN                                             0x0
+
+		# DIMM Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD0700F0, 0x0000003FU ,0x00000010U)  */
+    mask_write 0XFD0700F0 0x0000003F 0x00000010
+		# Register : RANKCTL @ 0XFD0700F4

+
+		# Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
+		# e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
+		# nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
+		# ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
+		# ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed 
+		# n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
+		# ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
+		# or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
+		#  to the next integer.
+		# PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP                                               0x6
+
+		# Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
+		# e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
+		# sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
+		# p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
+		# ), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
+		# requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
+		# quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and 
+		# ound it up to the next integer.
+		# PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP                                               0x6
+
+		# Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
+		# nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
+		# on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
+		# -by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
+		# _rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
+		# om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
+		# ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to 
+		# llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
+		# ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as 
+		# ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
+		# . FOR PERFORMANCE ONLY.
+		# PSU_DDRC_RANKCTL_MAX_RANK_RD                                                    0xf
+
+		# Rank Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD0700F4, 0x00000FFFU ,0x0000066FU)  */
+    mask_write 0XFD0700F4 0x00000FFF 0x0000066F
+		# Register : DRAMTMG0 @ 0XFD070100

+
+		# Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles 
+		#  15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
+		#  value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
+		# Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this 
+		# arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
+		# with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
+		# PSU_DDRC_DRAMTMG0_WR2PRE                                                        0x11
+
+		# tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
+		# in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next 
+		# nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks
+		# PSU_DDRC_DRAMTMG0_T_FAW                                                         0xc
+
+		# tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
+		# imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
+		#  No rounding up. Unit: Multiples of 1024 clocks.
+		# PSU_DDRC_DRAMTMG0_T_RAS_MAX                                                     0x24
+
+		# tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, 
+		# rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
+		#  (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
+		# PSU_DDRC_DRAMTMG0_T_RAS_MIN                                                     0x12
+
+		# SDRAM Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070100, 0x7F3F7F3FU ,0x110C2412U)  */
+    mask_write 0XFD070100 0x7F3F7F3F 0x110C2412
+		# Register : DRAMTMG1 @ 0XFD070104

+
+		# tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
+		#  is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, 
+		# rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks
+		# PSU_DDRC_DRAMTMG1_T_XP                                                          0x4
+
+		# tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
+		# R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
+		# S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
+		# 2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
+		# gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
+		# e. Unit: Clocks.
+		# PSU_DDRC_DRAMTMG1_RD2PRE                                                        0x4
+
+		# tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
+		#  up to next integer value. Unit: Clocks.
+		# PSU_DDRC_DRAMTMG1_T_RC                                                          0x19
+
+		# SDRAM Timing Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070104, 0x001F1F7FU ,0x00040419U)  */
+    mask_write 0XFD070104 0x001F1F7F 0x00040419
+		# Register : DRAMTMG2 @ 0XFD070108

+
+		# Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
+		# t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
+		# tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
+		# equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
+		#  is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
+		# PSU_DDRC_DRAMTMG2_WRITE_LATENCY                                                 0x7
+
+		# Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
+		# using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For 
+		# onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
+		# er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
+		# s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
+		# PSU_DDRC_DRAMTMG2_READ_LATENCY                                                  0x8
+
+		# DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL 
+		# PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
+		# /2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
+		# time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = 
+		# urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
+		# tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
+		# DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
+		# gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
+		# PSU_DDRC_DRAMTMG2_RD2WR                                                         0x6
+
+		# DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
+		# k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
+		#  per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
+		#  length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
+		# d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
+		#  delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
+		# ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
+		# PSU_DDRC_DRAMTMG2_WR2RD                                                         0xe
+
+		# SDRAM Timing Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD070108, 0x3F3F3F3FU ,0x0708060EU)  */
+    mask_write 0XFD070108 0x3F3F3F3F 0x0708060E
+		# Register : DRAMTMG3 @ 0XFD07010C

+
+		# Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
+		#  LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW 
+		# nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
+		#  used for the time from a MRW/MRR to a MRW/MRR.
+		# PSU_DDRC_DRAMTMG3_T_MRW                                                         0x5
+
+		# tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time 
+		# rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
+		# nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
+		# 4 is used, set to tMRD_PAR(tMOD+PL) instead.
+		# PSU_DDRC_DRAMTMG3_T_MRD                                                         0x4
+
+		# tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
+		# y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
+		#  if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
+		#  + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.
+		# PSU_DDRC_DRAMTMG3_T_MOD                                                         0xc
+
+		# SDRAM Timing Register 3
+		#(OFFSET, MASK, VALUE)      (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU)  */
+    mask_write 0XFD07010C 0x3FF3F3FF 0x0050400C
+		# Register : DRAMTMG4 @ 0XFD070110

+
+		# tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
+		# am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
+		# lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
+		# PSU_DDRC_DRAMTMG4_T_RCD                                                         0x8
+
+		# DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
+		# time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
+		# d it up to the next integer value. Unit: clocks.
+		# PSU_DDRC_DRAMTMG4_T_CCD                                                         0x3
+
+		# DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
+		#  activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
+		# it up to the next integer value. Unit: Clocks.
+		# PSU_DDRC_DRAMTMG4_T_RRD                                                         0x3
+
+		# tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
+		# (tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
+		# 2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
+		# PSU_DDRC_DRAMTMG4_T_RP                                                          0x9
+
+		# SDRAM Timing Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD070110, 0x1F0F0F1FU ,0x08030309U)  */
+    mask_write 0XFD070110 0x1F0F0F1F 0x08030309
+		# Register : DRAMTMG5 @ 0XFD070114

+
+		# This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
+		# e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
+		# tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
+		# eger.
+		# PSU_DDRC_DRAMTMG5_T_CKSRX                                                       0x6
+
+		# This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
+		#  SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: 
+		# ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
+		# to next integer.
+		# PSU_DDRC_DRAMTMG5_T_CKSRE                                                       0x6
+
+		# Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
+		# tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE 
+		#  1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
+		# .
+		# PSU_DDRC_DRAMTMG5_T_CKESR                                                       0x4
+
+		# Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of 
+		# CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set 
+		# his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
+		#  next integer value. Unit: Clocks.
+		# PSU_DDRC_DRAMTMG5_T_CKE                                                         0x3
+
+		# SDRAM Timing Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD070114, 0x0F0F3F1FU ,0x06060403U)  */
+    mask_write 0XFD070114 0x0F0F3F1F 0x06060403
+		# Register : DRAMTMG6 @ 0XFD070118

+
+		# This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after 
+		# PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
+		# ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
+		# devices.
+		# PSU_DDRC_DRAMTMG6_T_CKDPDE                                                      0x1
+
+		# This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock 
+		# table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
+		# gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
+		# R or LPDDR2 devices.
+		# PSU_DDRC_DRAMTMG6_T_CKDPDX                                                      0x1
+
+		# This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the 
+		# lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
+		# 2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it 
+		# p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
+		# PSU_DDRC_DRAMTMG6_T_CKCSX                                                       0x4
+
+		# SDRAM Timing Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD070118, 0x0F0F000FU ,0x01010004U)  */
+    mask_write 0XFD070118 0x0F0F000F 0x01010004
+		# Register : DRAMTMG7 @ 0XFD07011C

+
+		# This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. 
+		# ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
+		# is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
+		# DDR2/LPDDR3/LPDDR4 devices.
+		# PSU_DDRC_DRAMTMG7_T_CKPDE                                                       0x1
+
+		# This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
+		# time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
+		# , program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
+		# g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
+		# PSU_DDRC_DRAMTMG7_T_CKPDX                                                       0x1
+
+		# SDRAM Timing Register 7
+		#(OFFSET, MASK, VALUE)      (0XFD07011C, 0x00000F0FU ,0x00000101U)  */
+    mask_write 0XFD07011C 0x00000F0F 0x00000101
+		# Register : DRAMTMG8 @ 0XFD070120

+
+		# tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
+		# O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
+		#  is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.
+		# PSU_DDRC_DRAMTMG8_T_XS_FAST_X32                                                 0x4
+
+		# tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
+		# ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: 
+		# nsure this is less than or equal to t_xs_x32.
+		# PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32                                                0x4
+
+		# tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the 
+		# bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and 
+		# DR4 SDRAMs.
+		# PSU_DDRC_DRAMTMG8_T_XS_DLL_X32                                                  0xd
+
+		# tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
+		# above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
+		# DDR4 SDRAMs.
+		# PSU_DDRC_DRAMTMG8_T_XS_X32                                                      0x6
+
+		# SDRAM Timing Register 8
+		#(OFFSET, MASK, VALUE)      (0XFD070120, 0x7F7F7F7FU ,0x04040D06U)  */
+    mask_write 0XFD070120 0x7F7F7F7F 0x04040D06
+		# Register : DRAMTMG9 @ 0XFD070124

+
+		# DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
+		# PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE                                              0x0
+
+		# tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' 
+		# o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
+		# nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.
+		# PSU_DDRC_DRAMTMG9_T_CCD_S                                                       0x2
+
+		# tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
+		# ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
+		# R4. Unit: Clocks.
+		# PSU_DDRC_DRAMTMG9_T_RRD_S                                                       0x2
+
+		# CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
+		# round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
+		#  Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
+		# d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
+		# is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using 
+		# he above equation by 2, and round it up to next integer.
+		# PSU_DDRC_DRAMTMG9_WR2RD_S                                                       0xb
+
+		# SDRAM Timing Register 9
+		#(OFFSET, MASK, VALUE)      (0XFD070124, 0x40070F3FU ,0x0002020BU)  */
+    mask_write 0XFD070124 0x40070F3F 0x0002020B
+		# Register : DRAMTMG11 @ 0XFD07012C

+
+		# tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
+		# this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
+		# ples of 32 clocks.
+		# PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32                                            0x6f
+
+		# tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
+		#  RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.
+		# PSU_DDRC_DRAMTMG11_T_MPX_LH                                                     0x7
+
+		# tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
+		# up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.
+		# PSU_DDRC_DRAMTMG11_T_MPX_S                                                      0x1
+
+		# tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
+		# r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
+		# teger.
+		# PSU_DDRC_DRAMTMG11_T_CKMPE                                                      0xe
+
+		# SDRAM Timing Register 11
+		#(OFFSET, MASK, VALUE)      (0XFD07012C, 0x7F1F031FU ,0x6F07010EU)  */
+    mask_write 0XFD07012C 0x7F1F031F 0x6F07010E
+		# Register : DRAMTMG12 @ 0XFD070130

+
+		# tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
+		# REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.
+		# PSU_DDRC_DRAMTMG12_T_CMDCKE                                                     0x2
+
+		# tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
+		# /2) and round it up to next integer value.
+		# PSU_DDRC_DRAMTMG12_T_CKEHCMD                                                    0x6
+
+		# tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
+		# s to (tMRD_PDA/2) and round it up to next integer value.
+		# PSU_DDRC_DRAMTMG12_T_MRD_PDA                                                    0x8
+
+		# SDRAM Timing Register 12
+		#(OFFSET, MASK, VALUE)      (0XFD070130, 0x00030F1FU ,0x00020608U)  */
+    mask_write 0XFD070130 0x00030F1F 0x00020608
+		# Register : ZQCTL0 @ 0XFD070180

+
+		# - 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
+		# ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
+		# ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		# PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ                                                     0x1
+
+		# - 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
+		# or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
+		# own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
+		# ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		# PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL                                                    0x0
+
+		# - 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
+		# nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
+		# rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		# PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED                                              0x0
+
+		# - 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable 
+		# ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
+		# gns supporting DDR4 devices.
+		# PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL                                                  0x0
+
+		# tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
+		# on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
+		# er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
+		# ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for 
+		# esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		# PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP                                                   0x100
+
+		# tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
+		# ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
+		# e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
+		# s.
+		# PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP                                                  0x40
+
+		# ZQ Control Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070180, 0xF7FF03FFU ,0x81000040U)  */
+    mask_write 0XFD070180 0xF7FF03FF 0x81000040
+		# Register : ZQCTL1 @ 0XFD070184

+
+		# tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
+		# ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is 
+		# nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
+		# PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP                                                  0x20
+
+		# Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
+		# PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs 
+		# upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		# PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024                                       0x19707
+
+		# ZQ Control Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070184, 0x3FFFFFFFU ,0x02019707U)  */
+    mask_write 0XFD070184 0x3FFFFFFF 0x02019707
+		# Register : DFITMG0 @ 0XFD070190

+
+		# Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
+		# s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
+		# , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
+		#  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
+		# PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY                                               0x4
+
+		# Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
+		# 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
+		# fer to PHY specification for correct value.
+		# PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR                                             0x1
+
+		# Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
+		# ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
+		# , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
+		#  latency through the RDIMM. Unit: Clocks
+		# PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN                                                0xb
+
+		# Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
+		# .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
+		# HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
+		# e.
+		# PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR                                             0x1
+
+		# Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
+		#  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
+		# te, max supported value is 8. Unit: Clocks
+		# PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA                                                0x2
+
+		# Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
+		#  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
+		#  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
+		# rough the RDIMM.
+		# PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT                                                 0xb
+
+		# DFI Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070190, 0x1FBFBF3FU ,0x048B820BU)  */
+    mask_write 0XFD070190 0x1FBFBF3F 0x048B820B
+		# Register : DFITMG1 @ 0XFD070194

+
+		# Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. 
+		# his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
+		# the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
+		# PSU_DDRC_DFITMG1_DFI_T_CMD_LAT                                                  0x0
+
+		# Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
+		#  is driven.
+		# PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT                                                0x0
+
+		# Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
+		# nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
+		#  correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to 
+		# phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
+		# RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
+		# : Clocks
+		# PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY                                             0x3
+
+		# Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to 
+		# he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase 
+		# ligned, this timing parameter should be rounded up to the next integer value.
+		# PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE                                         0x3
+
+		# Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first 
+		# alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
+		# not phase aligned, this timing parameter should be rounded up to the next integer value.
+		# PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE                                          0x4
+
+		# DFI Timing Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070194, 0xF31F0F0FU ,0x00030304U)  */
+    mask_write 0XFD070194 0xF31F0F0F 0x00030304
+		# Register : DFILPCFG0 @ 0XFD070198

+
+		# Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
+		# g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.
+		# PSU_DDRC_DFILPCFG0_DFI_TLP_RESP                                                 0x7
+
+		# Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
+		# cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
+		# - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 
+		# 31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
+		# .
+		# PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD                                            0x0
+
+		# Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
+		# nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.
+		# PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD                                                0x0
+
+		# Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
+		# les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 
+		# 048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
+		# 72 cycles - 0xE - 262144 cycles - 0xF - Unlimited
+		# PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR                                             0x0
+
+		# Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
+		# PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR                                                 0x1
+
+		# Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
+		# s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
+		# 8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
+		#  cycles - 0xE - 262144 cycles - 0xF - Unlimited
+		# PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD                                             0x4
+
+		# Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
+		# PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD                                                 0x1
+
+		# DFI Low Power Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070198, 0x0FF1F1F1U ,0x07000141U)  */
+    mask_write 0XFD070198 0x0FF1F1F1 0x07000141
+		# Register : DFILPCFG1 @ 0XFD07019C

+
+		# Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
+		# - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles 
+		#  0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
+		# D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.
+		# PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM                                           0x2
+
+		# Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
+		# only present for designs supporting DDR4 devices.
+		# PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM                                               0x1
+
+		# DFI Low Power Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD07019C, 0x000000F1U ,0x00000021U)  */
+    mask_write 0XFD07019C 0x000000F1 0x00000021
+		# Register : DFIUPD1 @ 0XFD0701A4

+
+		# This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
+		# ). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
+		# t read request when the uMCTL2 is idle. Unit: 1024 clocks
+		# PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024                               0x41
+
+		# This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; 
+		# hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
+		# idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
+		# e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
+		# Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
+		# 024. Unit: 1024 clocks
+		# PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024                               0xe2
+
+		# DFI Update Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD0701A4, 0x00FF00FFU ,0x004100E2U)  */
+    mask_write 0XFD0701A4 0x00FF00FF 0x004100E2
+		# Register : DFIMISC @ 0XFD0701B0

+
+		# Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high
+		# PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY                                           0x0
+
+		# DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
+		# in designs configured to support DDR4 and LPDDR4.
+		# PSU_DDRC_DFIMISC_PHY_DBI_MODE                                                   0x0
+
+		# PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
+		# ion
+		# PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN                                           0x0
+
+		# DFI Miscellaneous Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD0701B0, 0x00000007U ,0x00000000U)  */
+    mask_write 0XFD0701B0 0x00000007 0x00000000
+		# Register : DFITMG2 @ 0XFD0701B4

+
+		# >Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
+		# l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
+		# PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT                                               0x9
+
+		# Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
+		# l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
+		# PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT                                               0x6
+
+		# DFI Timing Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD0701B4, 0x00003F3FU ,0x00000906U)  */
+    mask_write 0XFD0701B4 0x00003F3F 0x00000906
+		# Register : DBICTL @ 0XFD0701C0

+
+		# Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
+		# as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
+		# PSU_DDRC_DBICTL_RD_DBI_EN                                                       0x0
+
+		# Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
+		# ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
+		# PSU_DDRC_DBICTL_WR_DBI_EN                                                       0x0
+
+		# DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
+		# mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
+		# : Set this to inverted value of MR13[5] which is opposite polarity from this signal
+		# PSU_DDRC_DBICTL_DM_EN                                                           0x1
+
+		# DM/DBI Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD0701C0, 0x00000007U ,0x00000001U)  */
+    mask_write 0XFD0701C0 0x00000007 0x00000001
+		# Register : ADDRMAP0 @ 0XFD070200

+
+		# Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
+		#  bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+		# PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0                                               0x1f
+
+		# Address Map Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070200, 0x0000001FU ,0x0000001FU)  */
+    mask_write 0XFD070200 0x0000001F 0x0000001F
+		# Register : ADDRMAP1 @ 0XFD070204

+
+		# Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
+		# bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.
+		# PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2                                               0x1f
+
+		# Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
+		# r each of the bank address bits is determined by adding the internal base to the value of this field.
+		# PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1                                               0xa
+
+		# Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
+		# r each of the bank address bits is determined by adding the internal base to the value of this field.
+		# PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0                                               0xa
+
+		# Address Map Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070204, 0x001F1F1FU ,0x001F0A0AU)  */
+    mask_write 0XFD070204 0x001F1F1F 0x001F0A0A
+		# Register : ADDRMAP2 @ 0XFD070208

+
+		# - Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
+		# s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
+		#  Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
+		#  this field. If set to 15, this column address bit is set to 0.
+		# PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5                                                0x0
+
+		# - Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
+		# s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
+		# Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
+		# this field. If set to 15, this column address bit is set to 0.
+		# PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4                                                0x0
+
+		# - Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
+		# s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
+		# Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
+		# ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
+		#  this case.
+		# PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3                                                0x0
+
+		# - Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
+		# s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
+		# Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
+		# ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.
+		# PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2                                                0x0
+
+		# Address Map Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD070208, 0x0F0F0F0FU ,0x00000000U)  */
+    mask_write 0XFD070208 0x0F0F0F0F 0x00000000
+		# Register : ADDRMAP3 @ 0XFD07020C

+
+		# - Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
+		# s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
+		# column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
+		#  determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: 
+		# er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
+		# ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
+		#  hence column bit 10 is used.
+		# PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9                                                0x0
+
+		# - Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
+		# s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
+		#  LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
+		# ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
+		# cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
+		# mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
+		# .
+		# PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8                                                0x0
+
+		# - Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
+		# s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
+		# Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
+		# this field. If set to 15, this column address bit is set to 0.
+		# PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7                                                0x0
+
+		# - Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
+		# s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
+		# Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
+		# this field. If set to 15, this column address bit is set to 0.
+		# PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6                                                0x0
+
+		# Address Map Register 3
+		#(OFFSET, MASK, VALUE)      (0XFD07020C, 0x0F0F0F0FU ,0x00000000U)  */
+    mask_write 0XFD07020C 0x0F0F0F0F 0x00000000
+		# Register : ADDRMAP4 @ 0XFD070210

+
+		# - Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
+		# mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must 
+		# e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
+		# l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
+		# n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
+		# dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
+		# PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11                                               0xf
+
+		# - Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
+		# mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
+		# To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
+		# termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
+		# JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
+		# bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
+		# nce column bit 10 is used.
+		# PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10                                               0xf
+
+		# Address Map Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD070210, 0x00000F0FU ,0x00000F0FU)  */
+    mask_write 0XFD070210 0x00000F0F 0x00000F0F
+		# Register : ADDRMAP5 @ 0XFD070214

+
+		# Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
+		# s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.
+		# PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11                                               0x8
+
+		# Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
+		# bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF 
+		# ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value 
+		# 5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
+		# PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10                                             0xf
+
+		# Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
+		#  each of the row address bits is determined by adding the internal base to the value of this field.
+		# PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1                                                0x8
+
+		# Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
+		#  each of the row address bits is determined by adding the internal base to the value of this field.
+		# PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0                                                0x8
+
+		# Address Map Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD070214, 0x0F0F0F0FU ,0x080F0808U)  */
+    mask_write 0XFD070214 0x0F0F0F0F 0x080F0808
+		# Register : ADDRMAP6 @ 0XFD070218

+
+		# Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
+		# having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
+		# y in designs configured to support LPDDR3.
+		# PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB                                               0x0
+
+		# Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
+		# s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.
+		# PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15                                               0xf
+
+		# Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
+		# s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.
+		# PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14                                               0x8
+
+		# Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
+		# s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.
+		# PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13                                               0x8
+
+		# Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
+		# s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.
+		# PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12                                               0x8
+
+		# Address Map Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD070218, 0x8F0F0F0FU ,0x0F080808U)  */
+    mask_write 0XFD070218 0x8F0F0F0F 0x0F080808
+		# Register : ADDRMAP7 @ 0XFD07021C

+
+		# Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
+		# s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.
+		# PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17                                               0xf
+
+		# Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
+		# s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.
+		# PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16                                               0xf
+
+		# Address Map Register 7
+		#(OFFSET, MASK, VALUE)      (0XFD07021C, 0x00000F0FU ,0x00000F0FU)  */
+    mask_write 0XFD07021C 0x00000F0F 0x00000F0F
+		# Register : ADDRMAP8 @ 0XFD070220

+
+		# Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
+		# address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If 
+		# et to 31, bank group address bit 1 is set to 0.
+		# PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1                                                 0x8
+
+		# Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
+		# bit for each of the bank group address bits is determined by adding the internal base to the value of this field.
+		# PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0                                                 0x8
+
+		# Address Map Register 8
+		#(OFFSET, MASK, VALUE)      (0XFD070220, 0x00001F1FU ,0x00000808U)  */
+    mask_write 0XFD070220 0x00001F1F 0x00000808
+		# Register : ADDRMAP9 @ 0XFD070224

+
+		# Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
+		# r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		# ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		# PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5                                                0x8
+
+		# Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
+		# r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		# ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		# PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4                                                0x8
+
+		# Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
+		#  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
+		# d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		# PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3                                                0x8
+
+		# Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
+		#  each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
+		# d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		# PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2                                                0x8
+
+		# Address Map Register 9
+		#(OFFSET, MASK, VALUE)      (0XFD070224, 0x0F0F0F0FU ,0x08080808U)  */
+    mask_write 0XFD070224 0x0F0F0F0F 0x08080808
+		# Register : ADDRMAP10 @ 0XFD070228

+
+		# Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
+		# r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		# ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		# PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9                                               0x8
+
+		# Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
+		# r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		# ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		# PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8                                               0x8
+
+		# Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
+		# r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		# ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		# PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7                                               0x8
+
+		# Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
+		# r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		# ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		# PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6                                               0x8
+
+		# Address Map Register 10
+		#(OFFSET, MASK, VALUE)      (0XFD070228, 0x0F0F0F0FU ,0x08080808U)  */
+    mask_write 0XFD070228 0x0F0F0F0F 0x08080808
+		# Register : ADDRMAP11 @ 0XFD07022C

+
+		# Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit 
+		# or each of the row address bits is determined by adding the internal base to the value of this field. This register field is 
+		# sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		# PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10                                              0x8
+
+		# Address Map Register 11
+		#(OFFSET, MASK, VALUE)      (0XFD07022C, 0x0000000FU ,0x00000008U)  */
+    mask_write 0XFD07022C 0x0000000F 0x00000008
+		# Register : ODTCFG @ 0XFD070240

+
+		# Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
+		# 67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - 
+		# L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 
+		# CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
+		# PSU_DDRC_ODTCFG_WR_ODT_HOLD                                                     0x6
+
+		# The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
+		# remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
+		# 67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
+		#  DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
+		# PSU_DDRC_ODTCFG_WR_ODT_DELAY                                                    0x0
+
+		# Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
+		#  0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
+		# tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
+		# )
+		# PSU_DDRC_ODTCFG_RD_ODT_HOLD                                                     0x6
+
+		# The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must 
+		# emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
+		# CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
+		# L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
+		# write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
+		# uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
+		# PSU_DDRC_ODTCFG_RD_ODT_DELAY                                                    0x0
+
+		# ODT Configuration Register
+		#(OFFSET, MASK, VALUE)      (0XFD070240, 0x0F1F0F7CU ,0x06000600U)  */
+    mask_write 0XFD070240 0x0F1F0F7C 0x06000600
+		# Register : ODTMAP @ 0XFD070244

+
+		# Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can 
+		# e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
+		#  etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
+		# PSU_DDRC_ODTMAP_RANK1_RD_ODT                                                    0x0
+
+		# Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
+		#  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
+		# etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
+		# PSU_DDRC_ODTMAP_RANK1_WR_ODT                                                    0x0
+
+		# Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can 
+		# e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
+		#  etc. For each rank, set its bit to 1 to enable its ODT.
+		# PSU_DDRC_ODTMAP_RANK0_RD_ODT                                                    0x0
+
+		# Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
+		#  turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
+		# etc. For each rank, set its bit to 1 to enable its ODT.
+		# PSU_DDRC_ODTMAP_RANK0_WR_ODT                                                    0x1
+
+		# ODT/Rank Map Register
+		#(OFFSET, MASK, VALUE)      (0XFD070244, 0x00003333U ,0x00000001U)  */
+    mask_write 0XFD070244 0x00003333 0x00000001
+		# Register : SCHED @ 0XFD070250

+
+		# When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
+		# non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
+		# ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this 
+		# egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. 
+		# OR PERFORMANCE ONLY
+		# PSU_DDRC_SCHED_RDWR_IDLE_GAP                                                    0x1
+
+		# UNUSED
+		# PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS                                           0x0
+
+		# Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
+		#  the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
+		# to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
+		# priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
+		#  than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
+		# sing out of single bit error correction RMW operation.
+		# PSU_DDRC_SCHED_LPR_NUM_ENTRIES                                                  0x20
+
+		# If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
+		# e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this 
+		# egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
+		# es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed 
+		# s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
+		# ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open 
+		# age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
+		# ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.
+		# PSU_DDRC_SCHED_PAGECLOSE                                                        0x0
+
+		# If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
+		# PSU_DDRC_SCHED_PREFER_WRITE                                                     0x0
+
+		# Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
+		# ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
+		# e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
+		# ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.
+		# PSU_DDRC_SCHED_FORCE_LOW_PRI_N                                                  0x1
+
+		# Scheduler Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD070250, 0x7FFF3F07U ,0x01002001U)  */
+    mask_write 0XFD070250 0x7FFF3F07 0x01002001
+		# Register : PERFLPR1 @ 0XFD070264

+
+		# Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
+		#  transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
+		# PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH                                           0x8
+
+		# Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
+		# er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
+		# be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
+		# PSU_DDRC_PERFLPR1_LPR_MAX_STARVE                                                0x40
+
+		# Low Priority Read CAM Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070264, 0xFF00FFFFU ,0x08000040U)  */
+    mask_write 0XFD070264 0xFF00FFFF 0x08000040
+		# Register : PERFWR1 @ 0XFD07026C

+
+		# Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
+		# transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
+		# PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH                                              0x8
+
+		# Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
+		# r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not 
+		# e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
+		# PSU_DDRC_PERFWR1_W_MAX_STARVE                                                   0x40
+
+		# Write CAM Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD07026C, 0xFF00FFFFU ,0x08000040U)  */
+    mask_write 0XFD07026C 0xFF00FFFF 0x08000040
+		# Register : DQMAP5 @ 0XFD070294

+
+		# All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
+		# all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and 
+		# wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
+		# port DDR4.
+		# PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP                                                0x1
+
+		# DQ Map Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD070294, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFD070294 0x00000001 0x00000001
+		# Register : DBG0 @ 0XFD070300

+
+		# When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
+		# lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
+		# s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.
+		# PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT                                            0x0
+
+		# When 1, disable write combine. FOR DEBUG ONLY
+		# PSU_DDRC_DBG0_DIS_WC                                                            0x0
+
+		# Debug Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070300, 0x00000011U ,0x00000000U)  */
+    mask_write 0XFD070300 0x00000011 0x00000000
+		# Register : DBGCMD @ 0XFD07030C

+
+		# Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
+		# the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
+		# register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
+		# _refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
+		#  and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).
+		# PSU_DDRC_DBGCMD_HW_REF_ZQ_EN                                                    0x0
+
+		# Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in 
+		# he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
+		# PSU_DDRC_DBGCMD_CTRLUPD                                                         0x0
+
+		# Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to 
+		# he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
+		# en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
+		# d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
+		# de.
+		# PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT                                                  0x0
+
+		# Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
+		# refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
+		# be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
+		# wn operating modes or Maximum Power Saving Mode.
+		# PSU_DDRC_DBGCMD_RANK1_REFRESH                                                   0x0
+
+		# Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
+		# refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
+		# be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
+		# wn operating modes or Maximum Power Saving Mode.
+		# PSU_DDRC_DBGCMD_RANK0_REFRESH                                                   0x0
+
+		# Command Debug Register
+		#(OFFSET, MASK, VALUE)      (0XFD07030C, 0x80000033U ,0x00000000U)  */
+    mask_write 0XFD07030C 0x80000033 0x00000000
+		# Register : SWCTL @ 0XFD070320

+
+		# Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back 
+		# egister to 1 once programming is done.
+		# PSU_DDRC_SWCTL_SW_DONE                                                          0x0
+
+		# Software register programming control enable
+		#(OFFSET, MASK, VALUE)      (0XFD070320, 0x00000001U ,0x00000000U)  */
+    mask_write 0XFD070320 0x00000001 0x00000000
+		# Register : PCCFG @ 0XFD070400

+
+		# Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
+		# e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
+		# h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
+		# ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
+		# _mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
+		# ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
+		# DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
+		# only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
+		# -AC is enabled
+		# PSU_DDRC_PCCFG_BL_EXP_MODE                                                      0x0
+
+		# Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
+		# rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
+		# ge DDRC transactions.
+		# PSU_DDRC_PCCFG_PAGEMATCH_LIMIT                                                  0x0
+
+		# If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based 
+		# n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
+		# _lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
+		# PSU_DDRC_PCCFG_GO2CRITICAL_EN                                                   0x1
+
+		# Port Common Configuration Register
+		#(OFFSET, MASK, VALUE)      (0XFD070400, 0x00000111U ,0x00000001U)  */
+    mask_write 0XFD070400 0x00000111 0x00000001
+		# Register : PCFGR_0 @ 0XFD070404

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		# If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		# o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		# ess handshaking (it is not associated with any particular command).
+		# PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the read channel of the port.
+		# PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		# ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		# he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		# will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		# ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		# aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		# ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		# ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		# RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		# he two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Read Register
+		#(OFFSET, MASK, VALUE)      (0XFD070404, 0x000073FFU ,0x0000200FU)  */
+    mask_write 0XFD070404 0x000073FF 0x0000200F
+		# Register : PCFGW_0 @ 0XFD070408

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		# If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		#  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		# not associated with any particular command).
+		# PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the write channel of the port.
+		# PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		# rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		# The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		# s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		#  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		#  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		# ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		# ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Write Register
+		#(OFFSET, MASK, VALUE)      (0XFD070408, 0x000073FFU ,0x0000600FU)  */
+    mask_write 0XFD070408 0x000073FF 0x0000600F
+		# Register : PCTRL_0 @ 0XFD070490

+
+		# Enables port n.
+		# PSU_DDRC_PCTRL_0_PORT_EN                                                        0x1
+
+		# Port n Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD070490, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFD070490 0x00000001 0x00000001
+		# Register : PCFGQOS0_0 @ 0XFD070494

+
+		# This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		# gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		# disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1                                            0x2
+
+		# This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		# urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		#  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0                                            0x0
+
+		# Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		# al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		# ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		#  values.
+		# PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1                                             0xb
+
+		# Port n Read QoS Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070494, 0x0033000FU ,0x0020000BU)  */
+    mask_write 0XFD070494 0x0033000F 0x0020000B
+		# Register : PCFGQOS1_0 @ 0XFD070498

+
+		# Specifies the timeout value for transactions mapped to the red address queue.
+		# PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR                                           0x0
+
+		# Specifies the timeout value for transactions mapped to the blue address queue.
+		# PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB                                           0x0
+
+		# Port n Read QoS Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070498, 0x07FF07FFU ,0x00000000U)  */
+    mask_write 0XFD070498 0x07FF07FF 0x00000000
+		# Register : PCFGR_1 @ 0XFD0704B4

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		# If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		# o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		# ess handshaking (it is not associated with any particular command).
+		# PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the read channel of the port.
+		# PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		# ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		# he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		# will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		# ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		# aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		# ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		# ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		# RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		# he two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Read Register
+		#(OFFSET, MASK, VALUE)      (0XFD0704B4, 0x000073FFU ,0x0000200FU)  */
+    mask_write 0XFD0704B4 0x000073FF 0x0000200F
+		# Register : PCFGW_1 @ 0XFD0704B8

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		# If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		#  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		# not associated with any particular command).
+		# PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the write channel of the port.
+		# PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		# rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		# The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		# s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		#  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		#  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		# ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		# ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Write Register
+		#(OFFSET, MASK, VALUE)      (0XFD0704B8, 0x000073FFU ,0x0000600FU)  */
+    mask_write 0XFD0704B8 0x000073FF 0x0000600F
+		# Register : PCTRL_1 @ 0XFD070540

+
+		# Enables port n.
+		# PSU_DDRC_PCTRL_1_PORT_EN                                                        0x1
+
+		# Port n Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD070540, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFD070540 0x00000001 0x00000001
+		# Register : PCFGQOS0_1 @ 0XFD070544

+
+		# This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 
+		# ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 
+		# s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2                                            0x2
+
+		# This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		# gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		# disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1                                            0x0
+
+		# This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		# urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		#  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0                                            0x0
+
+		# Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
+		# el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
+		# directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 
+		# ust be set to distinct values.
+		# PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2                                             0xb
+
+		# Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		# al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		# ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		#  values.
+		# PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1                                             0x3
+
+		# Port n Read QoS Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070544, 0x03330F0FU ,0x02000B03U)  */
+    mask_write 0XFD070544 0x03330F0F 0x02000B03
+		# Register : PCFGQOS1_1 @ 0XFD070548

+
+		# Specifies the timeout value for transactions mapped to the red address queue.
+		# PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR                                           0x0
+
+		# Specifies the timeout value for transactions mapped to the blue address queue.
+		# PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB                                           0x0
+
+		# Port n Read QoS Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070548, 0x07FF07FFU ,0x00000000U)  */
+    mask_write 0XFD070548 0x07FF07FF 0x00000000
+		# Register : PCFGR_2 @ 0XFD070564

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		# If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		# o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		# ess handshaking (it is not associated with any particular command).
+		# PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the read channel of the port.
+		# PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		# ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		# he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		# will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		# ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		# aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		# ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		# ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		# RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		# he two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Read Register
+		#(OFFSET, MASK, VALUE)      (0XFD070564, 0x000073FFU ,0x0000200FU)  */
+    mask_write 0XFD070564 0x000073FF 0x0000200F
+		# Register : PCFGW_2 @ 0XFD070568

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		# If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		#  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		# not associated with any particular command).
+		# PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the write channel of the port.
+		# PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		# rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		# The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		# s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		#  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		#  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		# ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		# ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Write Register
+		#(OFFSET, MASK, VALUE)      (0XFD070568, 0x000073FFU ,0x0000600FU)  */
+    mask_write 0XFD070568 0x000073FF 0x0000600F
+		# Register : PCTRL_2 @ 0XFD0705F0

+
+		# Enables port n.
+		# PSU_DDRC_PCTRL_2_PORT_EN                                                        0x1
+
+		# Port n Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD0705F0, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFD0705F0 0x00000001 0x00000001
+		# Register : PCFGQOS0_2 @ 0XFD0705F4

+
+		# This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 
+		# ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 
+		# s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2                                            0x2
+
+		# This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		# gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		# disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1                                            0x0
+
+		# This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		# urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		#  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0                                            0x0
+
+		# Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
+		# el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
+		# directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 
+		# ust be set to distinct values.
+		# PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2                                             0xb
+
+		# Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		# al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		# ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		#  values.
+		# PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1                                             0x3
+
+		# Port n Read QoS Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD0705F4, 0x03330F0FU ,0x02000B03U)  */
+    mask_write 0XFD0705F4 0x03330F0F 0x02000B03
+		# Register : PCFGQOS1_2 @ 0XFD0705F8

+
+		# Specifies the timeout value for transactions mapped to the red address queue.
+		# PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR                                           0x0
+
+		# Specifies the timeout value for transactions mapped to the blue address queue.
+		# PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB                                           0x0
+
+		# Port n Read QoS Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD0705F8, 0x07FF07FFU ,0x00000000U)  */
+    mask_write 0XFD0705F8 0x07FF07FF 0x00000000
+		# Register : PCFGR_3 @ 0XFD070614

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		# If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		# o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		# ess handshaking (it is not associated with any particular command).
+		# PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the read channel of the port.
+		# PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		# ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		# he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		# will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		# ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		# aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		# ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		# ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		# RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		# he two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Read Register
+		#(OFFSET, MASK, VALUE)      (0XFD070614, 0x000073FFU ,0x0000200FU)  */
+    mask_write 0XFD070614 0x000073FF 0x0000200F
+		# Register : PCFGW_3 @ 0XFD070618

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		# If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		#  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		# not associated with any particular command).
+		# PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the write channel of the port.
+		# PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		# rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		# The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		# s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		#  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		#  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		# ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		# ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Write Register
+		#(OFFSET, MASK, VALUE)      (0XFD070618, 0x000073FFU ,0x0000600FU)  */
+    mask_write 0XFD070618 0x000073FF 0x0000600F
+		# Register : PCTRL_3 @ 0XFD0706A0

+
+		# Enables port n.
+		# PSU_DDRC_PCTRL_3_PORT_EN                                                        0x1
+
+		# Port n Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD0706A0, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFD0706A0 0x00000001 0x00000001
+		# Register : PCFGQOS0_3 @ 0XFD0706A4

+
+		# This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		# gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		# disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1                                            0x1
+
+		# This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		# urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		#  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0                                            0x0
+
+		# Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		# al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		# ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		#  values.
+		# PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1                                             0x3
+
+		# Port n Read QoS Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD0706A4, 0x0033000FU ,0x00100003U)  */
+    mask_write 0XFD0706A4 0x0033000F 0x00100003
+		# Register : PCFGQOS1_3 @ 0XFD0706A8

+
+		# Specifies the timeout value for transactions mapped to the red address queue.
+		# PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR                                           0x0
+
+		# Specifies the timeout value for transactions mapped to the blue address queue.
+		# PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB                                           0x4f
+
+		# Port n Read QoS Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD0706A8, 0x07FF07FFU ,0x0000004FU)  */
+    mask_write 0XFD0706A8 0x07FF07FF 0x0000004F
+		# Register : PCFGWQOS0_3 @ 0XFD0706AC

+
+		# This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		# VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
+		# PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1                                           0x1
+
+		# This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		# VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
+		# PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0                                           0x0
+
+		# Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		# rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		# s to higher port priority.
+		# PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL                                             0x3
+
+		# Port n Write QoS Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD0706AC, 0x0033000FU ,0x00100003U)  */
+    mask_write 0XFD0706AC 0x0033000F 0x00100003
+		# Register : PCFGWQOS1_3 @ 0XFD0706B0

+
+		# Specifies the timeout value for write transactions.
+		# PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT                                           0x4f
+
+		# Port n Write QoS Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD0706B0, 0x000007FFU ,0x0000004FU)  */
+    mask_write 0XFD0706B0 0x000007FF 0x0000004F
+		# Register : PCFGR_4 @ 0XFD0706C4

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN                                           0x1
+
+		# If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		# o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		# ess handshaking (it is not associated with any particular command).
+		# PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the read channel of the port.
+		# PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		# ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		# he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		# will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		# ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		# aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		# ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		# ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		# RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		# he two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Read Register
+		#(OFFSET, MASK, VALUE)      (0XFD0706C4, 0x000073FFU ,0x0000600FU)  */
+    mask_write 0XFD0706C4 0x000073FF 0x0000600F
+		# Register : PCFGW_4 @ 0XFD0706C8

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		# If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		#  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		# not associated with any particular command).
+		# PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the write channel of the port.
+		# PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		# rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		# The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		# s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		#  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		#  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		# ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		# ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Write Register
+		#(OFFSET, MASK, VALUE)      (0XFD0706C8, 0x000073FFU ,0x0000600FU)  */
+    mask_write 0XFD0706C8 0x000073FF 0x0000600F
+		# Register : PCTRL_4 @ 0XFD070750

+
+		# Enables port n.
+		# PSU_DDRC_PCTRL_4_PORT_EN                                                        0x1
+
+		# Port n Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD070750, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFD070750 0x00000001 0x00000001
+		# Register : PCFGQOS0_4 @ 0XFD070754

+
+		# This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		# gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		# disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1                                            0x1
+
+		# This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		# urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		#  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0                                            0x0
+
+		# Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		# al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		# ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		#  values.
+		# PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1                                             0x3
+
+		# Port n Read QoS Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070754, 0x0033000FU ,0x00100003U)  */
+    mask_write 0XFD070754 0x0033000F 0x00100003
+		# Register : PCFGQOS1_4 @ 0XFD070758

+
+		# Specifies the timeout value for transactions mapped to the red address queue.
+		# PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR                                           0x0
+
+		# Specifies the timeout value for transactions mapped to the blue address queue.
+		# PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB                                           0x4f
+
+		# Port n Read QoS Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070758, 0x07FF07FFU ,0x0000004FU)  */
+    mask_write 0XFD070758 0x07FF07FF 0x0000004F
+		# Register : PCFGWQOS0_4 @ 0XFD07075C

+
+		# This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		# VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
+		# PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1                                           0x1
+
+		# This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		# VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
+		# PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0                                           0x0
+
+		# Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		# rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		# s to higher port priority.
+		# PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL                                             0x3
+
+		# Port n Write QoS Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD07075C, 0x0033000FU ,0x00100003U)  */
+    mask_write 0XFD07075C 0x0033000F 0x00100003
+		# Register : PCFGWQOS1_4 @ 0XFD070760

+
+		# Specifies the timeout value for write transactions.
+		# PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT                                           0x4f
+
+		# Port n Write QoS Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070760, 0x000007FFU ,0x0000004FU)  */
+    mask_write 0XFD070760 0x000007FF 0x0000004F
+		# Register : PCFGR_5 @ 0XFD070774

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		# If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		# o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		# ess handshaking (it is not associated with any particular command).
+		# PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the read channel of the port.
+		# PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		# ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		# he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		# will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		# ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		# aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		# ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		# ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		# RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		# he two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Read Register
+		#(OFFSET, MASK, VALUE)      (0XFD070774, 0x000073FFU ,0x0000200FU)  */
+    mask_write 0XFD070774 0x000073FF 0x0000200F
+		# Register : PCFGW_5 @ 0XFD070778

+
+		# If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		# d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		# imit register.
+		# PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		# If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		#  becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		#  Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		# not associated with any particular command).
+		# PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN                                              0x1
+
+		# If set to 1, enables aging function for the write channel of the port.
+		# PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN                                               0x0
+
+		# Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		# rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		# The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		# s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		#  the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		#  be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		# ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		# ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		# PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY                                               0xf
+
+		# Port n Configuration Write Register
+		#(OFFSET, MASK, VALUE)      (0XFD070778, 0x000073FFU ,0x0000600FU)  */
+    mask_write 0XFD070778 0x000073FF 0x0000600F
+		# Register : PCTRL_5 @ 0XFD070800

+
+		# Enables port n.
+		# PSU_DDRC_PCTRL_5_PORT_EN                                                        0x1
+
+		# Port n Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD070800, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFD070800 0x00000001 0x00000001
+		# Register : PCFGQOS0_5 @ 0XFD070804

+
+		# This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		# gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		# disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1                                            0x1
+
+		# This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		# urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		#  disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		# PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0                                            0x0
+
+		# Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		# al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		# ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		#  values.
+		# PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1                                             0x3
+
+		# Port n Read QoS Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD070804, 0x0033000FU ,0x00100003U)  */
+    mask_write 0XFD070804 0x0033000F 0x00100003
+		# Register : PCFGQOS1_5 @ 0XFD070808

+
+		# Specifies the timeout value for transactions mapped to the red address queue.
+		# PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR                                           0x0
+
+		# Specifies the timeout value for transactions mapped to the blue address queue.
+		# PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB                                           0x4f
+
+		# Port n Read QoS Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070808, 0x07FF07FFU ,0x0000004FU)  */
+    mask_write 0XFD070808 0x07FF07FF 0x0000004F
+		# Register : PCFGWQOS0_5 @ 0XFD07080C

+
+		# This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		# VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
+		# PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1                                           0x1
+
+		# This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		# VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
+		# PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0                                           0x0
+
+		# Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		# rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		# s to higher port priority.
+		# PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL                                             0x3
+
+		# Port n Write QoS Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD07080C, 0x0033000FU ,0x00100003U)  */
+    mask_write 0XFD07080C 0x0033000F 0x00100003
+		# Register : PCFGWQOS1_5 @ 0XFD070810

+
+		# Specifies the timeout value for write transactions.
+		# PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT                                           0x4f
+
+		# Port n Write QoS Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD070810, 0x000007FFU ,0x0000004FU)  */
+    mask_write 0XFD070810 0x000007FF 0x0000004F
+		# Register : SARBASE0 @ 0XFD070F04

+
+		# Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
+		#  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
+		# PSU_DDRC_SARBASE0_BASE_ADDR                                                     0x0
+
+		# SAR Base Address Register n
+		#(OFFSET, MASK, VALUE)      (0XFD070F04, 0x000001FFU ,0x00000000U)  */
+    mask_write 0XFD070F04 0x000001FF 0x00000000
+		# Register : SARSIZE0 @ 0XFD070F08

+
+		# Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
+		# e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 
+		# or example, if register is programmed to 0, region will have 1 block.
+		# PSU_DDRC_SARSIZE0_NBLOCKS                                                       0x0
+
+		# SAR Size Register n
+		#(OFFSET, MASK, VALUE)      (0XFD070F08, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFD070F08 0x000000FF 0x00000000
+		# Register : SARBASE1 @ 0XFD070F0C

+
+		# Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
+		#  by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
+		# PSU_DDRC_SARBASE1_BASE_ADDR                                                     0x10
+
+		# SAR Base Address Register n
+		#(OFFSET, MASK, VALUE)      (0XFD070F0C, 0x000001FFU ,0x00000010U)  */
+    mask_write 0XFD070F0C 0x000001FF 0x00000010
+		# Register : SARSIZE1 @ 0XFD070F10

+
+		# Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
+		# e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 
+		# or example, if register is programmed to 0, region will have 1 block.
+		# PSU_DDRC_SARSIZE1_NBLOCKS                                                       0xf
+
+		# SAR Size Register n
+		#(OFFSET, MASK, VALUE)      (0XFD070F10, 0x000000FFU ,0x0000000FU)  */
+    mask_write 0XFD070F10 0x000000FF 0x0000000F
+		# Register : DFITMG0_SHADOW @ 0XFD072190

+
+		# Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
+		# s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
+		# , this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
+		#  this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
+		# PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY                                        0x7
+
+		# Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
+		# 0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
+		# fer to PHY specification for correct value.
+		# PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR                                      0x1
+
+		# Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
+		# ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
+		# , it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
+		#  latency through the RDIMM. Unit: Clocks
+		# PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN                                         0x2
+
+		# Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
+		# .dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
+		# HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
+		# e.
+		# PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR                                      0x1
+
+		# Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
+		#  dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
+		# te, max supported value is 8. Unit: Clocks
+		# PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA                                         0x0
+
+		# Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
+		#  parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
+		#  necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
+		# rough the RDIMM.
+		# PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT                                          0x2
+
+		# DFI Timing Shadow Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD072190, 0x1FBFBF3FU ,0x07828002U)  */
+    mask_write 0XFD072190 0x1FBFBF3F 0x07828002
+		# : DDR CONTROLLER RESET
+		# Register : RST_DDR_SS @ 0XFD1A0108

+
+		# DDR block level reset inside of the DDR Sub System
+		# PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X0
+
+		# DDR sub system block level reset
+		#(OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000000U)  */
+    mask_write 0XFD1A0108 0x00000008 0x00000000
+		# : DDR PHY
+		# Register : PGCR0 @ 0XFD080010

+
+		# Address Copy
+		# PSU_DDR_PHY_PGCR0_ADCP                                                          0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_PGCR0_RESERVED_30_27                                                0x0
+
+		# PHY FIFO Reset
+		# PSU_DDR_PHY_PGCR0_PHYFRST                                                       0x1
+
+		# Oscillator Mode Address/Command Delay Line Select
+		# PSU_DDR_PHY_PGCR0_OSCACDL                                                       0x3
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_PGCR0_RESERVED_23_19                                                0x0
+
+		# Digital Test Output Select
+		# PSU_DDR_PHY_PGCR0_DTOSEL                                                        0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_PGCR0_RESERVED_13                                                   0x0
+
+		# Oscillator Mode Division
+		# PSU_DDR_PHY_PGCR0_OSCDIV                                                        0xf
+
+		# Oscillator Enable
+		# PSU_DDR_PHY_PGCR0_OSCEN                                                         0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_PGCR0_RESERVED_7_0                                                  0x0
+
+		# PHY General Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080010, 0xFFFFFFFFU ,0x07001E00U)  */
+    mask_write 0XFD080010 0xFFFFFFFF 0x07001E00
+		# Register : PGCR2 @ 0XFD080018

+
+		# Clear Training Status Registers
+		# PSU_DDR_PHY_PGCR2_CLRTSTAT                                                      0x0
+
+		# Clear Impedance Calibration
+		# PSU_DDR_PHY_PGCR2_CLRZCAL                                                       0x0
+
+		# Clear Parity Error
+		# PSU_DDR_PHY_PGCR2_CLRPERR                                                       0x0
+
+		# Initialization Complete Pin Configuration
+		# PSU_DDR_PHY_PGCR2_ICPC                                                          0x0
+
+		# Data Training PUB Mode Exit Timer
+		# PSU_DDR_PHY_PGCR2_DTPMXTMR                                                      0xf
+
+		# Initialization Bypass
+		# PSU_DDR_PHY_PGCR2_INITFSMBYP                                                    0x0
+
+		# PLL FSM Bypass
+		# PSU_DDR_PHY_PGCR2_PLLFSMBYP                                                     0x0
+
+		# Refresh Period
+		# PSU_DDR_PHY_PGCR2_TREFPRD                                                       0x12302
+
+		# PHY General Configuration Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080018, 0xFFFFFFFFU ,0x00F12302U)  */
+    mask_write 0XFD080018 0xFFFFFFFF 0x00F12302
+		# Register : PGCR5 @ 0XFD080024

+
+		# Frequency B Ratio Term
+		# PSU_DDR_PHY_PGCR5_FRQBT                                                         0x1
+
+		# Frequency A Ratio Term
+		# PSU_DDR_PHY_PGCR5_FRQAT                                                         0x1
+
+		# DFI Disconnect Time Period
+		# PSU_DDR_PHY_PGCR5_DISCNPERIOD                                                   0x0
+
+		# Receiver bias core side control
+		# PSU_DDR_PHY_PGCR5_VREF_RBCTRL                                                   0xf
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_PGCR5_RESERVED_3                                                    0x0
+
+		# Internal VREF generator REFSEL ragne select
+		# PSU_DDR_PHY_PGCR5_DXREFISELRANGE                                                0x1
+
+		# DDL Page Read Write select
+		# PSU_DDR_PHY_PGCR5_DDLPGACT                                                      0x0
+
+		# DDL Page Read Write select
+		# PSU_DDR_PHY_PGCR5_DDLPGRW                                                       0x0
+
+		# PHY General Configuration Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080024, 0xFFFFFFFFU ,0x010100F4U)  */
+    mask_write 0XFD080024 0xFFFFFFFF 0x010100F4
+		# Register : PTR0 @ 0XFD080040

+
+		# PLL Power-Down Time
+		# PSU_DDR_PHY_PTR0_TPLLPD                                                         0x2f0
+
+		# PLL Gear Shift Time
+		# PSU_DDR_PHY_PTR0_TPLLGS                                                         0x60
+
+		# PHY Reset Time
+		# PSU_DDR_PHY_PTR0_TPHYRST                                                        0x10
+
+		# PHY Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080040, 0xFFFFFFFFU ,0x5E001810U)  */
+    mask_write 0XFD080040 0xFFFFFFFF 0x5E001810
+		# Register : PTR1 @ 0XFD080044

+
+		# PLL Lock Time
+		# PSU_DDR_PHY_PTR1_TPLLLOCK                                                       0x80
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_PTR1_RESERVED_15_13                                                 0x0
+
+		# PLL Reset Time
+		# PSU_DDR_PHY_PTR1_TPLLRST                                                        0x5f0
+
+		# PHY Timing Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080044, 0xFFFFFFFFU ,0x008005F0U)  */
+    mask_write 0XFD080044 0xFFFFFFFF 0x008005F0
+		# Register : DSGCR @ 0XFD080090

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DSGCR_RESERVED_31_28                                                0x0
+
+		# When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
+		# fault calculation.
+		# PSU_DDR_PHY_DSGCR_RDBICLSEL                                                     0x0
+
+		# When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.
+		# PSU_DDR_PHY_DSGCR_RDBICL                                                        0x2
+
+		# PHY Impedance Update Enable
+		# PSU_DDR_PHY_DSGCR_PHYZUEN                                                       0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DSGCR_RESERVED_22                                                   0x0
+
+		# SDRAM Reset Output Enable
+		# PSU_DDR_PHY_DSGCR_RSTOE                                                         0x1
+
+		# Single Data Rate Mode
+		# PSU_DDR_PHY_DSGCR_SDRMODE                                                       0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DSGCR_RESERVED_18                                                   0x0
+
+		# ATO Analog Test Enable
+		# PSU_DDR_PHY_DSGCR_ATOAE                                                         0x0
+
+		# DTO Output Enable
+		# PSU_DDR_PHY_DSGCR_DTOOE                                                         0x0
+
+		# DTO I/O Mode
+		# PSU_DDR_PHY_DSGCR_DTOIOM                                                        0x0
+
+		# DTO Power Down Receiver
+		# PSU_DDR_PHY_DSGCR_DTOPDR                                                        0x1
+
+		# Reserved. Return zeroes on reads
+		# PSU_DDR_PHY_DSGCR_RESERVED_13                                                   0x0
+
+		# DTO On-Die Termination
+		# PSU_DDR_PHY_DSGCR_DTOODT                                                        0x0
+
+		# PHY Update Acknowledge Delay
+		# PSU_DDR_PHY_DSGCR_PUAD                                                          0x4
+
+		# Controller Update Acknowledge Enable
+		# PSU_DDR_PHY_DSGCR_CUAEN                                                         0x1
+
+		# Reserved. Return zeroes on reads
+		# PSU_DDR_PHY_DSGCR_RESERVED_4_3                                                  0x0
+
+		# Controller Impedance Update Enable
+		# PSU_DDR_PHY_DSGCR_CTLZUEN                                                       0x0
+
+		# Reserved. Return zeroes on reads
+		# PSU_DDR_PHY_DSGCR_RESERVED_1                                                    0x0
+
+		# PHY Update Request Enable
+		# PSU_DDR_PHY_DSGCR_PUREN                                                         0x1
+
+		# DDR System General Configuration Register
+		#(OFFSET, MASK, VALUE)      (0XFD080090, 0xFFFFFFFFU ,0x02A04121U)  */
+    mask_write 0XFD080090 0xFFFFFFFF 0x02A04121
+		# Register : DCR @ 0XFD080100

+
+		# DDR4 Gear Down Timing.
+		# PSU_DDR_PHY_DCR_GEARDN                                                          0x0
+
+		# Un-used Bank Group
+		# PSU_DDR_PHY_DCR_UBG                                                             0x0
+
+		# Un-buffered DIMM Address Mirroring
+		# PSU_DDR_PHY_DCR_UDIMM                                                           0x0
+
+		# DDR 2T Timing
+		# PSU_DDR_PHY_DCR_DDR2T                                                           0x0
+
+		# No Simultaneous Rank Access
+		# PSU_DDR_PHY_DCR_NOSRA                                                           0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DCR_RESERVED_26_18                                                  0x0
+
+		# Byte Mask
+		# PSU_DDR_PHY_DCR_BYTEMASK                                                        0x1
+
+		# DDR Type
+		# PSU_DDR_PHY_DCR_DDRTYPE                                                         0x0
+
+		# Multi-Purpose Register (MPR) DQ (DDR3 Only)
+		# PSU_DDR_PHY_DCR_MPRDQ                                                           0x0
+
+		# Primary DQ (DDR3 Only)
+		# PSU_DDR_PHY_DCR_PDQ                                                             0x0
+
+		# DDR 8-Bank
+		# PSU_DDR_PHY_DCR_DDR8BNK                                                         0x1
+
+		# DDR Mode
+		# PSU_DDR_PHY_DCR_DDRMD                                                           0x4
+
+		# DRAM Configuration Register
+		#(OFFSET, MASK, VALUE)      (0XFD080100, 0xFFFFFFFFU ,0x0800040CU)  */
+    mask_write 0XFD080100 0xFFFFFFFF 0x0800040C
+		# Register : DTPR0 @ 0XFD080110

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR0_RESERVED_31_29                                                0x0
+
+		# Activate to activate command delay (different banks)
+		# PSU_DDR_PHY_DTPR0_TRRD                                                          0x6
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR0_RESERVED_23                                                   0x0
+
+		# Activate to precharge command delay
+		# PSU_DDR_PHY_DTPR0_TRAS                                                          0x24
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR0_RESERVED_15                                                   0x0
+
+		# Precharge command period
+		# PSU_DDR_PHY_DTPR0_TRP                                                           0x12
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR0_RESERVED_7_5                                                  0x0
+
+		# Internal read to precharge command delay
+		# PSU_DDR_PHY_DTPR0_TRTP                                                          0x8
+
+		# DRAM Timing Parameters Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080110, 0xFFFFFFFFU ,0x06241208U)  */
+    mask_write 0XFD080110 0xFFFFFFFF 0x06241208
+		# Register : DTPR1 @ 0XFD080114

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR1_RESERVED_31                                                   0x0
+
+		# Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.
+		# PSU_DDR_PHY_DTPR1_TWLMRD                                                        0x28
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR1_RESERVED_23                                                   0x0
+
+		# 4-bank activate period
+		# PSU_DDR_PHY_DTPR1_TFAW                                                          0x18
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR1_RESERVED_15_11                                                0x0
+
+		# Load mode update delay (DDR4 and DDR3 only)
+		# PSU_DDR_PHY_DTPR1_TMOD                                                          0x7
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR1_RESERVED_7_5                                                  0x0
+
+		# Load mode cycle time
+		# PSU_DDR_PHY_DTPR1_TMRD                                                          0x8
+
+		# DRAM Timing Parameters Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080114, 0xFFFFFFFFU ,0x28180708U)  */
+    mask_write 0XFD080114 0xFFFFFFFF 0x28180708
+		# Register : DTPR2 @ 0XFD080118

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR2_RESERVED_31_29                                                0x0
+
+		# Read to Write command delay. Valid values are
+		# PSU_DDR_PHY_DTPR2_TRTW                                                          0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR2_RESERVED_27_25                                                0x0
+
+		# Read to ODT delay (DDR3 only)
+		# PSU_DDR_PHY_DTPR2_TRTODT                                                        0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR2_RESERVED_23_20                                                0x0
+
+		# CKE minimum pulse width
+		# PSU_DDR_PHY_DTPR2_TCKE                                                          0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR2_RESERVED_15_10                                                0x0
+
+		# Self refresh exit delay
+		# PSU_DDR_PHY_DTPR2_TXS                                                           0x200
+
+		# DRAM Timing Parameters Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080118, 0xFFFFFFFFU ,0x00080200U)  */
+    mask_write 0XFD080118 0xFFFFFFFF 0x00080200
+		# Register : DTPR3 @ 0XFD08011C

+
+		# ODT turn-off delay extension
+		# PSU_DDR_PHY_DTPR3_TOFDX                                                         0x4
+
+		# Read to read and write to write command delay
+		# PSU_DDR_PHY_DTPR3_TCCD                                                          0x0
+
+		# DLL locking time
+		# PSU_DDR_PHY_DTPR3_TDLLK                                                         0x300
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR3_RESERVED_15_12                                                0x0
+
+		# Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
+		# PSU_DDR_PHY_DTPR3_TDQSCKMAX                                                     0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR3_RESERVED_7_3                                                  0x0
+
+		# DQS output access time from CK/CK# (LPDDR2/3 only)
+		# PSU_DDR_PHY_DTPR3_TDQSCK                                                        0x4
+
+		# DRAM Timing Parameters Register 3
+		#(OFFSET, MASK, VALUE)      (0XFD08011C, 0xFFFFFFFFU ,0x83000804U)  */
+    mask_write 0XFD08011C 0xFFFFFFFF 0x83000804
+		# Register : DTPR4 @ 0XFD080120

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR4_RESERVED_31_30                                                0x0
+
+		# ODT turn-on/turn-off delays (DDR2 only)
+		# PSU_DDR_PHY_DTPR4_TAOND_TAOFD                                                   0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR4_RESERVED_27_26                                                0x0
+
+		# Refresh-to-Refresh
+		# PSU_DDR_PHY_DTPR4_TRFC                                                          0x116
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR4_RESERVED_15_14                                                0x0
+
+		# Write leveling output delay
+		# PSU_DDR_PHY_DTPR4_TWLO                                                          0x2b
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR4_RESERVED_7_5                                                  0x0
+
+		# Power down exit delay
+		# PSU_DDR_PHY_DTPR4_TXP                                                           0x8
+
+		# DRAM Timing Parameters Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080120, 0xFFFFFFFFU ,0x01162B08U)  */
+    mask_write 0XFD080120 0xFFFFFFFF 0x01162B08
+		# Register : DTPR5 @ 0XFD080124

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR5_RESERVED_31_24                                                0x0
+
+		# Activate to activate command delay (same bank)
+		# PSU_DDR_PHY_DTPR5_TRC                                                           0x32
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR5_RESERVED_15                                                   0x0
+
+		# Activate to read or write delay
+		# PSU_DDR_PHY_DTPR5_TRCD                                                          0xf
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR5_RESERVED_7_5                                                  0x0
+
+		# Internal write to read command delay
+		# PSU_DDR_PHY_DTPR5_TWTR                                                          0x9
+
+		# DRAM Timing Parameters Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080124, 0xFFFFFFFFU ,0x00320F09U)  */
+    mask_write 0XFD080124 0xFFFFFFFF 0x00320F09
+		# Register : DTPR6 @ 0XFD080128

+
+		# PUB Write Latency Enable
+		# PSU_DDR_PHY_DTPR6_PUBWLEN                                                       0x0
+
+		# PUB Read Latency Enable
+		# PSU_DDR_PHY_DTPR6_PUBRLEN                                                       0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR6_RESERVED_29_14                                                0x0
+
+		# Write Latency
+		# PSU_DDR_PHY_DTPR6_PUBWL                                                         0xe
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTPR6_RESERVED_7_6                                                  0x0
+
+		# Read Latency
+		# PSU_DDR_PHY_DTPR6_PUBRL                                                         0xf
+
+		# DRAM Timing Parameters Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU)  */
+    mask_write 0XFD080128 0xFFFFFFFF 0x00000E0F
+		# Register : RDIMMGCR0 @ 0XFD080140

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR0_RESERVED_31                                               0x0
+
+		# RDMIMM Quad CS Enable
+		# PSU_DDR_PHY_RDIMMGCR0_QCSEN                                                     0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28                                            0x0
+
+		# RDIMM Outputs I/O Mode
+		# PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM                                                  0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24                                            0x0
+
+		# ERROUT# Output Enable
+		# PSU_DDR_PHY_RDIMMGCR0_ERROUTOE                                                  0x0
+
+		# ERROUT# I/O Mode
+		# PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM                                                 0x1
+
+		# ERROUT# Power Down Receiver
+		# PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR0_RESERVED_20                                               0x0
+
+		# ERROUT# On-Die Termination
+		# PSU_DDR_PHY_RDIMMGCR0_ERROUTODT                                                 0x0
+
+		# Load Reduced DIMM
+		# PSU_DDR_PHY_RDIMMGCR0_LRDIMM                                                    0x0
+
+		# PAR_IN I/O Mode
+		# PSU_DDR_PHY_RDIMMGCR0_PARINIOM                                                  0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8                                             0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD                                             0x0
+
+		# Rank Mirror Enable.
+		# PSU_DDR_PHY_RDIMMGCR0_RNKMRREN                                                  0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR0_RESERVED_3                                                0x0
+
+		# Stop on Parity Error
+		# PSU_DDR_PHY_RDIMMGCR0_SOPERR                                                    0x0
+
+		# Parity Error No Registering
+		# PSU_DDR_PHY_RDIMMGCR0_ERRNOREG                                                  0x0
+
+		# Registered DIMM
+		# PSU_DDR_PHY_RDIMMGCR0_RDIMM                                                     0x0
+
+		# RDIMM General Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080140, 0xFFFFFFFFU ,0x08400020U)  */
+    mask_write 0XFD080140 0xFFFFFFFF 0x08400020
+		# Register : RDIMMGCR1 @ 0XFD080144

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29                                            0x0
+
+		# Address [17] B-side Inversion Disable
+		# PSU_DDR_PHY_RDIMMGCR1_A17BID                                                    0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR1_RESERVED_27                                               0x0
+
+		# Command word to command word programming delay
+		# PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR1_RESERVED_23                                               0x0
+
+		# Command word to command word programming delay
+		# PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L                                                  0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR1_RESERVED_19                                               0x0
+
+		# Command word to command word programming delay
+		# PSU_DDR_PHY_RDIMMGCR1_TBCMRD                                                    0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14                                            0x0
+
+		# Stabilization time
+		# PSU_DDR_PHY_RDIMMGCR1_TBCSTAB                                                   0xc80
+
+		# RDIMM General Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080144, 0xFFFFFFFFU ,0x00000C80U)  */
+    mask_write 0XFD080144 0xFFFFFFFF 0x00000C80
+		# Register : RDIMMCR1 @ 0XFD080154

+
+		# Control Word 15
+		# PSU_DDR_PHY_RDIMMCR1_RC15                                                       0x0
+
+		# DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
+		# PSU_DDR_PHY_RDIMMCR1_RC14                                                       0x0
+
+		# DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
+		# PSU_DDR_PHY_RDIMMCR1_RC13                                                       0x0
+
+		# DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
+		# PSU_DDR_PHY_RDIMMCR1_RC12                                                       0x0
+
+		# DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
+		# rol Word)
+		# PSU_DDR_PHY_RDIMMCR1_RC11                                                       0x0
+
+		# DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
+		# PSU_DDR_PHY_RDIMMCR1_RC10                                                       0x2
+
+		# DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
+		# PSU_DDR_PHY_RDIMMCR1_RC9                                                        0x0
+
+		# DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
+		# Control Word)
+		# PSU_DDR_PHY_RDIMMCR1_RC8                                                        0x0
+
+		# RDIMM Control Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080154, 0xFFFFFFFFU ,0x00000200U)  */
+    mask_write 0XFD080154 0xFFFFFFFF 0x00000200
+		# Register : MR0 @ 0XFD080180

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR0_RESERVED_31_8                                                   0x8
+
+		# CA Terminating Rank
+		# PSU_DDR_PHY_MR0_CATR                                                            0x0
+
+		# Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR0_RSVD_6_5                                                        0x1
+
+		# Built-in Self-Test for RZQ
+		# PSU_DDR_PHY_MR0_RZQI                                                            0x2
+
+		# Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR0_RSVD_2_0                                                        0x0
+
+		# LPDDR4 Mode Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080180, 0xFFFFFFFFU ,0x00000830U)  */
+    mask_write 0XFD080180 0xFFFFFFFF 0x00000830
+		# Register : MR1 @ 0XFD080184

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR1_RESERVED_31_8                                                   0x3
+
+		# Read Postamble Length
+		# PSU_DDR_PHY_MR1_RDPST                                                           0x0
+
+		# Write-recovery for auto-precharge command
+		# PSU_DDR_PHY_MR1_NWR                                                             0x0
+
+		# Read Preamble Length
+		# PSU_DDR_PHY_MR1_RDPRE                                                           0x0
+
+		# Write Preamble Length
+		# PSU_DDR_PHY_MR1_WRPRE                                                           0x0
+
+		# Burst Length
+		# PSU_DDR_PHY_MR1_BL                                                              0x1
+
+		# LPDDR4 Mode Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080184, 0xFFFFFFFFU ,0x00000301U)  */
+    mask_write 0XFD080184 0xFFFFFFFF 0x00000301
+		# Register : MR2 @ 0XFD080188

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR2_RESERVED_31_8                                                   0x0
+
+		# Write Leveling
+		# PSU_DDR_PHY_MR2_WRL                                                             0x0
+
+		# Write Latency Set
+		# PSU_DDR_PHY_MR2_WLS                                                             0x0
+
+		# Write Latency
+		# PSU_DDR_PHY_MR2_WL                                                              0x4
+
+		# Read Latency
+		# PSU_DDR_PHY_MR2_RL                                                              0x0
+
+		# LPDDR4 Mode Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080188, 0xFFFFFFFFU ,0x00000020U)  */
+    mask_write 0XFD080188 0xFFFFFFFF 0x00000020
+		# Register : MR3 @ 0XFD08018C

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR3_RESERVED_31_8                                                   0x2
+
+		# DBI-Write Enable
+		# PSU_DDR_PHY_MR3_DBIWR                                                           0x0
+
+		# DBI-Read Enable
+		# PSU_DDR_PHY_MR3_DBIRD                                                           0x0
+
+		# Pull-down Drive Strength
+		# PSU_DDR_PHY_MR3_PDDS                                                            0x0
+
+		# These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR3_RSVD                                                            0x0
+
+		# Write Postamble Length
+		# PSU_DDR_PHY_MR3_WRPST                                                           0x0
+
+		# Pull-up Calibration Point
+		# PSU_DDR_PHY_MR3_PUCAL                                                           0x0
+
+		# LPDDR4 Mode Register 3
+		#(OFFSET, MASK, VALUE)      (0XFD08018C, 0xFFFFFFFFU ,0x00000200U)  */
+    mask_write 0XFD08018C 0xFFFFFFFF 0x00000200
+		# Register : MR4 @ 0XFD080190

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR4_RESERVED_31_16                                                  0x0
+
+		# These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR4_RSVD_15_13                                                      0x0
+
+		# Write Preamble
+		# PSU_DDR_PHY_MR4_WRP                                                             0x0
+
+		# Read Preamble
+		# PSU_DDR_PHY_MR4_RDP                                                             0x0
+
+		# Read Preamble Training Mode
+		# PSU_DDR_PHY_MR4_RPTM                                                            0x0
+
+		# Self Refresh Abort
+		# PSU_DDR_PHY_MR4_SRA                                                             0x0
+
+		# CS to Command Latency Mode
+		# PSU_DDR_PHY_MR4_CS2CMDL                                                         0x0
+
+		# These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR4_RSVD1                                                           0x0
+
+		# Internal VREF Monitor
+		# PSU_DDR_PHY_MR4_IVM                                                             0x0
+
+		# Temperature Controlled Refresh Mode
+		# PSU_DDR_PHY_MR4_TCRM                                                            0x0
+
+		# Temperature Controlled Refresh Range
+		# PSU_DDR_PHY_MR4_TCRR                                                            0x0
+
+		# Maximum Power Down Mode
+		# PSU_DDR_PHY_MR4_MPDM                                                            0x0
+
+		# This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR4_RSVD_0                                                          0x0
+
+		# DDR4 Mode Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080190, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD080190 0xFFFFFFFF 0x00000000
+		# Register : MR5 @ 0XFD080194

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR5_RESERVED_31_16                                                  0x0
+
+		# These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR5_RSVD                                                            0x0
+
+		# Read DBI
+		# PSU_DDR_PHY_MR5_RDBI                                                            0x0
+
+		# Write DBI
+		# PSU_DDR_PHY_MR5_WDBI                                                            0x0
+
+		# Data Mask
+		# PSU_DDR_PHY_MR5_DM                                                              0x1
+
+		# CA Parity Persistent Error
+		# PSU_DDR_PHY_MR5_CAPPE                                                           0x1
+
+		# RTT_PARK
+		# PSU_DDR_PHY_MR5_RTTPARK                                                         0x3
+
+		# ODT Input Buffer during Power Down mode
+		# PSU_DDR_PHY_MR5_ODTIBPD                                                         0x0
+
+		# C/A Parity Error Status
+		# PSU_DDR_PHY_MR5_CAPES                                                           0x0
+
+		# CRC Error Clear
+		# PSU_DDR_PHY_MR5_CRCEC                                                           0x0
+
+		# C/A Parity Latency Mode
+		# PSU_DDR_PHY_MR5_CAPM                                                            0x0
+
+		# DDR4 Mode Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080194, 0xFFFFFFFFU ,0x000006C0U)  */
+    mask_write 0XFD080194 0xFFFFFFFF 0x000006C0
+		# Register : MR6 @ 0XFD080198

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR6_RESERVED_31_16                                                  0x0
+
+		# These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR6_RSVD_15_13                                                      0x0
+
+		# CAS_n to CAS_n command delay for same bank group (tCCD_L)
+		# PSU_DDR_PHY_MR6_TCCDL                                                           0x2
+
+		# These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR6_RSVD_9_8                                                        0x0
+
+		# VrefDQ Training Enable
+		# PSU_DDR_PHY_MR6_VDDQTEN                                                         0x0
+
+		# VrefDQ Training Range
+		# PSU_DDR_PHY_MR6_VDQTRG                                                          0x0
+
+		# VrefDQ Training Values
+		# PSU_DDR_PHY_MR6_VDQTVAL                                                         0x19
+
+		# DDR4 Mode Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080198, 0xFFFFFFFFU ,0x00000819U)  */
+    mask_write 0XFD080198 0xFFFFFFFF 0x00000819
+		# Register : MR11 @ 0XFD0801AC

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR11_RESERVED_31_8                                                  0x0
+
+		# These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR11_RSVD                                                           0x0
+
+		# Power Down Control
+		# PSU_DDR_PHY_MR11_PDCTL                                                          0x0
+
+		# DQ Bus Receiver On-Die-Termination
+		# PSU_DDR_PHY_MR11_DQODT                                                          0x0
+
+		# LPDDR4 Mode Register 11
+		#(OFFSET, MASK, VALUE)      (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD0801AC 0xFFFFFFFF 0x00000000
+		# Register : MR12 @ 0XFD0801B0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR12_RESERVED_31_8                                                  0x0
+
+		# These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR12_RSVD                                                           0x0
+
+		# VREF_CA Range Select.
+		# PSU_DDR_PHY_MR12_VR_CA                                                          0x1
+
+		# Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
+		# PSU_DDR_PHY_MR12_VREF_CA                                                        0xd
+
+		# LPDDR4 Mode Register 12
+		#(OFFSET, MASK, VALUE)      (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU)  */
+    mask_write 0XFD0801B0 0xFFFFFFFF 0x0000004D
+		# Register : MR13 @ 0XFD0801B4

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR13_RESERVED_31_8                                                  0x0
+
+		# Frequency Set Point Operation Mode
+		# PSU_DDR_PHY_MR13_FSPOP                                                          0x0
+
+		# Frequency Set Point Write Enable
+		# PSU_DDR_PHY_MR13_FSPWR                                                          0x0
+
+		# Data Mask Enable
+		# PSU_DDR_PHY_MR13_DMD                                                            0x0
+
+		# Refresh Rate Option
+		# PSU_DDR_PHY_MR13_RRO                                                            0x0
+
+		# VREF Current Generator
+		# PSU_DDR_PHY_MR13_VRCG                                                           0x1
+
+		# VREF Output
+		# PSU_DDR_PHY_MR13_VRO                                                            0x0
+
+		# Read Preamble Training Mode
+		# PSU_DDR_PHY_MR13_RPT                                                            0x0
+
+		# Command Bus Training
+		# PSU_DDR_PHY_MR13_CBT                                                            0x0
+
+		# LPDDR4 Mode Register 13
+		#(OFFSET, MASK, VALUE)      (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U)  */
+    mask_write 0XFD0801B4 0xFFFFFFFF 0x00000008
+		# Register : MR14 @ 0XFD0801B8

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR14_RESERVED_31_8                                                  0x0
+
+		# These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR14_RSVD                                                           0x0
+
+		# VREFDQ Range Selects.
+		# PSU_DDR_PHY_MR14_VR_DQ                                                          0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR14_VREF_DQ                                                        0xd
+
+		# LPDDR4 Mode Register 14
+		#(OFFSET, MASK, VALUE)      (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU)  */
+    mask_write 0XFD0801B8 0xFFFFFFFF 0x0000004D
+		# Register : MR22 @ 0XFD0801D8

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_MR22_RESERVED_31_8                                                  0x0
+
+		# These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		# PSU_DDR_PHY_MR22_RSVD                                                           0x0
+
+		# CA ODT termination disable.
+		# PSU_DDR_PHY_MR22_ODTD_CA                                                        0x0
+
+		# ODT CS override.
+		# PSU_DDR_PHY_MR22_ODTE_CS                                                        0x0
+
+		# ODT CK override.
+		# PSU_DDR_PHY_MR22_ODTE_CK                                                        0x0
+
+		# Controller ODT value for VOH calibration.
+		# PSU_DDR_PHY_MR22_CODT                                                           0x0
+
+		# LPDDR4 Mode Register 22
+		#(OFFSET, MASK, VALUE)      (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD0801D8 0xFFFFFFFF 0x00000000
+		# Register : DTCR0 @ 0XFD080200

+
+		# Refresh During Training
+		# PSU_DDR_PHY_DTCR0_RFSHDT                                                        0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTCR0_RESERVED_27_26                                                0x0
+
+		# Data Training Debug Rank Select
+		# PSU_DDR_PHY_DTCR0_DTDRS                                                         0x1
+
+		# Data Training with Early/Extended Gate
+		# PSU_DDR_PHY_DTCR0_DTEXG                                                         0x0
+
+		# Data Training Extended Write DQS
+		# PSU_DDR_PHY_DTCR0_DTEXD                                                         0x0
+
+		# Data Training Debug Step
+		# PSU_DDR_PHY_DTCR0_DTDSTP                                                        0x0
+
+		# Data Training Debug Enable
+		# PSU_DDR_PHY_DTCR0_DTDEN                                                         0x0
+
+		# Data Training Debug Byte Select
+		# PSU_DDR_PHY_DTCR0_DTDBS                                                         0x0
+
+		# Data Training read DBI deskewing configuration
+		# PSU_DDR_PHY_DTCR0_DTRDBITR                                                      0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTCR0_RESERVED_13                                                   0x0
+
+		# Data Training Write Bit Deskew Data Mask
+		# PSU_DDR_PHY_DTCR0_DTWBDDM                                                       0x1
+
+		# Refreshes Issued During Entry to Training
+		# PSU_DDR_PHY_DTCR0_RFSHEN                                                        0x1
+
+		# Data Training Compare Data
+		# PSU_DDR_PHY_DTCR0_DTCMPD                                                        0x1
+
+		# Data Training Using MPR
+		# PSU_DDR_PHY_DTCR0_DTMPR                                                         0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTCR0_RESERVED_5_4                                                  0x0
+
+		# Data Training Repeat Number
+		# PSU_DDR_PHY_DTCR0_DTRPTN                                                        0x7
+
+		# Data Training Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080200, 0xFFFFFFFFU ,0x810011C7U)  */
+    mask_write 0XFD080200 0xFFFFFFFF 0x810011C7
+		# Register : DTCR1 @ 0XFD080204

+
+		# Rank Enable.
+		# PSU_DDR_PHY_DTCR1_RANKEN_RSVD                                                   0x0
+
+		# Rank Enable.
+		# PSU_DDR_PHY_DTCR1_RANKEN                                                        0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTCR1_RESERVED_15_14                                                0x0
+
+		# Data Training Rank
+		# PSU_DDR_PHY_DTCR1_DTRANK                                                        0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTCR1_RESERVED_11                                                   0x0
+
+		# Read Leveling Gate Sampling Difference
+		# PSU_DDR_PHY_DTCR1_RDLVLGDIFF                                                    0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTCR1_RESERVED_7                                                    0x0
+
+		# Read Leveling Gate Shift
+		# PSU_DDR_PHY_DTCR1_RDLVLGS                                                       0x3
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DTCR1_RESERVED_3                                                    0x0
+
+		# Read Preamble Training enable
+		# PSU_DDR_PHY_DTCR1_RDPRMVL_TRN                                                   0x1
+
+		# Read Leveling Enable
+		# PSU_DDR_PHY_DTCR1_RDLVLEN                                                       0x1
+
+		# Basic Gate Training Enable
+		# PSU_DDR_PHY_DTCR1_BSTEN                                                         0x0
+
+		# Data Training Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080204, 0xFFFFFFFFU ,0x00010236U)  */
+    mask_write 0XFD080204 0xFFFFFFFF 0x00010236
+		# Register : CATR0 @ 0XFD080240

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_CATR0_RESERVED_31_21                                                0x0
+
+		# Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command
+		# PSU_DDR_PHY_CATR0_CACD                                                          0x14
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_CATR0_RESERVED_15_13                                                0x0
+
+		# Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
+		#  been sent to the memory
+		# PSU_DDR_PHY_CATR0_CAADR                                                         0x10
+
+		# CA_1 Response Byte Lane 1
+		# PSU_DDR_PHY_CATR0_CA1BYTE1                                                      0x5
+
+		# CA_1 Response Byte Lane 0
+		# PSU_DDR_PHY_CATR0_CA1BYTE0                                                      0x4
+
+		# CA Training Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080240, 0xFFFFFFFFU ,0x00141054U)  */
+    mask_write 0XFD080240 0xFFFFFFFF 0x00141054
+		# Register : RIOCR5 @ 0XFD0804F4

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_RIOCR5_RESERVED_31_16                                               0x0
+
+		# Reserved. Return zeros on reads.
+		# PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD                                               0x0
+
+		# SDRAM On-die Termination Output Enable (OE) Mode Selection.
+		# PSU_DDR_PHY_RIOCR5_ODTOEMODE                                                    0x5
+
+		# Rank I/O Configuration Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U)  */
+    mask_write 0XFD0804F4 0xFFFFFFFF 0x00000005
+		# Register : ACIOCR0 @ 0XFD080500

+
+		# Address/Command Slew Rate (D3F I/O Only)
+		# PSU_DDR_PHY_ACIOCR0_ACSR                                                        0x0
+
+		# SDRAM Reset I/O Mode
+		# PSU_DDR_PHY_ACIOCR0_RSTIOM                                                      0x1
+
+		# SDRAM Reset Power Down Receiver
+		# PSU_DDR_PHY_ACIOCR0_RSTPDR                                                      0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACIOCR0_RESERVED_27                                                 0x0
+
+		# SDRAM Reset On-Die Termination
+		# PSU_DDR_PHY_ACIOCR0_RSTODT                                                      0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACIOCR0_RESERVED_25_10                                              0x0
+
+		# CK Duty Cycle Correction
+		# PSU_DDR_PHY_ACIOCR0_CKDCC                                                       0x0
+
+		# AC Power Down Receiver Mode
+		# PSU_DDR_PHY_ACIOCR0_ACPDRMODE                                                   0x2
+
+		# AC On-die Termination Mode
+		# PSU_DDR_PHY_ACIOCR0_ACODTMODE                                                   0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACIOCR0_RESERVED_1                                                  0x0
+
+		# Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
+		# PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL                                                0x0
+
+		# AC I/O Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080500, 0xFFFFFFFFU ,0x30000028U)  */
+    mask_write 0XFD080500 0xFFFFFFFF 0x30000028
+		# Register : ACIOCR2 @ 0XFD080508

+
+		# Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice
+		# PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE                                               0x0
+
+		# Clock gating for Output Enable D slices [0]
+		# PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0                                                0x0
+
+		# Clock gating for Power Down Receiver D slices [0]
+		# PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0                                               0x0
+
+		# Clock gating for Termination Enable D slices [0]
+		# PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0                                                0x0
+
+		# Clock gating for CK# D slices [1:0]
+		# PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0                                                 0x2
+
+		# Clock gating for CK D slices [1:0]
+		# PSU_DDR_PHY_ACIOCR2_CKCLKGATE0                                                  0x2
+
+		# Clock gating for AC D slices [23:0]
+		# PSU_DDR_PHY_ACIOCR2_ACCLKGATE0                                                  0x0
+
+		# AC I/O Configuration Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080508, 0xFFFFFFFFU ,0x0A000000U)  */
+    mask_write 0XFD080508 0xFFFFFFFF 0x0A000000
+		# Register : ACIOCR3 @ 0XFD08050C

+
+		# SDRAM Parity Output Enable (OE) Mode Selection
+		# PSU_DDR_PHY_ACIOCR3_PAROEMODE                                                   0x0
+
+		# SDRAM Bank Group Output Enable (OE) Mode Selection
+		# PSU_DDR_PHY_ACIOCR3_BGOEMODE                                                    0x0
+
+		# SDRAM Bank Address Output Enable (OE) Mode Selection
+		# PSU_DDR_PHY_ACIOCR3_BAOEMODE                                                    0x0
+
+		# SDRAM A[17] Output Enable (OE) Mode Selection
+		# PSU_DDR_PHY_ACIOCR3_A17OEMODE                                                   0x0
+
+		# SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
+		# PSU_DDR_PHY_ACIOCR3_A16OEMODE                                                   0x0
+
+		# SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
+		# PSU_DDR_PHY_ACIOCR3_ACTOEMODE                                                   0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACIOCR3_RESERVED_15_8                                               0x0
+
+		# Reserved. Return zeros on reads.
+		# PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD                                               0x0
+
+		# SDRAM CK Output Enable (OE) Mode Selection.
+		# PSU_DDR_PHY_ACIOCR3_CKOEMODE                                                    0x9
+
+		# AC I/O Configuration Register 3
+		#(OFFSET, MASK, VALUE)      (0XFD08050C, 0xFFFFFFFFU ,0x00000009U)  */
+    mask_write 0XFD08050C 0xFFFFFFFF 0x00000009
+		# Register : ACIOCR4 @ 0XFD080510

+
+		# Clock gating for AC LB slices and loopback read valid slices
+		# PSU_DDR_PHY_ACIOCR4_LBCLKGATE                                                   0x0
+
+		# Clock gating for Output Enable D slices [1]
+		# PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1                                                0x0
+
+		# Clock gating for Power Down Receiver D slices [1]
+		# PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1                                               0x0
+
+		# Clock gating for Termination Enable D slices [1]
+		# PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1                                                0x0
+
+		# Clock gating for CK# D slices [3:2]
+		# PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1                                                 0x2
+
+		# Clock gating for CK D slices [3:2]
+		# PSU_DDR_PHY_ACIOCR4_CKCLKGATE1                                                  0x2
+
+		# Clock gating for AC D slices [47:24]
+		# PSU_DDR_PHY_ACIOCR4_ACCLKGATE1                                                  0x0
+
+		# AC I/O Configuration Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080510, 0xFFFFFFFFU ,0x0A000000U)  */
+    mask_write 0XFD080510 0xFFFFFFFF 0x0A000000
+		# Register : IOVCR0 @ 0XFD080520

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_IOVCR0_RESERVED_31_29                                               0x0
+
+		# Address/command lane VREF Pad Enable
+		# PSU_DDR_PHY_IOVCR0_ACREFPEN                                                     0x0
+
+		# Address/command lane Internal VREF Enable
+		# PSU_DDR_PHY_IOVCR0_ACREFEEN                                                     0x0
+
+		# Address/command lane Single-End VREF Enable
+		# PSU_DDR_PHY_IOVCR0_ACREFSEN                                                     0x1
+
+		# Address/command lane Internal VREF Enable
+		# PSU_DDR_PHY_IOVCR0_ACREFIEN                                                     0x1
+
+		# External VREF generato REFSEL range select
+		# PSU_DDR_PHY_IOVCR0_ACREFESELRANGE                                               0x0
+
+		# Address/command lane External VREF Select
+		# PSU_DDR_PHY_IOVCR0_ACREFESEL                                                    0x0
+
+		# Single ended VREF generator REFSEL range select
+		# PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE                                               0x1
+
+		# Address/command lane Single-End VREF Select
+		# PSU_DDR_PHY_IOVCR0_ACREFSSEL                                                    0x30
+
+		# Internal VREF generator REFSEL ragne select
+		# PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE                                              0x1
+
+		# REFSEL Control for internal AC IOs
+		# PSU_DDR_PHY_IOVCR0_ACVREFISEL                                                   0x30
+
+		# IO VREF Control Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U)  */
+    mask_write 0XFD080520 0xFFFFFFFF 0x0300B0B0
+		# Register : VTCR0 @ 0XFD080528

+
+		# Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training
+		# PSU_DDR_PHY_VTCR0_TVREF                                                         0x7
+
+		# DRM DQ VREF training Enable
+		# PSU_DDR_PHY_VTCR0_DVEN                                                          0x1
+
+		# Per Device Addressability Enable
+		# PSU_DDR_PHY_VTCR0_PDAEN                                                         0x1
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_VTCR0_RESERVED_26                                                   0x0
+
+		# VREF Word Count
+		# PSU_DDR_PHY_VTCR0_VWCR                                                          0x4
+
+		# DRAM DQ VREF step size used during DRAM VREF training
+		# PSU_DDR_PHY_VTCR0_DVSS                                                          0x0
+
+		# Maximum VREF limit value used during DRAM VREF training
+		# PSU_DDR_PHY_VTCR0_DVMAX                                                         0x32
+
+		# Minimum VREF limit value used during DRAM VREF training
+		# PSU_DDR_PHY_VTCR0_DVMIN                                                         0x0
+
+		# Initial DRAM DQ VREF value used during DRAM VREF training
+		# PSU_DDR_PHY_VTCR0_DVINIT                                                        0x19
+
+		# VREF Training Control Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080528, 0xFFFFFFFFU ,0xF9032019U)  */
+    mask_write 0XFD080528 0xFFFFFFFF 0xF9032019
+		# Register : VTCR1 @ 0XFD08052C

+
+		# Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)
+		# PSU_DDR_PHY_VTCR1_HVSS                                                          0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_VTCR1_RESERVED_27                                                   0x0
+
+		# Maximum VREF limit value used during DRAM VREF training.
+		# PSU_DDR_PHY_VTCR1_HVMAX                                                         0x7f
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_VTCR1_RESERVED_19                                                   0x0
+
+		# Minimum VREF limit value used during DRAM VREF training.
+		# PSU_DDR_PHY_VTCR1_HVMIN                                                         0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_VTCR1_RESERVED_11                                                   0x0
+
+		# Static Host Vref Rank Value
+		# PSU_DDR_PHY_VTCR1_SHRNK                                                         0x0
+
+		# Static Host Vref Rank Enable
+		# PSU_DDR_PHY_VTCR1_SHREN                                                         0x1
+
+		# Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
+		# PSU_DDR_PHY_VTCR1_TVREFIO                                                       0x4
+
+		# Eye LCDL Offset value for VREF training
+		# PSU_DDR_PHY_VTCR1_EOFF                                                          0x1
+
+		# Number of LCDL Eye points for which VREF training is repeated
+		# PSU_DDR_PHY_VTCR1_ENUM                                                          0x1
+
+		# HOST (IO) internal VREF training Enable
+		# PSU_DDR_PHY_VTCR1_HVEN                                                          0x1
+
+		# Host IO Type Control
+		# PSU_DDR_PHY_VTCR1_HVIO                                                          0x1
+
+		# VREF Training Control Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD08052C, 0xFFFFFFFFU ,0x07F0018FU)  */
+    mask_write 0XFD08052C 0xFFFFFFFF 0x07F0018F
+		# Register : ACBDLR6 @ 0XFD080558

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR6_RESERVED_31_30                                              0x0
+
+		# Delay select for the BDL on Address A[3].
+		# PSU_DDR_PHY_ACBDLR6_A03BD                                                       0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR6_RESERVED_23_22                                              0x0
+
+		# Delay select for the BDL on Address A[2].
+		# PSU_DDR_PHY_ACBDLR6_A02BD                                                       0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR6_RESERVED_15_14                                              0x0
+
+		# Delay select for the BDL on Address A[1].
+		# PSU_DDR_PHY_ACBDLR6_A01BD                                                       0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR6_RESERVED_7_6                                                0x0
+
+		# Delay select for the BDL on Address A[0].
+		# PSU_DDR_PHY_ACBDLR6_A00BD                                                       0x0
+
+		# AC Bit Delay Line Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080558, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD080558 0xFFFFFFFF 0x00000000
+		# Register : ACBDLR7 @ 0XFD08055C

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR7_RESERVED_31_30                                              0x0
+
+		# Delay select for the BDL on Address A[7].
+		# PSU_DDR_PHY_ACBDLR7_A07BD                                                       0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR7_RESERVED_23_22                                              0x0
+
+		# Delay select for the BDL on Address A[6].
+		# PSU_DDR_PHY_ACBDLR7_A06BD                                                       0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR7_RESERVED_15_14                                              0x0
+
+		# Delay select for the BDL on Address A[5].
+		# PSU_DDR_PHY_ACBDLR7_A05BD                                                       0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR7_RESERVED_7_6                                                0x0
+
+		# Delay select for the BDL on Address A[4].
+		# PSU_DDR_PHY_ACBDLR7_A04BD                                                       0x0
+
+		# AC Bit Delay Line Register 7
+		#(OFFSET, MASK, VALUE)      (0XFD08055C, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD08055C 0xFFFFFFFF 0x00000000
+		# Register : ACBDLR8 @ 0XFD080560

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR8_RESERVED_31_30                                              0x0
+
+		# Delay select for the BDL on Address A[11].
+		# PSU_DDR_PHY_ACBDLR8_A11BD                                                       0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR8_RESERVED_23_22                                              0x0
+
+		# Delay select for the BDL on Address A[10].
+		# PSU_DDR_PHY_ACBDLR8_A10BD                                                       0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR8_RESERVED_15_14                                              0x0
+
+		# Delay select for the BDL on Address A[9].
+		# PSU_DDR_PHY_ACBDLR8_A09BD                                                       0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ACBDLR8_RESERVED_7_6                                                0x0
+
+		# Delay select for the BDL on Address A[8].
+		# PSU_DDR_PHY_ACBDLR8_A08BD                                                       0x0
+
+		# AC Bit Delay Line Register 8
+		#(OFFSET, MASK, VALUE)      (0XFD080560, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD080560 0xFFFFFFFF 0x00000000
+		# Register : ZQCR @ 0XFD080680

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_ZQCR_RESERVED_31_26                                                 0x0
+
+		# ZQ VREF Range
+		# PSU_DDR_PHY_ZQCR_ZQREFISELRANGE                                                 0x0
+
+		# Programmable Wait for Frequency B
+		# PSU_DDR_PHY_ZQCR_PGWAIT_FRQB                                                    0x11
+
+		# Programmable Wait for Frequency A
+		# PSU_DDR_PHY_ZQCR_PGWAIT_FRQA                                                    0x11
+
+		# ZQ VREF Pad Enable
+		# PSU_DDR_PHY_ZQCR_ZQREFPEN                                                       0x0
+
+		# ZQ Internal VREF Enable
+		# PSU_DDR_PHY_ZQCR_ZQREFIEN                                                       0x1
+
+		# Choice of termination mode
+		# PSU_DDR_PHY_ZQCR_ODT_MODE                                                       0x1
+
+		# Force ZCAL VT update
+		# PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE                                           0x0
+
+		# IO VT Drift Limit
+		# PSU_DDR_PHY_ZQCR_IODLMT                                                         0x2
+
+		# Averaging algorithm enable, if set, enables averaging algorithm
+		# PSU_DDR_PHY_ZQCR_AVGEN                                                          0x1
+
+		# Maximum number of averaging rounds to be used by averaging algorithm
+		# PSU_DDR_PHY_ZQCR_AVGMAX                                                         0x2
+
+		# ZQ Calibration Type
+		# PSU_DDR_PHY_ZQCR_ZCALT                                                          0x0
+
+		# ZQ Power Down
+		# PSU_DDR_PHY_ZQCR_ZQPD                                                           0x0
+
+		# ZQ Impedance Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U)  */
+    mask_write 0XFD080680 0xFFFFFFFF 0x008A2A58
+		# Register : ZQ0PR0 @ 0XFD080684

+
+		# Pull-down drive strength ZCTRL over-ride enable
+		# PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN                                                  0x0
+
+		# Pull-up drive strength ZCTRL over-ride enable
+		# PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN                                                  0x0
+
+		# Pull-down termination ZCTRL over-ride enable
+		# PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN                                                  0x0
+
+		# Pull-up termination ZCTRL over-ride enable
+		# PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN                                                  0x0
+
+		# Calibration segment bypass
+		# PSU_DDR_PHY_ZQ0PR0_ZSEGBYP                                                      0x0
+
+		# VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
+		# PSU_DDR_PHY_ZQ0PR0_ZLE_MODE                                                     0x0
+
+		# Termination adjustment
+		# PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST                                                   0x0
+
+		# Pulldown drive strength adjustment
+		# PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST                                                0x0
+
+		# Pullup drive strength adjustment
+		# PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST                                                0x0
+
+		# DRAM Impedance Divide Ratio
+		# PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT                                               0x7
+
+		# HOST Impedance Divide Ratio
+		# PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT                                               0x7
+
+		# Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
+		# PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD                                            0xd
+
+		# Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
+		# PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU                                            0xd
+
+		# ZQ n Impedance Control Program Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080684, 0xFFFFFFFFU ,0x000077DDU)  */
+    mask_write 0XFD080684 0xFFFFFFFF 0x000077DD
+		# Register : ZQ0OR0 @ 0XFD080694

+
+		# Reserved. Return zeros on reads.
+		# PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26                                               0x0
+
+		# Override value for the pull-up output impedance
+		# PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD                                            0x1e1
+
+		# Reserved. Return zeros on reads.
+		# PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10                                               0x0
+
+		# Override value for the pull-down output impedance
+		# PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD                                            0x210
+
+		# ZQ n Impedance Control Override Data Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080694, 0xFFFFFFFFU ,0x01E10210U)  */
+    mask_write 0XFD080694 0xFFFFFFFF 0x01E10210
+		# Register : ZQ0OR1 @ 0XFD080698

+
+		# Reserved. Return zeros on reads.
+		# PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26                                               0x0
+
+		# Override value for the pull-up termination
+		# PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD                                            0x1e1
+
+		# Reserved. Return zeros on reads.
+		# PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10                                               0x0
+
+		# Override value for the pull-down termination
+		# PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD                                            0x0
+
+		# ZQ n Impedance Control Override Data Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080698, 0xFFFFFFFFU ,0x01E10000U)  */
+    mask_write 0XFD080698 0xFFFFFFFF 0x01E10000
+		# Register : ZQ1PR0 @ 0XFD0806A4

+
+		# Pull-down drive strength ZCTRL over-ride enable
+		# PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN                                                  0x0
+
+		# Pull-up drive strength ZCTRL over-ride enable
+		# PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN                                                  0x0
+
+		# Pull-down termination ZCTRL over-ride enable
+		# PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN                                                  0x0
+
+		# Pull-up termination ZCTRL over-ride enable
+		# PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN                                                  0x0
+
+		# Calibration segment bypass
+		# PSU_DDR_PHY_ZQ1PR0_ZSEGBYP                                                      0x0
+
+		# VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
+		# PSU_DDR_PHY_ZQ1PR0_ZLE_MODE                                                     0x0
+
+		# Termination adjustment
+		# PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST                                                   0x0
+
+		# Pulldown drive strength adjustment
+		# PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST                                                0x1
+
+		# Pullup drive strength adjustment
+		# PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST                                                0x0
+
+		# DRAM Impedance Divide Ratio
+		# PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT                                               0x7
+
+		# HOST Impedance Divide Ratio
+		# PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT                                               0xb
+
+		# Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
+		# PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD                                            0xd
+
+		# Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
+		# PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU                                            0xb
+
+		# ZQ n Impedance Control Program Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU)  */
+    mask_write 0XFD0806A4 0xFFFFFFFF 0x00087BDB
+		# Register : DX0GCR0 @ 0XFD080700

+
+		# Calibration Bypass
+		# PSU_DDR_PHY_DX0GCR0_CALBYP                                                      0x0
+
+		# Master Delay Line Enable
+		# PSU_DDR_PHY_DX0GCR0_MDLEN                                                       0x1
+
+		# Configurable ODT(TE) Phase Shift
+		# PSU_DDR_PHY_DX0GCR0_CODTSHFT                                                    0x0
+
+		# DQS Duty Cycle Correction
+		# PSU_DDR_PHY_DX0GCR0_DQSDCC                                                      0x0
+
+		# Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		# PSU_DDR_PHY_DX0GCR0_RDDLY                                                       0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX0GCR0_RESERVED_19_14                                              0x0
+
+		# DQSNSE Power Down Receiver
+		# PSU_DDR_PHY_DX0GCR0_DQSNSEPDR                                                   0x0
+
+		# DQSSE Power Down Receiver
+		# PSU_DDR_PHY_DX0GCR0_DQSSEPDR                                                    0x0
+
+		# RTT On Additive Latency
+		# PSU_DDR_PHY_DX0GCR0_RTTOAL                                                      0x0
+
+		# RTT Output Hold
+		# PSU_DDR_PHY_DX0GCR0_RTTOH                                                       0x3
+
+		# Configurable PDR Phase Shift
+		# PSU_DDR_PHY_DX0GCR0_CPDRSHFT                                                    0x0
+
+		# DQSR Power Down
+		# PSU_DDR_PHY_DX0GCR0_DQSRPD                                                      0x0
+
+		# DQSG Power Down Receiver
+		# PSU_DDR_PHY_DX0GCR0_DQSGPDR                                                     0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX0GCR0_RESERVED_4                                                  0x0
+
+		# DQSG On-Die Termination
+		# PSU_DDR_PHY_DX0GCR0_DQSGODT                                                     0x0
+
+		# DQSG Output Enable
+		# PSU_DDR_PHY_DX0GCR0_DQSGOE                                                      0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX0GCR0_RESERVED_1_0                                                0x0
+
+		# DATX8 n General Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080700, 0xFFFFFFFFU ,0x40800604U)  */
+    mask_write 0XFD080700 0xFFFFFFFF 0x40800604
+		# Register : DX0GCR4 @ 0XFD080710

+
+		# Byte lane VREF IOM (Used only by D4MU IOs)
+		# PSU_DDR_PHY_DX0GCR4_RESERVED_31_29                                              0x0
+
+		# Byte Lane VREF Pad Enable
+		# PSU_DDR_PHY_DX0GCR4_DXREFPEN                                                    0x0
+
+		# Byte Lane Internal VREF Enable
+		# PSU_DDR_PHY_DX0GCR4_DXREFEEN                                                    0x3
+
+		# Byte Lane Single-End VREF Enable
+		# PSU_DDR_PHY_DX0GCR4_DXREFSEN                                                    0x1
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX0GCR4_RESERVED_24                                                 0x0
+
+		# External VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE                                              0x0
+
+		# Byte Lane External VREF Select
+		# PSU_DDR_PHY_DX0GCR4_DXREFESEL                                                   0x0
+
+		# Single ended VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE                                              0x1
+
+		# Byte Lane Single-End VREF Select
+		# PSU_DDR_PHY_DX0GCR4_DXREFSSEL                                                   0x30
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX0GCR4_RESERVED_7_6                                                0x0
+
+		# VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX0GCR4_DXREFIEN                                                    0xf
+
+		# VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX0GCR4_DXREFIMON                                                   0x0
+
+		# DATX8 n General Configuration Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU)  */
+    mask_write 0XFD080710 0xFFFFFFFF 0x0E00B03C
+		# Register : DX0GCR5 @ 0XFD080714

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX0GCR5_RESERVED_31                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 3
+		# PSU_DDR_PHY_DX0GCR5_DXREFISELR3                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX0GCR5_RESERVED_23                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 2
+		# PSU_DDR_PHY_DX0GCR5_DXREFISELR2                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX0GCR5_RESERVED_15                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 1
+		# PSU_DDR_PHY_DX0GCR5_DXREFISELR1                                                 0x55
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX0GCR5_RESERVED_7                                                  0x0
+
+		# Byte Lane internal VREF Select for Rank 0
+		# PSU_DDR_PHY_DX0GCR5_DXREFISELR0                                                 0x55
+
+		# DATX8 n General Configuration Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080714, 0xFFFFFFFFU ,0x09095555U)  */
+    mask_write 0XFD080714 0xFFFFFFFF 0x09095555
+		# Register : DX0GCR6 @ 0XFD080718

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX0GCR6_RESERVED_31_30                                              0x0
+
+		# DRAM DQ VREF Select for Rank3
+		# PSU_DDR_PHY_DX0GCR6_DXDQVREFR3                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX0GCR6_RESERVED_23_22                                              0x0
+
+		# DRAM DQ VREF Select for Rank2
+		# PSU_DDR_PHY_DX0GCR6_DXDQVREFR2                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX0GCR6_RESERVED_15_14                                              0x0
+
+		# DRAM DQ VREF Select for Rank1
+		# PSU_DDR_PHY_DX0GCR6_DXDQVREFR1                                                  0x2b
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX0GCR6_RESERVED_7_6                                                0x0
+
+		# DRAM DQ VREF Select for Rank0
+		# PSU_DDR_PHY_DX0GCR6_DXDQVREFR0                                                  0x2b
+
+		# DATX8 n General Configuration Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU)  */
+    mask_write 0XFD080718 0xFFFFFFFF 0x09092B2B
+		# Register : DX0LCDLR2 @ 0XFD080788

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25                                            0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16                                            0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9                                             0x0
+
+		# Read DQS Gating Delay
+		# PSU_DDR_PHY_DX0LCDLR2_DQSGD                                                     0x0
+
+		# DATX8 n Local Calibrated Delay Line Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080788, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD080788 0xFFFFFFFF 0x00000000
+		# Register : DX0GTR0 @ 0XFD0807C0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX0GTR0_RESERVED_31_24                                              0x0
+
+		# DQ Write Path Latency Pipeline
+		# PSU_DDR_PHY_DX0GTR0_WDQSL                                                       0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX0GTR0_RESERVED_23_20                                              0x0
+
+		# Write Leveling System Latency
+		# PSU_DDR_PHY_DX0GTR0_WLSL                                                        0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX0GTR0_RESERVED_15_13                                              0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX0GTR0_RESERVED_12_8                                               0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX0GTR0_RESERVED_7_5                                                0x0
+
+		# DQS Gating System Latency
+		# PSU_DDR_PHY_DX0GTR0_DGSL                                                        0x0
+
+		# DATX8 n General Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U)  */
+    mask_write 0XFD0807C0 0xFFFFFFFF 0x00020000
+		# Register : DX1GCR0 @ 0XFD080800

+
+		# Calibration Bypass
+		# PSU_DDR_PHY_DX1GCR0_CALBYP                                                      0x0
+
+		# Master Delay Line Enable
+		# PSU_DDR_PHY_DX1GCR0_MDLEN                                                       0x1
+
+		# Configurable ODT(TE) Phase Shift
+		# PSU_DDR_PHY_DX1GCR0_CODTSHFT                                                    0x0
+
+		# DQS Duty Cycle Correction
+		# PSU_DDR_PHY_DX1GCR0_DQSDCC                                                      0x0
+
+		# Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		# PSU_DDR_PHY_DX1GCR0_RDDLY                                                       0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX1GCR0_RESERVED_19_14                                              0x0
+
+		# DQSNSE Power Down Receiver
+		# PSU_DDR_PHY_DX1GCR0_DQSNSEPDR                                                   0x0
+
+		# DQSSE Power Down Receiver
+		# PSU_DDR_PHY_DX1GCR0_DQSSEPDR                                                    0x0
+
+		# RTT On Additive Latency
+		# PSU_DDR_PHY_DX1GCR0_RTTOAL                                                      0x0
+
+		# RTT Output Hold
+		# PSU_DDR_PHY_DX1GCR0_RTTOH                                                       0x3
+
+		# Configurable PDR Phase Shift
+		# PSU_DDR_PHY_DX1GCR0_CPDRSHFT                                                    0x0
+
+		# DQSR Power Down
+		# PSU_DDR_PHY_DX1GCR0_DQSRPD                                                      0x0
+
+		# DQSG Power Down Receiver
+		# PSU_DDR_PHY_DX1GCR0_DQSGPDR                                                     0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX1GCR0_RESERVED_4                                                  0x0
+
+		# DQSG On-Die Termination
+		# PSU_DDR_PHY_DX1GCR0_DQSGODT                                                     0x0
+
+		# DQSG Output Enable
+		# PSU_DDR_PHY_DX1GCR0_DQSGOE                                                      0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX1GCR0_RESERVED_1_0                                                0x0
+
+		# DATX8 n General Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080800, 0xFFFFFFFFU ,0x40800604U)  */
+    mask_write 0XFD080800 0xFFFFFFFF 0x40800604
+		# Register : DX1GCR4 @ 0XFD080810

+
+		# Byte lane VREF IOM (Used only by D4MU IOs)
+		# PSU_DDR_PHY_DX1GCR4_RESERVED_31_29                                              0x0
+
+		# Byte Lane VREF Pad Enable
+		# PSU_DDR_PHY_DX1GCR4_DXREFPEN                                                    0x0
+
+		# Byte Lane Internal VREF Enable
+		# PSU_DDR_PHY_DX1GCR4_DXREFEEN                                                    0x3
+
+		# Byte Lane Single-End VREF Enable
+		# PSU_DDR_PHY_DX1GCR4_DXREFSEN                                                    0x1
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX1GCR4_RESERVED_24                                                 0x0
+
+		# External VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE                                              0x0
+
+		# Byte Lane External VREF Select
+		# PSU_DDR_PHY_DX1GCR4_DXREFESEL                                                   0x0
+
+		# Single ended VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE                                              0x1
+
+		# Byte Lane Single-End VREF Select
+		# PSU_DDR_PHY_DX1GCR4_DXREFSSEL                                                   0x30
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX1GCR4_RESERVED_7_6                                                0x0
+
+		# VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX1GCR4_DXREFIEN                                                    0xf
+
+		# VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX1GCR4_DXREFIMON                                                   0x0
+
+		# DATX8 n General Configuration Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU)  */
+    mask_write 0XFD080810 0xFFFFFFFF 0x0E00B03C
+		# Register : DX1GCR5 @ 0XFD080814

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX1GCR5_RESERVED_31                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 3
+		# PSU_DDR_PHY_DX1GCR5_DXREFISELR3                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX1GCR5_RESERVED_23                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 2
+		# PSU_DDR_PHY_DX1GCR5_DXREFISELR2                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX1GCR5_RESERVED_15                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 1
+		# PSU_DDR_PHY_DX1GCR5_DXREFISELR1                                                 0x55
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX1GCR5_RESERVED_7                                                  0x0
+
+		# Byte Lane internal VREF Select for Rank 0
+		# PSU_DDR_PHY_DX1GCR5_DXREFISELR0                                                 0x55
+
+		# DATX8 n General Configuration Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080814, 0xFFFFFFFFU ,0x09095555U)  */
+    mask_write 0XFD080814 0xFFFFFFFF 0x09095555
+		# Register : DX1GCR6 @ 0XFD080818

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX1GCR6_RESERVED_31_30                                              0x0
+
+		# DRAM DQ VREF Select for Rank3
+		# PSU_DDR_PHY_DX1GCR6_DXDQVREFR3                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX1GCR6_RESERVED_23_22                                              0x0
+
+		# DRAM DQ VREF Select for Rank2
+		# PSU_DDR_PHY_DX1GCR6_DXDQVREFR2                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX1GCR6_RESERVED_15_14                                              0x0
+
+		# DRAM DQ VREF Select for Rank1
+		# PSU_DDR_PHY_DX1GCR6_DXDQVREFR1                                                  0x2b
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX1GCR6_RESERVED_7_6                                                0x0
+
+		# DRAM DQ VREF Select for Rank0
+		# PSU_DDR_PHY_DX1GCR6_DXDQVREFR0                                                  0x2b
+
+		# DATX8 n General Configuration Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU)  */
+    mask_write 0XFD080818 0xFFFFFFFF 0x09092B2B
+		# Register : DX1LCDLR2 @ 0XFD080888

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25                                            0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16                                            0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9                                             0x0
+
+		# Read DQS Gating Delay
+		# PSU_DDR_PHY_DX1LCDLR2_DQSGD                                                     0x0
+
+		# DATX8 n Local Calibrated Delay Line Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080888, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD080888 0xFFFFFFFF 0x00000000
+		# Register : DX1GTR0 @ 0XFD0808C0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX1GTR0_RESERVED_31_24                                              0x0
+
+		# DQ Write Path Latency Pipeline
+		# PSU_DDR_PHY_DX1GTR0_WDQSL                                                       0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX1GTR0_RESERVED_23_20                                              0x0
+
+		# Write Leveling System Latency
+		# PSU_DDR_PHY_DX1GTR0_WLSL                                                        0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX1GTR0_RESERVED_15_13                                              0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX1GTR0_RESERVED_12_8                                               0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX1GTR0_RESERVED_7_5                                                0x0
+
+		# DQS Gating System Latency
+		# PSU_DDR_PHY_DX1GTR0_DGSL                                                        0x0
+
+		# DATX8 n General Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U)  */
+    mask_write 0XFD0808C0 0xFFFFFFFF 0x00020000
+		# Register : DX2GCR0 @ 0XFD080900

+
+		# Calibration Bypass
+		# PSU_DDR_PHY_DX2GCR0_CALBYP                                                      0x0
+
+		# Master Delay Line Enable
+		# PSU_DDR_PHY_DX2GCR0_MDLEN                                                       0x1
+
+		# Configurable ODT(TE) Phase Shift
+		# PSU_DDR_PHY_DX2GCR0_CODTSHFT                                                    0x0
+
+		# DQS Duty Cycle Correction
+		# PSU_DDR_PHY_DX2GCR0_DQSDCC                                                      0x0
+
+		# Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		# PSU_DDR_PHY_DX2GCR0_RDDLY                                                       0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX2GCR0_RESERVED_19_14                                              0x0
+
+		# DQSNSE Power Down Receiver
+		# PSU_DDR_PHY_DX2GCR0_DQSNSEPDR                                                   0x0
+
+		# DQSSE Power Down Receiver
+		# PSU_DDR_PHY_DX2GCR0_DQSSEPDR                                                    0x0
+
+		# RTT On Additive Latency
+		# PSU_DDR_PHY_DX2GCR0_RTTOAL                                                      0x0
+
+		# RTT Output Hold
+		# PSU_DDR_PHY_DX2GCR0_RTTOH                                                       0x3
+
+		# Configurable PDR Phase Shift
+		# PSU_DDR_PHY_DX2GCR0_CPDRSHFT                                                    0x0
+
+		# DQSR Power Down
+		# PSU_DDR_PHY_DX2GCR0_DQSRPD                                                      0x0
+
+		# DQSG Power Down Receiver
+		# PSU_DDR_PHY_DX2GCR0_DQSGPDR                                                     0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX2GCR0_RESERVED_4                                                  0x0
+
+		# DQSG On-Die Termination
+		# PSU_DDR_PHY_DX2GCR0_DQSGODT                                                     0x0
+
+		# DQSG Output Enable
+		# PSU_DDR_PHY_DX2GCR0_DQSGOE                                                      0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX2GCR0_RESERVED_1_0                                                0x0
+
+		# DATX8 n General Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080900, 0xFFFFFFFFU ,0x40800604U)  */
+    mask_write 0XFD080900 0xFFFFFFFF 0x40800604
+		# Register : DX2GCR1 @ 0XFD080904

+
+		# Enables the PDR mode for DQ[7:0]
+		# PSU_DDR_PHY_DX2GCR1_DXPDRMODE                                                   0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_DX2GCR1_RESERVED_15                                                 0x0
+
+		# Select the delayed or non-delayed read data strobe #
+		# PSU_DDR_PHY_DX2GCR1_QSNSEL                                                      0x1
+
+		# Select the delayed or non-delayed read data strobe
+		# PSU_DDR_PHY_DX2GCR1_QSSEL                                                       0x1
+
+		# Enables Read Data Strobe in a byte lane
+		# PSU_DDR_PHY_DX2GCR1_OEEN                                                        0x1
+
+		# Enables PDR in a byte lane
+		# PSU_DDR_PHY_DX2GCR1_PDREN                                                       0x1
+
+		# Enables ODT/TE in a byte lane
+		# PSU_DDR_PHY_DX2GCR1_TEEN                                                        0x1
+
+		# Enables Write Data strobe in a byte lane
+		# PSU_DDR_PHY_DX2GCR1_DSEN                                                        0x1
+
+		# Enables DM pin in a byte lane
+		# PSU_DDR_PHY_DX2GCR1_DMEN                                                        0x1
+
+		# Enables DQ corresponding to each bit in a byte
+		# PSU_DDR_PHY_DX2GCR1_DQEN                                                        0xff
+
+		# DATX8 n General Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU)  */
+    mask_write 0XFD080904 0xFFFFFFFF 0x00007FFF
+		# Register : DX2GCR4 @ 0XFD080910

+
+		# Byte lane VREF IOM (Used only by D4MU IOs)
+		# PSU_DDR_PHY_DX2GCR4_RESERVED_31_29                                              0x0
+
+		# Byte Lane VREF Pad Enable
+		# PSU_DDR_PHY_DX2GCR4_DXREFPEN                                                    0x0
+
+		# Byte Lane Internal VREF Enable
+		# PSU_DDR_PHY_DX2GCR4_DXREFEEN                                                    0x3
+
+		# Byte Lane Single-End VREF Enable
+		# PSU_DDR_PHY_DX2GCR4_DXREFSEN                                                    0x1
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX2GCR4_RESERVED_24                                                 0x0
+
+		# External VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE                                              0x0
+
+		# Byte Lane External VREF Select
+		# PSU_DDR_PHY_DX2GCR4_DXREFESEL                                                   0x0
+
+		# Single ended VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE                                              0x1
+
+		# Byte Lane Single-End VREF Select
+		# PSU_DDR_PHY_DX2GCR4_DXREFSSEL                                                   0x30
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX2GCR4_RESERVED_7_6                                                0x0
+
+		# VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX2GCR4_DXREFIEN                                                    0xf
+
+		# VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX2GCR4_DXREFIMON                                                   0x0
+
+		# DATX8 n General Configuration Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU)  */
+    mask_write 0XFD080910 0xFFFFFFFF 0x0E00B03C
+		# Register : DX2GCR5 @ 0XFD080914

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX2GCR5_RESERVED_31                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 3
+		# PSU_DDR_PHY_DX2GCR5_DXREFISELR3                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX2GCR5_RESERVED_23                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 2
+		# PSU_DDR_PHY_DX2GCR5_DXREFISELR2                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX2GCR5_RESERVED_15                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 1
+		# PSU_DDR_PHY_DX2GCR5_DXREFISELR1                                                 0x55
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX2GCR5_RESERVED_7                                                  0x0
+
+		# Byte Lane internal VREF Select for Rank 0
+		# PSU_DDR_PHY_DX2GCR5_DXREFISELR0                                                 0x55
+
+		# DATX8 n General Configuration Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080914, 0xFFFFFFFFU ,0x09095555U)  */
+    mask_write 0XFD080914 0xFFFFFFFF 0x09095555
+		# Register : DX2GCR6 @ 0XFD080918

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX2GCR6_RESERVED_31_30                                              0x0
+
+		# DRAM DQ VREF Select for Rank3
+		# PSU_DDR_PHY_DX2GCR6_DXDQVREFR3                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX2GCR6_RESERVED_23_22                                              0x0
+
+		# DRAM DQ VREF Select for Rank2
+		# PSU_DDR_PHY_DX2GCR6_DXDQVREFR2                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX2GCR6_RESERVED_15_14                                              0x0
+
+		# DRAM DQ VREF Select for Rank1
+		# PSU_DDR_PHY_DX2GCR6_DXDQVREFR1                                                  0x2b
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX2GCR6_RESERVED_7_6                                                0x0
+
+		# DRAM DQ VREF Select for Rank0
+		# PSU_DDR_PHY_DX2GCR6_DXDQVREFR0                                                  0x2b
+
+		# DATX8 n General Configuration Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU)  */
+    mask_write 0XFD080918 0xFFFFFFFF 0x09092B2B
+		# Register : DX2LCDLR2 @ 0XFD080988

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25                                            0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16                                            0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9                                             0x0
+
+		# Read DQS Gating Delay
+		# PSU_DDR_PHY_DX2LCDLR2_DQSGD                                                     0x0
+
+		# DATX8 n Local Calibrated Delay Line Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080988, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD080988 0xFFFFFFFF 0x00000000
+		# Register : DX2GTR0 @ 0XFD0809C0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX2GTR0_RESERVED_31_24                                              0x0
+
+		# DQ Write Path Latency Pipeline
+		# PSU_DDR_PHY_DX2GTR0_WDQSL                                                       0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX2GTR0_RESERVED_23_20                                              0x0
+
+		# Write Leveling System Latency
+		# PSU_DDR_PHY_DX2GTR0_WLSL                                                        0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX2GTR0_RESERVED_15_13                                              0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX2GTR0_RESERVED_12_8                                               0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX2GTR0_RESERVED_7_5                                                0x0
+
+		# DQS Gating System Latency
+		# PSU_DDR_PHY_DX2GTR0_DGSL                                                        0x0
+
+		# DATX8 n General Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U)  */
+    mask_write 0XFD0809C0 0xFFFFFFFF 0x00020000
+		# Register : DX3GCR0 @ 0XFD080A00

+
+		# Calibration Bypass
+		# PSU_DDR_PHY_DX3GCR0_CALBYP                                                      0x0
+
+		# Master Delay Line Enable
+		# PSU_DDR_PHY_DX3GCR0_MDLEN                                                       0x1
+
+		# Configurable ODT(TE) Phase Shift
+		# PSU_DDR_PHY_DX3GCR0_CODTSHFT                                                    0x0
+
+		# DQS Duty Cycle Correction
+		# PSU_DDR_PHY_DX3GCR0_DQSDCC                                                      0x0
+
+		# Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		# PSU_DDR_PHY_DX3GCR0_RDDLY                                                       0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX3GCR0_RESERVED_19_14                                              0x0
+
+		# DQSNSE Power Down Receiver
+		# PSU_DDR_PHY_DX3GCR0_DQSNSEPDR                                                   0x0
+
+		# DQSSE Power Down Receiver
+		# PSU_DDR_PHY_DX3GCR0_DQSSEPDR                                                    0x0
+
+		# RTT On Additive Latency
+		# PSU_DDR_PHY_DX3GCR0_RTTOAL                                                      0x0
+
+		# RTT Output Hold
+		# PSU_DDR_PHY_DX3GCR0_RTTOH                                                       0x3
+
+		# Configurable PDR Phase Shift
+		# PSU_DDR_PHY_DX3GCR0_CPDRSHFT                                                    0x0
+
+		# DQSR Power Down
+		# PSU_DDR_PHY_DX3GCR0_DQSRPD                                                      0x0
+
+		# DQSG Power Down Receiver
+		# PSU_DDR_PHY_DX3GCR0_DQSGPDR                                                     0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX3GCR0_RESERVED_4                                                  0x0
+
+		# DQSG On-Die Termination
+		# PSU_DDR_PHY_DX3GCR0_DQSGODT                                                     0x0
+
+		# DQSG Output Enable
+		# PSU_DDR_PHY_DX3GCR0_DQSGOE                                                      0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX3GCR0_RESERVED_1_0                                                0x0
+
+		# DATX8 n General Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080A00, 0xFFFFFFFFU ,0x40800604U)  */
+    mask_write 0XFD080A00 0xFFFFFFFF 0x40800604
+		# Register : DX3GCR1 @ 0XFD080A04

+
+		# Enables the PDR mode for DQ[7:0]
+		# PSU_DDR_PHY_DX3GCR1_DXPDRMODE                                                   0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_DX3GCR1_RESERVED_15                                                 0x0
+
+		# Select the delayed or non-delayed read data strobe #
+		# PSU_DDR_PHY_DX3GCR1_QSNSEL                                                      0x1
+
+		# Select the delayed or non-delayed read data strobe
+		# PSU_DDR_PHY_DX3GCR1_QSSEL                                                       0x1
+
+		# Enables Read Data Strobe in a byte lane
+		# PSU_DDR_PHY_DX3GCR1_OEEN                                                        0x1
+
+		# Enables PDR in a byte lane
+		# PSU_DDR_PHY_DX3GCR1_PDREN                                                       0x1
+
+		# Enables ODT/TE in a byte lane
+		# PSU_DDR_PHY_DX3GCR1_TEEN                                                        0x1
+
+		# Enables Write Data strobe in a byte lane
+		# PSU_DDR_PHY_DX3GCR1_DSEN                                                        0x1
+
+		# Enables DM pin in a byte lane
+		# PSU_DDR_PHY_DX3GCR1_DMEN                                                        0x1
+
+		# Enables DQ corresponding to each bit in a byte
+		# PSU_DDR_PHY_DX3GCR1_DQEN                                                        0xff
+
+		# DATX8 n General Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU)  */
+    mask_write 0XFD080A04 0xFFFFFFFF 0x00007FFF
+		# Register : DX3GCR4 @ 0XFD080A10

+
+		# Byte lane VREF IOM (Used only by D4MU IOs)
+		# PSU_DDR_PHY_DX3GCR4_RESERVED_31_29                                              0x0
+
+		# Byte Lane VREF Pad Enable
+		# PSU_DDR_PHY_DX3GCR4_DXREFPEN                                                    0x0
+
+		# Byte Lane Internal VREF Enable
+		# PSU_DDR_PHY_DX3GCR4_DXREFEEN                                                    0x3
+
+		# Byte Lane Single-End VREF Enable
+		# PSU_DDR_PHY_DX3GCR4_DXREFSEN                                                    0x1
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX3GCR4_RESERVED_24                                                 0x0
+
+		# External VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE                                              0x0
+
+		# Byte Lane External VREF Select
+		# PSU_DDR_PHY_DX3GCR4_DXREFESEL                                                   0x0
+
+		# Single ended VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE                                              0x1
+
+		# Byte Lane Single-End VREF Select
+		# PSU_DDR_PHY_DX3GCR4_DXREFSSEL                                                   0x30
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX3GCR4_RESERVED_7_6                                                0x0
+
+		# VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX3GCR4_DXREFIEN                                                    0xf
+
+		# VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX3GCR4_DXREFIMON                                                   0x0
+
+		# DATX8 n General Configuration Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU)  */
+    mask_write 0XFD080A10 0xFFFFFFFF 0x0E00B03C
+		# Register : DX3GCR5 @ 0XFD080A14

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX3GCR5_RESERVED_31                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 3
+		# PSU_DDR_PHY_DX3GCR5_DXREFISELR3                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX3GCR5_RESERVED_23                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 2
+		# PSU_DDR_PHY_DX3GCR5_DXREFISELR2                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX3GCR5_RESERVED_15                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 1
+		# PSU_DDR_PHY_DX3GCR5_DXREFISELR1                                                 0x55
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX3GCR5_RESERVED_7                                                  0x0
+
+		# Byte Lane internal VREF Select for Rank 0
+		# PSU_DDR_PHY_DX3GCR5_DXREFISELR0                                                 0x55
+
+		# DATX8 n General Configuration Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080A14, 0xFFFFFFFFU ,0x09095555U)  */
+    mask_write 0XFD080A14 0xFFFFFFFF 0x09095555
+		# Register : DX3GCR6 @ 0XFD080A18

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX3GCR6_RESERVED_31_30                                              0x0
+
+		# DRAM DQ VREF Select for Rank3
+		# PSU_DDR_PHY_DX3GCR6_DXDQVREFR3                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX3GCR6_RESERVED_23_22                                              0x0
+
+		# DRAM DQ VREF Select for Rank2
+		# PSU_DDR_PHY_DX3GCR6_DXDQVREFR2                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX3GCR6_RESERVED_15_14                                              0x0
+
+		# DRAM DQ VREF Select for Rank1
+		# PSU_DDR_PHY_DX3GCR6_DXDQVREFR1                                                  0x2b
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX3GCR6_RESERVED_7_6                                                0x0
+
+		# DRAM DQ VREF Select for Rank0
+		# PSU_DDR_PHY_DX3GCR6_DXDQVREFR0                                                  0x2b
+
+		# DATX8 n General Configuration Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU)  */
+    mask_write 0XFD080A18 0xFFFFFFFF 0x09092B2B
+		# Register : DX3LCDLR2 @ 0XFD080A88

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25                                            0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16                                            0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9                                             0x0
+
+		# Read DQS Gating Delay
+		# PSU_DDR_PHY_DX3LCDLR2_DQSGD                                                     0x0
+
+		# DATX8 n Local Calibrated Delay Line Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080A88, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD080A88 0xFFFFFFFF 0x00000000
+		# Register : DX3GTR0 @ 0XFD080AC0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX3GTR0_RESERVED_31_24                                              0x0
+
+		# DQ Write Path Latency Pipeline
+		# PSU_DDR_PHY_DX3GTR0_WDQSL                                                       0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX3GTR0_RESERVED_23_20                                              0x0
+
+		# Write Leveling System Latency
+		# PSU_DDR_PHY_DX3GTR0_WLSL                                                        0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX3GTR0_RESERVED_15_13                                              0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX3GTR0_RESERVED_12_8                                               0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX3GTR0_RESERVED_7_5                                                0x0
+
+		# DQS Gating System Latency
+		# PSU_DDR_PHY_DX3GTR0_DGSL                                                        0x0
+
+		# DATX8 n General Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U)  */
+    mask_write 0XFD080AC0 0xFFFFFFFF 0x00020000
+		# Register : DX4GCR0 @ 0XFD080B00

+
+		# Calibration Bypass
+		# PSU_DDR_PHY_DX4GCR0_CALBYP                                                      0x0
+
+		# Master Delay Line Enable
+		# PSU_DDR_PHY_DX4GCR0_MDLEN                                                       0x1
+
+		# Configurable ODT(TE) Phase Shift
+		# PSU_DDR_PHY_DX4GCR0_CODTSHFT                                                    0x0
+
+		# DQS Duty Cycle Correction
+		# PSU_DDR_PHY_DX4GCR0_DQSDCC                                                      0x0
+
+		# Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		# PSU_DDR_PHY_DX4GCR0_RDDLY                                                       0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX4GCR0_RESERVED_19_14                                              0x0
+
+		# DQSNSE Power Down Receiver
+		# PSU_DDR_PHY_DX4GCR0_DQSNSEPDR                                                   0x0
+
+		# DQSSE Power Down Receiver
+		# PSU_DDR_PHY_DX4GCR0_DQSSEPDR                                                    0x0
+
+		# RTT On Additive Latency
+		# PSU_DDR_PHY_DX4GCR0_RTTOAL                                                      0x0
+
+		# RTT Output Hold
+		# PSU_DDR_PHY_DX4GCR0_RTTOH                                                       0x3
+
+		# Configurable PDR Phase Shift
+		# PSU_DDR_PHY_DX4GCR0_CPDRSHFT                                                    0x0
+
+		# DQSR Power Down
+		# PSU_DDR_PHY_DX4GCR0_DQSRPD                                                      0x0
+
+		# DQSG Power Down Receiver
+		# PSU_DDR_PHY_DX4GCR0_DQSGPDR                                                     0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX4GCR0_RESERVED_4                                                  0x0
+
+		# DQSG On-Die Termination
+		# PSU_DDR_PHY_DX4GCR0_DQSGODT                                                     0x0
+
+		# DQSG Output Enable
+		# PSU_DDR_PHY_DX4GCR0_DQSGOE                                                      0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX4GCR0_RESERVED_1_0                                                0x0
+
+		# DATX8 n General Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080B00, 0xFFFFFFFFU ,0x40800604U)  */
+    mask_write 0XFD080B00 0xFFFFFFFF 0x40800604
+		# Register : DX4GCR1 @ 0XFD080B04

+
+		# Enables the PDR mode for DQ[7:0]
+		# PSU_DDR_PHY_DX4GCR1_DXPDRMODE                                                   0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_DX4GCR1_RESERVED_15                                                 0x0
+
+		# Select the delayed or non-delayed read data strobe #
+		# PSU_DDR_PHY_DX4GCR1_QSNSEL                                                      0x1
+
+		# Select the delayed or non-delayed read data strobe
+		# PSU_DDR_PHY_DX4GCR1_QSSEL                                                       0x1
+
+		# Enables Read Data Strobe in a byte lane
+		# PSU_DDR_PHY_DX4GCR1_OEEN                                                        0x1
+
+		# Enables PDR in a byte lane
+		# PSU_DDR_PHY_DX4GCR1_PDREN                                                       0x1
+
+		# Enables ODT/TE in a byte lane
+		# PSU_DDR_PHY_DX4GCR1_TEEN                                                        0x1
+
+		# Enables Write Data strobe in a byte lane
+		# PSU_DDR_PHY_DX4GCR1_DSEN                                                        0x1
+
+		# Enables DM pin in a byte lane
+		# PSU_DDR_PHY_DX4GCR1_DMEN                                                        0x1
+
+		# Enables DQ corresponding to each bit in a byte
+		# PSU_DDR_PHY_DX4GCR1_DQEN                                                        0xff
+
+		# DATX8 n General Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU)  */
+    mask_write 0XFD080B04 0xFFFFFFFF 0x00007FFF
+		# Register : DX4GCR4 @ 0XFD080B10

+
+		# Byte lane VREF IOM (Used only by D4MU IOs)
+		# PSU_DDR_PHY_DX4GCR4_RESERVED_31_29                                              0x0
+
+		# Byte Lane VREF Pad Enable
+		# PSU_DDR_PHY_DX4GCR4_DXREFPEN                                                    0x0
+
+		# Byte Lane Internal VREF Enable
+		# PSU_DDR_PHY_DX4GCR4_DXREFEEN                                                    0x3
+
+		# Byte Lane Single-End VREF Enable
+		# PSU_DDR_PHY_DX4GCR4_DXREFSEN                                                    0x1
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX4GCR4_RESERVED_24                                                 0x0
+
+		# External VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE                                              0x0
+
+		# Byte Lane External VREF Select
+		# PSU_DDR_PHY_DX4GCR4_DXREFESEL                                                   0x0
+
+		# Single ended VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE                                              0x1
+
+		# Byte Lane Single-End VREF Select
+		# PSU_DDR_PHY_DX4GCR4_DXREFSSEL                                                   0x30
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX4GCR4_RESERVED_7_6                                                0x0
+
+		# VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX4GCR4_DXREFIEN                                                    0xf
+
+		# VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX4GCR4_DXREFIMON                                                   0x0
+
+		# DATX8 n General Configuration Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU)  */
+    mask_write 0XFD080B10 0xFFFFFFFF 0x0E00B03C
+		# Register : DX4GCR5 @ 0XFD080B14

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX4GCR5_RESERVED_31                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 3
+		# PSU_DDR_PHY_DX4GCR5_DXREFISELR3                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX4GCR5_RESERVED_23                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 2
+		# PSU_DDR_PHY_DX4GCR5_DXREFISELR2                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX4GCR5_RESERVED_15                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 1
+		# PSU_DDR_PHY_DX4GCR5_DXREFISELR1                                                 0x55
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX4GCR5_RESERVED_7                                                  0x0
+
+		# Byte Lane internal VREF Select for Rank 0
+		# PSU_DDR_PHY_DX4GCR5_DXREFISELR0                                                 0x55
+
+		# DATX8 n General Configuration Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080B14, 0xFFFFFFFFU ,0x09095555U)  */
+    mask_write 0XFD080B14 0xFFFFFFFF 0x09095555
+		# Register : DX4GCR6 @ 0XFD080B18

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX4GCR6_RESERVED_31_30                                              0x0
+
+		# DRAM DQ VREF Select for Rank3
+		# PSU_DDR_PHY_DX4GCR6_DXDQVREFR3                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX4GCR6_RESERVED_23_22                                              0x0
+
+		# DRAM DQ VREF Select for Rank2
+		# PSU_DDR_PHY_DX4GCR6_DXDQVREFR2                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX4GCR6_RESERVED_15_14                                              0x0
+
+		# DRAM DQ VREF Select for Rank1
+		# PSU_DDR_PHY_DX4GCR6_DXDQVREFR1                                                  0x2b
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX4GCR6_RESERVED_7_6                                                0x0
+
+		# DRAM DQ VREF Select for Rank0
+		# PSU_DDR_PHY_DX4GCR6_DXDQVREFR0                                                  0x2b
+
+		# DATX8 n General Configuration Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU)  */
+    mask_write 0XFD080B18 0xFFFFFFFF 0x09092B2B
+		# Register : DX4LCDLR2 @ 0XFD080B88

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25                                            0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16                                            0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9                                             0x0
+
+		# Read DQS Gating Delay
+		# PSU_DDR_PHY_DX4LCDLR2_DQSGD                                                     0x0
+
+		# DATX8 n Local Calibrated Delay Line Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080B88, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD080B88 0xFFFFFFFF 0x00000000
+		# Register : DX4GTR0 @ 0XFD080BC0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX4GTR0_RESERVED_31_24                                              0x0
+
+		# DQ Write Path Latency Pipeline
+		# PSU_DDR_PHY_DX4GTR0_WDQSL                                                       0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX4GTR0_RESERVED_23_20                                              0x0
+
+		# Write Leveling System Latency
+		# PSU_DDR_PHY_DX4GTR0_WLSL                                                        0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX4GTR0_RESERVED_15_13                                              0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX4GTR0_RESERVED_12_8                                               0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX4GTR0_RESERVED_7_5                                                0x0
+
+		# DQS Gating System Latency
+		# PSU_DDR_PHY_DX4GTR0_DGSL                                                        0x0
+
+		# DATX8 n General Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U)  */
+    mask_write 0XFD080BC0 0xFFFFFFFF 0x00020000
+		# Register : DX5GCR0 @ 0XFD080C00

+
+		# Calibration Bypass
+		# PSU_DDR_PHY_DX5GCR0_CALBYP                                                      0x0
+
+		# Master Delay Line Enable
+		# PSU_DDR_PHY_DX5GCR0_MDLEN                                                       0x1
+
+		# Configurable ODT(TE) Phase Shift
+		# PSU_DDR_PHY_DX5GCR0_CODTSHFT                                                    0x0
+
+		# DQS Duty Cycle Correction
+		# PSU_DDR_PHY_DX5GCR0_DQSDCC                                                      0x0
+
+		# Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		# PSU_DDR_PHY_DX5GCR0_RDDLY                                                       0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX5GCR0_RESERVED_19_14                                              0x0
+
+		# DQSNSE Power Down Receiver
+		# PSU_DDR_PHY_DX5GCR0_DQSNSEPDR                                                   0x0
+
+		# DQSSE Power Down Receiver
+		# PSU_DDR_PHY_DX5GCR0_DQSSEPDR                                                    0x0
+
+		# RTT On Additive Latency
+		# PSU_DDR_PHY_DX5GCR0_RTTOAL                                                      0x0
+
+		# RTT Output Hold
+		# PSU_DDR_PHY_DX5GCR0_RTTOH                                                       0x3
+
+		# Configurable PDR Phase Shift
+		# PSU_DDR_PHY_DX5GCR0_CPDRSHFT                                                    0x0
+
+		# DQSR Power Down
+		# PSU_DDR_PHY_DX5GCR0_DQSRPD                                                      0x0
+
+		# DQSG Power Down Receiver
+		# PSU_DDR_PHY_DX5GCR0_DQSGPDR                                                     0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX5GCR0_RESERVED_4                                                  0x0
+
+		# DQSG On-Die Termination
+		# PSU_DDR_PHY_DX5GCR0_DQSGODT                                                     0x0
+
+		# DQSG Output Enable
+		# PSU_DDR_PHY_DX5GCR0_DQSGOE                                                      0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX5GCR0_RESERVED_1_0                                                0x0
+
+		# DATX8 n General Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080C00, 0xFFFFFFFFU ,0x40800604U)  */
+    mask_write 0XFD080C00 0xFFFFFFFF 0x40800604
+		# Register : DX5GCR1 @ 0XFD080C04

+
+		# Enables the PDR mode for DQ[7:0]
+		# PSU_DDR_PHY_DX5GCR1_DXPDRMODE                                                   0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_DX5GCR1_RESERVED_15                                                 0x0
+
+		# Select the delayed or non-delayed read data strobe #
+		# PSU_DDR_PHY_DX5GCR1_QSNSEL                                                      0x1
+
+		# Select the delayed or non-delayed read data strobe
+		# PSU_DDR_PHY_DX5GCR1_QSSEL                                                       0x1
+
+		# Enables Read Data Strobe in a byte lane
+		# PSU_DDR_PHY_DX5GCR1_OEEN                                                        0x1
+
+		# Enables PDR in a byte lane
+		# PSU_DDR_PHY_DX5GCR1_PDREN                                                       0x1
+
+		# Enables ODT/TE in a byte lane
+		# PSU_DDR_PHY_DX5GCR1_TEEN                                                        0x1
+
+		# Enables Write Data strobe in a byte lane
+		# PSU_DDR_PHY_DX5GCR1_DSEN                                                        0x1
+
+		# Enables DM pin in a byte lane
+		# PSU_DDR_PHY_DX5GCR1_DMEN                                                        0x1
+
+		# Enables DQ corresponding to each bit in a byte
+		# PSU_DDR_PHY_DX5GCR1_DQEN                                                        0xff
+
+		# DATX8 n General Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU)  */
+    mask_write 0XFD080C04 0xFFFFFFFF 0x00007FFF
+		# Register : DX5GCR4 @ 0XFD080C10

+
+		# Byte lane VREF IOM (Used only by D4MU IOs)
+		# PSU_DDR_PHY_DX5GCR4_RESERVED_31_29                                              0x0
+
+		# Byte Lane VREF Pad Enable
+		# PSU_DDR_PHY_DX5GCR4_DXREFPEN                                                    0x0
+
+		# Byte Lane Internal VREF Enable
+		# PSU_DDR_PHY_DX5GCR4_DXREFEEN                                                    0x3
+
+		# Byte Lane Single-End VREF Enable
+		# PSU_DDR_PHY_DX5GCR4_DXREFSEN                                                    0x1
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX5GCR4_RESERVED_24                                                 0x0
+
+		# External VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE                                              0x0
+
+		# Byte Lane External VREF Select
+		# PSU_DDR_PHY_DX5GCR4_DXREFESEL                                                   0x0
+
+		# Single ended VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE                                              0x1
+
+		# Byte Lane Single-End VREF Select
+		# PSU_DDR_PHY_DX5GCR4_DXREFSSEL                                                   0x30
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX5GCR4_RESERVED_7_6                                                0x0
+
+		# VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX5GCR4_DXREFIEN                                                    0xf
+
+		# VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX5GCR4_DXREFIMON                                                   0x0
+
+		# DATX8 n General Configuration Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU)  */
+    mask_write 0XFD080C10 0xFFFFFFFF 0x0E00B03C
+		# Register : DX5GCR5 @ 0XFD080C14

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX5GCR5_RESERVED_31                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 3
+		# PSU_DDR_PHY_DX5GCR5_DXREFISELR3                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX5GCR5_RESERVED_23                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 2
+		# PSU_DDR_PHY_DX5GCR5_DXREFISELR2                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX5GCR5_RESERVED_15                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 1
+		# PSU_DDR_PHY_DX5GCR5_DXREFISELR1                                                 0x55
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX5GCR5_RESERVED_7                                                  0x0
+
+		# Byte Lane internal VREF Select for Rank 0
+		# PSU_DDR_PHY_DX5GCR5_DXREFISELR0                                                 0x55
+
+		# DATX8 n General Configuration Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080C14, 0xFFFFFFFFU ,0x09095555U)  */
+    mask_write 0XFD080C14 0xFFFFFFFF 0x09095555
+		# Register : DX5GCR6 @ 0XFD080C18

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX5GCR6_RESERVED_31_30                                              0x0
+
+		# DRAM DQ VREF Select for Rank3
+		# PSU_DDR_PHY_DX5GCR6_DXDQVREFR3                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX5GCR6_RESERVED_23_22                                              0x0
+
+		# DRAM DQ VREF Select for Rank2
+		# PSU_DDR_PHY_DX5GCR6_DXDQVREFR2                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX5GCR6_RESERVED_15_14                                              0x0
+
+		# DRAM DQ VREF Select for Rank1
+		# PSU_DDR_PHY_DX5GCR6_DXDQVREFR1                                                  0x2b
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX5GCR6_RESERVED_7_6                                                0x0
+
+		# DRAM DQ VREF Select for Rank0
+		# PSU_DDR_PHY_DX5GCR6_DXDQVREFR0                                                  0x2b
+
+		# DATX8 n General Configuration Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU)  */
+    mask_write 0XFD080C18 0xFFFFFFFF 0x09092B2B
+		# Register : DX5LCDLR2 @ 0XFD080C88

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25                                            0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16                                            0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9                                             0x0
+
+		# Read DQS Gating Delay
+		# PSU_DDR_PHY_DX5LCDLR2_DQSGD                                                     0x0
+
+		# DATX8 n Local Calibrated Delay Line Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080C88, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD080C88 0xFFFFFFFF 0x00000000
+		# Register : DX5GTR0 @ 0XFD080CC0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX5GTR0_RESERVED_31_24                                              0x0
+
+		# DQ Write Path Latency Pipeline
+		# PSU_DDR_PHY_DX5GTR0_WDQSL                                                       0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX5GTR0_RESERVED_23_20                                              0x0
+
+		# Write Leveling System Latency
+		# PSU_DDR_PHY_DX5GTR0_WLSL                                                        0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX5GTR0_RESERVED_15_13                                              0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX5GTR0_RESERVED_12_8                                               0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX5GTR0_RESERVED_7_5                                                0x0
+
+		# DQS Gating System Latency
+		# PSU_DDR_PHY_DX5GTR0_DGSL                                                        0x0
+
+		# DATX8 n General Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U)  */
+    mask_write 0XFD080CC0 0xFFFFFFFF 0x00020000
+		# Register : DX6GCR0 @ 0XFD080D00

+
+		# Calibration Bypass
+		# PSU_DDR_PHY_DX6GCR0_CALBYP                                                      0x0
+
+		# Master Delay Line Enable
+		# PSU_DDR_PHY_DX6GCR0_MDLEN                                                       0x1
+
+		# Configurable ODT(TE) Phase Shift
+		# PSU_DDR_PHY_DX6GCR0_CODTSHFT                                                    0x0
+
+		# DQS Duty Cycle Correction
+		# PSU_DDR_PHY_DX6GCR0_DQSDCC                                                      0x0
+
+		# Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		# PSU_DDR_PHY_DX6GCR0_RDDLY                                                       0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX6GCR0_RESERVED_19_14                                              0x0
+
+		# DQSNSE Power Down Receiver
+		# PSU_DDR_PHY_DX6GCR0_DQSNSEPDR                                                   0x0
+
+		# DQSSE Power Down Receiver
+		# PSU_DDR_PHY_DX6GCR0_DQSSEPDR                                                    0x0
+
+		# RTT On Additive Latency
+		# PSU_DDR_PHY_DX6GCR0_RTTOAL                                                      0x0
+
+		# RTT Output Hold
+		# PSU_DDR_PHY_DX6GCR0_RTTOH                                                       0x3
+
+		# Configurable PDR Phase Shift
+		# PSU_DDR_PHY_DX6GCR0_CPDRSHFT                                                    0x0
+
+		# DQSR Power Down
+		# PSU_DDR_PHY_DX6GCR0_DQSRPD                                                      0x0
+
+		# DQSG Power Down Receiver
+		# PSU_DDR_PHY_DX6GCR0_DQSGPDR                                                     0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX6GCR0_RESERVED_4                                                  0x0
+
+		# DQSG On-Die Termination
+		# PSU_DDR_PHY_DX6GCR0_DQSGODT                                                     0x0
+
+		# DQSG Output Enable
+		# PSU_DDR_PHY_DX6GCR0_DQSGOE                                                      0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX6GCR0_RESERVED_1_0                                                0x0
+
+		# DATX8 n General Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080D00, 0xFFFFFFFFU ,0x40800604U)  */
+    mask_write 0XFD080D00 0xFFFFFFFF 0x40800604
+		# Register : DX6GCR1 @ 0XFD080D04

+
+		# Enables the PDR mode for DQ[7:0]
+		# PSU_DDR_PHY_DX6GCR1_DXPDRMODE                                                   0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_DX6GCR1_RESERVED_15                                                 0x0
+
+		# Select the delayed or non-delayed read data strobe #
+		# PSU_DDR_PHY_DX6GCR1_QSNSEL                                                      0x1
+
+		# Select the delayed or non-delayed read data strobe
+		# PSU_DDR_PHY_DX6GCR1_QSSEL                                                       0x1
+
+		# Enables Read Data Strobe in a byte lane
+		# PSU_DDR_PHY_DX6GCR1_OEEN                                                        0x1
+
+		# Enables PDR in a byte lane
+		# PSU_DDR_PHY_DX6GCR1_PDREN                                                       0x1
+
+		# Enables ODT/TE in a byte lane
+		# PSU_DDR_PHY_DX6GCR1_TEEN                                                        0x1
+
+		# Enables Write Data strobe in a byte lane
+		# PSU_DDR_PHY_DX6GCR1_DSEN                                                        0x1
+
+		# Enables DM pin in a byte lane
+		# PSU_DDR_PHY_DX6GCR1_DMEN                                                        0x1
+
+		# Enables DQ corresponding to each bit in a byte
+		# PSU_DDR_PHY_DX6GCR1_DQEN                                                        0xff
+
+		# DATX8 n General Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU)  */
+    mask_write 0XFD080D04 0xFFFFFFFF 0x00007FFF
+		# Register : DX6GCR4 @ 0XFD080D10

+
+		# Byte lane VREF IOM (Used only by D4MU IOs)
+		# PSU_DDR_PHY_DX6GCR4_RESERVED_31_29                                              0x0
+
+		# Byte Lane VREF Pad Enable
+		# PSU_DDR_PHY_DX6GCR4_DXREFPEN                                                    0x0
+
+		# Byte Lane Internal VREF Enable
+		# PSU_DDR_PHY_DX6GCR4_DXREFEEN                                                    0x3
+
+		# Byte Lane Single-End VREF Enable
+		# PSU_DDR_PHY_DX6GCR4_DXREFSEN                                                    0x1
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX6GCR4_RESERVED_24                                                 0x0
+
+		# External VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE                                              0x0
+
+		# Byte Lane External VREF Select
+		# PSU_DDR_PHY_DX6GCR4_DXREFESEL                                                   0x0
+
+		# Single ended VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE                                              0x1
+
+		# Byte Lane Single-End VREF Select
+		# PSU_DDR_PHY_DX6GCR4_DXREFSSEL                                                   0x30
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX6GCR4_RESERVED_7_6                                                0x0
+
+		# VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX6GCR4_DXREFIEN                                                    0xf
+
+		# VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX6GCR4_DXREFIMON                                                   0x0
+
+		# DATX8 n General Configuration Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU)  */
+    mask_write 0XFD080D10 0xFFFFFFFF 0x0E00B03C
+		# Register : DX6GCR5 @ 0XFD080D14

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX6GCR5_RESERVED_31                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 3
+		# PSU_DDR_PHY_DX6GCR5_DXREFISELR3                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX6GCR5_RESERVED_23                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 2
+		# PSU_DDR_PHY_DX6GCR5_DXREFISELR2                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX6GCR5_RESERVED_15                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 1
+		# PSU_DDR_PHY_DX6GCR5_DXREFISELR1                                                 0x55
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX6GCR5_RESERVED_7                                                  0x0
+
+		# Byte Lane internal VREF Select for Rank 0
+		# PSU_DDR_PHY_DX6GCR5_DXREFISELR0                                                 0x55
+
+		# DATX8 n General Configuration Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080D14, 0xFFFFFFFFU ,0x09095555U)  */
+    mask_write 0XFD080D14 0xFFFFFFFF 0x09095555
+		# Register : DX6GCR6 @ 0XFD080D18

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX6GCR6_RESERVED_31_30                                              0x0
+
+		# DRAM DQ VREF Select for Rank3
+		# PSU_DDR_PHY_DX6GCR6_DXDQVREFR3                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX6GCR6_RESERVED_23_22                                              0x0
+
+		# DRAM DQ VREF Select for Rank2
+		# PSU_DDR_PHY_DX6GCR6_DXDQVREFR2                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX6GCR6_RESERVED_15_14                                              0x0
+
+		# DRAM DQ VREF Select for Rank1
+		# PSU_DDR_PHY_DX6GCR6_DXDQVREFR1                                                  0x2b
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX6GCR6_RESERVED_7_6                                                0x0
+
+		# DRAM DQ VREF Select for Rank0
+		# PSU_DDR_PHY_DX6GCR6_DXDQVREFR0                                                  0x2b
+
+		# DATX8 n General Configuration Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU)  */
+    mask_write 0XFD080D18 0xFFFFFFFF 0x09092B2B
+		# Register : DX6LCDLR2 @ 0XFD080D88

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25                                            0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16                                            0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9                                             0x0
+
+		# Read DQS Gating Delay
+		# PSU_DDR_PHY_DX6LCDLR2_DQSGD                                                     0x0
+
+		# DATX8 n Local Calibrated Delay Line Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080D88, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD080D88 0xFFFFFFFF 0x00000000
+		# Register : DX6GTR0 @ 0XFD080DC0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX6GTR0_RESERVED_31_24                                              0x0
+
+		# DQ Write Path Latency Pipeline
+		# PSU_DDR_PHY_DX6GTR0_WDQSL                                                       0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX6GTR0_RESERVED_23_20                                              0x0
+
+		# Write Leveling System Latency
+		# PSU_DDR_PHY_DX6GTR0_WLSL                                                        0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX6GTR0_RESERVED_15_13                                              0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX6GTR0_RESERVED_12_8                                               0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX6GTR0_RESERVED_7_5                                                0x0
+
+		# DQS Gating System Latency
+		# PSU_DDR_PHY_DX6GTR0_DGSL                                                        0x0
+
+		# DATX8 n General Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U)  */
+    mask_write 0XFD080DC0 0xFFFFFFFF 0x00020000
+		# Register : DX7GCR0 @ 0XFD080E00

+
+		# Calibration Bypass
+		# PSU_DDR_PHY_DX7GCR0_CALBYP                                                      0x0
+
+		# Master Delay Line Enable
+		# PSU_DDR_PHY_DX7GCR0_MDLEN                                                       0x1
+
+		# Configurable ODT(TE) Phase Shift
+		# PSU_DDR_PHY_DX7GCR0_CODTSHFT                                                    0x0
+
+		# DQS Duty Cycle Correction
+		# PSU_DDR_PHY_DX7GCR0_DQSDCC                                                      0x0
+
+		# Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		# PSU_DDR_PHY_DX7GCR0_RDDLY                                                       0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX7GCR0_RESERVED_19_14                                              0x0
+
+		# DQSNSE Power Down Receiver
+		# PSU_DDR_PHY_DX7GCR0_DQSNSEPDR                                                   0x0
+
+		# DQSSE Power Down Receiver
+		# PSU_DDR_PHY_DX7GCR0_DQSSEPDR                                                    0x0
+
+		# RTT On Additive Latency
+		# PSU_DDR_PHY_DX7GCR0_RTTOAL                                                      0x0
+
+		# RTT Output Hold
+		# PSU_DDR_PHY_DX7GCR0_RTTOH                                                       0x3
+
+		# Configurable PDR Phase Shift
+		# PSU_DDR_PHY_DX7GCR0_CPDRSHFT                                                    0x0
+
+		# DQSR Power Down
+		# PSU_DDR_PHY_DX7GCR0_DQSRPD                                                      0x0
+
+		# DQSG Power Down Receiver
+		# PSU_DDR_PHY_DX7GCR0_DQSGPDR                                                     0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX7GCR0_RESERVED_4                                                  0x0
+
+		# DQSG On-Die Termination
+		# PSU_DDR_PHY_DX7GCR0_DQSGODT                                                     0x0
+
+		# DQSG Output Enable
+		# PSU_DDR_PHY_DX7GCR0_DQSGOE                                                      0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX7GCR0_RESERVED_1_0                                                0x0
+
+		# DATX8 n General Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080E00, 0xFFFFFFFFU ,0x40800604U)  */
+    mask_write 0XFD080E00 0xFFFFFFFF 0x40800604
+		# Register : DX7GCR1 @ 0XFD080E04

+
+		# Enables the PDR mode for DQ[7:0]
+		# PSU_DDR_PHY_DX7GCR1_DXPDRMODE                                                   0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_DX7GCR1_RESERVED_15                                                 0x0
+
+		# Select the delayed or non-delayed read data strobe #
+		# PSU_DDR_PHY_DX7GCR1_QSNSEL                                                      0x1
+
+		# Select the delayed or non-delayed read data strobe
+		# PSU_DDR_PHY_DX7GCR1_QSSEL                                                       0x1
+
+		# Enables Read Data Strobe in a byte lane
+		# PSU_DDR_PHY_DX7GCR1_OEEN                                                        0x1
+
+		# Enables PDR in a byte lane
+		# PSU_DDR_PHY_DX7GCR1_PDREN                                                       0x1
+
+		# Enables ODT/TE in a byte lane
+		# PSU_DDR_PHY_DX7GCR1_TEEN                                                        0x1
+
+		# Enables Write Data strobe in a byte lane
+		# PSU_DDR_PHY_DX7GCR1_DSEN                                                        0x1
+
+		# Enables DM pin in a byte lane
+		# PSU_DDR_PHY_DX7GCR1_DMEN                                                        0x1
+
+		# Enables DQ corresponding to each bit in a byte
+		# PSU_DDR_PHY_DX7GCR1_DQEN                                                        0xff
+
+		# DATX8 n General Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU)  */
+    mask_write 0XFD080E04 0xFFFFFFFF 0x00007FFF
+		# Register : DX7GCR4 @ 0XFD080E10

+
+		# Byte lane VREF IOM (Used only by D4MU IOs)
+		# PSU_DDR_PHY_DX7GCR4_RESERVED_31_29                                              0x0
+
+		# Byte Lane VREF Pad Enable
+		# PSU_DDR_PHY_DX7GCR4_DXREFPEN                                                    0x0
+
+		# Byte Lane Internal VREF Enable
+		# PSU_DDR_PHY_DX7GCR4_DXREFEEN                                                    0x3
+
+		# Byte Lane Single-End VREF Enable
+		# PSU_DDR_PHY_DX7GCR4_DXREFSEN                                                    0x1
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX7GCR4_RESERVED_24                                                 0x0
+
+		# External VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE                                              0x0
+
+		# Byte Lane External VREF Select
+		# PSU_DDR_PHY_DX7GCR4_DXREFESEL                                                   0x0
+
+		# Single ended VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE                                              0x1
+
+		# Byte Lane Single-End VREF Select
+		# PSU_DDR_PHY_DX7GCR4_DXREFSSEL                                                   0x30
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX7GCR4_RESERVED_7_6                                                0x0
+
+		# VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX7GCR4_DXREFIEN                                                    0xf
+
+		# VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX7GCR4_DXREFIMON                                                   0x0
+
+		# DATX8 n General Configuration Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU)  */
+    mask_write 0XFD080E10 0xFFFFFFFF 0x0E00B03C
+		# Register : DX7GCR5 @ 0XFD080E14

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX7GCR5_RESERVED_31                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 3
+		# PSU_DDR_PHY_DX7GCR5_DXREFISELR3                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX7GCR5_RESERVED_23                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 2
+		# PSU_DDR_PHY_DX7GCR5_DXREFISELR2                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX7GCR5_RESERVED_15                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 1
+		# PSU_DDR_PHY_DX7GCR5_DXREFISELR1                                                 0x55
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX7GCR5_RESERVED_7                                                  0x0
+
+		# Byte Lane internal VREF Select for Rank 0
+		# PSU_DDR_PHY_DX7GCR5_DXREFISELR0                                                 0x55
+
+		# DATX8 n General Configuration Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080E14, 0xFFFFFFFFU ,0x09095555U)  */
+    mask_write 0XFD080E14 0xFFFFFFFF 0x09095555
+		# Register : DX7GCR6 @ 0XFD080E18

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX7GCR6_RESERVED_31_30                                              0x0
+
+		# DRAM DQ VREF Select for Rank3
+		# PSU_DDR_PHY_DX7GCR6_DXDQVREFR3                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX7GCR6_RESERVED_23_22                                              0x0
+
+		# DRAM DQ VREF Select for Rank2
+		# PSU_DDR_PHY_DX7GCR6_DXDQVREFR2                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX7GCR6_RESERVED_15_14                                              0x0
+
+		# DRAM DQ VREF Select for Rank1
+		# PSU_DDR_PHY_DX7GCR6_DXDQVREFR1                                                  0x2b
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX7GCR6_RESERVED_7_6                                                0x0
+
+		# DRAM DQ VREF Select for Rank0
+		# PSU_DDR_PHY_DX7GCR6_DXDQVREFR0                                                  0x2b
+
+		# DATX8 n General Configuration Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU)  */
+    mask_write 0XFD080E18 0xFFFFFFFF 0x09092B2B
+		# Register : DX7LCDLR2 @ 0XFD080E88

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25                                            0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16                                            0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9                                             0x0
+
+		# Read DQS Gating Delay
+		# PSU_DDR_PHY_DX7LCDLR2_DQSGD                                                     0xa
+
+		# DATX8 n Local Calibrated Delay Line Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU)  */
+    mask_write 0XFD080E88 0xFFFFFFFF 0x0000000A
+		# Register : DX7GTR0 @ 0XFD080EC0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX7GTR0_RESERVED_31_24                                              0x0
+
+		# DQ Write Path Latency Pipeline
+		# PSU_DDR_PHY_DX7GTR0_WDQSL                                                       0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX7GTR0_RESERVED_23_20                                              0x0
+
+		# Write Leveling System Latency
+		# PSU_DDR_PHY_DX7GTR0_WLSL                                                        0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX7GTR0_RESERVED_15_13                                              0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX7GTR0_RESERVED_12_8                                               0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX7GTR0_RESERVED_7_5                                                0x0
+
+		# DQS Gating System Latency
+		# PSU_DDR_PHY_DX7GTR0_DGSL                                                        0x0
+
+		# DATX8 n General Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U)  */
+    mask_write 0XFD080EC0 0xFFFFFFFF 0x00020000
+		# Register : DX8GCR0 @ 0XFD080F00

+
+		# Calibration Bypass
+		# PSU_DDR_PHY_DX8GCR0_CALBYP                                                      0x0
+
+		# Master Delay Line Enable
+		# PSU_DDR_PHY_DX8GCR0_MDLEN                                                       0x1
+
+		# Configurable ODT(TE) Phase Shift
+		# PSU_DDR_PHY_DX8GCR0_CODTSHFT                                                    0x0
+
+		# DQS Duty Cycle Correction
+		# PSU_DDR_PHY_DX8GCR0_DQSDCC                                                      0x0
+
+		# Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		# PSU_DDR_PHY_DX8GCR0_RDDLY                                                       0x8
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8GCR0_RESERVED_19_14                                              0x0
+
+		# DQSNSE Power Down Receiver
+		# PSU_DDR_PHY_DX8GCR0_DQSNSEPDR                                                   0x0
+
+		# DQSSE Power Down Receiver
+		# PSU_DDR_PHY_DX8GCR0_DQSSEPDR                                                    0x0
+
+		# RTT On Additive Latency
+		# PSU_DDR_PHY_DX8GCR0_RTTOAL                                                      0x0
+
+		# RTT Output Hold
+		# PSU_DDR_PHY_DX8GCR0_RTTOH                                                       0x3
+
+		# Configurable PDR Phase Shift
+		# PSU_DDR_PHY_DX8GCR0_CPDRSHFT                                                    0x0
+
+		# DQSR Power Down
+		# PSU_DDR_PHY_DX8GCR0_DQSRPD                                                      0x0
+
+		# DQSG Power Down Receiver
+		# PSU_DDR_PHY_DX8GCR0_DQSGPDR                                                     0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8GCR0_RESERVED_4                                                  0x0
+
+		# DQSG On-Die Termination
+		# PSU_DDR_PHY_DX8GCR0_DQSGODT                                                     0x0
+
+		# DQSG Output Enable
+		# PSU_DDR_PHY_DX8GCR0_DQSGOE                                                      0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8GCR0_RESERVED_1_0                                                0x0
+
+		# DATX8 n General Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080F00, 0xFFFFFFFFU ,0x40800624U)  */
+    mask_write 0XFD080F00 0xFFFFFFFF 0x40800624
+		# Register : DX8GCR1 @ 0XFD080F04

+
+		# Enables the PDR mode for DQ[7:0]
+		# PSU_DDR_PHY_DX8GCR1_DXPDRMODE                                                   0x0
+
+		# Reserved. Returns zeroes on reads.
+		# PSU_DDR_PHY_DX8GCR1_RESERVED_15                                                 0x0
+
+		# Select the delayed or non-delayed read data strobe #
+		# PSU_DDR_PHY_DX8GCR1_QSNSEL                                                      0x1
+
+		# Select the delayed or non-delayed read data strobe
+		# PSU_DDR_PHY_DX8GCR1_QSSEL                                                       0x1
+
+		# Enables Read Data Strobe in a byte lane
+		# PSU_DDR_PHY_DX8GCR1_OEEN                                                        0x1
+
+		# Enables PDR in a byte lane
+		# PSU_DDR_PHY_DX8GCR1_PDREN                                                       0x1
+
+		# Enables ODT/TE in a byte lane
+		# PSU_DDR_PHY_DX8GCR1_TEEN                                                        0x1
+
+		# Enables Write Data strobe in a byte lane
+		# PSU_DDR_PHY_DX8GCR1_DSEN                                                        0x1
+
+		# Enables DM pin in a byte lane
+		# PSU_DDR_PHY_DX8GCR1_DMEN                                                        0x1
+
+		# Enables DQ corresponding to each bit in a byte
+		# PSU_DDR_PHY_DX8GCR1_DQEN                                                        0x0
+
+		# DATX8 n General Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U)  */
+    mask_write 0XFD080F04 0xFFFFFFFF 0x00007F00
+		# Register : DX8GCR4 @ 0XFD080F10

+
+		# Byte lane VREF IOM (Used only by D4MU IOs)
+		# PSU_DDR_PHY_DX8GCR4_RESERVED_31_29                                              0x0
+
+		# Byte Lane VREF Pad Enable
+		# PSU_DDR_PHY_DX8GCR4_DXREFPEN                                                    0x0
+
+		# Byte Lane Internal VREF Enable
+		# PSU_DDR_PHY_DX8GCR4_DXREFEEN                                                    0x3
+
+		# Byte Lane Single-End VREF Enable
+		# PSU_DDR_PHY_DX8GCR4_DXREFSEN                                                    0x1
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX8GCR4_RESERVED_24                                                 0x0
+
+		# External VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE                                              0x0
+
+		# Byte Lane External VREF Select
+		# PSU_DDR_PHY_DX8GCR4_DXREFESEL                                                   0x0
+
+		# Single ended VREF generator REFSEL range select
+		# PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE                                              0x1
+
+		# Byte Lane Single-End VREF Select
+		# PSU_DDR_PHY_DX8GCR4_DXREFSSEL                                                   0x30
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX8GCR4_RESERVED_7_6                                                0x0
+
+		# VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX8GCR4_DXREFIEN                                                    0xf
+
+		# VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		# PSU_DDR_PHY_DX8GCR4_DXREFIMON                                                   0x0
+
+		# DATX8 n General Configuration Register 4
+		#(OFFSET, MASK, VALUE)      (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU)  */
+    mask_write 0XFD080F10 0xFFFFFFFF 0x0E00B03C
+		# Register : DX8GCR5 @ 0XFD080F14

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX8GCR5_RESERVED_31                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 3
+		# PSU_DDR_PHY_DX8GCR5_DXREFISELR3                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX8GCR5_RESERVED_23                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 2
+		# PSU_DDR_PHY_DX8GCR5_DXREFISELR2                                                 0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX8GCR5_RESERVED_15                                                 0x0
+
+		# Byte Lane internal VREF Select for Rank 1
+		# PSU_DDR_PHY_DX8GCR5_DXREFISELR1                                                 0x55
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX8GCR5_RESERVED_7                                                  0x0
+
+		# Byte Lane internal VREF Select for Rank 0
+		# PSU_DDR_PHY_DX8GCR5_DXREFISELR0                                                 0x55
+
+		# DATX8 n General Configuration Register 5
+		#(OFFSET, MASK, VALUE)      (0XFD080F14, 0xFFFFFFFFU ,0x09095555U)  */
+    mask_write 0XFD080F14 0xFFFFFFFF 0x09095555
+		# Register : DX8GCR6 @ 0XFD080F18

+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX8GCR6_RESERVED_31_30                                              0x0
+
+		# DRAM DQ VREF Select for Rank3
+		# PSU_DDR_PHY_DX8GCR6_DXDQVREFR3                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX8GCR6_RESERVED_23_22                                              0x0
+
+		# DRAM DQ VREF Select for Rank2
+		# PSU_DDR_PHY_DX8GCR6_DXDQVREFR2                                                  0x9
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX8GCR6_RESERVED_15_14                                              0x0
+
+		# DRAM DQ VREF Select for Rank1
+		# PSU_DDR_PHY_DX8GCR6_DXDQVREFR1                                                  0x2b
+
+		# Reserved. Returns zeros on reads.
+		# PSU_DDR_PHY_DX8GCR6_RESERVED_7_6                                                0x0
+
+		# DRAM DQ VREF Select for Rank0
+		# PSU_DDR_PHY_DX8GCR6_DXDQVREFR0                                                  0x2b
+
+		# DATX8 n General Configuration Register 6
+		#(OFFSET, MASK, VALUE)      (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU)  */
+    mask_write 0XFD080F18 0xFFFFFFFF 0x09092B2B
+		# Register : DX8LCDLR2 @ 0XFD080F88

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25                                            0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16                                            0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9                                             0x0
+
+		# Read DQS Gating Delay
+		# PSU_DDR_PHY_DX8LCDLR2_DQSGD                                                     0x0
+
+		# DATX8 n Local Calibrated Delay Line Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD080F88, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFD080F88 0xFFFFFFFF 0x00000000
+		# Register : DX8GTR0 @ 0XFD080FC0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8GTR0_RESERVED_31_24                                              0x0
+
+		# DQ Write Path Latency Pipeline
+		# PSU_DDR_PHY_DX8GTR0_WDQSL                                                       0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX8GTR0_RESERVED_23_20                                              0x0
+
+		# Write Leveling System Latency
+		# PSU_DDR_PHY_DX8GTR0_WLSL                                                        0x2
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8GTR0_RESERVED_15_13                                              0x0
+
+		# Reserved. Caution, do not write to this register field.
+		# PSU_DDR_PHY_DX8GTR0_RESERVED_12_8                                               0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8GTR0_RESERVED_7_5                                                0x0
+
+		# DQS Gating System Latency
+		# PSU_DDR_PHY_DX8GTR0_DGSL                                                        0x0
+
+		# DATX8 n General Timing Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U)  */
+    mask_write 0XFD080FC0 0xFFFFFFFF 0x00020000
+		# Register : DX8SL0DQSCTL @ 0XFD08141C

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25                                         0x0
+
+		# Read Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE                                                0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22                                         0x0
+
+		# Write Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE                                                0x1
+
+		# DQS Gate Extension
+		# PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX                                                  0x0
+
+		# Low Power PLL Power Down
+		# PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD                                                0x1
+
+		# Low Power I/O Power Down
+		# PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD                                                 0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15                                         0x0
+
+		# QS Counter Enable
+		# PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN                                                0x1
+
+		# Unused DQ I/O Mode
+		# PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10                                         0x0
+
+		# Data Slew Rate
+		# PSU_DDR_PHY_DX8SL0DQSCTL_DXSR                                                   0x3
+
+		# DQS_N Resistor
+		# PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES                                                0xc
+
+		# DQS Resistor
+		# PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES                                                 0x4
+
+		# DATX8 0-1 DQS Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD08141C, 0xFFFFFFFFU ,0x012643C4U)  */
+    mask_write 0XFD08141C 0xFFFFFFFF 0x012643C4
+		# Register : DX8SL0DXCTL2 @ 0XFD08142C

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24                                         0x0
+
+		# Configurable Read Data Enable
+		# PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN                                                  0x0
+
+		# OX Extension during Post-amble
+		# PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX                                                 0x0
+
+		# OE Extension during Pre-amble
+		# PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17                                            0x0
+
+		# I/O Assisted Gate Select
+		# PSU_DDR_PHY_DX8SL0DXCTL2_IOAG                                                   0x0
+
+		# I/O Loopback Select
+		# PSU_DDR_PHY_DX8SL0DXCTL2_IOLB                                                   0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13                                         0x0
+
+		# Low Power Wakeup Threshold
+		# PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		# Read Data Bus Inversion Enable
+		# PSU_DDR_PHY_DX8SL0DXCTL2_RDBI                                                   0x0
+
+		# Write Data Bus Inversion Enable
+		# PSU_DDR_PHY_DX8SL0DXCTL2_WDBI                                                   0x0
+
+		# PUB Read FIFO Bypass
+		# PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP                                                 0x0
+
+		# DATX8 Receive FIFO Read Mode
+		# PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE                                                 0x0
+
+		# Disables the Read FIFO Reset
+		# PSU_DDR_PHY_DX8SL0DXCTL2_DISRST                                                 0x0
+
+		# Read DQS Gate I/O Loopback
+		# PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0                                             0x0
+
+		# DATX8 0-1 DX Control Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD08142C, 0xFFFFFFFFU ,0x00001800U)  */
+    mask_write 0XFD08142C 0xFFFFFFFF 0x00001800
+		# Register : DX8SL0IOCR @ 0XFD081430

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31                                              0x0
+
+		# PVREF_DAC REFSEL range select
+		# PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE                                               0x7
+
+		# IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		# PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM                                                0x0
+
+		# DX IO Mode
+		# PSU_DDR_PHY_DX8SL0IOCR_DXIOM                                                    0x2
+
+		# DX IO Transmitter Mode
+		# PSU_DDR_PHY_DX8SL0IOCR_DXTXM                                                    0x0
+
+		# DX IO Receiver Mode
+		# PSU_DDR_PHY_DX8SL0IOCR_DXRXM                                                    0x0
+
+		# DATX8 0-1 I/O Configuration Register
+		#(OFFSET, MASK, VALUE)      (0XFD081430, 0xFFFFFFFFU ,0x70800000U)  */
+    mask_write 0XFD081430 0xFFFFFFFF 0x70800000
+		# Register : DX8SL1DQSCTL @ 0XFD08145C

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25                                         0x0
+
+		# Read Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE                                                0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22                                         0x0
+
+		# Write Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE                                                0x1
+
+		# DQS Gate Extension
+		# PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX                                                  0x0
+
+		# Low Power PLL Power Down
+		# PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD                                                0x1
+
+		# Low Power I/O Power Down
+		# PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD                                                 0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15                                         0x0
+
+		# QS Counter Enable
+		# PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN                                                0x1
+
+		# Unused DQ I/O Mode
+		# PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10                                         0x0
+
+		# Data Slew Rate
+		# PSU_DDR_PHY_DX8SL1DQSCTL_DXSR                                                   0x3
+
+		# DQS_N Resistor
+		# PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES                                                0xc
+
+		# DQS Resistor
+		# PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES                                                 0x4
+
+		# DATX8 0-1 DQS Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD08145C, 0xFFFFFFFFU ,0x012643C4U)  */
+    mask_write 0XFD08145C 0xFFFFFFFF 0x012643C4
+		# Register : DX8SL1DXCTL2 @ 0XFD08146C

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24                                         0x0
+
+		# Configurable Read Data Enable
+		# PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN                                                  0x0
+
+		# OX Extension during Post-amble
+		# PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX                                                 0x0
+
+		# OE Extension during Pre-amble
+		# PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17                                            0x0
+
+		# I/O Assisted Gate Select
+		# PSU_DDR_PHY_DX8SL1DXCTL2_IOAG                                                   0x0
+
+		# I/O Loopback Select
+		# PSU_DDR_PHY_DX8SL1DXCTL2_IOLB                                                   0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13                                         0x0
+
+		# Low Power Wakeup Threshold
+		# PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		# Read Data Bus Inversion Enable
+		# PSU_DDR_PHY_DX8SL1DXCTL2_RDBI                                                   0x0
+
+		# Write Data Bus Inversion Enable
+		# PSU_DDR_PHY_DX8SL1DXCTL2_WDBI                                                   0x0
+
+		# PUB Read FIFO Bypass
+		# PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP                                                 0x0
+
+		# DATX8 Receive FIFO Read Mode
+		# PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE                                                 0x0
+
+		# Disables the Read FIFO Reset
+		# PSU_DDR_PHY_DX8SL1DXCTL2_DISRST                                                 0x0
+
+		# Read DQS Gate I/O Loopback
+		# PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0                                             0x0
+
+		# DATX8 0-1 DX Control Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD08146C, 0xFFFFFFFFU ,0x00001800U)  */
+    mask_write 0XFD08146C 0xFFFFFFFF 0x00001800
+		# Register : DX8SL1IOCR @ 0XFD081470

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31                                              0x0
+
+		# PVREF_DAC REFSEL range select
+		# PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE                                               0x7
+
+		# IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		# PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM                                                0x0
+
+		# DX IO Mode
+		# PSU_DDR_PHY_DX8SL1IOCR_DXIOM                                                    0x2
+
+		# DX IO Transmitter Mode
+		# PSU_DDR_PHY_DX8SL1IOCR_DXTXM                                                    0x0
+
+		# DX IO Receiver Mode
+		# PSU_DDR_PHY_DX8SL1IOCR_DXRXM                                                    0x0
+
+		# DATX8 0-1 I/O Configuration Register
+		#(OFFSET, MASK, VALUE)      (0XFD081470, 0xFFFFFFFFU ,0x70800000U)  */
+    mask_write 0XFD081470 0xFFFFFFFF 0x70800000
+		# Register : DX8SL2DQSCTL @ 0XFD08149C

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25                                         0x0
+
+		# Read Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE                                                0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22                                         0x0
+
+		# Write Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE                                                0x1
+
+		# DQS Gate Extension
+		# PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX                                                  0x0
+
+		# Low Power PLL Power Down
+		# PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD                                                0x1
+
+		# Low Power I/O Power Down
+		# PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD                                                 0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15                                         0x0
+
+		# QS Counter Enable
+		# PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN                                                0x1
+
+		# Unused DQ I/O Mode
+		# PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10                                         0x0
+
+		# Data Slew Rate
+		# PSU_DDR_PHY_DX8SL2DQSCTL_DXSR                                                   0x3
+
+		# DQS_N Resistor
+		# PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES                                                0xc
+
+		# DQS Resistor
+		# PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES                                                 0x4
+
+		# DATX8 0-1 DQS Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD08149C, 0xFFFFFFFFU ,0x012643C4U)  */
+    mask_write 0XFD08149C 0xFFFFFFFF 0x012643C4
+		# Register : DX8SL2DXCTL2 @ 0XFD0814AC

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24                                         0x0
+
+		# Configurable Read Data Enable
+		# PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN                                                  0x0
+
+		# OX Extension during Post-amble
+		# PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX                                                 0x0
+
+		# OE Extension during Pre-amble
+		# PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17                                            0x0
+
+		# I/O Assisted Gate Select
+		# PSU_DDR_PHY_DX8SL2DXCTL2_IOAG                                                   0x0
+
+		# I/O Loopback Select
+		# PSU_DDR_PHY_DX8SL2DXCTL2_IOLB                                                   0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13                                         0x0
+
+		# Low Power Wakeup Threshold
+		# PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		# Read Data Bus Inversion Enable
+		# PSU_DDR_PHY_DX8SL2DXCTL2_RDBI                                                   0x0
+
+		# Write Data Bus Inversion Enable
+		# PSU_DDR_PHY_DX8SL2DXCTL2_WDBI                                                   0x0
+
+		# PUB Read FIFO Bypass
+		# PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP                                                 0x0
+
+		# DATX8 Receive FIFO Read Mode
+		# PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE                                                 0x0
+
+		# Disables the Read FIFO Reset
+		# PSU_DDR_PHY_DX8SL2DXCTL2_DISRST                                                 0x0
+
+		# Read DQS Gate I/O Loopback
+		# PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0                                             0x0
+
+		# DATX8 0-1 DX Control Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD0814AC, 0xFFFFFFFFU ,0x00001800U)  */
+    mask_write 0XFD0814AC 0xFFFFFFFF 0x00001800
+		# Register : DX8SL2IOCR @ 0XFD0814B0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31                                              0x0
+
+		# PVREF_DAC REFSEL range select
+		# PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE                                               0x7
+
+		# IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		# PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM                                                0x0
+
+		# DX IO Mode
+		# PSU_DDR_PHY_DX8SL2IOCR_DXIOM                                                    0x2
+
+		# DX IO Transmitter Mode
+		# PSU_DDR_PHY_DX8SL2IOCR_DXTXM                                                    0x0
+
+		# DX IO Receiver Mode
+		# PSU_DDR_PHY_DX8SL2IOCR_DXRXM                                                    0x0
+
+		# DATX8 0-1 I/O Configuration Register
+		#(OFFSET, MASK, VALUE)      (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U)  */
+    mask_write 0XFD0814B0 0xFFFFFFFF 0x70800000
+		# Register : DX8SL3DQSCTL @ 0XFD0814DC

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25                                         0x0
+
+		# Read Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE                                                0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22                                         0x0
+
+		# Write Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE                                                0x1
+
+		# DQS Gate Extension
+		# PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX                                                  0x0
+
+		# Low Power PLL Power Down
+		# PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD                                                0x1
+
+		# Low Power I/O Power Down
+		# PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD                                                 0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15                                         0x0
+
+		# QS Counter Enable
+		# PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN                                                0x1
+
+		# Unused DQ I/O Mode
+		# PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10                                         0x0
+
+		# Data Slew Rate
+		# PSU_DDR_PHY_DX8SL3DQSCTL_DXSR                                                   0x3
+
+		# DQS_N Resistor
+		# PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES                                                0xc
+
+		# DQS Resistor
+		# PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES                                                 0x4
+
+		# DATX8 0-1 DQS Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD0814DC, 0xFFFFFFFFU ,0x012643C4U)  */
+    mask_write 0XFD0814DC 0xFFFFFFFF 0x012643C4
+		# Register : DX8SL3DXCTL2 @ 0XFD0814EC

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24                                         0x0
+
+		# Configurable Read Data Enable
+		# PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN                                                  0x0
+
+		# OX Extension during Post-amble
+		# PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX                                                 0x0
+
+		# OE Extension during Pre-amble
+		# PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17                                            0x0
+
+		# I/O Assisted Gate Select
+		# PSU_DDR_PHY_DX8SL3DXCTL2_IOAG                                                   0x0
+
+		# I/O Loopback Select
+		# PSU_DDR_PHY_DX8SL3DXCTL2_IOLB                                                   0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13                                         0x0
+
+		# Low Power Wakeup Threshold
+		# PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		# Read Data Bus Inversion Enable
+		# PSU_DDR_PHY_DX8SL3DXCTL2_RDBI                                                   0x0
+
+		# Write Data Bus Inversion Enable
+		# PSU_DDR_PHY_DX8SL3DXCTL2_WDBI                                                   0x0
+
+		# PUB Read FIFO Bypass
+		# PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP                                                 0x0
+
+		# DATX8 Receive FIFO Read Mode
+		# PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE                                                 0x0
+
+		# Disables the Read FIFO Reset
+		# PSU_DDR_PHY_DX8SL3DXCTL2_DISRST                                                 0x0
+
+		# Read DQS Gate I/O Loopback
+		# PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0                                             0x0
+
+		# DATX8 0-1 DX Control Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD0814EC, 0xFFFFFFFFU ,0x00001800U)  */
+    mask_write 0XFD0814EC 0xFFFFFFFF 0x00001800
+		# Register : DX8SL3IOCR @ 0XFD0814F0

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31                                              0x0
+
+		# PVREF_DAC REFSEL range select
+		# PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE                                               0x7
+
+		# IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		# PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM                                                0x0
+
+		# DX IO Mode
+		# PSU_DDR_PHY_DX8SL3IOCR_DXIOM                                                    0x2
+
+		# DX IO Transmitter Mode
+		# PSU_DDR_PHY_DX8SL3IOCR_DXTXM                                                    0x0
+
+		# DX IO Receiver Mode
+		# PSU_DDR_PHY_DX8SL3IOCR_DXRXM                                                    0x0
+
+		# DATX8 0-1 I/O Configuration Register
+		#(OFFSET, MASK, VALUE)      (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U)  */
+    mask_write 0XFD0814F0 0xFFFFFFFF 0x70800000
+		# Register : DX8SL4DQSCTL @ 0XFD08151C

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25                                         0x0
+
+		# Read Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE                                                0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22                                         0x0
+
+		# Write Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE                                                0x1
+
+		# DQS Gate Extension
+		# PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX                                                  0x0
+
+		# Low Power PLL Power Down
+		# PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD                                                0x1
+
+		# Low Power I/O Power Down
+		# PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD                                                 0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15                                         0x0
+
+		# QS Counter Enable
+		# PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN                                                0x1
+
+		# Unused DQ I/O Mode
+		# PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10                                         0x0
+
+		# Data Slew Rate
+		# PSU_DDR_PHY_DX8SL4DQSCTL_DXSR                                                   0x3
+
+		# DQS_N Resistor
+		# PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES                                                0xc
+
+		# DQS Resistor
+		# PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES                                                 0x4
+
+		# DATX8 0-1 DQS Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD08151C, 0xFFFFFFFFU ,0x012643C4U)  */
+    mask_write 0XFD08151C 0xFFFFFFFF 0x012643C4
+		# Register : DX8SL4DXCTL2 @ 0XFD08152C

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24                                         0x0
+
+		# Configurable Read Data Enable
+		# PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN                                                  0x0
+
+		# OX Extension during Post-amble
+		# PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX                                                 0x0
+
+		# OE Extension during Pre-amble
+		# PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17                                            0x0
+
+		# I/O Assisted Gate Select
+		# PSU_DDR_PHY_DX8SL4DXCTL2_IOAG                                                   0x0
+
+		# I/O Loopback Select
+		# PSU_DDR_PHY_DX8SL4DXCTL2_IOLB                                                   0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13                                         0x0
+
+		# Low Power Wakeup Threshold
+		# PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		# Read Data Bus Inversion Enable
+		# PSU_DDR_PHY_DX8SL4DXCTL2_RDBI                                                   0x0
+
+		# Write Data Bus Inversion Enable
+		# PSU_DDR_PHY_DX8SL4DXCTL2_WDBI                                                   0x0
+
+		# PUB Read FIFO Bypass
+		# PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP                                                 0x0
+
+		# DATX8 Receive FIFO Read Mode
+		# PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE                                                 0x0
+
+		# Disables the Read FIFO Reset
+		# PSU_DDR_PHY_DX8SL4DXCTL2_DISRST                                                 0x0
+
+		# Read DQS Gate I/O Loopback
+		# PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0                                             0x0
+
+		# DATX8 0-1 DX Control Register 2
+		#(OFFSET, MASK, VALUE)      (0XFD08152C, 0xFFFFFFFFU ,0x00001800U)  */
+    mask_write 0XFD08152C 0xFFFFFFFF 0x00001800
+		# Register : DX8SL4IOCR @ 0XFD081530

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31                                              0x0
+
+		# PVREF_DAC REFSEL range select
+		# PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE                                               0x7
+
+		# IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		# PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM                                                0x0
+
+		# DX IO Mode
+		# PSU_DDR_PHY_DX8SL4IOCR_DXIOM                                                    0x2
+
+		# DX IO Transmitter Mode
+		# PSU_DDR_PHY_DX8SL4IOCR_DXTXM                                                    0x0
+
+		# DX IO Receiver Mode
+		# PSU_DDR_PHY_DX8SL4IOCR_DXRXM                                                    0x0
+
+		# DATX8 0-1 I/O Configuration Register
+		#(OFFSET, MASK, VALUE)      (0XFD081530, 0xFFFFFFFFU ,0x70800000U)  */
+    mask_write 0XFD081530 0xFFFFFFFF 0x70800000
+		# Register : DX8SLbDQSCTL @ 0XFD0817DC

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25                                         0x0
+
+		# Read Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE                                                0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22                                         0x0
+
+		# Write Path Rise-to-Rise Mode
+		# PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE                                                0x1
+
+		# DQS Gate Extension
+		# PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX                                                  0x0
+
+		# Low Power PLL Power Down
+		# PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD                                                0x1
+
+		# Low Power I/O Power Down
+		# PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD                                                 0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15                                         0x0
+
+		# QS Counter Enable
+		# PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN                                                0x1
+
+		# Unused DQ I/O Mode
+		# PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM                                                 0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10                                         0x0
+
+		# Data Slew Rate
+		# PSU_DDR_PHY_DX8SLBDQSCTL_DXSR                                                   0x3
+
+		# DQS# Resistor
+		# PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES                                                0xc
+
+		# DQS Resistor
+		# PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES                                                 0x4
+
+		# DATX8 0-8 DQS Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U)  */
+    mask_write 0XFD0817DC 0xFFFFFFFF 0x012643C4
+		# Register : PIR @ 0XFD080004

+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_PIR_RESERVED_31                                                     0x0
+
+		# Impedance Calibration Bypass
+		# PSU_DDR_PHY_PIR_ZCALBYP                                                         0x0
+
+		# Digital Delay Line (DDL) Calibration Pause
+		# PSU_DDR_PHY_PIR_DCALPSE                                                         0x0
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_PIR_RESERVED_28_21                                                  0x0
+
+		# Write DQS2DQ Training
+		# PSU_DDR_PHY_PIR_DQS2DQ                                                          0x0
+
+		# RDIMM Initialization
+		# PSU_DDR_PHY_PIR_RDIMMINIT                                                       0x0
+
+		# Controller DRAM Initialization
+		# PSU_DDR_PHY_PIR_CTLDINIT                                                        0x1
+
+		# VREF Training
+		# PSU_DDR_PHY_PIR_VREF                                                            0x0
+
+		# Static Read Training
+		# PSU_DDR_PHY_PIR_SRD                                                             0x0
+
+		# Write Data Eye Training
+		# PSU_DDR_PHY_PIR_WREYE                                                           0x0
+
+		# Read Data Eye Training
+		# PSU_DDR_PHY_PIR_RDEYE                                                           0x0
+
+		# Write Data Bit Deskew
+		# PSU_DDR_PHY_PIR_WRDSKW                                                          0x0
+
+		# Read Data Bit Deskew
+		# PSU_DDR_PHY_PIR_RDDSKW                                                          0x0
+
+		# Write Leveling Adjust
+		# PSU_DDR_PHY_PIR_WLADJ                                                           0x0
+
+		# Read DQS Gate Training
+		# PSU_DDR_PHY_PIR_QSGATE                                                          0x0
+
+		# Write Leveling
+		# PSU_DDR_PHY_PIR_WL                                                              0x0
+
+		# DRAM Initialization
+		# PSU_DDR_PHY_PIR_DRAMINIT                                                        0x0
+
+		# DRAM Reset (DDR3/DDR4/LPDDR4 Only)
+		# PSU_DDR_PHY_PIR_DRAMRST                                                         0x0
+
+		# PHY Reset
+		# PSU_DDR_PHY_PIR_PHYRST                                                          0x1
+
+		# Digital Delay Line (DDL) Calibration
+		# PSU_DDR_PHY_PIR_DCAL                                                            0x1
+
+		# PLL Initialiazation
+		# PSU_DDR_PHY_PIR_PLLINIT                                                         0x1
+
+		# Reserved. Return zeroes on reads.
+		# PSU_DDR_PHY_PIR_RESERVED_3                                                      0x0
+
+		# CA Training
+		# PSU_DDR_PHY_PIR_CA                                                              0x0
+
+		# Impedance Calibration
+		# PSU_DDR_PHY_PIR_ZCAL                                                            0x1
+
+		# Initialization Trigger
+		# PSU_DDR_PHY_PIR_INIT                                                            0x1
+
+		# PHY Initialization Register
+		#(OFFSET, MASK, VALUE)      (0XFD080004, 0xFFFFFFFFU ,0x00040073U)  */
+    mask_write 0XFD080004 0xFFFFFFFF 0x00040073
+}
+
+set psu_mio_init_data {
+		# : MIO PROGRAMMING
+		# Register : MIO_PIN_0 @ 0XFF180000

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
+		# PSU_IOU_SLCR_MIO_PIN_0_L0_SEL                                                   1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_0_L1_SEL                                                   0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
+		# t, test_scan_out[0]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_0_L2_SEL                                                   0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
+		# , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		# ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		# ) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		# lk- (Trace Port Clock)
+		# PSU_IOU_SLCR_MIO_PIN_0_L3_SEL                                                   0
+
+		# Configures MIO Pin 0 peripheral interface mapping. S
+		#(OFFSET, MASK, VALUE)      (0XFF180000, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180000 0x000000FE 0x00000002
+		# Register : MIO_PIN_1 @ 0XFF180004

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
+		# us)
+		# PSU_IOU_SLCR_MIO_PIN_1_L0_SEL                                                   1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_1_L1_SEL                                                   0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
+		# t, test_scan_out[1]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_1_L2_SEL                                                   0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
+		# , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		#  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
+		# t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		# Signal)
+		# PSU_IOU_SLCR_MIO_PIN_1_L3_SEL                                                   0
+
+		# Configures MIO Pin 1 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180004, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180004 0x000000FE 0x00000002
+		# Register : MIO_PIN_2 @ 0XFF180008

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
+		# PSU_IOU_SLCR_MIO_PIN_2_L0_SEL                                                   1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_2_L1_SEL                                                   0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
+		# t, test_scan_out[2]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_2_L2_SEL                                                   0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
+		# , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		#  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
+		#  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_2_L3_SEL                                                   0
+
+		# Configures MIO Pin 2 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180008, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180008 0x000000FE 0x00000002
+		# Register : MIO_PIN_3 @ 0XFF18000C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
+		# PSU_IOU_SLCR_MIO_PIN_3_L0_SEL                                                   1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_3_L1_SEL                                                   0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
+		# t, test_scan_out[3]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_3_L2_SEL                                                   0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
+		# , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		# ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		# - (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		# output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_3_L3_SEL                                                   0
+
+		# Configures MIO Pin 3 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18000C, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF18000C 0x000000FE 0x00000002
+		# Register : MIO_PIN_4 @ 0XFF180010

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
+		# us)
+		# PSU_IOU_SLCR_MIO_PIN_4_L0_SEL                                                   1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_4_L1_SEL                                                   0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
+		# t, test_scan_out[4]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_4_L2_SEL                                                   0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
+		# , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		# ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		# - (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		# utput, tracedq[2]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_4_L3_SEL                                                   0
+
+		# Configures MIO Pin 4 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180010, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180010 0x000000FE 0x00000002
+		# Register : MIO_PIN_5 @ 0XFF180014

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)
+		# PSU_IOU_SLCR_MIO_PIN_5_L0_SEL                                                   1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_5_L1_SEL                                                   0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
+		# t, test_scan_out[5]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_5_L2_SEL                                                   0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
+		# , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		#  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		# si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		#  trace, Output, tracedq[3]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_5_L3_SEL                                                   0
+
+		# Configures MIO Pin 5 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180014, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180014 0x000000FE 0x00000002
+		# Register : MIO_PIN_6 @ 0XFF180018

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
+		# PSU_IOU_SLCR_MIO_PIN_6_L0_SEL                                                   1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_6_L1_SEL                                                   0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
+		# t, test_scan_out[6]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_6_L2_SEL                                                   0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
+		# , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		#  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
+		# sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
+		# Output, tracedq[4]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_6_L3_SEL                                                   0
+
+		# Configures MIO Pin 6 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180018, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180018 0x000000FE 0x00000002
+		# Register : MIO_PIN_7 @ 0XFF18001C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)
+		# PSU_IOU_SLCR_MIO_PIN_7_L0_SEL                                                   1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_7_L1_SEL                                                   0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
+		# t, test_scan_out[7]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_7_L2_SEL                                                   0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
+		# , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		# ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= 
+		# tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, 
+		# racedq[5]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_7_L3_SEL                                                   0
+
+		# Configures MIO Pin 7 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18001C, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF18001C 0x000000FE 0x00000002
+		# Register : MIO_PIN_8 @ 0XFF180020

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		# [0]- (QSPI Upper Databus)
+		# PSU_IOU_SLCR_MIO_PIN_8_L0_SEL                                                   1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_8_L1_SEL                                                   0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
+		# t, test_scan_out[8]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_8_L2_SEL                                                   0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
+		# , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		# ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
+		# , Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
+		# ce Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_8_L3_SEL                                                   0
+
+		# Configures MIO Pin 8 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180020, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180020 0x000000FE 0x00000002
+		# Register : MIO_PIN_9 @ 0XFF180024

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		# [1]- (QSPI Upper Databus)
+		# PSU_IOU_SLCR_MIO_PIN_9_L0_SEL                                                   1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+		# PSU_IOU_SLCR_MIO_PIN_9_L1_SEL                                                   0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
+		# t, test_scan_out[9]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_9_L2_SEL                                                   0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
+		# , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		#  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, 
+		# utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
+		# RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_9_L3_SEL                                                   0
+
+		# Configures MIO Pin 9 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180024, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180024 0x000000FE 0x00000002
+		# Register : MIO_PIN_10 @ 0XFF180028

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		# [2]- (QSPI Upper Databus)
+		# PSU_IOU_SLCR_MIO_PIN_10_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+		# PSU_IOU_SLCR_MIO_PIN_10_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
+		# ut, test_scan_out[10]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_10_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		# o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		# t, tracedq[8]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_10_L3_SEL                                                  0
+
+		# Configures MIO Pin 10 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180028, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180028 0x000000FE 0x00000002
+		# Register : MIO_PIN_11 @ 0XFF18002C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		# [3]- (QSPI Upper Databus)
+		# PSU_IOU_SLCR_MIO_PIN_11_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+		# PSU_IOU_SLCR_MIO_PIN_11_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
+		# ut, test_scan_out[11]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_11_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		# i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		# tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_11_L3_SEL                                                  0
+
+		# Configures MIO Pin 11 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18002C, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF18002C 0x000000FE 0x00000002
+		# Register : MIO_PIN_12 @ 0XFF180030

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
+		# PSU_IOU_SLCR_MIO_PIN_12_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		# 
+		# PSU_IOU_SLCR_MIO_PIN_12_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
+		# ut, test_scan_out[12]- (Test Scan Port) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_12_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
+		# ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
+		# dq[10]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_12_L3_SEL                                                  0
+
+		# Configures MIO Pin 12 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180030, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180030 0x000000FE 0x00000002
+		# Register : MIO_PIN_13 @ 0XFF180034

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_13_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)
+		# PSU_IOU_SLCR_MIO_PIN_13_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		# bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
+		#  3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_13_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
+		# out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
+		# bus)
+		# PSU_IOU_SLCR_MIO_PIN_13_L3_SEL                                                  0
+
+		# Configures MIO Pin 13 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180034, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF180034 0x000000FE 0x00000000
+		# Register : MIO_PIN_14 @ 0XFF180038

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_14_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)
+		# PSU_IOU_SLCR_MIO_PIN_14_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		# bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
+		#  3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_14_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
+		# n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_14_L3_SEL                                                  2
+
+		# Configures MIO Pin 14 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180038, 0x000000FEU ,0x00000040U)  */
+    mask_write 0XFF180038 0x000000FE 0x00000040
+		# Register : MIO_PIN_15 @ 0XFF18003C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_15_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)
+		# PSU_IOU_SLCR_MIO_PIN_15_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		# bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
+		#  3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_15_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
+		# 0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
+		# l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_15_L3_SEL                                                  2
+
+		# Configures MIO Pin 15 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18003C, 0x000000FEU ,0x00000040U)  */
+    mask_write 0XFF18003C 0x000000FE 0x00000040
+		# Register : MIO_PIN_16 @ 0XFF180040

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_16_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND 
+		# ata Bus)
+		# PSU_IOU_SLCR_MIO_PIN_16_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		# bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
+		#  3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_16_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		# so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		#  Output, tracedq[14]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_16_L3_SEL                                                  2
+
+		# Configures MIO Pin 16 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180040, 0x000000FEU ,0x00000040U)  */
+    mask_write 0XFF180040 0x000000FE 0x00000040
+		# Register : MIO_PIN_17 @ 0XFF180044

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_17_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND 
+		# ata Bus)
+		# PSU_IOU_SLCR_MIO_PIN_17_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		# bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
+		#  3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_17_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		# 0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		# 7= trace, Output, tracedq[15]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_17_L3_SEL                                                  2
+
+		# Configures MIO Pin 17 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180044, 0x000000FEU ,0x00000040U)  */
+    mask_write 0XFF180044 0x000000FE 0x00000040
+		# Register : MIO_PIN_18 @ 0XFF180048

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_18_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND 
+		# ata Bus)
+		# PSU_IOU_SLCR_MIO_PIN_18_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		# bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
+		#  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		# PSU_IOU_SLCR_MIO_PIN_18_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		# o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_18_L3_SEL                                                  6
+
+		# Configures MIO Pin 18 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180048, 0x000000FEU ,0x000000C0U)  */
+    mask_write 0XFF180048 0x000000FE 0x000000C0
+		# Register : MIO_PIN_19 @ 0XFF18004C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_19_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND 
+		# ata Bus)
+		# PSU_IOU_SLCR_MIO_PIN_19_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		# bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
+		#  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		# PSU_IOU_SLCR_MIO_PIN_19_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		#  ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_19_L3_SEL                                                  6
+
+		# Configures MIO Pin 19 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18004C, 0x000000FEU ,0x000000C0U)  */
+    mask_write 0XFF18004C 0x000000FE 0x000000C0
+		# Register : MIO_PIN_20 @ 0XFF180050

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_20_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND 
+		# ata Bus)
+		# PSU_IOU_SLCR_MIO_PIN_20_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		# bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
+		#  3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		# PSU_IOU_SLCR_MIO_PIN_20_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
+		# c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_20_L3_SEL                                                  6
+
+		# Configures MIO Pin 20 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180050, 0x000000FEU ,0x000000C0U)  */
+    mask_write 0XFF180050 0x000000FE 0x000000C0
+		# Register : MIO_PIN_21 @ 0XFF180054

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_21_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND 
+		# ata Bus)
+		# PSU_IOU_SLCR_MIO_PIN_21_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		#  Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 
+		# = csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		# PSU_IOU_SLCR_MIO_PIN_21_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		#  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- 
+		# UART receiver serial input) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_21_L3_SEL                                                  6
+
+		# Configures MIO Pin 21 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180054, 0x000000FEU ,0x000000C0U)  */
+    mask_write 0XFF180054 0x000000FE 0x000000C0
+		# Register : MIO_PIN_22 @ 0XFF180058

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_22_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)
+		# PSU_IOU_SLCR_MIO_PIN_22_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
+		# (Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		# PSU_IOU_SLCR_MIO_PIN_22_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		# 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		# sed
+		# PSU_IOU_SLCR_MIO_PIN_22_L3_SEL                                                  0
+
+		# Configures MIO Pin 22 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180058, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF180058 0x000000FE 0x00000000
+		# Register : MIO_PIN_23 @ 0XFF18005C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_23_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND 
+		# ata Bus)
+		# PSU_IOU_SLCR_MIO_PIN_23_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
+		# 23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
+		# 
+		# PSU_IOU_SLCR_MIO_PIN_23_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		# i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		# tput) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_23_L3_SEL                                                  0
+
+		# Configures MIO Pin 23 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18005C, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF18005C 0x000000FE 0x00000000
+		# Register : MIO_PIN_24 @ 0XFF180060

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_24_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND 
+		# ata Bus)
+		# PSU_IOU_SLCR_MIO_PIN_24_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
+		# scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
+		#  Tamper)
+		# PSU_IOU_SLCR_MIO_PIN_24_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
+		# Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_24_L3_SEL                                                  1
+
+		# Configures MIO Pin 24 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180060, 0x000000FEU ,0x00000020U)  */
+    mask_write 0XFF180060 0x000000FE 0x00000020
+		# Register : MIO_PIN_25 @ 0XFF180064

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_25_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)
+		# PSU_IOU_SLCR_MIO_PIN_25_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
+		# test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
+		# U Ext Tamper)
+		# PSU_IOU_SLCR_MIO_PIN_25_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform 
+		# lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_25_L3_SEL                                                  1
+
+		# Configures MIO Pin 25 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180064, 0x000000FEU ,0x00000020U)  */
+    mask_write 0XFF180064 0x000000FE 0x00000020
+		# Register : MIO_PIN_26 @ 0XFF180068

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
+		# PSU_IOU_SLCR_MIO_PIN_26_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+		# PSU_IOU_SLCR_MIO_PIN_26_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
+		# n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		# PSU_IOU_SLCR_MIO_PIN_26_L2_SEL                                                  1
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
+		# , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		#  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
+		#  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		# Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_26_L3_SEL                                                  0
+
+		# Configures MIO Pin 26 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180068, 0x000000FEU ,0x00000008U)  */
+    mask_write 0XFF180068 0x000000FE 0x00000008
+		# Register : MIO_PIN_27 @ 0XFF18006C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_27_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+		# PSU_IOU_SLCR_MIO_PIN_27_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
+		# n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		# t, dp_aux_data_out- (Dp Aux Data)
+		# PSU_IOU_SLCR_MIO_PIN_27_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
+		# , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		# ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		# ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		# atabus)
+		# PSU_IOU_SLCR_MIO_PIN_27_L3_SEL                                                  0
+
+		# Configures MIO Pin 27 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18006C, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF18006C 0x000000FE 0x00000000
+		# Register : MIO_PIN_28 @ 0XFF180070

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_28_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+		# PSU_IOU_SLCR_MIO_PIN_28_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
+		# n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		# PSU_IOU_SLCR_MIO_PIN_28_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
+		# , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		# ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		# - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_28_L3_SEL                                                  0
+
+		# Configures MIO Pin 28 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180070, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF180070 0x000000FE 0x00000000
+		# Register : MIO_PIN_29 @ 0XFF180074

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_29_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		# PSU_IOU_SLCR_MIO_PIN_29_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
+		# n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		# t, dp_aux_data_out- (Dp Aux Data)
+		# PSU_IOU_SLCR_MIO_PIN_29_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
+		# , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		#  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
+		#  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		# ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_29_L3_SEL                                                  0
+
+		# Configures MIO Pin 29 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180074, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF180074 0x000000FE 0x00000000
+		# Register : MIO_PIN_30 @ 0XFF180078

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_30_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		# PSU_IOU_SLCR_MIO_PIN_30_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
+		# n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		# PSU_IOU_SLCR_MIO_PIN_30_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
+		# , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		#  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
+		#  (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
+		#  tracedq[8]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_30_L3_SEL                                                  0
+
+		# Configures MIO Pin 30 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180078, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF180078 0x000000FE 0x00000000
+		# Register : MIO_PIN_31 @ 0XFF18007C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
+		# PSU_IOU_SLCR_MIO_PIN_31_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		# PSU_IOU_SLCR_MIO_PIN_31_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
+		# n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		# PSU_IOU_SLCR_MIO_PIN_31_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
+		# , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		# ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
+		# _si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
+		# ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_31_L3_SEL                                                  0
+
+		# Configures MIO Pin 31 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18007C, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF18007C 0x000000FE 0x00000000
+		# Register : MIO_PIN_32 @ 0XFF180080

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
+		# PSU_IOU_SLCR_MIO_PIN_32_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		# 
+		# PSU_IOU_SLCR_MIO_PIN_32_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
+		# an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		# PSU_IOU_SLCR_MIO_PIN_32_L2_SEL                                                  1
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
+		# , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		# ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
+		# _sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= 
+		# race, Output, tracedq[10]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_32_L3_SEL                                                  0
+
+		# Configures MIO Pin 32 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180080, 0x000000FEU ,0x00000008U)  */
+    mask_write 0XFF180080 0x000000FE 0x00000008
+		# Register : MIO_PIN_33 @ 0XFF180084

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_33_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		# PSU_IOU_SLCR_MIO_PIN_33_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
+		# an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		# PSU_IOU_SLCR_MIO_PIN_33_L2_SEL                                                  1
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
+		# , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		#  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
+		# c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
+		# [11]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_33_L3_SEL                                                  0
+
+		# Configures MIO Pin 33 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180084, 0x000000FEU ,0x00000008U)  */
+    mask_write 0XFF180084 0x000000FE 0x00000008
+		# Register : MIO_PIN_34 @ 0XFF180088

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_34_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		# PSU_IOU_SLCR_MIO_PIN_34_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
+		# an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
+		# ut, dp_aux_data_out- (Dp Aux Data)
+		# PSU_IOU_SLCR_MIO_PIN_34_L2_SEL                                                  1
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
+		# , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		#  3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
+		#  Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
+		# rt Databus)
+		# PSU_IOU_SLCR_MIO_PIN_34_L3_SEL                                                  0
+
+		# Configures MIO Pin 34 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180088, 0x000000FEU ,0x00000008U)  */
+    mask_write 0XFF180088 0x000000FE 0x00000008
+		# Register : MIO_PIN_35 @ 0XFF18008C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_35_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		# PSU_IOU_SLCR_MIO_PIN_35_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
+		# an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		# PSU_IOU_SLCR_MIO_PIN_35_L2_SEL                                                  1
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
+		# , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		# ) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
+		# Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- 
+		# UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_35_L3_SEL                                                  0
+
+		# Configures MIO Pin 35 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18008C, 0x000000FEU ,0x00000008U)  */
+    mask_write 0XFF18008C 0x000000FE 0x00000008
+		# Register : MIO_PIN_36 @ 0XFF180090

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_36_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		# PSU_IOU_SLCR_MIO_PIN_36_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
+		# an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
+		# ut, dp_aux_data_out- (Dp Aux Data)
+		# PSU_IOU_SLCR_MIO_PIN_36_L2_SEL                                                  1
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		# so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		#  Output, tracedq[14]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_36_L3_SEL                                                  0
+
+		# Configures MIO Pin 36 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180090, 0x000000FEU ,0x00000008U)  */
+    mask_write 0XFF180090 0x000000FE 0x00000008
+		# Register : MIO_PIN_37 @ 0XFF180094

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
+		# PSU_IOU_SLCR_MIO_PIN_37_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		# PSU_IOU_SLCR_MIO_PIN_37_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
+		# an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		# PSU_IOU_SLCR_MIO_PIN_37_L2_SEL                                                  1
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		# 1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		# 7= trace, Output, tracedq[15]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_37_L3_SEL                                                  0
+
+		# Configures MIO Pin 37 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180094, 0x000000FEU ,0x00000008U)  */
+    mask_write 0XFF180094 0x000000FE 0x00000008
+		# Register : MIO_PIN_38 @ 0XFF180098

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
+		# PSU_IOU_SLCR_MIO_PIN_38_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_38_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_38_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
+		# k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
+		# (Trace Port Clock)
+		# PSU_IOU_SLCR_MIO_PIN_38_L3_SEL                                                  0
+
+		# Configures MIO Pin 38 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180098, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF180098 0x000000FE 0x00000000
+		# Register : MIO_PIN_39 @ 0XFF18009C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_39_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_39_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
+		# [4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_39_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
+		# _out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
+		# Control Signal)
+		# PSU_IOU_SLCR_MIO_PIN_39_L3_SEL                                                  0
+
+		# Configures MIO Pin 39 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18009C, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF18009C 0x000000FE 0x00000000
+		# Register : MIO_PIN_40 @ 0XFF1800A0

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_40_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_40_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		#  Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_40_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
+		# in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_40_L3_SEL                                                  0
+
+		# Configures MIO Pin 40 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800A0, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF1800A0 0x000000FE 0x00000000
+		# Register : MIO_PIN_41 @ 0XFF1800A4

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_41_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_41_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		# bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_41_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
+		# ]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
+		# ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_41_L3_SEL                                                  0
+
+		# Configures MIO Pin 41 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800A4, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF1800A4 0x000000FE 0x00000000
+		# Register : MIO_PIN_42 @ 0XFF1800A8

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_42_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_42_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		# bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_42_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
+		# o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		# t, tracedq[2]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_42_L3_SEL                                                  0
+
+		# Configures MIO Pin 42 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800A8, 0x000000FEU ,0x00000000U)  */
+    mask_write 0XFF1800A8 0x000000FE 0x00000000
+		# Register : MIO_PIN_43 @ 0XFF1800AC

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
+		# PSU_IOU_SLCR_MIO_PIN_43_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_43_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		# bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_43_L2_SEL                                                  2
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
+		# i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		# tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_43_L3_SEL                                                  0
+
+		# Configures MIO Pin 43 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800AC, 0x000000FEU ,0x00000010U)  */
+    mask_write 0XFF1800AC 0x000000FE 0x00000010
+		# Register : MIO_PIN_44 @ 0XFF1800B0

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
+		# PSU_IOU_SLCR_MIO_PIN_44_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_44_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		# bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_44_L2_SEL                                                  2
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
+		# i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		#  Not Used
+		# PSU_IOU_SLCR_MIO_PIN_44_L3_SEL                                                  0
+
+		# Configures MIO Pin 44 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800B0, 0x000000FEU ,0x00000010U)  */
+    mask_write 0XFF1800B0 0x000000FE 0x00000010
+		# Register : MIO_PIN_45 @ 0XFF1800B4

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_45_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_45_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		# bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_45_L2_SEL                                                  2
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
+		# ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_45_L3_SEL                                                  0
+
+		# Configures MIO Pin 45 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800B4, 0x000000FEU ,0x00000010U)  */
+    mask_write 0XFF1800B4 0x000000FE 0x00000010
+		# Register : MIO_PIN_46 @ 0XFF1800B8

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_46_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_46_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		# bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_46_L2_SEL                                                  2
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
+		# 0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_46_L3_SEL                                                  0
+
+		# Configures MIO Pin 46 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800B8, 0x000000FEU ,0x00000010U)  */
+    mask_write 0XFF1800B8 0x000000FE 0x00000010
+		# Register : MIO_PIN_47 @ 0XFF1800BC

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_47_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_47_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		# bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_47_L2_SEL                                                  2
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
+		# , Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		#  (UART transmitter serial output) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_47_L3_SEL                                                  0
+
+		# Configures MIO Pin 47 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800BC, 0x000000FEU ,0x00000010U)  */
+    mask_write 0XFF1800BC 0x000000FE 0x00000010
+		# Register : MIO_PIN_48 @ 0XFF1800C0

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_48_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_48_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		# bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_48_L2_SEL                                                  2
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		# so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
+		# ed
+		# PSU_IOU_SLCR_MIO_PIN_48_L3_SEL                                                  0
+
+		# Configures MIO Pin 48 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800C0, 0x000000FEU ,0x00000010U)  */
+    mask_write 0XFF1800C0 0x000000FE 0x00000010
+		# Register : MIO_PIN_49 @ 0XFF1800C4

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
+		# PSU_IOU_SLCR_MIO_PIN_49_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_49_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
+		# bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_49_L2_SEL                                                  2
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		# 1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		# 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_49_L3_SEL                                                  0
+
+		# Configures MIO Pin 49 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800C4, 0x000000FEU ,0x00000010U)  */
+    mask_write 0XFF1800C4 0x000000FE 0x00000010
+		# Register : MIO_PIN_50 @ 0XFF1800C8

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+		# PSU_IOU_SLCR_MIO_PIN_50_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_50_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
+		# d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_50_L2_SEL                                                  2
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
+		# clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_50_L3_SEL                                                  0
+
+		# Configures MIO Pin 50 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800C8, 0x000000FEU ,0x00000010U)  */
+    mask_write 0XFF1800C8 0x000000FE 0x00000010
+		# Register : MIO_PIN_51 @ 0XFF1800CC

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+		# PSU_IOU_SLCR_MIO_PIN_51_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_51_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_51_L2_SEL                                                  2
+
+		# Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
+		# t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
+		# serial output) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_51_L3_SEL                                                  0
+
+		# Configures MIO Pin 51 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800CC, 0x000000FEU ,0x00000010U)  */
+    mask_write 0XFF1800CC 0x000000FE 0x00000010
+		# Register : MIO_PIN_52 @ 0XFF1800D0

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)
+		# PSU_IOU_SLCR_MIO_PIN_52_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)
+		# PSU_IOU_SLCR_MIO_PIN_52_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_52_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
+		# , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		# ) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		# ) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		# lk- (Trace Port Clock)
+		# PSU_IOU_SLCR_MIO_PIN_52_L3_SEL                                                  0
+
+		# Configures MIO Pin 52 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800D0, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800D0 0x000000FE 0x00000004
+		# Register : MIO_PIN_53 @ 0XFF1800D4

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_53_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
+		# PSU_IOU_SLCR_MIO_PIN_53_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_53_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
+		# , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		#  3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
+		# t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		# Signal)
+		# PSU_IOU_SLCR_MIO_PIN_53_L3_SEL                                                  0
+
+		# Configures MIO Pin 53 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800D4, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800D4 0x000000FE 0x00000004
+		# Register : MIO_PIN_54 @ 0XFF1800D8

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_54_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		# ata[2]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_54_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_54_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
+		# , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		#  3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
+		#  (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_54_L3_SEL                                                  0
+
+		# Configures MIO Pin 54 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800D8, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800D8 0x000000FE 0x00000004
+		# Register : MIO_PIN_55 @ 0XFF1800DC

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_55_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
+		# PSU_IOU_SLCR_MIO_PIN_55_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_55_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
+		# , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		# ) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		# - (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		# output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_55_L3_SEL                                                  0
+
+		# Configures MIO Pin 55 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800DC, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800DC 0x000000FE 0x00000004
+		# Register : MIO_PIN_56 @ 0XFF1800E0

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_56_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		# ata[0]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_56_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_56_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
+		# , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		# ) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		# - (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		# utput, tracedq[2]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_56_L3_SEL                                                  0
+
+		# Configures MIO Pin 56 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800E0, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800E0 0x000000FE 0x00000004
+		# Register : MIO_PIN_57 @ 0XFF1800E4

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)
+		# PSU_IOU_SLCR_MIO_PIN_57_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		# ata[1]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_57_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_57_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
+		# , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		#  3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		# si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		#  trace, Output, tracedq[3]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_57_L3_SEL                                                  0
+
+		# Configures MIO Pin 57 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800E4, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800E4 0x000000FE 0x00000004
+		# Register : MIO_PIN_58 @ 0XFF1800E8

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)
+		# PSU_IOU_SLCR_MIO_PIN_58_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
+		# PSU_IOU_SLCR_MIO_PIN_58_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_58_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
+		# , Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		#  3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
+		#  5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		# Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_58_L3_SEL                                                  0
+
+		# Configures MIO Pin 58 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800E8, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800E8 0x000000FE 0x00000004
+		# Register : MIO_PIN_59 @ 0XFF1800EC

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_59_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		# ata[3]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_59_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_59_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
+		# , Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		# ) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		# ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		# atabus)
+		# PSU_IOU_SLCR_MIO_PIN_59_L3_SEL                                                  0
+
+		# Configures MIO Pin 59 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800EC, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800EC 0x000000FE 0x00000004
+		# Register : MIO_PIN_60 @ 0XFF1800F0

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_60_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		# ata[4]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_60_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_60_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
+		# , Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		# ) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		# - (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_60_L3_SEL                                                  0
+
+		# Configures MIO Pin 60 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800F0, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800F0 0x000000FE 0x00000004
+		# Register : MIO_PIN_61 @ 0XFF1800F4

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_61_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		# ata[5]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_61_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_61_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
+		# , Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		#  3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
+		#  (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		# ) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_61_L3_SEL                                                  0
+
+		# Configures MIO Pin 61 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800F4, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800F4 0x000000FE 0x00000004
+		# Register : MIO_PIN_62 @ 0XFF1800F8

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_62_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		# ata[6]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_62_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_62_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		# o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		# t, tracedq[8]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_62_L3_SEL                                                  0
+
+		# Configures MIO Pin 62 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800F8, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800F8 0x000000FE 0x00000004
+		# Register : MIO_PIN_63 @ 0XFF1800FC

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )
+		# PSU_IOU_SLCR_MIO_PIN_63_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		# ata[7]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_63_L1_SEL                                                  1
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_63_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		# i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		# tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_63_L3_SEL                                                  0
+
+		# Configures MIO Pin 63 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF1800FC, 0x000000FEU ,0x00000004U)  */
+    mask_write 0XFF1800FC 0x000000FE 0x00000004
+		# Register : MIO_PIN_64 @ 0XFF180100

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)
+		# PSU_IOU_SLCR_MIO_PIN_64_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)
+		# PSU_IOU_SLCR_MIO_PIN_64_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_64_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
+		# i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		#  trace, Output, tracedq[10]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_64_L3_SEL                                                  0
+
+		# Configures MIO Pin 64 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180100, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180100 0x000000FE 0x00000002
+		# Register : MIO_PIN_65 @ 0XFF180104

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_65_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
+		# PSU_IOU_SLCR_MIO_PIN_65_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_65_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
+		# ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
+		# dq[11]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_65_L3_SEL                                                  0
+
+		# Configures MIO Pin 65 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180104, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180104 0x000000FE 0x00000002
+		# Register : MIO_PIN_66 @ 0XFF180108

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_66_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		# ata[2]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_66_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		#  Indicator) 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_66_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
+		# 2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
+		# Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_66_L3_SEL                                                  0
+
+		# Configures MIO Pin 66 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180108, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180108 0x000000FE 0x00000002
+		# Register : MIO_PIN_67 @ 0XFF18010C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_67_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
+		# PSU_IOU_SLCR_MIO_PIN_67_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		# bit Data bus) 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_67_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
+		# , Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		#  (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_67_L3_SEL                                                  0
+
+		# Configures MIO Pin 67 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18010C, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF18010C 0x000000FE 0x00000002
+		# Register : MIO_PIN_68 @ 0XFF180110

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_68_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		# ata[0]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_68_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		# bit Data bus) 2= Not Used 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_68_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		# so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		#  Output, tracedq[14]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_68_L3_SEL                                                  0
+
+		# Configures MIO Pin 68 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180110, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180110 0x000000FE 0x00000002
+		# Register : MIO_PIN_69 @ 0XFF180114

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)
+		# PSU_IOU_SLCR_MIO_PIN_69_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		# ata[1]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_69_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		# bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_69_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		# 0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		# 7= trace, Output, tracedq[15]- (Trace Port Databus)
+		# PSU_IOU_SLCR_MIO_PIN_69_L3_SEL                                                  0
+
+		# Configures MIO Pin 69 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180114, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180114 0x000000FE 0x00000002
+		# Register : MIO_PIN_70 @ 0XFF180118

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)
+		# PSU_IOU_SLCR_MIO_PIN_70_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
+		# PSU_IOU_SLCR_MIO_PIN_70_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		# bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_70_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		# 1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		# sed
+		# PSU_IOU_SLCR_MIO_PIN_70_L3_SEL                                                  0
+
+		# Configures MIO Pin 70 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180118, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180118 0x000000FE 0x00000002
+		# Register : MIO_PIN_71 @ 0XFF18011C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_71_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		# ata[3]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_71_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		# bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_71_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		#  ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_71_L3_SEL                                                  0
+
+		# Configures MIO Pin 71 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18011C, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF18011C 0x000000FE 0x00000002
+		# Register : MIO_PIN_72 @ 0XFF180120

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_72_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		# ata[4]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_72_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		# bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_72_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
+		# t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_72_L3_SEL                                                  0
+
+		# Configures MIO Pin 72 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180120, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180120 0x000000FE 0x00000002
+		# Register : MIO_PIN_73 @ 0XFF180124

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_73_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		# ata[5]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_73_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		# bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_73_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		#  Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_73_L3_SEL                                                  0
+
+		# Configures MIO Pin 73 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180124, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180124 0x000000FE 0x00000002
+		# Register : MIO_PIN_74 @ 0XFF180128

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)
+		# PSU_IOU_SLCR_MIO_PIN_74_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		# ata[6]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_74_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		# bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_74_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
+		# n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		# l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		# o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_74_L3_SEL                                                  0
+
+		# Configures MIO Pin 74 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180128, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF180128 0x000000FE 0x00000002
+		# Register : MIO_PIN_75 @ 0XFF18012C

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )
+		# PSU_IOU_SLCR_MIO_PIN_75_L0_SEL                                                  1
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		# ata[7]- (ULPI data bus)
+		# PSU_IOU_SLCR_MIO_PIN_75_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
+		# d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_75_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
+		# n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		# al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		# i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_75_L3_SEL                                                  0
+
+		# Configures MIO Pin 75 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF18012C, 0x000000FEU ,0x00000002U)  */
+    mask_write 0XFF18012C 0x000000FE 0x00000002
+		# Register : MIO_PIN_76 @ 0XFF180130

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_76_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_76_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
+		# _clk_out- (SDSDIO clock) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_76_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
+		# n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		# al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
+		#  6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_76_L3_SEL                                                  6
+
+		# Configures MIO Pin 76 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180130, 0x000000FEU ,0x000000C0U)  */
+    mask_write 0XFF180130 0x000000FE 0x000000C0
+		# Register : MIO_PIN_77 @ 0XFF180134

+
+		# Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_77_L0_SEL                                                  0
+
+		# Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_77_L1_SEL                                                  0
+
+		# Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_77_L2_SEL                                                  0
+
+		# Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
+		# n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		# l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
+		# O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
+		# t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used
+		# PSU_IOU_SLCR_MIO_PIN_77_L3_SEL                                                  6
+
+		# Configures MIO Pin 77 peripheral interface mapping
+		#(OFFSET, MASK, VALUE)      (0XFF180134, 0x000000FEU ,0x000000C0U)  */
+    mask_write 0XFF180134 0x000000FE 0x000000C0
+		# Register : MIO_MST_TRI0 @ 0XFF180204

+
+		# Master Tri-state Enable for pin 0, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI                                            0
+
+		# Master Tri-state Enable for pin 1, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI                                            0
+
+		# Master Tri-state Enable for pin 2, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI                                            0
+
+		# Master Tri-state Enable for pin 3, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI                                            0
+
+		# Master Tri-state Enable for pin 4, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI                                            0
+
+		# Master Tri-state Enable for pin 5, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI                                            0
+
+		# Master Tri-state Enable for pin 6, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI                                            0
+
+		# Master Tri-state Enable for pin 7, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI                                            0
+
+		# Master Tri-state Enable for pin 8, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI                                            0
+
+		# Master Tri-state Enable for pin 9, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI                                            0
+
+		# Master Tri-state Enable for pin 10, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI                                            0
+
+		# Master Tri-state Enable for pin 11, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI                                            0
+
+		# Master Tri-state Enable for pin 12, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI                                            0
+
+		# Master Tri-state Enable for pin 13, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI                                            0
+
+		# Master Tri-state Enable for pin 14, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI                                            0
+
+		# Master Tri-state Enable for pin 15, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI                                            0
+
+		# Master Tri-state Enable for pin 16, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI                                            0
+
+		# Master Tri-state Enable for pin 17, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI                                            0
+
+		# Master Tri-state Enable for pin 18, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI                                            1
+
+		# Master Tri-state Enable for pin 19, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI                                            0
+
+		# Master Tri-state Enable for pin 20, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI                                            0
+
+		# Master Tri-state Enable for pin 21, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI                                            1
+
+		# Master Tri-state Enable for pin 22, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI                                            0
+
+		# Master Tri-state Enable for pin 23, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI                                            0
+
+		# Master Tri-state Enable for pin 24, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI                                            0
+
+		# Master Tri-state Enable for pin 25, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI                                            1
+
+		# Master Tri-state Enable for pin 26, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI                                            1
+
+		# Master Tri-state Enable for pin 27, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI                                            0
+
+		# Master Tri-state Enable for pin 28, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI                                            0
+
+		# Master Tri-state Enable for pin 29, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI                                            0
+
+		# Master Tri-state Enable for pin 30, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI                                            0
+
+		# Master Tri-state Enable for pin 31, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI                                            0
+
+		# MIO pin Tri-state Enables, 31:0
+		#(OFFSET, MASK, VALUE)      (0XFF180204, 0xFFFFFFFFU ,0x06240000U)  */
+    mask_write 0XFF180204 0xFFFFFFFF 0x06240000
+		# Register : MIO_MST_TRI1 @ 0XFF180208

+
+		# Master Tri-state Enable for pin 32, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI                                            0
+
+		# Master Tri-state Enable for pin 33, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI                                            0
+
+		# Master Tri-state Enable for pin 34, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI                                            0
+
+		# Master Tri-state Enable for pin 35, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI                                            0
+
+		# Master Tri-state Enable for pin 36, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI                                            0
+
+		# Master Tri-state Enable for pin 37, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI                                            0
+
+		# Master Tri-state Enable for pin 38, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI                                            0
+
+		# Master Tri-state Enable for pin 39, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI                                            0
+
+		# Master Tri-state Enable for pin 40, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI                                            0
+
+		# Master Tri-state Enable for pin 41, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI                                            0
+
+		# Master Tri-state Enable for pin 42, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI                                            0
+
+		# Master Tri-state Enable for pin 43, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI                                            0
+
+		# Master Tri-state Enable for pin 44, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI                                            1
+
+		# Master Tri-state Enable for pin 45, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI                                            1
+
+		# Master Tri-state Enable for pin 46, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI                                            0
+
+		# Master Tri-state Enable for pin 47, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI                                            0
+
+		# Master Tri-state Enable for pin 48, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI                                            0
+
+		# Master Tri-state Enable for pin 49, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI                                            0
+
+		# Master Tri-state Enable for pin 50, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI                                            0
+
+		# Master Tri-state Enable for pin 51, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI                                            0
+
+		# Master Tri-state Enable for pin 52, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI                                            1
+
+		# Master Tri-state Enable for pin 53, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI                                            1
+
+		# Master Tri-state Enable for pin 54, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI                                            0
+
+		# Master Tri-state Enable for pin 55, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI                                            1
+
+		# Master Tri-state Enable for pin 56, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI                                            0
+
+		# Master Tri-state Enable for pin 57, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI                                            0
+
+		# Master Tri-state Enable for pin 58, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI                                            0
+
+		# Master Tri-state Enable for pin 59, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI                                            0
+
+		# Master Tri-state Enable for pin 60, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI                                            0
+
+		# Master Tri-state Enable for pin 61, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI                                            0
+
+		# Master Tri-state Enable for pin 62, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI                                            0
+
+		# Master Tri-state Enable for pin 63, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI                                            0
+
+		# MIO pin Tri-state Enables, 63:32
+		#(OFFSET, MASK, VALUE)      (0XFF180208, 0xFFFFFFFFU ,0x00B03000U)  */
+    mask_write 0XFF180208 0xFFFFFFFF 0x00B03000
+		# Register : MIO_MST_TRI2 @ 0XFF18020C

+
+		# Master Tri-state Enable for pin 64, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI                                            0
+
+		# Master Tri-state Enable for pin 65, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI                                            0
+
+		# Master Tri-state Enable for pin 66, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI                                            0
+
+		# Master Tri-state Enable for pin 67, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI                                            0
+
+		# Master Tri-state Enable for pin 68, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI                                            0
+
+		# Master Tri-state Enable for pin 69, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI                                            0
+
+		# Master Tri-state Enable for pin 70, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI                                            1
+
+		# Master Tri-state Enable for pin 71, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI                                            1
+
+		# Master Tri-state Enable for pin 72, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI                                            1
+
+		# Master Tri-state Enable for pin 73, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI                                            1
+
+		# Master Tri-state Enable for pin 74, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI                                            1
+
+		# Master Tri-state Enable for pin 75, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI                                            1
+
+		# Master Tri-state Enable for pin 76, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI                                            0
+
+		# Master Tri-state Enable for pin 77, active high
+		# PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI                                            0
+
+		# MIO pin Tri-state Enables, 77:64
+		#(OFFSET, MASK, VALUE)      (0XFF18020C, 0x00003FFFU ,0x00000FC0U)  */
+    mask_write 0XFF18020C 0x00003FFF 0x00000FC0
+		# Register : bank0_ctrl0 @ 0XFF180138

+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25                                          1
+
+		# Drive0 control to MIO Bank 0 - control MIO[25:0]
+		#(OFFSET, MASK, VALUE)      (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF180138 0x03FFFFFF 0x03FFFFFF
+		# Register : bank0_ctrl1 @ 0XFF18013C

+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25                                          1
+
+		# Drive1 control to MIO Bank 0 - control MIO[25:0]
+		#(OFFSET, MASK, VALUE)      (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF18013C 0x03FFFFFF 0x03FFFFFF
+		# Register : bank0_ctrl3 @ 0XFF180140

+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
+
+		# Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0]
+		#(OFFSET, MASK, VALUE)      (0XFF180140, 0x03FFFFFFU ,0x00000000U)  */
+    mask_write 0XFF180140 0x03FFFFFF 0x00000000
+		# Register : bank0_ctrl4 @ 0XFF180144

+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
+
+		# When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
+		#(OFFSET, MASK, VALUE)      (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF180144 0x03FFFFFF 0x03FFFFFF
+		# Register : bank0_ctrl5 @ 0XFF180148

+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25                                     1
+
+		# When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
+		#(OFFSET, MASK, VALUE)      (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF180148 0x03FFFFFF 0x03FFFFFF
+		# Register : bank0_ctrl6 @ 0XFF18014C

+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[0].
+		# PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
+
+		# Slew rate control to MIO Bank 0 - control MIO[25:0]
+		#(OFFSET, MASK, VALUE)      (0XFF18014C, 0x03FFFFFFU ,0x00000000U)  */
+    mask_write 0XFF18014C 0x03FFFFFF 0x00000000
+		# Register : bank1_ctrl0 @ 0XFF180154

+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25                                          1
+
+		# Drive0 control to MIO Bank 1 - control MIO[51:26]
+		#(OFFSET, MASK, VALUE)      (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF180154 0x03FFFFFF 0x03FFFFFF
+		# Register : bank1_ctrl1 @ 0XFF180158

+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25                                          1
+
+		# Drive1 control to MIO Bank 1 - control MIO[51:26]
+		#(OFFSET, MASK, VALUE)      (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF180158 0x03FFFFFF 0x03FFFFFF
+		# Register : bank1_ctrl3 @ 0XFF18015C

+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
+
+		# Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26]
+		#(OFFSET, MASK, VALUE)      (0XFF18015C, 0x03FFFFFFU ,0x00000000U)  */
+    mask_write 0XFF18015C 0x03FFFFFF 0x00000000
+		# Register : bank1_ctrl4 @ 0XFF180160

+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
+
+		# When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
+		#(OFFSET, MASK, VALUE)      (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF180160 0x03FFFFFF 0x03FFFFFF
+		# Register : bank1_ctrl5 @ 0XFF180164

+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25                                     1
+
+		# When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
+		#(OFFSET, MASK, VALUE)      (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF180164 0x03FFFFFF 0x03FFFFFF
+		# Register : bank1_ctrl6 @ 0XFF180168

+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[26].
+		# PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
+
+		# Slew rate control to MIO Bank 1 - control MIO[51:26]
+		#(OFFSET, MASK, VALUE)      (0XFF180168, 0x03FFFFFFU ,0x00000000U)  */
+    mask_write 0XFF180168 0x03FFFFFF 0x00000000
+		# Register : bank2_ctrl0 @ 0XFF180170

+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25                                          1
+
+		# Drive0 control to MIO Bank 2 - control MIO[77:52]
+		#(OFFSET, MASK, VALUE)      (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF180170 0x03FFFFFF 0x03FFFFFF
+		# Register : bank2_ctrl1 @ 0XFF180174

+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9                                           1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24                                          1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25                                          1
+
+		# Drive1 control to MIO Bank 2 - control MIO[77:52]
+		#(OFFSET, MASK, VALUE)      (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF180174 0x03FFFFFF 0x03FFFFFF
+		# Register : bank2_ctrl3 @ 0XFF180178

+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
+
+		# Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52]
+		#(OFFSET, MASK, VALUE)      (0XFF180178, 0x03FFFFFFU ,0x00000000U)  */
+    mask_write 0XFF180178 0x03FFFFFF 0x00000000
+		# Register : bank2_ctrl4 @ 0XFF18017C

+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
+
+		# When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
+		#(OFFSET, MASK, VALUE)      (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF18017C 0x03FFFFFF 0x03FFFFFF
+		# Register : bank2_ctrl5 @ 0XFF180180

+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9                                      1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24                                     1
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25                                     1
+
+		# When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
+		#(OFFSET, MASK, VALUE)      (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU)  */
+    mask_write 0XFF180180 0x03FFFFFF 0x03FFFFFF
+		# Register : bank2_ctrl6 @ 0XFF180184

+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
+
+		# Each bit applies to a single IO. Bit 0 for MIO[52].
+		# PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
+
+		# Slew rate control to MIO Bank 2 - control MIO[77:52]
+		#(OFFSET, MASK, VALUE)      (0XFF180184, 0x03FFFFFFU ,0x00000000U)  */
+    mask_write 0XFF180184 0x03FFFFFF 0x00000000
+		# : LOOPBACK
+		# Register : MIO_LOOPBACK @ 0XFF180200

+
+		# I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
+		# ts to I2C 0 inputs.
+		# PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1                                        0
+
+		# CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
+		# .
+		# PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1                                        0
+
+		# UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
+		# outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.
+		# PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1                                          0
+
+		# SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
+		# ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.
+		# PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1                                        0
+
+		# Loopback function within MIO
+		#(OFFSET, MASK, VALUE)      (0XFF180200, 0x0000000FU ,0x00000000U)  */
+    mask_write 0XFF180200 0x0000000F 0x00000000
+}
+
+set psu_peripherals_init_data {
+		# : RESET BLOCKS
+		# : ENET
+		# Register : RST_LPD_IOU0 @ 0XFF5E0230

+
+		# GEM 3 reset
+		# PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0
+
+		# Software controlled reset for the GEMs
+		#(OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)  */
+    mask_write 0XFF5E0230 0x00000008 0x00000000
+		# : QSPI
+		# Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET                                             0
+
+		# Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		#(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000001U ,0x00000000U)  */
+    mask_write 0XFF5E0238 0x00000001 0x00000000
+		# : NAND
+		# : USB
+		# Register : RST_LPD_TOP @ 0XFF5E023C

+
+		# USB 0 reset for control registers
+		# PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0
+
+		# USB 0 sleep circuit reset
+		# PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0
+
+		# USB 0 reset
+		# PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0
+
+		# Software control register for the LPD block.
+		#(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000000U)  */
+    mask_write 0XFF5E023C 0x00000540 0x00000000
+		# : FPD RESET
+		# Register : RST_FPD_TOP @ 0XFD1A0100

+
+		# PCIE config reset
+		# PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0
+
+		# PCIE control block level reset
+		# PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0
+
+		# PCIE bridge block level reset (AXI interface)
+		# PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0
+
+		# Display Port block level reset (includes DPDMA)
+		# PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0
+
+		# FPD WDT reset
+		# PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET                                              0
+
+		# GDMA block level reset
+		# PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET                                              0
+
+		# Pixel Processor (submodule of GPU) block level reset
+		# PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET                                           0
+
+		# Pixel Processor (submodule of GPU) block level reset
+		# PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET                                           0
+
+		# GPU block level reset
+		# PSU_CRF_APB_RST_FPD_TOP_GPU_RESET                                               0
+
+		# GT block level reset
+		# PSU_CRF_APB_RST_FPD_TOP_GT_RESET                                                0
+
+		# Sata block level reset
+		# PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0
+
+		# FPD Block level software controlled reset
+		#(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000F807EU ,0x00000000U)  */
+    mask_write 0XFD1A0100 0x000F807E 0x00000000
+		# : SD
+		# Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET                                            0
+
+		# Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		#(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000040U ,0x00000000U)  */
+    mask_write 0XFF5E0238 0x00000040 0x00000000
+		# Register : CTRL_REG_SD @ 0XFF180310

+
+		# SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
+		# PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL                                           0
+
+		# SD eMMC selection
+		#(OFFSET, MASK, VALUE)      (0XFF180310, 0x00008000U ,0x00000000U)  */
+    mask_write 0XFF180310 0x00008000 0x00000000
+		# Register : SD_CONFIG_REG2 @ 0XFF180320

+
+		# Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		# t 11 - Reserved
+		# PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE                                        0
+
+		# 1.8V Support 1: 1.8V supported 0: 1.8V not supported support
+		# PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V                                            0
+
+		# 3.0V Support 1: 3.0V supported 0: 3.0V not supported support
+		# PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V                                            0
+
+		# 3.3V Support 1: 3.3V supported 0: 3.3V not supported support
+		# PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V                                            1
+
+		# SD Config Register 2
+		#(OFFSET, MASK, VALUE)      (0XFF180320, 0x33800000U ,0x00800000U)  */
+    mask_write 0XFF180320 0x33800000 0x00800000
+		# : SD1 BASE CLOCK
+		# Register : SD_CONFIG_REG1 @ 0XFF18031C

+
+		# Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
+		# PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK                                         0xc7
+
+		# SD Config Register 1
+		#(OFFSET, MASK, VALUE)      (0XFF18031C, 0x7F800000U ,0x63800000U)  */
+    mask_write 0XFF18031C 0x7F800000 0x63800000
+		# : CAN
+		# Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET                                             0
+
+		# Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		#(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000100U ,0x00000000U)  */
+    mask_write 0XFF5E0238 0x00000100 0x00000000
+		# : I2C
+		# Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET                                             0
+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET                                             0
+
+		# Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		#(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000600U ,0x00000000U)  */
+    mask_write 0XFF5E0238 0x00000600 0x00000000
+		# : SWDT
+		# Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET                                             0
+
+		# Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		#(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00008000U ,0x00000000U)  */
+    mask_write 0XFF5E0238 0x00008000 0x00000000
+		# : SPI
+		# : TTC
+		# Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET                                             0
+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET                                             0
+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET                                             0
+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET                                             0
+
+		# Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		#(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00007800U ,0x00000000U)  */
+    mask_write 0XFF5E0238 0x00007800 0x00000000
+		# : UART
+		# Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET                                            0
+
+		# Block level reset
+		# PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET                                            0
+
+		# Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		#(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000006U ,0x00000000U)  */
+    mask_write 0XFF5E0238 0x00000006 0x00000000
+		# : UART BAUD RATE
+		# Register : Baud_rate_divider_reg0 @ 0XFF000034

+
+		# Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+		# PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
+
+		# Baud Rate Divider Register
+		#(OFFSET, MASK, VALUE)      (0XFF000034, 0x000000FFU ,0x00000005U)  */
+    mask_write 0XFF000034 0x000000FF 0x00000005
+		# Register : Baud_rate_gen_reg0 @ 0XFF000018

+
+		# Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+		# PSU_UART0_BAUD_RATE_GEN_REG0_CD                                                 0x8f
+
+		# Baud Rate Generator Register.
+		#(OFFSET, MASK, VALUE)      (0XFF000018, 0x0000FFFFU ,0x0000008FU)  */
+    mask_write 0XFF000018 0x0000FFFF 0x0000008F
+		# Register : Control_reg0 @ 0XFF000000

+
+		# Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		# high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+		# PSU_UART0_CONTROL_REG0_STPBRK                                                   0x0
+
+		# Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		# transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+		# PSU_UART0_CONTROL_REG0_STTBRK                                                   0x0
+
+		# Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		# pleted.
+		# PSU_UART0_CONTROL_REG0_RSTTO                                                    0x0
+
+		# Transmit disable: 0: enable transmitter 1: disable transmitter
+		# PSU_UART0_CONTROL_REG0_TXDIS                                                    0x0
+
+		# Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+		# PSU_UART0_CONTROL_REG0_TXEN                                                     0x1
+
+		# Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+		# PSU_UART0_CONTROL_REG0_RXDIS                                                    0x0
+
+		# Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+		# PSU_UART0_CONTROL_REG0_RXEN                                                     0x1
+
+		# Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		#  bit is self clearing once the reset has completed.
+		# PSU_UART0_CONTROL_REG0_TXRES                                                    0x1
+
+		# Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		# is self clearing once the reset has completed.
+		# PSU_UART0_CONTROL_REG0_RXRES                                                    0x1
+
+		# UART Control Register
+		#(OFFSET, MASK, VALUE)      (0XFF000000, 0x000001FFU ,0x00000017U)  */
+    mask_write 0XFF000000 0x000001FF 0x00000017
+		# Register : mode_reg0 @ 0XFF000004

+
+		# Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+		# PSU_UART0_MODE_REG0_CHMODE                                                      0x0
+
+		# Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		# stop bits 10: 2 stop bits 11: reserved
+		# PSU_UART0_MODE_REG0_NBSTOP                                                      0x0
+
+		# Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		# 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+		# PSU_UART0_MODE_REG0_PAR                                                         0x4
+
+		# Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+		# PSU_UART0_MODE_REG0_CHRL                                                        0x0
+
+		# Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		# source is uart_ref_clk 1: clock source is uart_ref_clk/8
+		# PSU_UART0_MODE_REG0_CLKS                                                        0x0
+
+		# UART Mode Register
+		#(OFFSET, MASK, VALUE)      (0XFF000004, 0x000003FFU ,0x00000020U)  */
+    mask_write 0XFF000004 0x000003FF 0x00000020
+		# Register : Baud_rate_divider_reg0 @ 0XFF010034

+
+		# Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+		# PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
+
+		# Baud Rate Divider Register
+		#(OFFSET, MASK, VALUE)      (0XFF010034, 0x000000FFU ,0x00000005U)  */
+    mask_write 0XFF010034 0x000000FF 0x00000005
+		# Register : Baud_rate_gen_reg0 @ 0XFF010018

+
+		# Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+		# PSU_UART1_BAUD_RATE_GEN_REG0_CD                                                 0x8f
+
+		# Baud Rate Generator Register.
+		#(OFFSET, MASK, VALUE)      (0XFF010018, 0x0000FFFFU ,0x0000008FU)  */
+    mask_write 0XFF010018 0x0000FFFF 0x0000008F
+		# Register : Control_reg0 @ 0XFF010000

+
+		# Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		# high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+		# PSU_UART1_CONTROL_REG0_STPBRK                                                   0x0
+
+		# Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		# transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+		# PSU_UART1_CONTROL_REG0_STTBRK                                                   0x0
+
+		# Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		# pleted.
+		# PSU_UART1_CONTROL_REG0_RSTTO                                                    0x0
+
+		# Transmit disable: 0: enable transmitter 1: disable transmitter
+		# PSU_UART1_CONTROL_REG0_TXDIS                                                    0x0
+
+		# Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+		# PSU_UART1_CONTROL_REG0_TXEN                                                     0x1
+
+		# Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+		# PSU_UART1_CONTROL_REG0_RXDIS                                                    0x0
+
+		# Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+		# PSU_UART1_CONTROL_REG0_RXEN                                                     0x1
+
+		# Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		#  bit is self clearing once the reset has completed.
+		# PSU_UART1_CONTROL_REG0_TXRES                                                    0x1
+
+		# Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		# is self clearing once the reset has completed.
+		# PSU_UART1_CONTROL_REG0_RXRES                                                    0x1
+
+		# UART Control Register
+		#(OFFSET, MASK, VALUE)      (0XFF010000, 0x000001FFU ,0x00000017U)  */
+    mask_write 0XFF010000 0x000001FF 0x00000017
+		# Register : mode_reg0 @ 0XFF010004

+
+		# Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+		# PSU_UART1_MODE_REG0_CHMODE                                                      0x0
+
+		# Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		# stop bits 10: 2 stop bits 11: reserved
+		# PSU_UART1_MODE_REG0_NBSTOP                                                      0x0
+
+		# Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		# 01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+		# PSU_UART1_MODE_REG0_PAR                                                         0x4
+
+		# Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+		# PSU_UART1_MODE_REG0_CHRL                                                        0x0
+
+		# Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		# source is uart_ref_clk 1: clock source is uart_ref_clk/8
+		# PSU_UART1_MODE_REG0_CLKS                                                        0x0
+
+		# UART Mode Register
+		#(OFFSET, MASK, VALUE)      (0XFF010004, 0x000003FFU ,0x00000020U)  */
+    mask_write 0XFF010004 0x000003FF 0x00000020
+		# : GPIO
+		# : ADMA TZ
+		# Register : slcr_adma @ 0XFF4B0024

+
+		# TrustZone Classification for ADMA
+		# PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ                                                0XFF
+
+		# RPU TrustZone settings
+		#(OFFSET, MASK, VALUE)      (0XFF4B0024, 0x000000FFU ,0x000000FFU)  */
+    mask_write 0XFF4B0024 0x000000FF 0x000000FF
+		# : CSU TAMPERING
+		# : CSU TAMPER STATUS
+		# Register : tamper_status @ 0XFFCA5000

+
+		# CSU regsiter
+		# PSU_CSU_TAMPER_STATUS_TAMPER_0                                                  0
+
+		# External MIO
+		# PSU_CSU_TAMPER_STATUS_TAMPER_1                                                  0
+
+		# JTAG toggle detect
+		# PSU_CSU_TAMPER_STATUS_TAMPER_2                                                  0
+
+		# PL SEU error
+		# PSU_CSU_TAMPER_STATUS_TAMPER_3                                                  0
+
+		# AMS over temperature alarm for LPD
+		# PSU_CSU_TAMPER_STATUS_TAMPER_4                                                  0
+
+		# AMS over temperature alarm for APU
+		# PSU_CSU_TAMPER_STATUS_TAMPER_5                                                  0
+
+		# AMS voltage alarm for VCCPINT_FPD
+		# PSU_CSU_TAMPER_STATUS_TAMPER_6                                                  0
+
+		# AMS voltage alarm for VCCPINT_LPD
+		# PSU_CSU_TAMPER_STATUS_TAMPER_7                                                  0
+
+		# AMS voltage alarm for VCCPAUX
+		# PSU_CSU_TAMPER_STATUS_TAMPER_8                                                  0
+
+		# AMS voltage alarm for DDRPHY
+		# PSU_CSU_TAMPER_STATUS_TAMPER_9                                                  0
+
+		# AMS voltage alarm for PSIO bank 0/1/2
+		# PSU_CSU_TAMPER_STATUS_TAMPER_10                                                 0
+
+		# AMS voltage alarm for PSIO bank 3 (dedicated pins)
+		# PSU_CSU_TAMPER_STATUS_TAMPER_11                                                 0
+
+		# AMS voltaage alarm for GT
+		# PSU_CSU_TAMPER_STATUS_TAMPER_12                                                 0
+
+		# Tamper Response Status
+		#(OFFSET, MASK, VALUE)      (0XFFCA5000, 0x00001FFFU ,0x00000000U)  */
+    mask_write 0XFFCA5000 0x00001FFF 0x00000000
+		# : CSU TAMPER RESPONSE
+		# : AFIFM INTERFACE WIDTH
+		# : CPU QOS DEFAULT
+		# Register : ACE_CTRL @ 0XFD5C0060

+
+		# Set ACE outgoing AWQOS value
+		# PSU_APU_ACE_CTRL_AWQOS                                                          0X0
+
+		# Set ACE outgoing ARQOS value
+		# PSU_APU_ACE_CTRL_ARQOS                                                          0X0
+
+		# ACE Control Register
+		#(OFFSET, MASK, VALUE)      (0XFD5C0060, 0x000F000FU ,0x00000000U)  */
+    mask_write 0XFD5C0060 0x000F000F 0x00000000
+		# : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE
+		# Register : CONTROL @ 0XFFA60040

+
+		# Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from 
+		# he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
+		# pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
+		# g a 0 to this bit.
+		# PSU_RTC_CONTROL_BATTERY_DISABLE                                                 0X1
+
+		# This register controls various functionalities within the RTC
+		#(OFFSET, MASK, VALUE)      (0XFFA60040, 0x80000000U ,0x80000000U)  */
+    mask_write 0XFFA60040 0x80000000 0x80000000
+}
+
+set psu_post_config_data {
+		# : POST_CONFIG
+}
+
+set psu_peripherals_powerdwn_data {
+		# : POWER DOWN REQUEST INTERRUPT ENABLE
+		# : POWER DOWN TRIGGER
+}
+
+set psu_serdes_init_data {
+		# : SERDES INITIALIZATION
+		# : GT REFERENCE CLOCK SOURCE SELECTION
+		# Register : PLL_REF_SEL0 @ 0XFD410000

+
+		# PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		# 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		# Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		# PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0                                              0xD
+
+		# PLL0 Reference Selection Register
+		#(OFFSET, MASK, VALUE)      (0XFD410000, 0x0000001FU ,0x0000000DU)  */
+    mask_write 0XFD410000 0x0000001F 0x0000000D
+		# Register : PLL_REF_SEL1 @ 0XFD410004

+
+		# PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		# 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		# Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		# PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1                                              0x9
+
+		# PLL1 Reference Selection Register
+		#(OFFSET, MASK, VALUE)      (0XFD410004, 0x0000001FU ,0x00000009U)  */
+    mask_write 0XFD410004 0x0000001F 0x00000009
+		# Register : PLL_REF_SEL2 @ 0XFD410008

+
+		# PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		# 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		# Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		# PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2                                              0x8
+
+		# PLL2 Reference Selection Register
+		#(OFFSET, MASK, VALUE)      (0XFD410008, 0x0000001FU ,0x00000008U)  */
+    mask_write 0XFD410008 0x0000001F 0x00000008
+		# Register : PLL_REF_SEL3 @ 0XFD41000C

+
+		# PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		# 4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		# Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		# PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3                                              0xF
+
+		# PLL3 Reference Selection Register
+		#(OFFSET, MASK, VALUE)      (0XFD41000C, 0x0000001FU ,0x0000000FU)  */
+    mask_write 0XFD41000C 0x0000001F 0x0000000F
+		# : GT REFERENCE CLOCK FREQUENCY SELECTION
+		# Register : L0_L0_REF_CLK_SEL @ 0XFD402860

+
+		# Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.
+		# PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL                                 0x1
+
+		# Lane0 Ref Clock Selection Register
+		#(OFFSET, MASK, VALUE)      (0XFD402860, 0x00000080U ,0x00000080U)  */
+    mask_write 0XFD402860 0x00000080 0x00000080
+		# Register : L0_L1_REF_CLK_SEL @ 0XFD402864

+
+		# Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.
+		# PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL                                 0x0
+
+		# Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network
+		# PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3                                   0x1
+
+		# Lane1 Ref Clock Selection Register
+		#(OFFSET, MASK, VALUE)      (0XFD402864, 0x00000088U ,0x00000008U)  */
+    mask_write 0XFD402864 0x00000088 0x00000008
+		# Register : L0_L2_REF_CLK_SEL @ 0XFD402868

+
+		# Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.
+		# PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL                                 0x1
+
+		# Lane2 Ref Clock Selection Register
+		#(OFFSET, MASK, VALUE)      (0XFD402868, 0x00000080U ,0x00000080U)  */
+    mask_write 0XFD402868 0x00000080 0x00000080
+		# Register : L0_L3_REF_CLK_SEL @ 0XFD40286C

+
+		# Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.
+		# PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL                                 0x0
+
+		# Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network
+		# PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1                                   0x1
+
+		# Lane3 Ref Clock Selection Register
+		#(OFFSET, MASK, VALUE)      (0XFD40286C, 0x00000082U ,0x00000002U)  */
+    mask_write 0XFD40286C 0x00000082 0x00000002
+		# : ENABLE SPREAD SPECTRUM
+		# Register : L2_TM_PLL_DIG_37 @ 0XFD40A094

+
+		# Enable/Disable coarse code satureation limiting logic
+		# PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION                         0x1
+
+		# Test mode register 37
+		#(OFFSET, MASK, VALUE)      (0XFD40A094, 0x00000010U ,0x00000010U)  */
+    mask_write 0XFD40A094 0x00000010 0x00000010
+		# Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368

+
+		# Spread Spectrum No of Steps [7:0]
+		# PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x38
+
+		# Spread Spectrum No of Steps bits 7:0
+		#(OFFSET, MASK, VALUE)      (0XFD40A368, 0x000000FFU ,0x00000038U)  */
+    mask_write 0XFD40A368 0x000000FF 0x00000038
+		# Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C

+
+		# Spread Spectrum No of Steps [10:8]
+		# PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x03
+
+		# Spread Spectrum No of Steps bits 10:8
+		#(OFFSET, MASK, VALUE)      (0XFD40A36C, 0x00000007U ,0x00000003U)  */
+    mask_write 0XFD40A36C 0x00000007 0x00000003
+		# Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368

+
+		# Spread Spectrum No of Steps [7:0]
+		# PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x0
+
+		# Spread Spectrum No of Steps bits 7:0
+		#(OFFSET, MASK, VALUE)      (0XFD40E368, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFD40E368 0x000000FF 0x00000000
+		# Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C

+
+		# Spread Spectrum No of Steps [10:8]
+		# PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x0
+
+		# Spread Spectrum No of Steps bits 10:8
+		#(OFFSET, MASK, VALUE)      (0XFD40E36C, 0x00000007U ,0x00000000U)  */
+    mask_write 0XFD40E36C 0x00000007 0x00000000
+		# Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368

+
+		# Spread Spectrum No of Steps [7:0]
+		# PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x0
+
+		# Spread Spectrum No of Steps bits 7:0
+		#(OFFSET, MASK, VALUE)      (0XFD406368, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFD406368 0x000000FF 0x00000000
+		# Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C

+
+		# Spread Spectrum No of Steps [10:8]
+		# PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x0
+
+		# Spread Spectrum No of Steps bits 10:8
+		#(OFFSET, MASK, VALUE)      (0XFD40636C, 0x00000007U ,0x00000000U)  */
+    mask_write 0XFD40636C 0x00000007 0x00000000
+		# Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370

+
+		# Step Size for Spread Spectrum [7:0]
+		# PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0x0
+
+		# Step Size for Spread Spectrum LSB
+		#(OFFSET, MASK, VALUE)      (0XFD406370, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFD406370 0x000000FF 0x00000000
+		# Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374

+
+		# Step Size for Spread Spectrum [15:8]
+		# PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x0
+
+		# Step Size for Spread Spectrum 1
+		#(OFFSET, MASK, VALUE)      (0XFD406374, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFD406374 0x000000FF 0x00000000
+		# Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378

+
+		# Step Size for Spread Spectrum [23:16]
+		# PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x0
+
+		# Step Size for Spread Spectrum 2
+		#(OFFSET, MASK, VALUE)      (0XFD406378, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFD406378 0x000000FF 0x00000000
+		# Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C

+
+		# Step Size for Spread Spectrum [25:24]
+		# PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
+
+		# Enable/Disable test mode force on SS step size
+		# PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
+
+		# Enable/Disable test mode force on SS no of steps
+		# PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
+
+		# Enable force on enable Spread Spectrum
+		#(OFFSET, MASK, VALUE)      (0XFD40637C, 0x00000033U ,0x00000030U)  */
+    mask_write 0XFD40637C 0x00000033 0x00000030
+		# Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370

+
+		# Step Size for Spread Spectrum [7:0]
+		# PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0xF4
+
+		# Step Size for Spread Spectrum LSB
+		#(OFFSET, MASK, VALUE)      (0XFD40A370, 0x000000FFU ,0x000000F4U)  */
+    mask_write 0XFD40A370 0x000000FF 0x000000F4
+		# Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374

+
+		# Step Size for Spread Spectrum [15:8]
+		# PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x31
+
+		# Step Size for Spread Spectrum 1
+		#(OFFSET, MASK, VALUE)      (0XFD40A374, 0x000000FFU ,0x00000031U)  */
+    mask_write 0XFD40A374 0x000000FF 0x00000031
+		# Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378

+
+		# Step Size for Spread Spectrum [23:16]
+		# PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x2
+
+		# Step Size for Spread Spectrum 2
+		#(OFFSET, MASK, VALUE)      (0XFD40A378, 0x000000FFU ,0x00000002U)  */
+    mask_write 0XFD40A378 0x000000FF 0x00000002
+		# Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C

+
+		# Step Size for Spread Spectrum [25:24]
+		# PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
+
+		# Enable/Disable test mode force on SS step size
+		# PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
+
+		# Enable/Disable test mode force on SS no of steps
+		# PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
+
+		# Enable force on enable Spread Spectrum
+		#(OFFSET, MASK, VALUE)      (0XFD40A37C, 0x00000033U ,0x00000030U)  */
+    mask_write 0XFD40A37C 0x00000033 0x00000030
+		# Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370

+
+		# Step Size for Spread Spectrum [7:0]
+		# PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0x0
+
+		# Step Size for Spread Spectrum LSB
+		#(OFFSET, MASK, VALUE)      (0XFD40E370, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFD40E370 0x000000FF 0x00000000
+		# Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374

+
+		# Step Size for Spread Spectrum [15:8]
+		# PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x0
+
+		# Step Size for Spread Spectrum 1
+		#(OFFSET, MASK, VALUE)      (0XFD40E374, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFD40E374 0x000000FF 0x00000000
+		# Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378

+
+		# Step Size for Spread Spectrum [23:16]
+		# PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x0
+
+		# Step Size for Spread Spectrum 2
+		#(OFFSET, MASK, VALUE)      (0XFD40E378, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFD40E378 0x000000FF 0x00000000
+		# Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C

+
+		# Step Size for Spread Spectrum [25:24]
+		# PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
+
+		# Enable/Disable test mode force on SS step size
+		# PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
+
+		# Enable/Disable test mode force on SS no of steps
+		# PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
+
+		# Enable test mode forcing on enable Spread Spectrum
+		# PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS                             0x1
+
+		# Enable force on enable Spread Spectrum
+		#(OFFSET, MASK, VALUE)      (0XFD40E37C, 0x000000B3U ,0x000000B0U)  */
+    mask_write 0XFD40E37C 0x000000B3 0x000000B0
+		# Register : L2_TM_DIG_6 @ 0XFD40906C

+
+		# Bypass Descrambler
+		# PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM                                           0x1
+
+		# Enable Bypass for <1> TM_DIG_CTRL_6
+		# PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
+
+		# Data path test modes in decoder and descram
+		#(OFFSET, MASK, VALUE)      (0XFD40906C, 0x00000003U ,0x00000003U)  */
+    mask_write 0XFD40906C 0x00000003 0x00000003
+		# Register : L2_TX_DIG_TM_61 @ 0XFD4080F4

+
+		# Bypass scrambler signal
+		# PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
+
+		# Enable/disable scrambler bypass signal
+		# PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
+
+		# MPHY PLL Gear and bypass scrambler
+		#(OFFSET, MASK, VALUE)      (0XFD4080F4, 0x00000003U ,0x00000003U)  */
+    mask_write 0XFD4080F4 0x00000003 0x00000003
+		# Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360

+
+		# Enable test mode force on fractional mode enable
+		# PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC                             0x1
+
+		# Fractional feedback division control and fractional value for feedback division bits 26:24
+		#(OFFSET, MASK, VALUE)      (0XFD40E360, 0x00000040U ,0x00000040U)  */
+    mask_write 0XFD40E360 0x00000040 0x00000040
+		# Register : L3_TM_DIG_6 @ 0XFD40D06C

+
+		# Bypass 8b10b decoder
+		# PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER                                           0x1
+
+		# Enable Bypass for <3> TM_DIG_CTRL_6
+		# PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC                                         0x1
+
+		# Bypass Descrambler
+		# PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM                                           0x1
+
+		# Enable Bypass for <1> TM_DIG_CTRL_6
+		# PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
+
+		# Data path test modes in decoder and descram
+		#(OFFSET, MASK, VALUE)      (0XFD40D06C, 0x0000000FU ,0x0000000FU)  */
+    mask_write 0XFD40D06C 0x0000000F 0x0000000F
+		# Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4

+
+		# Enable/disable encoder bypass signal
+		# PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC                                           0x1
+
+		# Bypass scrambler signal
+		# PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
+
+		# Enable/disable scrambler bypass signal
+		# PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
+
+		# MPHY PLL Gear and bypass scrambler
+		#(OFFSET, MASK, VALUE)      (0XFD40C0F4, 0x0000000BU ,0x0000000BU)  */
+    mask_write 0XFD40C0F4 0x0000000B 0x0000000B
+		# Register : L3_TXPMA_ST_0 @ 0XFD40CB00

+
+		# PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY
+		# PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE                                            0x21
+
+		# Opmode Info
+		#(OFFSET, MASK, VALUE)      (0XFD40CB00, 0x000000F0U ,0x000000F0U)  */
+    mask_write 0XFD40CB00 0x000000F0 0x000000F0
+		# : GT LANE SETTINGS
+		# Register : ICM_CFG0 @ 0XFD410010

+
+		# Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
+		# , 7 - Unused
+		# PSU_SERDES_ICM_CFG0_L0_ICM_CFG                                                  1
+
+		# Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
+		#  7 - Unused
+		# PSU_SERDES_ICM_CFG0_L1_ICM_CFG                                                  4
+
+		# ICM Configuration Register 0
+		#(OFFSET, MASK, VALUE)      (0XFD410010, 0x00000077U ,0x00000041U)  */
+    mask_write 0XFD410010 0x00000077 0x00000041
+		# Register : ICM_CFG1 @ 0XFD410014

+
+		# Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
+		#  7 - Unused
+		# PSU_SERDES_ICM_CFG1_L2_ICM_CFG                                                  3
+
+		# Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
+		#  7 - Unused
+		# PSU_SERDES_ICM_CFG1_L3_ICM_CFG                                                  2
+
+		# ICM Configuration Register 1
+		#(OFFSET, MASK, VALUE)      (0XFD410014, 0x00000077U ,0x00000023U)  */
+    mask_write 0XFD410014 0x00000077 0x00000023
+		# : CHECKING PLL LOCK
+		# : ENABLE SERIAL DATA MUX DEEMPH
+		# Register : L1_TXPMD_TM_45 @ 0XFD404CB4

+
+		# Enable/disable DP post2 path
+		# PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH                         0x1
+
+		# Override enable/disable of DP post2 path
+		# PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH                    0x1
+
+		# Override enable/disable of DP post1 path
+		# PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH                    0x1
+
+		# Enable/disable DP main path
+		# PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH                          0x1
+
+		# Override enable/disable of DP main path
+		# PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH                     0x1
+
+		# Post or pre or main DP path selection
+		#(OFFSET, MASK, VALUE)      (0XFD404CB4, 0x00000037U ,0x00000037U)  */
+    mask_write 0XFD404CB4 0x00000037 0x00000037
+		# Register : L1_TX_ANA_TM_118 @ 0XFD4041D8

+
+		# Test register force for enabling/disablign TX deemphasis bits <17:0>
+		# PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0                                0x1
+
+		# Enable Override of TX deemphasis
+		#(OFFSET, MASK, VALUE)      (0XFD4041D8, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFD4041D8 0x00000001 0x00000001
+		# : ENABLE PRE EMPHAIS AND VOLTAGE SWING
+		# Register : L1_TXPMD_TM_48 @ 0XFD404CC0

+
+		# Margining factor value
+		# PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR                         0
+
+		# Margining factor
+		#(OFFSET, MASK, VALUE)      (0XFD404CC0, 0x0000001FU ,0x00000000U)  */
+    mask_write 0XFD404CC0 0x0000001F 0x00000000
+		# Register : L1_TX_ANA_TM_18 @ 0XFD404048

+
+		# pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
+		# PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0                                   0
+
+		# Override for PIPE TX de-emphasis
+		#(OFFSET, MASK, VALUE)      (0XFD404048, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFD404048 0x000000FF 0x00000000
+}
+
+set psu_resetout_init_data {
+		# : TAKING SERDES PERIPHERAL OUT OF RESET RESET
+		# : PUTTING USB0 IN RESET
+		# Register : RST_LPD_TOP @ 0XFF5E023C

+
+		# USB 0 reset for control registers
+		# PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X0
+
+		# Software control register for the LPD block.
+		#(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000400U ,0x00000000U)  */
+    mask_write 0XFF5E023C 0x00000400 0x00000000
+		# : USB0 PIPE POWER PRESENT
+		# Register : fpd_power_prsnt @ 0XFF9D0080

+
+		# This bit is used to choose between PIPE power present and 1'b1
+		# PSU_USB3_0_FPD_POWER_PRSNT_OPTION                                               0X1
+
+		# fpd_power_prsnt
+		#(OFFSET, MASK, VALUE)      (0XFF9D0080, 0x00000001U ,0x00000001U)  */
+    mask_write 0XFF9D0080 0x00000001 0x00000001
+		# : 
+		# Register : RST_LPD_TOP @ 0XFF5E023C

+
+		# USB 0 sleep circuit reset
+		# PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X0
+
+		# USB 0 reset
+		# PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X0
+
+		# Software control register for the LPD block.
+		#(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000140U ,0x00000000U)  */
+    mask_write 0XFF5E023C 0x00000140 0x00000000
+		# : PUTTING GEM0 IN RESET
+		# Register : RST_LPD_IOU0 @ 0XFF5E0230

+
+		# GEM 3 reset
+		# PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X0
+
+		# Software controlled reset for the GEMs
+		#(OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)  */
+    mask_write 0XFF5E0230 0x00000008 0x00000000
+		# : PUTTING SATA IN RESET
+		# Register : sata_misc_ctrl @ 0XFD3D0100

+
+		# Sata PM clock control select
+		# PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL                                         0x3
+
+		# Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled)
+		#(OFFSET, MASK, VALUE)      (0XFD3D0100, 0x00000003U ,0x00000003U)  */
+    mask_write 0XFD3D0100 0x00000003 0x00000003
+		# Register : RST_FPD_TOP @ 0XFD1A0100

+
+		# Sata block level reset
+		# PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X0
+
+		# FPD Block level software controlled reset
+		#(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000000U)  */
+    mask_write 0XFD1A0100 0x00000002 0x00000000
+		# : PUTTING PCIE IN RESET
+		# Register : RST_FPD_TOP @ 0XFD1A0100

+
+		# PCIE config reset
+		# PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0X0
+
+		# PCIE control block level reset
+		# PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0X0
+
+		# PCIE bridge block level reset (AXI interface)
+		# PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0X0
+
+		# FPD Block level software controlled reset
+		#(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000E0000U ,0x00000000U)  */
+    mask_write 0XFD1A0100 0x000E0000 0x00000000
+		# : PUTTING DP IN RESET
+		# Register : RST_FPD_TOP @ 0XFD1A0100

+
+		# Display Port block level reset (includes DPDMA)
+		# PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X0
+
+		# FPD Block level software controlled reset
+		#(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00000000U)  */
+    mask_write 0XFD1A0100 0x00010000 0x00000000
+		# Register : DP_PHY_RESET @ 0XFD4A0200

+
+		# Set to '1' to hold the GT in reset. Clear to release.
+		# PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X0
+
+		# Reset the transmitter PHY.
+		#(OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000000U)  */
+    mask_write 0XFD4A0200 0x00000002 0x00000000
+		# Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

+
+		# Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 
+		# ane0 Bits [3:2] - lane 1
+		# PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0X0
+
+		# Control PHY Power down
+		#(OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x00000000U)  */
+    mask_write 0XFD4A0238 0x0000000F 0x00000000
+		# : USB0 GFLADJ
+		# Register : GUSB2PHYCFG @ 0XFE20C200

+
+		# USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to 
+		# he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
+		# C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
+		# . The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
+		# UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger 
+		# alue. Note: This field is valid only in device mode.
+		# PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM                                           0X9
+
+		# Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
+		#  of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
+		# time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
+		# ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
+		# off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
+		# ng hibernation. - This bit is valid only in device mode.
+		# PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY                                             0X0
+
+		# Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
+		# _n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
+		#  to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. 
+		# ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
+		# n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
+		# d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
+		# d.
+		# PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM                                            0X0
+
+		# USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
+		# Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - 
+		# 'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
+		#  in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
+		#  active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
+		# PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL                                              0X0
+
+		# Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
+		# figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
+		# ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
+		# r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
+		# t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
+		# g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
+		#  when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.
+		# PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20                                        0X1
+
+		# Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
+		# full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with 
+		# ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
+		# B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
+		# PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF                                              0X0
+
+		# ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
+		# e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
+		# ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
+		# lected through DWC_USB3_HSPHY_INTERFACE.
+		# PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL                                       0X1
+
+		# PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
+		#  8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same 
+		# lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
+		#  ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
+		#  any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
+		# PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF                                               0X0
+
+		# HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
+		# a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for 
+		# dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
+		# e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
+		# The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this 
+		# ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
+		#  clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
+		# 60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
+		# PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL                                             0X7
+
+		# Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either 
+		# he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
+		# ented.
+		#(OFFSET, MASK, VALUE)      (0XFE20C200, 0x00003FFFU ,0x00002457U)  */
+    mask_write 0XFE20C200 0x00003FFF 0x00002457
+		# Register : GFLADJ @ 0XFE20C630

+
+		# This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register 
+		# alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
+		# _SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
+		# TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
+		# riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
+		# cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
+		# uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
+		# ((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
+		# RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
+		# PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ                                      0X0
+
+		# Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
+		# ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
+		#  to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely 
+		# rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
+		#(OFFSET, MASK, VALUE)      (0XFE20C630, 0x003FFF00U ,0x00000000U)  */
+    mask_write 0XFE20C630 0x003FFF00 0x00000000
+		# : CHECK PLL LOCK FOR LANE0
+		# Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4

+
+		# Status Read value of PLL Lock
+		# PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+    mask_poll 0XFD4023E4 0x00000010
+		# : CHECK PLL LOCK FOR LANE1
+		# Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4

+
+		# Status Read value of PLL Lock
+		# PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+    mask_poll 0XFD4063E4 0x00000010
+		# : CHECK PLL LOCK FOR LANE2
+		# Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4

+
+		# Status Read value of PLL Lock
+		# PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+    mask_poll 0XFD40A3E4 0x00000010
+		# : CHECK PLL LOCK FOR LANE3
+		# Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4

+
+		# Status Read value of PLL Lock
+		# PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+    mask_poll 0XFD40E3E4 0x00000010
+		# : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
+		# Register : ATTR_37 @ 0XFD480094

+
+		# Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
+		# gister.; EP=0x0001; RP=0x0001
+		# PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY                          0X1
+
+		# ATTR_37
+		#(OFFSET, MASK, VALUE)      (0XFD480094, 0x00004000U ,0x00004000U)  */
+    mask_write 0XFD480094 0x00004000 0x00004000
+		# Register : ATTR_25 @ 0XFD480064

+
+		# If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
+		# ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001
+		# PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED                      0X1
+
+		# ATTR_25
+		#(OFFSET, MASK, VALUE)      (0XFD480064, 0x00000200U ,0x00000200U)  */
+    mask_write 0XFD480064 0x00000200 0x00000200
+		# : PCIE SETTINGS
+		# Register : ATTR_7 @ 0XFD48001C

+
+		# Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
+		# ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
+		# Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
+		# erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 
+		# set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
+		# re size in bytes.; EP=0x0004; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0                                                0x0
+
+		# ATTR_7
+		#(OFFSET, MASK, VALUE)      (0XFD48001C, 0x0000FFFFU ,0x00000000U)  */
+    mask_write 0XFD48001C 0x0000FFFF 0x00000000
+		# Register : ATTR_8 @ 0XFD480020

+
+		# Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
+		# ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
+		# Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
+		# erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 
+		# set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
+		# re size in bytes.; EP=0xFFF0; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0                                                0x0
+
+		# ATTR_8
+		#(OFFSET, MASK, VALUE)      (0XFD480020, 0x0000FFFFU ,0x00000000U)  */
+    mask_write 0XFD480020 0x0000FFFF 0x00000000
+		# Register : ATTR_9 @ 0XFD480024

+
+		# Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 
+		# AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
+		#  bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 
+		# o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
+		# 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 
+		# '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
+		# ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1                                                0x0
+
+		# ATTR_9
+		#(OFFSET, MASK, VALUE)      (0XFD480024, 0x0000FFFFU ,0x00000000U)  */
+    mask_write 0XFD480024 0x0000FFFF 0x00000000
+		# Register : ATTR_10 @ 0XFD480028

+
+		# Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 
+		# AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
+		#  bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 
+		# o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
+		# 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 
+		# '7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
+		# ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1                                               0x0
+
+		# ATTR_10
+		#(OFFSET, MASK, VALUE)      (0XFD480028, 0x0000FFFFU ,0x00000000U)  */
+    mask_write 0XFD480028 0x0000FFFF 0x00000000
+		# Register : ATTR_11 @ 0XFD48002C

+
+		# For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
+		# AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
+		# tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
+		# , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		# ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		# most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 
+		# . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		# ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF
+		# PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2                                               0xFFFF
+
+		# ATTR_11
+		#(OFFSET, MASK, VALUE)      (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU)  */
+    mask_write 0XFD48002C 0x0000FFFF 0x0000FFFF
+		# Register : ATTR_12 @ 0XFD480030

+
+		# For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
+		# AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
+		# tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
+		# , bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		# ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		# most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 
+		# . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		# ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF
+		# PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2                                               0xFF
+
+		# ATTR_12
+		#(OFFSET, MASK, VALUE)      (0XFD480030, 0x0000FFFFU ,0x000000FFU)  */
+    mask_write 0XFD480030 0x0000FFFF 0x000000FF
+		# Register : ATTR_13 @ 0XFD480034

+
+		# For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
+		# AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
+		# tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
+		#  Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
+		# t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
+		# t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
+		# if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 
+		# f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
+		#  bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3                                               0x0
+
+		# ATTR_13
+		#(OFFSET, MASK, VALUE)      (0XFD480034, 0x0000FFFFU ,0x00000000U)  */
+    mask_write 0XFD480034 0x0000FFFF 0x00000000
+		# Register : ATTR_14 @ 0XFD480038

+
+		# For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
+		# AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
+		# tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
+		#  Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
+		# t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
+		# t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
+		# if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 
+		# f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
+		#  bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF
+		# PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3                                               0xFFFF
+
+		# ATTR_14
+		#(OFFSET, MASK, VALUE)      (0XFD480038, 0x0000FFFFU ,0x0000FFFFU)  */
+    mask_write 0XFD480038 0x0000FFFF 0x0000FFFF
+		# Register : ATTR_15 @ 0XFD48003C

+
+		# For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
+		# AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
+		# tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
+		# , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		# ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		# most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 
+		# . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		# ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0
+		# PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4                                               0xFFF0
+
+		# ATTR_15
+		#(OFFSET, MASK, VALUE)      (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U)  */
+    mask_write 0XFD48003C 0x0000FFFF 0x0000FFF0
+		# Register : ATTR_16 @ 0XFD480040

+
+		# For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
+		# AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
+		# tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
+		# , bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		# ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		# most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 
+		# . IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		# ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0
+		# PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4                                               0xFFF0
+
+		# ATTR_16
+		#(OFFSET, MASK, VALUE)      (0XFD480040, 0x0000FFFFU ,0x0000FFF0U)  */
+    mask_write 0XFD480040 0x0000FFFF 0x0000FFF0
+		# Register : ATTR_17 @ 0XFD480044

+
+		# For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
+		# AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
+		# tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
+		# Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 
+		# refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
+		# R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 
+		# refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 
+		# ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
+		# permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
+		# PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5                                               0xFFF1
+
+		# ATTR_17
+		#(OFFSET, MASK, VALUE)      (0XFD480044, 0x0000FFFFU ,0x0000FFF1U)  */
+    mask_write 0XFD480044 0x0000FFFF 0x0000FFF1
+		# Register : ATTR_18 @ 0XFD480048

+
+		# For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
+		# AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
+		# tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
+		# Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 
+		# refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
+		# R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 
+		# refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 
+		# ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
+		# permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
+		# PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5                                               0xFFF1
+
+		# ATTR_18
+		#(OFFSET, MASK, VALUE)      (0XFD480048, 0x0000FFFFU ,0x0000FFF1U)  */
+    mask_write 0XFD480048 0x0000FFFF 0x0000FFF1
+		# Register : ATTR_27 @ 0XFD48006C

+
+		# Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
+		# to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001
+		# PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED                      1
+
+		# Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
+		# state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
+		#  32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY                        0x0
+
+		# ATTR_27
+		#(OFFSET, MASK, VALUE)      (0XFD48006C, 0x00000738U ,0x00000100U)  */
+    mask_write 0XFD48006C 0x00000738 0x00000100
+		# Register : ATTR_50 @ 0XFD4800C8

+
+		# Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
+		# 00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
+		# tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
+		# gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004
+		# PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE                          4
+
+		# PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
+		# lity.; EP=0x009C; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR                                   0
+
+		# ATTR_50
+		#(OFFSET, MASK, VALUE)      (0XFD4800C8, 0x0000FFF0U ,0x00000040U)  */
+    mask_write 0XFD4800C8 0x0000FFF0 0x00000040
+		# Register : ATTR_105 @ 0XFD4801A4

+
+		# Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
+		# ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
+		# PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD                              0xCD
+
+		# ATTR_105
+		#(OFFSET, MASK, VALUE)      (0XFD4801A4, 0x000007FFU ,0x000000CDU)  */
+    mask_write 0XFD4801A4 0x000007FF 0x000000CD
+		# Register : ATTR_106 @ 0XFD4801A8

+
+		# Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non 
+		# osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024
+		# PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH                              0x24
+
+		# Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
+		# a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
+		# completion header credits must be <= 80; EP=0x0004; RP=0x000C
+		# PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH                             0xC
+
+		# ATTR_106
+		#(OFFSET, MASK, VALUE)      (0XFD4801A8, 0x00003FFFU ,0x00000624U)  */
+    mask_write 0XFD4801A8 0x00003FFF 0x00000624
+		# Register : ATTR_107 @ 0XFD4801AC

+
+		# Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data 
+		# redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
+		# d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
+		# less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
+		# PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD                             0x18
+
+		# ATTR_107
+		#(OFFSET, MASK, VALUE)      (0XFD4801AC, 0x000007FFU ,0x00000018U)  */
+    mask_write 0XFD4801AC 0x000007FF 0x00000018
+		# Register : ATTR_108 @ 0XFD4801B0

+
+		# Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less 
+		# han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
+		# PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD                              0xB5
+
+		# ATTR_108
+		#(OFFSET, MASK, VALUE)      (0XFD4801B0, 0x000007FFU ,0x000000B5U)  */
+    mask_write 0XFD4801B0 0x000007FF 0x000000B5
+		# Register : ATTR_109 @ 0XFD4801B4

+
+		# Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
+		# 0
+		# PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV                                      0x0
+
+		# Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001
+		# PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM                                    0x1
+
+		# Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
+		# cap structure; EP=0x0003; RP=0x0003
+		# PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK                                         0x3
+
+		# Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
+		# mber of brams configured for transmit; EP=0x001C; RP=0x001C
+		# PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET                                 0x1c
+
+		# Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
+		# d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020
+		# PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH                              0x20
+
+		# ATTR_109
+		#(OFFSET, MASK, VALUE)      (0XFD4801B4, 0x0000FFFFU ,0x00007E20U)  */
+    mask_write 0XFD4801B4 0x0000FFFF 0x00007E20
+		# Register : ATTR_34 @ 0XFD480088

+
+		# Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
+		# 0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001
+		# PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE                                        0x1
+
+		# ATTR_34
+		#(OFFSET, MASK, VALUE)      (0XFD480088, 0x000000FFU ,0x00000001U)  */
+    mask_write 0XFD480088 0x000000FF 0x00000001
+		# Register : ATTR_53 @ 0XFD4800D4

+
+		# PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
+		# ty.; EP=0x0048; RP=0x0060
+		# PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR                                     0x60
+
+		# ATTR_53
+		#(OFFSET, MASK, VALUE)      (0XFD4800D4, 0x000000FFU ,0x00000060U)  */
+    mask_write 0XFD4800D4 0x000000FF 0x00000060
+		# Register : ATTR_41 @ 0XFD4800A4

+
+		# MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
+		#  to Cap structure; EP=0x0000; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE                 0x0
+
+		# Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 
+		# he management port.; EP=0x0001; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON                                         0
+
+		# MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
+		# ity.; EP=0x0060; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR                                    0x0
+
+		# Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 
+		# he management port.; EP=0x0001; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON                                         0
+
+		# ATTR_41
+		#(OFFSET, MASK, VALUE)      (0XFD4800A4, 0x000003FFU ,0x00000000U)  */
+    mask_write 0XFD4800A4 0x000003FF 0x00000000
+		# Register : ATTR_97 @ 0XFD480184

+
+		# Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004
+		# PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH                            0x1
+
+		# Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
+		# 4; RP=0x0004
+		# PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH                               0x1
+
+		# ATTR_97
+		#(OFFSET, MASK, VALUE)      (0XFD480184, 0x00000FFFU ,0x00000041U)  */
+    mask_write 0XFD480184 0x00000FFF 0x00000041
+		# Register : ATTR_100 @ 0XFD480190

+
+		# TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING                                   0x0
+
+		# ATTR_100
+		#(OFFSET, MASK, VALUE)      (0XFD480190, 0x00000040U ,0x00000000U)  */
+    mask_write 0XFD480190 0x00000040 0x00000000
+		# Register : ATTR_101 @ 0XFD480194

+
+		# Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message 
+		# LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
+		# Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
+		# EP=0x0000; RP=0x07FF
+		# PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE                                  0x7FF
+
+		# Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001
+		# PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING                             0x1
+
+		# ATTR_101
+		#(OFFSET, MASK, VALUE)      (0XFD480194, 0x0000FFE2U ,0x0000FFE2U)  */
+    mask_write 0XFD480194 0x0000FFE2 0x0000FFE2
+		# Register : ATTR_37 @ 0XFD480094

+
+		# Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
+		# Required for Root.; EP=0x0000; RP=0x0001
+		# PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP           0x1
+
+		# ATTR_37
+		#(OFFSET, MASK, VALUE)      (0XFD480094, 0x00000200U ,0x00000200U)  */
+    mask_write 0XFD480094 0x00000200 0x00000200
+		# Register : ATTR_93 @ 0XFD480174

+
+		# Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
+		# _REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN                               0x1
+
+		# Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
+		# TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
+		# 4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT                                  0x1000
+
+		# ATTR_93
+		#(OFFSET, MASK, VALUE)      (0XFD480174, 0x0000FFFFU ,0x00009000U)  */
+    mask_write 0XFD480174 0x0000FFFF 0x00009000
+		# Register : ID @ 0XFD480200

+
+		# Device ID for the the PCIe Cap Structure Device ID field
+		# PSU_PCIE_ATTRIB_ID_CFG_DEV_ID                                                   0xd021
+
+		# Vendor ID for the PCIe Cap Structure Vendor ID field
+		# PSU_PCIE_ATTRIB_ID_CFG_VEND_ID                                                  0x10ee
+
+		# ID
+		#(OFFSET, MASK, VALUE)      (0XFD480200, 0xFFFFFFFFU ,0x10EED021U)  */
+    mask_write 0XFD480200 0xFFFFFFFF 0x10EED021
+		# Register : SUBSYS_ID @ 0XFD480204

+
+		# Subsystem ID for the the PCIe Cap Structure Subsystem ID field
+		# PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID                                         0x7
+
+		# Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
+		# PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID                                    0x10ee
+
+		# SUBSYS_ID
+		#(OFFSET, MASK, VALUE)      (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U)  */
+    mask_write 0XFD480204 0xFFFFFFFF 0x10EE0007
+		# Register : REV_ID @ 0XFD480208

+
+		# Revision ID for the the PCIe Cap Structure
+		# PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID                                               0x0
+
+		# REV_ID
+		#(OFFSET, MASK, VALUE)      (0XFD480208, 0x000000FFU ,0x00000000U)  */
+    mask_write 0XFD480208 0x000000FF 0x00000000
+		# Register : ATTR_24 @ 0XFD480060

+
+		# Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
+		# 8000; RP=0x8000
+		# PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE                                         0x400
+
+		# ATTR_24
+		#(OFFSET, MASK, VALUE)      (0XFD480060, 0x0000FFFFU ,0x00000400U)  */
+    mask_write 0XFD480060 0x0000FFFF 0x00000400
+		# Register : ATTR_25 @ 0XFD480064

+
+		# Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
+		# 0005; RP=0x0006
+		# PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE                                         0x6
+
+		# INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001
+		# PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED                               0
+
+		# ATTR_25
+		#(OFFSET, MASK, VALUE)      (0XFD480064, 0x000001FFU ,0x00000006U)  */
+    mask_write 0XFD480064 0x000001FF 0x00000006
+		# Register : ATTR_4 @ 0XFD480010

+
+		# Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 
+		# he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
+		# ges are sent if an error is detected).; EP=0x0001; RP=0x0001
+		# PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON                                          0
+
+		# Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 
+		# he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
+		# ges are sent if an error is detected).; EP=0x0001; RP=0x0001
+		# PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON                                          0
+
+		# ATTR_4
+		#(OFFSET, MASK, VALUE)      (0XFD480010, 0x00001000U ,0x00000000U)  */
+    mask_write 0XFD480010 0x00001000 0x00000000
+		# Register : ATTR_89 @ 0XFD480164

+
+		# VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
+		# 0x0140; RP=0x0140
+		# PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR                                   0
+
+		# ATTR_89
+		#(OFFSET, MASK, VALUE)      (0XFD480164, 0x00001FFEU ,0x00000000U)  */
+    mask_write 0XFD480164 0x00001FFE 0x00000000
+		# Register : ATTR_79 @ 0XFD48013C

+
+		# CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY                         1
+
+		# ATTR_79
+		#(OFFSET, MASK, VALUE)      (0XFD48013C, 0x00000020U ,0x00000020U)  */
+    mask_write 0XFD48013C 0x00000020 0x00000020
+		# Register : ATTR_43 @ 0XFD4800AC

+
+		# Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
+		#  the management port.; EP=0x0001; RP=0x0000
+		# PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON                                        0
+
+		# ATTR_43
+		#(OFFSET, MASK, VALUE)      (0XFD4800AC, 0x00000100U ,0x00000000U)  */
+    mask_write 0XFD4800AC 0x00000100 0x00000000
+}
+
+set psu_resetin_init_data {
+		# : PUTTING SERDES PERIPHERAL IN RESET
+		# : PUTTING USB0 IN RESET
+		# Register : RST_LPD_TOP @ 0XFF5E023C

+
+		# USB 0 reset for control registers
+		# PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X1
+
+		# USB 0 sleep circuit reset
+		# PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X1
+
+		# USB 0 reset
+		# PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X1
+
+		# Software control register for the LPD block.
+		#(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000540U)  */
+    mask_write 0XFF5E023C 0x00000540 0x00000540
+		# : PUTTING GEM0 IN RESET
+		# Register : RST_LPD_IOU0 @ 0XFF5E0230

+
+		# GEM 3 reset
+		# PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X1
+
+		# Software controlled reset for the GEMs
+		#(OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000008U)  */
+    mask_write 0XFF5E0230 0x00000008 0x00000008
+		# : PUTTING SATA IN RESET
+		# Register : RST_FPD_TOP @ 0XFD1A0100

+
+		# Sata block level reset
+		# PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X1
+
+		# FPD Block level software controlled reset
+		#(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000002U)  */
+    mask_write 0XFD1A0100 0x00000002 0x00000002
+		# : PUTTING PCIE IN RESET
+		# Register : RST_FPD_TOP @ 0XFD1A0100

+
+		# PCIE config reset
+		# PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0X1
+
+		# PCIE control block level reset
+		# PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0X1
+
+		# PCIE bridge block level reset (AXI interface)
+		# PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0X1
+
+		# FPD Block level software controlled reset
+		#(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000E0000U ,0x000E0000U)  */
+    mask_write 0XFD1A0100 0x000E0000 0x000E0000
+		# : PUTTING DP IN RESET
+		# Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

+
+		# Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 
+		# ane0 Bits [3:2] - lane 1
+		# PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0XA
+
+		# Control PHY Power down
+		#(OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x0000000AU)  */
+    mask_write 0XFD4A0238 0x0000000F 0x0000000A
+		# Register : DP_PHY_RESET @ 0XFD4A0200

+
+		# Set to '1' to hold the GT in reset. Clear to release.
+		# PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X1
+
+		# Reset the transmitter PHY.
+		#(OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000002U)  */
+    mask_write 0XFD4A0200 0x00000002 0x00000002
+		# Register : RST_FPD_TOP @ 0XFD1A0100

+
+		# Display Port block level reset (includes DPDMA)
+		# PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X1
+
+		# FPD Block level software controlled reset
+		#(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00010000U)  */
+    mask_write 0XFD1A0100 0x00010000 0x00010000
+}
+
+set psu_ps_pl_isolation_removal_data {
+		# : PS-PL POWER UP REQUEST
+		# Register : REQ_PWRUP_INT_EN @ 0XFFD80118

+
+		# Power-up Request Interrupt Enable for PL
+		# PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL                                              1
+
+		# Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt.
+		#(OFFSET, MASK, VALUE)      (0XFFD80118, 0x00800000U ,0x00800000U)  */
+    mask_write 0XFFD80118 0x00800000 0x00800000
+		# Register : REQ_PWRUP_TRIG @ 0XFFD80120

+
+		# Power-up Request Trigger for PL
+		# PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL                                                1
+
+		# Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU.
+		#(OFFSET, MASK, VALUE)      (0XFFD80120, 0x00800000U ,0x00800000U)  */
+    mask_write 0XFFD80120 0x00800000 0x00800000
+		# : POLL ON PL POWER STATUS
+		# Register : REQ_PWRUP_STATUS @ 0XFFD80110

+
+		# Power-up Request Status for PL
+		# PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL                                              1
+    mask_poll 0XFFD80110 0x00800000 0x00000000
+}
+
+set psu_ps_pl_reset_config_data {
+		# : PS PL RESET SEQUENCE
+		# : FABRIC RESET USING EMIO
+		# Register : MASK_DATA_5_MSW @ 0XFF0A002C

+
+		# Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
+		# PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW                                             0x8000
+
+		# Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits)
+		#(OFFSET, MASK, VALUE)      (0XFF0A002C, 0xFFFF0000U ,0x80000000U)  */
+    mask_write 0XFF0A002C 0xFFFF0000 0x80000000
+		# Register : DIRM_5 @ 0XFF0A0344

+
+		# Operation is the same as DIRM_0[DIRECTION_0]
+		# PSU_GPIO_DIRM_5_DIRECTION_5                                                     0x80000000
+
+		# Direction mode (GPIO Bank5, EMIO)
+		#(OFFSET, MASK, VALUE)      (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U)  */
+    mask_write 0XFF0A0344 0xFFFFFFFF 0x80000000
+		# Register : OEN_5 @ 0XFF0A0348

+
+		# Operation is the same as OEN_0[OP_ENABLE_0]
+		# PSU_GPIO_OEN_5_OP_ENABLE_5                                                      0x80000000
+
+		# Output enable (GPIO Bank5, EMIO)
+		#(OFFSET, MASK, VALUE)      (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U)  */
+    mask_write 0XFF0A0348 0xFFFFFFFF 0x80000000
+		# Register : DATA_5 @ 0XFF0A0054

+
+		# Output Data
+		# PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
+
+		# Output Data (GPIO Bank5, EMIO)
+		#(OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)  */
+    mask_write 0XFF0A0054 0xFFFFFFFF 0x80000000
+    mask_delay 0x00000000 1
+		# : FABRIC RESET USING DATA_5 TOGGLE
+		# Register : DATA_5 @ 0XFF0A0054

+
+		# Output Data
+		# PSU_GPIO_DATA_5_DATA_5                                                          0X00000000
+
+		# Output Data (GPIO Bank5, EMIO)
+		#(OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U)  */
+    mask_write 0XFF0A0054 0xFFFFFFFF 0x00000000
+    mask_delay 0x00000000 1
+		# : FABRIC RESET USING DATA_5 TOGGLE
+		# Register : DATA_5 @ 0XFF0A0054

+
+		# Output Data
+		# PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
+
+		# Output Data (GPIO Bank5, EMIO)
+		#(OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)  */
+    mask_write 0XFF0A0054 0xFFFFFFFF 0x80000000
+}
+
+proc psu_init {} {
+    # save current mode
+    set saved_mode [configparams force-mem-accesses]                  
+    # force accesses
+    configparams force-mem-accesses 1 
+    variable psu_mio_init_data 
+    variable psu_pll_init_data 
+    variable psu_clock_init_data
+	variable psu_ddr_init_data
+    variable psu_peripherals_init_data
+    variable psu_resetin_init_data
+    variable psu_resetout_init_data
+    variable psu_serdes_init_data
+    variable psu_resetin_init_data
+    variable psu_peripherals_powerdwn_data 
+
+    init_ps [subst {$psu_mio_init_data $psu_pll_init_data $psu_clock_init_data $psu_ddr_init_data }]
+    psu_ddr_phybringup_data 
+    init_ps [subst {$psu_peripherals_init_data $psu_resetin_init_data }]
+    init_serdes 
+    init_ps [subst {$psu_serdes_init_data $psu_resetout_init_data }]
+    init_peripheral 
+    init_ps [subst {$psu_peripherals_powerdwn_data }]
+    # restore original mode
+    configparams force-mem-accesses $saved_mode                                       
+}
+
+proc psu_post_config {} {
+    variable psu_post_config_data
+    init_ps [subst {$psu_post_config_data}]
+}
+
+proc psu_ps_pl_reset_config {} {
+    variable psu_ps_pl_reset_config_data
+    init_ps [subst {$psu_ps_pl_reset_config_data}]
+}
+
+proc psu_ps_pl_isolation_removal {} {
+    variable psu_ps_pl_isolation_removal_data
+    init_ps [subst {$psu_ps_pl_isolation_removal_data}]
+}
+
+
+proc mask_read { addr mask } {
+    set curval "0x[string range [mrd -force $addr] end-8 end]"
+    set maskedval [expr {$curval & $mask}]
+    return $maskedval
+}
+
+
+proc mask_poll { addr mask } {
+    set count 1
+    set curval "0x[string range [mrd -force $addr] end-8 end]"
+    set maskedval [expr {$curval & $mask}]
+    while { $maskedval == 0 } {
+        set curval "0x[string range [mrd -force $addr] end-8 end]"
+        set maskedval [expr {$curval & $mask}]
+        set count [ expr { $count + 1 } ]
+        if { $count == 100000000 } {
+          puts "Timeout Reached. Mask poll failed at ADDRESS: $addr MASK: $mask"
+          break
+        }
+    }
+}
+
+proc psu_mask_write { addr mask value } {
+    set curval "0x[string range [mrd -force $addr] end-8 end]"
+    set curval [expr {$curval & ~($mask)}]
+    set maskedval [expr {$value & $mask}]
+    set maskedval [expr {$curval | $maskedval}]
+    mwr -force $addr $maskedval
+}
+
+
+proc  serdes_fixcal_code {} {
+   #/*
+   # * L3_TM_CALIB_DIG19
+   # */
+   mask_write 0xFD40EC4C 0xFFFFFFFF 0x00000020
+   
+   
+   #/*
+   # * ICM_CFG0
+   # */
+   mask_write 0xFD410010 0xFFFFFFFF 0x00000001
+
+   
+   #/*
+   # * is calibration done, polling on L3_CALIB_DONE_STATUS
+   # */
+   mask_poll 0xFD40EF14 0x2
+ 
+   #unsigned int tmp_0_1; 
+   set tmp_0_1 [mrd -force -value 0xFD400B0C]
+   set tmp_0_1 [expr {$tmp_0_1 & 0x3F}]
+
+   set tmp_0_2 [expr {$tmp_0_1 & 0x7}]
+   set tmp_0_3 [expr {$tmp_0_1 & 0x38}]
+   
+   #Configure ICM for de-asserting CMN_Resetn
+   mask_write 0xFD410010 0xFFFFFFFF 0x00000000
+   mask_write 0xFD410014 0xFFFFFFFF 0x00000000
+
+   set tmp_0_2_mod [expr {($tmp_0_2 << 1) | (0x1)}]
+   set tmp_0_2_mod [expr {$tmp_0_2_mod << 4}]
+   
+   set tmp_0_3 [expr {$tmp_0_3 >> 3}]
+   mask_write 0xFD40EC4C 0xFFFFFFFF $tmp_0_3
+   
+   #L3_TM_CALIB_DIG18
+   mask_write 0xFD40EC48 0xFFFFFFFF $tmp_0_2_mod
+
+
+}
+
+proc serdes_enb_coarse_saturation {} { 
+   #/* 
+   # * Enable PLL Coarse Code saturation Logic
+   # */
+   mask_write 0xFD402094 0xFFFFFFFF 0x00000010 
+   mask_write 0xFD406094 0xFFFFFFFF 0x00000010 
+   mask_write 0xFD40A094 0xFFFFFFFF 0x00000010 
+   mask_write 0xFD40E094 0xFFFFFFFF 0x00000010
+
+}
+
+
+proc init_serdes {} {
+
+  serdes_fixcal_code
+  serdes_enb_coarse_saturation
+
+}
+
+proc poll { addr mask data} {
+    set curval "0x[string range [mrd -force $addr] end-8 end]"
+    set maskedval [expr {$curval & $mask}]
+    while { $maskedval != $data } {
+        set curval "0x[string range [mrd -force $addr] end-8 end]"
+        set maskedval [expr {$curval & $mask}]
+    }
+}
+
+proc init_peripheral {} {
+
+	# Release all resets in the IOU */
+   mask_write 0xFF5E0230 0xFFFFFFFF 0x00000000
+   mask_write 0xFF5E0234 0xFFFFFFFF 0x00000000
+   mask_write 0xFF5E0238 0xFFFFFFFF 0x00000000 
+
+	# Take LPD out of reset except R5 */
+   set tmp_0_1 [mrd -force -value 0xFF5E023C]
+   set tmp_0_1 [expr {$tmp_0_1 & 0x7}]
+   mask_write 0xFF5E023C 0xFFFFFFFF $tmp_0_1
+
+	# Take most of FPD out of reset */
+   mask_write 0XFD1A0100 0xFFFFFFFF 0x00000000 
+
+	# Making DPDMA as secure 
+   mask_write 0xFD690040 0x00000001 0x00000000 
+	# Making PCIe as secure 
+   mask_write 0xFD690030 0x00000001 0x00000000 
+
+}
+
+
+proc psu_ddr_phybringup_data {} {
+mwr -force  0xFD090000 0x0000A845
+mwr -force  0xFD090004 0x003FFFFF
+mwr -force  0xFD09000C 0x00000010
+mwr -force  0xFD090010 0x00000010
+
+poll 0xFD080030 0x0000000F 0x0000000F  
+	psu_mask_write 0xFD080004 0x00000001 0x00000001
+#poll for PHY initialization to complete 
+poll 0xFD080030 0x000000FF 0x0000001F 
+
+mwr -force  0xFD0701B0 0x00000001
+mwr -force  0xFD070320 0x00000001
+#//poll for DDR initialization to complete 
+poll 0xFD070004 0x0000000F 0x00000001 
+
+	psu_mask_write 0xFD080014 0x00000040 0x00000040
+#Dummy reads before PHY training starts
+mrd -force 0xFD070004    
+  #//dummy reads 
+mrd -force 0xFD070004    
+  #//dummy reads 
+mrd -force 0xFD070004    
+  #//dummy reads 
+mrd -force 0xFD070004    
+  #//dummy reads 
+mrd -force 0xFD070004    
+  #//dummy reads 
+mrd -force 0xFD070004    
+  #//dummy reads 
+psu_mask_write 0xFD080004 0xFFFFFFFF 0x0004FE01
+ #trigger PHY training 
+poll 0xFD080030 0x00000FFF 0x00000FFF
+ 
+  #Poll PUB_PGSR0 for Trng complete  
+
+
+ # Run Vref training in static read mode  
+mwr -force  0xFD080200 0x110011C7
+mwr -force  0xFD080018 0x00F01EF2
+mwr -force  0xFD08001C 0x55AA0098
+mwr -force  0xFD08142C 0x00001830
+mwr -force  0xFD08146C 0x00001830
+mwr -force  0xFD0814AC 0x00001830
+mwr -force  0xFD0814EC 0x00001830
+mwr -force  0xFD08152C 0x00001830
+psu_mask_write 0xFD080004 0xFFFFFFFF 0x00060001
+  
+ #trigger VreFPHY training 
+poll 0xFD080030 0x00004001 0x00004001
+     
+ #//Poll PUB_PGSR0 for Trng complete  
+ # Vref training is complete, disabling static read mode 
+mwr -force  0xFD080200 0x810011C7
+mwr -force  0xFD080018 0x00F12302
+mwr -force  0xFD08001C 0x55AA0080
+mwr -force  0xFD08142C 0x00001800
+mwr -force  0xFD08146C 0x00001800
+mwr -force  0xFD0814AC 0x00001800
+mwr -force  0xFD0814EC 0x00001800
+mwr -force  0xFD08152C 0x00001800
+mwr -force  0xFD070180 0x01000040
+mwr -force  0xFD070060 0x00000000
+	psu_mask_write 0xFD080014 0x00000040 0x00000000
+
+ 
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c
new file mode 100644
index 000000000..a6cdc38f1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.c
@@ -0,0 +1,19357 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* 
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+* 
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, see 
+* 
+* 
+******************************************************************************/ 
+
+#include 
+#include "psu_init_gpl.h"
+
+static void PSU_Mask_Write (unsigned long offset, unsigned long mask, unsigned long val)
+{
+	unsigned long RegVal = 0x0;
+	RegVal = Xil_In32 (offset);
+	RegVal &= ~(mask);
+	RegVal |= (val & mask);
+	Xil_Out32 (offset, RegVal);
+}
+
+unsigned long psu_pll_init_data() {
+		// : RPLL INIT
+		/*Register : RPLL_CFG @ 0XFF5E0034

+
+		PLL loop filter resistor control
+		PSU_CRL_APB_RPLL_CFG_RES                                                        0x2
+
+		PLL charge pump control
+		PSU_CRL_APB_RPLL_CFG_CP                                                         0x3
+
+		PLL loop filter high frequency capacitor control
+		PSU_CRL_APB_RPLL_CFG_LFHF                                                       0x3
+
+		Lock circuit counter setting
+		PSU_CRL_APB_RPLL_CFG_LOCK_CNT                                                   0x258
+
+		Lock circuit configuration settings for lock windowsize
+		PSU_CRL_APB_RPLL_CFG_LOCK_DLY                                                   0x3f
+
+		Helper data. Values are to be looked up in a table from Data Sheet
+		(OFFSET, MASK, VALUE)      (0XFF5E0034, 0xFE7FEDEFU ,0x7E4B0C62U)  
+		RegMask = (CRL_APB_RPLL_CFG_RES_MASK | CRL_APB_RPLL_CFG_CP_MASK | CRL_APB_RPLL_CFG_LFHF_MASK | CRL_APB_RPLL_CFG_LOCK_CNT_MASK | CRL_APB_RPLL_CFG_LOCK_DLY_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRL_APB_RPLL_CFG_RES_SHIFT
+			| 0x00000003U << CRL_APB_RPLL_CFG_CP_SHIFT
+			| 0x00000003U << CRL_APB_RPLL_CFG_LFHF_SHIFT
+			| 0x00000258U << CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT
+			| 0x0000003FU << CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
+	/*############################################################################################################################ */
+
+		// : UPDATE FB_DIV
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		PSU_CRL_APB_RPLL_CTRL_PRE_SRC                                                   0x0
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRL_APB_RPLL_CTRL_FBDIV                                                     0x48
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRL_APB_RPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00717F00U ,0x00014800U)  
+		RegMask = (CRL_APB_RPLL_CTRL_PRE_SRC_MASK | CRL_APB_RPLL_CTRL_FBDIV_MASK | CRL_APB_RPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT
+			| 0x00000048U << CRL_APB_RPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRL_APB_RPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00717F00U ,0x00014800U);
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000008U)  
+		RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRL_APB_RPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000001U)  
+		RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_RPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRL_APB_RPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000001U ,0x00000000U)  
+		RegMask = (CRL_APB_RPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFF5E0040

+
+		RPLL is locked
+		PSU_CRL_APB_PLL_STATUS_RPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000002U ,0x00000002U)  */
+		mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000002U);
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : RPLL_CTRL @ 0XFF5E0030

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_RPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0030, 0x00000008U ,0x00000000U)  
+		RegMask = (CRL_APB_RPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : RPLL_TO_FPD_CTRL @ 0XFF5E0048

+
+		Divisor value for this clock.
+		PSU_CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0                                           0x3
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFF5E0048, 0x00003F00U ,0x00000300U)  
+		RegMask = (CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000003U << CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		// : RPLL FRAC CFG
+		/*Register : RPLL_FRAC_CFG @ 0XFF5E0038

+
+		Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.
+		PSU_CRL_APB_RPLL_FRAC_CFG_ENABLED                                               0x0
+
+		Fractional value for the Feedback value.
+		PSU_CRL_APB_RPLL_FRAC_CFG_DATA                                                  0x0
+
+		Fractional control for the PLL
+		(OFFSET, MASK, VALUE)      (0XFF5E0038, 0x8000FFFFU ,0x00000000U)  
+		RegMask = (CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_RPLL_FRAC_CFG_DATA_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT
+			| 0x00000000U << CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : IOPLL INIT
+		/*Register : IOPLL_CFG @ 0XFF5E0024

+
+		PLL loop filter resistor control
+		PSU_CRL_APB_IOPLL_CFG_RES                                                       0xc
+
+		PLL charge pump control
+		PSU_CRL_APB_IOPLL_CFG_CP                                                        0x3
+
+		PLL loop filter high frequency capacitor control
+		PSU_CRL_APB_IOPLL_CFG_LFHF                                                      0x3
+
+		Lock circuit counter setting
+		PSU_CRL_APB_IOPLL_CFG_LOCK_CNT                                                  0x339
+
+		Lock circuit configuration settings for lock windowsize
+		PSU_CRL_APB_IOPLL_CFG_LOCK_DLY                                                  0x3f
+
+		Helper data. Values are to be looked up in a table from Data Sheet
+		(OFFSET, MASK, VALUE)      (0XFF5E0024, 0xFE7FEDEFU ,0x7E672C6CU)  
+		RegMask = (CRL_APB_IOPLL_CFG_RES_MASK | CRL_APB_IOPLL_CFG_CP_MASK | CRL_APB_IOPLL_CFG_LFHF_MASK | CRL_APB_IOPLL_CFG_LOCK_CNT_MASK | CRL_APB_IOPLL_CFG_LOCK_DLY_MASK |  0 );
+
+		RegVal = ((0x0000000CU << CRL_APB_IOPLL_CFG_RES_SHIFT
+			| 0x00000003U << CRL_APB_IOPLL_CFG_CP_SHIFT
+			| 0x00000003U << CRL_APB_IOPLL_CFG_LFHF_SHIFT
+			| 0x00000339U << CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT
+			| 0x0000003FU << CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E672C6CU);
+	/*############################################################################################################################ */
+
+		// : UPDATE FB_DIV
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		PSU_CRL_APB_IOPLL_CTRL_PRE_SRC                                                  0x0
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRL_APB_IOPLL_CTRL_FBDIV                                                    0x2d
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRL_APB_IOPLL_CTRL_DIV2                                                     0x0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00717F00U ,0x00002D00U)  
+		RegMask = (CRL_APB_IOPLL_CTRL_PRE_SRC_MASK | CRL_APB_IOPLL_CTRL_FBDIV_MASK | CRL_APB_IOPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT
+			| 0x0000002DU << CRL_APB_IOPLL_CTRL_FBDIV_SHIFT
+			| 0x00000000U << CRL_APB_IOPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00717F00U ,0x00002D00U);
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000008U)  
+		RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRL_APB_IOPLL_CTRL_RESET                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000001U)  
+		RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRL_APB_IOPLL_CTRL_RESET                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000001U ,0x00000000U)  
+		RegMask = (CRL_APB_IOPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFF5E0040

+
+		IOPLL is locked
+		PSU_CRL_APB_PLL_STATUS_IOPLL_LOCK                                               1
+		(OFFSET, MASK, VALUE)      (0XFF5E0040, 0x00000001U ,0x00000001U)  */
+		mask_poll(CRL_APB_PLL_STATUS_OFFSET,0x00000001U);
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : IOPLL_CTRL @ 0XFF5E0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOPLL_CTRL_BYPASS                                                   0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFF5E0020, 0x00000008U ,0x00000000U)  
+		RegMask = (CRL_APB_IOPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_IOPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : IOPLL_TO_FPD_CTRL @ 0XFF5E0044

+
+		Divisor value for this clock.
+		PSU_CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0                                          0x3
+
+		Control for a clock that will be generated in the LPD, but used in the FPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFF5E0044, 0x00003F00U ,0x00000300U)  
+		RegMask = (CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000003U << CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		// : IOPLL FRAC CFG
+		/*Register : IOPLL_FRAC_CFG @ 0XFF5E0028

+
+		Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.
+		PSU_CRL_APB_IOPLL_FRAC_CFG_ENABLED                                              0x0
+
+		Fractional value for the Feedback value.
+		PSU_CRL_APB_IOPLL_FRAC_CFG_DATA                                                 0x0
+
+		Fractional control for the PLL
+		(OFFSET, MASK, VALUE)      (0XFF5E0028, 0x8000FFFFU ,0x00000000U)  
+		RegMask = (CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK | CRL_APB_IOPLL_FRAC_CFG_DATA_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT
+			| 0x00000000U << CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : APU_PLL INIT
+		/*Register : APLL_CFG @ 0XFD1A0024

+
+		PLL loop filter resistor control
+		PSU_CRF_APB_APLL_CFG_RES                                                        0x2
+
+		PLL charge pump control
+		PSU_CRF_APB_APLL_CFG_CP                                                         0x3
+
+		PLL loop filter high frequency capacitor control
+		PSU_CRF_APB_APLL_CFG_LFHF                                                       0x3
+
+		Lock circuit counter setting
+		PSU_CRF_APB_APLL_CFG_LOCK_CNT                                                   0x258
+
+		Lock circuit configuration settings for lock windowsize
+		PSU_CRF_APB_APLL_CFG_LOCK_DLY                                                   0x3f
+
+		Helper data. Values are to be looked up in a table from Data Sheet
+		(OFFSET, MASK, VALUE)      (0XFD1A0024, 0xFE7FEDEFU ,0x7E4B0C62U)  
+		RegMask = (CRF_APB_APLL_CFG_RES_MASK | CRF_APB_APLL_CFG_CP_MASK | CRF_APB_APLL_CFG_LFHF_MASK | CRF_APB_APLL_CFG_LOCK_CNT_MASK | CRF_APB_APLL_CFG_LOCK_DLY_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_APLL_CFG_RES_SHIFT
+			| 0x00000003U << CRF_APB_APLL_CFG_CP_SHIFT
+			| 0x00000003U << CRF_APB_APLL_CFG_LFHF_SHIFT
+			| 0x00000258U << CRF_APB_APLL_CFG_LOCK_CNT_SHIFT
+			| 0x0000003FU << CRF_APB_APLL_CFG_LOCK_DLY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
+	/*############################################################################################################################ */
+
+		// : UPDATE FB_DIV
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		PSU_CRF_APB_APLL_CTRL_PRE_SRC                                                   0x0
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_APLL_CTRL_FBDIV                                                     0x42
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_APLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00717F00U ,0x00014200U)  
+		RegMask = (CRF_APB_APLL_CTRL_PRE_SRC_MASK | CRF_APB_APLL_CTRL_FBDIV_MASK | CRF_APB_APLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_PRE_SRC_SHIFT
+			| 0x00000042U << CRF_APB_APLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_APLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00717F00U ,0x00014200U);
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_APLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000008U)  
+		RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_APLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000001U)  
+		RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_APLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_APLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000001U ,0x00000000U)  
+		RegMask = (CRF_APB_APLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044

+
+		APLL is locked
+		PSU_CRF_APB_PLL_STATUS_APLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000001U ,0x00000001U)  */
+		mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000001U);
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : APLL_CTRL @ 0XFD1A0020

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_APLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0020, 0x00000008U ,0x00000000U)  
+		RegMask = (CRF_APB_APLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_APLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : APLL_TO_LPD_CTRL @ 0XFD1A0048

+
+		Divisor value for this clock.
+		PSU_CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0                                           0x3
+
+		Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A0048, 0x00003F00U ,0x00000300U)  
+		RegMask = (CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000003U << CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		// : APLL FRAC CFG
+		/*Register : APLL_FRAC_CFG @ 0XFD1A0028

+
+		Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.
+		PSU_CRF_APB_APLL_FRAC_CFG_ENABLED                                               0x0
+
+		Fractional value for the Feedback value.
+		PSU_CRF_APB_APLL_FRAC_CFG_DATA                                                  0x0
+
+		Fractional control for the PLL
+		(OFFSET, MASK, VALUE)      (0XFD1A0028, 0x8000FFFFU ,0x00000000U)  
+		RegMask = (CRF_APB_APLL_FRAC_CFG_ENABLED_MASK | CRF_APB_APLL_FRAC_CFG_DATA_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT
+			| 0x00000000U << CRF_APB_APLL_FRAC_CFG_DATA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_APLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : DDR_PLL INIT
+		/*Register : DPLL_CFG @ 0XFD1A0030

+
+		PLL loop filter resistor control
+		PSU_CRF_APB_DPLL_CFG_RES                                                        0x2
+
+		PLL charge pump control
+		PSU_CRF_APB_DPLL_CFG_CP                                                         0x3
+
+		PLL loop filter high frequency capacitor control
+		PSU_CRF_APB_DPLL_CFG_LFHF                                                       0x3
+
+		Lock circuit counter setting
+		PSU_CRF_APB_DPLL_CFG_LOCK_CNT                                                   0x258
+
+		Lock circuit configuration settings for lock windowsize
+		PSU_CRF_APB_DPLL_CFG_LOCK_DLY                                                   0x3f
+
+		Helper data. Values are to be looked up in a table from Data Sheet
+		(OFFSET, MASK, VALUE)      (0XFD1A0030, 0xFE7FEDEFU ,0x7E4B0C62U)  
+		RegMask = (CRF_APB_DPLL_CFG_RES_MASK | CRF_APB_DPLL_CFG_CP_MASK | CRF_APB_DPLL_CFG_LFHF_MASK | CRF_APB_DPLL_CFG_LOCK_CNT_MASK | CRF_APB_DPLL_CFG_LOCK_DLY_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DPLL_CFG_RES_SHIFT
+			| 0x00000003U << CRF_APB_DPLL_CFG_CP_SHIFT
+			| 0x00000003U << CRF_APB_DPLL_CFG_LFHF_SHIFT
+			| 0x00000258U << CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT
+			| 0x0000003FU << CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E4B0C62U);
+	/*############################################################################################################################ */
+
+		// : UPDATE FB_DIV
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		PSU_CRF_APB_DPLL_CTRL_PRE_SRC                                                   0x0
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_DPLL_CTRL_FBDIV                                                     0x40
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_DPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00717F00U ,0x00014000U)  
+		RegMask = (CRF_APB_DPLL_CTRL_PRE_SRC_MASK | CRF_APB_DPLL_CTRL_FBDIV_MASK | CRF_APB_DPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT
+			| 0x00000040U << CRF_APB_DPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_DPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00717F00U ,0x00014000U);
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000008U)  
+		RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_DPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000001U)  
+		RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_DPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_DPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000001U ,0x00000000U)  
+		RegMask = (CRF_APB_DPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044

+
+		DPLL is locked
+		PSU_CRF_APB_PLL_STATUS_DPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000002U ,0x00000002U)  */
+		mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000002U);
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : DPLL_CTRL @ 0XFD1A002C

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A002C, 0x00000008U ,0x00000000U)  
+		RegMask = (CRF_APB_DPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_DPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DPLL_TO_LPD_CTRL @ 0XFD1A004C

+
+		Divisor value for this clock.
+		PSU_CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
+
+		Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A004C, 0x00003F00U ,0x00000300U)  
+		RegMask = (CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000003U << CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		// : DPLL FRAC CFG
+		/*Register : DPLL_FRAC_CFG @ 0XFD1A0034

+
+		Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.
+		PSU_CRF_APB_DPLL_FRAC_CFG_ENABLED                                               0x0
+
+		Fractional value for the Feedback value.
+		PSU_CRF_APB_DPLL_FRAC_CFG_DATA                                                  0x0
+
+		Fractional control for the PLL
+		(OFFSET, MASK, VALUE)      (0XFD1A0034, 0x8000FFFFU ,0x00000000U)  
+		RegMask = (CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_DPLL_FRAC_CFG_DATA_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT
+			| 0x00000000U << CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : VIDEO_PLL INIT
+		/*Register : VPLL_CFG @ 0XFD1A003C

+
+		PLL loop filter resistor control
+		PSU_CRF_APB_VPLL_CFG_RES                                                        0x2
+
+		PLL charge pump control
+		PSU_CRF_APB_VPLL_CFG_CP                                                         0x3
+
+		PLL loop filter high frequency capacitor control
+		PSU_CRF_APB_VPLL_CFG_LFHF                                                       0x3
+
+		Lock circuit counter setting
+		PSU_CRF_APB_VPLL_CFG_LOCK_CNT                                                   0x28a
+
+		Lock circuit configuration settings for lock windowsize
+		PSU_CRF_APB_VPLL_CFG_LOCK_DLY                                                   0x3f
+
+		Helper data. Values are to be looked up in a table from Data Sheet
+		(OFFSET, MASK, VALUE)      (0XFD1A003C, 0xFE7FEDEFU ,0x7E514C62U)  
+		RegMask = (CRF_APB_VPLL_CFG_RES_MASK | CRF_APB_VPLL_CFG_CP_MASK | CRF_APB_VPLL_CFG_LFHF_MASK | CRF_APB_VPLL_CFG_LOCK_CNT_MASK | CRF_APB_VPLL_CFG_LOCK_DLY_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_VPLL_CFG_RES_SHIFT
+			| 0x00000003U << CRF_APB_VPLL_CFG_CP_SHIFT
+			| 0x00000003U << CRF_APB_VPLL_CFG_LFHF_SHIFT
+			| 0x0000028AU << CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT
+			| 0x0000003FU << CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CFG_OFFSET ,0xFE7FEDEFU ,0x7E514C62U);
+	/*############################################################################################################################ */
+
+		// : UPDATE FB_DIV
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source
+		PSU_CRF_APB_VPLL_CTRL_PRE_SRC                                                   0x0
+
+		The integer portion of the feedback divider to the PLL
+		PSU_CRF_APB_VPLL_CTRL_FBDIV                                                     0x39
+
+		This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency
+		PSU_CRF_APB_VPLL_CTRL_DIV2                                                      0x1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00717F00U ,0x00013900U)  
+		RegMask = (CRF_APB_VPLL_CTRL_PRE_SRC_MASK | CRF_APB_VPLL_CTRL_FBDIV_MASK | CRF_APB_VPLL_CTRL_DIV2_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT
+			| 0x00000039U << CRF_APB_VPLL_CTRL_FBDIV_SHIFT
+			| 0x00000001U << CRF_APB_VPLL_CTRL_DIV2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00717F00U ,0x00013900U);
+	/*############################################################################################################################ */
+
+		// : BY PASS PLL
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000008U)  
+		RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : ASSERT RESET
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_VPLL_CTRL_RESET                                                     1
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000001U)  
+		RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_VPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : DEASSERT RESET
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.
+		PSU_CRF_APB_VPLL_CTRL_RESET                                                     0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000001U ,0x00000000U)  
+		RegMask = (CRF_APB_VPLL_CTRL_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL STATUS
+		/*Register : PLL_STATUS @ 0XFD1A0044

+
+		VPLL is locked
+		PSU_CRF_APB_PLL_STATUS_VPLL_LOCK                                                1
+		(OFFSET, MASK, VALUE)      (0XFD1A0044, 0x00000004U ,0x00000004U)  */
+		mask_poll(CRF_APB_PLL_STATUS_OFFSET,0x00000004U);
+
+	/*############################################################################################################################ */
+
+		// : REMOVE PLL BY PASS
+		/*Register : VPLL_CTRL @ 0XFD1A0038

+
+		Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_VPLL_CTRL_BYPASS                                                    0
+
+		PLL Basic Control
+		(OFFSET, MASK, VALUE)      (0XFD1A0038, 0x00000008U ,0x00000000U)  
+		RegMask = (CRF_APB_VPLL_CTRL_BYPASS_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_VPLL_CTRL_BYPASS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_CTRL_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : VPLL_TO_LPD_CTRL @ 0XFD1A0050

+
+		Divisor value for this clock.
+		PSU_CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0                                           0x3
+
+		Control for a clock that will be generated in the FPD, but used in the LPD as a clock source for the peripheral clock muxes.
+		(OFFSET, MASK, VALUE)      (0XFD1A0050, 0x00003F00U ,0x00000300U)  
+		RegMask = (CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000003U << CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_TO_LPD_CTRL_OFFSET ,0x00003F00U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		// : VIDEO FRAC CFG
+		/*Register : VPLL_FRAC_CFG @ 0XFD1A0040

+
+		Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.
+		PSU_CRF_APB_VPLL_FRAC_CFG_ENABLED                                               0x1
+
+		Fractional value for the Feedback value.
+		PSU_CRF_APB_VPLL_FRAC_CFG_DATA                                                  0x820c
+
+		Fractional control for the PLL
+		(OFFSET, MASK, VALUE)      (0XFD1A0040, 0x8000FFFFU ,0x8000820CU)  
+		RegMask = (CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK | CRF_APB_VPLL_FRAC_CFG_DATA_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT
+			| 0x0000820CU << CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_VPLL_FRAC_CFG_OFFSET ,0x8000FFFFU ,0x8000820CU);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_clock_init_data() {
+		// : CLOCK CONTROL SLCR REGISTER
+		/*Register : GEM0_REF_CTRL @ 0XFF5E0050

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM0_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM0_REF_CTRL_DIVISOR0                                              0x8
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0050, 0x063F3F07U ,0x06010800U)  
+		RegMask = (CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_CLKACT_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000008U << CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_GEM0_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
+	/*############################################################################################################################ */
+
+		/*Register : GEM1_REF_CTRL @ 0XFF5E0054

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM1_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM1_REF_CTRL_DIVISOR0                                              0x8
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0054, 0x063F3F07U ,0x06010800U)  
+		RegMask = (CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_CLKACT_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000008U << CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_GEM1_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
+	/*############################################################################################################################ */
+
+		/*Register : GEM2_REF_CTRL @ 0XFF5E0058

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM2_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM2_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM2_REF_CTRL_DIVISOR0                                              0x8
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM2_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0058, 0x063F3F07U ,0x06010800U)  
+		RegMask = (CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_CLKACT_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000008U << CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_GEM2_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010800U);
+	/*############################################################################################################################ */
+
+		/*Register : GEM3_REF_CTRL @ 0XFF5E005C

+
+		Clock active for the RX channel
+		PSU_CRL_APB_GEM3_REF_CTRL_RX_CLKACT                                             0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM3_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_GEM3_REF_CTRL_DIVISOR0                                              0xc
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM3_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E005C, 0x063F3F07U ,0x06010C00U)  
+		RegMask = (CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_CLKACT_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000CU << CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_GEM3_REF_CTRL_OFFSET ,0x063F3F07U ,0x06010C00U);
+	/*############################################################################################################################ */
+
+		/*Register : GEM_TSU_REF_CTRL @ 0XFF5E0100

+
+		6 bit divider
+		PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0                                           0x6
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_GEM_TSU_REF_CTRL_SRCSEL                                             0x2
+
+		6 bit divider
+		PSU_CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1                                           0x1
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_GEM_TSU_REF_CTRL_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0100, 0x013F3F07U ,0x01010602U)  
+		RegMask = (CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK | CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK | CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK | CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000006U << CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000001U << CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_GEM_TSU_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U);
+	/*############################################################################################################################ */
+
+		/*Register : USB0_BUS_REF_CTRL @ 0XFF5E0060

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_CLKACT                                            0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1                                          0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0                                          0x6
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_USB0_BUS_REF_CTRL_SRCSEL                                            0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0060, 0x023F3F07U ,0x02010600U)  
+		RegMask = (CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000006U << CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_USB0_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010600U);
+	/*############################################################################################################################ */
+
+		/*Register : USB1_BUS_REF_CTRL @ 0XFF5E0064

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_USB1_BUS_REF_CTRL_CLKACT                                            0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1                                          0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0                                          0x4
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_USB1_BUS_REF_CTRL_SRCSEL                                            0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0064, 0x023F3F07U ,0x02010400U)  
+		RegMask = (CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK | CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000004U << CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_USB1_BUS_REF_CTRL_OFFSET ,0x023F3F07U ,0x02010400U);
+	/*############################################################################################################################ */
+
+		/*Register : USB3_DUAL_REF_CTRL @ 0XFF5E004C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_CLKACT                                           0x1
+
+		6 bit divider
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1                                         0xf
+
+		6 bit divider
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0                                         0x5
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL                                           0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E004C, 0x023F3F07U ,0x020F0500U)  
+		RegMask = (CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK | CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK | CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT
+			| 0x0000000FU << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000005U << CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_USB3_DUAL_REF_CTRL_OFFSET ,0x023F3F07U ,0x020F0500U);
+	/*############################################################################################################################ */
+
+		/*Register : QSPI_REF_CTRL @ 0XFF5E0068

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_QSPI_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_QSPI_REF_CTRL_DIVISOR0                                              0xc
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_QSPI_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0068, 0x013F3F07U ,0x01010C00U)  
+		RegMask = (CRL_APB_QSPI_REF_CTRL_CLKACT_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK | CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK | CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000CU << CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_QSPI_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010C00U);
+	/*############################################################################################################################ */
+
+		/*Register : SDIO0_REF_CTRL @ 0XFF5E006C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SDIO0_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR1                                             0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO0_REF_CTRL_DIVISOR0                                             0x7
+
+		000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SDIO0_REF_CTRL_SRCSEL                                               0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E006C, 0x013F3F07U ,0x01010702U)  
+		RegMask = (CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000007U << CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_SDIO0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
+	/*############################################################################################################################ */
+
+		/*Register : SDIO1_REF_CTRL @ 0XFF5E0070

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SDIO1_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR1                                             0x1
+
+		6 bit divider
+		PSU_CRL_APB_SDIO1_REF_CTRL_DIVISOR0                                             0x6
+
+		000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SDIO1_REF_CTRL_SRCSEL                                               0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0070, 0x013F3F07U ,0x01010602U)  
+		RegMask = (CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000006U << CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_SDIO1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010602U);
+	/*############################################################################################################################ */
+
+		/*Register : SDIO_CLK_CTRL @ 0XFF18030C

+
+		MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]
+		PSU_IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL                                     0
+
+		SoC Debug Clock Control
+		(OFFSET, MASK, VALUE)      (0XFF18030C, 0x00020000U ,0x00000000U)  
+		RegMask = (IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_SDIO_CLK_CTRL_OFFSET ,0x00020000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : UART0_REF_CTRL @ 0XFF5E0074

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_UART0_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART0_REF_CTRL_DIVISOR1                                             0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART0_REF_CTRL_DIVISOR0                                             0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_UART0_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0074, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_UART0_REF_CTRL_CLKACT_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_UART0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : UART1_REF_CTRL @ 0XFF5E0078

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_UART1_REF_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART1_REF_CTRL_DIVISOR1                                             0x1
+
+		6 bit divider
+		PSU_CRL_APB_UART1_REF_CTRL_DIVISOR0                                             0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_UART1_REF_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0078, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_UART1_REF_CTRL_CLKACT_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK | CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK | CRL_APB_UART1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_UART1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : I2C0_REF_CTRL @ 0XFF5E0120

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_I2C0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C0_REF_CTRL_DIVISOR0                                              0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_I2C0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0120, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_I2C0_REF_CTRL_CLKACT_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_I2C0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : I2C1_REF_CTRL @ 0XFF5E0124

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_I2C1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_I2C1_REF_CTRL_DIVISOR0                                              0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_I2C1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0124, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_I2C1_REF_CTRL_CLKACT_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK | CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK | CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_I2C1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : SPI0_REF_CTRL @ 0XFF5E007C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SPI0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI0_REF_CTRL_DIVISOR0                                              0x7
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SPI0_REF_CTRL_SRCSEL                                                0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E007C, 0x013F3F07U ,0x01010702U)  
+		RegMask = (CRL_APB_SPI0_REF_CTRL_CLKACT_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000007U << CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_SPI0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
+	/*############################################################################################################################ */
+
+		/*Register : SPI1_REF_CTRL @ 0XFF5E0080

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_SPI1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_SPI1_REF_CTRL_DIVISOR0                                              0x7
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_SPI1_REF_CTRL_SRCSEL                                                0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0080, 0x013F3F07U ,0x01010702U)  
+		RegMask = (CRL_APB_SPI1_REF_CTRL_CLKACT_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK | CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK | CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000007U << CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_SPI1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010702U);
+	/*############################################################################################################################ */
+
+		/*Register : CAN0_REF_CTRL @ 0XFF5E0084

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CAN0_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN0_REF_CTRL_DIVISOR0                                              0xa
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CAN0_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0084, 0x013F3F07U ,0x01010A00U)  
+		RegMask = (CRL_APB_CAN0_REF_CTRL_CLKACT_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000AU << CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_CAN0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010A00U);
+	/*############################################################################################################################ */
+
+		/*Register : CAN1_REF_CTRL @ 0XFF5E0088

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CAN1_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_CAN1_REF_CTRL_DIVISOR0                                              0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CAN1_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0088, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_CAN1_REF_CTRL_CLKACT_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK | CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK | CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_CAN1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : CPU_R5_CTRL @ 0XFF5E0090

+
+		Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
+		d lead to system hang
+		PSU_CRL_APB_CPU_R5_CTRL_CLKACT                                                  0x1
+
+		6 bit divider
+		PSU_CRL_APB_CPU_R5_CTRL_DIVISOR0                                                0x3
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CPU_R5_CTRL_SRCSEL                                                  0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0090, 0x01003F07U ,0x01000302U)  
+		RegMask = (CRL_APB_CPU_R5_CTRL_CLKACT_MASK | CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK | CRL_APB_CPU_R5_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT
+			| 0x00000003U << CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_CPU_R5_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
+	/*############################################################################################################################ */
+
+		/*Register : IOU_SWITCH_CTRL @ 0XFF5E009C

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_IOU_SWITCH_CTRL_CLKACT                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_IOU_SWITCH_CTRL_DIVISOR0                                            0x6
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_IOU_SWITCH_CTRL_SRCSEL                                              0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E009C, 0x01003F07U ,0x01000602U)  
+		RegMask = (CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK | CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT
+			| 0x00000006U << CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_IOU_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
+	/*############################################################################################################################ */
+
+		/*Register : CSU_PLL_CTRL @ 0XFF5E00A0

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_CSU_PLL_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_CSU_PLL_CTRL_DIVISOR0                                               0x3
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_CSU_PLL_CTRL_SRCSEL                                                 0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00A0, 0x01003F07U ,0x01000302U)  
+		RegMask = (CRL_APB_CSU_PLL_CTRL_CLKACT_MASK | CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK | CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT
+			| 0x00000003U << CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_CSU_PLL_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
+	/*############################################################################################################################ */
+
+		/*Register : PCAP_CTRL @ 0XFF5E00A4

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PCAP_CTRL_CLKACT                                                    0x1
+
+		6 bit divider
+		PSU_CRL_APB_PCAP_CTRL_DIVISOR0                                                  0x6
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PCAP_CTRL_SRCSEL                                                    0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00A4, 0x01003F07U ,0x01000602U)  
+		RegMask = (CRL_APB_PCAP_CTRL_CLKACT_MASK | CRL_APB_PCAP_CTRL_DIVISOR0_MASK | CRL_APB_PCAP_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_PCAP_CTRL_CLKACT_SHIFT
+			| 0x00000006U << CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_PCAP_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_PCAP_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
+	/*############################################################################################################################ */
+
+		/*Register : LPD_SWITCH_CTRL @ 0XFF5E00A8

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_LPD_SWITCH_CTRL_CLKACT                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_LPD_SWITCH_CTRL_DIVISOR0                                            0x3
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_LPD_SWITCH_CTRL_SRCSEL                                              0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00A8, 0x01003F07U ,0x01000302U)  
+		RegMask = (CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK | CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK | CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT
+			| 0x00000003U << CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_LPD_SWITCH_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
+	/*############################################################################################################################ */
+
+		/*Register : LPD_LSBUS_CTRL @ 0XFF5E00AC

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_LPD_LSBUS_CTRL_CLKACT                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_LPD_LSBUS_CTRL_DIVISOR0                                             0xf
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_LPD_LSBUS_CTRL_SRCSEL                                               0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00AC, 0x01003F07U ,0x01000F02U)  
+		RegMask = (CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK | CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK | CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT
+			| 0x0000000FU << CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_LPD_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000F02U);
+	/*############################################################################################################################ */
+
+		/*Register : DBG_LPD_CTRL @ 0XFF5E00B0

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_DBG_LPD_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_DBG_LPD_CTRL_DIVISOR0                                               0x6
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_DBG_LPD_CTRL_SRCSEL                                                 0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B0, 0x01003F07U ,0x01000602U)  
+		RegMask = (CRL_APB_DBG_LPD_CTRL_CLKACT_MASK | CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK | CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT
+			| 0x00000006U << CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_DBG_LPD_CTRL_OFFSET ,0x01003F07U ,0x01000602U);
+	/*############################################################################################################################ */
+
+		/*Register : NAND_REF_CTRL @ 0XFF5E00B4

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_NAND_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_NAND_REF_CTRL_DIVISOR1                                              0x1
+
+		6 bit divider
+		PSU_CRL_APB_NAND_REF_CTRL_DIVISOR0                                              0xa
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_NAND_REF_CTRL_SRCSEL                                                0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B4, 0x013F3F07U ,0x01010A00U)  
+		RegMask = (CRL_APB_NAND_REF_CTRL_CLKACT_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK | CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK | CRL_APB_NAND_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000AU << CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_NAND_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010A00U);
+	/*############################################################################################################################ */
+
+		/*Register : ADMA_REF_CTRL @ 0XFF5E00B8

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_ADMA_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRL_APB_ADMA_REF_CTRL_DIVISOR0                                              0x3
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_ADMA_REF_CTRL_SRCSEL                                                0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00B8, 0x01003F07U ,0x01000302U)  
+		RegMask = (CRL_APB_ADMA_REF_CTRL_CLKACT_MASK | CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK | CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT
+			| 0x00000003U << CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_ADMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000302U);
+	/*############################################################################################################################ */
+
+		/*Register : PL0_REF_CTRL @ 0XFF5E00C0

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PL0_REF_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL0_REF_CTRL_DIVISOR1                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL0_REF_CTRL_DIVISOR0                                               0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PL0_REF_CTRL_SRCSEL                                                 0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00C0, 0x013F3F07U ,0x01010F00U)  
+		RegMask = (CRL_APB_PL0_REF_CTRL_CLKACT_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL0_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_PL0_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010F00U);
+	/*############################################################################################################################ */
+
+		/*Register : PL1_REF_CTRL @ 0XFF5E00C4

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PL1_REF_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL1_REF_CTRL_DIVISOR1                                               0x4
+
+		6 bit divider
+		PSU_CRL_APB_PL1_REF_CTRL_DIVISOR0                                               0xf
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PL1_REF_CTRL_SRCSEL                                                 0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00C4, 0x013F3F07U ,0x01040F00U)  
+		RegMask = (CRL_APB_PL1_REF_CTRL_CLKACT_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL1_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT
+			| 0x00000004U << CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000000FU << CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_PL1_REF_CTRL_OFFSET ,0x013F3F07U ,0x01040F00U);
+	/*############################################################################################################################ */
+
+		/*Register : PL2_REF_CTRL @ 0XFF5E00C8

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PL2_REF_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL2_REF_CTRL_DIVISOR1                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL2_REF_CTRL_DIVISOR0                                               0x4
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PL2_REF_CTRL_SRCSEL                                                 0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00C8, 0x013F3F07U ,0x01010402U)  
+		RegMask = (CRL_APB_PL2_REF_CTRL_CLKACT_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL2_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000004U << CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_PL2_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010402U);
+	/*############################################################################################################################ */
+
+		/*Register : PL3_REF_CTRL @ 0XFF5E00CC

+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_PL3_REF_CTRL_CLKACT                                                 0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL3_REF_CTRL_DIVISOR1                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_PL3_REF_CTRL_DIVISOR0                                               0x3
+
+		000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_PL3_REF_CTRL_SRCSEL                                                 0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E00CC, 0x013F3F07U ,0x01010302U)  
+		RegMask = (CRL_APB_PL3_REF_CTRL_CLKACT_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK | CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK | CRL_APB_PL3_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000003U << CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_PL3_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010302U);
+	/*############################################################################################################################ */
+
+		/*Register : AMS_REF_CTRL @ 0XFF5E0108

+
+		6 bit divider
+		PSU_CRL_APB_AMS_REF_CTRL_DIVISOR1                                               0x1
+
+		6 bit divider
+		PSU_CRL_APB_AMS_REF_CTRL_DIVISOR0                                               0x1d
+
+		000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_AMS_REF_CTRL_SRCSEL                                                 0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_AMS_REF_CTRL_CLKACT                                                 0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0108, 0x013F3F07U ,0x01011D02U)  
+		RegMask = (CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK | CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK | CRL_APB_AMS_REF_CTRL_SRCSEL_MASK | CRL_APB_AMS_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT
+			| 0x0000001DU << CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_AMS_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011D02U);
+	/*############################################################################################################################ */
+
+		/*Register : DLL_REF_CTRL @ 0XFF5E0104

+
+		000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
+		is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_DLL_REF_CTRL_SRCSEL                                                 0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0104, 0x00000007U ,0x00000000U)  
+		RegMask = (CRL_APB_DLL_REF_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_DLL_REF_CTRL_OFFSET ,0x00000007U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : TIMESTAMP_REF_CTRL @ 0XFF5E0128

+
+		6 bit divider
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0                                         0xf
+
+		1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 
+		 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL                                           0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT                                           0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFF5E0128, 0x01003F07U ,0x01000F00U)  
+		RegMask = (CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK | CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK | CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x0000000FU << CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_TIMESTAMP_REF_CTRL_OFFSET ,0x01003F07U ,0x01000F00U);
+	/*############################################################################################################################ */
+
+		/*Register : SATA_REF_CTRL @ 0XFD1A00A0

+
+		000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_SATA_REF_CTRL_SRCSEL                                                0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_SATA_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRF_APB_SATA_REF_CTRL_DIVISOR0                                              0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00A0, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_SATA_REF_CTRL_SRCSEL_MASK | CRF_APB_SATA_REF_CTRL_CLKACT_MASK | CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_SATA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : PCIE_REF_CTRL @ 0XFD1A00B4

+
+		000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
+		es of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_PCIE_REF_CTRL_SRCSEL                                                0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_PCIE_REF_CTRL_CLKACT                                                0x1
+
+		6 bit divider
+		PSU_CRF_APB_PCIE_REF_CTRL_DIVISOR0                                              0x2
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00B4, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK | CRF_APB_PCIE_REF_CTRL_CLKACT_MASK | CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT
+			| 0x00000002U << CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_PCIE_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : DP_VIDEO_REF_CTRL @ 0XFD1A0070

+
+		6 bit divider
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1                                          0x1
+
+		6 bit divider
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0                                          0x3
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 
+		ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL                                            0x3
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_VIDEO_REF_CTRL_CLKACT                                            0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0070, 0x013F3F07U ,0x01010303U)  
+		RegMask = (CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000003U << CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DP_VIDEO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01010303U);
+	/*############################################################################################################################ */
+
+		/*Register : DP_AUDIO_REF_CTRL @ 0XFD1A0074

+
+		6 bit divider
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1                                          0x1
+
+		6 bit divider
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0                                          0x27
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 
+		ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL                                            0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_AUDIO_REF_CTRL_CLKACT                                            0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0074, 0x013F3F07U ,0x01012700U)  
+		RegMask = (CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000027U << CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DP_AUDIO_REF_CTRL_OFFSET ,0x013F3F07U ,0x01012700U);
+	/*############################################################################################################################ */
+
+		/*Register : DP_STC_REF_CTRL @ 0XFD1A007C

+
+		6 bit divider
+		PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR1                                            0x1
+
+		6 bit divider
+		PSU_CRF_APB_DP_STC_REF_CTRL_DIVISOR0                                            0x11
+
+		000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
+		e new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DP_STC_REF_CTRL_SRCSEL                                              0x3
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DP_STC_REF_CTRL_CLKACT                                              0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A007C, 0x013F3F07U ,0x01011103U)  
+		RegMask = (CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK | CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK | CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK | CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT
+			| 0x00000011U << CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000003U << CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DP_STC_REF_CTRL_OFFSET ,0x013F3F07U ,0x01011103U);
+	/*############################################################################################################################ */
+
+		/*Register : ACPU_CTRL @ 0XFD1A0060

+
+		6 bit divider
+		PSU_CRF_APB_ACPU_CTRL_DIVISOR0                                                  0x1
+
+		000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_ACPU_CTRL_SRCSEL                                                    0x0
+
+		Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock
+		PSU_CRF_APB_ACPU_CTRL_CLKACT_HALF                                               0x1
+
+		Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
+		 to the entire APU
+		PSU_CRF_APB_ACPU_CTRL_CLKACT_FULL                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0060, 0x03003F07U ,0x03000100U)  
+		RegMask = (CRF_APB_ACPU_CTRL_DIVISOR0_MASK | CRF_APB_ACPU_CTRL_SRCSEL_MASK | CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK | CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_ACPU_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT
+			| 0x00000001U << CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_ACPU_CTRL_OFFSET ,0x03003F07U ,0x03000100U);
+	/*############################################################################################################################ */
+
+		/*Register : DBG_TRACE_CTRL @ 0XFD1A0064

+
+		6 bit divider
+		PSU_CRF_APB_DBG_TRACE_CTRL_DIVISOR0                                             0x2
+
+		000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_TRACE_CTRL_SRCSEL                                               0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DBG_TRACE_CTRL_CLKACT                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0064, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK | CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DBG_TRACE_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : DBG_FPD_CTRL @ 0XFD1A0068

+
+		6 bit divider
+		PSU_CRF_APB_DBG_FPD_CTRL_DIVISOR0                                               0x2
+
+		000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_FPD_CTRL_SRCSEL                                                 0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DBG_FPD_CTRL_CLKACT                                                 0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0068, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK | CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK | CRF_APB_DBG_FPD_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DBG_FPD_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : DDR_CTRL @ 0XFD1A0080

+
+		6 bit divider
+		PSU_CRF_APB_DDR_CTRL_DIVISOR0                                                   0x2
+
+		000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This 
+		s not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DDR_CTRL_SRCSEL                                                     0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0080, 0x00003F07U ,0x00000200U)  
+		RegMask = (CRF_APB_DDR_CTRL_DIVISOR0_MASK | CRF_APB_DDR_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DDR_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DDR_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DDR_CTRL_OFFSET ,0x00003F07U ,0x00000200U);
+	/*############################################################################################################################ */
+
+		/*Register : GPU_REF_CTRL @ 0XFD1A0084

+
+		6 bit divider
+		PSU_CRF_APB_GPU_REF_CTRL_DIVISOR0                                               0x1
+
+		000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GPU_REF_CTRL_SRCSEL                                                 0x0
+
+		Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).
+		PSU_CRF_APB_GPU_REF_CTRL_CLKACT                                                 0x1
+
+		Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
+		PSU_CRF_APB_GPU_REF_CTRL_PP0_CLKACT                                             0x1
+
+		Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor
+		PSU_CRF_APB_GPU_REF_CTRL_PP1_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A0084, 0x07003F07U ,0x07000100U)  
+		RegMask = (CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK | CRF_APB_GPU_REF_CTRL_SRCSEL_MASK | CRF_APB_GPU_REF_CTRL_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK | CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT
+			| 0x00000001U << CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_GPU_REF_CTRL_OFFSET ,0x07003F07U ,0x07000100U);
+	/*############################################################################################################################ */
+
+		/*Register : GDMA_REF_CTRL @ 0XFD1A00B8

+
+		6 bit divider
+		PSU_CRF_APB_GDMA_REF_CTRL_DIVISOR0                                              0x2
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GDMA_REF_CTRL_SRCSEL                                                0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_GDMA_REF_CTRL_CLKACT                                                0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00B8, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_GDMA_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_GDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : DPDMA_REF_CTRL @ 0XFD1A00BC

+
+		6 bit divider
+		PSU_CRF_APB_DPDMA_REF_CTRL_DIVISOR0                                             0x2
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DPDMA_REF_CTRL_SRCSEL                                               0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_DPDMA_REF_CTRL_CLKACT                                               0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00BC, 0x01003F07U ,0x01000200U)  
+		RegMask = (CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK | CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK | CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DPDMA_REF_CTRL_OFFSET ,0x01003F07U ,0x01000200U);
+	/*############################################################################################################################ */
+
+		/*Register : TOPSW_MAIN_CTRL @ 0XFD1A00C0

+
+		6 bit divider
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0                                            0x2
+
+		000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_SRCSEL                                              0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_TOPSW_MAIN_CTRL_CLKACT                                              0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C0, 0x01003F07U ,0x01000202U)  
+		RegMask = (CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_TOPSW_MAIN_CTRL_OFFSET ,0x01003F07U ,0x01000202U);
+	/*############################################################################################################################ */
+
+		/*Register : TOPSW_LSBUS_CTRL @ 0XFD1A00C4

+
+		6 bit divider
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0                                           0x5
+
+		000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL                                             0x2
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_TOPSW_LSBUS_CTRL_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C4, 0x01003F07U ,0x01000502U)  
+		RegMask = (CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK | CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK | CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000005U << CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT
+			| 0x00000002U << CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_TOPSW_LSBUS_CTRL_OFFSET ,0x01003F07U ,0x01000502U);
+	/*############################################################################################################################ */
+
+		/*Register : GTGREF0_REF_CTRL @ 0XFD1A00C8

+
+		6 bit divider
+		PSU_CRF_APB_GTGREF0_REF_CTRL_DIVISOR0                                           0x4
+
+		000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_GTGREF0_REF_CTRL_SRCSEL                                             0x0
+
+		Clock active signal. Switch to 0 to disable the clock
+		PSU_CRF_APB_GTGREF0_REF_CTRL_CLKACT                                             0x1
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00C8, 0x01003F07U ,0x01000400U)  
+		RegMask = (CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK | CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK | CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK |  0 );
+
+		RegVal = ((0x00000004U << CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT
+			| 0x00000001U << CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_GTGREF0_REF_CTRL_OFFSET ,0x01003F07U ,0x01000400U);
+	/*############################################################################################################################ */
+
+		/*Register : DBG_TSTMP_CTRL @ 0XFD1A00F8

+
+		6 bit divider
+		PSU_CRF_APB_DBG_TSTMP_CTRL_DIVISOR0                                             0x2
+
+		000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)
+		PSU_CRF_APB_DBG_TSTMP_CTRL_SRCSEL                                               0x0
+
+		This register controls this reference clock
+		(OFFSET, MASK, VALUE)      (0XFD1A00F8, 0x00003F07U ,0x00000200U)  
+		RegMask = (CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK | CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK |  0 );
+
+		RegVal = ((0x00000002U << CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT
+			| 0x00000000U << CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_DBG_TSTMP_CTRL_OFFSET ,0x00003F07U ,0x00000200U);
+	/*############################################################################################################################ */
+
+		/*Register : IOU_TTC_APB_CLK @ 0XFF180380

+
+		00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
+		0" = Select the R5 clock for the APB interface of TTC0
+		PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL                                           0
+
+		00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
+		0" = Select the R5 clock for the APB interface of TTC1
+		PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL                                           0
+
+		00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
+		0" = Select the R5 clock for the APB interface of TTC2
+		PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL                                           0
+
+		00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
+		0" = Select the R5 clock for the APB interface of TTC3
+		PSU_IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL                                           0
+
+		TTC APB clock select
+		(OFFSET, MASK, VALUE)      (0XFF180380, 0x000000FFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK | IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_IOU_TTC_APB_CLK_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : WDT_CLK_SEL @ 0XFD610100

+
+		System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)
+		PSU_FPD_SLCR_WDT_CLK_SEL_SELECT                                                 0
+
+		SWDT clock source select
+		(OFFSET, MASK, VALUE)      (0XFD610100, 0x00000001U ,0x00000000U)  
+		RegMask = (FPD_SLCR_WDT_CLK_SEL_SELECT_MASK |  0 );
+
+		RegVal = ((0x00000000U << FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (FPD_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : WDT_CLK_SEL @ 0XFF180300

+
+		System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout 
+		ia MIO
+		PSU_IOU_SLCR_WDT_CLK_SEL_SELECT                                                 0
+
+		SWDT clock source select
+		(OFFSET, MASK, VALUE)      (0XFF180300, 0x00000001U ,0x00000000U)  
+		RegMask = (IOU_SLCR_WDT_CLK_SEL_SELECT_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : CSUPMU_WDT_CLK_SEL @ 0XFF410050

+
+		System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk
+		PSU_LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT                                          0
+
+		SWDT clock source select
+		(OFFSET, MASK, VALUE)      (0XFF410050, 0x00000001U ,0x00000000U)  
+		RegMask = (LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK |  0 );
+
+		RegVal = ((0x00000000U << LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_ddr_init_data() {
+		// : DDR INITIALIZATION
+		// : DDR CONTROLLER RESET
+		/*Register : RST_DDR_SS @ 0XFD1A0108

+
+		DDR block level reset inside of the DDR Sub System
+		PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X1
+
+		DDR sub system block level reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000008U)  
+		RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MSTR @ 0XFD070000

+
+		Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 
+		evice
+		PSU_DDRC_MSTR_DEVICE_CONFIG                                                     0x1
+
+		Choose which registers are used. - 0 - Original registers - 1 - Shadow registers
+		PSU_DDRC_MSTR_FREQUENCY_MODE                                                    0x0
+
+		Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
+		esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - 
+		ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
+		ks - 1111 - Four ranks
+		PSU_DDRC_MSTR_ACTIVE_RANKS                                                      0x1
+
+		SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
+		 of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls 
+		he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
+		-fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
+		 is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1
+		PSU_DDRC_MSTR_BURST_RDWR                                                        0x4
+
+		Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM 
+		n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
+		l_off_mode is not supported, and this bit must be set to '0'.
+		PSU_DDRC_MSTR_DLL_OFF_MODE                                                      0x0
+
+		Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
+		AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
+		dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
+		figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).
+		PSU_DDRC_MSTR_DATA_BUS_WIDTH                                                    0x0
+
+		1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
+		 only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode 
+		s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set
+		PSU_DDRC_MSTR_GEARDOWN_MODE                                                     0x0
+
+		If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held 
+		or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in 
+		PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
+		ing is not supported in DDR4 geardown mode.
+		PSU_DDRC_MSTR_EN_2T_TIMING_MODE                                                 0x0
+
+		When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
+		t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
+		 (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
+		_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'
+		PSU_DDRC_MSTR_BURSTCHOP                                                         0x0
+
+		Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
+		port LPDDR4.
+		PSU_DDRC_MSTR_LPDDR4                                                            0x0
+
+		Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support 
+		DR4.
+		PSU_DDRC_MSTR_DDR4                                                              0x1
+
+		Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
+		port LPDDR3.
+		PSU_DDRC_MSTR_LPDDR3                                                            0x0
+
+		Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
+		port LPDDR2.
+		PSU_DDRC_MSTR_LPDDR2                                                            0x0
+
+		Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
+		
+		PSU_DDRC_MSTR_DDR3                                                              0x0
+
+		Master Register
+		(OFFSET, MASK, VALUE)      (0XFD070000, 0xE30FBE3DU ,0x41040010U)  
+		RegMask = (DDRC_MSTR_DEVICE_CONFIG_MASK | DDRC_MSTR_FREQUENCY_MODE_MASK | DDRC_MSTR_ACTIVE_RANKS_MASK | DDRC_MSTR_BURST_RDWR_MASK | DDRC_MSTR_DLL_OFF_MODE_MASK | DDRC_MSTR_DATA_BUS_WIDTH_MASK | DDRC_MSTR_GEARDOWN_MODE_MASK | DDRC_MSTR_EN_2T_TIMING_MODE_MASK | DDRC_MSTR_BURSTCHOP_MASK | DDRC_MSTR_LPDDR4_MASK | DDRC_MSTR_DDR4_MASK | DDRC_MSTR_LPDDR3_MASK | DDRC_MSTR_LPDDR2_MASK | DDRC_MSTR_DDR3_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_MSTR_DEVICE_CONFIG_SHIFT
+			| 0x00000000U << DDRC_MSTR_FREQUENCY_MODE_SHIFT
+			| 0x00000001U << DDRC_MSTR_ACTIVE_RANKS_SHIFT
+			| 0x00000004U << DDRC_MSTR_BURST_RDWR_SHIFT
+			| 0x00000000U << DDRC_MSTR_DLL_OFF_MODE_SHIFT
+			| 0x00000000U << DDRC_MSTR_DATA_BUS_WIDTH_SHIFT
+			| 0x00000000U << DDRC_MSTR_GEARDOWN_MODE_SHIFT
+			| 0x00000000U << DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT
+			| 0x00000000U << DDRC_MSTR_BURSTCHOP_SHIFT
+			| 0x00000000U << DDRC_MSTR_LPDDR4_SHIFT
+			| 0x00000001U << DDRC_MSTR_DDR4_SHIFT
+			| 0x00000000U << DDRC_MSTR_LPDDR3_SHIFT
+			| 0x00000000U << DDRC_MSTR_LPDDR2_SHIFT
+			| 0x00000000U << DDRC_MSTR_DDR3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_MSTR_OFFSET ,0xE30FBE3DU ,0x41040010U);
+	/*############################################################################################################################ */
+
+		/*Register : MRCTRL0 @ 0XFD070010

+
+		Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
+		 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
+		re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.
+		PSU_DDRC_MRCTRL0_MR_WR                                                          0x0
+
+		Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
+		 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
+		R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
+		dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well 
+		s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
+		put Inversion of RDIMMs.
+		PSU_DDRC_MRCTRL0_MR_ADDR                                                        0x0
+
+		Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
+		 However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
+		amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks 
+		 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3
+		PSU_DDRC_MRCTRL0_MR_RANK                                                        0x3
+
+		Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. 
+		or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
+		 be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared 
+		o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
+		n is not allowed - 1 - Software intervention is allowed
+		PSU_DDRC_MRCTRL0_SW_INIT_INT                                                    0x0
+
+		Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode
+		PSU_DDRC_MRCTRL0_PDA_EN                                                         0x0
+
+		Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR
+		PSU_DDRC_MRCTRL0_MPR_EN                                                         0x0
+
+		Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
+		d
+		PSU_DDRC_MRCTRL0_MR_TYPE                                                        0x0
+
+		Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_i
+		it_int - pda_en - mpr_en
+		(OFFSET, MASK, VALUE)      (0XFD070010, 0x8000F03FU ,0x00000030U)  
+		RegMask = (DDRC_MRCTRL0_MR_WR_MASK | DDRC_MRCTRL0_MR_ADDR_MASK | DDRC_MRCTRL0_MR_RANK_MASK | DDRC_MRCTRL0_SW_INIT_INT_MASK | DDRC_MRCTRL0_PDA_EN_MASK | DDRC_MRCTRL0_MPR_EN_MASK | DDRC_MRCTRL0_MR_TYPE_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_MRCTRL0_MR_WR_SHIFT
+			| 0x00000000U << DDRC_MRCTRL0_MR_ADDR_SHIFT
+			| 0x00000003U << DDRC_MRCTRL0_MR_RANK_SHIFT
+			| 0x00000000U << DDRC_MRCTRL0_SW_INIT_INT_SHIFT
+			| 0x00000000U << DDRC_MRCTRL0_PDA_EN_SHIFT
+			| 0x00000000U << DDRC_MRCTRL0_MPR_EN_SHIFT
+			| 0x00000000U << DDRC_MRCTRL0_MR_TYPE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_MRCTRL0_OFFSET ,0x8000F03FU ,0x00000030U);
+	/*############################################################################################################################ */
+
+		/*Register : DERATEEN @ 0XFD070020

+
+		Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
+		 Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
+		g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.
+		PSU_DDRC_DERATEEN_RC_DERATE_VALUE                                               0x3
+
+		Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
+		r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.
+		PSU_DDRC_DERATEEN_DERATE_BYTE                                                   0x0
+
+		Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
+		4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
+		for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.
+		PSU_DDRC_DERATEEN_DERATE_VALUE                                                  0x0
+
+		Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
+		Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
+		mode.
+		PSU_DDRC_DERATEEN_DERATE_ENABLE                                                 0x0
+
+		Temperature Derate Enable Register
+		(OFFSET, MASK, VALUE)      (0XFD070020, 0x000003F3U ,0x00000300U)  
+		RegMask = (DDRC_DERATEEN_RC_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_BYTE_MASK | DDRC_DERATEEN_DERATE_VALUE_MASK | DDRC_DERATEEN_DERATE_ENABLE_MASK |  0 );
+
+		RegVal = ((0x00000003U << DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT
+			| 0x00000000U << DDRC_DERATEEN_DERATE_BYTE_SHIFT
+			| 0x00000000U << DDRC_DERATEEN_DERATE_VALUE_SHIFT
+			| 0x00000000U << DDRC_DERATEEN_DERATE_ENABLE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DERATEEN_OFFSET ,0x000003F3U ,0x00000300U);
+	/*############################################################################################################################ */
+
+		/*Register : DERATEINT @ 0XFD070024

+
+		Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
+		DR3/LPDDR4. This register must not be set to zero
+		PSU_DDRC_DERATEINT_MR4_READ_INTERVAL                                            0x800000
+
+		Temperature Derate Interval Register
+		(OFFSET, MASK, VALUE)      (0XFD070024, 0xFFFFFFFFU ,0x00800000U)  
+		RegMask = (DDRC_DERATEINT_MR4_READ_INTERVAL_MASK |  0 );
+
+		RegVal = ((0x00800000U << DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DERATEINT_OFFSET ,0xFFFFFFFFU ,0x00800000U);
+	/*############################################################################################################################ */
+
+		/*Register : PWRCTL @ 0XFD070030

+
+		Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
+		r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 
+		 - Allow transition from Self refresh state
+		PSU_DDRC_PWRCTL_STAY_IN_SELFREF                                                 0x0
+
+		A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
+		M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
+		are Exit from Self Refresh
+		PSU_DDRC_PWRCTL_SELFREF_SW                                                      0x0
+
+		When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
+		st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For 
+		on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
+		DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PWRCTL_MPSM_EN                                                         0x0
+
+		Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
+		is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
+		4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in 
+		ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
+		rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)
+		PSU_DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE                                         0x0
+
+		When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
+		et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down 
+		xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
+		 should not be set to 1. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PWRCTL_DEEPPOWERDOWN_EN                                                0x0
+
+		If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
+		RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.
+		PSU_DDRC_PWRCTL_POWERDOWN_EN                                                    0x0
+
+		If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
+		f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.
+		PSU_DDRC_PWRCTL_SELFREF_EN                                                      0x0
+
+		Low Power Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070030, 0x0000007FU ,0x00000000U)  
+		RegMask = (DDRC_PWRCTL_STAY_IN_SELFREF_MASK | DDRC_PWRCTL_SELFREF_SW_MASK | DDRC_PWRCTL_MPSM_EN_MASK | DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK | DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK | DDRC_PWRCTL_POWERDOWN_EN_MASK | DDRC_PWRCTL_SELFREF_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_SELFREF_SW_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_MPSM_EN_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_POWERDOWN_EN_SHIFT
+			| 0x00000000U << DDRC_PWRCTL_SELFREF_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PWRCTL_OFFSET ,0x0000007FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : PWRTMG @ 0XFD070034

+
+		After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in 
+		he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PWRTMG_SELFREF_TO_X32                                                  0x40
+
+		Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
+		ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
+		iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PWRTMG_T_DPD_X4096                                                     0x84
+
+		After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
+		 PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.
+		PSU_DDRC_PWRTMG_POWERDOWN_TO_X32                                                0x10
+
+		Low Power Timing Register
+		(OFFSET, MASK, VALUE)      (0XFD070034, 0x00FFFF1FU ,0x00408410U)  
+		RegMask = (DDRC_PWRTMG_SELFREF_TO_X32_MASK | DDRC_PWRTMG_T_DPD_X4096_MASK | DDRC_PWRTMG_POWERDOWN_TO_X32_MASK |  0 );
+
+		RegVal = ((0x00000040U << DDRC_PWRTMG_SELFREF_TO_X32_SHIFT
+			| 0x00000084U << DDRC_PWRTMG_T_DPD_X4096_SHIFT
+			| 0x00000010U << DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PWRTMG_OFFSET ,0x00FFFF1FU ,0x00408410U);
+	/*############################################################################################################################ */
+
+		/*Register : RFSHCTL0 @ 0XFD070050

+
+		Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
+		d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
+		 It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
+		may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
+		om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.
+		PSU_DDRC_RFSHCTL0_REFRESH_MARGIN                                                0x2
+
+		If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
+		1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
+		 would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
+		HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
+		formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
+		ued to the uMCTL2. FOR PERFORMANCE ONLY.
+		PSU_DDRC_RFSHCTL0_REFRESH_TO_X32                                                0x10
+
+		The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
+		reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
+		reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
+		RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
+		. - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
+		tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
+		fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
+		ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
+		tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
+		d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
+		initiated update is complete.
+		PSU_DDRC_RFSHCTL0_REFRESH_BURST                                                 0x0
+
+		- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
+		t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
+		support LPDDR2/LPDDR3/LPDDR4
+		PSU_DDRC_RFSHCTL0_PER_BANK_REFRESH                                              0x0
+
+		Refresh Control Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070050, 0x00F1F1F4U ,0x00210000U)  
+		RegMask = (DDRC_RFSHCTL0_REFRESH_MARGIN_MASK | DDRC_RFSHCTL0_REFRESH_TO_X32_MASK | DDRC_RFSHCTL0_REFRESH_BURST_MASK | DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT
+			| 0x00000010U << DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT
+			| 0x00000000U << DDRC_RFSHCTL0_REFRESH_BURST_SHIFT
+			| 0x00000000U << DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_RFSHCTL0_OFFSET ,0x00F1F1F4U ,0x00210000U);
+	/*############################################################################################################################ */
+
+		/*Register : RFSHCTL3 @ 0XFD070060

+
+		Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
+		ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
+		orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
+		self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in 
+		uture version of the uMCTL2.
+		PSU_DDRC_RFSHCTL3_REFRESH_MODE                                                  0x0
+
+		Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value 
+		s automatically updated when exiting reset, so it does not need to be toggled initially.
+		PSU_DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL                                          0x0
+
+		When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
+		ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
+		auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
+		is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. 
+		his register field is changeable on the fly.
+		PSU_DDRC_RFSHCTL3_DIS_AUTO_REFRESH                                              0x1
+
+		Refresh Control Register 3
+		(OFFSET, MASK, VALUE)      (0XFD070060, 0x00000073U ,0x00000001U)  
+		RegMask = (DDRC_RFSHCTL3_REFRESH_MODE_MASK | DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK | DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_RFSHCTL3_REFRESH_MODE_SHIFT
+			| 0x00000000U << DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT
+			| 0x00000001U << DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_RFSHCTL3_OFFSET ,0x00000073U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : RFSHTMG @ 0XFD070064

+
+		tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
+		 for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
+		, this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should 
+		e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
+		ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
+		programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
+		TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.
+		PSU_DDRC_RFSHTMG_T_RFC_NOM_X32                                                  0x82
+
+		Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the 
+		REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
+		 - 0 - tREFBW parameter not used - 1 - tREFBW parameter used
+		PSU_DDRC_RFSHTMG_LPDDR3_TREFBW_EN                                               0x1
+
+		tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
+		 RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
+		DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
+		 per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
+		equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
+		opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.
+		PSU_DDRC_RFSHTMG_T_RFC_MIN                                                      0x8b
+
+		Refresh Timing Register
+		(OFFSET, MASK, VALUE)      (0XFD070064, 0x0FFF83FFU ,0x0082808BU)  
+		RegMask = (DDRC_RFSHTMG_T_RFC_NOM_X32_MASK | DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK | DDRC_RFSHTMG_T_RFC_MIN_MASK |  0 );
+
+		RegVal = ((0x00000082U << DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT
+			| 0x00000001U << DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT
+			| 0x0000008BU << DDRC_RFSHTMG_T_RFC_MIN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_RFSHTMG_OFFSET ,0x0FFF83FFU ,0x0082808BU);
+	/*############################################################################################################################ */
+
+		/*Register : ECCCFG0 @ 0XFD070070

+
+		Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined
+		PSU_DDRC_ECCCFG0_DIS_SCRUB                                                      0x1
+
+		ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
+		 use
+		PSU_DDRC_ECCCFG0_ECC_MODE                                                       0x0
+
+		ECC Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070070, 0x00000017U ,0x00000010U)  
+		RegMask = (DDRC_ECCCFG0_DIS_SCRUB_MASK | DDRC_ECCCFG0_ECC_MODE_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_ECCCFG0_DIS_SCRUB_SHIFT
+			| 0x00000000U << DDRC_ECCCFG0_ECC_MODE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ECCCFG0_OFFSET ,0x00000017U ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : ECCCFG1 @ 0XFD070074

+
+		Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
+		ng, if ECCCFG1.data_poison_en=1
+		PSU_DDRC_ECCCFG1_DATA_POISON_BIT                                                0x0
+
+		Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers
+		PSU_DDRC_ECCCFG1_DATA_POISON_EN                                                 0x0
+
+		ECC Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070074, 0x00000003U ,0x00000000U)  
+		RegMask = (DDRC_ECCCFG1_DATA_POISON_BIT_MASK | DDRC_ECCCFG1_DATA_POISON_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT
+			| 0x00000000U << DDRC_ECCCFG1_DATA_POISON_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ECCCFG1_OFFSET ,0x00000003U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : CRCPARCTL1 @ 0XFD0700C4

+
+		The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
+		the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY 
+		pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
+		L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
+		dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
+		e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks
+		PSU_DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT                                             0x10
+
+		After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
+		M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
+		the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
+		the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
+		RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
+		 handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
+		rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
+		ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in 
+		he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is 
+		one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in 
+		PR Page 1 should be treated as 'Don't care'.
+		PSU_DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW                                           0x1
+
+		- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
+		 CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
+		 disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)
+		PSU_DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE                                     0x0
+
+		CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
+		d to support DDR4.
+		PSU_DDRC_CRCPARCTL1_CRC_INC_DM                                                  0x0
+
+		CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
+		 CRC mode register setting in the DRAM.
+		PSU_DDRC_CRCPARCTL1_CRC_ENABLE                                                  0x0
+
+		C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of 
+		/A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
+		is register should be 1.
+		PSU_DDRC_CRCPARCTL1_PARITY_ENABLE                                               0x0
+
+		CRC Parity Control Register1
+		(OFFSET, MASK, VALUE)      (0XFD0700C4, 0x3F000391U ,0x10000200U)  
+		RegMask = (DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK | DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK | DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK | DDRC_CRCPARCTL1_CRC_INC_DM_MASK | DDRC_CRCPARCTL1_CRC_ENABLE_MASK | DDRC_CRCPARCTL1_PARITY_ENABLE_MASK |  0 );
+
+		RegVal = ((0x00000010U << DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT
+			| 0x00000001U << DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT
+			| 0x00000000U << DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT
+			| 0x00000000U << DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT
+			| 0x00000000U << DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT
+			| 0x00000000U << DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_CRCPARCTL1_OFFSET ,0x3F000391U ,0x10000200U);
+	/*############################################################################################################################ */
+
+		/*Register : CRCPARCTL2 @ 0XFD0700C8

+
+		Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
+		 - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
+		er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.
+		PSU_DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX                                          0x40
+
+		Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
+		tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
+		value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.
+		PSU_DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX                                          0x5
+
+		Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
+		ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
+		er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
+		les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
+		or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
+		ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
+		max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
+		bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
+		+ board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
+		ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The 
+		ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
+		to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
+		 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
+		PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
+		_FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
+		C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
+		e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
+		 bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
+		H-6 Values of 0, 1 and 2 are illegal.
+		PSU_DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4                                0x1f
+
+		CRC Parity Control Register2
+		(OFFSET, MASK, VALUE)      (0XFD0700C8, 0x01FF1F3FU ,0x0040051FU)  
+		RegMask = (DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK | DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK |  0 );
+
+		RegVal = ((0x00000040U << DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT
+			| 0x00000005U << DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT
+			| 0x0000001FU << DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_CRCPARCTL2_OFFSET ,0x01FF1F3FU ,0x0040051FU);
+	/*############################################################################################################################ */
+
+		/*Register : INIT0 @ 0XFD0700D0

+
+		If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
+		 in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
+		ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
+		r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported 
+		or LPDDR4 in this version of the uMCTL2.
+		PSU_DDRC_INIT0_SKIP_DRAM_INIT                                                   0x0
+
+		Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires 
+		 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
+		grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
+		MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.
+		PSU_DDRC_INIT0_POST_CKE_X1024                                                   0x2
+
+		Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 
+		pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
+		tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
+		 to next integer value.
+		PSU_DDRC_INIT0_PRE_CKE_X1024                                                    0x106
+
+		SDRAM Initialization Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0700D0, 0xC3FF0FFFU ,0x00020106U)  
+		RegMask = (DDRC_INIT0_SKIP_DRAM_INIT_MASK | DDRC_INIT0_POST_CKE_X1024_MASK | DDRC_INIT0_PRE_CKE_X1024_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_INIT0_SKIP_DRAM_INIT_SHIFT
+			| 0x00000002U << DDRC_INIT0_POST_CKE_X1024_SHIFT
+			| 0x00000106U << DDRC_INIT0_PRE_CKE_X1024_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT0_OFFSET ,0xC3FF0FFFU ,0x00020106U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT1 @ 0XFD0700D4

+
+		Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
+		LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1
+		PSU_DDRC_INIT1_DRAM_RSTN_X1024                                                  0x2
+
+		Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
+		bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.
+		PSU_DDRC_INIT1_FINAL_WAIT_X32                                                   0x0
+
+		Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
+		. There is no known specific requirement for this; it may be set to zero.
+		PSU_DDRC_INIT1_PRE_OCD_X32                                                      0x0
+
+		SDRAM Initialization Register 1
+		(OFFSET, MASK, VALUE)      (0XFD0700D4, 0x01FF7F0FU ,0x00020000U)  
+		RegMask = (DDRC_INIT1_DRAM_RSTN_X1024_MASK | DDRC_INIT1_FINAL_WAIT_X32_MASK | DDRC_INIT1_PRE_OCD_X32_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_INIT1_DRAM_RSTN_X1024_SHIFT
+			| 0x00000000U << DDRC_INIT1_FINAL_WAIT_X32_SHIFT
+			| 0x00000000U << DDRC_INIT1_PRE_OCD_X32_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT1_OFFSET ,0x01FF7F0FU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT2 @ 0XFD0700D8

+
+		Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.
+		PSU_DDRC_INIT2_IDLE_AFTER_RESET_X32                                             0x23
+
+		Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
+		e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.
+		PSU_DDRC_INIT2_MIN_STABLE_CLOCK_X1                                              0x5
+
+		SDRAM Initialization Register 2
+		(OFFSET, MASK, VALUE)      (0XFD0700D8, 0x0000FF0FU ,0x00002305U)  
+		RegMask = (DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK | DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK |  0 );
+
+		RegVal = ((0x00000023U << DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT
+			| 0x00000005U << DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT2_OFFSET ,0x0000FF0FU ,0x00002305U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT3 @ 0XFD0700DC

+
+		DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
+		 DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
+		register
+		PSU_DDRC_INIT3_MR                                                               0x930
+
+		DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
+		bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
+		 bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
+		lue to write to MR2 register
+		PSU_DDRC_INIT3_EMR                                                              0x301
+
+		SDRAM Initialization Register 3
+		(OFFSET, MASK, VALUE)      (0XFD0700DC, 0xFFFFFFFFU ,0x09300301U)  
+		RegMask = (DDRC_INIT3_MR_MASK | DDRC_INIT3_EMR_MASK |  0 );
+
+		RegVal = ((0x00000930U << DDRC_INIT3_MR_SHIFT
+			| 0x00000301U << DDRC_INIT3_EMR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT3_OFFSET ,0xFFFFFFFFU ,0x09300301U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT4 @ 0XFD0700E0

+
+		DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 
+		egister mDDR: Unused
+		PSU_DDRC_INIT4_EMR2                                                             0x20
+
+		DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to 
+		rite to MR13 register
+		PSU_DDRC_INIT4_EMR3                                                             0x200
+
+		SDRAM Initialization Register 4
+		(OFFSET, MASK, VALUE)      (0XFD0700E0, 0xFFFFFFFFU ,0x00200200U)  
+		RegMask = (DDRC_INIT4_EMR2_MASK | DDRC_INIT4_EMR3_MASK |  0 );
+
+		RegVal = ((0x00000020U << DDRC_INIT4_EMR2_SHIFT
+			| 0x00000200U << DDRC_INIT4_EMR3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT4_OFFSET ,0xFFFFFFFFU ,0x00200200U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT5 @ 0XFD0700E4

+
+		ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock 
+		ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.
+		PSU_DDRC_INIT5_DEV_ZQINIT_X32                                                   0x21
+
+		Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
+		3 typically requires 10 us.
+		PSU_DDRC_INIT5_MAX_AUTO_INIT_X1024                                              0x4
+
+		SDRAM Initialization Register 5
+		(OFFSET, MASK, VALUE)      (0XFD0700E4, 0x00FF03FFU ,0x00210004U)  
+		RegMask = (DDRC_INIT5_DEV_ZQINIT_X32_MASK | DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK |  0 );
+
+		RegVal = ((0x00000021U << DDRC_INIT5_DEV_ZQINIT_X32_SHIFT
+			| 0x00000004U << DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT5_OFFSET ,0x00FF03FFU ,0x00210004U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT6 @ 0XFD0700E8

+
+		DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.
+		PSU_DDRC_INIT6_MR4                                                              0x0
+
+		DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.
+		PSU_DDRC_INIT6_MR5                                                              0x6c0
+
+		SDRAM Initialization Register 6
+		(OFFSET, MASK, VALUE)      (0XFD0700E8, 0xFFFFFFFFU ,0x000006C0U)  
+		RegMask = (DDRC_INIT6_MR4_MASK | DDRC_INIT6_MR5_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_INIT6_MR4_SHIFT
+			| 0x000006C0U << DDRC_INIT6_MR5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT6_OFFSET ,0xFFFFFFFFU ,0x000006C0U);
+	/*############################################################################################################################ */
+
+		/*Register : INIT7 @ 0XFD0700EC

+
+		DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.
+		PSU_DDRC_INIT7_MR6                                                              0x819
+
+		SDRAM Initialization Register 7
+		(OFFSET, MASK, VALUE)      (0XFD0700EC, 0xFFFF0000U ,0x08190000U)  
+		RegMask = (DDRC_INIT7_MR6_MASK |  0 );
+
+		RegVal = ((0x00000819U << DDRC_INIT7_MR6_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_INIT7_OFFSET ,0xFFFF0000U ,0x08190000U);
+	/*############################################################################################################################ */
+
+		/*Register : DIMMCTL @ 0XFD0700F0

+
+		Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
+		ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
+		 address mirroring is enabled.
+		PSU_DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING                                          0x0
+
+		Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
+		 be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output 
+		nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
+		effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
+		led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled
+		PSU_DDRC_DIMMCTL_MRS_BG1_EN                                                     0x1
+
+		Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
+		 be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, 
+		his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address 
+		f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled
+		PSU_DDRC_DIMMCTL_MRS_A17_EN                                                     0x0
+
+		Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
+		which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, 
+		A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
+		lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. 
+		or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
+		 has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
+		ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.
+		PSU_DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN                                             0x0
+
+		Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
+		4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits 
+		re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
+		at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
+		sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
+		 swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
+		ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
+		or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
+		hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
+		ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
+		not implement address mirroring
+		PSU_DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN                                              0x0
+
+		Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
+		R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
+		CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
+		 each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses
+		PSU_DDRC_DIMMCTL_DIMM_STAGGER_CS_EN                                             0x0
+
+		DIMM Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0700F0, 0x0000003FU ,0x00000010U)  
+		RegMask = (DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK | DDRC_DIMMCTL_MRS_BG1_EN_MASK | DDRC_DIMMCTL_MRS_A17_EN_MASK | DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK | DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK | DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT
+			| 0x00000001U << DDRC_DIMMCTL_MRS_BG1_EN_SHIFT
+			| 0x00000000U << DDRC_DIMMCTL_MRS_A17_EN_SHIFT
+			| 0x00000000U << DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT
+			| 0x00000000U << DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT
+			| 0x00000000U << DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DIMMCTL_OFFSET ,0x0000003FU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : RANKCTL @ 0XFD0700F4

+
+		Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
+		e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
+		nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
+		ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
+		ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed 
+		n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
+		ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
+		or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
+		 to the next integer.
+		PSU_DDRC_RANKCTL_DIFF_RANK_WR_GAP                                               0x6
+
+		Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
+		e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
+		sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
+		p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
+		), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
+		requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
+		quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and 
+		ound it up to the next integer.
+		PSU_DDRC_RANKCTL_DIFF_RANK_RD_GAP                                               0x6
+
+		Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
+		nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
+		on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
+		-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
+		_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
+		om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
+		ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to 
+		llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
+		ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as 
+		ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
+		. FOR PERFORMANCE ONLY.
+		PSU_DDRC_RANKCTL_MAX_RANK_RD                                                    0xf
+
+		Rank Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0700F4, 0x00000FFFU ,0x0000066FU)  
+		RegMask = (DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK | DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK | DDRC_RANKCTL_MAX_RANK_RD_MASK |  0 );
+
+		RegVal = ((0x00000006U << DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT
+			| 0x00000006U << DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT
+			| 0x0000000FU << DDRC_RANKCTL_MAX_RANK_RD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_RANKCTL_OFFSET ,0x00000FFFU ,0x0000066FU);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG0 @ 0XFD070100

+
+		Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles 
+		 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
+		 value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
+		Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this 
+		arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
+		with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.
+		PSU_DDRC_DRAMTMG0_WR2PRE                                                        0x11
+
+		tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
+		in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next 
+		nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks
+		PSU_DDRC_DRAMTMG0_T_FAW                                                         0xc
+
+		tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
+		imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
+		 No rounding up. Unit: Multiples of 1024 clocks.
+		PSU_DDRC_DRAMTMG0_T_RAS_MAX                                                     0x24
+
+		tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, 
+		rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
+		 (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks
+		PSU_DDRC_DRAMTMG0_T_RAS_MIN                                                     0x12
+
+		SDRAM Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070100, 0x7F3F7F3FU ,0x110C2412U)  
+		RegMask = (DDRC_DRAMTMG0_WR2PRE_MASK | DDRC_DRAMTMG0_T_FAW_MASK | DDRC_DRAMTMG0_T_RAS_MAX_MASK | DDRC_DRAMTMG0_T_RAS_MIN_MASK |  0 );
+
+		RegVal = ((0x00000011U << DDRC_DRAMTMG0_WR2PRE_SHIFT
+			| 0x0000000CU << DDRC_DRAMTMG0_T_FAW_SHIFT
+			| 0x00000024U << DDRC_DRAMTMG0_T_RAS_MAX_SHIFT
+			| 0x00000012U << DDRC_DRAMTMG0_T_RAS_MIN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG0_OFFSET ,0x7F3F7F3FU ,0x110C2412U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG1 @ 0XFD070104

+
+		tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
+		 is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, 
+		rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks
+		PSU_DDRC_DRAMTMG1_T_XP                                                          0x4
+
+		tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
+		R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
+		S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
+		2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
+		gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
+		e. Unit: Clocks.
+		PSU_DDRC_DRAMTMG1_RD2PRE                                                        0x4
+
+		tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
+		 up to next integer value. Unit: Clocks.
+		PSU_DDRC_DRAMTMG1_T_RC                                                          0x19
+
+		SDRAM Timing Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070104, 0x001F1F7FU ,0x00040419U)  
+		RegMask = (DDRC_DRAMTMG1_T_XP_MASK | DDRC_DRAMTMG1_RD2PRE_MASK | DDRC_DRAMTMG1_T_RC_MASK |  0 );
+
+		RegVal = ((0x00000004U << DDRC_DRAMTMG1_T_XP_SHIFT
+			| 0x00000004U << DDRC_DRAMTMG1_RD2PRE_SHIFT
+			| 0x00000019U << DDRC_DRAMTMG1_T_RC_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG1_OFFSET ,0x001F1F7FU ,0x00040419U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG2 @ 0XFD070108

+
+		Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
+		t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
+		tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
+		equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
+		 is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
+		PSU_DDRC_DRAMTMG2_WRITE_LATENCY                                                 0x7
+
+		Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
+		using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For 
+		onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
+		er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
+		s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks
+		PSU_DDRC_DRAMTMG2_READ_LATENCY                                                  0x8
+
+		DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL 
+		PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
+		/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
+		time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = 
+		urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
+		tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
+		DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
+		gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
+		PSU_DDRC_DRAMTMG2_RD2WR                                                         0x6
+
+		DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
+		k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
+		 per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
+		 length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
+		d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
+		 delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
+		ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.
+		PSU_DDRC_DRAMTMG2_WR2RD                                                         0xe
+
+		SDRAM Timing Register 2
+		(OFFSET, MASK, VALUE)      (0XFD070108, 0x3F3F3F3FU ,0x0708060EU)  
+		RegMask = (DDRC_DRAMTMG2_WRITE_LATENCY_MASK | DDRC_DRAMTMG2_READ_LATENCY_MASK | DDRC_DRAMTMG2_RD2WR_MASK | DDRC_DRAMTMG2_WR2RD_MASK |  0 );
+
+		RegVal = ((0x00000007U << DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT
+			| 0x00000008U << DDRC_DRAMTMG2_READ_LATENCY_SHIFT
+			| 0x00000006U << DDRC_DRAMTMG2_RD2WR_SHIFT
+			| 0x0000000EU << DDRC_DRAMTMG2_WR2RD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG2_OFFSET ,0x3F3F3F3FU ,0x0708060EU);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG3 @ 0XFD07010C

+
+		Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
+		 LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW 
+		nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
+		 used for the time from a MRW/MRR to a MRW/MRR.
+		PSU_DDRC_DRAMTMG3_T_MRW                                                         0x5
+
+		tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time 
+		rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
+		nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
+		4 is used, set to tMRD_PAR(tMOD+PL) instead.
+		PSU_DDRC_DRAMTMG3_T_MRD                                                         0x4
+
+		tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
+		y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
+		 if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
+		 + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.
+		PSU_DDRC_DRAMTMG3_T_MOD                                                         0xc
+
+		SDRAM Timing Register 3
+		(OFFSET, MASK, VALUE)      (0XFD07010C, 0x3FF3F3FFU ,0x0050400CU)  
+		RegMask = (DDRC_DRAMTMG3_T_MRW_MASK | DDRC_DRAMTMG3_T_MRD_MASK | DDRC_DRAMTMG3_T_MOD_MASK |  0 );
+
+		RegVal = ((0x00000005U << DDRC_DRAMTMG3_T_MRW_SHIFT
+			| 0x00000004U << DDRC_DRAMTMG3_T_MRD_SHIFT
+			| 0x0000000CU << DDRC_DRAMTMG3_T_MOD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG3_OFFSET ,0x3FF3F3FFU ,0x0050400CU);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG4 @ 0XFD070110

+
+		tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
+		am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
+		lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.
+		PSU_DDRC_DRAMTMG4_T_RCD                                                         0x8
+
+		DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
+		time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
+		d it up to the next integer value. Unit: clocks.
+		PSU_DDRC_DRAMTMG4_T_CCD                                                         0x3
+
+		DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
+		 activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
+		it up to the next integer value. Unit: Clocks.
+		PSU_DDRC_DRAMTMG4_T_RRD                                                         0x3
+
+		tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
+		(tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
+		2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.
+		PSU_DDRC_DRAMTMG4_T_RP                                                          0x9
+
+		SDRAM Timing Register 4
+		(OFFSET, MASK, VALUE)      (0XFD070110, 0x1F0F0F1FU ,0x08030309U)  
+		RegMask = (DDRC_DRAMTMG4_T_RCD_MASK | DDRC_DRAMTMG4_T_CCD_MASK | DDRC_DRAMTMG4_T_RRD_MASK | DDRC_DRAMTMG4_T_RP_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_DRAMTMG4_T_RCD_SHIFT
+			| 0x00000003U << DDRC_DRAMTMG4_T_CCD_SHIFT
+			| 0x00000003U << DDRC_DRAMTMG4_T_RRD_SHIFT
+			| 0x00000009U << DDRC_DRAMTMG4_T_RP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG4_OFFSET ,0x1F0F0F1FU ,0x08030309U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG5 @ 0XFD070114

+
+		This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
+		e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
+		tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
+		eger.
+		PSU_DDRC_DRAMTMG5_T_CKSRX                                                       0x6
+
+		This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
+		 SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: 
+		ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
+		to next integer.
+		PSU_DDRC_DRAMTMG5_T_CKSRE                                                       0x6
+
+		Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
+		tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE 
+		 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
+		.
+		PSU_DDRC_DRAMTMG5_T_CKESR                                                       0x4
+
+		Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of 
+		CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set 
+		his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
+		 next integer value. Unit: Clocks.
+		PSU_DDRC_DRAMTMG5_T_CKE                                                         0x3
+
+		SDRAM Timing Register 5
+		(OFFSET, MASK, VALUE)      (0XFD070114, 0x0F0F3F1FU ,0x06060403U)  
+		RegMask = (DDRC_DRAMTMG5_T_CKSRX_MASK | DDRC_DRAMTMG5_T_CKSRE_MASK | DDRC_DRAMTMG5_T_CKESR_MASK | DDRC_DRAMTMG5_T_CKE_MASK |  0 );
+
+		RegVal = ((0x00000006U << DDRC_DRAMTMG5_T_CKSRX_SHIFT
+			| 0x00000006U << DDRC_DRAMTMG5_T_CKSRE_SHIFT
+			| 0x00000004U << DDRC_DRAMTMG5_T_CKESR_SHIFT
+			| 0x00000003U << DDRC_DRAMTMG5_T_CKE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG5_OFFSET ,0x0F0F3F1FU ,0x06060403U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG6 @ 0XFD070118

+
+		This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after 
+		PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
+		ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
+		devices.
+		PSU_DDRC_DRAMTMG6_T_CKDPDE                                                      0x1
+
+		This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock 
+		table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
+		gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
+		R or LPDDR2 devices.
+		PSU_DDRC_DRAMTMG6_T_CKDPDX                                                      0x1
+
+		This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the 
+		lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
+		2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it 
+		p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_DRAMTMG6_T_CKCSX                                                       0x4
+
+		SDRAM Timing Register 6
+		(OFFSET, MASK, VALUE)      (0XFD070118, 0x0F0F000FU ,0x01010004U)  
+		RegMask = (DDRC_DRAMTMG6_T_CKDPDE_MASK | DDRC_DRAMTMG6_T_CKDPDX_MASK | DDRC_DRAMTMG6_T_CKCSX_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_DRAMTMG6_T_CKDPDE_SHIFT
+			| 0x00000001U << DDRC_DRAMTMG6_T_CKDPDX_SHIFT
+			| 0x00000004U << DDRC_DRAMTMG6_T_CKCSX_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG6_OFFSET ,0x0F0F000FU ,0x01010004U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG7 @ 0XFD07011C

+
+		This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. 
+		ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
+		is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
+		DDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_DRAMTMG7_T_CKPDE                                                       0x1
+
+		This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
+		time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
+		, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
+		g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_DRAMTMG7_T_CKPDX                                                       0x1
+
+		SDRAM Timing Register 7
+		(OFFSET, MASK, VALUE)      (0XFD07011C, 0x00000F0FU ,0x00000101U)  
+		RegMask = (DDRC_DRAMTMG7_T_CKPDE_MASK | DDRC_DRAMTMG7_T_CKPDX_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_DRAMTMG7_T_CKPDE_SHIFT
+			| 0x00000001U << DDRC_DRAMTMG7_T_CKPDX_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG7_OFFSET ,0x00000F0FU ,0x00000101U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG8 @ 0XFD070120

+
+		tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
+		O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
+		 is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.
+		PSU_DDRC_DRAMTMG8_T_XS_FAST_X32                                                 0x4
+
+		tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
+		ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: 
+		nsure this is less than or equal to t_xs_x32.
+		PSU_DDRC_DRAMTMG8_T_XS_ABORT_X32                                                0x4
+
+		tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the 
+		bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and 
+		DR4 SDRAMs.
+		PSU_DDRC_DRAMTMG8_T_XS_DLL_X32                                                  0xd
+
+		tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
+		above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
+		DDR4 SDRAMs.
+		PSU_DDRC_DRAMTMG8_T_XS_X32                                                      0x6
+
+		SDRAM Timing Register 8
+		(OFFSET, MASK, VALUE)      (0XFD070120, 0x7F7F7F7FU ,0x04040D06U)  
+		RegMask = (DDRC_DRAMTMG8_T_XS_FAST_X32_MASK | DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK | DDRC_DRAMTMG8_T_XS_DLL_X32_MASK | DDRC_DRAMTMG8_T_XS_X32_MASK |  0 );
+
+		RegVal = ((0x00000004U << DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT
+			| 0x00000004U << DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT
+			| 0x0000000DU << DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT
+			| 0x00000006U << DDRC_DRAMTMG8_T_XS_X32_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG8_OFFSET ,0x7F7F7F7FU ,0x04040D06U);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG9 @ 0XFD070124

+
+		DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2
+		PSU_DDRC_DRAMTMG9_DDR4_WR_PREAMBLE                                              0x0
+
+		tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' 
+		o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
+		nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.
+		PSU_DDRC_DRAMTMG9_T_CCD_S                                                       0x2
+
+		tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
+		ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
+		R4. Unit: Clocks.
+		PSU_DDRC_DRAMTMG9_T_RRD_S                                                       0x2
+
+		CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
+		round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
+		 Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
+		d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
+		is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using 
+		he above equation by 2, and round it up to next integer.
+		PSU_DDRC_DRAMTMG9_WR2RD_S                                                       0xb
+
+		SDRAM Timing Register 9
+		(OFFSET, MASK, VALUE)      (0XFD070124, 0x40070F3FU ,0x0002020BU)  
+		RegMask = (DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK | DDRC_DRAMTMG9_T_CCD_S_MASK | DDRC_DRAMTMG9_T_RRD_S_MASK | DDRC_DRAMTMG9_WR2RD_S_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT
+			| 0x00000002U << DDRC_DRAMTMG9_T_CCD_S_SHIFT
+			| 0x00000002U << DDRC_DRAMTMG9_T_RRD_S_SHIFT
+			| 0x0000000BU << DDRC_DRAMTMG9_WR2RD_S_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG9_OFFSET ,0x40070F3FU ,0x0002020BU);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG11 @ 0XFD07012C

+
+		tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
+		this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
+		ples of 32 clocks.
+		PSU_DDRC_DRAMTMG11_POST_MPSM_GAP_X32                                            0x6f
+
+		tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
+		 RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.
+		PSU_DDRC_DRAMTMG11_T_MPX_LH                                                     0x7
+
+		tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
+		up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.
+		PSU_DDRC_DRAMTMG11_T_MPX_S                                                      0x1
+
+		tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
+		r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
+		teger.
+		PSU_DDRC_DRAMTMG11_T_CKMPE                                                      0xe
+
+		SDRAM Timing Register 11
+		(OFFSET, MASK, VALUE)      (0XFD07012C, 0x7F1F031FU ,0x6F07010EU)  
+		RegMask = (DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK | DDRC_DRAMTMG11_T_MPX_LH_MASK | DDRC_DRAMTMG11_T_MPX_S_MASK | DDRC_DRAMTMG11_T_CKMPE_MASK |  0 );
+
+		RegVal = ((0x0000006FU << DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT
+			| 0x00000007U << DDRC_DRAMTMG11_T_MPX_LH_SHIFT
+			| 0x00000001U << DDRC_DRAMTMG11_T_MPX_S_SHIFT
+			| 0x0000000EU << DDRC_DRAMTMG11_T_CKMPE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG11_OFFSET ,0x7F1F031FU ,0x6F07010EU);
+	/*############################################################################################################################ */
+
+		/*Register : DRAMTMG12 @ 0XFD070130

+
+		tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
+		REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.
+		PSU_DDRC_DRAMTMG12_T_CMDCKE                                                     0x2
+
+		tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
+		/2) and round it up to next integer value.
+		PSU_DDRC_DRAMTMG12_T_CKEHCMD                                                    0x6
+
+		tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
+		s to (tMRD_PDA/2) and round it up to next integer value.
+		PSU_DDRC_DRAMTMG12_T_MRD_PDA                                                    0x8
+
+		SDRAM Timing Register 12
+		(OFFSET, MASK, VALUE)      (0XFD070130, 0x00030F1FU ,0x00020608U)  
+		RegMask = (DDRC_DRAMTMG12_T_CMDCKE_MASK | DDRC_DRAMTMG12_T_CKEHCMD_MASK | DDRC_DRAMTMG12_T_MRD_PDA_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_DRAMTMG12_T_CMDCKE_SHIFT
+			| 0x00000006U << DDRC_DRAMTMG12_T_CKEHCMD_SHIFT
+			| 0x00000008U << DDRC_DRAMTMG12_T_MRD_PDA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DRAMTMG12_OFFSET ,0x00030F1FU ,0x00020608U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQCTL0 @ 0XFD070180

+
+		- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
+		ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
+		ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL0_DIS_AUTO_ZQ                                                     0x1
+
+		- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
+		or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
+		own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
+		ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL0_DIS_SRX_ZQCL                                                    0x0
+
+		- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
+		nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
+		rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL0_ZQ_RESISTOR_SHARED                                              0x0
+
+		- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable 
+		ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
+		gns supporting DDR4 devices.
+		PSU_DDRC_ZQCTL0_DIS_MPSMX_ZQCL                                                  0x0
+
+		tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
+		on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
+		er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
+		ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for 
+		esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL0_T_ZQ_LONG_NOP                                                   0x100
+
+		tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
+		ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
+		e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
+		s.
+		PSU_DDRC_ZQCTL0_T_ZQ_SHORT_NOP                                                  0x40
+
+		ZQ Control Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070180, 0xF7FF03FFU ,0x81000040U)  
+		RegMask = (DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK | DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK | DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK | DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK | DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK | DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT
+			| 0x00000000U << DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT
+			| 0x00000000U << DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT
+			| 0x00000000U << DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT
+			| 0x00000100U << DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT
+			| 0x00000040U << DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ZQCTL0_OFFSET ,0xF7FF03FFU ,0x81000040U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQCTL1 @ 0XFD070184

+
+		tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
+		ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is 
+		nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL1_T_ZQ_RESET_NOP                                                  0x20
+
+		Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
+		PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs 
+		upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.
+		PSU_DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024                                       0x19707
+
+		ZQ Control Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070184, 0x3FFFFFFFU ,0x02019707U)  
+		RegMask = (DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK | DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK |  0 );
+
+		RegVal = ((0x00000020U << DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT
+			| 0x00019707U << DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ZQCTL1_OFFSET ,0x3FFFFFFFU ,0x02019707U);
+	/*############################################################################################################################ */
+
+		/*Register : DFITMG0 @ 0XFD070190

+
+		Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
+		s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
+		, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
+		 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
+		PSU_DDRC_DFITMG0_DFI_T_CTRL_DELAY                                               0x4
+
+		Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
+		0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
+		fer to PHY specification for correct value.
+		PSU_DDRC_DFITMG0_DFI_RDDATA_USE_SDR                                             0x1
+
+		Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
+		ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
+		, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
+		 latency through the RDIMM. Unit: Clocks
+		PSU_DDRC_DFITMG0_DFI_T_RDDATA_EN                                                0xb
+
+		Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
+		.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
+		HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
+		e.
+		PSU_DDRC_DFITMG0_DFI_WRDATA_USE_SDR                                             0x1
+
+		Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
+		 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
+		te, max supported value is 8. Unit: Clocks
+		PSU_DDRC_DFITMG0_DFI_TPHY_WRDATA                                                0x2
+
+		Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
+		 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
+		 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
+		rough the RDIMM.
+		PSU_DDRC_DFITMG0_DFI_TPHY_WRLAT                                                 0xb
+
+		DFI Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070190, 0x1FBFBF3FU ,0x048B820BU)  
+		RegMask = (DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK |  0 );
+
+		RegVal = ((0x00000004U << DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT
+			| 0x00000001U << DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT
+			| 0x0000000BU << DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT
+			| 0x00000001U << DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT
+			| 0x00000002U << DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT
+			| 0x0000000BU << DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFITMG0_OFFSET ,0x1FBFBF3FU ,0x048B820BU);
+	/*############################################################################################################################ */
+
+		/*Register : DFITMG1 @ 0XFD070194

+
+		Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. 
+		his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
+		the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8
+		PSU_DDRC_DFITMG1_DFI_T_CMD_LAT                                                  0x0
+
+		Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
+		 is driven.
+		PSU_DDRC_DFITMG1_DFI_T_PARIN_LAT                                                0x0
+
+		Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
+		nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
+		 correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to 
+		phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
+		RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
+		: Clocks
+		PSU_DDRC_DFITMG1_DFI_T_WRDATA_DELAY                                             0x3
+
+		Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to 
+		he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase 
+		ligned, this timing parameter should be rounded up to the next integer value.
+		PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE                                         0x3
+
+		Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first 
+		alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
+		not phase aligned, this timing parameter should be rounded up to the next integer value.
+		PSU_DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE                                          0x4
+
+		DFI Timing Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070194, 0xF31F0F0FU ,0x00030304U)  
+		RegMask = (DDRC_DFITMG1_DFI_T_CMD_LAT_MASK | DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK | DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK | DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT
+			| 0x00000000U << DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT
+			| 0x00000003U << DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT
+			| 0x00000003U << DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT
+			| 0x00000004U << DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFITMG1_OFFSET ,0xF31F0F0FU ,0x00030304U);
+	/*############################################################################################################################ */
+
+		/*Register : DFILPCFG0 @ 0XFD070198

+
+		Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
+		g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.
+		PSU_DDRC_DFILPCFG0_DFI_TLP_RESP                                                 0x7
+
+		Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
+		cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
+		- 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 
+		31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
+		.
+		PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD                                            0x0
+
+		Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
+		nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.
+		PSU_DDRC_DFILPCFG0_DFI_LP_EN_DPD                                                0x0
+
+		Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
+		les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 
+		048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
+		72 cycles - 0xE - 262144 cycles - 0xF - Unlimited
+		PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR                                             0x0
+
+		Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled
+		PSU_DDRC_DFILPCFG0_DFI_LP_EN_SR                                                 0x1
+
+		Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
+		s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
+		8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
+		 cycles - 0xE - 262144 cycles - 0xF - Unlimited
+		PSU_DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD                                             0x4
+
+		Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled
+		PSU_DDRC_DFILPCFG0_DFI_LP_EN_PD                                                 0x1
+
+		DFI Low Power Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070198, 0x0FF1F1F1U ,0x07000141U)  
+		RegMask = (DDRC_DFILPCFG0_DFI_TLP_RESP_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK | DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK | DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK | DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK |  0 );
+
+		RegVal = ((0x00000007U << DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT
+			| 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT
+			| 0x00000000U << DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT
+			| 0x00000000U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT
+			| 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT
+			| 0x00000004U << DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT
+			| 0x00000001U << DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFILPCFG0_OFFSET ,0x0FF1F1F1U ,0x07000141U);
+	/*############################################################################################################################ */
+
+		/*Register : DFILPCFG1 @ 0XFD07019C

+
+		Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
+		- 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles 
+		 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
+		D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.
+		PSU_DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM                                           0x2
+
+		Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
+		only present for designs supporting DDR4 devices.
+		PSU_DDRC_DFILPCFG1_DFI_LP_EN_MPSM                                               0x1
+
+		DFI Low Power Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD07019C, 0x000000F1U ,0x00000021U)  
+		RegMask = (DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK | DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT
+			| 0x00000001U << DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFILPCFG1_OFFSET ,0x000000F1U ,0x00000021U);
+	/*############################################################################################################################ */
+
+		/*Register : DFIUPD1 @ 0XFD0701A4

+
+		This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
+		). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
+		t read request when the uMCTL2 is idle. Unit: 1024 clocks
+		PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024                               0x41
+
+		This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; 
+		hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
+		idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
+		e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
+		Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
+		024. Unit: 1024 clocks
+		PSU_DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024                               0xe2
+
+		DFI Update Register 1
+		(OFFSET, MASK, VALUE)      (0XFD0701A4, 0x00FF00FFU ,0x004100E2U)  
+		RegMask = (DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK | DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK |  0 );
+
+		RegVal = ((0x00000041U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT
+			| 0x000000E2U << DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFIUPD1_OFFSET ,0x00FF00FFU ,0x004100E2U);
+	/*############################################################################################################################ */
+
+		/*Register : DFIMISC @ 0XFD0701B0

+
+		Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high
+		PSU_DDRC_DFIMISC_DFI_DATA_CS_POLARITY                                           0x0
+
+		DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
+		in designs configured to support DDR4 and LPDDR4.
+		PSU_DDRC_DFIMISC_PHY_DBI_MODE                                                   0x0
+
+		PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
+		ion
+		PSU_DDRC_DFIMISC_DFI_INIT_COMPLETE_EN                                           0x0
+
+		DFI Miscellaneous Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0701B0, 0x00000007U ,0x00000000U)  
+		RegMask = (DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK | DDRC_DFIMISC_PHY_DBI_MODE_MASK | DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT
+			| 0x00000000U << DDRC_DFIMISC_PHY_DBI_MODE_SHIFT
+			| 0x00000000U << DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFIMISC_OFFSET ,0x00000007U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DFITMG2 @ 0XFD0701B4

+
+		>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
+		l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.
+		PSU_DDRC_DFITMG2_DFI_TPHY_RDCSLAT                                               0x9
+
+		Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
+		l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.
+		PSU_DDRC_DFITMG2_DFI_TPHY_WRCSLAT                                               0x6
+
+		DFI Timing Register 2
+		(OFFSET, MASK, VALUE)      (0XFD0701B4, 0x00003F3FU ,0x00000906U)  
+		RegMask = (DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK | DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK |  0 );
+
+		RegVal = ((0x00000009U << DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT
+			| 0x00000006U << DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFITMG2_OFFSET ,0x00003F3FU ,0x00000906U);
+	/*############################################################################################################################ */
+
+		/*Register : DBICTL @ 0XFD0701C0

+
+		Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
+		as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]
+		PSU_DDRC_DBICTL_RD_DBI_EN                                                       0x0
+
+		Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
+		ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]
+		PSU_DDRC_DBICTL_WR_DBI_EN                                                       0x0
+
+		DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
+		mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
+		: Set this to inverted value of MR13[5] which is opposite polarity from this signal
+		PSU_DDRC_DBICTL_DM_EN                                                           0x1
+
+		DM/DBI Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0701C0, 0x00000007U ,0x00000001U)  
+		RegMask = (DDRC_DBICTL_RD_DBI_EN_MASK | DDRC_DBICTL_WR_DBI_EN_MASK | DDRC_DBICTL_DM_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DBICTL_RD_DBI_EN_SHIFT
+			| 0x00000000U << DDRC_DBICTL_WR_DBI_EN_SHIFT
+			| 0x00000001U << DDRC_DBICTL_DM_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DBICTL_OFFSET ,0x00000007U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP0 @ 0XFD070200

+
+		Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
+		 bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.
+		PSU_DDRC_ADDRMAP0_ADDRMAP_CS_BIT0                                               0x1f
+
+		Address Map Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070200, 0x0000001FU ,0x0000001FU)  
+		RegMask = (DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK |  0 );
+
+		RegVal = ((0x0000001FU << DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP0_OFFSET ,0x0000001FU ,0x0000001FU);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP1 @ 0XFD070204

+
+		Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
+		bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.
+		PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B2                                               0x1f
+
+		Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
+		r each of the bank address bits is determined by adding the internal base to the value of this field.
+		PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B1                                               0xa
+
+		Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
+		r each of the bank address bits is determined by adding the internal base to the value of this field.
+		PSU_DDRC_ADDRMAP1_ADDRMAP_BANK_B0                                               0xa
+
+		Address Map Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070204, 0x001F1F1FU ,0x001F0A0AU)  
+		RegMask = (DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK | DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK |  0 );
+
+		RegVal = ((0x0000001FU << DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT
+			| 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT
+			| 0x0000000AU << DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP1_OFFSET ,0x001F1F1FU ,0x001F0A0AU);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP2 @ 0XFD070208

+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
+		 Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
+		 this field. If set to 15, this column address bit is set to 0.
+		PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B5                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
+		Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.
+		PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B4                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
+		Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
+		ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
+		 this case.
+		PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B3                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
+		Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
+		ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.
+		PSU_DDRC_ADDRMAP2_ADDRMAP_COL_B2                                                0x0
+
+		Address Map Register 2
+		(OFFSET, MASK, VALUE)      (0XFD070208, 0x0F0F0F0FU ,0x00000000U)  
+		RegMask = (DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK | DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP2_OFFSET ,0x0F0F0F0FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP3 @ 0XFD07020C

+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
+		column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
+		 determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: 
+		er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
+		ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
+		 hence column bit 10 is used.
+		PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B9                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
+		 LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
+		ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
+		cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
+		mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
+		.
+		PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B8                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
+		Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.
+		PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B7                                                0x0
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
+		Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.
+		PSU_DDRC_ADDRMAP3_ADDRMAP_COL_B6                                                0x0
+
+		Address Map Register 3
+		(OFFSET, MASK, VALUE)      (0XFD07020C, 0x0F0F0F0FU ,0x00000000U)  
+		RegMask = (DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK | DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT
+			| 0x00000000U << DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP3_OFFSET ,0x0F0F0F0FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP4 @ 0XFD070210

+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
+		mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must 
+		e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
+		l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
+		n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
+		dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.
+		PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B11                                               0xf
+
+		- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
+		mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
+		To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
+		termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
+		JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
+		bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
+		nce column bit 10 is used.
+		PSU_DDRC_ADDRMAP4_ADDRMAP_COL_B10                                               0xf
+
+		Address Map Register 4
+		(OFFSET, MASK, VALUE)      (0XFD070210, 0x00000F0FU ,0x00000F0FU)  
+		RegMask = (DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK | DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK |  0 );
+
+		RegVal = ((0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT
+			| 0x0000000FU << DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP4_OFFSET ,0x00000F0FU ,0x00000F0FU);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP5 @ 0XFD070214

+
+		Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.
+		PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B11                                               0x8
+
+		Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
+		bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF 
+		ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value 
+		5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.
+		PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10                                             0xf
+
+		Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field.
+		PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B1                                                0x8
+
+		Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field.
+		PSU_DDRC_ADDRMAP5_ADDRMAP_ROW_B0                                                0x8
+
+		Address Map Register 5
+		(OFFSET, MASK, VALUE)      (0XFD070214, 0x0F0F0F0FU ,0x080F0808U)  
+		RegMask = (DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK | DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT
+			| 0x0000000FU << DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP5_OFFSET ,0x0F0F0F0FU ,0x080F0808U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP6 @ 0XFD070218

+
+		Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
+		having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
+		y in designs configured to support LPDDR3.
+		PSU_DDRC_ADDRMAP6_LPDDR3_6GB_12GB                                               0x0
+
+		Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.
+		PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B15                                               0xf
+
+		Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.
+		PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B14                                               0x8
+
+		Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.
+		PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B13                                               0x8
+
+		Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.
+		PSU_DDRC_ADDRMAP6_ADDRMAP_ROW_B12                                               0x8
+
+		Address Map Register 6
+		(OFFSET, MASK, VALUE)      (0XFD070218, 0x8F0F0F0FU ,0x0F080808U)  
+		RegMask = (DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK | DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT
+			| 0x0000000FU << DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP6_OFFSET ,0x8F0F0F0FU ,0x0F080808U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP7 @ 0XFD07021C

+
+		Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.
+		PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B17                                               0xf
+
+		Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.
+		PSU_DDRC_ADDRMAP7_ADDRMAP_ROW_B16                                               0xf
+
+		Address Map Register 7
+		(OFFSET, MASK, VALUE)      (0XFD07021C, 0x00000F0FU ,0x00000F0FU)  
+		RegMask = (DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK | DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK |  0 );
+
+		RegVal = ((0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT
+			| 0x0000000FU << DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP7_OFFSET ,0x00000F0FU ,0x00000F0FU);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP8 @ 0XFD070220

+
+		Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
+		address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If 
+		et to 31, bank group address bit 1 is set to 0.
+		PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B1                                                 0x8
+
+		Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
+		bit for each of the bank group address bits is determined by adding the internal base to the value of this field.
+		PSU_DDRC_ADDRMAP8_ADDRMAP_BG_B0                                                 0x8
+
+		Address Map Register 8
+		(OFFSET, MASK, VALUE)      (0XFD070220, 0x00001F1FU ,0x00000808U)  
+		RegMask = (DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK | DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP8_OFFSET ,0x00001F1FU ,0x00000808U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP9 @ 0XFD070224

+
+		Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B5                                                0x8
+
+		Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B4                                                0x8
+
+		Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
+		d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B3                                                0x8
+
+		Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
+		d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP9_ADDRMAP_ROW_B2                                                0x8
+
+		Address Map Register 9
+		(OFFSET, MASK, VALUE)      (0XFD070224, 0x0F0F0F0FU ,0x08080808U)  
+		RegMask = (DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK | DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP9_OFFSET ,0x0F0F0F0FU ,0x08080808U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP10 @ 0XFD070228

+
+		Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B9                                               0x8
+
+		Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B8                                               0x8
+
+		Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B7                                               0x8
+
+		Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP10_ADDRMAP_ROW_B6                                               0x8
+
+		Address Map Register 10
+		(OFFSET, MASK, VALUE)      (0XFD070228, 0x0F0F0F0FU ,0x08080808U)  
+		RegMask = (DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK | DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT
+			| 0x00000008U << DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP10_OFFSET ,0x0F0F0F0FU ,0x08080808U);
+	/*############################################################################################################################ */
+
+		/*Register : ADDRMAP11 @ 0XFD07022C

+
+		Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit 
+		or each of the row address bits is determined by adding the internal base to the value of this field. This register field is 
+		sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.
+		PSU_DDRC_ADDRMAP11_ADDRMAP_ROW_B10                                              0x8
+
+		Address Map Register 11
+		(OFFSET, MASK, VALUE)      (0XFD07022C, 0x0000000FU ,0x00000008U)  
+		RegMask = (DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ADDRMAP11_OFFSET ,0x0000000FU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : ODTCFG @ 0XFD070240

+
+		Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
+		67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - 
+		L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 
+		CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)
+		PSU_DDRC_ODTCFG_WR_ODT_HOLD                                                     0x6
+
+		The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
+		remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
+		67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
+		 DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))
+		PSU_DDRC_ODTCFG_WR_ODT_DELAY                                                    0x0
+
+		Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
+		 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
+		tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
+		)
+		PSU_DDRC_ODTCFG_RD_ODT_HOLD                                                     0x6
+
+		The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must 
+		emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
+		CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
+		L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
+		write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
+		uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)
+		PSU_DDRC_ODTCFG_RD_ODT_DELAY                                                    0x0
+
+		ODT Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD070240, 0x0F1F0F7CU ,0x06000600U)  
+		RegMask = (DDRC_ODTCFG_WR_ODT_HOLD_MASK | DDRC_ODTCFG_WR_ODT_DELAY_MASK | DDRC_ODTCFG_RD_ODT_HOLD_MASK | DDRC_ODTCFG_RD_ODT_DELAY_MASK |  0 );
+
+		RegVal = ((0x00000006U << DDRC_ODTCFG_WR_ODT_HOLD_SHIFT
+			| 0x00000000U << DDRC_ODTCFG_WR_ODT_DELAY_SHIFT
+			| 0x00000006U << DDRC_ODTCFG_RD_ODT_HOLD_SHIFT
+			| 0x00000000U << DDRC_ODTCFG_RD_ODT_DELAY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ODTCFG_OFFSET ,0x0F1F0F7CU ,0x06000600U);
+	/*############################################################################################################################ */
+
+		/*Register : ODTMAP @ 0XFD070244

+
+		Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can 
+		e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
+		 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
+		PSU_DDRC_ODTMAP_RANK1_RD_ODT                                                    0x0
+
+		Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
+		 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
+		etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks
+		PSU_DDRC_ODTMAP_RANK1_WR_ODT                                                    0x0
+
+		Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can 
+		e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
+		 etc. For each rank, set its bit to 1 to enable its ODT.
+		PSU_DDRC_ODTMAP_RANK0_RD_ODT                                                    0x0
+
+		Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
+		 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
+		etc. For each rank, set its bit to 1 to enable its ODT.
+		PSU_DDRC_ODTMAP_RANK0_WR_ODT                                                    0x1
+
+		ODT/Rank Map Register
+		(OFFSET, MASK, VALUE)      (0XFD070244, 0x00003333U ,0x00000001U)  
+		RegMask = (DDRC_ODTMAP_RANK1_RD_ODT_MASK | DDRC_ODTMAP_RANK1_WR_ODT_MASK | DDRC_ODTMAP_RANK0_RD_ODT_MASK | DDRC_ODTMAP_RANK0_WR_ODT_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_ODTMAP_RANK1_RD_ODT_SHIFT
+			| 0x00000000U << DDRC_ODTMAP_RANK1_WR_ODT_SHIFT
+			| 0x00000000U << DDRC_ODTMAP_RANK0_RD_ODT_SHIFT
+			| 0x00000001U << DDRC_ODTMAP_RANK0_WR_ODT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_ODTMAP_OFFSET ,0x00003333U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : SCHED @ 0XFD070250

+
+		When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
+		non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
+		ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this 
+		egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. 
+		OR PERFORMANCE ONLY
+		PSU_DDRC_SCHED_RDWR_IDLE_GAP                                                    0x1
+
+		UNUSED
+		PSU_DDRC_SCHED_GO2CRITICAL_HYSTERESIS                                           0x0
+
+		Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
+		 the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
+		to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
+		priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
+		 than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
+		sing out of single bit error correction RMW operation.
+		PSU_DDRC_SCHED_LPR_NUM_ENTRIES                                                  0x20
+
+		If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
+		e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this 
+		egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
+		es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed 
+		s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
+		ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open 
+		age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
+		ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.
+		PSU_DDRC_SCHED_PAGECLOSE                                                        0x0
+
+		If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.
+		PSU_DDRC_SCHED_PREFER_WRITE                                                     0x0
+
+		Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
+		ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
+		e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
+		ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.
+		PSU_DDRC_SCHED_FORCE_LOW_PRI_N                                                  0x1
+
+		Scheduler Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070250, 0x7FFF3F07U ,0x01002001U)  
+		RegMask = (DDRC_SCHED_RDWR_IDLE_GAP_MASK | DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK | DDRC_SCHED_LPR_NUM_ENTRIES_MASK | DDRC_SCHED_PAGECLOSE_MASK | DDRC_SCHED_PREFER_WRITE_MASK | DDRC_SCHED_FORCE_LOW_PRI_N_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_SCHED_RDWR_IDLE_GAP_SHIFT
+			| 0x00000000U << DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT
+			| 0x00000020U << DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT
+			| 0x00000000U << DDRC_SCHED_PAGECLOSE_SHIFT
+			| 0x00000000U << DDRC_SCHED_PREFER_WRITE_SHIFT
+			| 0x00000001U << DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SCHED_OFFSET ,0x7FFF3F07U ,0x01002001U);
+	/*############################################################################################################################ */
+
+		/*Register : PERFLPR1 @ 0XFD070264

+
+		Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
+		 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH                                           0x8
+
+		Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
+		er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
+		be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PERFLPR1_LPR_MAX_STARVE                                                0x40
+
+		Low Priority Read CAM Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070264, 0xFF00FFFFU ,0x08000040U)  
+		RegMask = (DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK | DDRC_PERFLPR1_LPR_MAX_STARVE_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT
+			| 0x00000040U << DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PERFLPR1_OFFSET ,0xFF00FFFFU ,0x08000040U);
+	/*############################################################################################################################ */
+
+		/*Register : PERFWR1 @ 0XFD07026C

+
+		Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
+		transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PERFWR1_W_XACT_RUN_LENGTH                                              0x8
+
+		Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
+		r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not 
+		e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.
+		PSU_DDRC_PERFWR1_W_MAX_STARVE                                                   0x40
+
+		Write CAM Register 1
+		(OFFSET, MASK, VALUE)      (0XFD07026C, 0xFF00FFFFU ,0x08000040U)  
+		RegMask = (DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK | DDRC_PERFWR1_W_MAX_STARVE_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT
+			| 0x00000040U << DDRC_PERFWR1_W_MAX_STARVE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PERFWR1_OFFSET ,0xFF00FFFFU ,0x08000040U);
+	/*############################################################################################################################ */
+
+		/*Register : DQMAP5 @ 0XFD070294

+
+		All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
+		all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and 
+		wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
+		port DDR4.
+		PSU_DDRC_DQMAP5_DIS_DQ_RANK_SWAP                                                0x1
+
+		DQ Map Register 5
+		(OFFSET, MASK, VALUE)      (0XFD070294, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DQMAP5_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : DBG0 @ 0XFD070300

+
+		When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
+		lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
+		s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.
+		PSU_DDRC_DBG0_DIS_COLLISION_PAGE_OPT                                            0x0
+
+		When 1, disable write combine. FOR DEBUG ONLY
+		PSU_DDRC_DBG0_DIS_WC                                                            0x0
+
+		Debug Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070300, 0x00000011U ,0x00000000U)  
+		RegMask = (DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK | DDRC_DBG0_DIS_WC_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT
+			| 0x00000000U << DDRC_DBG0_DIS_WC_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DBG0_OFFSET ,0x00000011U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DBGCMD @ 0XFD07030C

+
+		Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
+		the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
+		register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
+		_refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
+		 and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).
+		PSU_DDRC_DBGCMD_HW_REF_ZQ_EN                                                    0x0
+
+		Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in 
+		he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.
+		PSU_DDRC_DBGCMD_CTRLUPD                                                         0x0
+
+		Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to 
+		he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
+		en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
+		d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
+		de.
+		PSU_DDRC_DBGCMD_ZQ_CALIB_SHORT                                                  0x0
+
+		Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
+		refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
+		be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
+		wn operating modes or Maximum Power Saving Mode.
+		PSU_DDRC_DBGCMD_RANK1_REFRESH                                                   0x0
+
+		Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
+		refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
+		be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
+		wn operating modes or Maximum Power Saving Mode.
+		PSU_DDRC_DBGCMD_RANK0_REFRESH                                                   0x0
+
+		Command Debug Register
+		(OFFSET, MASK, VALUE)      (0XFD07030C, 0x80000033U ,0x00000000U)  
+		RegMask = (DDRC_DBGCMD_HW_REF_ZQ_EN_MASK | DDRC_DBGCMD_CTRLUPD_MASK | DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK | DDRC_DBGCMD_RANK1_REFRESH_MASK | DDRC_DBGCMD_RANK0_REFRESH_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT
+			| 0x00000000U << DDRC_DBGCMD_CTRLUPD_SHIFT
+			| 0x00000000U << DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT
+			| 0x00000000U << DDRC_DBGCMD_RANK1_REFRESH_SHIFT
+			| 0x00000000U << DDRC_DBGCMD_RANK0_REFRESH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DBGCMD_OFFSET ,0x80000033U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : SWCTL @ 0XFD070320

+
+		Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back 
+		egister to 1 once programming is done.
+		PSU_DDRC_SWCTL_SW_DONE                                                          0x0
+
+		Software register programming control enable
+		(OFFSET, MASK, VALUE)      (0XFD070320, 0x00000001U ,0x00000000U)  
+		RegMask = (DDRC_SWCTL_SW_DONE_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_SWCTL_SW_DONE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SWCTL_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : PCCFG @ 0XFD070400

+
+		Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
+		e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
+		h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
+		ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
+		_mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
+		ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
+		DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
+		only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
+		-AC is enabled
+		PSU_DDRC_PCCFG_BL_EXP_MODE                                                      0x0
+
+		Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
+		rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
+		ge DDRC transactions.
+		PSU_DDRC_PCCFG_PAGEMATCH_LIMIT                                                  0x0
+
+		If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based 
+		n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
+		_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.
+		PSU_DDRC_PCCFG_GO2CRITICAL_EN                                                   0x1
+
+		Port Common Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD070400, 0x00000111U ,0x00000001U)  
+		RegMask = (DDRC_PCCFG_BL_EXP_MODE_MASK | DDRC_PCCFG_PAGEMATCH_LIMIT_MASK | DDRC_PCCFG_GO2CRITICAL_EN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCCFG_BL_EXP_MODE_SHIFT
+			| 0x00000000U << DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT
+			| 0x00000001U << DDRC_PCCFG_GO2CRITICAL_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCCFG_OFFSET ,0x00000111U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_0 @ 0XFD070404

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_0_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_0_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_0_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD070404, 0x000073FFU ,0x0000200FU)  
+		RegMask = (DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_0_OFFSET ,0x000073FFU ,0x0000200FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_0 @ 0XFD070408

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_0_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_0_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_0_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD070408, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_0_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_0 @ 0XFD070490

+
+		Enables port n.
+		PSU_DDRC_PCTRL_0_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070490, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_0_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_0_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_0_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_0 @ 0XFD070494

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION1                                            0x2
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_0_RQOS_MAP_REGION0                                            0x0
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1                                             0xb
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070494, 0x0033000FU ,0x0020000BU)  
+		RegMask = (DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT
+			| 0x0000000BU << DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_0_OFFSET ,0x0033000FU ,0x0020000BU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_0 @ 0XFD070498

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB                                           0x0
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070498, 0x07FF07FFU ,0x00000000U)  
+		RegMask = (DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_0_OFFSET ,0x07FF07FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_1 @ 0XFD0704B4

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_1_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_1_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_1_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD0704B4, 0x000073FFU ,0x0000200FU)  
+		RegMask = (DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_1_OFFSET ,0x000073FFU ,0x0000200FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_1 @ 0XFD0704B8

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_1_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_1_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_1_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD0704B8, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_1_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_1 @ 0XFD070540

+
+		Enables port n.
+		PSU_DDRC_PCTRL_1_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070540, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_1_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_1_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_1_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_1 @ 0XFD070544

+
+		This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 
+		ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 
+		s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION2                                            0x2
+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION1                                            0x0
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_1_RQOS_MAP_REGION0                                            0x0
+
+		Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
+		el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
+		directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 
+		ust be set to distinct values.
+		PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2                                             0xb
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1                                             0x3
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070544, 0x03330F0FU ,0x02000B03U)  
+		RegMask = (DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT
+			| 0x0000000BU << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT
+			| 0x00000003U << DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_1_OFFSET ,0x03330F0FU ,0x02000B03U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_1 @ 0XFD070548

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB                                           0x0
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070548, 0x07FF07FFU ,0x00000000U)  
+		RegMask = (DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_1_OFFSET ,0x07FF07FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_2 @ 0XFD070564

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_2_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_2_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_2_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD070564, 0x000073FFU ,0x0000200FU)  
+		RegMask = (DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_2_OFFSET ,0x000073FFU ,0x0000200FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_2 @ 0XFD070568

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_2_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_2_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_2_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD070568, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_2_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_2 @ 0XFD0705F0

+
+		Enables port n.
+		PSU_DDRC_PCTRL_2_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0705F0, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_2_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_2_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_2_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_2 @ 0XFD0705F4

+
+		This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 
+		ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 
+		s set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION2                                            0x2
+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION1                                            0x0
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_2_RQOS_MAP_REGION0                                            0x0
+
+		Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
+		el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
+		directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 
+		ust be set to distinct values.
+		PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2                                             0xb
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1                                             0x3
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0705F4, 0x03330F0FU ,0x02000B03U)  
+		RegMask = (DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK | DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT
+			| 0x0000000BU << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT
+			| 0x00000003U << DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_2_OFFSET ,0x03330F0FU ,0x02000B03U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_2 @ 0XFD0705F8

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB                                           0x0
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD0705F8, 0x07FF07FFU ,0x00000000U)  
+		RegMask = (DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_2_OFFSET ,0x07FF07FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_3 @ 0XFD070614

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_3_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_3_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_3_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD070614, 0x000073FFU ,0x0000200FU)  
+		RegMask = (DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_3_OFFSET ,0x000073FFU ,0x0000200FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_3 @ 0XFD070618

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_3_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_3_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_3_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD070618, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_3_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_3 @ 0XFD0706A0

+
+		Enables port n.
+		PSU_DDRC_PCTRL_3_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0706A0, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_3_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_3_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_3_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_3 @ 0XFD0706A4

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION1                                            0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_3_RQOS_MAP_REGION0                                            0x0
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1                                             0x3
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0706A4, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_3_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_3 @ 0XFD0706A8

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB                                           0x4f
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD0706A8, 0x07FF07FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x0000004FU << DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_3_OFFSET ,0x07FF07FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS0_3 @ 0XFD0706AC

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
+		PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1                                           0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
+		PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0                                           0x0
+
+		Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.
+		PSU_DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL                                             0x3
+
+		Port n Write QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0706AC, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS0_3_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS1_3 @ 0XFD0706B0

+
+		Specifies the timeout value for write transactions.
+		PSU_DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT                                           0x4f
+
+		Port n Write QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD0706B0, 0x000007FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK |  0 );
+
+		RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS1_3_OFFSET ,0x000007FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_4 @ 0XFD0706C4

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_4_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_4_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_4_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD0706C4, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_4_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_4 @ 0XFD0706C8

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_4_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_4_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_4_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD0706C8, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_4_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_4 @ 0XFD070750

+
+		Enables port n.
+		PSU_DDRC_PCTRL_4_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070750, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_4_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_4_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_4_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_4 @ 0XFD070754

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION1                                            0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_4_RQOS_MAP_REGION0                                            0x0
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1                                             0x3
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070754, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_4_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_4 @ 0XFD070758

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB                                           0x4f
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070758, 0x07FF07FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x0000004FU << DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_4_OFFSET ,0x07FF07FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS0_4 @ 0XFD07075C

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
+		PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1                                           0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
+		PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0                                           0x0
+
+		Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.
+		PSU_DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL                                             0x3
+
+		Port n Write QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD07075C, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS0_4_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS1_4 @ 0XFD070760

+
+		Specifies the timeout value for write transactions.
+		PSU_DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT                                           0x4f
+
+		Port n Write QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070760, 0x000007FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK |  0 );
+
+		RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS1_4_OFFSET ,0x000007FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGR_5 @ 0XFD070774

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN                                           0x0
+
+		If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).
+		PSU_DDRC_PCFGR_5_RD_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the read channel of the port.
+		PSU_DDRC_PCFGR_5_RD_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGR_5_RD_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Read Register
+		(OFFSET, MASK, VALUE)      (0XFD070774, 0x000073FFU ,0x0000200FU)  
+		RegMask = (DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK | DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK | DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGR_5_OFFSET ,0x000073FFU ,0x0000200FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGW_5 @ 0XFD070778

+
+		If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.
+		PSU_DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN                                           0x1
+
+		If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).
+		PSU_DDRC_PCFGW_5_WR_PORT_URGENT_EN                                              0x1
+
+		If set to 1, enables aging function for the write channel of the port.
+		PSU_DDRC_PCFGW_5_WR_PORT_AGING_EN                                               0x0
+
+		Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.
+		PSU_DDRC_PCFGW_5_WR_PORT_PRIORITY                                               0xf
+
+		Port n Configuration Write Register
+		(OFFSET, MASK, VALUE)      (0XFD070778, 0x000073FFU ,0x0000600FU)  
+		RegMask = (DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK | DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK | DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK | DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT
+			| 0x00000001U << DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT
+			| 0x00000000U << DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT
+			| 0x0000000FU << DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGW_5_OFFSET ,0x000073FFU ,0x0000600FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCTRL_5 @ 0XFD070800

+
+		Enables port n.
+		PSU_DDRC_PCTRL_5_PORT_EN                                                        0x1
+
+		Port n Control Register
+		(OFFSET, MASK, VALUE)      (0XFD070800, 0x00000001U ,0x00000001U)  
+		RegMask = (DDRC_PCTRL_5_PORT_EN_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCTRL_5_PORT_EN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCTRL_5_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS0_5 @ 0XFD070804

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION1                                            0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.
+		PSU_DDRC_PCFGQOS0_5_RQOS_MAP_REGION0                                            0x0
+
+		Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.
+		PSU_DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1                                             0x3
+
+		Port n Read QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD070804, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK | DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS0_5_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGQOS1_5 @ 0XFD070808

+
+		Specifies the timeout value for transactions mapped to the red address queue.
+		PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR                                           0x0
+
+		Specifies the timeout value for transactions mapped to the blue address queue.
+		PSU_DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB                                           0x4f
+
+		Port n Read QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070808, 0x07FF07FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK | DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT
+			| 0x0000004FU << DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGQOS1_5_OFFSET ,0x07FF07FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS0_5 @ 0XFD07080C

+
+		This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.
+		PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1                                           0x1
+
+		This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.
+		PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0                                           0x0
+
+		Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.
+		PSU_DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL                                             0x3
+
+		Port n Write QoS Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD07080C, 0x0033000FU ,0x00100003U)  
+		RegMask = (DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK | DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT
+			| 0x00000000U << DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT
+			| 0x00000003U << DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS0_5_OFFSET ,0x0033000FU ,0x00100003U);
+	/*############################################################################################################################ */
+
+		/*Register : PCFGWQOS1_5 @ 0XFD070810

+
+		Specifies the timeout value for write transactions.
+		PSU_DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT                                           0x4f
+
+		Port n Write QoS Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD070810, 0x000007FFU ,0x0000004FU)  
+		RegMask = (DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK |  0 );
+
+		RegVal = ((0x0000004FU << DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_PCFGWQOS1_5_OFFSET ,0x000007FFU ,0x0000004FU);
+	/*############################################################################################################################ */
+
+		/*Register : SARBASE0 @ 0XFD070F04

+
+		Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
+		 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
+		PSU_DDRC_SARBASE0_BASE_ADDR                                                     0x0
+
+		SAR Base Address Register n
+		(OFFSET, MASK, VALUE)      (0XFD070F04, 0x000001FFU ,0x00000000U)  
+		RegMask = (DDRC_SARBASE0_BASE_ADDR_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_SARBASE0_BASE_ADDR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SARBASE0_OFFSET ,0x000001FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : SARSIZE0 @ 0XFD070F08

+
+		Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
+		e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 
+		or example, if register is programmed to 0, region will have 1 block.
+		PSU_DDRC_SARSIZE0_NBLOCKS                                                       0x0
+
+		SAR Size Register n
+		(OFFSET, MASK, VALUE)      (0XFD070F08, 0x000000FFU ,0x00000000U)  
+		RegMask = (DDRC_SARSIZE0_NBLOCKS_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDRC_SARSIZE0_NBLOCKS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SARSIZE0_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : SARBASE1 @ 0XFD070F0C

+
+		Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
+		 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).
+		PSU_DDRC_SARBASE1_BASE_ADDR                                                     0x10
+
+		SAR Base Address Register n
+		(OFFSET, MASK, VALUE)      (0XFD070F0C, 0x000001FFU ,0x00000010U)  
+		RegMask = (DDRC_SARBASE1_BASE_ADDR_MASK |  0 );
+
+		RegVal = ((0x00000010U << DDRC_SARBASE1_BASE_ADDR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SARBASE1_OFFSET ,0x000001FFU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : SARSIZE1 @ 0XFD070F10

+
+		Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
+		e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 
+		or example, if register is programmed to 0, region will have 1 block.
+		PSU_DDRC_SARSIZE1_NBLOCKS                                                       0xf
+
+		SAR Size Register n
+		(OFFSET, MASK, VALUE)      (0XFD070F10, 0x000000FFU ,0x0000000FU)  
+		RegMask = (DDRC_SARSIZE1_NBLOCKS_MASK |  0 );
+
+		RegVal = ((0x0000000FU << DDRC_SARSIZE1_NBLOCKS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_SARSIZE1_OFFSET ,0x000000FFU ,0x0000000FU);
+	/*############################################################################################################################ */
+
+		/*Register : DFITMG0_SHADOW @ 0XFD072190

+
+		Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
+		s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
+		, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
+		 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.
+		PSU_DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY                                        0x7
+
+		Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
+		0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
+		fer to PHY specification for correct value.
+		PSU_DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR                                      0x1
+
+		Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
+		ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
+		, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
+		 latency through the RDIMM. Unit: Clocks
+		PSU_DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN                                         0x2
+
+		Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
+		.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
+		HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
+		e.
+		PSU_DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR                                      0x1
+
+		Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
+		 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
+		te, max supported value is 8. Unit: Clocks
+		PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA                                         0x0
+
+		Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
+		 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
+		 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
+		rough the RDIMM.
+		PSU_DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT                                          0x2
+
+		DFI Timing Shadow Register 0
+		(OFFSET, MASK, VALUE)      (0XFD072190, 0x1FBFBF3FU ,0x07828002U)  
+		RegMask = (DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK | DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK | DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK | DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK |  0 );
+
+		RegVal = ((0x00000007U << DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT
+			| 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT
+			| 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT
+			| 0x00000001U << DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT
+			| 0x00000000U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT
+			| 0x00000002U << DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDRC_DFITMG0_SHADOW_OFFSET ,0x1FBFBF3FU ,0x07828002U);
+	/*############################################################################################################################ */
+
+		// : DDR CONTROLLER RESET
+		/*Register : RST_DDR_SS @ 0XFD1A0108

+
+		DDR block level reset inside of the DDR Sub System
+		PSU_CRF_APB_RST_DDR_SS_DDR_RESET                                                0X0
+
+		DDR sub system block level reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0108, 0x00000008U ,0x00000000U)  
+		RegMask = (CRF_APB_RST_DDR_SS_DDR_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_DDR_SS_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : DDR PHY
+		/*Register : PGCR0 @ 0XFD080010

+
+		Address Copy
+		PSU_DDR_PHY_PGCR0_ADCP                                                          0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_PGCR0_RESERVED_30_27                                                0x0
+
+		PHY FIFO Reset
+		PSU_DDR_PHY_PGCR0_PHYFRST                                                       0x1
+
+		Oscillator Mode Address/Command Delay Line Select
+		PSU_DDR_PHY_PGCR0_OSCACDL                                                       0x3
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_PGCR0_RESERVED_23_19                                                0x0
+
+		Digital Test Output Select
+		PSU_DDR_PHY_PGCR0_DTOSEL                                                        0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_PGCR0_RESERVED_13                                                   0x0
+
+		Oscillator Mode Division
+		PSU_DDR_PHY_PGCR0_OSCDIV                                                        0xf
+
+		Oscillator Enable
+		PSU_DDR_PHY_PGCR0_OSCEN                                                         0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_PGCR0_RESERVED_7_0                                                  0x0
+
+		PHY General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080010, 0xFFFFFFFFU ,0x07001E00U)  
+		RegMask = (DDR_PHY_PGCR0_ADCP_MASK | DDR_PHY_PGCR0_RESERVED_30_27_MASK | DDR_PHY_PGCR0_PHYFRST_MASK | DDR_PHY_PGCR0_OSCACDL_MASK | DDR_PHY_PGCR0_RESERVED_23_19_MASK | DDR_PHY_PGCR0_DTOSEL_MASK | DDR_PHY_PGCR0_RESERVED_13_MASK | DDR_PHY_PGCR0_OSCDIV_MASK | DDR_PHY_PGCR0_OSCEN_MASK | DDR_PHY_PGCR0_RESERVED_7_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_PGCR0_ADCP_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_RESERVED_30_27_SHIFT
+			| 0x00000001U << DDR_PHY_PGCR0_PHYFRST_SHIFT
+			| 0x00000003U << DDR_PHY_PGCR0_OSCACDL_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_RESERVED_23_19_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_DTOSEL_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_RESERVED_13_SHIFT
+			| 0x0000000FU << DDR_PHY_PGCR0_OSCDIV_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_OSCEN_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR0_RESERVED_7_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PGCR0_OFFSET ,0xFFFFFFFFU ,0x07001E00U);
+	/*############################################################################################################################ */
+
+		/*Register : PGCR2 @ 0XFD080018

+
+		Clear Training Status Registers
+		PSU_DDR_PHY_PGCR2_CLRTSTAT                                                      0x0
+
+		Clear Impedance Calibration
+		PSU_DDR_PHY_PGCR2_CLRZCAL                                                       0x0
+
+		Clear Parity Error
+		PSU_DDR_PHY_PGCR2_CLRPERR                                                       0x0
+
+		Initialization Complete Pin Configuration
+		PSU_DDR_PHY_PGCR2_ICPC                                                          0x0
+
+		Data Training PUB Mode Exit Timer
+		PSU_DDR_PHY_PGCR2_DTPMXTMR                                                      0xf
+
+		Initialization Bypass
+		PSU_DDR_PHY_PGCR2_INITFSMBYP                                                    0x0
+
+		PLL FSM Bypass
+		PSU_DDR_PHY_PGCR2_PLLFSMBYP                                                     0x0
+
+		Refresh Period
+		PSU_DDR_PHY_PGCR2_TREFPRD                                                       0x12302
+
+		PHY General Configuration Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080018, 0xFFFFFFFFU ,0x00F12302U)  
+		RegMask = (DDR_PHY_PGCR2_CLRTSTAT_MASK | DDR_PHY_PGCR2_CLRZCAL_MASK | DDR_PHY_PGCR2_CLRPERR_MASK | DDR_PHY_PGCR2_ICPC_MASK | DDR_PHY_PGCR2_DTPMXTMR_MASK | DDR_PHY_PGCR2_INITFSMBYP_MASK | DDR_PHY_PGCR2_PLLFSMBYP_MASK | DDR_PHY_PGCR2_TREFPRD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_PGCR2_CLRTSTAT_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR2_CLRZCAL_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR2_CLRPERR_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR2_ICPC_SHIFT
+			| 0x0000000FU << DDR_PHY_PGCR2_DTPMXTMR_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR2_INITFSMBYP_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR2_PLLFSMBYP_SHIFT
+			| 0x00012302U << DDR_PHY_PGCR2_TREFPRD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PGCR2_OFFSET ,0xFFFFFFFFU ,0x00F12302U);
+	/*############################################################################################################################ */
+
+		/*Register : PGCR5 @ 0XFD080024

+
+		Frequency B Ratio Term
+		PSU_DDR_PHY_PGCR5_FRQBT                                                         0x1
+
+		Frequency A Ratio Term
+		PSU_DDR_PHY_PGCR5_FRQAT                                                         0x1
+
+		DFI Disconnect Time Period
+		PSU_DDR_PHY_PGCR5_DISCNPERIOD                                                   0x0
+
+		Receiver bias core side control
+		PSU_DDR_PHY_PGCR5_VREF_RBCTRL                                                   0xf
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_PGCR5_RESERVED_3                                                    0x0
+
+		Internal VREF generator REFSEL ragne select
+		PSU_DDR_PHY_PGCR5_DXREFISELRANGE                                                0x1
+
+		DDL Page Read Write select
+		PSU_DDR_PHY_PGCR5_DDLPGACT                                                      0x0
+
+		DDL Page Read Write select
+		PSU_DDR_PHY_PGCR5_DDLPGRW                                                       0x0
+
+		PHY General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080024, 0xFFFFFFFFU ,0x010100F4U)  
+		RegMask = (DDR_PHY_PGCR5_FRQBT_MASK | DDR_PHY_PGCR5_FRQAT_MASK | DDR_PHY_PGCR5_DISCNPERIOD_MASK | DDR_PHY_PGCR5_VREF_RBCTRL_MASK | DDR_PHY_PGCR5_RESERVED_3_MASK | DDR_PHY_PGCR5_DXREFISELRANGE_MASK | DDR_PHY_PGCR5_DDLPGACT_MASK | DDR_PHY_PGCR5_DDLPGRW_MASK |  0 );
+
+		RegVal = ((0x00000001U << DDR_PHY_PGCR5_FRQBT_SHIFT
+			| 0x00000001U << DDR_PHY_PGCR5_FRQAT_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR5_DISCNPERIOD_SHIFT
+			| 0x0000000FU << DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR5_RESERVED_3_SHIFT
+			| 0x00000001U << DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR5_DDLPGACT_SHIFT
+			| 0x00000000U << DDR_PHY_PGCR5_DDLPGRW_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PGCR5_OFFSET ,0xFFFFFFFFU ,0x010100F4U);
+	/*############################################################################################################################ */
+
+		/*Register : PTR0 @ 0XFD080040

+
+		PLL Power-Down Time
+		PSU_DDR_PHY_PTR0_TPLLPD                                                         0x2f0
+
+		PLL Gear Shift Time
+		PSU_DDR_PHY_PTR0_TPLLGS                                                         0x60
+
+		PHY Reset Time
+		PSU_DDR_PHY_PTR0_TPHYRST                                                        0x10
+
+		PHY Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080040, 0xFFFFFFFFU ,0x5E001810U)  
+		RegMask = (DDR_PHY_PTR0_TPLLPD_MASK | DDR_PHY_PTR0_TPLLGS_MASK | DDR_PHY_PTR0_TPHYRST_MASK |  0 );
+
+		RegVal = ((0x000002F0U << DDR_PHY_PTR0_TPLLPD_SHIFT
+			| 0x00000060U << DDR_PHY_PTR0_TPLLGS_SHIFT
+			| 0x00000010U << DDR_PHY_PTR0_TPHYRST_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PTR0_OFFSET ,0xFFFFFFFFU ,0x5E001810U);
+	/*############################################################################################################################ */
+
+		/*Register : PTR1 @ 0XFD080044

+
+		PLL Lock Time
+		PSU_DDR_PHY_PTR1_TPLLLOCK                                                       0x80
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_PTR1_RESERVED_15_13                                                 0x0
+
+		PLL Reset Time
+		PSU_DDR_PHY_PTR1_TPLLRST                                                        0x5f0
+
+		PHY Timing Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080044, 0xFFFFFFFFU ,0x008005F0U)  
+		RegMask = (DDR_PHY_PTR1_TPLLLOCK_MASK | DDR_PHY_PTR1_RESERVED_15_13_MASK | DDR_PHY_PTR1_TPLLRST_MASK |  0 );
+
+		RegVal = ((0x00000080U << DDR_PHY_PTR1_TPLLLOCK_SHIFT
+			| 0x00000000U << DDR_PHY_PTR1_RESERVED_15_13_SHIFT
+			| 0x000005F0U << DDR_PHY_PTR1_TPLLRST_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PTR1_OFFSET ,0xFFFFFFFFU ,0x008005F0U);
+	/*############################################################################################################################ */
+
+		/*Register : DSGCR @ 0XFD080090

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DSGCR_RESERVED_31_28                                                0x0
+
+		When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
+		fault calculation.
+		PSU_DDR_PHY_DSGCR_RDBICLSEL                                                     0x0
+
+		When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.
+		PSU_DDR_PHY_DSGCR_RDBICL                                                        0x2
+
+		PHY Impedance Update Enable
+		PSU_DDR_PHY_DSGCR_PHYZUEN                                                       0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DSGCR_RESERVED_22                                                   0x0
+
+		SDRAM Reset Output Enable
+		PSU_DDR_PHY_DSGCR_RSTOE                                                         0x1
+
+		Single Data Rate Mode
+		PSU_DDR_PHY_DSGCR_SDRMODE                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DSGCR_RESERVED_18                                                   0x0
+
+		ATO Analog Test Enable
+		PSU_DDR_PHY_DSGCR_ATOAE                                                         0x0
+
+		DTO Output Enable
+		PSU_DDR_PHY_DSGCR_DTOOE                                                         0x0
+
+		DTO I/O Mode
+		PSU_DDR_PHY_DSGCR_DTOIOM                                                        0x0
+
+		DTO Power Down Receiver
+		PSU_DDR_PHY_DSGCR_DTOPDR                                                        0x1
+
+		Reserved. Return zeroes on reads
+		PSU_DDR_PHY_DSGCR_RESERVED_13                                                   0x0
+
+		DTO On-Die Termination
+		PSU_DDR_PHY_DSGCR_DTOODT                                                        0x0
+
+		PHY Update Acknowledge Delay
+		PSU_DDR_PHY_DSGCR_PUAD                                                          0x4
+
+		Controller Update Acknowledge Enable
+		PSU_DDR_PHY_DSGCR_CUAEN                                                         0x1
+
+		Reserved. Return zeroes on reads
+		PSU_DDR_PHY_DSGCR_RESERVED_4_3                                                  0x0
+
+		Controller Impedance Update Enable
+		PSU_DDR_PHY_DSGCR_CTLZUEN                                                       0x0
+
+		Reserved. Return zeroes on reads
+		PSU_DDR_PHY_DSGCR_RESERVED_1                                                    0x0
+
+		PHY Update Request Enable
+		PSU_DDR_PHY_DSGCR_PUREN                                                         0x1
+
+		DDR System General Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD080090, 0xFFFFFFFFU ,0x02A04121U)  
+		RegMask = (DDR_PHY_DSGCR_RESERVED_31_28_MASK | DDR_PHY_DSGCR_RDBICLSEL_MASK | DDR_PHY_DSGCR_RDBICL_MASK | DDR_PHY_DSGCR_PHYZUEN_MASK | DDR_PHY_DSGCR_RESERVED_22_MASK | DDR_PHY_DSGCR_RSTOE_MASK | DDR_PHY_DSGCR_SDRMODE_MASK | DDR_PHY_DSGCR_RESERVED_18_MASK | DDR_PHY_DSGCR_ATOAE_MASK | DDR_PHY_DSGCR_DTOOE_MASK | DDR_PHY_DSGCR_DTOIOM_MASK | DDR_PHY_DSGCR_DTOPDR_MASK | DDR_PHY_DSGCR_RESERVED_13_MASK | DDR_PHY_DSGCR_DTOODT_MASK | DDR_PHY_DSGCR_PUAD_MASK | DDR_PHY_DSGCR_CUAEN_MASK | DDR_PHY_DSGCR_RESERVED_4_3_MASK | DDR_PHY_DSGCR_CTLZUEN_MASK | DDR_PHY_DSGCR_RESERVED_1_MASK | DDR_PHY_DSGCR_PUREN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DSGCR_RESERVED_31_28_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RDBICLSEL_SHIFT
+			| 0x00000002U << DDR_PHY_DSGCR_RDBICL_SHIFT
+			| 0x00000001U << DDR_PHY_DSGCR_PHYZUEN_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RESERVED_22_SHIFT
+			| 0x00000001U << DDR_PHY_DSGCR_RSTOE_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_SDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RESERVED_18_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_ATOAE_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_DTOOE_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_DTOIOM_SHIFT
+			| 0x00000001U << DDR_PHY_DSGCR_DTOPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RESERVED_13_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_DTOODT_SHIFT
+			| 0x00000004U << DDR_PHY_DSGCR_PUAD_SHIFT
+			| 0x00000001U << DDR_PHY_DSGCR_CUAEN_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RESERVED_4_3_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_CTLZUEN_SHIFT
+			| 0x00000000U << DDR_PHY_DSGCR_RESERVED_1_SHIFT
+			| 0x00000001U << DDR_PHY_DSGCR_PUREN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DSGCR_OFFSET ,0xFFFFFFFFU ,0x02A04121U);
+	/*############################################################################################################################ */
+
+		/*Register : DCR @ 0XFD080100

+
+		DDR4 Gear Down Timing.
+		PSU_DDR_PHY_DCR_GEARDN                                                          0x0
+
+		Un-used Bank Group
+		PSU_DDR_PHY_DCR_UBG                                                             0x0
+
+		Un-buffered DIMM Address Mirroring
+		PSU_DDR_PHY_DCR_UDIMM                                                           0x0
+
+		DDR 2T Timing
+		PSU_DDR_PHY_DCR_DDR2T                                                           0x0
+
+		No Simultaneous Rank Access
+		PSU_DDR_PHY_DCR_NOSRA                                                           0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DCR_RESERVED_26_18                                                  0x0
+
+		Byte Mask
+		PSU_DDR_PHY_DCR_BYTEMASK                                                        0x1
+
+		DDR Type
+		PSU_DDR_PHY_DCR_DDRTYPE                                                         0x0
+
+		Multi-Purpose Register (MPR) DQ (DDR3 Only)
+		PSU_DDR_PHY_DCR_MPRDQ                                                           0x0
+
+		Primary DQ (DDR3 Only)
+		PSU_DDR_PHY_DCR_PDQ                                                             0x0
+
+		DDR 8-Bank
+		PSU_DDR_PHY_DCR_DDR8BNK                                                         0x1
+
+		DDR Mode
+		PSU_DDR_PHY_DCR_DDRMD                                                           0x4
+
+		DRAM Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD080100, 0xFFFFFFFFU ,0x0800040CU)  
+		RegMask = (DDR_PHY_DCR_GEARDN_MASK | DDR_PHY_DCR_UBG_MASK | DDR_PHY_DCR_UDIMM_MASK | DDR_PHY_DCR_DDR2T_MASK | DDR_PHY_DCR_NOSRA_MASK | DDR_PHY_DCR_RESERVED_26_18_MASK | DDR_PHY_DCR_BYTEMASK_MASK | DDR_PHY_DCR_DDRTYPE_MASK | DDR_PHY_DCR_MPRDQ_MASK | DDR_PHY_DCR_PDQ_MASK | DDR_PHY_DCR_DDR8BNK_MASK | DDR_PHY_DCR_DDRMD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DCR_GEARDN_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_UBG_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_UDIMM_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_DDR2T_SHIFT
+			| 0x00000001U << DDR_PHY_DCR_NOSRA_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_RESERVED_26_18_SHIFT
+			| 0x00000001U << DDR_PHY_DCR_BYTEMASK_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_DDRTYPE_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_MPRDQ_SHIFT
+			| 0x00000000U << DDR_PHY_DCR_PDQ_SHIFT
+			| 0x00000001U << DDR_PHY_DCR_DDR8BNK_SHIFT
+			| 0x00000004U << DDR_PHY_DCR_DDRMD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DCR_OFFSET ,0xFFFFFFFFU ,0x0800040CU);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR0 @ 0XFD080110

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR0_RESERVED_31_29                                                0x0
+
+		Activate to activate command delay (different banks)
+		PSU_DDR_PHY_DTPR0_TRRD                                                          0x6
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR0_RESERVED_23                                                   0x0
+
+		Activate to precharge command delay
+		PSU_DDR_PHY_DTPR0_TRAS                                                          0x24
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR0_RESERVED_15                                                   0x0
+
+		Precharge command period
+		PSU_DDR_PHY_DTPR0_TRP                                                           0x12
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR0_RESERVED_7_5                                                  0x0
+
+		Internal read to precharge command delay
+		PSU_DDR_PHY_DTPR0_TRTP                                                          0x8
+
+		DRAM Timing Parameters Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080110, 0xFFFFFFFFU ,0x06241208U)  
+		RegMask = (DDR_PHY_DTPR0_RESERVED_31_29_MASK | DDR_PHY_DTPR0_TRRD_MASK | DDR_PHY_DTPR0_RESERVED_23_MASK | DDR_PHY_DTPR0_TRAS_MASK | DDR_PHY_DTPR0_RESERVED_15_MASK | DDR_PHY_DTPR0_TRP_MASK | DDR_PHY_DTPR0_RESERVED_7_5_MASK | DDR_PHY_DTPR0_TRTP_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR0_RESERVED_31_29_SHIFT
+			| 0x00000006U << DDR_PHY_DTPR0_TRRD_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR0_RESERVED_23_SHIFT
+			| 0x00000024U << DDR_PHY_DTPR0_TRAS_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR0_RESERVED_15_SHIFT
+			| 0x00000012U << DDR_PHY_DTPR0_TRP_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR0_RESERVED_7_5_SHIFT
+			| 0x00000008U << DDR_PHY_DTPR0_TRTP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR0_OFFSET ,0xFFFFFFFFU ,0x06241208U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR1 @ 0XFD080114

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR1_RESERVED_31                                                   0x0
+
+		Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.
+		PSU_DDR_PHY_DTPR1_TWLMRD                                                        0x28
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR1_RESERVED_23                                                   0x0
+
+		4-bank activate period
+		PSU_DDR_PHY_DTPR1_TFAW                                                          0x18
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR1_RESERVED_15_11                                                0x0
+
+		Load mode update delay (DDR4 and DDR3 only)
+		PSU_DDR_PHY_DTPR1_TMOD                                                          0x7
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR1_RESERVED_7_5                                                  0x0
+
+		Load mode cycle time
+		PSU_DDR_PHY_DTPR1_TMRD                                                          0x8
+
+		DRAM Timing Parameters Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080114, 0xFFFFFFFFU ,0x28180708U)  
+		RegMask = (DDR_PHY_DTPR1_RESERVED_31_MASK | DDR_PHY_DTPR1_TWLMRD_MASK | DDR_PHY_DTPR1_RESERVED_23_MASK | DDR_PHY_DTPR1_TFAW_MASK | DDR_PHY_DTPR1_RESERVED_15_11_MASK | DDR_PHY_DTPR1_TMOD_MASK | DDR_PHY_DTPR1_RESERVED_7_5_MASK | DDR_PHY_DTPR1_TMRD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR1_RESERVED_31_SHIFT
+			| 0x00000028U << DDR_PHY_DTPR1_TWLMRD_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR1_RESERVED_23_SHIFT
+			| 0x00000018U << DDR_PHY_DTPR1_TFAW_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR1_RESERVED_15_11_SHIFT
+			| 0x00000007U << DDR_PHY_DTPR1_TMOD_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR1_RESERVED_7_5_SHIFT
+			| 0x00000008U << DDR_PHY_DTPR1_TMRD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR1_OFFSET ,0xFFFFFFFFU ,0x28180708U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR2 @ 0XFD080118

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR2_RESERVED_31_29                                                0x0
+
+		Read to Write command delay. Valid values are
+		PSU_DDR_PHY_DTPR2_TRTW                                                          0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR2_RESERVED_27_25                                                0x0
+
+		Read to ODT delay (DDR3 only)
+		PSU_DDR_PHY_DTPR2_TRTODT                                                        0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR2_RESERVED_23_20                                                0x0
+
+		CKE minimum pulse width
+		PSU_DDR_PHY_DTPR2_TCKE                                                          0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR2_RESERVED_15_10                                                0x0
+
+		Self refresh exit delay
+		PSU_DDR_PHY_DTPR2_TXS                                                           0x200
+
+		DRAM Timing Parameters Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080118, 0xFFFFFFFFU ,0x00080200U)  
+		RegMask = (DDR_PHY_DTPR2_RESERVED_31_29_MASK | DDR_PHY_DTPR2_TRTW_MASK | DDR_PHY_DTPR2_RESERVED_27_25_MASK | DDR_PHY_DTPR2_TRTODT_MASK | DDR_PHY_DTPR2_RESERVED_23_20_MASK | DDR_PHY_DTPR2_TCKE_MASK | DDR_PHY_DTPR2_RESERVED_15_10_MASK | DDR_PHY_DTPR2_TXS_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR2_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR2_TRTW_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR2_RESERVED_27_25_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR2_TRTODT_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR2_RESERVED_23_20_SHIFT
+			| 0x00000008U << DDR_PHY_DTPR2_TCKE_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR2_RESERVED_15_10_SHIFT
+			| 0x00000200U << DDR_PHY_DTPR2_TXS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR2_OFFSET ,0xFFFFFFFFU ,0x00080200U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR3 @ 0XFD08011C

+
+		ODT turn-off delay extension
+		PSU_DDR_PHY_DTPR3_TOFDX                                                         0x4
+
+		Read to read and write to write command delay
+		PSU_DDR_PHY_DTPR3_TCCD                                                          0x0
+
+		DLL locking time
+		PSU_DDR_PHY_DTPR3_TDLLK                                                         0x300
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR3_RESERVED_15_12                                                0x0
+
+		Maximum DQS output access time from CK/CK# (LPDDR2/3 only)
+		PSU_DDR_PHY_DTPR3_TDQSCKMAX                                                     0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR3_RESERVED_7_3                                                  0x0
+
+		DQS output access time from CK/CK# (LPDDR2/3 only)
+		PSU_DDR_PHY_DTPR3_TDQSCK                                                        0x4
+
+		DRAM Timing Parameters Register 3
+		(OFFSET, MASK, VALUE)      (0XFD08011C, 0xFFFFFFFFU ,0x83000804U)  
+		RegMask = (DDR_PHY_DTPR3_TOFDX_MASK | DDR_PHY_DTPR3_TCCD_MASK | DDR_PHY_DTPR3_TDLLK_MASK | DDR_PHY_DTPR3_RESERVED_15_12_MASK | DDR_PHY_DTPR3_TDQSCKMAX_MASK | DDR_PHY_DTPR3_RESERVED_7_3_MASK | DDR_PHY_DTPR3_TDQSCK_MASK |  0 );
+
+		RegVal = ((0x00000004U << DDR_PHY_DTPR3_TOFDX_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR3_TCCD_SHIFT
+			| 0x00000300U << DDR_PHY_DTPR3_TDLLK_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR3_RESERVED_15_12_SHIFT
+			| 0x00000008U << DDR_PHY_DTPR3_TDQSCKMAX_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR3_RESERVED_7_3_SHIFT
+			| 0x00000004U << DDR_PHY_DTPR3_TDQSCK_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR3_OFFSET ,0xFFFFFFFFU ,0x83000804U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR4 @ 0XFD080120

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR4_RESERVED_31_30                                                0x0
+
+		ODT turn-on/turn-off delays (DDR2 only)
+		PSU_DDR_PHY_DTPR4_TAOND_TAOFD                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR4_RESERVED_27_26                                                0x0
+
+		Refresh-to-Refresh
+		PSU_DDR_PHY_DTPR4_TRFC                                                          0x116
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR4_RESERVED_15_14                                                0x0
+
+		Write leveling output delay
+		PSU_DDR_PHY_DTPR4_TWLO                                                          0x2b
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR4_RESERVED_7_5                                                  0x0
+
+		Power down exit delay
+		PSU_DDR_PHY_DTPR4_TXP                                                           0x8
+
+		DRAM Timing Parameters Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080120, 0xFFFFFFFFU ,0x01162B08U)  
+		RegMask = (DDR_PHY_DTPR4_RESERVED_31_30_MASK | DDR_PHY_DTPR4_TAOND_TAOFD_MASK | DDR_PHY_DTPR4_RESERVED_27_26_MASK | DDR_PHY_DTPR4_TRFC_MASK | DDR_PHY_DTPR4_RESERVED_15_14_MASK | DDR_PHY_DTPR4_TWLO_MASK | DDR_PHY_DTPR4_RESERVED_7_5_MASK | DDR_PHY_DTPR4_TXP_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR4_RESERVED_31_30_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR4_RESERVED_27_26_SHIFT
+			| 0x00000116U << DDR_PHY_DTPR4_TRFC_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR4_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DTPR4_TWLO_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR4_RESERVED_7_5_SHIFT
+			| 0x00000008U << DDR_PHY_DTPR4_TXP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR4_OFFSET ,0xFFFFFFFFU ,0x01162B08U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR5 @ 0XFD080124

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR5_RESERVED_31_24                                                0x0
+
+		Activate to activate command delay (same bank)
+		PSU_DDR_PHY_DTPR5_TRC                                                           0x32
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR5_RESERVED_15                                                   0x0
+
+		Activate to read or write delay
+		PSU_DDR_PHY_DTPR5_TRCD                                                          0xf
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR5_RESERVED_7_5                                                  0x0
+
+		Internal write to read command delay
+		PSU_DDR_PHY_DTPR5_TWTR                                                          0x9
+
+		DRAM Timing Parameters Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080124, 0xFFFFFFFFU ,0x00320F09U)  
+		RegMask = (DDR_PHY_DTPR5_RESERVED_31_24_MASK | DDR_PHY_DTPR5_TRC_MASK | DDR_PHY_DTPR5_RESERVED_15_MASK | DDR_PHY_DTPR5_TRCD_MASK | DDR_PHY_DTPR5_RESERVED_7_5_MASK | DDR_PHY_DTPR5_TWTR_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR5_RESERVED_31_24_SHIFT
+			| 0x00000032U << DDR_PHY_DTPR5_TRC_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR5_RESERVED_15_SHIFT
+			| 0x0000000FU << DDR_PHY_DTPR5_TRCD_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR5_RESERVED_7_5_SHIFT
+			| 0x00000009U << DDR_PHY_DTPR5_TWTR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR5_OFFSET ,0xFFFFFFFFU ,0x00320F09U);
+	/*############################################################################################################################ */
+
+		/*Register : DTPR6 @ 0XFD080128

+
+		PUB Write Latency Enable
+		PSU_DDR_PHY_DTPR6_PUBWLEN                                                       0x0
+
+		PUB Read Latency Enable
+		PSU_DDR_PHY_DTPR6_PUBRLEN                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR6_RESERVED_29_14                                                0x0
+
+		Write Latency
+		PSU_DDR_PHY_DTPR6_PUBWL                                                         0xe
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTPR6_RESERVED_7_6                                                  0x0
+
+		Read Latency
+		PSU_DDR_PHY_DTPR6_PUBRL                                                         0xf
+
+		DRAM Timing Parameters Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080128, 0xFFFFFFFFU ,0x00000E0FU)  
+		RegMask = (DDR_PHY_DTPR6_PUBWLEN_MASK | DDR_PHY_DTPR6_PUBRLEN_MASK | DDR_PHY_DTPR6_RESERVED_29_14_MASK | DDR_PHY_DTPR6_PUBWL_MASK | DDR_PHY_DTPR6_RESERVED_7_6_MASK | DDR_PHY_DTPR6_PUBRL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTPR6_PUBWLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR6_PUBRLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR6_RESERVED_29_14_SHIFT
+			| 0x0000000EU << DDR_PHY_DTPR6_PUBWL_SHIFT
+			| 0x00000000U << DDR_PHY_DTPR6_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DTPR6_PUBRL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTPR6_OFFSET ,0xFFFFFFFFU ,0x00000E0FU);
+	/*############################################################################################################################ */
+
+		/*Register : RDIMMGCR0 @ 0XFD080140

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_31                                               0x0
+
+		RDMIMM Quad CS Enable
+		PSU_DDR_PHY_RDIMMGCR0_QCSEN                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_29_28                                            0x0
+
+		RDIMM Outputs I/O Mode
+		PSU_DDR_PHY_RDIMMGCR0_RDIMMIOM                                                  0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_26_24                                            0x0
+
+		ERROUT# Output Enable
+		PSU_DDR_PHY_RDIMMGCR0_ERROUTOE                                                  0x0
+
+		ERROUT# I/O Mode
+		PSU_DDR_PHY_RDIMMGCR0_ERROUTIOM                                                 0x1
+
+		ERROUT# Power Down Receiver
+		PSU_DDR_PHY_RDIMMGCR0_ERROUTPDR                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_20                                               0x0
+
+		ERROUT# On-Die Termination
+		PSU_DDR_PHY_RDIMMGCR0_ERROUTODT                                                 0x0
+
+		Load Reduced DIMM
+		PSU_DDR_PHY_RDIMMGCR0_LRDIMM                                                    0x0
+
+		PAR_IN I/O Mode
+		PSU_DDR_PHY_RDIMMGCR0_PARINIOM                                                  0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_16_8                                             0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD                                             0x0
+
+		Rank Mirror Enable.
+		PSU_DDR_PHY_RDIMMGCR0_RNKMRREN                                                  0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR0_RESERVED_3                                                0x0
+
+		Stop on Parity Error
+		PSU_DDR_PHY_RDIMMGCR0_SOPERR                                                    0x0
+
+		Parity Error No Registering
+		PSU_DDR_PHY_RDIMMGCR0_ERRNOREG                                                  0x0
+
+		Registered DIMM
+		PSU_DDR_PHY_RDIMMGCR0_RDIMM                                                     0x0
+
+		RDIMM General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080140, 0xFFFFFFFFU ,0x08400020U)  
+		RegMask = (DDR_PHY_RDIMMGCR0_RESERVED_31_MASK | DDR_PHY_RDIMMGCR0_QCSEN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK | DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK | DDR_PHY_RDIMMGCR0_ERROUTOE_MASK | DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK | DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK | DDR_PHY_RDIMMGCR0_RESERVED_20_MASK | DDR_PHY_RDIMMGCR0_ERROUTODT_MASK | DDR_PHY_RDIMMGCR0_LRDIMM_MASK | DDR_PHY_RDIMMGCR0_PARINIOM_MASK | DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK | DDR_PHY_RDIMMGCR0_RNKMRREN_MASK | DDR_PHY_RDIMMGCR0_RESERVED_3_MASK | DDR_PHY_RDIMMGCR0_SOPERR_MASK | DDR_PHY_RDIMMGCR0_ERRNOREG_MASK | DDR_PHY_RDIMMGCR0_RDIMM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_QCSEN_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT
+			| 0x00000001U << DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT
+			| 0x00000001U << DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT
+			| 0x00000002U << DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_SOPERR_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR0_RDIMM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_RDIMMGCR0_OFFSET ,0xFFFFFFFFU ,0x08400020U);
+	/*############################################################################################################################ */
+
+		/*Register : RDIMMGCR1 @ 0XFD080144

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR1_RESERVED_31_29                                            0x0
+
+		Address [17] B-side Inversion Disable
+		PSU_DDR_PHY_RDIMMGCR1_A17BID                                                    0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR1_RESERVED_27                                               0x0
+
+		Command word to command word programming delay
+		PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L2                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR1_RESERVED_23                                               0x0
+
+		Command word to command word programming delay
+		PSU_DDR_PHY_RDIMMGCR1_TBCMRD_L                                                  0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR1_RESERVED_19                                               0x0
+
+		Command word to command word programming delay
+		PSU_DDR_PHY_RDIMMGCR1_TBCMRD                                                    0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RDIMMGCR1_RESERVED_15_14                                            0x0
+
+		Stabilization time
+		PSU_DDR_PHY_RDIMMGCR1_TBCSTAB                                                   0xc80
+
+		RDIMM General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080144, 0xFFFFFFFFU ,0x00000C80U)  
+		RegMask = (DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK | DDR_PHY_RDIMMGCR1_A17BID_MASK | DDR_PHY_RDIMMGCR1_RESERVED_27_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK | DDR_PHY_RDIMMGCR1_RESERVED_23_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK | DDR_PHY_RDIMMGCR1_RESERVED_19_MASK | DDR_PHY_RDIMMGCR1_TBCMRD_MASK | DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK | DDR_PHY_RDIMMGCR1_TBCSTAB_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_A17BID_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT
+			| 0x00000C80U << DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_RDIMMGCR1_OFFSET ,0xFFFFFFFFU ,0x00000C80U);
+	/*############################################################################################################################ */
+
+		/*Register : RDIMMCR1 @ 0XFD080154

+
+		Control Word 15
+		PSU_DDR_PHY_RDIMMCR1_RC15                                                       0x0
+
+		DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved
+		PSU_DDR_PHY_RDIMMCR1_RC14                                                       0x0
+
+		DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved
+		PSU_DDR_PHY_RDIMMCR1_RC13                                                       0x0
+
+		DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved
+		PSU_DDR_PHY_RDIMMCR1_RC12                                                       0x0
+
+		DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
+		rol Word)
+		PSU_DDR_PHY_RDIMMCR1_RC11                                                       0x0
+
+		DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)
+		PSU_DDR_PHY_RDIMMCR1_RC10                                                       0x2
+
+		DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)
+		PSU_DDR_PHY_RDIMMCR1_RC9                                                        0x0
+
+		DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
+		Control Word)
+		PSU_DDR_PHY_RDIMMCR1_RC8                                                        0x0
+
+		RDIMM Control Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080154, 0xFFFFFFFFU ,0x00000200U)  
+		RegMask = (DDR_PHY_RDIMMCR1_RC15_MASK | DDR_PHY_RDIMMCR1_RC14_MASK | DDR_PHY_RDIMMCR1_RC13_MASK | DDR_PHY_RDIMMCR1_RC12_MASK | DDR_PHY_RDIMMCR1_RC11_MASK | DDR_PHY_RDIMMCR1_RC10_MASK | DDR_PHY_RDIMMCR1_RC9_MASK | DDR_PHY_RDIMMCR1_RC8_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_RDIMMCR1_RC15_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC14_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC13_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC12_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC11_SHIFT
+			| 0x00000002U << DDR_PHY_RDIMMCR1_RC10_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC9_SHIFT
+			| 0x00000000U << DDR_PHY_RDIMMCR1_RC8_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_RDIMMCR1_OFFSET ,0xFFFFFFFFU ,0x00000200U);
+	/*############################################################################################################################ */
+
+		/*Register : MR0 @ 0XFD080180

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR0_RESERVED_31_8                                                   0x8
+
+		CA Terminating Rank
+		PSU_DDR_PHY_MR0_CATR                                                            0x0
+
+		Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR0_RSVD_6_5                                                        0x1
+
+		Built-in Self-Test for RZQ
+		PSU_DDR_PHY_MR0_RZQI                                                            0x2
+
+		Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR0_RSVD_2_0                                                        0x0
+
+		LPDDR4 Mode Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080180, 0xFFFFFFFFU ,0x00000830U)  
+		RegMask = (DDR_PHY_MR0_RESERVED_31_8_MASK | DDR_PHY_MR0_CATR_MASK | DDR_PHY_MR0_RSVD_6_5_MASK | DDR_PHY_MR0_RZQI_MASK | DDR_PHY_MR0_RSVD_2_0_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDR_PHY_MR0_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR0_CATR_SHIFT
+			| 0x00000001U << DDR_PHY_MR0_RSVD_6_5_SHIFT
+			| 0x00000002U << DDR_PHY_MR0_RZQI_SHIFT
+			| 0x00000000U << DDR_PHY_MR0_RSVD_2_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR0_OFFSET ,0xFFFFFFFFU ,0x00000830U);
+	/*############################################################################################################################ */
+
+		/*Register : MR1 @ 0XFD080184

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR1_RESERVED_31_8                                                   0x3
+
+		Read Postamble Length
+		PSU_DDR_PHY_MR1_RDPST                                                           0x0
+
+		Write-recovery for auto-precharge command
+		PSU_DDR_PHY_MR1_NWR                                                             0x0
+
+		Read Preamble Length
+		PSU_DDR_PHY_MR1_RDPRE                                                           0x0
+
+		Write Preamble Length
+		PSU_DDR_PHY_MR1_WRPRE                                                           0x0
+
+		Burst Length
+		PSU_DDR_PHY_MR1_BL                                                              0x1
+
+		LPDDR4 Mode Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080184, 0xFFFFFFFFU ,0x00000301U)  
+		RegMask = (DDR_PHY_MR1_RESERVED_31_8_MASK | DDR_PHY_MR1_RDPST_MASK | DDR_PHY_MR1_NWR_MASK | DDR_PHY_MR1_RDPRE_MASK | DDR_PHY_MR1_WRPRE_MASK | DDR_PHY_MR1_BL_MASK |  0 );
+
+		RegVal = ((0x00000003U << DDR_PHY_MR1_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR1_RDPST_SHIFT
+			| 0x00000000U << DDR_PHY_MR1_NWR_SHIFT
+			| 0x00000000U << DDR_PHY_MR1_RDPRE_SHIFT
+			| 0x00000000U << DDR_PHY_MR1_WRPRE_SHIFT
+			| 0x00000001U << DDR_PHY_MR1_BL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR1_OFFSET ,0xFFFFFFFFU ,0x00000301U);
+	/*############################################################################################################################ */
+
+		/*Register : MR2 @ 0XFD080188

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR2_RESERVED_31_8                                                   0x0
+
+		Write Leveling
+		PSU_DDR_PHY_MR2_WRL                                                             0x0
+
+		Write Latency Set
+		PSU_DDR_PHY_MR2_WLS                                                             0x0
+
+		Write Latency
+		PSU_DDR_PHY_MR2_WL                                                              0x4
+
+		Read Latency
+		PSU_DDR_PHY_MR2_RL                                                              0x0
+
+		LPDDR4 Mode Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080188, 0xFFFFFFFFU ,0x00000020U)  
+		RegMask = (DDR_PHY_MR2_RESERVED_31_8_MASK | DDR_PHY_MR2_WRL_MASK | DDR_PHY_MR2_WLS_MASK | DDR_PHY_MR2_WL_MASK | DDR_PHY_MR2_RL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR2_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR2_WRL_SHIFT
+			| 0x00000000U << DDR_PHY_MR2_WLS_SHIFT
+			| 0x00000004U << DDR_PHY_MR2_WL_SHIFT
+			| 0x00000000U << DDR_PHY_MR2_RL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR2_OFFSET ,0xFFFFFFFFU ,0x00000020U);
+	/*############################################################################################################################ */
+
+		/*Register : MR3 @ 0XFD08018C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR3_RESERVED_31_8                                                   0x2
+
+		DBI-Write Enable
+		PSU_DDR_PHY_MR3_DBIWR                                                           0x0
+
+		DBI-Read Enable
+		PSU_DDR_PHY_MR3_DBIRD                                                           0x0
+
+		Pull-down Drive Strength
+		PSU_DDR_PHY_MR3_PDDS                                                            0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR3_RSVD                                                            0x0
+
+		Write Postamble Length
+		PSU_DDR_PHY_MR3_WRPST                                                           0x0
+
+		Pull-up Calibration Point
+		PSU_DDR_PHY_MR3_PUCAL                                                           0x0
+
+		LPDDR4 Mode Register 3
+		(OFFSET, MASK, VALUE)      (0XFD08018C, 0xFFFFFFFFU ,0x00000200U)  
+		RegMask = (DDR_PHY_MR3_RESERVED_31_8_MASK | DDR_PHY_MR3_DBIWR_MASK | DDR_PHY_MR3_DBIRD_MASK | DDR_PHY_MR3_PDDS_MASK | DDR_PHY_MR3_RSVD_MASK | DDR_PHY_MR3_WRPST_MASK | DDR_PHY_MR3_PUCAL_MASK |  0 );
+
+		RegVal = ((0x00000002U << DDR_PHY_MR3_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_DBIWR_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_DBIRD_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_PDDS_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_RSVD_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_WRPST_SHIFT
+			| 0x00000000U << DDR_PHY_MR3_PUCAL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR3_OFFSET ,0xFFFFFFFFU ,0x00000200U);
+	/*############################################################################################################################ */
+
+		/*Register : MR4 @ 0XFD080190

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR4_RESERVED_31_16                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR4_RSVD_15_13                                                      0x0
+
+		Write Preamble
+		PSU_DDR_PHY_MR4_WRP                                                             0x0
+
+		Read Preamble
+		PSU_DDR_PHY_MR4_RDP                                                             0x0
+
+		Read Preamble Training Mode
+		PSU_DDR_PHY_MR4_RPTM                                                            0x0
+
+		Self Refresh Abort
+		PSU_DDR_PHY_MR4_SRA                                                             0x0
+
+		CS to Command Latency Mode
+		PSU_DDR_PHY_MR4_CS2CMDL                                                         0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR4_RSVD1                                                           0x0
+
+		Internal VREF Monitor
+		PSU_DDR_PHY_MR4_IVM                                                             0x0
+
+		Temperature Controlled Refresh Mode
+		PSU_DDR_PHY_MR4_TCRM                                                            0x0
+
+		Temperature Controlled Refresh Range
+		PSU_DDR_PHY_MR4_TCRR                                                            0x0
+
+		Maximum Power Down Mode
+		PSU_DDR_PHY_MR4_MPDM                                                            0x0
+
+		This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR4_RSVD_0                                                          0x0
+
+		DDR4 Mode Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080190, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_MR4_RESERVED_31_16_MASK | DDR_PHY_MR4_RSVD_15_13_MASK | DDR_PHY_MR4_WRP_MASK | DDR_PHY_MR4_RDP_MASK | DDR_PHY_MR4_RPTM_MASK | DDR_PHY_MR4_SRA_MASK | DDR_PHY_MR4_CS2CMDL_MASK | DDR_PHY_MR4_RSVD1_MASK | DDR_PHY_MR4_IVM_MASK | DDR_PHY_MR4_TCRM_MASK | DDR_PHY_MR4_TCRR_MASK | DDR_PHY_MR4_MPDM_MASK | DDR_PHY_MR4_RSVD_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR4_RESERVED_31_16_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_RSVD_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_WRP_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_RDP_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_RPTM_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_SRA_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_CS2CMDL_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_RSVD1_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_IVM_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_TCRM_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_TCRR_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_MPDM_SHIFT
+			| 0x00000000U << DDR_PHY_MR4_RSVD_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR4_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MR5 @ 0XFD080194

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR5_RESERVED_31_16                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR5_RSVD                                                            0x0
+
+		Read DBI
+		PSU_DDR_PHY_MR5_RDBI                                                            0x0
+
+		Write DBI
+		PSU_DDR_PHY_MR5_WDBI                                                            0x0
+
+		Data Mask
+		PSU_DDR_PHY_MR5_DM                                                              0x1
+
+		CA Parity Persistent Error
+		PSU_DDR_PHY_MR5_CAPPE                                                           0x1
+
+		RTT_PARK
+		PSU_DDR_PHY_MR5_RTTPARK                                                         0x3
+
+		ODT Input Buffer during Power Down mode
+		PSU_DDR_PHY_MR5_ODTIBPD                                                         0x0
+
+		C/A Parity Error Status
+		PSU_DDR_PHY_MR5_CAPES                                                           0x0
+
+		CRC Error Clear
+		PSU_DDR_PHY_MR5_CRCEC                                                           0x0
+
+		C/A Parity Latency Mode
+		PSU_DDR_PHY_MR5_CAPM                                                            0x0
+
+		DDR4 Mode Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080194, 0xFFFFFFFFU ,0x000006C0U)  
+		RegMask = (DDR_PHY_MR5_RESERVED_31_16_MASK | DDR_PHY_MR5_RSVD_MASK | DDR_PHY_MR5_RDBI_MASK | DDR_PHY_MR5_WDBI_MASK | DDR_PHY_MR5_DM_MASK | DDR_PHY_MR5_CAPPE_MASK | DDR_PHY_MR5_RTTPARK_MASK | DDR_PHY_MR5_ODTIBPD_MASK | DDR_PHY_MR5_CAPES_MASK | DDR_PHY_MR5_CRCEC_MASK | DDR_PHY_MR5_CAPM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR5_RESERVED_31_16_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_RSVD_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_WDBI_SHIFT
+			| 0x00000001U << DDR_PHY_MR5_DM_SHIFT
+			| 0x00000001U << DDR_PHY_MR5_CAPPE_SHIFT
+			| 0x00000003U << DDR_PHY_MR5_RTTPARK_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_ODTIBPD_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_CAPES_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_CRCEC_SHIFT
+			| 0x00000000U << DDR_PHY_MR5_CAPM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR5_OFFSET ,0xFFFFFFFFU ,0x000006C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MR6 @ 0XFD080198

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR6_RESERVED_31_16                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR6_RSVD_15_13                                                      0x0
+
+		CAS_n to CAS_n command delay for same bank group (tCCD_L)
+		PSU_DDR_PHY_MR6_TCCDL                                                           0x2
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR6_RSVD_9_8                                                        0x0
+
+		VrefDQ Training Enable
+		PSU_DDR_PHY_MR6_VDDQTEN                                                         0x0
+
+		VrefDQ Training Range
+		PSU_DDR_PHY_MR6_VDQTRG                                                          0x0
+
+		VrefDQ Training Values
+		PSU_DDR_PHY_MR6_VDQTVAL                                                         0x19
+
+		DDR4 Mode Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080198, 0xFFFFFFFFU ,0x00000819U)  
+		RegMask = (DDR_PHY_MR6_RESERVED_31_16_MASK | DDR_PHY_MR6_RSVD_15_13_MASK | DDR_PHY_MR6_TCCDL_MASK | DDR_PHY_MR6_RSVD_9_8_MASK | DDR_PHY_MR6_VDDQTEN_MASK | DDR_PHY_MR6_VDQTRG_MASK | DDR_PHY_MR6_VDQTVAL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR6_RESERVED_31_16_SHIFT
+			| 0x00000000U << DDR_PHY_MR6_RSVD_15_13_SHIFT
+			| 0x00000002U << DDR_PHY_MR6_TCCDL_SHIFT
+			| 0x00000000U << DDR_PHY_MR6_RSVD_9_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR6_VDDQTEN_SHIFT
+			| 0x00000000U << DDR_PHY_MR6_VDQTRG_SHIFT
+			| 0x00000019U << DDR_PHY_MR6_VDQTVAL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR6_OFFSET ,0xFFFFFFFFU ,0x00000819U);
+	/*############################################################################################################################ */
+
+		/*Register : MR11 @ 0XFD0801AC

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR11_RESERVED_31_8                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR11_RSVD                                                           0x0
+
+		Power Down Control
+		PSU_DDR_PHY_MR11_PDCTL                                                          0x0
+
+		DQ Bus Receiver On-Die-Termination
+		PSU_DDR_PHY_MR11_DQODT                                                          0x0
+
+		LPDDR4 Mode Register 11
+		(OFFSET, MASK, VALUE)      (0XFD0801AC, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_MR11_RESERVED_31_8_MASK | DDR_PHY_MR11_RSVD_MASK | DDR_PHY_MR11_PDCTL_MASK | DDR_PHY_MR11_DQODT_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR11_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR11_RSVD_SHIFT
+			| 0x00000000U << DDR_PHY_MR11_PDCTL_SHIFT
+			| 0x00000000U << DDR_PHY_MR11_DQODT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR11_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MR12 @ 0XFD0801B0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR12_RESERVED_31_8                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR12_RSVD                                                           0x0
+
+		VREF_CA Range Select.
+		PSU_DDR_PHY_MR12_VR_CA                                                          0x1
+
+		Controls the VREF(ca) levels for Frequency-Set-Point[1:0].
+		PSU_DDR_PHY_MR12_VREF_CA                                                        0xd
+
+		LPDDR4 Mode Register 12
+		(OFFSET, MASK, VALUE)      (0XFD0801B0, 0xFFFFFFFFU ,0x0000004DU)  
+		RegMask = (DDR_PHY_MR12_RESERVED_31_8_MASK | DDR_PHY_MR12_RSVD_MASK | DDR_PHY_MR12_VR_CA_MASK | DDR_PHY_MR12_VREF_CA_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR12_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR12_RSVD_SHIFT
+			| 0x00000001U << DDR_PHY_MR12_VR_CA_SHIFT
+			| 0x0000000DU << DDR_PHY_MR12_VREF_CA_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR12_OFFSET ,0xFFFFFFFFU ,0x0000004DU);
+	/*############################################################################################################################ */
+
+		/*Register : MR13 @ 0XFD0801B4

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR13_RESERVED_31_8                                                  0x0
+
+		Frequency Set Point Operation Mode
+		PSU_DDR_PHY_MR13_FSPOP                                                          0x0
+
+		Frequency Set Point Write Enable
+		PSU_DDR_PHY_MR13_FSPWR                                                          0x0
+
+		Data Mask Enable
+		PSU_DDR_PHY_MR13_DMD                                                            0x0
+
+		Refresh Rate Option
+		PSU_DDR_PHY_MR13_RRO                                                            0x0
+
+		VREF Current Generator
+		PSU_DDR_PHY_MR13_VRCG                                                           0x1
+
+		VREF Output
+		PSU_DDR_PHY_MR13_VRO                                                            0x0
+
+		Read Preamble Training Mode
+		PSU_DDR_PHY_MR13_RPT                                                            0x0
+
+		Command Bus Training
+		PSU_DDR_PHY_MR13_CBT                                                            0x0
+
+		LPDDR4 Mode Register 13
+		(OFFSET, MASK, VALUE)      (0XFD0801B4, 0xFFFFFFFFU ,0x00000008U)  
+		RegMask = (DDR_PHY_MR13_RESERVED_31_8_MASK | DDR_PHY_MR13_FSPOP_MASK | DDR_PHY_MR13_FSPWR_MASK | DDR_PHY_MR13_DMD_MASK | DDR_PHY_MR13_RRO_MASK | DDR_PHY_MR13_VRCG_MASK | DDR_PHY_MR13_VRO_MASK | DDR_PHY_MR13_RPT_MASK | DDR_PHY_MR13_CBT_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR13_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_FSPOP_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_FSPWR_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_DMD_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_RRO_SHIFT
+			| 0x00000001U << DDR_PHY_MR13_VRCG_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_VRO_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_RPT_SHIFT
+			| 0x00000000U << DDR_PHY_MR13_CBT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR13_OFFSET ,0xFFFFFFFFU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MR14 @ 0XFD0801B8

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR14_RESERVED_31_8                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR14_RSVD                                                           0x0
+
+		VREFDQ Range Selects.
+		PSU_DDR_PHY_MR14_VR_DQ                                                          0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR14_VREF_DQ                                                        0xd
+
+		LPDDR4 Mode Register 14
+		(OFFSET, MASK, VALUE)      (0XFD0801B8, 0xFFFFFFFFU ,0x0000004DU)  
+		RegMask = (DDR_PHY_MR14_RESERVED_31_8_MASK | DDR_PHY_MR14_RSVD_MASK | DDR_PHY_MR14_VR_DQ_MASK | DDR_PHY_MR14_VREF_DQ_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR14_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR14_RSVD_SHIFT
+			| 0x00000001U << DDR_PHY_MR14_VR_DQ_SHIFT
+			| 0x0000000DU << DDR_PHY_MR14_VREF_DQ_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR14_OFFSET ,0xFFFFFFFFU ,0x0000004DU);
+	/*############################################################################################################################ */
+
+		/*Register : MR22 @ 0XFD0801D8

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_MR22_RESERVED_31_8                                                  0x0
+
+		These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.
+		PSU_DDR_PHY_MR22_RSVD                                                           0x0
+
+		CA ODT termination disable.
+		PSU_DDR_PHY_MR22_ODTD_CA                                                        0x0
+
+		ODT CS override.
+		PSU_DDR_PHY_MR22_ODTE_CS                                                        0x0
+
+		ODT CK override.
+		PSU_DDR_PHY_MR22_ODTE_CK                                                        0x0
+
+		Controller ODT value for VOH calibration.
+		PSU_DDR_PHY_MR22_CODT                                                           0x0
+
+		LPDDR4 Mode Register 22
+		(OFFSET, MASK, VALUE)      (0XFD0801D8, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_MR22_RESERVED_31_8_MASK | DDR_PHY_MR22_RSVD_MASK | DDR_PHY_MR22_ODTD_CA_MASK | DDR_PHY_MR22_ODTE_CS_MASK | DDR_PHY_MR22_ODTE_CK_MASK | DDR_PHY_MR22_CODT_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_MR22_RESERVED_31_8_SHIFT
+			| 0x00000000U << DDR_PHY_MR22_RSVD_SHIFT
+			| 0x00000000U << DDR_PHY_MR22_ODTD_CA_SHIFT
+			| 0x00000000U << DDR_PHY_MR22_ODTE_CS_SHIFT
+			| 0x00000000U << DDR_PHY_MR22_ODTE_CK_SHIFT
+			| 0x00000000U << DDR_PHY_MR22_CODT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_MR22_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DTCR0 @ 0XFD080200

+
+		Refresh During Training
+		PSU_DDR_PHY_DTCR0_RFSHDT                                                        0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR0_RESERVED_27_26                                                0x0
+
+		Data Training Debug Rank Select
+		PSU_DDR_PHY_DTCR0_DTDRS                                                         0x1
+
+		Data Training with Early/Extended Gate
+		PSU_DDR_PHY_DTCR0_DTEXG                                                         0x0
+
+		Data Training Extended Write DQS
+		PSU_DDR_PHY_DTCR0_DTEXD                                                         0x0
+
+		Data Training Debug Step
+		PSU_DDR_PHY_DTCR0_DTDSTP                                                        0x0
+
+		Data Training Debug Enable
+		PSU_DDR_PHY_DTCR0_DTDEN                                                         0x0
+
+		Data Training Debug Byte Select
+		PSU_DDR_PHY_DTCR0_DTDBS                                                         0x0
+
+		Data Training read DBI deskewing configuration
+		PSU_DDR_PHY_DTCR0_DTRDBITR                                                      0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR0_RESERVED_13                                                   0x0
+
+		Data Training Write Bit Deskew Data Mask
+		PSU_DDR_PHY_DTCR0_DTWBDDM                                                       0x1
+
+		Refreshes Issued During Entry to Training
+		PSU_DDR_PHY_DTCR0_RFSHEN                                                        0x1
+
+		Data Training Compare Data
+		PSU_DDR_PHY_DTCR0_DTCMPD                                                        0x1
+
+		Data Training Using MPR
+		PSU_DDR_PHY_DTCR0_DTMPR                                                         0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR0_RESERVED_5_4                                                  0x0
+
+		Data Training Repeat Number
+		PSU_DDR_PHY_DTCR0_DTRPTN                                                        0x7
+
+		Data Training Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080200, 0xFFFFFFFFU ,0x810011C7U)  
+		RegMask = (DDR_PHY_DTCR0_RFSHDT_MASK | DDR_PHY_DTCR0_RESERVED_27_26_MASK | DDR_PHY_DTCR0_DTDRS_MASK | DDR_PHY_DTCR0_DTEXG_MASK | DDR_PHY_DTCR0_DTEXD_MASK | DDR_PHY_DTCR0_DTDSTP_MASK | DDR_PHY_DTCR0_DTDEN_MASK | DDR_PHY_DTCR0_DTDBS_MASK | DDR_PHY_DTCR0_DTRDBITR_MASK | DDR_PHY_DTCR0_RESERVED_13_MASK | DDR_PHY_DTCR0_DTWBDDM_MASK | DDR_PHY_DTCR0_RFSHEN_MASK | DDR_PHY_DTCR0_DTCMPD_MASK | DDR_PHY_DTCR0_DTMPR_MASK | DDR_PHY_DTCR0_RESERVED_5_4_MASK | DDR_PHY_DTCR0_DTRPTN_MASK |  0 );
+
+		RegVal = ((0x00000008U << DDR_PHY_DTCR0_RFSHDT_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_RESERVED_27_26_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR0_DTDRS_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTEXG_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTEXD_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTDSTP_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTDBS_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_DTRDBITR_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_RESERVED_13_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR0_DTWBDDM_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR0_RFSHEN_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR0_DTCMPD_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR0_DTMPR_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR0_RESERVED_5_4_SHIFT
+			| 0x00000007U << DDR_PHY_DTCR0_DTRPTN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTCR0_OFFSET ,0xFFFFFFFFU ,0x810011C7U);
+	/*############################################################################################################################ */
+
+		/*Register : DTCR1 @ 0XFD080204

+
+		Rank Enable.
+		PSU_DDR_PHY_DTCR1_RANKEN_RSVD                                                   0x0
+
+		Rank Enable.
+		PSU_DDR_PHY_DTCR1_RANKEN                                                        0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR1_RESERVED_15_14                                                0x0
+
+		Data Training Rank
+		PSU_DDR_PHY_DTCR1_DTRANK                                                        0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR1_RESERVED_11                                                   0x0
+
+		Read Leveling Gate Sampling Difference
+		PSU_DDR_PHY_DTCR1_RDLVLGDIFF                                                    0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR1_RESERVED_7                                                    0x0
+
+		Read Leveling Gate Shift
+		PSU_DDR_PHY_DTCR1_RDLVLGS                                                       0x3
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DTCR1_RESERVED_3                                                    0x0
+
+		Read Preamble Training enable
+		PSU_DDR_PHY_DTCR1_RDPRMVL_TRN                                                   0x1
+
+		Read Leveling Enable
+		PSU_DDR_PHY_DTCR1_RDLVLEN                                                       0x1
+
+		Basic Gate Training Enable
+		PSU_DDR_PHY_DTCR1_BSTEN                                                         0x0
+
+		Data Training Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080204, 0xFFFFFFFFU ,0x00010236U)  
+		RegMask = (DDR_PHY_DTCR1_RANKEN_RSVD_MASK | DDR_PHY_DTCR1_RANKEN_MASK | DDR_PHY_DTCR1_RESERVED_15_14_MASK | DDR_PHY_DTCR1_DTRANK_MASK | DDR_PHY_DTCR1_RESERVED_11_MASK | DDR_PHY_DTCR1_RDLVLGDIFF_MASK | DDR_PHY_DTCR1_RESERVED_7_MASK | DDR_PHY_DTCR1_RDLVLGS_MASK | DDR_PHY_DTCR1_RESERVED_3_MASK | DDR_PHY_DTCR1_RDPRMVL_TRN_MASK | DDR_PHY_DTCR1_RDLVLEN_MASK | DDR_PHY_DTCR1_BSTEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR1_RANKEN_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_RESERVED_15_14_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_DTRANK_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_RESERVED_11_SHIFT
+			| 0x00000002U << DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_RESERVED_7_SHIFT
+			| 0x00000003U << DDR_PHY_DTCR1_RDLVLGS_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_RESERVED_3_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT
+			| 0x00000001U << DDR_PHY_DTCR1_RDLVLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DTCR1_BSTEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DTCR1_OFFSET ,0xFFFFFFFFU ,0x00010236U);
+	/*############################################################################################################################ */
+
+		/*Register : CATR0 @ 0XFD080240

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_CATR0_RESERVED_31_21                                                0x0
+
+		Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command
+		PSU_DDR_PHY_CATR0_CACD                                                          0x14
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_CATR0_RESERVED_15_13                                                0x0
+
+		Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
+		 been sent to the memory
+		PSU_DDR_PHY_CATR0_CAADR                                                         0x10
+
+		CA_1 Response Byte Lane 1
+		PSU_DDR_PHY_CATR0_CA1BYTE1                                                      0x5
+
+		CA_1 Response Byte Lane 0
+		PSU_DDR_PHY_CATR0_CA1BYTE0                                                      0x4
+
+		CA Training Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080240, 0xFFFFFFFFU ,0x00141054U)  
+		RegMask = (DDR_PHY_CATR0_RESERVED_31_21_MASK | DDR_PHY_CATR0_CACD_MASK | DDR_PHY_CATR0_RESERVED_15_13_MASK | DDR_PHY_CATR0_CAADR_MASK | DDR_PHY_CATR0_CA1BYTE1_MASK | DDR_PHY_CATR0_CA1BYTE0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_CATR0_RESERVED_31_21_SHIFT
+			| 0x00000014U << DDR_PHY_CATR0_CACD_SHIFT
+			| 0x00000000U << DDR_PHY_CATR0_RESERVED_15_13_SHIFT
+			| 0x00000010U << DDR_PHY_CATR0_CAADR_SHIFT
+			| 0x00000005U << DDR_PHY_CATR0_CA1BYTE1_SHIFT
+			| 0x00000004U << DDR_PHY_CATR0_CA1BYTE0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_CATR0_OFFSET ,0xFFFFFFFFU ,0x00141054U);
+	/*############################################################################################################################ */
+
+		/*Register : RIOCR5 @ 0XFD0804F4

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_RIOCR5_RESERVED_31_16                                               0x0
+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_RIOCR5_ODTOEMODE_RSVD                                               0x0
+
+		SDRAM On-die Termination Output Enable (OE) Mode Selection.
+		PSU_DDR_PHY_RIOCR5_ODTOEMODE                                                    0x5
+
+		Rank I/O Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD0804F4, 0xFFFFFFFFU ,0x00000005U)  
+		RegMask = (DDR_PHY_RIOCR5_RESERVED_31_16_MASK | DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK | DDR_PHY_RIOCR5_ODTOEMODE_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT
+			| 0x00000000U << DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT
+			| 0x00000005U << DDR_PHY_RIOCR5_ODTOEMODE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_RIOCR5_OFFSET ,0xFFFFFFFFU ,0x00000005U);
+	/*############################################################################################################################ */
+
+		/*Register : ACIOCR0 @ 0XFD080500

+
+		Address/Command Slew Rate (D3F I/O Only)
+		PSU_DDR_PHY_ACIOCR0_ACSR                                                        0x0
+
+		SDRAM Reset I/O Mode
+		PSU_DDR_PHY_ACIOCR0_RSTIOM                                                      0x1
+
+		SDRAM Reset Power Down Receiver
+		PSU_DDR_PHY_ACIOCR0_RSTPDR                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACIOCR0_RESERVED_27                                                 0x0
+
+		SDRAM Reset On-Die Termination
+		PSU_DDR_PHY_ACIOCR0_RSTODT                                                      0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACIOCR0_RESERVED_25_10                                              0x0
+
+		CK Duty Cycle Correction
+		PSU_DDR_PHY_ACIOCR0_CKDCC                                                       0x0
+
+		AC Power Down Receiver Mode
+		PSU_DDR_PHY_ACIOCR0_ACPDRMODE                                                   0x2
+
+		AC On-die Termination Mode
+		PSU_DDR_PHY_ACIOCR0_ACODTMODE                                                   0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACIOCR0_RESERVED_1                                                  0x0
+
+		Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.
+		PSU_DDR_PHY_ACIOCR0_ACRANKCLKSEL                                                0x0
+
+		AC I/O Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080500, 0xFFFFFFFFU ,0x30000028U)  
+		RegMask = (DDR_PHY_ACIOCR0_ACSR_MASK | DDR_PHY_ACIOCR0_RSTIOM_MASK | DDR_PHY_ACIOCR0_RSTPDR_MASK | DDR_PHY_ACIOCR0_RESERVED_27_MASK | DDR_PHY_ACIOCR0_RSTODT_MASK | DDR_PHY_ACIOCR0_RESERVED_25_10_MASK | DDR_PHY_ACIOCR0_CKDCC_MASK | DDR_PHY_ACIOCR0_ACPDRMODE_MASK | DDR_PHY_ACIOCR0_ACODTMODE_MASK | DDR_PHY_ACIOCR0_RESERVED_1_MASK | DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACIOCR0_ACSR_SHIFT
+			| 0x00000001U << DDR_PHY_ACIOCR0_RSTIOM_SHIFT
+			| 0x00000001U << DDR_PHY_ACIOCR0_RSTPDR_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_27_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_RSTODT_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_CKDCC_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR0_ACODTMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_RESERVED_1_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACIOCR0_OFFSET ,0xFFFFFFFFU ,0x30000028U);
+	/*############################################################################################################################ */
+
+		/*Register : ACIOCR2 @ 0XFD080508

+
+		Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice
+		PSU_DDR_PHY_ACIOCR2_CLKGENCLKGATE                                               0x0
+
+		Clock gating for Output Enable D slices [0]
+		PSU_DDR_PHY_ACIOCR2_ACOECLKGATE0                                                0x0
+
+		Clock gating for Power Down Receiver D slices [0]
+		PSU_DDR_PHY_ACIOCR2_ACPDRCLKGATE0                                               0x0
+
+		Clock gating for Termination Enable D slices [0]
+		PSU_DDR_PHY_ACIOCR2_ACTECLKGATE0                                                0x0
+
+		Clock gating for CK# D slices [1:0]
+		PSU_DDR_PHY_ACIOCR2_CKNCLKGATE0                                                 0x2
+
+		Clock gating for CK D slices [1:0]
+		PSU_DDR_PHY_ACIOCR2_CKCLKGATE0                                                  0x2
+
+		Clock gating for AC D slices [23:0]
+		PSU_DDR_PHY_ACIOCR2_ACCLKGATE0                                                  0x0
+
+		AC I/O Configuration Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080508, 0xFFFFFFFFU ,0x0A000000U)  
+		RegMask = (DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK | DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK | DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK | DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK | DDR_PHY_ACIOCR2_CKCLKGATE0_MASK | DDR_PHY_ACIOCR2_ACCLKGATE0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACIOCR2_OFFSET ,0xFFFFFFFFU ,0x0A000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ACIOCR3 @ 0XFD08050C

+
+		SDRAM Parity Output Enable (OE) Mode Selection
+		PSU_DDR_PHY_ACIOCR3_PAROEMODE                                                   0x0
+
+		SDRAM Bank Group Output Enable (OE) Mode Selection
+		PSU_DDR_PHY_ACIOCR3_BGOEMODE                                                    0x0
+
+		SDRAM Bank Address Output Enable (OE) Mode Selection
+		PSU_DDR_PHY_ACIOCR3_BAOEMODE                                                    0x0
+
+		SDRAM A[17] Output Enable (OE) Mode Selection
+		PSU_DDR_PHY_ACIOCR3_A17OEMODE                                                   0x0
+
+		SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection
+		PSU_DDR_PHY_ACIOCR3_A16OEMODE                                                   0x0
+
+		SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)
+		PSU_DDR_PHY_ACIOCR3_ACTOEMODE                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACIOCR3_RESERVED_15_8                                               0x0
+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_ACIOCR3_CKOEMODE_RSVD                                               0x0
+
+		SDRAM CK Output Enable (OE) Mode Selection.
+		PSU_DDR_PHY_ACIOCR3_CKOEMODE                                                    0x9
+
+		AC I/O Configuration Register 3
+		(OFFSET, MASK, VALUE)      (0XFD08050C, 0xFFFFFFFFU ,0x00000009U)  
+		RegMask = (DDR_PHY_ACIOCR3_PAROEMODE_MASK | DDR_PHY_ACIOCR3_BGOEMODE_MASK | DDR_PHY_ACIOCR3_BAOEMODE_MASK | DDR_PHY_ACIOCR3_A17OEMODE_MASK | DDR_PHY_ACIOCR3_A16OEMODE_MASK | DDR_PHY_ACIOCR3_ACTOEMODE_MASK | DDR_PHY_ACIOCR3_RESERVED_15_8_MASK | DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK | DDR_PHY_ACIOCR3_CKOEMODE_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACIOCR3_PAROEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_BGOEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_BAOEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_A17OEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_A16OEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT
+			| 0x00000009U << DDR_PHY_ACIOCR3_CKOEMODE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACIOCR3_OFFSET ,0xFFFFFFFFU ,0x00000009U);
+	/*############################################################################################################################ */
+
+		/*Register : ACIOCR4 @ 0XFD080510

+
+		Clock gating for AC LB slices and loopback read valid slices
+		PSU_DDR_PHY_ACIOCR4_LBCLKGATE                                                   0x0
+
+		Clock gating for Output Enable D slices [1]
+		PSU_DDR_PHY_ACIOCR4_ACOECLKGATE1                                                0x0
+
+		Clock gating for Power Down Receiver D slices [1]
+		PSU_DDR_PHY_ACIOCR4_ACPDRCLKGATE1                                               0x0
+
+		Clock gating for Termination Enable D slices [1]
+		PSU_DDR_PHY_ACIOCR4_ACTECLKGATE1                                                0x0
+
+		Clock gating for CK# D slices [3:2]
+		PSU_DDR_PHY_ACIOCR4_CKNCLKGATE1                                                 0x2
+
+		Clock gating for CK D slices [3:2]
+		PSU_DDR_PHY_ACIOCR4_CKCLKGATE1                                                  0x2
+
+		Clock gating for AC D slices [47:24]
+		PSU_DDR_PHY_ACIOCR4_ACCLKGATE1                                                  0x0
+
+		AC I/O Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080510, 0xFFFFFFFFU ,0x0A000000U)  
+		RegMask = (DDR_PHY_ACIOCR4_LBCLKGATE_MASK | DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK | DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK | DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK | DDR_PHY_ACIOCR4_CKCLKGATE1_MASK | DDR_PHY_ACIOCR4_ACCLKGATE1_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT
+			| 0x00000002U << DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT
+			| 0x00000000U << DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACIOCR4_OFFSET ,0xFFFFFFFFU ,0x0A000000U);
+	/*############################################################################################################################ */
+
+		/*Register : IOVCR0 @ 0XFD080520

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_IOVCR0_RESERVED_31_29                                               0x0
+
+		Address/command lane VREF Pad Enable
+		PSU_DDR_PHY_IOVCR0_ACREFPEN                                                     0x0
+
+		Address/command lane Internal VREF Enable
+		PSU_DDR_PHY_IOVCR0_ACREFEEN                                                     0x0
+
+		Address/command lane Single-End VREF Enable
+		PSU_DDR_PHY_IOVCR0_ACREFSEN                                                     0x1
+
+		Address/command lane Internal VREF Enable
+		PSU_DDR_PHY_IOVCR0_ACREFIEN                                                     0x1
+
+		External VREF generato REFSEL range select
+		PSU_DDR_PHY_IOVCR0_ACREFESELRANGE                                               0x0
+
+		Address/command lane External VREF Select
+		PSU_DDR_PHY_IOVCR0_ACREFESEL                                                    0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_IOVCR0_ACREFSSELRANGE                                               0x1
+
+		Address/command lane Single-End VREF Select
+		PSU_DDR_PHY_IOVCR0_ACREFSSEL                                                    0x30
+
+		Internal VREF generator REFSEL ragne select
+		PSU_DDR_PHY_IOVCR0_ACVREFISELRANGE                                              0x1
+
+		REFSEL Control for internal AC IOs
+		PSU_DDR_PHY_IOVCR0_ACVREFISEL                                                   0x30
+
+		IO VREF Control Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080520, 0xFFFFFFFFU ,0x0300B0B0U)  
+		RegMask = (DDR_PHY_IOVCR0_RESERVED_31_29_MASK | DDR_PHY_IOVCR0_ACREFPEN_MASK | DDR_PHY_IOVCR0_ACREFEEN_MASK | DDR_PHY_IOVCR0_ACREFSEN_MASK | DDR_PHY_IOVCR0_ACREFIEN_MASK | DDR_PHY_IOVCR0_ACREFESELRANGE_MASK | DDR_PHY_IOVCR0_ACREFESEL_MASK | DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK | DDR_PHY_IOVCR0_ACREFSSEL_MASK | DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK | DDR_PHY_IOVCR0_ACVREFISEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_IOVCR0_ACREFPEN_SHIFT
+			| 0x00000000U << DDR_PHY_IOVCR0_ACREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_IOVCR0_ACREFSEN_SHIFT
+			| 0x00000001U << DDR_PHY_IOVCR0_ACREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_IOVCR0_ACREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_IOVCR0_ACREFSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_IOVCR0_ACVREFISEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_IOVCR0_OFFSET ,0xFFFFFFFFU ,0x0300B0B0U);
+	/*############################################################################################################################ */
+
+		/*Register : VTCR0 @ 0XFD080528

+
+		Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training
+		PSU_DDR_PHY_VTCR0_TVREF                                                         0x7
+
+		DRM DQ VREF training Enable
+		PSU_DDR_PHY_VTCR0_DVEN                                                          0x1
+
+		Per Device Addressability Enable
+		PSU_DDR_PHY_VTCR0_PDAEN                                                         0x1
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_VTCR0_RESERVED_26                                                   0x0
+
+		VREF Word Count
+		PSU_DDR_PHY_VTCR0_VWCR                                                          0x4
+
+		DRAM DQ VREF step size used during DRAM VREF training
+		PSU_DDR_PHY_VTCR0_DVSS                                                          0x0
+
+		Maximum VREF limit value used during DRAM VREF training
+		PSU_DDR_PHY_VTCR0_DVMAX                                                         0x32
+
+		Minimum VREF limit value used during DRAM VREF training
+		PSU_DDR_PHY_VTCR0_DVMIN                                                         0x0
+
+		Initial DRAM DQ VREF value used during DRAM VREF training
+		PSU_DDR_PHY_VTCR0_DVINIT                                                        0x19
+
+		VREF Training Control Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080528, 0xFFFFFFFFU ,0xF9032019U)  
+		RegMask = (DDR_PHY_VTCR0_TVREF_MASK | DDR_PHY_VTCR0_DVEN_MASK | DDR_PHY_VTCR0_PDAEN_MASK | DDR_PHY_VTCR0_RESERVED_26_MASK | DDR_PHY_VTCR0_VWCR_MASK | DDR_PHY_VTCR0_DVSS_MASK | DDR_PHY_VTCR0_DVMAX_MASK | DDR_PHY_VTCR0_DVMIN_MASK | DDR_PHY_VTCR0_DVINIT_MASK |  0 );
+
+		RegVal = ((0x00000007U << DDR_PHY_VTCR0_TVREF_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR0_DVEN_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR0_PDAEN_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR0_RESERVED_26_SHIFT
+			| 0x00000004U << DDR_PHY_VTCR0_VWCR_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR0_DVSS_SHIFT
+			| 0x00000032U << DDR_PHY_VTCR0_DVMAX_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR0_DVMIN_SHIFT
+			| 0x00000019U << DDR_PHY_VTCR0_DVINIT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_VTCR0_OFFSET ,0xFFFFFFFFU ,0xF9032019U);
+	/*############################################################################################################################ */
+
+		/*Register : VTCR1 @ 0XFD08052C

+
+		Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)
+		PSU_DDR_PHY_VTCR1_HVSS                                                          0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_VTCR1_RESERVED_27                                                   0x0
+
+		Maximum VREF limit value used during DRAM VREF training.
+		PSU_DDR_PHY_VTCR1_HVMAX                                                         0x7f
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_VTCR1_RESERVED_19                                                   0x0
+
+		Minimum VREF limit value used during DRAM VREF training.
+		PSU_DDR_PHY_VTCR1_HVMIN                                                         0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_VTCR1_RESERVED_11                                                   0x0
+
+		Static Host Vref Rank Value
+		PSU_DDR_PHY_VTCR1_SHRNK                                                         0x0
+
+		Static Host Vref Rank Enable
+		PSU_DDR_PHY_VTCR1_SHREN                                                         0x1
+
+		Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training
+		PSU_DDR_PHY_VTCR1_TVREFIO                                                       0x4
+
+		Eye LCDL Offset value for VREF training
+		PSU_DDR_PHY_VTCR1_EOFF                                                          0x1
+
+		Number of LCDL Eye points for which VREF training is repeated
+		PSU_DDR_PHY_VTCR1_ENUM                                                          0x1
+
+		HOST (IO) internal VREF training Enable
+		PSU_DDR_PHY_VTCR1_HVEN                                                          0x1
+
+		Host IO Type Control
+		PSU_DDR_PHY_VTCR1_HVIO                                                          0x1
+
+		VREF Training Control Register 1
+		(OFFSET, MASK, VALUE)      (0XFD08052C, 0xFFFFFFFFU ,0x07F0018FU)  
+		RegMask = (DDR_PHY_VTCR1_HVSS_MASK | DDR_PHY_VTCR1_RESERVED_27_MASK | DDR_PHY_VTCR1_HVMAX_MASK | DDR_PHY_VTCR1_RESERVED_19_MASK | DDR_PHY_VTCR1_HVMIN_MASK | DDR_PHY_VTCR1_RESERVED_11_MASK | DDR_PHY_VTCR1_SHRNK_MASK | DDR_PHY_VTCR1_SHREN_MASK | DDR_PHY_VTCR1_TVREFIO_MASK | DDR_PHY_VTCR1_EOFF_MASK | DDR_PHY_VTCR1_ENUM_MASK | DDR_PHY_VTCR1_HVEN_MASK | DDR_PHY_VTCR1_HVIO_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_VTCR1_HVSS_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR1_RESERVED_27_SHIFT
+			| 0x0000007FU << DDR_PHY_VTCR1_HVMAX_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR1_RESERVED_19_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR1_HVMIN_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR1_RESERVED_11_SHIFT
+			| 0x00000000U << DDR_PHY_VTCR1_SHRNK_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR1_SHREN_SHIFT
+			| 0x00000004U << DDR_PHY_VTCR1_TVREFIO_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR1_EOFF_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR1_ENUM_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR1_HVEN_SHIFT
+			| 0x00000001U << DDR_PHY_VTCR1_HVIO_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_VTCR1_OFFSET ,0xFFFFFFFFU ,0x07F0018FU);
+	/*############################################################################################################################ */
+
+		/*Register : ACBDLR6 @ 0XFD080558

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR6_RESERVED_31_30                                              0x0
+
+		Delay select for the BDL on Address A[3].
+		PSU_DDR_PHY_ACBDLR6_A03BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR6_RESERVED_23_22                                              0x0
+
+		Delay select for the BDL on Address A[2].
+		PSU_DDR_PHY_ACBDLR6_A02BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR6_RESERVED_15_14                                              0x0
+
+		Delay select for the BDL on Address A[1].
+		PSU_DDR_PHY_ACBDLR6_A01BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR6_RESERVED_7_6                                                0x0
+
+		Delay select for the BDL on Address A[0].
+		PSU_DDR_PHY_ACBDLR6_A00BD                                                       0x0
+
+		AC Bit Delay Line Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080558, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_ACBDLR6_RESERVED_31_30_MASK | DDR_PHY_ACBDLR6_A03BD_MASK | DDR_PHY_ACBDLR6_RESERVED_23_22_MASK | DDR_PHY_ACBDLR6_A02BD_MASK | DDR_PHY_ACBDLR6_RESERVED_15_14_MASK | DDR_PHY_ACBDLR6_A01BD_MASK | DDR_PHY_ACBDLR6_RESERVED_7_6_MASK | DDR_PHY_ACBDLR6_A00BD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_A03BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_A02BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_A01BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR6_A00BD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACBDLR6_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ACBDLR7 @ 0XFD08055C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR7_RESERVED_31_30                                              0x0
+
+		Delay select for the BDL on Address A[7].
+		PSU_DDR_PHY_ACBDLR7_A07BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR7_RESERVED_23_22                                              0x0
+
+		Delay select for the BDL on Address A[6].
+		PSU_DDR_PHY_ACBDLR7_A06BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR7_RESERVED_15_14                                              0x0
+
+		Delay select for the BDL on Address A[5].
+		PSU_DDR_PHY_ACBDLR7_A05BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR7_RESERVED_7_6                                                0x0
+
+		Delay select for the BDL on Address A[4].
+		PSU_DDR_PHY_ACBDLR7_A04BD                                                       0x0
+
+		AC Bit Delay Line Register 7
+		(OFFSET, MASK, VALUE)      (0XFD08055C, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_ACBDLR7_RESERVED_31_30_MASK | DDR_PHY_ACBDLR7_A07BD_MASK | DDR_PHY_ACBDLR7_RESERVED_23_22_MASK | DDR_PHY_ACBDLR7_A06BD_MASK | DDR_PHY_ACBDLR7_RESERVED_15_14_MASK | DDR_PHY_ACBDLR7_A05BD_MASK | DDR_PHY_ACBDLR7_RESERVED_7_6_MASK | DDR_PHY_ACBDLR7_A04BD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_A07BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_A06BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_A05BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR7_A04BD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACBDLR7_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ACBDLR8 @ 0XFD080560

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR8_RESERVED_31_30                                              0x0
+
+		Delay select for the BDL on Address A[11].
+		PSU_DDR_PHY_ACBDLR8_A11BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR8_RESERVED_23_22                                              0x0
+
+		Delay select for the BDL on Address A[10].
+		PSU_DDR_PHY_ACBDLR8_A10BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR8_RESERVED_15_14                                              0x0
+
+		Delay select for the BDL on Address A[9].
+		PSU_DDR_PHY_ACBDLR8_A09BD                                                       0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ACBDLR8_RESERVED_7_6                                                0x0
+
+		Delay select for the BDL on Address A[8].
+		PSU_DDR_PHY_ACBDLR8_A08BD                                                       0x0
+
+		AC Bit Delay Line Register 8
+		(OFFSET, MASK, VALUE)      (0XFD080560, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_ACBDLR8_RESERVED_31_30_MASK | DDR_PHY_ACBDLR8_A11BD_MASK | DDR_PHY_ACBDLR8_RESERVED_23_22_MASK | DDR_PHY_ACBDLR8_A10BD_MASK | DDR_PHY_ACBDLR8_RESERVED_15_14_MASK | DDR_PHY_ACBDLR8_A09BD_MASK | DDR_PHY_ACBDLR8_RESERVED_7_6_MASK | DDR_PHY_ACBDLR8_A08BD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_A11BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_A10BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_A09BD_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT
+			| 0x00000000U << DDR_PHY_ACBDLR8_A08BD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ACBDLR8_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQCR @ 0XFD080680

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_ZQCR_RESERVED_31_26                                                 0x0
+
+		ZQ VREF Range
+		PSU_DDR_PHY_ZQCR_ZQREFISELRANGE                                                 0x0
+
+		Programmable Wait for Frequency B
+		PSU_DDR_PHY_ZQCR_PGWAIT_FRQB                                                    0x11
+
+		Programmable Wait for Frequency A
+		PSU_DDR_PHY_ZQCR_PGWAIT_FRQA                                                    0x11
+
+		ZQ VREF Pad Enable
+		PSU_DDR_PHY_ZQCR_ZQREFPEN                                                       0x0
+
+		ZQ Internal VREF Enable
+		PSU_DDR_PHY_ZQCR_ZQREFIEN                                                       0x1
+
+		Choice of termination mode
+		PSU_DDR_PHY_ZQCR_ODT_MODE                                                       0x1
+
+		Force ZCAL VT update
+		PSU_DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE                                           0x0
+
+		IO VT Drift Limit
+		PSU_DDR_PHY_ZQCR_IODLMT                                                         0x2
+
+		Averaging algorithm enable, if set, enables averaging algorithm
+		PSU_DDR_PHY_ZQCR_AVGEN                                                          0x1
+
+		Maximum number of averaging rounds to be used by averaging algorithm
+		PSU_DDR_PHY_ZQCR_AVGMAX                                                         0x2
+
+		ZQ Calibration Type
+		PSU_DDR_PHY_ZQCR_ZCALT                                                          0x0
+
+		ZQ Power Down
+		PSU_DDR_PHY_ZQCR_ZQPD                                                           0x0
+
+		ZQ Impedance Control Register
+		(OFFSET, MASK, VALUE)      (0XFD080680, 0xFFFFFFFFU ,0x008A2A58U)  
+		RegMask = (DDR_PHY_ZQCR_RESERVED_31_26_MASK | DDR_PHY_ZQCR_ZQREFISELRANGE_MASK | DDR_PHY_ZQCR_PGWAIT_FRQB_MASK | DDR_PHY_ZQCR_PGWAIT_FRQA_MASK | DDR_PHY_ZQCR_ZQREFPEN_MASK | DDR_PHY_ZQCR_ZQREFIEN_MASK | DDR_PHY_ZQCR_ODT_MODE_MASK | DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK | DDR_PHY_ZQCR_IODLMT_MASK | DDR_PHY_ZQCR_AVGEN_MASK | DDR_PHY_ZQCR_AVGMAX_MASK | DDR_PHY_ZQCR_ZCALT_MASK | DDR_PHY_ZQCR_ZQPD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ZQCR_RESERVED_31_26_SHIFT
+			| 0x00000000U << DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT
+			| 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT
+			| 0x00000011U << DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT
+			| 0x00000000U << DDR_PHY_ZQCR_ZQREFPEN_SHIFT
+			| 0x00000001U << DDR_PHY_ZQCR_ZQREFIEN_SHIFT
+			| 0x00000001U << DDR_PHY_ZQCR_ODT_MODE_SHIFT
+			| 0x00000000U << DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT
+			| 0x00000002U << DDR_PHY_ZQCR_IODLMT_SHIFT
+			| 0x00000001U << DDR_PHY_ZQCR_AVGEN_SHIFT
+			| 0x00000002U << DDR_PHY_ZQCR_AVGMAX_SHIFT
+			| 0x00000000U << DDR_PHY_ZQCR_ZCALT_SHIFT
+			| 0x00000000U << DDR_PHY_ZQCR_ZQPD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ZQCR_OFFSET ,0xFFFFFFFFU ,0x008A2A58U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQ0PR0 @ 0XFD080684

+
+		Pull-down drive strength ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ0PR0_PD_DRV_ZDEN                                                  0x0
+
+		Pull-up drive strength ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ0PR0_PU_DRV_ZDEN                                                  0x0
+
+		Pull-down termination ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ0PR0_PD_ODT_ZDEN                                                  0x0
+
+		Pull-up termination ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ0PR0_PU_ODT_ZDEN                                                  0x0
+
+		Calibration segment bypass
+		PSU_DDR_PHY_ZQ0PR0_ZSEGBYP                                                      0x0
+
+		VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
+		PSU_DDR_PHY_ZQ0PR0_ZLE_MODE                                                     0x0
+
+		Termination adjustment
+		PSU_DDR_PHY_ZQ0PR0_ODT_ADJUST                                                   0x0
+
+		Pulldown drive strength adjustment
+		PSU_DDR_PHY_ZQ0PR0_PD_DRV_ADJUST                                                0x0
+
+		Pullup drive strength adjustment
+		PSU_DDR_PHY_ZQ0PR0_PU_DRV_ADJUST                                                0x0
+
+		DRAM Impedance Divide Ratio
+		PSU_DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT                                               0x7
+
+		HOST Impedance Divide Ratio
+		PSU_DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT                                               0x7
+
+		Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
+		PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD                                            0xd
+
+		Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
+		PSU_DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU                                            0xd
+
+		ZQ n Impedance Control Program Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080684, 0xFFFFFFFFU ,0x000077DDU)  
+		RegMask = (DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ0PR0_ZSEGBYP_MASK | DDR_PHY_ZQ0PR0_ZLE_MODE_MASK | DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT
+			| 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT
+			| 0x00000007U << DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT
+			| 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT
+			| 0x0000000DU << DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ZQ0PR0_OFFSET ,0xFFFFFFFFU ,0x000077DDU);
+	/*############################################################################################################################ */
+
+		/*Register : ZQ0OR0 @ 0XFD080694

+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_ZQ0OR0_RESERVED_31_26                                               0x0
+
+		Override value for the pull-up output impedance
+		PSU_DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD                                            0x1e1
+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_ZQ0OR0_RESERVED_15_10                                               0x0
+
+		Override value for the pull-down output impedance
+		PSU_DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD                                            0x210
+
+		ZQ n Impedance Control Override Data Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080694, 0xFFFFFFFFU ,0x01E10210U)  
+		RegMask = (DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK | DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT
+			| 0x000001E1U << DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT
+			| 0x00000210U << DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ZQ0OR0_OFFSET ,0xFFFFFFFFU ,0x01E10210U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQ0OR1 @ 0XFD080698

+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_ZQ0OR1_RESERVED_31_26                                               0x0
+
+		Override value for the pull-up termination
+		PSU_DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD                                            0x1e1
+
+		Reserved. Return zeros on reads.
+		PSU_DDR_PHY_ZQ0OR1_RESERVED_15_10                                               0x0
+
+		Override value for the pull-down termination
+		PSU_DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD                                            0x0
+
+		ZQ n Impedance Control Override Data Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080698, 0xFFFFFFFFU ,0x01E10000U)  
+		RegMask = (DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK | DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK | DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK | DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT
+			| 0x000001E1U << DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ZQ0OR1_OFFSET ,0xFFFFFFFFU ,0x01E10000U);
+	/*############################################################################################################################ */
+
+		/*Register : ZQ1PR0 @ 0XFD0806A4

+
+		Pull-down drive strength ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ1PR0_PD_DRV_ZDEN                                                  0x0
+
+		Pull-up drive strength ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ1PR0_PU_DRV_ZDEN                                                  0x0
+
+		Pull-down termination ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ1PR0_PD_ODT_ZDEN                                                  0x0
+
+		Pull-up termination ZCTRL over-ride enable
+		PSU_DDR_PHY_ZQ1PR0_PU_ODT_ZDEN                                                  0x0
+
+		Calibration segment bypass
+		PSU_DDR_PHY_ZQ1PR0_ZSEGBYP                                                      0x0
+
+		VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB
+		PSU_DDR_PHY_ZQ1PR0_ZLE_MODE                                                     0x0
+
+		Termination adjustment
+		PSU_DDR_PHY_ZQ1PR0_ODT_ADJUST                                                   0x0
+
+		Pulldown drive strength adjustment
+		PSU_DDR_PHY_ZQ1PR0_PD_DRV_ADJUST                                                0x1
+
+		Pullup drive strength adjustment
+		PSU_DDR_PHY_ZQ1PR0_PU_DRV_ADJUST                                                0x0
+
+		DRAM Impedance Divide Ratio
+		PSU_DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT                                               0x7
+
+		HOST Impedance Divide Ratio
+		PSU_DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT                                               0xb
+
+		Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)
+		PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD                                            0xd
+
+		Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)
+		PSU_DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU                                            0xb
+
+		ZQ n Impedance Control Program Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0806A4, 0xFFFFFFFFU ,0x00087BDBU)  
+		RegMask = (DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK | DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK | DDR_PHY_ZQ1PR0_ZSEGBYP_MASK | DDR_PHY_ZQ1PR0_ZLE_MODE_MASK | DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK | DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK | DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK | DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT
+			| 0x00000001U << DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT
+			| 0x00000000U << DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT
+			| 0x00000007U << DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT
+			| 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT
+			| 0x0000000DU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT
+			| 0x0000000BU << DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_ZQ1PR0_OFFSET ,0xFFFFFFFFU ,0x00087BDBU);
+	/*############################################################################################################################ */
+
+		/*Register : DX0GCR0 @ 0XFD080700

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX0GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX0GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX0GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX0GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX0GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX0GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX0GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX0GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX0GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX0GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX0GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX0GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX0GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX0GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080700, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX0GCR0_CALBYP_MASK | DDR_PHY_DX0GCR0_MDLEN_MASK | DDR_PHY_DX0GCR0_CODTSHFT_MASK | DDR_PHY_DX0GCR0_DQSDCC_MASK | DDR_PHY_DX0GCR0_RDDLY_MASK | DDR_PHY_DX0GCR0_RESERVED_19_14_MASK | DDR_PHY_DX0GCR0_DQSNSEPDR_MASK | DDR_PHY_DX0GCR0_DQSSEPDR_MASK | DDR_PHY_DX0GCR0_RTTOAL_MASK | DDR_PHY_DX0GCR0_RTTOH_MASK | DDR_PHY_DX0GCR0_CPDRSHFT_MASK | DDR_PHY_DX0GCR0_DQSRPD_MASK | DDR_PHY_DX0GCR0_DQSGPDR_MASK | DDR_PHY_DX0GCR0_RESERVED_4_MASK | DDR_PHY_DX0GCR0_DQSGODT_MASK | DDR_PHY_DX0GCR0_DQSGOE_MASK | DDR_PHY_DX0GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX0GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX0GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX0GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX0GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX0GCR4 @ 0XFD080710

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX0GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX0GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX0GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX0GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX0GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX0GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX0GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX0GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX0GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX0GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080710, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX0GCR4_RESERVED_31_29_MASK | DDR_PHY_DX0GCR4_DXREFPEN_MASK | DDR_PHY_DX0GCR4_DXREFEEN_MASK | DDR_PHY_DX0GCR4_DXREFSEN_MASK | DDR_PHY_DX0GCR4_RESERVED_24_MASK | DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFESEL_MASK | DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX0GCR4_DXREFSSEL_MASK | DDR_PHY_DX0GCR4_RESERVED_7_6_MASK | DDR_PHY_DX0GCR4_DXREFIEN_MASK | DDR_PHY_DX0GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX0GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX0GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX0GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX0GCR5 @ 0XFD080714

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX0GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX0GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX0GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX0GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080714, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX0GCR5_RESERVED_31_MASK | DDR_PHY_DX0GCR5_DXREFISELR3_MASK | DDR_PHY_DX0GCR5_RESERVED_23_MASK | DDR_PHY_DX0GCR5_DXREFISELR2_MASK | DDR_PHY_DX0GCR5_RESERVED_15_MASK | DDR_PHY_DX0GCR5_DXREFISELR1_MASK | DDR_PHY_DX0GCR5_RESERVED_7_MASK | DDR_PHY_DX0GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX0GCR6 @ 0XFD080718

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX0GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX0GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX0GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX0GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX0GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080718, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX0GCR6_RESERVED_31_30_MASK | DDR_PHY_DX0GCR6_DXDQVREFR3_MASK | DDR_PHY_DX0GCR6_RESERVED_23_22_MASK | DDR_PHY_DX0GCR6_DXDQVREFR2_MASK | DDR_PHY_DX0GCR6_RESERVED_15_14_MASK | DDR_PHY_DX0GCR6_DXDQVREFR1_MASK | DDR_PHY_DX0GCR6_RESERVED_7_6_MASK | DDR_PHY_DX0GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX0LCDLR2 @ 0XFD080788

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX0LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX0LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080788, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX0LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX0LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX0GTR0 @ 0XFD0807C0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX0GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX0GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX0GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX0GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX0GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX0GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0807C0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX0GTR0_RESERVED_31_24_MASK | DDR_PHY_DX0GTR0_WDQSL_MASK | DDR_PHY_DX0GTR0_RESERVED_23_20_MASK | DDR_PHY_DX0GTR0_WLSL_MASK | DDR_PHY_DX0GTR0_RESERVED_15_13_MASK | DDR_PHY_DX0GTR0_RESERVED_12_8_MASK | DDR_PHY_DX0GTR0_RESERVED_7_5_MASK | DDR_PHY_DX0GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX0GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX0GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX0GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX1GCR0 @ 0XFD080800

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX1GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX1GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX1GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX1GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX1GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX1GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX1GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX1GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX1GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX1GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX1GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX1GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX1GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX1GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080800, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX1GCR0_CALBYP_MASK | DDR_PHY_DX1GCR0_MDLEN_MASK | DDR_PHY_DX1GCR0_CODTSHFT_MASK | DDR_PHY_DX1GCR0_DQSDCC_MASK | DDR_PHY_DX1GCR0_RDDLY_MASK | DDR_PHY_DX1GCR0_RESERVED_19_14_MASK | DDR_PHY_DX1GCR0_DQSNSEPDR_MASK | DDR_PHY_DX1GCR0_DQSSEPDR_MASK | DDR_PHY_DX1GCR0_RTTOAL_MASK | DDR_PHY_DX1GCR0_RTTOH_MASK | DDR_PHY_DX1GCR0_CPDRSHFT_MASK | DDR_PHY_DX1GCR0_DQSRPD_MASK | DDR_PHY_DX1GCR0_DQSGPDR_MASK | DDR_PHY_DX1GCR0_RESERVED_4_MASK | DDR_PHY_DX1GCR0_DQSGODT_MASK | DDR_PHY_DX1GCR0_DQSGOE_MASK | DDR_PHY_DX1GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX1GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX1GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX1GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX1GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX1GCR4 @ 0XFD080810

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX1GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX1GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX1GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX1GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX1GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX1GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX1GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX1GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX1GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX1GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080810, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX1GCR4_RESERVED_31_29_MASK | DDR_PHY_DX1GCR4_DXREFPEN_MASK | DDR_PHY_DX1GCR4_DXREFEEN_MASK | DDR_PHY_DX1GCR4_DXREFSEN_MASK | DDR_PHY_DX1GCR4_RESERVED_24_MASK | DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFESEL_MASK | DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX1GCR4_DXREFSSEL_MASK | DDR_PHY_DX1GCR4_RESERVED_7_6_MASK | DDR_PHY_DX1GCR4_DXREFIEN_MASK | DDR_PHY_DX1GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX1GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX1GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX1GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX1GCR5 @ 0XFD080814

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX1GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX1GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX1GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX1GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080814, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX1GCR5_RESERVED_31_MASK | DDR_PHY_DX1GCR5_DXREFISELR3_MASK | DDR_PHY_DX1GCR5_RESERVED_23_MASK | DDR_PHY_DX1GCR5_DXREFISELR2_MASK | DDR_PHY_DX1GCR5_RESERVED_15_MASK | DDR_PHY_DX1GCR5_DXREFISELR1_MASK | DDR_PHY_DX1GCR5_RESERVED_7_MASK | DDR_PHY_DX1GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX1GCR6 @ 0XFD080818

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX1GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX1GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX1GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX1GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX1GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080818, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX1GCR6_RESERVED_31_30_MASK | DDR_PHY_DX1GCR6_DXDQVREFR3_MASK | DDR_PHY_DX1GCR6_RESERVED_23_22_MASK | DDR_PHY_DX1GCR6_DXDQVREFR2_MASK | DDR_PHY_DX1GCR6_RESERVED_15_14_MASK | DDR_PHY_DX1GCR6_DXDQVREFR1_MASK | DDR_PHY_DX1GCR6_RESERVED_7_6_MASK | DDR_PHY_DX1GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX1LCDLR2 @ 0XFD080888

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX1LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX1LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080888, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX1LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX1LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX1GTR0 @ 0XFD0808C0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX1GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX1GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX1GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX1GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX1GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX1GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0808C0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX1GTR0_RESERVED_31_24_MASK | DDR_PHY_DX1GTR0_WDQSL_MASK | DDR_PHY_DX1GTR0_RESERVED_23_20_MASK | DDR_PHY_DX1GTR0_WLSL_MASK | DDR_PHY_DX1GTR0_RESERVED_15_13_MASK | DDR_PHY_DX1GTR0_RESERVED_12_8_MASK | DDR_PHY_DX1GTR0_RESERVED_7_5_MASK | DDR_PHY_DX1GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX1GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX1GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX1GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GCR0 @ 0XFD080900

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX2GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX2GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX2GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX2GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX2GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX2GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX2GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX2GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX2GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX2GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX2GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX2GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX2GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX2GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080900, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX2GCR0_CALBYP_MASK | DDR_PHY_DX2GCR0_MDLEN_MASK | DDR_PHY_DX2GCR0_CODTSHFT_MASK | DDR_PHY_DX2GCR0_DQSDCC_MASK | DDR_PHY_DX2GCR0_RDDLY_MASK | DDR_PHY_DX2GCR0_RESERVED_19_14_MASK | DDR_PHY_DX2GCR0_DQSNSEPDR_MASK | DDR_PHY_DX2GCR0_DQSSEPDR_MASK | DDR_PHY_DX2GCR0_RTTOAL_MASK | DDR_PHY_DX2GCR0_RTTOH_MASK | DDR_PHY_DX2GCR0_CPDRSHFT_MASK | DDR_PHY_DX2GCR0_DQSRPD_MASK | DDR_PHY_DX2GCR0_DQSGPDR_MASK | DDR_PHY_DX2GCR0_RESERVED_4_MASK | DDR_PHY_DX2GCR0_DQSGODT_MASK | DDR_PHY_DX2GCR0_DQSGOE_MASK | DDR_PHY_DX2GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX2GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX2GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GCR1 @ 0XFD080904

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX2GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX2GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX2GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX2GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX2GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX2GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX2GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX2GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX2GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX2GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080904, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX2GCR1_DXPDRMODE_MASK | DDR_PHY_DX2GCR1_RESERVED_15_MASK | DDR_PHY_DX2GCR1_QSNSEL_MASK | DDR_PHY_DX2GCR1_QSSEL_MASK | DDR_PHY_DX2GCR1_OEEN_MASK | DDR_PHY_DX2GCR1_PDREN_MASK | DDR_PHY_DX2GCR1_TEEN_MASK | DDR_PHY_DX2GCR1_DSEN_MASK | DDR_PHY_DX2GCR1_DMEN_MASK | DDR_PHY_DX2GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX2GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GCR4 @ 0XFD080910

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX2GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX2GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX2GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX2GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX2GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX2GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX2GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX2GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX2GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX2GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080910, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX2GCR4_RESERVED_31_29_MASK | DDR_PHY_DX2GCR4_DXREFPEN_MASK | DDR_PHY_DX2GCR4_DXREFEEN_MASK | DDR_PHY_DX2GCR4_DXREFSEN_MASK | DDR_PHY_DX2GCR4_RESERVED_24_MASK | DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFESEL_MASK | DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX2GCR4_DXREFSSEL_MASK | DDR_PHY_DX2GCR4_RESERVED_7_6_MASK | DDR_PHY_DX2GCR4_DXREFIEN_MASK | DDR_PHY_DX2GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX2GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX2GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GCR5 @ 0XFD080914

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX2GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX2GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX2GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX2GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080914, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX2GCR5_RESERVED_31_MASK | DDR_PHY_DX2GCR5_DXREFISELR3_MASK | DDR_PHY_DX2GCR5_RESERVED_23_MASK | DDR_PHY_DX2GCR5_DXREFISELR2_MASK | DDR_PHY_DX2GCR5_RESERVED_15_MASK | DDR_PHY_DX2GCR5_DXREFISELR1_MASK | DDR_PHY_DX2GCR5_RESERVED_7_MASK | DDR_PHY_DX2GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GCR6 @ 0XFD080918

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX2GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX2GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX2GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX2GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX2GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080918, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX2GCR6_RESERVED_31_30_MASK | DDR_PHY_DX2GCR6_DXDQVREFR3_MASK | DDR_PHY_DX2GCR6_RESERVED_23_22_MASK | DDR_PHY_DX2GCR6_DXDQVREFR2_MASK | DDR_PHY_DX2GCR6_RESERVED_15_14_MASK | DDR_PHY_DX2GCR6_DXDQVREFR1_MASK | DDR_PHY_DX2GCR6_RESERVED_7_6_MASK | DDR_PHY_DX2GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX2LCDLR2 @ 0XFD080988

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX2LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX2LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080988, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX2LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX2LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX2GTR0 @ 0XFD0809C0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX2GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX2GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX2GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX2GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX2GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX2GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD0809C0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX2GTR0_RESERVED_31_24_MASK | DDR_PHY_DX2GTR0_WDQSL_MASK | DDR_PHY_DX2GTR0_RESERVED_23_20_MASK | DDR_PHY_DX2GTR0_WLSL_MASK | DDR_PHY_DX2GTR0_RESERVED_15_13_MASK | DDR_PHY_DX2GTR0_RESERVED_12_8_MASK | DDR_PHY_DX2GTR0_RESERVED_7_5_MASK | DDR_PHY_DX2GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX2GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX2GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX2GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GCR0 @ 0XFD080A00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX3GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX3GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX3GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX3GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX3GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX3GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX3GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX3GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX3GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX3GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX3GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX3GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX3GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX3GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080A00, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX3GCR0_CALBYP_MASK | DDR_PHY_DX3GCR0_MDLEN_MASK | DDR_PHY_DX3GCR0_CODTSHFT_MASK | DDR_PHY_DX3GCR0_DQSDCC_MASK | DDR_PHY_DX3GCR0_RDDLY_MASK | DDR_PHY_DX3GCR0_RESERVED_19_14_MASK | DDR_PHY_DX3GCR0_DQSNSEPDR_MASK | DDR_PHY_DX3GCR0_DQSSEPDR_MASK | DDR_PHY_DX3GCR0_RTTOAL_MASK | DDR_PHY_DX3GCR0_RTTOH_MASK | DDR_PHY_DX3GCR0_CPDRSHFT_MASK | DDR_PHY_DX3GCR0_DQSRPD_MASK | DDR_PHY_DX3GCR0_DQSGPDR_MASK | DDR_PHY_DX3GCR0_RESERVED_4_MASK | DDR_PHY_DX3GCR0_DQSGODT_MASK | DDR_PHY_DX3GCR0_DQSGOE_MASK | DDR_PHY_DX3GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX3GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX3GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GCR1 @ 0XFD080A04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX3GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX3GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX3GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX3GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX3GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX3GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX3GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX3GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX3GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX3GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080A04, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX3GCR1_DXPDRMODE_MASK | DDR_PHY_DX3GCR1_RESERVED_15_MASK | DDR_PHY_DX3GCR1_QSNSEL_MASK | DDR_PHY_DX3GCR1_QSSEL_MASK | DDR_PHY_DX3GCR1_OEEN_MASK | DDR_PHY_DX3GCR1_PDREN_MASK | DDR_PHY_DX3GCR1_TEEN_MASK | DDR_PHY_DX3GCR1_DSEN_MASK | DDR_PHY_DX3GCR1_DMEN_MASK | DDR_PHY_DX3GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX3GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GCR4 @ 0XFD080A10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX3GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX3GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX3GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX3GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX3GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX3GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX3GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX3GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX3GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX3GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080A10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX3GCR4_RESERVED_31_29_MASK | DDR_PHY_DX3GCR4_DXREFPEN_MASK | DDR_PHY_DX3GCR4_DXREFEEN_MASK | DDR_PHY_DX3GCR4_DXREFSEN_MASK | DDR_PHY_DX3GCR4_RESERVED_24_MASK | DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFESEL_MASK | DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX3GCR4_DXREFSSEL_MASK | DDR_PHY_DX3GCR4_RESERVED_7_6_MASK | DDR_PHY_DX3GCR4_DXREFIEN_MASK | DDR_PHY_DX3GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX3GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX3GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GCR5 @ 0XFD080A14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX3GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX3GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX3GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX3GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080A14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX3GCR5_RESERVED_31_MASK | DDR_PHY_DX3GCR5_DXREFISELR3_MASK | DDR_PHY_DX3GCR5_RESERVED_23_MASK | DDR_PHY_DX3GCR5_DXREFISELR2_MASK | DDR_PHY_DX3GCR5_RESERVED_15_MASK | DDR_PHY_DX3GCR5_DXREFISELR1_MASK | DDR_PHY_DX3GCR5_RESERVED_7_MASK | DDR_PHY_DX3GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GCR6 @ 0XFD080A18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX3GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX3GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX3GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX3GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX3GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080A18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX3GCR6_RESERVED_31_30_MASK | DDR_PHY_DX3GCR6_DXDQVREFR3_MASK | DDR_PHY_DX3GCR6_RESERVED_23_22_MASK | DDR_PHY_DX3GCR6_DXDQVREFR2_MASK | DDR_PHY_DX3GCR6_RESERVED_15_14_MASK | DDR_PHY_DX3GCR6_DXDQVREFR1_MASK | DDR_PHY_DX3GCR6_RESERVED_7_6_MASK | DDR_PHY_DX3GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX3LCDLR2 @ 0XFD080A88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX3LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX3LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080A88, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX3LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX3LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX3GTR0 @ 0XFD080AC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX3GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX3GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX3GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX3GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX3GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX3GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080AC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX3GTR0_RESERVED_31_24_MASK | DDR_PHY_DX3GTR0_WDQSL_MASK | DDR_PHY_DX3GTR0_RESERVED_23_20_MASK | DDR_PHY_DX3GTR0_WLSL_MASK | DDR_PHY_DX3GTR0_RESERVED_15_13_MASK | DDR_PHY_DX3GTR0_RESERVED_12_8_MASK | DDR_PHY_DX3GTR0_RESERVED_7_5_MASK | DDR_PHY_DX3GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX3GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX3GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX3GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GCR0 @ 0XFD080B00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX4GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX4GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX4GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX4GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX4GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX4GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX4GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX4GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX4GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX4GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX4GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX4GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX4GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX4GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080B00, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX4GCR0_CALBYP_MASK | DDR_PHY_DX4GCR0_MDLEN_MASK | DDR_PHY_DX4GCR0_CODTSHFT_MASK | DDR_PHY_DX4GCR0_DQSDCC_MASK | DDR_PHY_DX4GCR0_RDDLY_MASK | DDR_PHY_DX4GCR0_RESERVED_19_14_MASK | DDR_PHY_DX4GCR0_DQSNSEPDR_MASK | DDR_PHY_DX4GCR0_DQSSEPDR_MASK | DDR_PHY_DX4GCR0_RTTOAL_MASK | DDR_PHY_DX4GCR0_RTTOH_MASK | DDR_PHY_DX4GCR0_CPDRSHFT_MASK | DDR_PHY_DX4GCR0_DQSRPD_MASK | DDR_PHY_DX4GCR0_DQSGPDR_MASK | DDR_PHY_DX4GCR0_RESERVED_4_MASK | DDR_PHY_DX4GCR0_DQSGODT_MASK | DDR_PHY_DX4GCR0_DQSGOE_MASK | DDR_PHY_DX4GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX4GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX4GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GCR1 @ 0XFD080B04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX4GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX4GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX4GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX4GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX4GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX4GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX4GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX4GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX4GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX4GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080B04, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX4GCR1_DXPDRMODE_MASK | DDR_PHY_DX4GCR1_RESERVED_15_MASK | DDR_PHY_DX4GCR1_QSNSEL_MASK | DDR_PHY_DX4GCR1_QSSEL_MASK | DDR_PHY_DX4GCR1_OEEN_MASK | DDR_PHY_DX4GCR1_PDREN_MASK | DDR_PHY_DX4GCR1_TEEN_MASK | DDR_PHY_DX4GCR1_DSEN_MASK | DDR_PHY_DX4GCR1_DMEN_MASK | DDR_PHY_DX4GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX4GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GCR4 @ 0XFD080B10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX4GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX4GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX4GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX4GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX4GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX4GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX4GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX4GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX4GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX4GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080B10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX4GCR4_RESERVED_31_29_MASK | DDR_PHY_DX4GCR4_DXREFPEN_MASK | DDR_PHY_DX4GCR4_DXREFEEN_MASK | DDR_PHY_DX4GCR4_DXREFSEN_MASK | DDR_PHY_DX4GCR4_RESERVED_24_MASK | DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFESEL_MASK | DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX4GCR4_DXREFSSEL_MASK | DDR_PHY_DX4GCR4_RESERVED_7_6_MASK | DDR_PHY_DX4GCR4_DXREFIEN_MASK | DDR_PHY_DX4GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX4GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX4GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GCR5 @ 0XFD080B14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX4GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX4GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX4GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX4GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080B14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX4GCR5_RESERVED_31_MASK | DDR_PHY_DX4GCR5_DXREFISELR3_MASK | DDR_PHY_DX4GCR5_RESERVED_23_MASK | DDR_PHY_DX4GCR5_DXREFISELR2_MASK | DDR_PHY_DX4GCR5_RESERVED_15_MASK | DDR_PHY_DX4GCR5_DXREFISELR1_MASK | DDR_PHY_DX4GCR5_RESERVED_7_MASK | DDR_PHY_DX4GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GCR6 @ 0XFD080B18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX4GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX4GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX4GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX4GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX4GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080B18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX4GCR6_RESERVED_31_30_MASK | DDR_PHY_DX4GCR6_DXDQVREFR3_MASK | DDR_PHY_DX4GCR6_RESERVED_23_22_MASK | DDR_PHY_DX4GCR6_DXDQVREFR2_MASK | DDR_PHY_DX4GCR6_RESERVED_15_14_MASK | DDR_PHY_DX4GCR6_DXDQVREFR1_MASK | DDR_PHY_DX4GCR6_RESERVED_7_6_MASK | DDR_PHY_DX4GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX4LCDLR2 @ 0XFD080B88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX4LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX4LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080B88, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX4LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX4LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX4GTR0 @ 0XFD080BC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX4GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX4GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX4GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX4GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX4GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX4GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080BC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX4GTR0_RESERVED_31_24_MASK | DDR_PHY_DX4GTR0_WDQSL_MASK | DDR_PHY_DX4GTR0_RESERVED_23_20_MASK | DDR_PHY_DX4GTR0_WLSL_MASK | DDR_PHY_DX4GTR0_RESERVED_15_13_MASK | DDR_PHY_DX4GTR0_RESERVED_12_8_MASK | DDR_PHY_DX4GTR0_RESERVED_7_5_MASK | DDR_PHY_DX4GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX4GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX4GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX4GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GCR0 @ 0XFD080C00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX5GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX5GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX5GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX5GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX5GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX5GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX5GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX5GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX5GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX5GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX5GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX5GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX5GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX5GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080C00, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX5GCR0_CALBYP_MASK | DDR_PHY_DX5GCR0_MDLEN_MASK | DDR_PHY_DX5GCR0_CODTSHFT_MASK | DDR_PHY_DX5GCR0_DQSDCC_MASK | DDR_PHY_DX5GCR0_RDDLY_MASK | DDR_PHY_DX5GCR0_RESERVED_19_14_MASK | DDR_PHY_DX5GCR0_DQSNSEPDR_MASK | DDR_PHY_DX5GCR0_DQSSEPDR_MASK | DDR_PHY_DX5GCR0_RTTOAL_MASK | DDR_PHY_DX5GCR0_RTTOH_MASK | DDR_PHY_DX5GCR0_CPDRSHFT_MASK | DDR_PHY_DX5GCR0_DQSRPD_MASK | DDR_PHY_DX5GCR0_DQSGPDR_MASK | DDR_PHY_DX5GCR0_RESERVED_4_MASK | DDR_PHY_DX5GCR0_DQSGODT_MASK | DDR_PHY_DX5GCR0_DQSGOE_MASK | DDR_PHY_DX5GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX5GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX5GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GCR1 @ 0XFD080C04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX5GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX5GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX5GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX5GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX5GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX5GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX5GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX5GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX5GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX5GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080C04, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX5GCR1_DXPDRMODE_MASK | DDR_PHY_DX5GCR1_RESERVED_15_MASK | DDR_PHY_DX5GCR1_QSNSEL_MASK | DDR_PHY_DX5GCR1_QSSEL_MASK | DDR_PHY_DX5GCR1_OEEN_MASK | DDR_PHY_DX5GCR1_PDREN_MASK | DDR_PHY_DX5GCR1_TEEN_MASK | DDR_PHY_DX5GCR1_DSEN_MASK | DDR_PHY_DX5GCR1_DMEN_MASK | DDR_PHY_DX5GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX5GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GCR4 @ 0XFD080C10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX5GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX5GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX5GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX5GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX5GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX5GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX5GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX5GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX5GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX5GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080C10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX5GCR4_RESERVED_31_29_MASK | DDR_PHY_DX5GCR4_DXREFPEN_MASK | DDR_PHY_DX5GCR4_DXREFEEN_MASK | DDR_PHY_DX5GCR4_DXREFSEN_MASK | DDR_PHY_DX5GCR4_RESERVED_24_MASK | DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFESEL_MASK | DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX5GCR4_DXREFSSEL_MASK | DDR_PHY_DX5GCR4_RESERVED_7_6_MASK | DDR_PHY_DX5GCR4_DXREFIEN_MASK | DDR_PHY_DX5GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX5GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX5GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GCR5 @ 0XFD080C14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX5GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX5GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX5GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX5GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080C14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX5GCR5_RESERVED_31_MASK | DDR_PHY_DX5GCR5_DXREFISELR3_MASK | DDR_PHY_DX5GCR5_RESERVED_23_MASK | DDR_PHY_DX5GCR5_DXREFISELR2_MASK | DDR_PHY_DX5GCR5_RESERVED_15_MASK | DDR_PHY_DX5GCR5_DXREFISELR1_MASK | DDR_PHY_DX5GCR5_RESERVED_7_MASK | DDR_PHY_DX5GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GCR6 @ 0XFD080C18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX5GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX5GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX5GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX5GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX5GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080C18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX5GCR6_RESERVED_31_30_MASK | DDR_PHY_DX5GCR6_DXDQVREFR3_MASK | DDR_PHY_DX5GCR6_RESERVED_23_22_MASK | DDR_PHY_DX5GCR6_DXDQVREFR2_MASK | DDR_PHY_DX5GCR6_RESERVED_15_14_MASK | DDR_PHY_DX5GCR6_DXDQVREFR1_MASK | DDR_PHY_DX5GCR6_RESERVED_7_6_MASK | DDR_PHY_DX5GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX5LCDLR2 @ 0XFD080C88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX5LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX5LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080C88, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX5LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX5LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX5GTR0 @ 0XFD080CC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX5GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX5GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX5GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX5GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX5GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX5GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080CC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX5GTR0_RESERVED_31_24_MASK | DDR_PHY_DX5GTR0_WDQSL_MASK | DDR_PHY_DX5GTR0_RESERVED_23_20_MASK | DDR_PHY_DX5GTR0_WLSL_MASK | DDR_PHY_DX5GTR0_RESERVED_15_13_MASK | DDR_PHY_DX5GTR0_RESERVED_12_8_MASK | DDR_PHY_DX5GTR0_RESERVED_7_5_MASK | DDR_PHY_DX5GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX5GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX5GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX5GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GCR0 @ 0XFD080D00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX6GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX6GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX6GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX6GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX6GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX6GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX6GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX6GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX6GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX6GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX6GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX6GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX6GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX6GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080D00, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX6GCR0_CALBYP_MASK | DDR_PHY_DX6GCR0_MDLEN_MASK | DDR_PHY_DX6GCR0_CODTSHFT_MASK | DDR_PHY_DX6GCR0_DQSDCC_MASK | DDR_PHY_DX6GCR0_RDDLY_MASK | DDR_PHY_DX6GCR0_RESERVED_19_14_MASK | DDR_PHY_DX6GCR0_DQSNSEPDR_MASK | DDR_PHY_DX6GCR0_DQSSEPDR_MASK | DDR_PHY_DX6GCR0_RTTOAL_MASK | DDR_PHY_DX6GCR0_RTTOH_MASK | DDR_PHY_DX6GCR0_CPDRSHFT_MASK | DDR_PHY_DX6GCR0_DQSRPD_MASK | DDR_PHY_DX6GCR0_DQSGPDR_MASK | DDR_PHY_DX6GCR0_RESERVED_4_MASK | DDR_PHY_DX6GCR0_DQSGODT_MASK | DDR_PHY_DX6GCR0_DQSGOE_MASK | DDR_PHY_DX6GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX6GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX6GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GCR1 @ 0XFD080D04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX6GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX6GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX6GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX6GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX6GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX6GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX6GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX6GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX6GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX6GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080D04, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX6GCR1_DXPDRMODE_MASK | DDR_PHY_DX6GCR1_RESERVED_15_MASK | DDR_PHY_DX6GCR1_QSNSEL_MASK | DDR_PHY_DX6GCR1_QSSEL_MASK | DDR_PHY_DX6GCR1_OEEN_MASK | DDR_PHY_DX6GCR1_PDREN_MASK | DDR_PHY_DX6GCR1_TEEN_MASK | DDR_PHY_DX6GCR1_DSEN_MASK | DDR_PHY_DX6GCR1_DMEN_MASK | DDR_PHY_DX6GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX6GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GCR4 @ 0XFD080D10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX6GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX6GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX6GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX6GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX6GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX6GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX6GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX6GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX6GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX6GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080D10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX6GCR4_RESERVED_31_29_MASK | DDR_PHY_DX6GCR4_DXREFPEN_MASK | DDR_PHY_DX6GCR4_DXREFEEN_MASK | DDR_PHY_DX6GCR4_DXREFSEN_MASK | DDR_PHY_DX6GCR4_RESERVED_24_MASK | DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFESEL_MASK | DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX6GCR4_DXREFSSEL_MASK | DDR_PHY_DX6GCR4_RESERVED_7_6_MASK | DDR_PHY_DX6GCR4_DXREFIEN_MASK | DDR_PHY_DX6GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX6GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX6GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GCR5 @ 0XFD080D14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX6GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX6GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX6GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX6GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080D14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX6GCR5_RESERVED_31_MASK | DDR_PHY_DX6GCR5_DXREFISELR3_MASK | DDR_PHY_DX6GCR5_RESERVED_23_MASK | DDR_PHY_DX6GCR5_DXREFISELR2_MASK | DDR_PHY_DX6GCR5_RESERVED_15_MASK | DDR_PHY_DX6GCR5_DXREFISELR1_MASK | DDR_PHY_DX6GCR5_RESERVED_7_MASK | DDR_PHY_DX6GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GCR6 @ 0XFD080D18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX6GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX6GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX6GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX6GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX6GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080D18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX6GCR6_RESERVED_31_30_MASK | DDR_PHY_DX6GCR6_DXDQVREFR3_MASK | DDR_PHY_DX6GCR6_RESERVED_23_22_MASK | DDR_PHY_DX6GCR6_DXDQVREFR2_MASK | DDR_PHY_DX6GCR6_RESERVED_15_14_MASK | DDR_PHY_DX6GCR6_DXDQVREFR1_MASK | DDR_PHY_DX6GCR6_RESERVED_7_6_MASK | DDR_PHY_DX6GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX6LCDLR2 @ 0XFD080D88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX6LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX6LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080D88, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX6LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX6LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX6GTR0 @ 0XFD080DC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX6GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX6GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX6GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX6GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX6GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX6GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080DC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX6GTR0_RESERVED_31_24_MASK | DDR_PHY_DX6GTR0_WDQSL_MASK | DDR_PHY_DX6GTR0_RESERVED_23_20_MASK | DDR_PHY_DX6GTR0_WLSL_MASK | DDR_PHY_DX6GTR0_RESERVED_15_13_MASK | DDR_PHY_DX6GTR0_RESERVED_12_8_MASK | DDR_PHY_DX6GTR0_RESERVED_7_5_MASK | DDR_PHY_DX6GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX6GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX6GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX6GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GCR0 @ 0XFD080E00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX7GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX7GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX7GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX7GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX7GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX7GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX7GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX7GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX7GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX7GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX7GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX7GCR0_DQSGPDR                                                     0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX7GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX7GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080E00, 0xFFFFFFFFU ,0x40800604U)  
+		RegMask = (DDR_PHY_DX7GCR0_CALBYP_MASK | DDR_PHY_DX7GCR0_MDLEN_MASK | DDR_PHY_DX7GCR0_CODTSHFT_MASK | DDR_PHY_DX7GCR0_DQSDCC_MASK | DDR_PHY_DX7GCR0_RDDLY_MASK | DDR_PHY_DX7GCR0_RESERVED_19_14_MASK | DDR_PHY_DX7GCR0_DQSNSEPDR_MASK | DDR_PHY_DX7GCR0_DQSSEPDR_MASK | DDR_PHY_DX7GCR0_RTTOAL_MASK | DDR_PHY_DX7GCR0_RTTOH_MASK | DDR_PHY_DX7GCR0_CPDRSHFT_MASK | DDR_PHY_DX7GCR0_DQSRPD_MASK | DDR_PHY_DX7GCR0_DQSGPDR_MASK | DDR_PHY_DX7GCR0_RESERVED_4_MASK | DDR_PHY_DX7GCR0_DQSGODT_MASK | DDR_PHY_DX7GCR0_DQSGOE_MASK | DDR_PHY_DX7GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX7GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX7GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSRPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GCR0_OFFSET ,0xFFFFFFFFU ,0x40800604U);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GCR1 @ 0XFD080E04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX7GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX7GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX7GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX7GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX7GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX7GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX7GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX7GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX7GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX7GCR1_DQEN                                                        0xff
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080E04, 0xFFFFFFFFU ,0x00007FFFU)  
+		RegMask = (DDR_PHY_DX7GCR1_DXPDRMODE_MASK | DDR_PHY_DX7GCR1_RESERVED_15_MASK | DDR_PHY_DX7GCR1_QSNSEL_MASK | DDR_PHY_DX7GCR1_QSSEL_MASK | DDR_PHY_DX7GCR1_OEEN_MASK | DDR_PHY_DX7GCR1_PDREN_MASK | DDR_PHY_DX7GCR1_TEEN_MASK | DDR_PHY_DX7GCR1_DSEN_MASK | DDR_PHY_DX7GCR1_DMEN_MASK | DDR_PHY_DX7GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR1_DMEN_SHIFT
+			| 0x000000FFU << DDR_PHY_DX7GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GCR1_OFFSET ,0xFFFFFFFFU ,0x00007FFFU);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GCR4 @ 0XFD080E10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX7GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX7GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX7GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX7GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX7GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX7GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX7GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX7GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX7GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX7GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080E10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX7GCR4_RESERVED_31_29_MASK | DDR_PHY_DX7GCR4_DXREFPEN_MASK | DDR_PHY_DX7GCR4_DXREFEEN_MASK | DDR_PHY_DX7GCR4_DXREFSEN_MASK | DDR_PHY_DX7GCR4_RESERVED_24_MASK | DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFESEL_MASK | DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX7GCR4_DXREFSSEL_MASK | DDR_PHY_DX7GCR4_RESERVED_7_6_MASK | DDR_PHY_DX7GCR4_DXREFIEN_MASK | DDR_PHY_DX7GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX7GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX7GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GCR5 @ 0XFD080E14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX7GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX7GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX7GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX7GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080E14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX7GCR5_RESERVED_31_MASK | DDR_PHY_DX7GCR5_DXREFISELR3_MASK | DDR_PHY_DX7GCR5_RESERVED_23_MASK | DDR_PHY_DX7GCR5_DXREFISELR2_MASK | DDR_PHY_DX7GCR5_RESERVED_15_MASK | DDR_PHY_DX7GCR5_DXREFISELR1_MASK | DDR_PHY_DX7GCR5_RESERVED_7_MASK | DDR_PHY_DX7GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GCR6 @ 0XFD080E18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX7GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX7GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX7GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX7GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX7GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080E18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX7GCR6_RESERVED_31_30_MASK | DDR_PHY_DX7GCR6_DXDQVREFR3_MASK | DDR_PHY_DX7GCR6_RESERVED_23_22_MASK | DDR_PHY_DX7GCR6_DXDQVREFR2_MASK | DDR_PHY_DX7GCR6_RESERVED_15_14_MASK | DDR_PHY_DX7GCR6_DXDQVREFR1_MASK | DDR_PHY_DX7GCR6_RESERVED_7_6_MASK | DDR_PHY_DX7GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX7LCDLR2 @ 0XFD080E88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX7LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX7LCDLR2_DQSGD                                                     0xa
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080E88, 0xFFFFFFFFU ,0x0000000AU)  
+		RegMask = (DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX7LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT
+			| 0x0000000AU << DDR_PHY_DX7LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7LCDLR2_OFFSET ,0xFFFFFFFFU ,0x0000000AU);
+	/*############################################################################################################################ */
+
+		/*Register : DX7GTR0 @ 0XFD080EC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX7GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX7GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX7GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX7GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX7GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX7GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080EC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX7GTR0_RESERVED_31_24_MASK | DDR_PHY_DX7GTR0_WDQSL_MASK | DDR_PHY_DX7GTR0_RESERVED_23_20_MASK | DDR_PHY_DX7GTR0_WLSL_MASK | DDR_PHY_DX7GTR0_RESERVED_15_13_MASK | DDR_PHY_DX7GTR0_RESERVED_12_8_MASK | DDR_PHY_DX7GTR0_RESERVED_7_5_MASK | DDR_PHY_DX7GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX7GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX7GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX7GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GCR0 @ 0XFD080F00

+
+		Calibration Bypass
+		PSU_DDR_PHY_DX8GCR0_CALBYP                                                      0x0
+
+		Master Delay Line Enable
+		PSU_DDR_PHY_DX8GCR0_MDLEN                                                       0x1
+
+		Configurable ODT(TE) Phase Shift
+		PSU_DDR_PHY_DX8GCR0_CODTSHFT                                                    0x0
+
+		DQS Duty Cycle Correction
+		PSU_DDR_PHY_DX8GCR0_DQSDCC                                                      0x0
+
+		Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY
+		PSU_DDR_PHY_DX8GCR0_RDDLY                                                       0x8
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GCR0_RESERVED_19_14                                              0x0
+
+		DQSNSE Power Down Receiver
+		PSU_DDR_PHY_DX8GCR0_DQSNSEPDR                                                   0x0
+
+		DQSSE Power Down Receiver
+		PSU_DDR_PHY_DX8GCR0_DQSSEPDR                                                    0x0
+
+		RTT On Additive Latency
+		PSU_DDR_PHY_DX8GCR0_RTTOAL                                                      0x0
+
+		RTT Output Hold
+		PSU_DDR_PHY_DX8GCR0_RTTOH                                                       0x3
+
+		Configurable PDR Phase Shift
+		PSU_DDR_PHY_DX8GCR0_CPDRSHFT                                                    0x0
+
+		DQSR Power Down
+		PSU_DDR_PHY_DX8GCR0_DQSRPD                                                      0x0
+
+		DQSG Power Down Receiver
+		PSU_DDR_PHY_DX8GCR0_DQSGPDR                                                     0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GCR0_RESERVED_4                                                  0x0
+
+		DQSG On-Die Termination
+		PSU_DDR_PHY_DX8GCR0_DQSGODT                                                     0x0
+
+		DQSG Output Enable
+		PSU_DDR_PHY_DX8GCR0_DQSGOE                                                      0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GCR0_RESERVED_1_0                                                0x0
+
+		DATX8 n General Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080F00, 0xFFFFFFFFU ,0x40800624U)  
+		RegMask = (DDR_PHY_DX8GCR0_CALBYP_MASK | DDR_PHY_DX8GCR0_MDLEN_MASK | DDR_PHY_DX8GCR0_CODTSHFT_MASK | DDR_PHY_DX8GCR0_DQSDCC_MASK | DDR_PHY_DX8GCR0_RDDLY_MASK | DDR_PHY_DX8GCR0_RESERVED_19_14_MASK | DDR_PHY_DX8GCR0_DQSNSEPDR_MASK | DDR_PHY_DX8GCR0_DQSSEPDR_MASK | DDR_PHY_DX8GCR0_RTTOAL_MASK | DDR_PHY_DX8GCR0_RTTOH_MASK | DDR_PHY_DX8GCR0_CPDRSHFT_MASK | DDR_PHY_DX8GCR0_DQSRPD_MASK | DDR_PHY_DX8GCR0_DQSGPDR_MASK | DDR_PHY_DX8GCR0_RESERVED_4_MASK | DDR_PHY_DX8GCR0_DQSGODT_MASK | DDR_PHY_DX8GCR0_DQSGOE_MASK | DDR_PHY_DX8GCR0_RESERVED_1_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GCR0_CALBYP_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR0_MDLEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_CODTSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_DQSDCC_SHIFT
+			| 0x00000008U << DDR_PHY_DX8GCR0_RDDLY_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_RTTOAL_SHIFT
+			| 0x00000003U << DDR_PHY_DX8GCR0_RTTOH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_DQSRPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR0_DQSGPDR_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_4_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_DQSGODT_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR0_DQSGOE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GCR0_OFFSET ,0xFFFFFFFFU ,0x40800624U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GCR1 @ 0XFD080F04

+
+		Enables the PDR mode for DQ[7:0]
+		PSU_DDR_PHY_DX8GCR1_DXPDRMODE                                                   0x0
+
+		Reserved. Returns zeroes on reads.
+		PSU_DDR_PHY_DX8GCR1_RESERVED_15                                                 0x0
+
+		Select the delayed or non-delayed read data strobe #
+		PSU_DDR_PHY_DX8GCR1_QSNSEL                                                      0x1
+
+		Select the delayed or non-delayed read data strobe
+		PSU_DDR_PHY_DX8GCR1_QSSEL                                                       0x1
+
+		Enables Read Data Strobe in a byte lane
+		PSU_DDR_PHY_DX8GCR1_OEEN                                                        0x1
+
+		Enables PDR in a byte lane
+		PSU_DDR_PHY_DX8GCR1_PDREN                                                       0x1
+
+		Enables ODT/TE in a byte lane
+		PSU_DDR_PHY_DX8GCR1_TEEN                                                        0x1
+
+		Enables Write Data strobe in a byte lane
+		PSU_DDR_PHY_DX8GCR1_DSEN                                                        0x1
+
+		Enables DM pin in a byte lane
+		PSU_DDR_PHY_DX8GCR1_DMEN                                                        0x1
+
+		Enables DQ corresponding to each bit in a byte
+		PSU_DDR_PHY_DX8GCR1_DQEN                                                        0x0
+
+		DATX8 n General Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD080F04, 0xFFFFFFFFU ,0x00007F00U)  
+		RegMask = (DDR_PHY_DX8GCR1_DXPDRMODE_MASK | DDR_PHY_DX8GCR1_RESERVED_15_MASK | DDR_PHY_DX8GCR1_QSNSEL_MASK | DDR_PHY_DX8GCR1_QSSEL_MASK | DDR_PHY_DX8GCR1_OEEN_MASK | DDR_PHY_DX8GCR1_PDREN_MASK | DDR_PHY_DX8GCR1_TEEN_MASK | DDR_PHY_DX8GCR1_DSEN_MASK | DDR_PHY_DX8GCR1_DMEN_MASK | DDR_PHY_DX8GCR1_DQEN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR1_RESERVED_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_QSNSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_QSSEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_OEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_PDREN_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_TEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_DSEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR1_DMEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR1_DQEN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GCR1_OFFSET ,0xFFFFFFFFU ,0x00007F00U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GCR4 @ 0XFD080F10

+
+		Byte lane VREF IOM (Used only by D4MU IOs)
+		PSU_DDR_PHY_DX8GCR4_RESERVED_31_29                                              0x0
+
+		Byte Lane VREF Pad Enable
+		PSU_DDR_PHY_DX8GCR4_DXREFPEN                                                    0x0
+
+		Byte Lane Internal VREF Enable
+		PSU_DDR_PHY_DX8GCR4_DXREFEEN                                                    0x3
+
+		Byte Lane Single-End VREF Enable
+		PSU_DDR_PHY_DX8GCR4_DXREFSEN                                                    0x1
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR4_RESERVED_24                                                 0x0
+
+		External VREF generator REFSEL range select
+		PSU_DDR_PHY_DX8GCR4_DXREFESELRANGE                                              0x0
+
+		Byte Lane External VREF Select
+		PSU_DDR_PHY_DX8GCR4_DXREFESEL                                                   0x0
+
+		Single ended VREF generator REFSEL range select
+		PSU_DDR_PHY_DX8GCR4_DXREFSSELRANGE                                              0x1
+
+		Byte Lane Single-End VREF Select
+		PSU_DDR_PHY_DX8GCR4_DXREFSSEL                                                   0x30
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR4_RESERVED_7_6                                                0x0
+
+		VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX8GCR4_DXREFIEN                                                    0xf
+
+		VRMON control for DQ IO (Single Ended) buffers of a byte lane.
+		PSU_DDR_PHY_DX8GCR4_DXREFIMON                                                   0x0
+
+		DATX8 n General Configuration Register 4
+		(OFFSET, MASK, VALUE)      (0XFD080F10, 0xFFFFFFFFU ,0x0E00B03CU)  
+		RegMask = (DDR_PHY_DX8GCR4_RESERVED_31_29_MASK | DDR_PHY_DX8GCR4_DXREFPEN_MASK | DDR_PHY_DX8GCR4_DXREFEEN_MASK | DDR_PHY_DX8GCR4_DXREFSEN_MASK | DDR_PHY_DX8GCR4_RESERVED_24_MASK | DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFESEL_MASK | DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK | DDR_PHY_DX8GCR4_DXREFSSEL_MASK | DDR_PHY_DX8GCR4_RESERVED_7_6_MASK | DDR_PHY_DX8GCR4_DXREFIEN_MASK | DDR_PHY_DX8GCR4_DXREFIMON_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_DXREFPEN_SHIFT
+			| 0x00000003U << DDR_PHY_DX8GCR4_DXREFEEN_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR4_DXREFSEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_DXREFESEL_SHIFT
+			| 0x00000001U << DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT
+			| 0x00000030U << DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT
+			| 0x0000000FU << DDR_PHY_DX8GCR4_DXREFIEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR4_DXREFIMON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GCR4_OFFSET ,0xFFFFFFFFU ,0x0E00B03CU);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GCR5 @ 0XFD080F14

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR5_RESERVED_31                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 3
+		PSU_DDR_PHY_DX8GCR5_DXREFISELR3                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR5_RESERVED_23                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 2
+		PSU_DDR_PHY_DX8GCR5_DXREFISELR2                                                 0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR5_RESERVED_15                                                 0x0
+
+		Byte Lane internal VREF Select for Rank 1
+		PSU_DDR_PHY_DX8GCR5_DXREFISELR1                                                 0x55
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR5_RESERVED_7                                                  0x0
+
+		Byte Lane internal VREF Select for Rank 0
+		PSU_DDR_PHY_DX8GCR5_DXREFISELR0                                                 0x55
+
+		DATX8 n General Configuration Register 5
+		(OFFSET, MASK, VALUE)      (0XFD080F14, 0xFFFFFFFFU ,0x09095555U)  
+		RegMask = (DDR_PHY_DX8GCR5_RESERVED_31_MASK | DDR_PHY_DX8GCR5_DXREFISELR3_MASK | DDR_PHY_DX8GCR5_RESERVED_23_MASK | DDR_PHY_DX8GCR5_DXREFISELR2_MASK | DDR_PHY_DX8GCR5_RESERVED_15_MASK | DDR_PHY_DX8GCR5_DXREFISELR1_MASK | DDR_PHY_DX8GCR5_RESERVED_7_MASK | DDR_PHY_DX8GCR5_DXREFISELR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GCR5_RESERVED_31_SHIFT
+			| 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_23_SHIFT
+			| 0x00000009U << DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_15_SHIFT
+			| 0x00000055U << DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR5_RESERVED_7_SHIFT
+			| 0x00000055U << DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GCR5_OFFSET ,0xFFFFFFFFU ,0x09095555U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GCR6 @ 0XFD080F18

+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR6_RESERVED_31_30                                              0x0
+
+		DRAM DQ VREF Select for Rank3
+		PSU_DDR_PHY_DX8GCR6_DXDQVREFR3                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR6_RESERVED_23_22                                              0x0
+
+		DRAM DQ VREF Select for Rank2
+		PSU_DDR_PHY_DX8GCR6_DXDQVREFR2                                                  0x9
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR6_RESERVED_15_14                                              0x0
+
+		DRAM DQ VREF Select for Rank1
+		PSU_DDR_PHY_DX8GCR6_DXDQVREFR1                                                  0x2b
+
+		Reserved. Returns zeros on reads.
+		PSU_DDR_PHY_DX8GCR6_RESERVED_7_6                                                0x0
+
+		DRAM DQ VREF Select for Rank0
+		PSU_DDR_PHY_DX8GCR6_DXDQVREFR0                                                  0x2b
+
+		DATX8 n General Configuration Register 6
+		(OFFSET, MASK, VALUE)      (0XFD080F18, 0xFFFFFFFFU ,0x09092B2BU)  
+		RegMask = (DDR_PHY_DX8GCR6_RESERVED_31_30_MASK | DDR_PHY_DX8GCR6_DXDQVREFR3_MASK | DDR_PHY_DX8GCR6_RESERVED_23_22_MASK | DDR_PHY_DX8GCR6_DXDQVREFR2_MASK | DDR_PHY_DX8GCR6_RESERVED_15_14_MASK | DDR_PHY_DX8GCR6_DXDQVREFR1_MASK | DDR_PHY_DX8GCR6_RESERVED_7_6_MASK | DDR_PHY_DX8GCR6_DXDQVREFR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT
+			| 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT
+			| 0x00000009U << DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT
+			| 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT
+			| 0x0000002BU << DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GCR6_OFFSET ,0xFFFFFFFFU ,0x09092B2BU);
+	/*############################################################################################################################ */
+
+		/*Register : DX8LCDLR2 @ 0XFD080F88

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8LCDLR2_RESERVED_31_25                                            0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX8LCDLR2_RESERVED_24_16                                            0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8LCDLR2_RESERVED_15_9                                             0x0
+
+		Read DQS Gating Delay
+		PSU_DDR_PHY_DX8LCDLR2_DQSGD                                                     0x0
+
+		DATX8 n Local Calibrated Delay Line Register 2
+		(OFFSET, MASK, VALUE)      (0XFD080F88, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK | DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK | DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK | DDR_PHY_DX8LCDLR2_DQSGD_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT
+			| 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT
+			| 0x00000000U << DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT
+			| 0x00000000U << DDR_PHY_DX8LCDLR2_DQSGD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8LCDLR2_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8GTR0 @ 0XFD080FC0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GTR0_RESERVED_31_24                                              0x0
+
+		DQ Write Path Latency Pipeline
+		PSU_DDR_PHY_DX8GTR0_WDQSL                                                       0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX8GTR0_RESERVED_23_20                                              0x0
+
+		Write Leveling System Latency
+		PSU_DDR_PHY_DX8GTR0_WLSL                                                        0x2
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GTR0_RESERVED_15_13                                              0x0
+
+		Reserved. Caution, do not write to this register field.
+		PSU_DDR_PHY_DX8GTR0_RESERVED_12_8                                               0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8GTR0_RESERVED_7_5                                                0x0
+
+		DQS Gating System Latency
+		PSU_DDR_PHY_DX8GTR0_DGSL                                                        0x0
+
+		DATX8 n General Timing Register 0
+		(OFFSET, MASK, VALUE)      (0XFD080FC0, 0xFFFFFFFFU ,0x00020000U)  
+		RegMask = (DDR_PHY_DX8GTR0_RESERVED_31_24_MASK | DDR_PHY_DX8GTR0_WDQSL_MASK | DDR_PHY_DX8GTR0_RESERVED_23_20_MASK | DDR_PHY_DX8GTR0_WLSL_MASK | DDR_PHY_DX8GTR0_RESERVED_15_13_MASK | DDR_PHY_DX8GTR0_RESERVED_12_8_MASK | DDR_PHY_DX8GTR0_RESERVED_7_5_MASK | DDR_PHY_DX8GTR0_DGSL_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_WDQSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT
+			| 0x00000002U << DDR_PHY_DX8GTR0_WLSL_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT
+			| 0x00000000U << DDR_PHY_DX8GTR0_DGSL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8GTR0_OFFSET ,0xFFFFFFFFU ,0x00020000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL0DQSCTL @ 0XFD08141C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL0DQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL0DQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SL0DQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SL0DQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SL0DQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SL0DQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SL0DQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SL0DQSCTL_DXSR                                                   0x3
+
+		DQS_N Resistor
+		PSU_DDR_PHY_DX8SL0DQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SL0DQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-1 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD08141C, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL0DQSCTL_DXSR_MASK | DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL0DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL0DXCTL2 @ 0XFD08142C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24                                         0x0
+
+		Configurable Read Data Enable
+		PSU_DDR_PHY_DX8SL0DXCTL2_CRDEN                                                  0x0
+
+		OX Extension during Post-amble
+		PSU_DDR_PHY_DX8SL0DXCTL2_POSOEX                                                 0x0
+
+		OE Extension during Pre-amble
+		PSU_DDR_PHY_DX8SL0DXCTL2_PREOEX                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_17                                            0x0
+
+		I/O Assisted Gate Select
+		PSU_DDR_PHY_DX8SL0DXCTL2_IOAG                                                   0x0
+
+		I/O Loopback Select
+		PSU_DDR_PHY_DX8SL0DXCTL2_IOLB                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13                                         0x0
+
+		Low Power Wakeup Threshold
+		PSU_DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		Read Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL0DXCTL2_RDBI                                                   0x0
+
+		Write Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL0DXCTL2_WDBI                                                   0x0
+
+		PUB Read FIFO Bypass
+		PSU_DDR_PHY_DX8SL0DXCTL2_PRFBYP                                                 0x0
+
+		DATX8 Receive FIFO Read Mode
+		PSU_DDR_PHY_DX8SL0DXCTL2_RDMODE                                                 0x0
+
+		Disables the Read FIFO Reset
+		PSU_DDR_PHY_DX8SL0DXCTL2_DISRST                                                 0x0
+
+		Read DQS Gate I/O Loopback
+		PSU_DDR_PHY_DX8SL0DXCTL2_DQSGLB                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0DXCTL2_RESERVED_0                                             0x0
+
+		DATX8 0-1 DX Control Register 2
+		(OFFSET, MASK, VALUE)      (0XFD08142C, 0xFFFFFFFFU ,0x00001800U)  
+		RegMask = (DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL0DXCTL2_IOAG_MASK | DDR_PHY_DX8SL0DXCTL2_IOLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL0DXCTL2_RDBI_MASK | DDR_PHY_DX8SL0DXCTL2_WDBI_MASK | DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL0DXCTL2_DISRST_MASK | DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL0DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL0IOCR @ 0XFD081430

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL0IOCR_RESERVED_31                                              0x0
+
+		PVREF_DAC REFSEL range select
+		PSU_DDR_PHY_DX8SL0IOCR_DXDACRANGE                                               0x7
+
+		IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		PSU_DDR_PHY_DX8SL0IOCR_DXVREFIOM                                                0x0
+
+		DX IO Mode
+		PSU_DDR_PHY_DX8SL0IOCR_DXIOM                                                    0x2
+
+		DX IO Transmitter Mode
+		PSU_DDR_PHY_DX8SL0IOCR_DXTXM                                                    0x0
+
+		DX IO Receiver Mode
+		PSU_DDR_PHY_DX8SL0IOCR_DXRXM                                                    0x0
+
+		DATX8 0-1 I/O Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD081430, 0xFFFFFFFFU ,0x70800000U)  
+		RegMask = (DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL0IOCR_DXIOM_MASK | DDR_PHY_DX8SL0IOCR_DXTXM_MASK | DDR_PHY_DX8SL0IOCR_DXRXM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT
+			| 0x00000007U << DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT
+			| 0x00000002U << DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL0IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL1DQSCTL @ 0XFD08145C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL1DQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL1DQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SL1DQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SL1DQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SL1DQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SL1DQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SL1DQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SL1DQSCTL_DXSR                                                   0x3
+
+		DQS_N Resistor
+		PSU_DDR_PHY_DX8SL1DQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SL1DQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-1 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD08145C, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL1DQSCTL_DXSR_MASK | DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL1DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL1DXCTL2 @ 0XFD08146C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24                                         0x0
+
+		Configurable Read Data Enable
+		PSU_DDR_PHY_DX8SL1DXCTL2_CRDEN                                                  0x0
+
+		OX Extension during Post-amble
+		PSU_DDR_PHY_DX8SL1DXCTL2_POSOEX                                                 0x0
+
+		OE Extension during Pre-amble
+		PSU_DDR_PHY_DX8SL1DXCTL2_PREOEX                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_17                                            0x0
+
+		I/O Assisted Gate Select
+		PSU_DDR_PHY_DX8SL1DXCTL2_IOAG                                                   0x0
+
+		I/O Loopback Select
+		PSU_DDR_PHY_DX8SL1DXCTL2_IOLB                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13                                         0x0
+
+		Low Power Wakeup Threshold
+		PSU_DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		Read Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL1DXCTL2_RDBI                                                   0x0
+
+		Write Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL1DXCTL2_WDBI                                                   0x0
+
+		PUB Read FIFO Bypass
+		PSU_DDR_PHY_DX8SL1DXCTL2_PRFBYP                                                 0x0
+
+		DATX8 Receive FIFO Read Mode
+		PSU_DDR_PHY_DX8SL1DXCTL2_RDMODE                                                 0x0
+
+		Disables the Read FIFO Reset
+		PSU_DDR_PHY_DX8SL1DXCTL2_DISRST                                                 0x0
+
+		Read DQS Gate I/O Loopback
+		PSU_DDR_PHY_DX8SL1DXCTL2_DQSGLB                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1DXCTL2_RESERVED_0                                             0x0
+
+		DATX8 0-1 DX Control Register 2
+		(OFFSET, MASK, VALUE)      (0XFD08146C, 0xFFFFFFFFU ,0x00001800U)  
+		RegMask = (DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL1DXCTL2_IOAG_MASK | DDR_PHY_DX8SL1DXCTL2_IOLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL1DXCTL2_RDBI_MASK | DDR_PHY_DX8SL1DXCTL2_WDBI_MASK | DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL1DXCTL2_DISRST_MASK | DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL1DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL1IOCR @ 0XFD081470

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL1IOCR_RESERVED_31                                              0x0
+
+		PVREF_DAC REFSEL range select
+		PSU_DDR_PHY_DX8SL1IOCR_DXDACRANGE                                               0x7
+
+		IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		PSU_DDR_PHY_DX8SL1IOCR_DXVREFIOM                                                0x0
+
+		DX IO Mode
+		PSU_DDR_PHY_DX8SL1IOCR_DXIOM                                                    0x2
+
+		DX IO Transmitter Mode
+		PSU_DDR_PHY_DX8SL1IOCR_DXTXM                                                    0x0
+
+		DX IO Receiver Mode
+		PSU_DDR_PHY_DX8SL1IOCR_DXRXM                                                    0x0
+
+		DATX8 0-1 I/O Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD081470, 0xFFFFFFFFU ,0x70800000U)  
+		RegMask = (DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL1IOCR_DXIOM_MASK | DDR_PHY_DX8SL1IOCR_DXTXM_MASK | DDR_PHY_DX8SL1IOCR_DXRXM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT
+			| 0x00000007U << DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT
+			| 0x00000002U << DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL1IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL2DQSCTL @ 0XFD08149C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL2DQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL2DQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SL2DQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SL2DQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SL2DQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SL2DQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SL2DQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SL2DQSCTL_DXSR                                                   0x3
+
+		DQS_N Resistor
+		PSU_DDR_PHY_DX8SL2DQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SL2DQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-1 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD08149C, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL2DQSCTL_DXSR_MASK | DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL2DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL2DXCTL2 @ 0XFD0814AC

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24                                         0x0
+
+		Configurable Read Data Enable
+		PSU_DDR_PHY_DX8SL2DXCTL2_CRDEN                                                  0x0
+
+		OX Extension during Post-amble
+		PSU_DDR_PHY_DX8SL2DXCTL2_POSOEX                                                 0x0
+
+		OE Extension during Pre-amble
+		PSU_DDR_PHY_DX8SL2DXCTL2_PREOEX                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_17                                            0x0
+
+		I/O Assisted Gate Select
+		PSU_DDR_PHY_DX8SL2DXCTL2_IOAG                                                   0x0
+
+		I/O Loopback Select
+		PSU_DDR_PHY_DX8SL2DXCTL2_IOLB                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13                                         0x0
+
+		Low Power Wakeup Threshold
+		PSU_DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		Read Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL2DXCTL2_RDBI                                                   0x0
+
+		Write Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL2DXCTL2_WDBI                                                   0x0
+
+		PUB Read FIFO Bypass
+		PSU_DDR_PHY_DX8SL2DXCTL2_PRFBYP                                                 0x0
+
+		DATX8 Receive FIFO Read Mode
+		PSU_DDR_PHY_DX8SL2DXCTL2_RDMODE                                                 0x0
+
+		Disables the Read FIFO Reset
+		PSU_DDR_PHY_DX8SL2DXCTL2_DISRST                                                 0x0
+
+		Read DQS Gate I/O Loopback
+		PSU_DDR_PHY_DX8SL2DXCTL2_DQSGLB                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2DXCTL2_RESERVED_0                                             0x0
+
+		DATX8 0-1 DX Control Register 2
+		(OFFSET, MASK, VALUE)      (0XFD0814AC, 0xFFFFFFFFU ,0x00001800U)  
+		RegMask = (DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL2DXCTL2_IOAG_MASK | DDR_PHY_DX8SL2DXCTL2_IOLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL2DXCTL2_RDBI_MASK | DDR_PHY_DX8SL2DXCTL2_WDBI_MASK | DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL2DXCTL2_DISRST_MASK | DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL2DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL2IOCR @ 0XFD0814B0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL2IOCR_RESERVED_31                                              0x0
+
+		PVREF_DAC REFSEL range select
+		PSU_DDR_PHY_DX8SL2IOCR_DXDACRANGE                                               0x7
+
+		IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		PSU_DDR_PHY_DX8SL2IOCR_DXVREFIOM                                                0x0
+
+		DX IO Mode
+		PSU_DDR_PHY_DX8SL2IOCR_DXIOM                                                    0x2
+
+		DX IO Transmitter Mode
+		PSU_DDR_PHY_DX8SL2IOCR_DXTXM                                                    0x0
+
+		DX IO Receiver Mode
+		PSU_DDR_PHY_DX8SL2IOCR_DXRXM                                                    0x0
+
+		DATX8 0-1 I/O Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD0814B0, 0xFFFFFFFFU ,0x70800000U)  
+		RegMask = (DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL2IOCR_DXIOM_MASK | DDR_PHY_DX8SL2IOCR_DXTXM_MASK | DDR_PHY_DX8SL2IOCR_DXRXM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT
+			| 0x00000007U << DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT
+			| 0x00000002U << DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL2IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL3DQSCTL @ 0XFD0814DC

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL3DQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL3DQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SL3DQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SL3DQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SL3DQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SL3DQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SL3DQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SL3DQSCTL_DXSR                                                   0x3
+
+		DQS_N Resistor
+		PSU_DDR_PHY_DX8SL3DQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SL3DQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-1 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0814DC, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL3DQSCTL_DXSR_MASK | DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL3DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL3DXCTL2 @ 0XFD0814EC

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24                                         0x0
+
+		Configurable Read Data Enable
+		PSU_DDR_PHY_DX8SL3DXCTL2_CRDEN                                                  0x0
+
+		OX Extension during Post-amble
+		PSU_DDR_PHY_DX8SL3DXCTL2_POSOEX                                                 0x0
+
+		OE Extension during Pre-amble
+		PSU_DDR_PHY_DX8SL3DXCTL2_PREOEX                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_17                                            0x0
+
+		I/O Assisted Gate Select
+		PSU_DDR_PHY_DX8SL3DXCTL2_IOAG                                                   0x0
+
+		I/O Loopback Select
+		PSU_DDR_PHY_DX8SL3DXCTL2_IOLB                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13                                         0x0
+
+		Low Power Wakeup Threshold
+		PSU_DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		Read Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL3DXCTL2_RDBI                                                   0x0
+
+		Write Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL3DXCTL2_WDBI                                                   0x0
+
+		PUB Read FIFO Bypass
+		PSU_DDR_PHY_DX8SL3DXCTL2_PRFBYP                                                 0x0
+
+		DATX8 Receive FIFO Read Mode
+		PSU_DDR_PHY_DX8SL3DXCTL2_RDMODE                                                 0x0
+
+		Disables the Read FIFO Reset
+		PSU_DDR_PHY_DX8SL3DXCTL2_DISRST                                                 0x0
+
+		Read DQS Gate I/O Loopback
+		PSU_DDR_PHY_DX8SL3DXCTL2_DQSGLB                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3DXCTL2_RESERVED_0                                             0x0
+
+		DATX8 0-1 DX Control Register 2
+		(OFFSET, MASK, VALUE)      (0XFD0814EC, 0xFFFFFFFFU ,0x00001800U)  
+		RegMask = (DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL3DXCTL2_IOAG_MASK | DDR_PHY_DX8SL3DXCTL2_IOLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL3DXCTL2_RDBI_MASK | DDR_PHY_DX8SL3DXCTL2_WDBI_MASK | DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL3DXCTL2_DISRST_MASK | DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL3DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL3IOCR @ 0XFD0814F0

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL3IOCR_RESERVED_31                                              0x0
+
+		PVREF_DAC REFSEL range select
+		PSU_DDR_PHY_DX8SL3IOCR_DXDACRANGE                                               0x7
+
+		IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		PSU_DDR_PHY_DX8SL3IOCR_DXVREFIOM                                                0x0
+
+		DX IO Mode
+		PSU_DDR_PHY_DX8SL3IOCR_DXIOM                                                    0x2
+
+		DX IO Transmitter Mode
+		PSU_DDR_PHY_DX8SL3IOCR_DXTXM                                                    0x0
+
+		DX IO Receiver Mode
+		PSU_DDR_PHY_DX8SL3IOCR_DXRXM                                                    0x0
+
+		DATX8 0-1 I/O Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD0814F0, 0xFFFFFFFFU ,0x70800000U)  
+		RegMask = (DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL3IOCR_DXIOM_MASK | DDR_PHY_DX8SL3IOCR_DXTXM_MASK | DDR_PHY_DX8SL3IOCR_DXRXM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT
+			| 0x00000007U << DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT
+			| 0x00000002U << DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL3IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL4DQSCTL @ 0XFD08151C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL4DQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SL4DQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SL4DQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SL4DQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SL4DQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SL4DQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SL4DQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SL4DQSCTL_DXSR                                                   0x3
+
+		DQS_N Resistor
+		PSU_DDR_PHY_DX8SL4DQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SL4DQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-1 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD08151C, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK | DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK | DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK | DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SL4DQSCTL_DXSR_MASK | DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK | DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL4DQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL4DXCTL2 @ 0XFD08152C

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24                                         0x0
+
+		Configurable Read Data Enable
+		PSU_DDR_PHY_DX8SL4DXCTL2_CRDEN                                                  0x0
+
+		OX Extension during Post-amble
+		PSU_DDR_PHY_DX8SL4DXCTL2_POSOEX                                                 0x0
+
+		OE Extension during Pre-amble
+		PSU_DDR_PHY_DX8SL4DXCTL2_PREOEX                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_17                                            0x0
+
+		I/O Assisted Gate Select
+		PSU_DDR_PHY_DX8SL4DXCTL2_IOAG                                                   0x0
+
+		I/O Loopback Select
+		PSU_DDR_PHY_DX8SL4DXCTL2_IOLB                                                   0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13                                         0x0
+
+		Low Power Wakeup Threshold
+		PSU_DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH                                         0xc
+
+		Read Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL4DXCTL2_RDBI                                                   0x0
+
+		Write Data Bus Inversion Enable
+		PSU_DDR_PHY_DX8SL4DXCTL2_WDBI                                                   0x0
+
+		PUB Read FIFO Bypass
+		PSU_DDR_PHY_DX8SL4DXCTL2_PRFBYP                                                 0x0
+
+		DATX8 Receive FIFO Read Mode
+		PSU_DDR_PHY_DX8SL4DXCTL2_RDMODE                                                 0x0
+
+		Disables the Read FIFO Reset
+		PSU_DDR_PHY_DX8SL4DXCTL2_DISRST                                                 0x0
+
+		Read DQS Gate I/O Loopback
+		PSU_DDR_PHY_DX8SL4DXCTL2_DQSGLB                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4DXCTL2_RESERVED_0                                             0x0
+
+		DATX8 0-1 DX Control Register 2
+		(OFFSET, MASK, VALUE)      (0XFD08152C, 0xFFFFFFFFU ,0x00001800U)  
+		RegMask = (DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK | DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK | DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK | DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK | DDR_PHY_DX8SL4DXCTL2_IOAG_MASK | DDR_PHY_DX8SL4DXCTL2_IOLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK | DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK | DDR_PHY_DX8SL4DXCTL2_RDBI_MASK | DDR_PHY_DX8SL4DXCTL2_WDBI_MASK | DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK | DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK | DDR_PHY_DX8SL4DXCTL2_DISRST_MASK | DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK | DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL4DXCTL2_OFFSET ,0xFFFFFFFFU ,0x00001800U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SL4IOCR @ 0XFD081530

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SL4IOCR_RESERVED_31                                              0x0
+
+		PVREF_DAC REFSEL range select
+		PSU_DDR_PHY_DX8SL4IOCR_DXDACRANGE                                               0x7
+
+		IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring
+		PSU_DDR_PHY_DX8SL4IOCR_DXVREFIOM                                                0x0
+
+		DX IO Mode
+		PSU_DDR_PHY_DX8SL4IOCR_DXIOM                                                    0x2
+
+		DX IO Transmitter Mode
+		PSU_DDR_PHY_DX8SL4IOCR_DXTXM                                                    0x0
+
+		DX IO Receiver Mode
+		PSU_DDR_PHY_DX8SL4IOCR_DXRXM                                                    0x0
+
+		DATX8 0-1 I/O Configuration Register
+		(OFFSET, MASK, VALUE)      (0XFD081530, 0xFFFFFFFFU ,0x70800000U)  
+		RegMask = (DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK | DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK | DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK | DDR_PHY_DX8SL4IOCR_DXIOM_MASK | DDR_PHY_DX8SL4IOCR_DXTXM_MASK | DDR_PHY_DX8SL4IOCR_DXRXM_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT
+			| 0x00000007U << DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT
+			| 0x00000002U << DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SL4IOCR_OFFSET ,0xFFFFFFFFU ,0x70800000U);
+	/*############################################################################################################################ */
+
+		/*Register : DX8SLbDQSCTL @ 0XFD0817DC

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25                                         0x0
+
+		Read Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SLBDQSCTL_RRRMODE                                                0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22                                         0x0
+
+		Write Path Rise-to-Rise Mode
+		PSU_DDR_PHY_DX8SLBDQSCTL_WRRMODE                                                0x1
+
+		DQS Gate Extension
+		PSU_DDR_PHY_DX8SLBDQSCTL_DQSGX                                                  0x0
+
+		Low Power PLL Power Down
+		PSU_DDR_PHY_DX8SLBDQSCTL_LPPLLPD                                                0x1
+
+		Low Power I/O Power Down
+		PSU_DDR_PHY_DX8SLBDQSCTL_LPIOPD                                                 0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15                                         0x0
+
+		QS Counter Enable
+		PSU_DDR_PHY_DX8SLBDQSCTL_QSCNTEN                                                0x1
+
+		Unused DQ I/O Mode
+		PSU_DDR_PHY_DX8SLBDQSCTL_UDQIOM                                                 0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10                                         0x0
+
+		Data Slew Rate
+		PSU_DDR_PHY_DX8SLBDQSCTL_DXSR                                                   0x3
+
+		DQS# Resistor
+		PSU_DDR_PHY_DX8SLBDQSCTL_DQSNRES                                                0xc
+
+		DQS Resistor
+		PSU_DDR_PHY_DX8SLBDQSCTL_DQSRES                                                 0x4
+
+		DATX8 0-8 DQS Control Register
+		(OFFSET, MASK, VALUE)      (0XFD0817DC, 0xFFFFFFFFU ,0x012643C4U)  
+		RegMask = (DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK | DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK | DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK | DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK | DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK | DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK | DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK | DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK | DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK | DDR_PHY_DX8SLBDQSCTL_DXSR_MASK | DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK | DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT
+			| 0x00000001U << DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT
+			| 0x00000000U << DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT
+			| 0x00000003U << DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT
+			| 0x0000000CU << DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT
+			| 0x00000004U << DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_DX8SLBDQSCTL_OFFSET ,0xFFFFFFFFU ,0x012643C4U);
+	/*############################################################################################################################ */
+
+		/*Register : PIR @ 0XFD080004

+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_PIR_RESERVED_31                                                     0x0
+
+		Impedance Calibration Bypass
+		PSU_DDR_PHY_PIR_ZCALBYP                                                         0x0
+
+		Digital Delay Line (DDL) Calibration Pause
+		PSU_DDR_PHY_PIR_DCALPSE                                                         0x0
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_PIR_RESERVED_28_21                                                  0x0
+
+		Write DQS2DQ Training
+		PSU_DDR_PHY_PIR_DQS2DQ                                                          0x0
+
+		RDIMM Initialization
+		PSU_DDR_PHY_PIR_RDIMMINIT                                                       0x0
+
+		Controller DRAM Initialization
+		PSU_DDR_PHY_PIR_CTLDINIT                                                        0x1
+
+		VREF Training
+		PSU_DDR_PHY_PIR_VREF                                                            0x0
+
+		Static Read Training
+		PSU_DDR_PHY_PIR_SRD                                                             0x0
+
+		Write Data Eye Training
+		PSU_DDR_PHY_PIR_WREYE                                                           0x0
+
+		Read Data Eye Training
+		PSU_DDR_PHY_PIR_RDEYE                                                           0x0
+
+		Write Data Bit Deskew
+		PSU_DDR_PHY_PIR_WRDSKW                                                          0x0
+
+		Read Data Bit Deskew
+		PSU_DDR_PHY_PIR_RDDSKW                                                          0x0
+
+		Write Leveling Adjust
+		PSU_DDR_PHY_PIR_WLADJ                                                           0x0
+
+		Read DQS Gate Training
+		PSU_DDR_PHY_PIR_QSGATE                                                          0x0
+
+		Write Leveling
+		PSU_DDR_PHY_PIR_WL                                                              0x0
+
+		DRAM Initialization
+		PSU_DDR_PHY_PIR_DRAMINIT                                                        0x0
+
+		DRAM Reset (DDR3/DDR4/LPDDR4 Only)
+		PSU_DDR_PHY_PIR_DRAMRST                                                         0x0
+
+		PHY Reset
+		PSU_DDR_PHY_PIR_PHYRST                                                          0x1
+
+		Digital Delay Line (DDL) Calibration
+		PSU_DDR_PHY_PIR_DCAL                                                            0x1
+
+		PLL Initialiazation
+		PSU_DDR_PHY_PIR_PLLINIT                                                         0x1
+
+		Reserved. Return zeroes on reads.
+		PSU_DDR_PHY_PIR_RESERVED_3                                                      0x0
+
+		CA Training
+		PSU_DDR_PHY_PIR_CA                                                              0x0
+
+		Impedance Calibration
+		PSU_DDR_PHY_PIR_ZCAL                                                            0x1
+
+		Initialization Trigger
+		PSU_DDR_PHY_PIR_INIT                                                            0x1
+
+		PHY Initialization Register
+		(OFFSET, MASK, VALUE)      (0XFD080004, 0xFFFFFFFFU ,0x00040073U)  
+		RegMask = (DDR_PHY_PIR_RESERVED_31_MASK | DDR_PHY_PIR_ZCALBYP_MASK | DDR_PHY_PIR_DCALPSE_MASK | DDR_PHY_PIR_RESERVED_28_21_MASK | DDR_PHY_PIR_DQS2DQ_MASK | DDR_PHY_PIR_RDIMMINIT_MASK | DDR_PHY_PIR_CTLDINIT_MASK | DDR_PHY_PIR_VREF_MASK | DDR_PHY_PIR_SRD_MASK | DDR_PHY_PIR_WREYE_MASK | DDR_PHY_PIR_RDEYE_MASK | DDR_PHY_PIR_WRDSKW_MASK | DDR_PHY_PIR_RDDSKW_MASK | DDR_PHY_PIR_WLADJ_MASK | DDR_PHY_PIR_QSGATE_MASK | DDR_PHY_PIR_WL_MASK | DDR_PHY_PIR_DRAMINIT_MASK | DDR_PHY_PIR_DRAMRST_MASK | DDR_PHY_PIR_PHYRST_MASK | DDR_PHY_PIR_DCAL_MASK | DDR_PHY_PIR_PLLINIT_MASK | DDR_PHY_PIR_RESERVED_3_MASK | DDR_PHY_PIR_CA_MASK | DDR_PHY_PIR_ZCAL_MASK | DDR_PHY_PIR_INIT_MASK |  0 );
+
+		RegVal = ((0x00000000U << DDR_PHY_PIR_RESERVED_31_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_ZCALBYP_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_DCALPSE_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_RESERVED_28_21_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_DQS2DQ_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_RDIMMINIT_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_CTLDINIT_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_VREF_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_SRD_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_WREYE_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_RDEYE_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_WRDSKW_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_RDDSKW_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_WLADJ_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_QSGATE_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_WL_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_DRAMINIT_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_DRAMRST_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_PHYRST_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_DCAL_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_PLLINIT_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_RESERVED_3_SHIFT
+			| 0x00000000U << DDR_PHY_PIR_CA_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_ZCAL_SHIFT
+			| 0x00000001U << DDR_PHY_PIR_INIT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DDR_PHY_PIR_OFFSET ,0xFFFFFFFFU ,0x00040073U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_mio_init_data() {
+		// : MIO PROGRAMMING
+		/*Register : MIO_PIN_0 @ 0XFF180000

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_0_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_0_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[0]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_0_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_0_L3_SEL                                                   0
+
+		Configures MIO Pin 0 peripheral interface mapping. S
+		(OFFSET, MASK, VALUE)      (0XFF180000, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_0_L0_SEL_MASK | IOU_SLCR_MIO_PIN_0_L1_SEL_MASK | IOU_SLCR_MIO_PIN_0_L2_SEL_MASK | IOU_SLCR_MIO_PIN_0_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_0_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_1 @ 0XFF180004

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
+		us)
+		PSU_IOU_SLCR_MIO_PIN_1_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_1_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[1]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_1_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)
+		PSU_IOU_SLCR_MIO_PIN_1_L3_SEL                                                   0
+
+		Configures MIO Pin 1 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180004, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_1_L0_SEL_MASK | IOU_SLCR_MIO_PIN_1_L1_SEL_MASK | IOU_SLCR_MIO_PIN_1_L2_SEL_MASK | IOU_SLCR_MIO_PIN_1_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_1_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_2 @ 0XFF180008

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)
+		PSU_IOU_SLCR_MIO_PIN_2_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_2_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[2]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_2_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_2_L3_SEL                                                   0
+
+		Configures MIO Pin 2 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180008, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_2_L0_SEL_MASK | IOU_SLCR_MIO_PIN_2_L1_SEL_MASK | IOU_SLCR_MIO_PIN_2_L2_SEL_MASK | IOU_SLCR_MIO_PIN_2_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_2_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_3 @ 0XFF18000C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)
+		PSU_IOU_SLCR_MIO_PIN_3_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_3_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[3]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_3_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_3_L3_SEL                                                   0
+
+		Configures MIO Pin 3 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18000C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_3_L0_SEL_MASK | IOU_SLCR_MIO_PIN_3_L1_SEL_MASK | IOU_SLCR_MIO_PIN_3_L2_SEL_MASK | IOU_SLCR_MIO_PIN_3_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_3_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_4 @ 0XFF180010

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
+		us)
+		PSU_IOU_SLCR_MIO_PIN_4_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_4_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[4]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_4_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_4_L3_SEL                                                   0
+
+		Configures MIO Pin 4 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180010, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_4_L0_SEL_MASK | IOU_SLCR_MIO_PIN_4_L1_SEL_MASK | IOU_SLCR_MIO_PIN_4_L2_SEL_MASK | IOU_SLCR_MIO_PIN_4_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_4_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_5 @ 0XFF180014

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)
+		PSU_IOU_SLCR_MIO_PIN_5_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_5_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[5]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_5_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_5_L3_SEL                                                   0
+
+		Configures MIO Pin 5 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180014, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_5_L0_SEL_MASK | IOU_SLCR_MIO_PIN_5_L1_SEL_MASK | IOU_SLCR_MIO_PIN_5_L2_SEL_MASK | IOU_SLCR_MIO_PIN_5_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_5_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_6 @ 0XFF180018

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)
+		PSU_IOU_SLCR_MIO_PIN_6_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_6_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[6]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_6_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
+		sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
+		Output, tracedq[4]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_6_L3_SEL                                                   0
+
+		Configures MIO Pin 6 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180018, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_6_L0_SEL_MASK | IOU_SLCR_MIO_PIN_6_L1_SEL_MASK | IOU_SLCR_MIO_PIN_6_L2_SEL_MASK | IOU_SLCR_MIO_PIN_6_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_6_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_7 @ 0XFF18001C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)
+		PSU_IOU_SLCR_MIO_PIN_7_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_7_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[7]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_7_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= 
+		tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, 
+		racedq[5]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_7_L3_SEL                                                   0
+
+		Configures MIO Pin 7 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18001C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_7_L0_SEL_MASK | IOU_SLCR_MIO_PIN_7_L1_SEL_MASK | IOU_SLCR_MIO_PIN_7_L2_SEL_MASK | IOU_SLCR_MIO_PIN_7_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_7_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_8 @ 0XFF180020

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[0]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_8_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_8_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[8]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_8_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
+		, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
+		ce Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_8_L3_SEL                                                   0
+
+		Configures MIO Pin 8 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180020, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_8_L0_SEL_MASK | IOU_SLCR_MIO_PIN_8_L1_SEL_MASK | IOU_SLCR_MIO_PIN_8_L2_SEL_MASK | IOU_SLCR_MIO_PIN_8_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_8_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_9 @ 0XFF180024

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[1]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_9_L0_SEL                                                   1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_9_L1_SEL                                                   0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[9]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_9_L2_SEL                                                   0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, 
+		utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
+		RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_9_L3_SEL                                                   0
+
+		Configures MIO Pin 9 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180024, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_9_L0_SEL_MASK | IOU_SLCR_MIO_PIN_9_L1_SEL_MASK | IOU_SLCR_MIO_PIN_9_L2_SEL_MASK | IOU_SLCR_MIO_PIN_9_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_9_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_10 @ 0XFF180028

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[2]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_10_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_10_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[10]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_10_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_10_L3_SEL                                                  0
+
+		Configures MIO Pin 10 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180028, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_10_L0_SEL_MASK | IOU_SLCR_MIO_PIN_10_L1_SEL_MASK | IOU_SLCR_MIO_PIN_10_L2_SEL_MASK | IOU_SLCR_MIO_PIN_10_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_10_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_11 @ 0XFF18002C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[3]- (QSPI Upper Databus)
+		PSU_IOU_SLCR_MIO_PIN_11_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_11_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[11]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_11_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_11_L3_SEL                                                  0
+
+		Configures MIO Pin 11 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18002C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_11_L0_SEL_MASK | IOU_SLCR_MIO_PIN_11_L1_SEL_MASK | IOU_SLCR_MIO_PIN_11_L2_SEL_MASK | IOU_SLCR_MIO_PIN_11_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_11_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_12 @ 0XFF180030

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)
+		PSU_IOU_SLCR_MIO_PIN_12_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		
+		PSU_IOU_SLCR_MIO_PIN_12_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[12]- (Test Scan Port) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_12_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
+		ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
+		dq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_12_L3_SEL                                                  0
+
+		Configures MIO Pin 12 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180030, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_12_L0_SEL_MASK | IOU_SLCR_MIO_PIN_12_L1_SEL_MASK | IOU_SLCR_MIO_PIN_12_L2_SEL_MASK | IOU_SLCR_MIO_PIN_12_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_12_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_13 @ 0XFF180034

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_13_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_13_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_13_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
+		out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
+		bus)
+		PSU_IOU_SLCR_MIO_PIN_13_L3_SEL                                                  0
+
+		Configures MIO Pin 13 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180034, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_13_L0_SEL_MASK | IOU_SLCR_MIO_PIN_13_L1_SEL_MASK | IOU_SLCR_MIO_PIN_13_L2_SEL_MASK | IOU_SLCR_MIO_PIN_13_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_13_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_14 @ 0XFF180038

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_14_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)
+		PSU_IOU_SLCR_MIO_PIN_14_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_14_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
+		n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_14_L3_SEL                                                  2
+
+		Configures MIO Pin 14 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180038, 0x000000FEU ,0x00000040U)  
+		RegMask = (IOU_SLCR_MIO_PIN_14_L0_SEL_MASK | IOU_SLCR_MIO_PIN_14_L1_SEL_MASK | IOU_SLCR_MIO_PIN_14_L2_SEL_MASK | IOU_SLCR_MIO_PIN_14_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_14_OFFSET ,0x000000FEU ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_15 @ 0XFF18003C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_15_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)
+		PSU_IOU_SLCR_MIO_PIN_15_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_15_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
+		0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
+		l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_15_L3_SEL                                                  2
+
+		Configures MIO Pin 15 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18003C, 0x000000FEU ,0x00000040U)  
+		RegMask = (IOU_SLCR_MIO_PIN_15_L0_SEL_MASK | IOU_SLCR_MIO_PIN_15_L1_SEL_MASK | IOU_SLCR_MIO_PIN_15_L2_SEL_MASK | IOU_SLCR_MIO_PIN_15_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_15_OFFSET ,0x000000FEU ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_16 @ 0XFF180040

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_16_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_16_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_16_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_16_L3_SEL                                                  2
+
+		Configures MIO Pin 16 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180040, 0x000000FEU ,0x00000040U)  
+		RegMask = (IOU_SLCR_MIO_PIN_16_L0_SEL_MASK | IOU_SLCR_MIO_PIN_16_L1_SEL_MASK | IOU_SLCR_MIO_PIN_16_L2_SEL_MASK | IOU_SLCR_MIO_PIN_16_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_16_OFFSET ,0x000000FEU ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_17 @ 0XFF180044

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_17_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_17_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
+		 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_17_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_17_L3_SEL                                                  2
+
+		Configures MIO Pin 17 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180044, 0x000000FEU ,0x00000040U)  
+		RegMask = (IOU_SLCR_MIO_PIN_17_L0_SEL_MASK | IOU_SLCR_MIO_PIN_17_L1_SEL_MASK | IOU_SLCR_MIO_PIN_17_L2_SEL_MASK | IOU_SLCR_MIO_PIN_17_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_17_OFFSET ,0x000000FEU ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_18 @ 0XFF180048

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_18_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_18_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_18_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_18_L3_SEL                                                  6
+
+		Configures MIO Pin 18 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180048, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_18_L0_SEL_MASK | IOU_SLCR_MIO_PIN_18_L1_SEL_MASK | IOU_SLCR_MIO_PIN_18_L2_SEL_MASK | IOU_SLCR_MIO_PIN_18_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_18_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_19 @ 0XFF18004C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_19_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_19_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_19_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_19_L3_SEL                                                  6
+
+		Configures MIO Pin 19 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18004C, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_19_L0_SEL_MASK | IOU_SLCR_MIO_PIN_19_L1_SEL_MASK | IOU_SLCR_MIO_PIN_19_L2_SEL_MASK | IOU_SLCR_MIO_PIN_19_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_19_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_20 @ 0XFF180050

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_20_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_20_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_20_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
+		c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_20_L3_SEL                                                  6
+
+		Configures MIO Pin 20 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180050, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_20_L0_SEL_MASK | IOU_SLCR_MIO_PIN_20_L1_SEL_MASK | IOU_SLCR_MIO_PIN_20_L2_SEL_MASK | IOU_SLCR_MIO_PIN_20_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_20_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_21 @ 0XFF180054

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_21_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_21_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 
+		= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_21_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- 
+		UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_21_L3_SEL                                                  6
+
+		Configures MIO Pin 21 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180054, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_21_L0_SEL_MASK | IOU_SLCR_MIO_PIN_21_L1_SEL_MASK | IOU_SLCR_MIO_PIN_21_L2_SEL_MASK | IOU_SLCR_MIO_PIN_21_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_21_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_22 @ 0XFF180058

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_22_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)
+		PSU_IOU_SLCR_MIO_PIN_22_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
+		(Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_22_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed
+		PSU_IOU_SLCR_MIO_PIN_22_L3_SEL                                                  0
+
+		Configures MIO Pin 22 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180058, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_22_L0_SEL_MASK | IOU_SLCR_MIO_PIN_22_L1_SEL_MASK | IOU_SLCR_MIO_PIN_22_L2_SEL_MASK | IOU_SLCR_MIO_PIN_22_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_22_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_23 @ 0XFF18005C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_23_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_23_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
+		23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
+		
+		PSU_IOU_SLCR_MIO_PIN_23_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_23_L3_SEL                                                  0
+
+		Configures MIO Pin 23 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18005C, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_23_L0_SEL_MASK | IOU_SLCR_MIO_PIN_23_L1_SEL_MASK | IOU_SLCR_MIO_PIN_23_L2_SEL_MASK | IOU_SLCR_MIO_PIN_23_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_23_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_24 @ 0XFF180060

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_24_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND 
+		ata Bus)
+		PSU_IOU_SLCR_MIO_PIN_24_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
+		scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
+		 Tamper)
+		PSU_IOU_SLCR_MIO_PIN_24_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
+		Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_24_L3_SEL                                                  1
+
+		Configures MIO Pin 24 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180060, 0x000000FEU ,0x00000020U)  
+		RegMask = (IOU_SLCR_MIO_PIN_24_L0_SEL_MASK | IOU_SLCR_MIO_PIN_24_L1_SEL_MASK | IOU_SLCR_MIO_PIN_24_L2_SEL_MASK | IOU_SLCR_MIO_PIN_24_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_24_OFFSET ,0x000000FEU ,0x00000020U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_25 @ 0XFF180064

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_25_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)
+		PSU_IOU_SLCR_MIO_PIN_25_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
+		test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
+		U Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_25_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform 
+		lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_25_L3_SEL                                                  1
+
+		Configures MIO Pin 25 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180064, 0x000000FEU ,0x00000020U)  
+		RegMask = (IOU_SLCR_MIO_PIN_25_L0_SEL_MASK | IOU_SLCR_MIO_PIN_25_L1_SEL_MASK | IOU_SLCR_MIO_PIN_25_L2_SEL_MASK | IOU_SLCR_MIO_PIN_25_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_25_OFFSET ,0x000000FEU ,0x00000020U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_26 @ 0XFF180068

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_26_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)
+		PSU_IOU_SLCR_MIO_PIN_26_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_26_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_26_L3_SEL                                                  0
+
+		Configures MIO Pin 26 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180068, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_26_L0_SEL_MASK | IOU_SLCR_MIO_PIN_26_L1_SEL_MASK | IOU_SLCR_MIO_PIN_26_L2_SEL_MASK | IOU_SLCR_MIO_PIN_26_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_26_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_27 @ 0XFF18006C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_27_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_27_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_27_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)
+		PSU_IOU_SLCR_MIO_PIN_27_L3_SEL                                                  0
+
+		Configures MIO Pin 27 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18006C, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_27_L0_SEL_MASK | IOU_SLCR_MIO_PIN_27_L1_SEL_MASK | IOU_SLCR_MIO_PIN_27_L2_SEL_MASK | IOU_SLCR_MIO_PIN_27_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_27_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_28 @ 0XFF180070

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_28_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)
+		PSU_IOU_SLCR_MIO_PIN_28_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_28_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_28_L3_SEL                                                  0
+
+		Configures MIO Pin 28 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180070, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_28_L0_SEL_MASK | IOU_SLCR_MIO_PIN_28_L1_SEL_MASK | IOU_SLCR_MIO_PIN_28_L2_SEL_MASK | IOU_SLCR_MIO_PIN_28_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_28_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_29 @ 0XFF180074

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_29_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_29_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_29_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_29_L3_SEL                                                  0
+
+		Configures MIO Pin 29 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180074, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_29_L0_SEL_MASK | IOU_SLCR_MIO_PIN_29_L1_SEL_MASK | IOU_SLCR_MIO_PIN_29_L2_SEL_MASK | IOU_SLCR_MIO_PIN_29_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_29_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_30 @ 0XFF180078

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_30_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_30_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_30_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
+		 (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
+		 tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_30_L3_SEL                                                  0
+
+		Configures MIO Pin 30 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180078, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_30_L0_SEL_MASK | IOU_SLCR_MIO_PIN_30_L1_SEL_MASK | IOU_SLCR_MIO_PIN_30_L2_SEL_MASK | IOU_SLCR_MIO_PIN_30_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_30_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_31 @ 0XFF18007C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_31_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_31_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_31_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
+		_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
+		ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_31_L3_SEL                                                  0
+
+		Configures MIO Pin 31 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18007C, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_31_L0_SEL_MASK | IOU_SLCR_MIO_PIN_31_L1_SEL_MASK | IOU_SLCR_MIO_PIN_31_L2_SEL_MASK | IOU_SLCR_MIO_PIN_31_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_31_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_32 @ 0XFF180080

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_32_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		
+		PSU_IOU_SLCR_MIO_PIN_32_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
+		an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_32_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
+		_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= 
+		race, Output, tracedq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_32_L3_SEL                                                  0
+
+		Configures MIO Pin 32 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180080, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_32_L0_SEL_MASK | IOU_SLCR_MIO_PIN_32_L1_SEL_MASK | IOU_SLCR_MIO_PIN_32_L2_SEL_MASK | IOU_SLCR_MIO_PIN_32_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_32_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_33 @ 0XFF180084

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_33_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_33_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
+		an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)
+		PSU_IOU_SLCR_MIO_PIN_33_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
+		c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
+		[11]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_33_L3_SEL                                                  0
+
+		Configures MIO Pin 33 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180084, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_33_L0_SEL_MASK | IOU_SLCR_MIO_PIN_33_L1_SEL_MASK | IOU_SLCR_MIO_PIN_33_L2_SEL_MASK | IOU_SLCR_MIO_PIN_33_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_33_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_34 @ 0XFF180088

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_34_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_34_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
+		an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
+		ut, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_34_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
+		 Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
+		rt Databus)
+		PSU_IOU_SLCR_MIO_PIN_34_L3_SEL                                                  0
+
+		Configures MIO Pin 34 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180088, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_34_L0_SEL_MASK | IOU_SLCR_MIO_PIN_34_L1_SEL_MASK | IOU_SLCR_MIO_PIN_34_L2_SEL_MASK | IOU_SLCR_MIO_PIN_34_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_34_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_35 @ 0XFF18008C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_35_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_35_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
+		an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_35_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
+		Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- 
+		UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_35_L3_SEL                                                  0
+
+		Configures MIO Pin 35 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18008C, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_35_L0_SEL_MASK | IOU_SLCR_MIO_PIN_35_L1_SEL_MASK | IOU_SLCR_MIO_PIN_35_L2_SEL_MASK | IOU_SLCR_MIO_PIN_35_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_35_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_36 @ 0XFF180090

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_36_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_36_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
+		an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
+		ut, dp_aux_data_out- (Dp Aux Data)
+		PSU_IOU_SLCR_MIO_PIN_36_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_36_L3_SEL                                                  0
+
+		Configures MIO Pin 36 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180090, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_36_L0_SEL_MASK | IOU_SLCR_MIO_PIN_36_L1_SEL_MASK | IOU_SLCR_MIO_PIN_36_L2_SEL_MASK | IOU_SLCR_MIO_PIN_36_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_36_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_37 @ 0XFF180094

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_37_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)
+		PSU_IOU_SLCR_MIO_PIN_37_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
+		an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)
+		PSU_IOU_SLCR_MIO_PIN_37_L2_SEL                                                  1
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_37_L3_SEL                                                  0
+
+		Configures MIO Pin 37 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180094, 0x000000FEU ,0x00000008U)  
+		RegMask = (IOU_SLCR_MIO_PIN_37_L0_SEL_MASK | IOU_SLCR_MIO_PIN_37_L1_SEL_MASK | IOU_SLCR_MIO_PIN_37_L2_SEL_MASK | IOU_SLCR_MIO_PIN_37_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_37_OFFSET ,0x000000FEU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_38 @ 0XFF180098

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_38_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_38_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_38_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
+		k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
+		(Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_38_L3_SEL                                                  0
+
+		Configures MIO Pin 38 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180098, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_38_L0_SEL_MASK | IOU_SLCR_MIO_PIN_38_L1_SEL_MASK | IOU_SLCR_MIO_PIN_38_L2_SEL_MASK | IOU_SLCR_MIO_PIN_38_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_38_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_39 @ 0XFF18009C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_39_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_39_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
+		[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_39_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
+		_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
+		Control Signal)
+		PSU_IOU_SLCR_MIO_PIN_39_L3_SEL                                                  0
+
+		Configures MIO Pin 39 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18009C, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_39_L0_SEL_MASK | IOU_SLCR_MIO_PIN_39_L1_SEL_MASK | IOU_SLCR_MIO_PIN_39_L2_SEL_MASK | IOU_SLCR_MIO_PIN_39_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_39_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_40 @ 0XFF1800A0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_40_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_40_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_40_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
+		in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_40_L3_SEL                                                  0
+
+		Configures MIO Pin 40 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A0, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_40_L0_SEL_MASK | IOU_SLCR_MIO_PIN_40_L1_SEL_MASK | IOU_SLCR_MIO_PIN_40_L2_SEL_MASK | IOU_SLCR_MIO_PIN_40_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_40_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_41 @ 0XFF1800A4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_41_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_41_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_41_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
+		]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
+		ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_41_L3_SEL                                                  0
+
+		Configures MIO Pin 41 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A4, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_41_L0_SEL_MASK | IOU_SLCR_MIO_PIN_41_L1_SEL_MASK | IOU_SLCR_MIO_PIN_41_L2_SEL_MASK | IOU_SLCR_MIO_PIN_41_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_41_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_42 @ 0XFF1800A8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_42_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_42_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_42_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_42_L3_SEL                                                  0
+
+		Configures MIO Pin 42 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800A8, 0x000000FEU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_PIN_42_L0_SEL_MASK | IOU_SLCR_MIO_PIN_42_L1_SEL_MASK | IOU_SLCR_MIO_PIN_42_L2_SEL_MASK | IOU_SLCR_MIO_PIN_42_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_42_OFFSET ,0x000000FEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_43 @ 0XFF1800AC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_43_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_43_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_43_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
+		i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_43_L3_SEL                                                  0
+
+		Configures MIO Pin 43 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800AC, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_43_L0_SEL_MASK | IOU_SLCR_MIO_PIN_43_L1_SEL_MASK | IOU_SLCR_MIO_PIN_43_L2_SEL_MASK | IOU_SLCR_MIO_PIN_43_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_43_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_44 @ 0XFF1800B0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_44_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
+		i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 Not Used
+		PSU_IOU_SLCR_MIO_PIN_44_L3_SEL                                                  0
+
+		Configures MIO Pin 44 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B0, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_44_L0_SEL_MASK | IOU_SLCR_MIO_PIN_44_L1_SEL_MASK | IOU_SLCR_MIO_PIN_44_L2_SEL_MASK | IOU_SLCR_MIO_PIN_44_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_44_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_45 @ 0XFF1800B4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_45_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_45_L3_SEL                                                  0
+
+		Configures MIO Pin 45 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B4, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_45_L0_SEL_MASK | IOU_SLCR_MIO_PIN_45_L1_SEL_MASK | IOU_SLCR_MIO_PIN_45_L2_SEL_MASK | IOU_SLCR_MIO_PIN_45_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_45_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_46 @ 0XFF1800B8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_46_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
+		0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_46_L3_SEL                                                  0
+
+		Configures MIO Pin 46 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800B8, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_46_L0_SEL_MASK | IOU_SLCR_MIO_PIN_46_L1_SEL_MASK | IOU_SLCR_MIO_PIN_46_L2_SEL_MASK | IOU_SLCR_MIO_PIN_46_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_46_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_47 @ 0XFF1800BC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_47_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_47_L3_SEL                                                  0
+
+		Configures MIO Pin 47 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800BC, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_47_L0_SEL_MASK | IOU_SLCR_MIO_PIN_47_L1_SEL_MASK | IOU_SLCR_MIO_PIN_47_L2_SEL_MASK | IOU_SLCR_MIO_PIN_47_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_47_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_48 @ 0XFF1800C0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_48_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_48_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_48_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
+		ed
+		PSU_IOU_SLCR_MIO_PIN_48_L3_SEL                                                  0
+
+		Configures MIO Pin 48 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C0, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_48_L0_SEL_MASK | IOU_SLCR_MIO_PIN_48_L1_SEL_MASK | IOU_SLCR_MIO_PIN_48_L2_SEL_MASK | IOU_SLCR_MIO_PIN_48_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_48_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_49 @ 0XFF1800C4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_49_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
+		bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_49_L3_SEL                                                  0
+
+		Configures MIO Pin 49 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C4, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_49_L0_SEL_MASK | IOU_SLCR_MIO_PIN_49_L1_SEL_MASK | IOU_SLCR_MIO_PIN_49_L2_SEL_MASK | IOU_SLCR_MIO_PIN_49_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_49_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_50 @ 0XFF1800C8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+		PSU_IOU_SLCR_MIO_PIN_50_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
+		d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
+		clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_50_L3_SEL                                                  0
+
+		Configures MIO Pin 50 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800C8, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_50_L0_SEL_MASK | IOU_SLCR_MIO_PIN_50_L1_SEL_MASK | IOU_SLCR_MIO_PIN_50_L2_SEL_MASK | IOU_SLCR_MIO_PIN_50_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_50_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_51 @ 0XFF1800CC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)
+		PSU_IOU_SLCR_MIO_PIN_51_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L2_SEL                                                  2
+
+		Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
+		t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
+		serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_51_L3_SEL                                                  0
+
+		Configures MIO Pin 51 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800CC, 0x000000FEU ,0x00000010U)  
+		RegMask = (IOU_SLCR_MIO_PIN_51_L0_SEL_MASK | IOU_SLCR_MIO_PIN_51_L1_SEL_MASK | IOU_SLCR_MIO_PIN_51_L2_SEL_MASK | IOU_SLCR_MIO_PIN_51_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT
+			| 0x00000002U << IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_51_OFFSET ,0x000000FEU ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_52 @ 0XFF1800D0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_52_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)
+		PSU_IOU_SLCR_MIO_PIN_52_L3_SEL                                                  0
+
+		Configures MIO Pin 52 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D0, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_52_L0_SEL_MASK | IOU_SLCR_MIO_PIN_52_L1_SEL_MASK | IOU_SLCR_MIO_PIN_52_L2_SEL_MASK | IOU_SLCR_MIO_PIN_52_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_52_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_53 @ 0XFF1800D4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_53_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)
+		PSU_IOU_SLCR_MIO_PIN_53_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_53_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)
+		PSU_IOU_SLCR_MIO_PIN_53_L3_SEL                                                  0
+
+		Configures MIO Pin 53 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D4, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_53_L0_SEL_MASK | IOU_SLCR_MIO_PIN_53_L1_SEL_MASK | IOU_SLCR_MIO_PIN_53_L2_SEL_MASK | IOU_SLCR_MIO_PIN_53_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_53_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_54 @ 0XFF1800D8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_54_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[2]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_54_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_54_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_54_L3_SEL                                                  0
+
+		Configures MIO Pin 54 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800D8, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_54_L0_SEL_MASK | IOU_SLCR_MIO_PIN_54_L1_SEL_MASK | IOU_SLCR_MIO_PIN_54_L2_SEL_MASK | IOU_SLCR_MIO_PIN_54_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_54_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_55 @ 0XFF1800DC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_55_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)
+		PSU_IOU_SLCR_MIO_PIN_55_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_55_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_55_L3_SEL                                                  0
+
+		Configures MIO Pin 55 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800DC, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_55_L0_SEL_MASK | IOU_SLCR_MIO_PIN_55_L1_SEL_MASK | IOU_SLCR_MIO_PIN_55_L2_SEL_MASK | IOU_SLCR_MIO_PIN_55_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_55_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_56 @ 0XFF1800E0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_56_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[0]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_56_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_56_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_56_L3_SEL                                                  0
+
+		Configures MIO Pin 56 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E0, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_56_L0_SEL_MASK | IOU_SLCR_MIO_PIN_56_L1_SEL_MASK | IOU_SLCR_MIO_PIN_56_L2_SEL_MASK | IOU_SLCR_MIO_PIN_56_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_56_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_57 @ 0XFF1800E4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_57_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[1]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_57_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_57_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_57_L3_SEL                                                  0
+
+		Configures MIO Pin 57 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E4, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_57_L0_SEL_MASK | IOU_SLCR_MIO_PIN_57_L1_SEL_MASK | IOU_SLCR_MIO_PIN_57_L2_SEL_MASK | IOU_SLCR_MIO_PIN_57_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_57_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_58 @ 0XFF1800E8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_58_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)
+		PSU_IOU_SLCR_MIO_PIN_58_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_58_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_58_L3_SEL                                                  0
+
+		Configures MIO Pin 58 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800E8, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_58_L0_SEL_MASK | IOU_SLCR_MIO_PIN_58_L1_SEL_MASK | IOU_SLCR_MIO_PIN_58_L2_SEL_MASK | IOU_SLCR_MIO_PIN_58_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_58_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_59 @ 0XFF1800EC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_59_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[3]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_59_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_59_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)
+		PSU_IOU_SLCR_MIO_PIN_59_L3_SEL                                                  0
+
+		Configures MIO Pin 59 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800EC, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_59_L0_SEL_MASK | IOU_SLCR_MIO_PIN_59_L1_SEL_MASK | IOU_SLCR_MIO_PIN_59_L2_SEL_MASK | IOU_SLCR_MIO_PIN_59_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_59_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_60 @ 0XFF1800F0

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_60_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[4]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_60_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_60_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_60_L3_SEL                                                  0
+
+		Configures MIO Pin 60 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F0, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_60_L0_SEL_MASK | IOU_SLCR_MIO_PIN_60_L1_SEL_MASK | IOU_SLCR_MIO_PIN_60_L2_SEL_MASK | IOU_SLCR_MIO_PIN_60_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_60_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_61 @ 0XFF1800F4

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_61_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[5]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_61_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_61_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_61_L3_SEL                                                  0
+
+		Configures MIO Pin 61 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F4, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_61_L0_SEL_MASK | IOU_SLCR_MIO_PIN_61_L1_SEL_MASK | IOU_SLCR_MIO_PIN_61_L2_SEL_MASK | IOU_SLCR_MIO_PIN_61_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_61_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_62 @ 0XFF1800F8

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_62_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[6]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_62_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_62_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_62_L3_SEL                                                  0
+
+		Configures MIO Pin 62 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800F8, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_62_L0_SEL_MASK | IOU_SLCR_MIO_PIN_62_L1_SEL_MASK | IOU_SLCR_MIO_PIN_62_L2_SEL_MASK | IOU_SLCR_MIO_PIN_62_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_62_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_63 @ 0XFF1800FC

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_63_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[7]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_63_L1_SEL                                                  1
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_63_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_63_L3_SEL                                                  0
+
+		Configures MIO Pin 63 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF1800FC, 0x000000FEU ,0x00000004U)  
+		RegMask = (IOU_SLCR_MIO_PIN_63_L0_SEL_MASK | IOU_SLCR_MIO_PIN_63_L1_SEL_MASK | IOU_SLCR_MIO_PIN_63_L2_SEL_MASK | IOU_SLCR_MIO_PIN_63_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_63_OFFSET ,0x000000FEU ,0x00000004U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_64 @ 0XFF180100

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_64_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)
+		PSU_IOU_SLCR_MIO_PIN_64_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_64_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
+		i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 trace, Output, tracedq[10]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_64_L3_SEL                                                  0
+
+		Configures MIO Pin 64 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180100, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_64_L0_SEL_MASK | IOU_SLCR_MIO_PIN_64_L1_SEL_MASK | IOU_SLCR_MIO_PIN_64_L2_SEL_MASK | IOU_SLCR_MIO_PIN_64_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_64_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_65 @ 0XFF180104

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_65_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)
+		PSU_IOU_SLCR_MIO_PIN_65_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_65_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
+		dq[11]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_65_L3_SEL                                                  0
+
+		Configures MIO Pin 65 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180104, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_65_L0_SEL_MASK | IOU_SLCR_MIO_PIN_65_L1_SEL_MASK | IOU_SLCR_MIO_PIN_65_L2_SEL_MASK | IOU_SLCR_MIO_PIN_65_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_65_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_66 @ 0XFF180108

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_66_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[2]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_66_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_66_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
+		2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
+		Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_66_L3_SEL                                                  0
+
+		Configures MIO Pin 66 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180108, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_66_L0_SEL_MASK | IOU_SLCR_MIO_PIN_66_L1_SEL_MASK | IOU_SLCR_MIO_PIN_66_L2_SEL_MASK | IOU_SLCR_MIO_PIN_66_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_66_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_67 @ 0XFF18010C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_67_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)
+		PSU_IOU_SLCR_MIO_PIN_67_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_67_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_67_L3_SEL                                                  0
+
+		Configures MIO Pin 67 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18010C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_67_L0_SEL_MASK | IOU_SLCR_MIO_PIN_67_L1_SEL_MASK | IOU_SLCR_MIO_PIN_67_L2_SEL_MASK | IOU_SLCR_MIO_PIN_67_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_67_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_68 @ 0XFF180110

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_68_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[0]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_68_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= Not Used 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_68_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_68_L3_SEL                                                  0
+
+		Configures MIO Pin 68 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180110, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_68_L0_SEL_MASK | IOU_SLCR_MIO_PIN_68_L1_SEL_MASK | IOU_SLCR_MIO_PIN_68_L2_SEL_MASK | IOU_SLCR_MIO_PIN_68_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_68_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_69 @ 0XFF180114

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)
+		PSU_IOU_SLCR_MIO_PIN_69_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[1]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_69_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_69_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)
+		PSU_IOU_SLCR_MIO_PIN_69_L3_SEL                                                  0
+
+		Configures MIO Pin 69 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180114, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_69_L0_SEL_MASK | IOU_SLCR_MIO_PIN_69_L1_SEL_MASK | IOU_SLCR_MIO_PIN_69_L2_SEL_MASK | IOU_SLCR_MIO_PIN_69_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_69_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_70 @ 0XFF180118

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)
+		PSU_IOU_SLCR_MIO_PIN_70_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)
+		PSU_IOU_SLCR_MIO_PIN_70_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_70_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed
+		PSU_IOU_SLCR_MIO_PIN_70_L3_SEL                                                  0
+
+		Configures MIO Pin 70 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180118, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_70_L0_SEL_MASK | IOU_SLCR_MIO_PIN_70_L1_SEL_MASK | IOU_SLCR_MIO_PIN_70_L2_SEL_MASK | IOU_SLCR_MIO_PIN_70_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_70_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_71 @ 0XFF18011C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_71_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[3]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_71_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_71_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_71_L3_SEL                                                  0
+
+		Configures MIO Pin 71 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18011C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_71_L0_SEL_MASK | IOU_SLCR_MIO_PIN_71_L1_SEL_MASK | IOU_SLCR_MIO_PIN_71_L2_SEL_MASK | IOU_SLCR_MIO_PIN_71_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_71_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_72 @ 0XFF180120

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_72_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[4]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_72_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_72_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
+		t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_72_L3_SEL                                                  0
+
+		Configures MIO Pin 72 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180120, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_72_L0_SEL_MASK | IOU_SLCR_MIO_PIN_72_L1_SEL_MASK | IOU_SLCR_MIO_PIN_72_L2_SEL_MASK | IOU_SLCR_MIO_PIN_72_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_72_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_73 @ 0XFF180124

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_73_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[5]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_73_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_73_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_73_L3_SEL                                                  0
+
+		Configures MIO Pin 73 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180124, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_73_L0_SEL_MASK | IOU_SLCR_MIO_PIN_73_L1_SEL_MASK | IOU_SLCR_MIO_PIN_73_L2_SEL_MASK | IOU_SLCR_MIO_PIN_73_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_73_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_74 @ 0XFF180128

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)
+		PSU_IOU_SLCR_MIO_PIN_74_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[6]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_74_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_74_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_74_L3_SEL                                                  0
+
+		Configures MIO Pin 74 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180128, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_74_L0_SEL_MASK | IOU_SLCR_MIO_PIN_74_L1_SEL_MASK | IOU_SLCR_MIO_PIN_74_L2_SEL_MASK | IOU_SLCR_MIO_PIN_74_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_74_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_75 @ 0XFF18012C

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )
+		PSU_IOU_SLCR_MIO_PIN_75_L0_SEL                                                  1
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[7]- (ULPI data bus)
+		PSU_IOU_SLCR_MIO_PIN_75_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
+		d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_75_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_75_L3_SEL                                                  0
+
+		Configures MIO Pin 75 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF18012C, 0x000000FEU ,0x00000002U)  
+		RegMask = (IOU_SLCR_MIO_PIN_75_L0_SEL_MASK | IOU_SLCR_MIO_PIN_75_L1_SEL_MASK | IOU_SLCR_MIO_PIN_75_L2_SEL_MASK | IOU_SLCR_MIO_PIN_75_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_75_OFFSET ,0x000000FEU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_76 @ 0XFF180130

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
+		_clk_out- (SDSDIO clock) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
+		 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_76_L3_SEL                                                  6
+
+		Configures MIO Pin 76 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180130, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_76_L0_SEL_MASK | IOU_SLCR_MIO_PIN_76_L1_SEL_MASK | IOU_SLCR_MIO_PIN_76_L2_SEL_MASK | IOU_SLCR_MIO_PIN_76_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_76_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_PIN_77 @ 0XFF180134

+
+		Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L0_SEL                                                  0
+
+		Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L1_SEL                                                  0
+
+		Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L2_SEL                                                  0
+
+		Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
+		O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
+		t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used
+		PSU_IOU_SLCR_MIO_PIN_77_L3_SEL                                                  6
+
+		Configures MIO Pin 77 peripheral interface mapping
+		(OFFSET, MASK, VALUE)      (0XFF180134, 0x000000FEU ,0x000000C0U)  
+		RegMask = (IOU_SLCR_MIO_PIN_77_L0_SEL_MASK | IOU_SLCR_MIO_PIN_77_L1_SEL_MASK | IOU_SLCR_MIO_PIN_77_L2_SEL_MASK | IOU_SLCR_MIO_PIN_77_L3_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT
+			| 0x00000006U << IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_PIN_77_OFFSET ,0x000000FEU ,0x000000C0U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI0 @ 0XFF180204

+
+		Master Tri-state Enable for pin 0, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI                                            0
+
+		Master Tri-state Enable for pin 1, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI                                            0
+
+		Master Tri-state Enable for pin 2, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI                                            0
+
+		Master Tri-state Enable for pin 3, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI                                            0
+
+		Master Tri-state Enable for pin 4, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI                                            0
+
+		Master Tri-state Enable for pin 5, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI                                            0
+
+		Master Tri-state Enable for pin 6, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI                                            0
+
+		Master Tri-state Enable for pin 7, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI                                            0
+
+		Master Tri-state Enable for pin 8, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI                                            0
+
+		Master Tri-state Enable for pin 9, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI                                            0
+
+		Master Tri-state Enable for pin 10, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI                                            0
+
+		Master Tri-state Enable for pin 11, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI                                            0
+
+		Master Tri-state Enable for pin 12, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI                                            0
+
+		Master Tri-state Enable for pin 13, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI                                            0
+
+		Master Tri-state Enable for pin 14, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI                                            0
+
+		Master Tri-state Enable for pin 15, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI                                            0
+
+		Master Tri-state Enable for pin 16, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI                                            0
+
+		Master Tri-state Enable for pin 17, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI                                            0
+
+		Master Tri-state Enable for pin 18, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI                                            1
+
+		Master Tri-state Enable for pin 19, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI                                            0
+
+		Master Tri-state Enable for pin 20, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI                                            0
+
+		Master Tri-state Enable for pin 21, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI                                            1
+
+		Master Tri-state Enable for pin 22, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI                                            0
+
+		Master Tri-state Enable for pin 23, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI                                            0
+
+		Master Tri-state Enable for pin 24, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI                                            0
+
+		Master Tri-state Enable for pin 25, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI                                            1
+
+		Master Tri-state Enable for pin 26, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI                                            1
+
+		Master Tri-state Enable for pin 27, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI                                            0
+
+		Master Tri-state Enable for pin 28, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI                                            0
+
+		Master Tri-state Enable for pin 29, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI                                            0
+
+		Master Tri-state Enable for pin 30, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI                                            0
+
+		Master Tri-state Enable for pin 31, active high
+		PSU_IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI                                            0
+
+		MIO pin Tri-state Enables, 31:0
+		(OFFSET, MASK, VALUE)      (0XFF180204, 0xFFFFFFFFU ,0x06240000U)  
+		RegMask = (IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK | IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI0_OFFSET ,0xFFFFFFFFU ,0x06240000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI1 @ 0XFF180208

+
+		Master Tri-state Enable for pin 32, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI                                            0
+
+		Master Tri-state Enable for pin 33, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI                                            0
+
+		Master Tri-state Enable for pin 34, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI                                            0
+
+		Master Tri-state Enable for pin 35, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI                                            0
+
+		Master Tri-state Enable for pin 36, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI                                            0
+
+		Master Tri-state Enable for pin 37, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI                                            0
+
+		Master Tri-state Enable for pin 38, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI                                            0
+
+		Master Tri-state Enable for pin 39, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI                                            0
+
+		Master Tri-state Enable for pin 40, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI                                            0
+
+		Master Tri-state Enable for pin 41, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI                                            0
+
+		Master Tri-state Enable for pin 42, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI                                            0
+
+		Master Tri-state Enable for pin 43, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI                                            0
+
+		Master Tri-state Enable for pin 44, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI                                            1
+
+		Master Tri-state Enable for pin 45, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI                                            1
+
+		Master Tri-state Enable for pin 46, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI                                            0
+
+		Master Tri-state Enable for pin 47, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI                                            0
+
+		Master Tri-state Enable for pin 48, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI                                            0
+
+		Master Tri-state Enable for pin 49, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI                                            0
+
+		Master Tri-state Enable for pin 50, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI                                            0
+
+		Master Tri-state Enable for pin 51, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI                                            0
+
+		Master Tri-state Enable for pin 52, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI                                            1
+
+		Master Tri-state Enable for pin 53, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI                                            1
+
+		Master Tri-state Enable for pin 54, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI                                            0
+
+		Master Tri-state Enable for pin 55, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI                                            1
+
+		Master Tri-state Enable for pin 56, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI                                            0
+
+		Master Tri-state Enable for pin 57, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI                                            0
+
+		Master Tri-state Enable for pin 58, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI                                            0
+
+		Master Tri-state Enable for pin 59, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI                                            0
+
+		Master Tri-state Enable for pin 60, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI                                            0
+
+		Master Tri-state Enable for pin 61, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI                                            0
+
+		Master Tri-state Enable for pin 62, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI                                            0
+
+		Master Tri-state Enable for pin 63, active high
+		PSU_IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI                                            0
+
+		MIO pin Tri-state Enables, 63:32
+		(OFFSET, MASK, VALUE)      (0XFF180208, 0xFFFFFFFFU ,0x00B03000U)  
+		RegMask = (IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK | IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI1_OFFSET ,0xFFFFFFFFU ,0x00B03000U);
+	/*############################################################################################################################ */
+
+		/*Register : MIO_MST_TRI2 @ 0XFF18020C

+
+		Master Tri-state Enable for pin 64, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI                                            0
+
+		Master Tri-state Enable for pin 65, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI                                            0
+
+		Master Tri-state Enable for pin 66, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI                                            0
+
+		Master Tri-state Enable for pin 67, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI                                            0
+
+		Master Tri-state Enable for pin 68, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI                                            0
+
+		Master Tri-state Enable for pin 69, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI                                            0
+
+		Master Tri-state Enable for pin 70, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI                                            1
+
+		Master Tri-state Enable for pin 71, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI                                            1
+
+		Master Tri-state Enable for pin 72, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI                                            1
+
+		Master Tri-state Enable for pin 73, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI                                            1
+
+		Master Tri-state Enable for pin 74, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI                                            1
+
+		Master Tri-state Enable for pin 75, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI                                            1
+
+		Master Tri-state Enable for pin 76, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI                                            0
+
+		Master Tri-state Enable for pin 77, active high
+		PSU_IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI                                            0
+
+		MIO pin Tri-state Enables, 77:64
+		(OFFSET, MASK, VALUE)      (0XFF18020C, 0x00003FFFU ,0x00000FC0U)  
+		RegMask = (IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK | IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT
+			| 0x00000001U << IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_MST_TRI2_OFFSET ,0x00003FFFU ,0x00000FC0U);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl0 @ 0XFF180138

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25                                          1
+
+		Drive0 control to MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF180138, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl1 @ 0XFF18013C

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25                                          1
+
+		Drive1 control to MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF18013C, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl3 @ 0XFF180140

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
+
+		Selects either Schmitt or CMOS input for MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF180140, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl4 @ 0XFF180144

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
+
+		When mio_bank0_pull_enable is set, this selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF180144, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl5 @ 0XFF180148

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25                                     1
+
+		When set, this enables mio_bank0_pullupdown to selects pull up or pull down for MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF180148, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank0_ctrl6 @ 0XFF18014C

+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[0].
+		PSU_IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
+
+		Slew rate control to MIO Bank 0 - control MIO[25:0]
+		(OFFSET, MASK, VALUE)      (0XFF18014C, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK0_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl0 @ 0XFF180154

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25                                          1
+
+		Drive0 control to MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF180154, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl1 @ 0XFF180158

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25                                          1
+
+		Drive1 control to MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF180158, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl3 @ 0XFF18015C

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
+
+		Selects either Schmitt or CMOS input for MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF18015C, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl4 @ 0XFF180160

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
+
+		When mio_bank1_pull_enable is set, this selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF180160, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl5 @ 0XFF180164

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25                                     1
+
+		When set, this enables mio_bank1_pullupdown to selects pull up or pull down for MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF180164, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank1_ctrl6 @ 0XFF180168

+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[26].
+		PSU_IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
+
+		Slew rate control to MIO Bank 1 - control MIO[51:26]
+		(OFFSET, MASK, VALUE)      (0XFF180168, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK1_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl0 @ 0XFF180170

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25                                          1
+
+		Drive0 control to MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF180170, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK | IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL0_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl1 @ 0XFF180174

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9                                           1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24                                          1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25                                          1
+
+		Drive1 control to MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF180174, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK | IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL1_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl3 @ 0XFF180178

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9                                   0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24                                  0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25                                  0
+
+		Selects either Schmitt or CMOS input for MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF180178, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL3_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl4 @ 0XFF18017C

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9                                  1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24                                 1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25                                 1
+
+		When mio_bank2_pull_enable is set, this selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF18017C, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL4_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl5 @ 0XFF180180

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9                                      1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24                                     1
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25                                     1
+
+		When set, this enables mio_bank2_pullupdown to selects pull up or pull down for MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF180180, 0x03FFFFFFU ,0x03FFFFFFU)  
+		RegMask = (IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK | IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT
+			| 0x00000001U << IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL5_OFFSET ,0x03FFFFFFU ,0x03FFFFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : bank2_ctrl6 @ 0XFF180184

+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9                                 0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24                                0
+
+		Each bit applies to a single IO. Bit 0 for MIO[52].
+		PSU_IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25                                0
+
+		Slew rate control to MIO Bank 2 - control MIO[77:52]
+		(OFFSET, MASK, VALUE)      (0XFF180184, 0x03FFFFFFU ,0x00000000U)  
+		RegMask = (IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK | IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT
+			| 0x00000000U << IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_BANK2_CTRL6_OFFSET ,0x03FFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : LOOPBACK
+		/*Register : MIO_LOOPBACK @ 0XFF180200

+
+		I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
+		ts to I2C 0 inputs.
+		PSU_IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1                                        0
+
+		CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
+		.
+		PSU_IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1                                        0
+
+		UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
+		outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.
+		PSU_IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1                                          0
+
+		SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
+		ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.
+		PSU_IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1                                        0
+
+		Loopback function within MIO
+		(OFFSET, MASK, VALUE)      (0XFF180200, 0x0000000FU ,0x00000000U)  
+		RegMask = (IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK | IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK | IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK | IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT
+			| 0x00000000U << IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_MIO_LOOPBACK_OFFSET ,0x0000000FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_peripherals_init_data() {
+		// : RESET BLOCKS
+		// : ENET
+		/*Register : RST_LPD_IOU0 @ 0XFF5E0230

+
+		GEM 3 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0
+
+		Software controlled reset for the GEMs
+		(OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : QSPI
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_QSPI_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000001U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000001U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : NAND
+		// : USB
+		/*Register : RST_LPD_TOP @ 0XFF5E023C

+
+		USB 0 reset for control registers
+		PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0
+
+		USB 0 sleep circuit reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0
+
+		USB 0 reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0
+
+		Software control register for the LPD block.
+		(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : FPD RESET
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		PCIE config reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0
+
+		PCIE control block level reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0
+
+		PCIE bridge block level reset (AXI interface)
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0
+
+		Display Port block level reset (includes DPDMA)
+		PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0
+
+		FPD WDT reset
+		PSU_CRF_APB_RST_FPD_TOP_SWDT_RESET                                              0
+
+		GDMA block level reset
+		PSU_CRF_APB_RST_FPD_TOP_GDMA_RESET                                              0
+
+		Pixel Processor (submodule of GPU) block level reset
+		PSU_CRF_APB_RST_FPD_TOP_GPU_PP0_RESET                                           0
+
+		Pixel Processor (submodule of GPU) block level reset
+		PSU_CRF_APB_RST_FPD_TOP_GPU_PP1_RESET                                           0
+
+		GPU block level reset
+		PSU_CRF_APB_RST_FPD_TOP_GPU_RESET                                               0
+
+		GT block level reset
+		PSU_CRF_APB_RST_FPD_TOP_GT_RESET                                                0
+
+		Sata block level reset
+		PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000F807EU ,0x00000000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK | CRF_APB_RST_FPD_TOP_DP_RESET_MASK | CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK | CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK | CRF_APB_RST_FPD_TOP_GPU_RESET_MASK | CRF_APB_RST_FPD_TOP_GT_RESET_MASK | CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000F807EU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : SD
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SDIO1_RESET                                            0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000040U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000040U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : CTRL_REG_SD @ 0XFF180310

+
+		SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled
+		PSU_IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL                                           0
+
+		SD eMMC selection
+		(OFFSET, MASK, VALUE)      (0XFF180310, 0x00008000U ,0x00000000U)  
+		RegMask = (IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_CTRL_REG_SD_OFFSET ,0x00008000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : SD_CONFIG_REG2 @ 0XFF180320

+
+		Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE                                        0
+
+		1.8V Support 1: 1.8V supported 0: 1.8V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V                                            0
+
+		3.0V Support 1: 3.0V supported 0: 3.0V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V                                            0
+
+		3.3V Support 1: 3.3V supported 0: 3.3V not supported support
+		PSU_IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V                                            1
+
+		SD Config Register 2
+		(OFFSET, MASK, VALUE)      (0XFF180320, 0x33800000U ,0x00800000U)  
+		RegMask = (IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK | IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK |  0 );
+
+		RegVal = ((0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT
+			| 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT
+			| 0x00000000U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT
+			| 0x00000001U << IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG2_OFFSET ,0x33800000U ,0x00800000U);
+	/*############################################################################################################################ */
+
+		// : SD1 BASE CLOCK
+		/*Register : SD_CONFIG_REG1 @ 0XFF18031C

+
+		Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.
+		PSU_IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK                                         0xc7
+
+		SD Config Register 1
+		(OFFSET, MASK, VALUE)      (0XFF18031C, 0x7F800000U ,0x63800000U)  
+		RegMask = (IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK |  0 );
+
+		RegVal = ((0x000000C7U << IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (IOU_SLCR_SD_CONFIG_REG1_OFFSET ,0x7F800000U ,0x63800000U);
+	/*############################################################################################################################ */
+
+		// : CAN
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_CAN1_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000100U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000100U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : I2C
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_I2C0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_I2C1_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000600U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK | CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000600U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : SWDT
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_SWDT_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00008000U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00008000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : SPI
+		// : TTC
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC0_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC1_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC2_RESET                                             0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_TTC3_RESET                                             0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00007800U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK | CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00007800U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : UART
+		/*Register : RST_LPD_IOU2 @ 0XFF5E0238

+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_UART0_RESET                                            0
+
+		Block level reset
+		PSU_CRL_APB_RST_LPD_IOU2_UART1_RESET                                            0
+
+		Software control register for the IOU block. Each bit will cause a singlerperipheral or part of the peripheral to be reset.
+		(OFFSET, MASK, VALUE)      (0XFF5E0238, 0x00000006U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK | CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU2_OFFSET ,0x00000006U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : UART BAUD RATE
+		/*Register : Baud_rate_divider_reg0 @ 0XFF000034

+
+		Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+		PSU_UART0_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
+
+		Baud Rate Divider Register
+		(OFFSET, MASK, VALUE)      (0XFF000034, 0x000000FFU ,0x00000005U)  
+		RegMask = (UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
+
+		RegVal = ((0x00000005U << UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART0_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U);
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_gen_reg0 @ 0XFF000018

+
+		Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+		PSU_UART0_BAUD_RATE_GEN_REG0_CD                                                 0x8f
+
+		Baud Rate Generator Register.
+		(OFFSET, MASK, VALUE)      (0XFF000018, 0x0000FFFFU ,0x0000008FU)  
+		RegMask = (UART0_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
+
+		RegVal = ((0x0000008FU << UART0_BAUD_RATE_GEN_REG0_CD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART0_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU);
+	/*############################################################################################################################ */
+
+		/*Register : Control_reg0 @ 0XFF000000

+
+		Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+		PSU_UART0_CONTROL_REG0_STPBRK                                                   0x0
+
+		Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+		PSU_UART0_CONTROL_REG0_STTBRK                                                   0x0
+
+		Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.
+		PSU_UART0_CONTROL_REG0_RSTTO                                                    0x0
+
+		Transmit disable: 0: enable transmitter 1: disable transmitter
+		PSU_UART0_CONTROL_REG0_TXDIS                                                    0x0
+
+		Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+		PSU_UART0_CONTROL_REG0_TXEN                                                     0x1
+
+		Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+		PSU_UART0_CONTROL_REG0_RXDIS                                                    0x0
+
+		Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+		PSU_UART0_CONTROL_REG0_RXEN                                                     0x1
+
+		Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.
+		PSU_UART0_CONTROL_REG0_TXRES                                                    0x1
+
+		Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.
+		PSU_UART0_CONTROL_REG0_RXRES                                                    0x1
+
+		UART Control Register
+		(OFFSET, MASK, VALUE)      (0XFF000000, 0x000001FFU ,0x00000017U)  
+		RegMask = (UART0_CONTROL_REG0_STPBRK_MASK | UART0_CONTROL_REG0_STTBRK_MASK | UART0_CONTROL_REG0_RSTTO_MASK | UART0_CONTROL_REG0_TXDIS_MASK | UART0_CONTROL_REG0_TXEN_MASK | UART0_CONTROL_REG0_RXDIS_MASK | UART0_CONTROL_REG0_RXEN_MASK | UART0_CONTROL_REG0_TXRES_MASK | UART0_CONTROL_REG0_RXRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << UART0_CONTROL_REG0_STPBRK_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_STTBRK_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_RSTTO_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_TXDIS_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_TXEN_SHIFT
+			| 0x00000000U << UART0_CONTROL_REG0_RXDIS_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_RXEN_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_TXRES_SHIFT
+			| 0x00000001U << UART0_CONTROL_REG0_RXRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART0_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U);
+	/*############################################################################################################################ */
+
+		/*Register : mode_reg0 @ 0XFF000004

+
+		Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+		PSU_UART0_MODE_REG0_CHMODE                                                      0x0
+
+		Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved
+		PSU_UART0_MODE_REG0_NBSTOP                                                      0x0
+
+		Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+		PSU_UART0_MODE_REG0_PAR                                                         0x4
+
+		Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+		PSU_UART0_MODE_REG0_CHRL                                                        0x0
+
+		Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8
+		PSU_UART0_MODE_REG0_CLKS                                                        0x0
+
+		UART Mode Register
+		(OFFSET, MASK, VALUE)      (0XFF000004, 0x000003FFU ,0x00000020U)  
+		RegMask = (UART0_MODE_REG0_CHMODE_MASK | UART0_MODE_REG0_NBSTOP_MASK | UART0_MODE_REG0_PAR_MASK | UART0_MODE_REG0_CHRL_MASK | UART0_MODE_REG0_CLKS_MASK |  0 );
+
+		RegVal = ((0x00000000U << UART0_MODE_REG0_CHMODE_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_NBSTOP_SHIFT
+			| 0x00000004U << UART0_MODE_REG0_PAR_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_CHRL_SHIFT
+			| 0x00000000U << UART0_MODE_REG0_CLKS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART0_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U);
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_divider_reg0 @ 0XFF010034

+
+		Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate
+		PSU_UART1_BAUD_RATE_DIVIDER_REG0_BDIV                                           0x5
+
+		Baud Rate Divider Register
+		(OFFSET, MASK, VALUE)      (0XFF010034, 0x000000FFU ,0x00000005U)  
+		RegMask = (UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK |  0 );
+
+		RegVal = ((0x00000005U << UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART1_BAUD_RATE_DIVIDER_REG0_OFFSET ,0x000000FFU ,0x00000005U);
+	/*############################################################################################################################ */
+
+		/*Register : Baud_rate_gen_reg0 @ 0XFF010018

+
+		Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample
+		PSU_UART1_BAUD_RATE_GEN_REG0_CD                                                 0x8f
+
+		Baud Rate Generator Register.
+		(OFFSET, MASK, VALUE)      (0XFF010018, 0x0000FFFFU ,0x0000008FU)  
+		RegMask = (UART1_BAUD_RATE_GEN_REG0_CD_MASK |  0 );
+
+		RegVal = ((0x0000008FU << UART1_BAUD_RATE_GEN_REG0_CD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART1_BAUD_RATE_GEN_REG0_OFFSET ,0x0000FFFFU ,0x0000008FU);
+	/*############################################################################################################################ */
+
+		/*Register : Control_reg0 @ 0XFF010000

+
+		Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.
+		PSU_UART1_CONTROL_REG0_STPBRK                                                   0x0
+
+		Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.
+		PSU_UART1_CONTROL_REG0_STTBRK                                                   0x0
+
+		Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.
+		PSU_UART1_CONTROL_REG0_RSTTO                                                    0x0
+
+		Transmit disable: 0: enable transmitter 1: disable transmitter
+		PSU_UART1_CONTROL_REG0_TXDIS                                                    0x0
+
+		Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.
+		PSU_UART1_CONTROL_REG0_TXEN                                                     0x1
+
+		Receive disable: 0: enable 1: disable, regardless of the value of RXEN
+		PSU_UART1_CONTROL_REG0_RXDIS                                                    0x0
+
+		Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.
+		PSU_UART1_CONTROL_REG0_RXEN                                                     0x1
+
+		Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.
+		PSU_UART1_CONTROL_REG0_TXRES                                                    0x1
+
+		Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.
+		PSU_UART1_CONTROL_REG0_RXRES                                                    0x1
+
+		UART Control Register
+		(OFFSET, MASK, VALUE)      (0XFF010000, 0x000001FFU ,0x00000017U)  
+		RegMask = (UART1_CONTROL_REG0_STPBRK_MASK | UART1_CONTROL_REG0_STTBRK_MASK | UART1_CONTROL_REG0_RSTTO_MASK | UART1_CONTROL_REG0_TXDIS_MASK | UART1_CONTROL_REG0_TXEN_MASK | UART1_CONTROL_REG0_RXDIS_MASK | UART1_CONTROL_REG0_RXEN_MASK | UART1_CONTROL_REG0_TXRES_MASK | UART1_CONTROL_REG0_RXRES_MASK |  0 );
+
+		RegVal = ((0x00000000U << UART1_CONTROL_REG0_STPBRK_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_STTBRK_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_RSTTO_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_TXDIS_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_TXEN_SHIFT
+			| 0x00000000U << UART1_CONTROL_REG0_RXDIS_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_RXEN_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_TXRES_SHIFT
+			| 0x00000001U << UART1_CONTROL_REG0_RXRES_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART1_CONTROL_REG0_OFFSET ,0x000001FFU ,0x00000017U);
+	/*############################################################################################################################ */
+
+		/*Register : mode_reg0 @ 0XFF010004

+
+		Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback
+		PSU_UART1_MODE_REG0_CHMODE                                                      0x0
+
+		Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved
+		PSU_UART1_MODE_REG0_NBSTOP                                                      0x0
+
+		Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity
+		PSU_UART1_MODE_REG0_PAR                                                         0x4
+
+		Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits
+		PSU_UART1_MODE_REG0_CHRL                                                        0x0
+
+		Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8
+		PSU_UART1_MODE_REG0_CLKS                                                        0x0
+
+		UART Mode Register
+		(OFFSET, MASK, VALUE)      (0XFF010004, 0x000003FFU ,0x00000020U)  
+		RegMask = (UART1_MODE_REG0_CHMODE_MASK | UART1_MODE_REG0_NBSTOP_MASK | UART1_MODE_REG0_PAR_MASK | UART1_MODE_REG0_CHRL_MASK | UART1_MODE_REG0_CLKS_MASK |  0 );
+
+		RegVal = ((0x00000000U << UART1_MODE_REG0_CHMODE_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_NBSTOP_SHIFT
+			| 0x00000004U << UART1_MODE_REG0_PAR_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_CHRL_SHIFT
+			| 0x00000000U << UART1_MODE_REG0_CLKS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (UART1_MODE_REG0_OFFSET ,0x000003FFU ,0x00000020U);
+	/*############################################################################################################################ */
+
+		// : GPIO
+		// : ADMA TZ
+		/*Register : slcr_adma @ 0XFF4B0024

+
+		TrustZone Classification for ADMA
+		PSU_LPD_SLCR_SECURE_SLCR_ADMA_TZ                                                0XFF
+
+		RPU TrustZone settings
+		(OFFSET, MASK, VALUE)      (0XFF4B0024, 0x000000FFU ,0x000000FFU)  
+		RegMask = (LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK |  0 );
+
+		RegVal = ((0x000000FFU << LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (LPD_SLCR_SECURE_SLCR_ADMA_OFFSET ,0x000000FFU ,0x000000FFU);
+	/*############################################################################################################################ */
+
+		// : CSU TAMPERING
+		// : CSU TAMPER STATUS
+		/*Register : tamper_status @ 0XFFCA5000

+
+		CSU regsiter
+		PSU_CSU_TAMPER_STATUS_TAMPER_0                                                  0
+
+		External MIO
+		PSU_CSU_TAMPER_STATUS_TAMPER_1                                                  0
+
+		JTAG toggle detect
+		PSU_CSU_TAMPER_STATUS_TAMPER_2                                                  0
+
+		PL SEU error
+		PSU_CSU_TAMPER_STATUS_TAMPER_3                                                  0
+
+		AMS over temperature alarm for LPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_4                                                  0
+
+		AMS over temperature alarm for APU
+		PSU_CSU_TAMPER_STATUS_TAMPER_5                                                  0
+
+		AMS voltage alarm for VCCPINT_FPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_6                                                  0
+
+		AMS voltage alarm for VCCPINT_LPD
+		PSU_CSU_TAMPER_STATUS_TAMPER_7                                                  0
+
+		AMS voltage alarm for VCCPAUX
+		PSU_CSU_TAMPER_STATUS_TAMPER_8                                                  0
+
+		AMS voltage alarm for DDRPHY
+		PSU_CSU_TAMPER_STATUS_TAMPER_9                                                  0
+
+		AMS voltage alarm for PSIO bank 0/1/2
+		PSU_CSU_TAMPER_STATUS_TAMPER_10                                                 0
+
+		AMS voltage alarm for PSIO bank 3 (dedicated pins)
+		PSU_CSU_TAMPER_STATUS_TAMPER_11                                                 0
+
+		AMS voltaage alarm for GT
+		PSU_CSU_TAMPER_STATUS_TAMPER_12                                                 0
+
+		Tamper Response Status
+		(OFFSET, MASK, VALUE)      (0XFFCA5000, 0x00001FFFU ,0x00000000U)  
+		RegMask = (CSU_TAMPER_STATUS_TAMPER_0_MASK | CSU_TAMPER_STATUS_TAMPER_1_MASK | CSU_TAMPER_STATUS_TAMPER_2_MASK | CSU_TAMPER_STATUS_TAMPER_3_MASK | CSU_TAMPER_STATUS_TAMPER_4_MASK | CSU_TAMPER_STATUS_TAMPER_5_MASK | CSU_TAMPER_STATUS_TAMPER_6_MASK | CSU_TAMPER_STATUS_TAMPER_7_MASK | CSU_TAMPER_STATUS_TAMPER_8_MASK | CSU_TAMPER_STATUS_TAMPER_9_MASK | CSU_TAMPER_STATUS_TAMPER_10_MASK | CSU_TAMPER_STATUS_TAMPER_11_MASK | CSU_TAMPER_STATUS_TAMPER_12_MASK |  0 );
+
+		RegVal = ((0x00000000U << CSU_TAMPER_STATUS_TAMPER_0_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_1_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_2_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_3_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_4_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_5_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_6_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_7_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_8_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_9_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_10_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_11_SHIFT
+			| 0x00000000U << CSU_TAMPER_STATUS_TAMPER_12_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CSU_TAMPER_STATUS_OFFSET ,0x00001FFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CSU TAMPER RESPONSE
+		// : AFIFM INTERFACE WIDTH
+		// : CPU QOS DEFAULT
+		/*Register : ACE_CTRL @ 0XFD5C0060

+
+		Set ACE outgoing AWQOS value
+		PSU_APU_ACE_CTRL_AWQOS                                                          0X0
+
+		Set ACE outgoing ARQOS value
+		PSU_APU_ACE_CTRL_ARQOS                                                          0X0
+
+		ACE Control Register
+		(OFFSET, MASK, VALUE)      (0XFD5C0060, 0x000F000FU ,0x00000000U)  
+		RegMask = (APU_ACE_CTRL_AWQOS_MASK | APU_ACE_CTRL_ARQOS_MASK |  0 );
+
+		RegVal = ((0x00000000U << APU_ACE_CTRL_AWQOS_SHIFT
+			| 0x00000000U << APU_ACE_CTRL_ARQOS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (APU_ACE_CTRL_OFFSET ,0x000F000FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : ENABLES RTC SWITCH TO BATTERY WHEN VCC_PSAUX IS NOT AVAILABLE
+		/*Register : CONTROL @ 0XFFA60040

+
+		Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from 
+		he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
+		pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
+		g a 0 to this bit.
+		PSU_RTC_CONTROL_BATTERY_DISABLE                                                 0X1
+
+		This register controls various functionalities within the RTC
+		(OFFSET, MASK, VALUE)      (0XFFA60040, 0x80000000U ,0x80000000U)  
+		RegMask = (RTC_CONTROL_BATTERY_DISABLE_MASK |  0 );
+
+		RegVal = ((0x00000001U << RTC_CONTROL_BATTERY_DISABLE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (RTC_CONTROL_OFFSET ,0x80000000U ,0x80000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_post_config_data() {
+		// : POST_CONFIG
+
+  return 1;
+}
+unsigned long psu_peripherals_powerdwn_data() {
+		// : POWER DOWN REQUEST INTERRUPT ENABLE
+		// : POWER DOWN TRIGGER
+
+  return 1;
+}
+unsigned long psu_serdes_init_data() {
+		// : SERDES INITIALIZATION
+		// : GT REFERENCE CLOCK SOURCE SELECTION
+		/*Register : PLL_REF_SEL0 @ 0XFD410000

+
+		PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		PSU_SERDES_PLL_REF_SEL0_PLLREFSEL0                                              0xD
+
+		PLL0 Reference Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD410000, 0x0000001FU ,0x0000000DU)  
+		RegMask = (SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK |  0 );
+
+		RegVal = ((0x0000000DU << SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_PLL_REF_SEL0_OFFSET ,0x0000001FU ,0x0000000DU);
+	/*############################################################################################################################ */
+
+		/*Register : PLL_REF_SEL1 @ 0XFD410004

+
+		PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		PSU_SERDES_PLL_REF_SEL1_PLLREFSEL1                                              0x9
+
+		PLL1 Reference Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD410004, 0x0000001FU ,0x00000009U)  
+		RegMask = (SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK |  0 );
+
+		RegVal = ((0x00000009U << SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_PLL_REF_SEL1_OFFSET ,0x0000001FU ,0x00000009U);
+	/*############################################################################################################################ */
+
+		/*Register : PLL_REF_SEL2 @ 0XFD410008

+
+		PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		PSU_SERDES_PLL_REF_SEL2_PLLREFSEL2                                              0x8
+
+		PLL2 Reference Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD410008, 0x0000001FU ,0x00000008U)  
+		RegMask = (SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK |  0 );
+
+		RegVal = ((0x00000008U << SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_PLL_REF_SEL2_OFFSET ,0x0000001FU ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : PLL_REF_SEL3 @ 0XFD41000C

+
+		PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved
+		PSU_SERDES_PLL_REF_SEL3_PLLREFSEL3                                              0xF
+
+		PLL3 Reference Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD41000C, 0x0000001FU ,0x0000000FU)  
+		RegMask = (SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK |  0 );
+
+		RegVal = ((0x0000000FU << SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_PLL_REF_SEL3_OFFSET ,0x0000001FU ,0x0000000FU);
+	/*############################################################################################################################ */
+
+		// : GT REFERENCE CLOCK FREQUENCY SELECTION
+		/*Register : L0_L0_REF_CLK_SEL @ 0XFD402860

+
+		Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.
+		PSU_SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL                                 0x1
+
+		Lane0 Ref Clock Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD402860, 0x00000080U ,0x00000080U)  
+		RegMask = (SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L0_L0_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
+	/*############################################################################################################################ */
+
+		/*Register : L0_L1_REF_CLK_SEL @ 0XFD402864

+
+		Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.
+		PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL                                 0x0
+
+		Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network
+		PSU_SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3                                   0x1
+
+		Lane1 Ref Clock Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD402864, 0x00000088U ,0x00000008U)  
+		RegMask = (SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK | SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT
+			| 0x00000001U << SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L0_L1_REF_CLK_SEL_OFFSET ,0x00000088U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		/*Register : L0_L2_REF_CLK_SEL @ 0XFD402868

+
+		Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.
+		PSU_SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL                                 0x1
+
+		Lane2 Ref Clock Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD402868, 0x00000080U ,0x00000080U)  
+		RegMask = (SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L0_L2_REF_CLK_SEL_OFFSET ,0x00000080U ,0x00000080U);
+	/*############################################################################################################################ */
+
+		/*Register : L0_L3_REF_CLK_SEL @ 0XFD40286C

+
+		Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.
+		PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL                                 0x0
+
+		Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network
+		PSU_SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1                                   0x1
+
+		Lane3 Ref Clock Selection Register
+		(OFFSET, MASK, VALUE)      (0XFD40286C, 0x00000082U ,0x00000002U)  
+		RegMask = (SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK | SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT
+			| 0x00000001U << SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L0_L3_REF_CLK_SEL_OFFSET ,0x00000082U ,0x00000002U);
+	/*############################################################################################################################ */
+
+		// : ENABLE SPREAD SPECTRUM
+		/*Register : L2_TM_PLL_DIG_37 @ 0XFD40A094

+
+		Enable/Disable coarse code satureation limiting logic
+		PSU_SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION                         0x1
+
+		Test mode register 37
+		(OFFSET, MASK, VALUE)      (0XFD40A094, 0x00000010U ,0x00000010U)  
+		RegMask = (SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_TM_PLL_DIG_37_OFFSET ,0x00000010U ,0x00000010U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEPS_0_LSB @ 0XFD40A368

+
+		Spread Spectrum No of Steps [7:0]
+		PSU_SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x38
+
+		Spread Spectrum No of Steps bits 7:0
+		(OFFSET, MASK, VALUE)      (0XFD40A368, 0x000000FFU ,0x00000038U)  
+		RegMask = (SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
+
+		RegVal = ((0x00000038U << SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000038U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEPS_1_MSB @ 0XFD40A36C

+
+		Spread Spectrum No of Steps [10:8]
+		PSU_SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x03
+
+		Spread Spectrum No of Steps bits 10:8
+		(OFFSET, MASK, VALUE)      (0XFD40A36C, 0x00000007U ,0x00000003U)  
+		RegMask = (SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
+
+		RegVal = ((0x00000003U << SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000003U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEPS_0_LSB @ 0XFD40E368

+
+		Spread Spectrum No of Steps [7:0]
+		PSU_SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x0
+
+		Spread Spectrum No of Steps bits 7:0
+		(OFFSET, MASK, VALUE)      (0XFD40E368, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEPS_1_MSB @ 0XFD40E36C

+
+		Spread Spectrum No of Steps [10:8]
+		PSU_SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x0
+
+		Spread Spectrum No of Steps bits 10:8
+		(OFFSET, MASK, VALUE)      (0XFD40E36C, 0x00000007U ,0x00000000U)  
+		RegMask = (SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEPS_0_LSB @ 0XFD406368

+
+		Spread Spectrum No of Steps [7:0]
+		PSU_SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB                          0x0
+
+		Spread Spectrum No of Steps bits 7:0
+		(OFFSET, MASK, VALUE)      (0XFD406368, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEPS_1_MSB @ 0XFD40636C

+
+		Spread Spectrum No of Steps [10:8]
+		PSU_SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB                          0x0
+
+		Spread Spectrum No of Steps bits 10:8
+		(OFFSET, MASK, VALUE)      (0XFD40636C, 0x00000007U ,0x00000000U)  
+		RegMask = (SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET ,0x00000007U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEP_SIZE_0_LSB @ 0XFD406370

+
+		Step Size for Spread Spectrum [7:0]
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0x0
+
+		Step Size for Spread Spectrum LSB
+		(OFFSET, MASK, VALUE)      (0XFD406370, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEP_SIZE_1 @ 0XFD406374

+
+		Step Size for Spread Spectrum [15:8]
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x0
+
+		Step Size for Spread Spectrum 1
+		(OFFSET, MASK, VALUE)      (0XFD406374, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEP_SIZE_2 @ 0XFD406378

+
+		Step Size for Spread Spectrum [23:16]
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x0
+
+		Step Size for Spread Spectrum 2
+		(OFFSET, MASK, VALUE)      (0XFD406378, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40637C

+
+		Step Size for Spread Spectrum [25:24]
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
+
+		Enable/Disable test mode force on SS step size
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
+
+		Enable/Disable test mode force on SS no of steps
+		PSU_SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
+
+		Enable force on enable Spread Spectrum
+		(OFFSET, MASK, VALUE)      (0XFD40637C, 0x00000033U ,0x00000030U)  
+		RegMask = (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+			| 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+			| 0x00000001U << SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40A370

+
+		Step Size for Spread Spectrum [7:0]
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0xF4
+
+		Step Size for Spread Spectrum LSB
+		(OFFSET, MASK, VALUE)      (0XFD40A370, 0x000000FFU ,0x000000F4U)  
+		RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
+
+		RegVal = ((0x000000F4U << SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x000000F4U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEP_SIZE_1 @ 0XFD40A374

+
+		Step Size for Spread Spectrum [15:8]
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x31
+
+		Step Size for Spread Spectrum 1
+		(OFFSET, MASK, VALUE)      (0XFD40A374, 0x000000FFU ,0x00000031U)  
+		RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
+
+		RegVal = ((0x00000031U << SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000031U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEP_SIZE_2 @ 0XFD40A378

+
+		Step Size for Spread Spectrum [23:16]
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x2
+
+		Step Size for Spread Spectrum 2
+		(OFFSET, MASK, VALUE)      (0XFD40A378, 0x000000FFU ,0x00000002U)  
+		RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
+
+		RegVal = ((0x00000002U << SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40A37C

+
+		Step Size for Spread Spectrum [25:24]
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
+
+		Enable/Disable test mode force on SS step size
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
+
+		Enable/Disable test mode force on SS no of steps
+		PSU_SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
+
+		Enable force on enable Spread Spectrum
+		(OFFSET, MASK, VALUE)      (0XFD40A37C, 0x00000033U ,0x00000030U)  
+		RegMask = (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+			| 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+			| 0x00000001U << SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x00000033U ,0x00000030U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEP_SIZE_0_LSB @ 0XFD40E370

+
+		Step Size for Spread Spectrum [7:0]
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB                         0x0
+
+		Step Size for Spread Spectrum LSB
+		(OFFSET, MASK, VALUE)      (0XFD40E370, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEP_SIZE_1 @ 0XFD40E374

+
+		Step Size for Spread Spectrum [15:8]
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1                                 0x0
+
+		Step Size for Spread Spectrum 1
+		(OFFSET, MASK, VALUE)      (0XFD40E374, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEP_SIZE_2 @ 0XFD40E378

+
+		Step Size for Spread Spectrum [23:16]
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2                                 0x0
+
+		Step Size for Spread Spectrum 2
+		(OFFSET, MASK, VALUE)      (0XFD40E378, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_SS_STEP_SIZE_3_MSB @ 0XFD40E37C

+
+		Step Size for Spread Spectrum [25:24]
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB                         0x0
+
+		Enable/Disable test mode force on SS step size
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE                         0x1
+
+		Enable/Disable test mode force on SS no of steps
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS                      0x1
+
+		Enable test mode forcing on enable Spread Spectrum
+		PSU_SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS                             0x1
+
+		Enable force on enable Spread Spectrum
+		(OFFSET, MASK, VALUE)      (0XFD40E37C, 0x000000B3U ,0x000000B0U)  
+		RegMask = (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK | SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT
+			| 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT
+			| 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT
+			| 0x00000001U << SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET ,0x000000B3U ,0x000000B0U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_TM_DIG_6 @ 0XFD40906C

+
+		Bypass Descrambler
+		PSU_SERDES_L2_TM_DIG_6_BYPASS_DESCRAM                                           0x1
+
+		Enable Bypass for <1> TM_DIG_CTRL_6
+		PSU_SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
+
+		Data path test modes in decoder and descram
+		(OFFSET, MASK, VALUE)      (0XFD40906C, 0x00000003U ,0x00000003U)  
+		RegMask = (SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT
+			| 0x00000001U << SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_TM_DIG_6_OFFSET ,0x00000003U ,0x00000003U);
+	/*############################################################################################################################ */
+
+		/*Register : L2_TX_DIG_TM_61 @ 0XFD4080F4

+
+		Bypass scrambler signal
+		PSU_SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
+
+		Enable/disable scrambler bypass signal
+		PSU_SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
+
+		MPHY PLL Gear and bypass scrambler
+		(OFFSET, MASK, VALUE)      (0XFD4080F4, 0x00000003U ,0x00000003U)  
+		RegMask = (SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
+			| 0x00000001U << SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L2_TX_DIG_TM_61_OFFSET ,0x00000003U ,0x00000003U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_PLL_FBDIV_FRAC_3_MSB @ 0XFD40E360

+
+		Enable test mode force on fractional mode enable
+		PSU_SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC                             0x1
+
+		Fractional feedback division control and fractional value for feedback division bits 26:24
+		(OFFSET, MASK, VALUE)      (0XFD40E360, 0x00000040U ,0x00000040U)  
+		RegMask = (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET ,0x00000040U ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : L3_TM_DIG_6 @ 0XFD40D06C

+
+		Bypass 8b10b decoder
+		PSU_SERDES_L3_TM_DIG_6_BYPASS_DECODER                                           0x1
+
+		Enable Bypass for <3> TM_DIG_CTRL_6
+		PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC                                         0x1
+
+		Bypass Descrambler
+		PSU_SERDES_L3_TM_DIG_6_BYPASS_DESCRAM                                           0x1
+
+		Enable Bypass for <1> TM_DIG_CTRL_6
+		PSU_SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM                                     0x1
+
+		Data path test modes in decoder and descram
+		(OFFSET, MASK, VALUE)      (0XFD40D06C, 0x0000000FU ,0x0000000FU)  
+		RegMask = (SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK | SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK | SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT
+			| 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT
+			| 0x00000001U << SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT
+			| 0x00000001U << SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_TM_DIG_6_OFFSET ,0x0000000FU ,0x0000000FU);
+	/*############################################################################################################################ */
+
+		/*Register : L3_TX_DIG_TM_61 @ 0XFD40C0F4

+
+		Enable/disable encoder bypass signal
+		PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_ENC                                           0x1
+
+		Bypass scrambler signal
+		PSU_SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM                                         0x1
+
+		Enable/disable scrambler bypass signal
+		PSU_SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM                                   0x1
+
+		MPHY PLL Gear and bypass scrambler
+		(OFFSET, MASK, VALUE)      (0XFD40C0F4, 0x0000000BU ,0x0000000BU)  
+		RegMask = (SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK | SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK | SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT
+			| 0x00000001U << SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT
+			| 0x00000001U << SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_TX_DIG_TM_61_OFFSET ,0x0000000BU ,0x0000000BU);
+	/*############################################################################################################################ */
+
+		/*Register : L3_TXPMA_ST_0 @ 0XFD40CB00

+
+		PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY
+		PSU_SERDES_L3_TXPMA_ST_0_TX_PHY_MODE                                            0x21
+
+		Opmode Info
+		(OFFSET, MASK, VALUE)      (0XFD40CB00, 0x000000F0U ,0x000000F0U)  
+		RegMask = (SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK |  0 );
+
+		RegVal = ((0x00000021U << SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L3_TXPMA_ST_0_OFFSET ,0x000000F0U ,0x000000F0U);
+	/*############################################################################################################################ */
+
+		// : GT LANE SETTINGS
+		/*Register : ICM_CFG0 @ 0XFD410010

+
+		Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
+		, 7 - Unused
+		PSU_SERDES_ICM_CFG0_L0_ICM_CFG                                                  1
+
+		Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
+		 7 - Unused
+		PSU_SERDES_ICM_CFG0_L1_ICM_CFG                                                  4
+
+		ICM Configuration Register 0
+		(OFFSET, MASK, VALUE)      (0XFD410010, 0x00000077U ,0x00000041U)  
+		RegMask = (SERDES_ICM_CFG0_L0_ICM_CFG_MASK | SERDES_ICM_CFG0_L1_ICM_CFG_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT
+			| 0x00000004U << SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_ICM_CFG0_OFFSET ,0x00000077U ,0x00000041U);
+	/*############################################################################################################################ */
+
+		/*Register : ICM_CFG1 @ 0XFD410014

+
+		Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
+		 7 - Unused
+		PSU_SERDES_ICM_CFG1_L2_ICM_CFG                                                  3
+
+		Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
+		 7 - Unused
+		PSU_SERDES_ICM_CFG1_L3_ICM_CFG                                                  2
+
+		ICM Configuration Register 1
+		(OFFSET, MASK, VALUE)      (0XFD410014, 0x00000077U ,0x00000023U)  
+		RegMask = (SERDES_ICM_CFG1_L2_ICM_CFG_MASK | SERDES_ICM_CFG1_L3_ICM_CFG_MASK |  0 );
+
+		RegVal = ((0x00000003U << SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT
+			| 0x00000002U << SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_ICM_CFG1_OFFSET ,0x00000077U ,0x00000023U);
+	/*############################################################################################################################ */
+
+		// : CHECKING PLL LOCK
+		// : ENABLE SERIAL DATA MUX DEEMPH
+		/*Register : L1_TXPMD_TM_45 @ 0XFD404CB4

+
+		Enable/disable DP post2 path
+		PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH                         0x1
+
+		Override enable/disable of DP post2 path
+		PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH                    0x1
+
+		Override enable/disable of DP post1 path
+		PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH                    0x1
+
+		Enable/disable DP main path
+		PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH                          0x1
+
+		Override enable/disable of DP main path
+		PSU_SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH                     0x1
+
+		Post or pre or main DP path selection
+		(OFFSET, MASK, VALUE)      (0XFD404CB4, 0x00000037U ,0x00000037U)  
+		RegMask = (SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK | SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT
+			| 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT
+			| 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT
+			| 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT
+			| 0x00000001U << SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_TXPMD_TM_45_OFFSET ,0x00000037U ,0x00000037U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_TX_ANA_TM_118 @ 0XFD4041D8

+
+		Test register force for enabling/disablign TX deemphasis bits <17:0>
+		PSU_SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0                                0x1
+
+		Enable Override of TX deemphasis
+		(OFFSET, MASK, VALUE)      (0XFD4041D8, 0x00000001U ,0x00000001U)  
+		RegMask = (SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK |  0 );
+
+		RegVal = ((0x00000001U << SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_TX_ANA_TM_118_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : ENABLE PRE EMPHAIS AND VOLTAGE SWING
+		/*Register : L1_TXPMD_TM_48 @ 0XFD404CC0

+
+		Margining factor value
+		PSU_SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR                         0
+
+		Margining factor
+		(OFFSET, MASK, VALUE)      (0XFD404CC0, 0x0000001FU ,0x00000000U)  
+		RegMask = (SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_TXPMD_TM_48_OFFSET ,0x0000001FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : L1_TX_ANA_TM_18 @ 0XFD404048

+
+		pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved
+		PSU_SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0                                   0
+
+		Override for PIPE TX de-emphasis
+		(OFFSET, MASK, VALUE)      (0XFD404048, 0x000000FFU ,0x00000000U)  
+		RegMask = (SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK |  0 );
+
+		RegVal = ((0x00000000U << SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SERDES_L1_TX_ANA_TM_18_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_resetout_init_data() {
+		// : TAKING SERDES PERIPHERAL OUT OF RESET RESET
+		// : PUTTING USB0 IN RESET
+		/*Register : RST_LPD_TOP @ 0XFF5E023C

+
+		USB 0 reset for control registers
+		PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X0
+
+		Software control register for the LPD block.
+		(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000400U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000400U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : USB0 PIPE POWER PRESENT
+		/*Register : fpd_power_prsnt @ 0XFF9D0080

+
+		This bit is used to choose between PIPE power present and 1'b1
+		PSU_USB3_0_FPD_POWER_PRSNT_OPTION                                               0X1
+
+		fpd_power_prsnt
+		(OFFSET, MASK, VALUE)      (0XFF9D0080, 0x00000001U ,0x00000001U)  
+		RegMask = (USB3_0_FPD_POWER_PRSNT_OPTION_MASK |  0 );
+
+		RegVal = ((0x00000001U << USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (USB3_0_FPD_POWER_PRSNT_OFFSET ,0x00000001U ,0x00000001U);
+	/*############################################################################################################################ */
+
+		// : 
+		/*Register : RST_LPD_TOP @ 0XFF5E023C

+
+		USB 0 sleep circuit reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X0
+
+		USB 0 reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X0
+
+		Software control register for the LPD block.
+		(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000140U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+			| 0x00000000U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000140U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : PUTTING GEM0 IN RESET
+		/*Register : RST_LPD_IOU0 @ 0XFF5E0230

+
+		GEM 3 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X0
+
+		Software controlled reset for the GEMs
+		(OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000000U)  
+		RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : PUTTING SATA IN RESET
+		/*Register : sata_misc_ctrl @ 0XFD3D0100

+
+		Sata PM clock control select
+		PSU_SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL                                         0x3
+
+		Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled)
+		(OFFSET, MASK, VALUE)      (0XFD3D0100, 0x00000003U ,0x00000003U)  
+		RegMask = (SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK |  0 );
+
+		RegVal = ((0x00000003U << SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (SIOU_SATA_MISC_CTRL_OFFSET ,0x00000003U ,0x00000003U);
+	/*############################################################################################################################ */
+
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		Sata block level reset
+		PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X0
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : PUTTING PCIE IN RESET
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		PCIE config reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0X0
+
+		PCIE control block level reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0X0
+
+		PCIE bridge block level reset (AXI interface)
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0X0
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000E0000U ,0x00000000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
+			| 0x00000000U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : PUTTING DP IN RESET
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		Display Port block level reset (includes DPDMA)
+		PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X0
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00000000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DP_PHY_RESET @ 0XFD4A0200

+
+		Set to '1' to hold the GT in reset. Clear to release.
+		PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X0
+
+		Reset the transmitter PHY.
+		(OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000000U)  
+		RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK |  0 );
+
+		RegVal = ((0x00000000U << DP_DP_PHY_RESET_GT_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

+
+		Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 
+		ane0 Bits [3:2] - lane 1
+		PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0X0
+
+		Control PHY Power down
+		(OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x00000000U)  
+		RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK |  0 );
+
+		RegVal = ((0x00000000U << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : USB0 GFLADJ
+		/*Register : GUSB2PHYCFG @ 0XFE20C200

+
+		USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to 
+		he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
+		C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
+		. The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
+		UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger 
+		alue. Note: This field is valid only in device mode.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM                                           0X9
+
+		Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
+		 of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
+		time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
+		ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
+		off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
+		ng hibernation. - This bit is valid only in device mode.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY                                             0X0
+
+		Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
+		_n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
+		 to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. 
+		ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
+		n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
+		d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
+		d.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM                                            0X0
+
+		USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
+		Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - 
+		'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
+		 in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
+		 active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYSEL                                              0X0
+
+		Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
+		figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
+		ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
+		r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
+		t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
+		g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
+		 when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20                                        0X1
+
+		Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
+		full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with 
+		ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
+		B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_FSINTF                                              0X0
+
+		ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
+		e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
+		ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
+		lected through DWC_USB3_HSPHY_INTERFACE.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL                                       0X1
+
+		PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
+		 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same 
+		lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
+		 ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
+		 any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_PHYIF                                               0X0
+
+		HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
+		a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for 
+		dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
+		e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
+		The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this 
+		ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
+		 clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
+		60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times
+		PSU_USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL                                             0X7
+
+		Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either 
+		he SoC bus or the USB. In Device-only configurations, only one register is needed. In Host mode, per-port registers are imple
+		ented.
+		(OFFSET, MASK, VALUE)      (0XFE20C200, 0x00003FFFU ,0x00002457U)  
+		RegMask = (USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK | USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK | USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK | USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK | USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK | USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK | USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK |  0 );
+
+		RegVal = ((0x00000009U << USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT
+			| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT
+			| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT
+			| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT
+			| 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT
+			| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT
+			| 0x00000001U << USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT
+			| 0x00000000U << USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT
+			| 0x00000007U << USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (USB3_0_XHCI_GUSB2PHYCFG_OFFSET ,0x00003FFFU ,0x00002457U);
+	/*############################################################################################################################ */
+
+		/*Register : GFLADJ @ 0XFE20C630

+
+		This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register 
+		alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
+		_SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
+		TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
+		riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
+		cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
+		uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
+		((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
+		RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)
+		PSU_USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ                                      0X0
+
+		Global Frame Length Adjustment Register This register provides options for the software to control the core behavior with res
+		ect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It provides an optio
+		 to override the fladj_30mhz_reg sideband signal. In addition, it enables running SOF or ITP frame timer counters completely 
+		rom the ref_clk. This facilitates hardware LPM in host mode with the SOF or ITP counters being run from the ref_clk signal.
+		(OFFSET, MASK, VALUE)      (0XFE20C630, 0x003FFF00U ,0x00000000U)  
+		RegMask = (USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK |  0 );
+
+		RegVal = ((0x00000000U << USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (USB3_0_XHCI_GFLADJ_OFFSET ,0x003FFF00U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		// : CHECK PLL LOCK FOR LANE0
+		/*Register : L0_PLL_STATUS_READ_1 @ 0XFD4023E4

+
+		Status Read value of PLL Lock
+		PSU_SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+		(OFFSET, MASK, VALUE)      (0XFD4023E4, 0x00000010U ,0x00000010U)  */
+		mask_poll(SERDES_L0_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL LOCK FOR LANE1
+		/*Register : L1_PLL_STATUS_READ_1 @ 0XFD4063E4

+
+		Status Read value of PLL Lock
+		PSU_SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+		(OFFSET, MASK, VALUE)      (0XFD4063E4, 0x00000010U ,0x00000010U)  */
+		mask_poll(SERDES_L1_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL LOCK FOR LANE2
+		/*Register : L2_PLL_STATUS_READ_1 @ 0XFD40A3E4

+
+		Status Read value of PLL Lock
+		PSU_SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+		(OFFSET, MASK, VALUE)      (0XFD40A3E4, 0x00000010U ,0x00000010U)  */
+		mask_poll(SERDES_L2_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+	/*############################################################################################################################ */
+
+		// : CHECK PLL LOCK FOR LANE3
+		/*Register : L3_PLL_STATUS_READ_1 @ 0XFD40E3E4

+
+		Status Read value of PLL Lock
+		PSU_SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ                            1
+		(OFFSET, MASK, VALUE)      (0XFD40E3E4, 0x00000010U ,0x00000010U)  */
+		mask_poll(SERDES_L3_PLL_STATUS_READ_1_OFFSET,0x00000010U);
+
+	/*############################################################################################################################ */
+
+		// : UPDATING TWO PCIE REGISTERS DEFAULT VALUES, AS THESE REGISTERS HAVE INCORRECT RESET VALUES IN SILICON.
+		/*Register : ATTR_37 @ 0XFD480094

+
+		Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
+		gister.; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY                          0X1
+
+		ATTR_37
+		(OFFSET, MASK, VALUE)      (0XFD480094, 0x00004000U ,0x00004000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00004000U ,0x00004000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_25 @ 0XFD480064

+
+		If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
+		ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED                      0X1
+
+		ATTR_25
+		(OFFSET, MASK, VALUE)      (0XFD480064, 0x00000200U ,0x00000200U)  
+		RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x00000200U ,0x00000200U);
+	/*############################################################################################################################ */
+
+		// : PCIE SETTINGS
+		/*Register : ATTR_7 @ 0XFD48001C

+
+		Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
+		ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
+		Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
+		erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 
+		set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
+		re size in bytes.; EP=0x0004; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_7_ATTR_BAR0                                                0x0
+
+		ATTR_7
+		(OFFSET, MASK, VALUE)      (0XFD48001C, 0x0000FFFFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_7_OFFSET ,0x0000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_8 @ 0XFD480020

+
+		Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
+		ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
+		Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
+		erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 
+		set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
+		re size in bytes.; EP=0xFFF0; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_8_ATTR_BAR0                                                0x0
+
+		ATTR_8
+		(OFFSET, MASK, VALUE)      (0XFD480020, 0x0000FFFFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_8_OFFSET ,0x0000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_9 @ 0XFD480024

+
+		Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 
+		AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
+		 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 
+		o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
+		32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 
+		'7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
+		ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_9_ATTR_BAR1                                                0x0
+
+		ATTR_9
+		(OFFSET, MASK, VALUE)      (0XFD480024, 0x0000FFFFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_9_OFFSET ,0x0000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_10 @ 0XFD480028

+
+		Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 
+		AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
+		 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 
+		o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
+		32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 
+		'7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
+		ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_10_ATTR_BAR1                                               0x0
+
+		ATTR_10
+		(OFFSET, MASK, VALUE)      (0XFD480028, 0x0000FFFFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_10_OFFSET ,0x0000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_11 @ 0XFD48002C

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
+		AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF
+		PSU_PCIE_ATTRIB_ATTR_11_ATTR_BAR2                                               0xFFFF
+
+		ATTR_11
+		(OFFSET, MASK, VALUE)      (0XFD48002C, 0x0000FFFFU ,0x0000FFFFU)  
+		RegMask = (PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK |  0 );
+
+		RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_11_OFFSET ,0x0000FFFFU ,0x0000FFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_12 @ 0XFD480030

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
+		AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF
+		PSU_PCIE_ATTRIB_ATTR_12_ATTR_BAR2                                               0xFF
+
+		ATTR_12
+		(OFFSET, MASK, VALUE)      (0XFD480030, 0x0000FFFFU ,0x000000FFU)  
+		RegMask = (PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK |  0 );
+
+		RegVal = ((0x000000FFU << PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_12_OFFSET ,0x0000FFFFU ,0x000000FFU);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_13 @ 0XFD480034

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
+		AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
+		 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
+		t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
+		t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
+		if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 
+		f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
+		 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_13_ATTR_BAR3                                               0x0
+
+		ATTR_13
+		(OFFSET, MASK, VALUE)      (0XFD480034, 0x0000FFFFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_13_OFFSET ,0x0000FFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_14 @ 0XFD480038

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
+		AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
+		 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
+		t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
+		t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
+		if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 
+		f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
+		 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF
+		PSU_PCIE_ATTRIB_ATTR_14_ATTR_BAR3                                               0xFFFF
+
+		ATTR_14
+		(OFFSET, MASK, VALUE)      (0XFD480038, 0x0000FFFFU ,0x0000FFFFU)  
+		RegMask = (PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK |  0 );
+
+		RegVal = ((0x0000FFFFU << PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_14_OFFSET ,0x0000FFFFU ,0x0000FFFFU);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_15 @ 0XFD48003C

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
+		AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0
+		PSU_PCIE_ATTRIB_ATTR_15_ATTR_BAR4                                               0xFFF0
+
+		ATTR_15
+		(OFFSET, MASK, VALUE)      (0XFD48003C, 0x0000FFFFU ,0x0000FFF0U)  
+		RegMask = (PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK |  0 );
+
+		RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_15_OFFSET ,0x0000FFFFU ,0x0000FFF0U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_16 @ 0XFD480040

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
+		AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0
+		PSU_PCIE_ATTRIB_ATTR_16_ATTR_BAR4                                               0xFFF0
+
+		ATTR_16
+		(OFFSET, MASK, VALUE)      (0XFD480040, 0x0000FFFFU ,0x0000FFF0U)  
+		RegMask = (PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK |  0 );
+
+		RegVal = ((0x0000FFF0U << PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_16_OFFSET ,0x0000FFFFU ,0x0000FFF0U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_17 @ 0XFD480044

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
+		AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
+		Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 
+		refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
+		R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 
+		refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 
+		ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
+		permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
+		PSU_PCIE_ATTRIB_ATTR_17_ATTR_BAR5                                               0xFFF1
+
+		ATTR_17
+		(OFFSET, MASK, VALUE)      (0XFD480044, 0x0000FFFFU ,0x0000FFF1U)  
+		RegMask = (PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK |  0 );
+
+		RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_17_OFFSET ,0x0000FFFFU ,0x0000FFF1U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_18 @ 0XFD480048

+
+		For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
+		AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
+		Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 
+		refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
+		R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 
+		refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 
+		ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
+		permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1
+		PSU_PCIE_ATTRIB_ATTR_18_ATTR_BAR5                                               0xFFF1
+
+		ATTR_18
+		(OFFSET, MASK, VALUE)      (0XFD480048, 0x0000FFFFU ,0x0000FFF1U)  
+		RegMask = (PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK |  0 );
+
+		RegVal = ((0x0000FFF1U << PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_18_OFFSET ,0x0000FFFFU ,0x0000FFF1U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_27 @ 0XFD48006C

+
+		Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
+		to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED                      1
+
+		Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
+		state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
+		 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY                        0x0
+
+		ATTR_27
+		(OFFSET, MASK, VALUE)      (0XFD48006C, 0x00000738U ,0x00000100U)  
+		RegMask = (PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK | PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_27_OFFSET ,0x00000738U ,0x00000100U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_50 @ 0XFD4800C8

+
+		Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
+		00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
+		tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
+		gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004
+		PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE                          4
+
+		PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
+		lity.; EP=0x009C; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR                                   0
+
+		ATTR_50
+		(OFFSET, MASK, VALUE)      (0XFD4800C8, 0x0000FFF0U ,0x00000040U)  
+		RegMask = (PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK | PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK |  0 );
+
+		RegVal = ((0x00000004U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_50_OFFSET ,0x0000FFF0U ,0x00000040U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_105 @ 0XFD4801A4

+
+		Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
+		ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD
+		PSU_PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD                              0xCD
+
+		ATTR_105
+		(OFFSET, MASK, VALUE)      (0XFD4801A4, 0x000007FFU ,0x000000CDU)  
+		RegMask = (PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK |  0 );
+
+		RegVal = ((0x000000CDU << PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_105_OFFSET ,0x000007FFU ,0x000000CDU);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_106 @ 0XFD4801A8

+
+		Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non 
+		osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024
+		PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH                              0x24
+
+		Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
+		a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
+		completion header credits must be <= 80; EP=0x0004; RP=0x000C
+		PSU_PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH                             0xC
+
+		ATTR_106
+		(OFFSET, MASK, VALUE)      (0XFD4801A8, 0x00003FFFU ,0x00000624U)  
+		RegMask = (PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK | PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK |  0 );
+
+		RegVal = ((0x00000024U << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT
+			| 0x0000000CU << PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_106_OFFSET ,0x00003FFFU ,0x00000624U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_107 @ 0XFD4801AC

+
+		Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data 
+		redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
+		d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
+		less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018
+		PSU_PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD                             0x18
+
+		ATTR_107
+		(OFFSET, MASK, VALUE)      (0XFD4801AC, 0x000007FFU ,0x00000018U)  
+		RegMask = (PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK |  0 );
+
+		RegVal = ((0x00000018U << PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_107_OFFSET ,0x000007FFU ,0x00000018U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_108 @ 0XFD4801B0

+
+		Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less 
+		han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5
+		PSU_PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD                              0xB5
+
+		ATTR_108
+		(OFFSET, MASK, VALUE)      (0XFD4801B0, 0x000007FFU ,0x000000B5U)  
+		RegMask = (PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK |  0 );
+
+		RegVal = ((0x000000B5U << PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_108_OFFSET ,0x000007FFU ,0x000000B5U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_109 @ 0XFD4801B4

+
+		Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
+		0
+		PSU_PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV                                      0x0
+
+		Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM                                    0x1
+
+		Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
+		cap structure; EP=0x0003; RP=0x0003
+		PSU_PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK                                         0x3
+
+		Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
+		mber of brams configured for transmit; EP=0x001C; RP=0x001C
+		PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET                                 0x1c
+
+		Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
+		d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020
+		PSU_PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH                              0x20
+
+		ATTR_109
+		(OFFSET, MASK, VALUE)      (0XFD4801B4, 0x0000FFFFU ,0x00007E20U)  
+		RegMask = (PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK | PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK | PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT
+			| 0x00000001U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT
+			| 0x00000003U << PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT
+			| 0x0000001CU << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT
+			| 0x00000020U << PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_109_OFFSET ,0x0000FFFFU ,0x00007E20U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_34 @ 0XFD480088

+
+		Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
+		0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE                                        0x1
+
+		ATTR_34
+		(OFFSET, MASK, VALUE)      (0XFD480088, 0x000000FFU ,0x00000001U)  
+		RegMask = (PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_34_OFFSET ,0x000000FFU ,0x00000001U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_53 @ 0XFD4800D4

+
+		PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
+		ty.; EP=0x0048; RP=0x0060
+		PSU_PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR                                     0x60
+
+		ATTR_53
+		(OFFSET, MASK, VALUE)      (0XFD4800D4, 0x000000FFU ,0x00000060U)  
+		RegMask = (PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK |  0 );
+
+		RegVal = ((0x00000060U << PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_53_OFFSET ,0x000000FFU ,0x00000060U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_41 @ 0XFD4800A4

+
+		MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
+		 to Cap structure; EP=0x0000; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE                 0x0
+
+		Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 
+		he management port.; EP=0x0001; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON                                         0
+
+		MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
+		ity.; EP=0x0060; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR                                    0x0
+
+		Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 
+		he management port.; EP=0x0001; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON                                         0
+
+		ATTR_41
+		(OFFSET, MASK, VALUE)      (0XFD4800A4, 0x000003FFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK | PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_41_OFFSET ,0x000003FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_97 @ 0XFD480184

+
+		Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004
+		PSU_PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH                            0x1
+
+		Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
+		4; RP=0x0004
+		PSU_PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH                               0x1
+
+		ATTR_97
+		(OFFSET, MASK, VALUE)      (0XFD480184, 0x00000FFFU ,0x00000041U)  
+		RegMask = (PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK | PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT
+			| 0x00000001U << PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_97_OFFSET ,0x00000FFFU ,0x00000041U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_100 @ 0XFD480190

+
+		TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING                                   0x0
+
+		ATTR_100
+		(OFFSET, MASK, VALUE)      (0XFD480190, 0x00000040U ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_100_OFFSET ,0x00000040U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_101 @ 0XFD480194

+
+		Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message 
+		LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
+		Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
+		EP=0x0000; RP=0x07FF
+		PSU_PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE                                  0x7FF
+
+		Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING                             0x1
+
+		ATTR_101
+		(OFFSET, MASK, VALUE)      (0XFD480194, 0x0000FFE2U ,0x0000FFE2U)  
+		RegMask = (PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK | PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK |  0 );
+
+		RegVal = ((0x000007FFU << PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT
+			| 0x00000001U << PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_101_OFFSET ,0x0000FFE2U ,0x0000FFE2U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_37 @ 0XFD480094

+
+		Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
+		Required for Root.; EP=0x0000; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP           0x1
+
+		ATTR_37
+		(OFFSET, MASK, VALUE)      (0XFD480094, 0x00000200U ,0x00000200U)  
+		RegMask = (PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_37_OFFSET ,0x00000200U ,0x00000200U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_93 @ 0XFD480174

+
+		Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
+		_REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN                               0x1
+
+		Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
+		TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
+		4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT                                  0x1000
+
+		ATTR_93
+		(OFFSET, MASK, VALUE)      (0XFD480174, 0x0000FFFFU ,0x00009000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK | PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT
+			| 0x00001000U << PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_93_OFFSET ,0x0000FFFFU ,0x00009000U);
+	/*############################################################################################################################ */
+
+		/*Register : ID @ 0XFD480200

+
+		Device ID for the the PCIe Cap Structure Device ID field
+		PSU_PCIE_ATTRIB_ID_CFG_DEV_ID                                                   0xd021
+
+		Vendor ID for the PCIe Cap Structure Vendor ID field
+		PSU_PCIE_ATTRIB_ID_CFG_VEND_ID                                                  0x10ee
+
+		ID
+		(OFFSET, MASK, VALUE)      (0XFD480200, 0xFFFFFFFFU ,0x10EED021U)  
+		RegMask = (PCIE_ATTRIB_ID_CFG_DEV_ID_MASK | PCIE_ATTRIB_ID_CFG_VEND_ID_MASK |  0 );
+
+		RegVal = ((0x0000D021U << PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT
+			| 0x000010EEU << PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ID_OFFSET ,0xFFFFFFFFU ,0x10EED021U);
+	/*############################################################################################################################ */
+
+		/*Register : SUBSYS_ID @ 0XFD480204

+
+		Subsystem ID for the the PCIe Cap Structure Subsystem ID field
+		PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID                                         0x7
+
+		Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field
+		PSU_PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID                                    0x10ee
+
+		SUBSYS_ID
+		(OFFSET, MASK, VALUE)      (0XFD480204, 0xFFFFFFFFU ,0x10EE0007U)  
+		RegMask = (PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK | PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK |  0 );
+
+		RegVal = ((0x00000007U << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT
+			| 0x000010EEU << PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_SUBSYS_ID_OFFSET ,0xFFFFFFFFU ,0x10EE0007U);
+	/*############################################################################################################################ */
+
+		/*Register : REV_ID @ 0XFD480208

+
+		Revision ID for the the PCIe Cap Structure
+		PSU_PCIE_ATTRIB_REV_ID_CFG_REV_ID                                               0x0
+
+		REV_ID
+		(OFFSET, MASK, VALUE)      (0XFD480208, 0x000000FFU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_REV_ID_OFFSET ,0x000000FFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_24 @ 0XFD480060

+
+		Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
+		8000; RP=0x8000
+		PSU_PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE                                         0x400
+
+		ATTR_24
+		(OFFSET, MASK, VALUE)      (0XFD480060, 0x0000FFFFU ,0x00000400U)  
+		RegMask = (PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK |  0 );
+
+		RegVal = ((0x00000400U << PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_24_OFFSET ,0x0000FFFFU ,0x00000400U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_25 @ 0XFD480064

+
+		Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
+		0005; RP=0x0006
+		PSU_PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE                                         0x6
+
+		INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED                               0
+
+		ATTR_25
+		(OFFSET, MASK, VALUE)      (0XFD480064, 0x000001FFU ,0x00000006U)  
+		RegMask = (PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK | PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK |  0 );
+
+		RegVal = ((0x00000006U << PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_25_OFFSET ,0x000001FFU ,0x00000006U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_4 @ 0XFD480010

+
+		Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 
+		he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
+		ges are sent if an error is detected).; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON                                          0
+
+		Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 
+		he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
+		ges are sent if an error is detected).; EP=0x0001; RP=0x0001
+		PSU_PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON                                          0
+
+		ATTR_4
+		(OFFSET, MASK, VALUE)      (0XFD480010, 0x00001000U ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK | PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
+			| 0x00000000U << PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_4_OFFSET ,0x00001000U ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_89 @ 0XFD480164

+
+		VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
+		0x0140; RP=0x0140
+		PSU_PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR                                   0
+
+		ATTR_89
+		(OFFSET, MASK, VALUE)      (0XFD480164, 0x00001FFEU ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_89_OFFSET ,0x00001FFEU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_79 @ 0XFD48013C

+
+		CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY                         1
+
+		ATTR_79
+		(OFFSET, MASK, VALUE)      (0XFD48013C, 0x00000020U ,0x00000020U)  
+		RegMask = (PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK |  0 );
+
+		RegVal = ((0x00000001U << PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_79_OFFSET ,0x00000020U ,0x00000020U);
+	/*############################################################################################################################ */
+
+		/*Register : ATTR_43 @ 0XFD4800AC

+
+		Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
+		 the management port.; EP=0x0001; RP=0x0000
+		PSU_PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON                                        0
+
+		ATTR_43
+		(OFFSET, MASK, VALUE)      (0XFD4800AC, 0x00000100U ,0x00000000U)  
+		RegMask = (PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK |  0 );
+
+		RegVal = ((0x00000000U << PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PCIE_ATTRIB_ATTR_43_OFFSET ,0x00000100U ,0x00000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_resetin_init_data() {
+		// : PUTTING SERDES PERIPHERAL IN RESET
+		// : PUTTING USB0 IN RESET
+		/*Register : RST_LPD_TOP @ 0XFF5E023C

+
+		USB 0 reset for control registers
+		PSU_CRL_APB_RST_LPD_TOP_USB0_APB_RESET                                          0X1
+
+		USB 0 sleep circuit reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_HIBERRESET                                         0X1
+
+		USB 0 reset
+		PSU_CRL_APB_RST_LPD_TOP_USB0_CORERESET                                          0X1
+
+		Software control register for the LPD block.
+		(OFFSET, MASK, VALUE)      (0XFF5E023C, 0x00000540U ,0x00000540U)  
+		RegMask = (CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK | CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK | CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT
+			| 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT
+			| 0x00000001U << CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_TOP_OFFSET ,0x00000540U ,0x00000540U);
+	/*############################################################################################################################ */
+
+		// : PUTTING GEM0 IN RESET
+		/*Register : RST_LPD_IOU0 @ 0XFF5E0230

+
+		GEM 3 reset
+		PSU_CRL_APB_RST_LPD_IOU0_GEM3_RESET                                             0X1
+
+		Software controlled reset for the GEMs
+		(OFFSET, MASK, VALUE)      (0XFF5E0230, 0x00000008U ,0x00000008U)  
+		RegMask = (CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRL_APB_RST_LPD_IOU0_OFFSET ,0x00000008U ,0x00000008U);
+	/*############################################################################################################################ */
+
+		// : PUTTING SATA IN RESET
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		Sata block level reset
+		PSU_CRF_APB_RST_FPD_TOP_SATA_RESET                                              0X1
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00000002U ,0x00000002U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_SATA_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00000002U ,0x00000002U);
+	/*############################################################################################################################ */
+
+		// : PUTTING PCIE IN RESET
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		PCIE config reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET                                          0X1
+
+		PCIE control block level reset
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET                                         0X1
+
+		PCIE bridge block level reset (AXI interface)
+		PSU_CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET                                       0X1
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x000E0000U ,0x000E0000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK | CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT
+			| 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT
+			| 0x00000001U << CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x000E0000U ,0x000E0000U);
+	/*############################################################################################################################ */
+
+		// : PUTTING DP IN RESET
+		/*Register : DP_TX_PHY_POWER_DOWN @ 0XFD4A0238

+
+		Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 
+		ane0 Bits [3:2] - lane 1
+		PSU_DP_DP_TX_PHY_POWER_DOWN_POWER_DWN                                           0XA
+
+		Control PHY Power down
+		(OFFSET, MASK, VALUE)      (0XFD4A0238, 0x0000000FU ,0x0000000AU)  
+		RegMask = (DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK |  0 );
+
+		RegVal = ((0x0000000AU << DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DP_DP_TX_PHY_POWER_DOWN_OFFSET ,0x0000000FU ,0x0000000AU);
+	/*############################################################################################################################ */
+
+		/*Register : DP_PHY_RESET @ 0XFD4A0200

+
+		Set to '1' to hold the GT in reset. Clear to release.
+		PSU_DP_DP_PHY_RESET_GT_RESET                                                    0X1
+
+		Reset the transmitter PHY.
+		(OFFSET, MASK, VALUE)      (0XFD4A0200, 0x00000002U ,0x00000002U)  
+		RegMask = (DP_DP_PHY_RESET_GT_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << DP_DP_PHY_RESET_GT_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (DP_DP_PHY_RESET_OFFSET ,0x00000002U ,0x00000002U);
+	/*############################################################################################################################ */
+
+		/*Register : RST_FPD_TOP @ 0XFD1A0100

+
+		Display Port block level reset (includes DPDMA)
+		PSU_CRF_APB_RST_FPD_TOP_DP_RESET                                                0X1
+
+		FPD Block level software controlled reset
+		(OFFSET, MASK, VALUE)      (0XFD1A0100, 0x00010000U ,0x00010000U)  
+		RegMask = (CRF_APB_RST_FPD_TOP_DP_RESET_MASK |  0 );
+
+		RegVal = ((0x00000001U << CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (CRF_APB_RST_FPD_TOP_OFFSET ,0x00010000U ,0x00010000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_ps_pl_isolation_removal_data() {
+		// : PS-PL POWER UP REQUEST
+		/*Register : REQ_PWRUP_INT_EN @ 0XFFD80118

+
+		Power-up Request Interrupt Enable for PL
+		PSU_PMU_GLOBAL_REQ_PWRUP_INT_EN_PL                                              1
+
+		Power-up Request Interrupt Enable Register. Writing a 1 to this location will unmask the interrupt.
+		(OFFSET, MASK, VALUE)      (0XFFD80118, 0x00800000U ,0x00800000U)  
+		RegMask = (PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK |  0 );
+
+		RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET ,0x00800000U ,0x00800000U);
+	/*############################################################################################################################ */
+
+		/*Register : REQ_PWRUP_TRIG @ 0XFFD80120

+
+		Power-up Request Trigger for PL
+		PSU_PMU_GLOBAL_REQ_PWRUP_TRIG_PL                                                1
+
+		Power-up Request Trigger Register. A write of one to this location will generate a power-up request to the PMU.
+		(OFFSET, MASK, VALUE)      (0XFFD80120, 0x00800000U ,0x00800000U)  
+		RegMask = (PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK |  0 );
+
+		RegVal = ((0x00000001U << PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET ,0x00800000U ,0x00800000U);
+	/*############################################################################################################################ */
+
+		// : POLL ON PL POWER STATUS
+		/*Register : REQ_PWRUP_STATUS @ 0XFFD80110

+
+		Power-up Request Status for PL
+		PSU_PMU_GLOBAL_REQ_PWRUP_STATUS_PL                                              1
+		(OFFSET, MASK, VALUE)      (0XFFD80110, 0x00800000U ,0x00000000U)  */
+		mask_pollOnValue(PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET,0x00800000U,0x00000000U);
+
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+unsigned long psu_ps_pl_reset_config_data() {
+		// : PS PL RESET SEQUENCE
+		// : FABRIC RESET USING EMIO
+		/*Register : MASK_DATA_5_MSW @ 0XFF0A002C

+
+		Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]
+		PSU_GPIO_MASK_DATA_5_MSW_MASK_5_MSW                                             0x8000
+
+		Maskable Output Data (GPIO Bank5, EMIO, Upper 16bits)
+		(OFFSET, MASK, VALUE)      (0XFF0A002C, 0xFFFF0000U ,0x80000000U)  
+		RegMask = (GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK |  0 );
+
+		RegVal = ((0x00008000U << GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_MASK_DATA_5_MSW_OFFSET ,0xFFFF0000U ,0x80000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DIRM_5 @ 0XFF0A0344

+
+		Operation is the same as DIRM_0[DIRECTION_0]
+		PSU_GPIO_DIRM_5_DIRECTION_5                                                     0x80000000
+
+		Direction mode (GPIO Bank5, EMIO)
+		(OFFSET, MASK, VALUE)      (0XFF0A0344, 0xFFFFFFFFU ,0x80000000U)  
+		RegMask = (GPIO_DIRM_5_DIRECTION_5_MASK |  0 );
+
+		RegVal = ((0x80000000U << GPIO_DIRM_5_DIRECTION_5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_DIRM_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
+	/*############################################################################################################################ */
+
+		/*Register : OEN_5 @ 0XFF0A0348

+
+		Operation is the same as OEN_0[OP_ENABLE_0]
+		PSU_GPIO_OEN_5_OP_ENABLE_5                                                      0x80000000
+
+		Output enable (GPIO Bank5, EMIO)
+		(OFFSET, MASK, VALUE)      (0XFF0A0348, 0xFFFFFFFFU ,0x80000000U)  
+		RegMask = (GPIO_OEN_5_OP_ENABLE_5_MASK |  0 );
+
+		RegVal = ((0x80000000U << GPIO_OEN_5_OP_ENABLE_5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_OEN_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
+	/*############################################################################################################################ */
+
+		/*Register : DATA_5 @ 0XFF0A0054

+
+		Output Data
+		PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
+
+		Output Data (GPIO Bank5, EMIO)
+		(OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)  
+		RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
+
+		RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
+	/*############################################################################################################################ */
+
+		mask_delay(1);
+
+	/*############################################################################################################################ */
+
+		// : FABRIC RESET USING DATA_5 TOGGLE
+		/*Register : DATA_5 @ 0XFF0A0054

+
+		Output Data
+		PSU_GPIO_DATA_5_DATA_5                                                          0X00000000
+
+		Output Data (GPIO Bank5, EMIO)
+		(OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x00000000U)  
+		RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
+
+		RegVal = ((0x00000000U << GPIO_DATA_5_DATA_5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x00000000U);
+	/*############################################################################################################################ */
+
+		mask_delay(1);
+
+	/*############################################################################################################################ */
+
+		// : FABRIC RESET USING DATA_5 TOGGLE
+		/*Register : DATA_5 @ 0XFF0A0054

+
+		Output Data
+		PSU_GPIO_DATA_5_DATA_5                                                          0x80000000
+
+		Output Data (GPIO Bank5, EMIO)
+		(OFFSET, MASK, VALUE)      (0XFF0A0054, 0xFFFFFFFFU ,0x80000000U)  
+		RegMask = (GPIO_DATA_5_DATA_5_MASK |  0 );
+
+		RegVal = ((0x80000000U << GPIO_DATA_5_DATA_5_SHIFT
+			|  0 ) & RegMask); */
+		PSU_Mask_Write (GPIO_DATA_5_OFFSET ,0xFFFFFFFFU ,0x80000000U);
+	/*############################################################################################################################ */
+
+
+  return 1;
+}
+
+unsigned long psu_ddr_phybringup_data() {
+
+
+		unsigned int regval = 0;
+	Xil_Out32(0xFD090000U, 0x0000A845U);
+	Xil_Out32(0xFD090004U, 0x003FFFFFU);
+	Xil_Out32(0xFD09000CU, 0x00000010U);
+	Xil_Out32(0xFD090010U, 0x00000010U);
+	// PHY BRINGUP SEQ
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000000FU);
+	prog_reg (0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
+	//poll for PHY initialization to complete 
+	while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU);
+	
+	Xil_Out32(0xFD0701B0U, 0x00000001U);
+	Xil_Out32(0xFD070320U, 0x00000001U);
+	while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U);
+	prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
+	 Xil_Out32(0xFD080004, 0x0004FE01); //PUB_PIR  
+	  regval = Xil_In32(0xFD080030); //PUB_PGSR0
+	  while(regval != 0x80000FFF){   
+	     regval = Xil_In32(0xFD080030); //PUB_PGSR0 
+	  } 
+
+	
+ // Run Vref training in static read mode  
+	Xil_Out32(0xFD080200U, 0x110011C7U);
+	Xil_Out32(0xFD080018U, 0x00F01EF2U);
+	Xil_Out32(0xFD08001CU, 0x55AA0098U);
+	Xil_Out32(0xFD08142CU, 0x00001830U);
+	Xil_Out32(0xFD08146CU, 0x00001830U);
+	Xil_Out32(0xFD0814ACU, 0x00001830U);
+	Xil_Out32(0xFD0814ECU, 0x00001830U);
+	Xil_Out32(0xFD08152CU, 0x00001830U);
+	 
+
+	 Xil_Out32(0xFD080004, 0x00060001); //PUB_PIR  
+	  regval = Xil_In32(0xFD080030); //PUB_PGSR0
+	  while((regval & 0x80004001) != 0x80004001){   
+	     regval = Xil_In32(0xFD080030); //PUB_PGSR0 
+	  } 
+
+	 // Vref training is complete, disabling static read mode 
+	Xil_Out32(0xFD080200U, 0x810011C7U);
+	Xil_Out32(0xFD080018U, 0x00F12302U);
+	Xil_Out32(0xFD08001CU, 0x55AA0080U);
+	Xil_Out32(0xFD08142CU, 0x00001800U);
+	Xil_Out32(0xFD08146CU, 0x00001800U);
+	Xil_Out32(0xFD0814ACU, 0x00001800U);
+	Xil_Out32(0xFD0814ECU, 0x00001800U);
+	Xil_Out32(0xFD08152CU, 0x00001800U);
+	Xil_Out32(0xFD070180U, 0x01000040U);
+	Xil_Out32(0xFD070060U, 0x00000000U);
+	prog_reg (0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
+
+return 1; 
+}
+
+/**
+ * CRL_APB Base Address
+ */
+#define CRL_APB_BASEADDR      0XFF5E0000U
+#define CRL_APB_RST_LPD_IOU0    ( ( CRL_APB_BASEADDR ) + 0X00000230U )
+#define CRL_APB_RST_LPD_IOU1    ( ( CRL_APB_BASEADDR ) + 0X00000234U )
+#define CRL_APB_RST_LPD_IOU2    ( ( CRL_APB_BASEADDR ) + 0X00000238U )
+#define CRL_APB_RST_LPD_TOP    ( ( CRL_APB_BASEADDR ) + 0X0000023CU )
+#define CRL_APB_IOU_SWITCH_CTRL    ( ( CRL_APB_BASEADDR ) + 0X0000009CU )
+
+/**
+ * CRF_APB Base Address
+ */
+#define CRF_APB_BASEADDR      0XFD1A0000U
+
+#define CRF_APB_RST_FPD_TOP    ( ( CRF_APB_BASEADDR ) + 0X00000100U )
+#define CRF_APB_GPU_REF_CTRL    ( ( CRF_APB_BASEADDR ) + 0X00000084U )
+#define CRF_APB_RST_DDR_SS    ( ( CRF_APB_BASEADDR ) + 0X00000108U )
+#define PSU_MASK_POLL_TIME 1100000
+
+
+int mask_pollOnValue(u32 add , u32 mask, u32 value ) {
+	volatile u32 *addr = (volatile u32*) add;
+	int i = 0;
+	while ((*addr & mask)!= value) {
+		if (i == PSU_MASK_POLL_TIME) {
+			return 0;
+		}
+		i++;
+	}
+	return 1;   
+	//xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+int mask_poll(u32 add , u32 mask) {
+	volatile u32 *addr = (volatile u32*) add;
+	int i = 0;
+	while (!(*addr & mask)) {
+		if (i == PSU_MASK_POLL_TIME) {
+			return 0;
+		}
+		i++;
+	}
+	return 1;   
+	//xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr);
+}
+
+void mask_delay(u32 delay) {
+    usleep (delay);
+}
+
+u32 mask_read(u32 add , u32 mask ) {
+        volatile u32 *addr = (volatile u32*) add;
+        u32 val = (*addr & mask);
+        //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val);
+        return val;
+}
+
+
+//Following SERDES programming sequences that a user need to follow to work around the known limitation with SERDES. 
+//These sequences should done before STEP 1 and STEP 2 as described in previous section. These programming steps are
+//required for current silicon version and are likely to undergo further changes with subsequent silicon versions.
+
+
+
+int serdes_fixcal_code() {
+	int MaskStatus = 1;
+
+   // L3_TM_CALIB_DIG19
+   Xil_Out32(0xFD40EC4C,0x00000020);
+   //ICM_CFG0
+   Xil_Out32(0xFD410010,0x00000001);
+
+   //is calibration done, polling on L3_CALIB_DONE_STATUS
+   MaskStatus = mask_poll(0xFD40EF14, 0x2);
+   
+   if (MaskStatus == 0)
+   {
+        xil_printf("SERDES initialization timed out\n\r");
+   }
+ 
+   unsigned int tmp_0_1; 
+   tmp_0_1 = mask_read(0xFD400B0C, 0x3F);
+   
+   unsigned int tmp_0_2 = tmp_0_1 & (0x7); 
+   unsigned int tmp_0_3 = tmp_0_1 & (0x38);
+   //Configure ICM for de-asserting CMN_Resetn
+   Xil_Out32(0xFD410010,0x00000000);
+   Xil_Out32(0xFD410014,0x00000000);
+   
+   unsigned int tmp_0_2_mod = (tmp_0_2 <<1) | (0x1); 
+   tmp_0_2_mod = (tmp_0_2_mod <<4); 
+   
+   tmp_0_3 = tmp_0_3 >>3;
+   Xil_Out32(0xFD40EC4C,tmp_0_3);
+
+   //L3_TM_CALIB_DIG18
+   Xil_Out32(0xFD40EC48,tmp_0_2_mod);
+   return MaskStatus;
+
+
+}
+
+int serdes_enb_coarse_saturation() {
+  //Enable PLL Coarse Code saturation Logic
+   Xil_Out32(0xFD402094,0x00000010); 
+   Xil_Out32(0xFD406094,0x00000010); 
+   Xil_Out32(0xFD40A094,0x00000010); 
+   Xil_Out32(0xFD40E094,0x00000010);
+   return 1;
+}
+
+int init_serdes() {
+	int status = 1;
+	status &=  psu_resetin_init_data();
+
+	status &= serdes_fixcal_code();
+	status &= serdes_enb_coarse_saturation();
+
+    status &=  psu_serdes_init_data();
+	status &=  psu_resetout_init_data();
+
+	return status;
+}
+
+
+
+
+
+
+void init_peripheral()
+{
+	unsigned int RegValue;
+
+	/* Turn on IOU Clock */
+	//Xil_Out32( CRL_APB_IOU_SWITCH_CTRL, 0x01001500);
+
+	/* Release all resets in the IOU */
+	Xil_Out32( CRL_APB_RST_LPD_IOU0, 0x00000000);
+	Xil_Out32( CRL_APB_RST_LPD_IOU1, 0x00000000);
+	Xil_Out32( CRL_APB_RST_LPD_IOU2, 0x00000000);
+
+	/* Activate GPU clocks */
+	//Xil_Out32(CRF_APB_GPU_REF_CTRL, 0x07001500);
+
+	/* Take LPD out of reset except R5 */
+	RegValue = Xil_In32(CRL_APB_RST_LPD_TOP);
+	RegValue &= 0x7;
+	Xil_Out32( CRL_APB_RST_LPD_TOP, RegValue);
+
+	/* Take most of FPD out of reset */
+	Xil_Out32( CRF_APB_RST_FPD_TOP, 0x00000000);
+
+	/* Making DPDMA as secure */
+  unsigned int tmp_regval; 
+  tmp_regval = Xil_In32(0xFD690040);
+  tmp_regval &= ~0x00000001;
+  Xil_Out32(0xFD690040, tmp_regval);
+
+	/* Making PCIe as secure */
+  tmp_regval = Xil_In32(0xFD690030);
+  tmp_regval &= ~0x00000001;
+  Xil_Out32(0xFD690030, tmp_regval);
+}
+int
+psu_init() 
+{
+	int status = 1; 
+	status &= psu_mio_init_data ();
+	status &=   psu_pll_init_data ();
+	status &=   psu_clock_init_data ();
+
+	status &=  psu_ddr_init_data ();
+	status &=  psu_ddr_phybringup_data ();
+	status &=  psu_peripherals_init_data ();
+
+	status &=  init_serdes();
+	init_peripheral ();
+
+	status &=  psu_peripherals_powerdwn_data ();
+   
+	if (status == 0) {
+		return 1;
+	}
+	return 0;
+}
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h
new file mode 100644
index 000000000..ae33f880c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/psu_init_gpl.h
@@ -0,0 +1,26148 @@
+/******************************************************************************
+*
+* Copyright (C) 2015 Xilinx, Inc.  All rights reserved.
+* 
+*  This program is free software; you can redistribute it and/or modify
+*  it under the terms of the GNU General Public License as published by
+*  the Free Software Foundation; either version 2 of the License, or
+*  (at your option) any later version.
+*
+*  This program is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+*  GNU General Public License for more details.
+* 
+*  You should have received a copy of the GNU General Public License along
+*  with this program; if not, see 
+* 
+* 
+******************************************************************************/ 
+/****************************************************************************/
+/**
+*
+* @file psu_init_gpl.h
+*
+* This file is automatically generated 
+*
+*****************************************************************************/
+
+
+#undef CRL_APB_RPLL_CFG_OFFSET 
+#define CRL_APB_RPLL_CFG_OFFSET                                                    0XFF5E0034
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_CTRL_OFFSET 
+#define CRL_APB_RPLL_CTRL_OFFSET                                                   0XFF5E0030
+#undef CRL_APB_RPLL_TO_FPD_CTRL_OFFSET 
+#define CRL_APB_RPLL_TO_FPD_CTRL_OFFSET                                            0XFF5E0048
+#undef CRL_APB_RPLL_FRAC_CFG_OFFSET 
+#define CRL_APB_RPLL_FRAC_CFG_OFFSET                                               0XFF5E0038
+#undef CRL_APB_IOPLL_CFG_OFFSET 
+#define CRL_APB_IOPLL_CFG_OFFSET                                                   0XFF5E0024
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_CTRL_OFFSET 
+#define CRL_APB_IOPLL_CTRL_OFFSET                                                  0XFF5E0020
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET 
+#define CRL_APB_IOPLL_TO_FPD_CTRL_OFFSET                                           0XFF5E0044
+#undef CRL_APB_IOPLL_FRAC_CFG_OFFSET 
+#define CRL_APB_IOPLL_FRAC_CFG_OFFSET                                              0XFF5E0028
+#undef CRF_APB_APLL_CFG_OFFSET 
+#define CRF_APB_APLL_CFG_OFFSET                                                    0XFD1A0024
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_CTRL_OFFSET 
+#define CRF_APB_APLL_CTRL_OFFSET                                                   0XFD1A0020
+#undef CRF_APB_APLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_APLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0048
+#undef CRF_APB_APLL_FRAC_CFG_OFFSET 
+#define CRF_APB_APLL_FRAC_CFG_OFFSET                                               0XFD1A0028
+#undef CRF_APB_DPLL_CFG_OFFSET 
+#define CRF_APB_DPLL_CFG_OFFSET                                                    0XFD1A0030
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_CTRL_OFFSET 
+#define CRF_APB_DPLL_CTRL_OFFSET                                                   0XFD1A002C
+#undef CRF_APB_DPLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_DPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A004C
+#undef CRF_APB_DPLL_FRAC_CFG_OFFSET 
+#define CRF_APB_DPLL_FRAC_CFG_OFFSET                                               0XFD1A0034
+#undef CRF_APB_VPLL_CFG_OFFSET 
+#define CRF_APB_VPLL_CFG_OFFSET                                                    0XFD1A003C
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_CTRL_OFFSET 
+#define CRF_APB_VPLL_CTRL_OFFSET                                                   0XFD1A0038
+#undef CRF_APB_VPLL_TO_LPD_CTRL_OFFSET 
+#define CRF_APB_VPLL_TO_LPD_CTRL_OFFSET                                            0XFD1A0050
+#undef CRF_APB_VPLL_FRAC_CFG_OFFSET 
+#define CRF_APB_VPLL_FRAC_CFG_OFFSET                                               0XFD1A0040
+
+/*PLL loop filter resistor control*/
+#undef CRL_APB_RPLL_CFG_RES_DEFVAL 
+#undef CRL_APB_RPLL_CFG_RES_SHIFT 
+#undef CRL_APB_RPLL_CFG_RES_MASK 
+#define CRL_APB_RPLL_CFG_RES_DEFVAL                                                0x00000000
+#define CRL_APB_RPLL_CFG_RES_SHIFT                                                 0
+#define CRL_APB_RPLL_CFG_RES_MASK                                                  0x0000000FU
+
+/*PLL charge pump control*/
+#undef CRL_APB_RPLL_CFG_CP_DEFVAL 
+#undef CRL_APB_RPLL_CFG_CP_SHIFT 
+#undef CRL_APB_RPLL_CFG_CP_MASK 
+#define CRL_APB_RPLL_CFG_CP_DEFVAL                                                 0x00000000
+#define CRL_APB_RPLL_CFG_CP_SHIFT                                                  5
+#define CRL_APB_RPLL_CFG_CP_MASK                                                   0x000001E0U
+
+/*PLL loop filter high frequency capacitor control*/
+#undef CRL_APB_RPLL_CFG_LFHF_DEFVAL 
+#undef CRL_APB_RPLL_CFG_LFHF_SHIFT 
+#undef CRL_APB_RPLL_CFG_LFHF_MASK 
+#define CRL_APB_RPLL_CFG_LFHF_DEFVAL                                               0x00000000
+#define CRL_APB_RPLL_CFG_LFHF_SHIFT                                                10
+#define CRL_APB_RPLL_CFG_LFHF_MASK                                                 0x00000C00U
+
+/*Lock circuit counter setting*/
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRL_APB_RPLL_CFG_LOCK_CNT_MASK 
+#define CRL_APB_RPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
+#define CRL_APB_RPLL_CFG_LOCK_CNT_SHIFT                                            13
+#define CRL_APB_RPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
+
+/*Lock circuit configuration settings for lock windowsize*/
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRL_APB_RPLL_CFG_LOCK_DLY_MASK 
+#define CRL_APB_RPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
+#define CRL_APB_RPLL_CFG_LOCK_DLY_SHIFT                                            25
+#define CRL_APB_RPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
+
+/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRL_APB_RPLL_CTRL_PRE_SRC_MASK 
+#define CRL_APB_RPLL_CTRL_PRE_SRC_DEFVAL                                           0x00012C09
+#define CRL_APB_RPLL_CTRL_PRE_SRC_SHIFT                                            20
+#define CRL_APB_RPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRL_APB_RPLL_CTRL_FBDIV_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_FBDIV_SHIFT 
+#undef CRL_APB_RPLL_CTRL_FBDIV_MASK 
+#define CRL_APB_RPLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRL_APB_RPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRL_APB_RPLL_CTRL_DIV2_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_DIV2_SHIFT 
+#undef CRL_APB_RPLL_CTRL_DIV2_MASK 
+#define CRL_APB_RPLL_CTRL_DIV2_DEFVAL                                              0x00012C09
+#define CRL_APB_RPLL_CTRL_DIV2_SHIFT                                               16
+#define CRL_APB_RPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
+#define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRL_APB_RPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_RPLL_CTRL_RESET_MASK 
+#define CRL_APB_RPLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRL_APB_RPLL_CTRL_RESET_SHIFT                                              0
+#define CRL_APB_RPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*RPLL is locked*/
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL 
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT 
+#undef CRL_APB_PLL_STATUS_RPLL_LOCK_MASK 
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_DEFVAL                                        0x00000018
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_SHIFT                                         1
+#define CRL_APB_PLL_STATUS_RPLL_LOCK_MASK                                          0x00000002U
+#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_RPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_RPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_RPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_RPLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRL_APB_RPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRL_APB_RPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRL_APB_RPLL_TO_FPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
+#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL 
+#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT 
+#undef CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK 
+#define CRL_APB_RPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
+#define CRL_APB_RPLL_FRAC_CFG_ENABLED_SHIFT                                        31
+#define CRL_APB_RPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
+
+/*Fractional value for the Feedback value.*/
+#undef CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL 
+#undef CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT 
+#undef CRL_APB_RPLL_FRAC_CFG_DATA_MASK 
+#define CRL_APB_RPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
+#define CRL_APB_RPLL_FRAC_CFG_DATA_SHIFT                                           0
+#define CRL_APB_RPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
+
+/*PLL loop filter resistor control*/
+#undef CRL_APB_IOPLL_CFG_RES_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_RES_SHIFT 
+#undef CRL_APB_IOPLL_CFG_RES_MASK 
+#define CRL_APB_IOPLL_CFG_RES_DEFVAL                                               0x00000000
+#define CRL_APB_IOPLL_CFG_RES_SHIFT                                                0
+#define CRL_APB_IOPLL_CFG_RES_MASK                                                 0x0000000FU
+
+/*PLL charge pump control*/
+#undef CRL_APB_IOPLL_CFG_CP_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_CP_SHIFT 
+#undef CRL_APB_IOPLL_CFG_CP_MASK 
+#define CRL_APB_IOPLL_CFG_CP_DEFVAL                                                0x00000000
+#define CRL_APB_IOPLL_CFG_CP_SHIFT                                                 5
+#define CRL_APB_IOPLL_CFG_CP_MASK                                                  0x000001E0U
+
+/*PLL loop filter high frequency capacitor control*/
+#undef CRL_APB_IOPLL_CFG_LFHF_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_LFHF_SHIFT 
+#undef CRL_APB_IOPLL_CFG_LFHF_MASK 
+#define CRL_APB_IOPLL_CFG_LFHF_DEFVAL                                              0x00000000
+#define CRL_APB_IOPLL_CFG_LFHF_SHIFT                                               10
+#define CRL_APB_IOPLL_CFG_LFHF_MASK                                                0x00000C00U
+
+/*Lock circuit counter setting*/
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRL_APB_IOPLL_CFG_LOCK_CNT_MASK 
+#define CRL_APB_IOPLL_CFG_LOCK_CNT_DEFVAL                                          0x00000000
+#define CRL_APB_IOPLL_CFG_LOCK_CNT_SHIFT                                           13
+#define CRL_APB_IOPLL_CFG_LOCK_CNT_MASK                                            0x007FE000U
+
+/*Lock circuit configuration settings for lock windowsize*/
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRL_APB_IOPLL_CFG_LOCK_DLY_MASK 
+#define CRL_APB_IOPLL_CFG_LOCK_DLY_DEFVAL                                          0x00000000
+#define CRL_APB_IOPLL_CFG_LOCK_DLY_SHIFT                                           25
+#define CRL_APB_IOPLL_CFG_LOCK_DLY_MASK                                            0xFE000000U
+
+/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_PRE_SRC_MASK 
+#define CRL_APB_IOPLL_CTRL_PRE_SRC_DEFVAL                                          0x00012C09
+#define CRL_APB_IOPLL_CTRL_PRE_SRC_SHIFT                                           20
+#define CRL_APB_IOPLL_CTRL_PRE_SRC_MASK                                            0x00700000U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_FBDIV_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_FBDIV_MASK 
+#define CRL_APB_IOPLL_CTRL_FBDIV_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_FBDIV_SHIFT                                             8
+#define CRL_APB_IOPLL_CTRL_FBDIV_MASK                                              0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRL_APB_IOPLL_CTRL_DIV2_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_DIV2_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_DIV2_MASK 
+#define CRL_APB_IOPLL_CTRL_DIV2_DEFVAL                                             0x00012C09
+#define CRL_APB_IOPLL_CTRL_DIV2_SHIFT                                              16
+#define CRL_APB_IOPLL_CTRL_DIV2_MASK                                               0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
+#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
+#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
+#define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRL_APB_IOPLL_CTRL_RESET_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_RESET_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_RESET_MASK 
+#define CRL_APB_IOPLL_CTRL_RESET_DEFVAL                                            0x00012C09
+#define CRL_APB_IOPLL_CTRL_RESET_SHIFT                                             0
+#define CRL_APB_IOPLL_CTRL_RESET_MASK                                              0x00000001U
+
+/*IOPLL is locked*/
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL 
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT 
+#undef CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK 
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_DEFVAL                                       0x00000018
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_SHIFT                                        0
+#define CRL_APB_PLL_STATUS_IOPLL_LOCK_MASK                                         0x00000001U
+#define CRL_APB_PLL_STATUS_OFFSET                                                  0XFF5E0040
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_SHIFT 
+#undef CRL_APB_IOPLL_CTRL_BYPASS_MASK 
+#define CRL_APB_IOPLL_CTRL_BYPASS_DEFVAL                                           0x00012C09
+#define CRL_APB_IOPLL_CTRL_BYPASS_SHIFT                                            3
+#define CRL_APB_IOPLL_CTRL_BYPASS_MASK                                             0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_DEFVAL                                  0x00000400
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_SHIFT                                   8
+#define CRL_APB_IOPLL_TO_FPD_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
+#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL 
+#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT 
+#undef CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK 
+#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_DEFVAL                                      0x00000000
+#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_SHIFT                                       31
+#define CRL_APB_IOPLL_FRAC_CFG_ENABLED_MASK                                        0x80000000U
+
+/*Fractional value for the Feedback value.*/
+#undef CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL 
+#undef CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT 
+#undef CRL_APB_IOPLL_FRAC_CFG_DATA_MASK 
+#define CRL_APB_IOPLL_FRAC_CFG_DATA_DEFVAL                                         0x00000000
+#define CRL_APB_IOPLL_FRAC_CFG_DATA_SHIFT                                          0
+#define CRL_APB_IOPLL_FRAC_CFG_DATA_MASK                                           0x0000FFFFU
+
+/*PLL loop filter resistor control*/
+#undef CRF_APB_APLL_CFG_RES_DEFVAL 
+#undef CRF_APB_APLL_CFG_RES_SHIFT 
+#undef CRF_APB_APLL_CFG_RES_MASK 
+#define CRF_APB_APLL_CFG_RES_DEFVAL                                                0x00000000
+#define CRF_APB_APLL_CFG_RES_SHIFT                                                 0
+#define CRF_APB_APLL_CFG_RES_MASK                                                  0x0000000FU
+
+/*PLL charge pump control*/
+#undef CRF_APB_APLL_CFG_CP_DEFVAL 
+#undef CRF_APB_APLL_CFG_CP_SHIFT 
+#undef CRF_APB_APLL_CFG_CP_MASK 
+#define CRF_APB_APLL_CFG_CP_DEFVAL                                                 0x00000000
+#define CRF_APB_APLL_CFG_CP_SHIFT                                                  5
+#define CRF_APB_APLL_CFG_CP_MASK                                                   0x000001E0U
+
+/*PLL loop filter high frequency capacitor control*/
+#undef CRF_APB_APLL_CFG_LFHF_DEFVAL 
+#undef CRF_APB_APLL_CFG_LFHF_SHIFT 
+#undef CRF_APB_APLL_CFG_LFHF_MASK 
+#define CRF_APB_APLL_CFG_LFHF_DEFVAL                                               0x00000000
+#define CRF_APB_APLL_CFG_LFHF_SHIFT                                                10
+#define CRF_APB_APLL_CFG_LFHF_MASK                                                 0x00000C00U
+
+/*Lock circuit counter setting*/
+#undef CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRF_APB_APLL_CFG_LOCK_CNT_SHIFT 
+#undef CRF_APB_APLL_CFG_LOCK_CNT_MASK 
+#define CRF_APB_APLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
+#define CRF_APB_APLL_CFG_LOCK_CNT_SHIFT                                            13
+#define CRF_APB_APLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
+
+/*Lock circuit configuration settings for lock windowsize*/
+#undef CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRF_APB_APLL_CFG_LOCK_DLY_SHIFT 
+#undef CRF_APB_APLL_CFG_LOCK_DLY_MASK 
+#define CRF_APB_APLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
+#define CRF_APB_APLL_CFG_LOCK_DLY_SHIFT                                            25
+#define CRF_APB_APLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
+
+/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
+#undef CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRF_APB_APLL_CTRL_PRE_SRC_SHIFT 
+#undef CRF_APB_APLL_CTRL_PRE_SRC_MASK 
+#define CRF_APB_APLL_CTRL_PRE_SRC_DEFVAL                                           0x00012C09
+#define CRF_APB_APLL_CTRL_PRE_SRC_SHIFT                                            20
+#define CRF_APB_APLL_CTRL_PRE_SRC_MASK                                             0x00700000U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_APLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_APLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_APLL_CTRL_FBDIV_MASK 
+#define CRF_APB_APLL_CTRL_FBDIV_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_APLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_APLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_APLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_APLL_CTRL_DIV2_MASK 
+#define CRF_APB_APLL_CTRL_DIV2_DEFVAL                                              0x00012C09
+#define CRF_APB_APLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_APLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_APLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_APLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_APLL_CTRL_RESET_MASK 
+#define CRF_APB_APLL_CTRL_RESET_DEFVAL                                             0x00012C09
+#define CRF_APB_APLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_APLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*APLL is locked*/
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_APLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_APLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_APLL_LOCK_SHIFT                                         0
+#define CRF_APB_PLL_STATUS_APLL_LOCK_MASK                                          0x00000001U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_APLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_APLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_APLL_CTRL_BYPASS_MASK 
+#define CRF_APB_APLL_CTRL_BYPASS_DEFVAL                                            0x00012C09
+#define CRF_APB_APLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_APLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_APLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
+#undef CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL 
+#undef CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT 
+#undef CRF_APB_APLL_FRAC_CFG_ENABLED_MASK 
+#define CRF_APB_APLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
+#define CRF_APB_APLL_FRAC_CFG_ENABLED_SHIFT                                        31
+#define CRF_APB_APLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
+
+/*Fractional value for the Feedback value.*/
+#undef CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL 
+#undef CRF_APB_APLL_FRAC_CFG_DATA_SHIFT 
+#undef CRF_APB_APLL_FRAC_CFG_DATA_MASK 
+#define CRF_APB_APLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
+#define CRF_APB_APLL_FRAC_CFG_DATA_SHIFT                                           0
+#define CRF_APB_APLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
+
+/*PLL loop filter resistor control*/
+#undef CRF_APB_DPLL_CFG_RES_DEFVAL 
+#undef CRF_APB_DPLL_CFG_RES_SHIFT 
+#undef CRF_APB_DPLL_CFG_RES_MASK 
+#define CRF_APB_DPLL_CFG_RES_DEFVAL                                                0x00000000
+#define CRF_APB_DPLL_CFG_RES_SHIFT                                                 0
+#define CRF_APB_DPLL_CFG_RES_MASK                                                  0x0000000FU
+
+/*PLL charge pump control*/
+#undef CRF_APB_DPLL_CFG_CP_DEFVAL 
+#undef CRF_APB_DPLL_CFG_CP_SHIFT 
+#undef CRF_APB_DPLL_CFG_CP_MASK 
+#define CRF_APB_DPLL_CFG_CP_DEFVAL                                                 0x00000000
+#define CRF_APB_DPLL_CFG_CP_SHIFT                                                  5
+#define CRF_APB_DPLL_CFG_CP_MASK                                                   0x000001E0U
+
+/*PLL loop filter high frequency capacitor control*/
+#undef CRF_APB_DPLL_CFG_LFHF_DEFVAL 
+#undef CRF_APB_DPLL_CFG_LFHF_SHIFT 
+#undef CRF_APB_DPLL_CFG_LFHF_MASK 
+#define CRF_APB_DPLL_CFG_LFHF_DEFVAL                                               0x00000000
+#define CRF_APB_DPLL_CFG_LFHF_SHIFT                                                10
+#define CRF_APB_DPLL_CFG_LFHF_MASK                                                 0x00000C00U
+
+/*Lock circuit counter setting*/
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRF_APB_DPLL_CFG_LOCK_CNT_MASK 
+#define CRF_APB_DPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
+#define CRF_APB_DPLL_CFG_LOCK_CNT_SHIFT                                            13
+#define CRF_APB_DPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
+
+/*Lock circuit configuration settings for lock windowsize*/
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRF_APB_DPLL_CFG_LOCK_DLY_MASK 
+#define CRF_APB_DPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
+#define CRF_APB_DPLL_CFG_LOCK_DLY_SHIFT                                            25
+#define CRF_APB_DPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
+
+/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRF_APB_DPLL_CTRL_PRE_SRC_MASK 
+#define CRF_APB_DPLL_CTRL_PRE_SRC_DEFVAL                                           0x00002C09
+#define CRF_APB_DPLL_CTRL_PRE_SRC_SHIFT                                            20
+#define CRF_APB_DPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_DPLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_DPLL_CTRL_FBDIV_MASK 
+#define CRF_APB_DPLL_CTRL_FBDIV_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_DPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_DPLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_DPLL_CTRL_DIV2_MASK 
+#define CRF_APB_DPLL_CTRL_DIV2_DEFVAL                                              0x00002C09
+#define CRF_APB_DPLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_DPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
+#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_DPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_DPLL_CTRL_RESET_MASK 
+#define CRF_APB_DPLL_CTRL_RESET_DEFVAL                                             0x00002C09
+#define CRF_APB_DPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_DPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*DPLL is locked*/
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_DPLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_SHIFT                                         1
+#define CRF_APB_PLL_STATUS_DPLL_LOCK_MASK                                          0x00000002U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_DPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_DPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_DPLL_CTRL_BYPASS_DEFVAL                                            0x00002C09
+#define CRF_APB_DPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_DPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_DPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
+#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL 
+#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT 
+#undef CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK 
+#define CRF_APB_DPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
+#define CRF_APB_DPLL_FRAC_CFG_ENABLED_SHIFT                                        31
+#define CRF_APB_DPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
+
+/*Fractional value for the Feedback value.*/
+#undef CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL 
+#undef CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT 
+#undef CRF_APB_DPLL_FRAC_CFG_DATA_MASK 
+#define CRF_APB_DPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
+#define CRF_APB_DPLL_FRAC_CFG_DATA_SHIFT                                           0
+#define CRF_APB_DPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
+
+/*PLL loop filter resistor control*/
+#undef CRF_APB_VPLL_CFG_RES_DEFVAL 
+#undef CRF_APB_VPLL_CFG_RES_SHIFT 
+#undef CRF_APB_VPLL_CFG_RES_MASK 
+#define CRF_APB_VPLL_CFG_RES_DEFVAL                                                0x00000000
+#define CRF_APB_VPLL_CFG_RES_SHIFT                                                 0
+#define CRF_APB_VPLL_CFG_RES_MASK                                                  0x0000000FU
+
+/*PLL charge pump control*/
+#undef CRF_APB_VPLL_CFG_CP_DEFVAL 
+#undef CRF_APB_VPLL_CFG_CP_SHIFT 
+#undef CRF_APB_VPLL_CFG_CP_MASK 
+#define CRF_APB_VPLL_CFG_CP_DEFVAL                                                 0x00000000
+#define CRF_APB_VPLL_CFG_CP_SHIFT                                                  5
+#define CRF_APB_VPLL_CFG_CP_MASK                                                   0x000001E0U
+
+/*PLL loop filter high frequency capacitor control*/
+#undef CRF_APB_VPLL_CFG_LFHF_DEFVAL 
+#undef CRF_APB_VPLL_CFG_LFHF_SHIFT 
+#undef CRF_APB_VPLL_CFG_LFHF_MASK 
+#define CRF_APB_VPLL_CFG_LFHF_DEFVAL                                               0x00000000
+#define CRF_APB_VPLL_CFG_LFHF_SHIFT                                                10
+#define CRF_APB_VPLL_CFG_LFHF_MASK                                                 0x00000C00U
+
+/*Lock circuit counter setting*/
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL 
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT 
+#undef CRF_APB_VPLL_CFG_LOCK_CNT_MASK 
+#define CRF_APB_VPLL_CFG_LOCK_CNT_DEFVAL                                           0x00000000
+#define CRF_APB_VPLL_CFG_LOCK_CNT_SHIFT                                            13
+#define CRF_APB_VPLL_CFG_LOCK_CNT_MASK                                             0x007FE000U
+
+/*Lock circuit configuration settings for lock windowsize*/
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL 
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT 
+#undef CRF_APB_VPLL_CFG_LOCK_DLY_MASK 
+#define CRF_APB_VPLL_CFG_LOCK_DLY_DEFVAL                                           0x00000000
+#define CRF_APB_VPLL_CFG_LOCK_DLY_SHIFT                                            25
+#define CRF_APB_VPLL_CFG_LOCK_DLY_MASK                                             0xFE000000U
+
+/*Mux select for determining which clock feeds this PLL. 0XX pss_ref_clk is the source 100 video clk is the source 101 pss_alt_
+		ef_clk is the source 110 aux_refclk[X] is the source 111 gt_crx_ref_clk is the source*/
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT 
+#undef CRF_APB_VPLL_CTRL_PRE_SRC_MASK 
+#define CRF_APB_VPLL_CTRL_PRE_SRC_DEFVAL                                           0x00012809
+#define CRF_APB_VPLL_CTRL_PRE_SRC_SHIFT                                            20
+#define CRF_APB_VPLL_CTRL_PRE_SRC_MASK                                             0x00700000U
+
+/*The integer portion of the feedback divider to the PLL*/
+#undef CRF_APB_VPLL_CTRL_FBDIV_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_FBDIV_SHIFT 
+#undef CRF_APB_VPLL_CTRL_FBDIV_MASK 
+#define CRF_APB_VPLL_CTRL_FBDIV_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_FBDIV_SHIFT                                              8
+#define CRF_APB_VPLL_CTRL_FBDIV_MASK                                               0x00007F00U
+
+/*This turns on the divide by 2 that is inside of the PLL. This does not change the VCO frequency, just the output frequency*/
+#undef CRF_APB_VPLL_CTRL_DIV2_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_DIV2_SHIFT 
+#undef CRF_APB_VPLL_CTRL_DIV2_MASK 
+#define CRF_APB_VPLL_CTRL_DIV2_DEFVAL                                              0x00012809
+#define CRF_APB_VPLL_CTRL_DIV2_SHIFT                                               16
+#define CRF_APB_VPLL_CTRL_DIV2_MASK                                                0x00010000U
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
+#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*Asserts Reset to the PLL. When asserting reset, the PLL must already be in BYPASS.*/
+#undef CRF_APB_VPLL_CTRL_RESET_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_RESET_SHIFT 
+#undef CRF_APB_VPLL_CTRL_RESET_MASK 
+#define CRF_APB_VPLL_CTRL_RESET_DEFVAL                                             0x00012809
+#define CRF_APB_VPLL_CTRL_RESET_SHIFT                                              0
+#define CRF_APB_VPLL_CTRL_RESET_MASK                                               0x00000001U
+
+/*VPLL is locked*/
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL 
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT 
+#undef CRF_APB_PLL_STATUS_VPLL_LOCK_MASK 
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_DEFVAL                                        0x00000038
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_SHIFT                                         2
+#define CRF_APB_PLL_STATUS_VPLL_LOCK_MASK                                          0x00000004U
+#define CRF_APB_PLL_STATUS_OFFSET                                                  0XFD1A0044
+
+/*Bypasses the PLL clock. The usable clock will be determined from the POST_SRC field. (This signal may only be toggled after 4
+		cycles of the old clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_VPLL_CTRL_BYPASS_DEFVAL 
+#undef CRF_APB_VPLL_CTRL_BYPASS_SHIFT 
+#undef CRF_APB_VPLL_CTRL_BYPASS_MASK 
+#define CRF_APB_VPLL_CTRL_BYPASS_DEFVAL                                            0x00012809
+#define CRF_APB_VPLL_CTRL_BYPASS_SHIFT                                             3
+#define CRF_APB_VPLL_CTRL_BYPASS_MASK                                              0x00000008U
+
+/*Divisor value for this clock.*/
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_DEFVAL                                   0x00000400
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_VPLL_TO_LPD_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*Fractional SDM bypass control. When 0, PLL is in integer mode and it ignores all fractional data. When 1, PLL is in fractiona
+		 mode and uses DATA of this register for the fractional portion of the feedback divider.*/
+#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL 
+#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT 
+#undef CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK 
+#define CRF_APB_VPLL_FRAC_CFG_ENABLED_DEFVAL                                       0x00000000
+#define CRF_APB_VPLL_FRAC_CFG_ENABLED_SHIFT                                        31
+#define CRF_APB_VPLL_FRAC_CFG_ENABLED_MASK                                         0x80000000U
+
+/*Fractional value for the Feedback value.*/
+#undef CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL 
+#undef CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT 
+#undef CRF_APB_VPLL_FRAC_CFG_DATA_MASK 
+#define CRF_APB_VPLL_FRAC_CFG_DATA_DEFVAL                                          0x00000000
+#define CRF_APB_VPLL_FRAC_CFG_DATA_SHIFT                                           0
+#define CRF_APB_VPLL_FRAC_CFG_DATA_MASK                                            0x0000FFFFU
+#undef CRL_APB_GEM0_REF_CTRL_OFFSET 
+#define CRL_APB_GEM0_REF_CTRL_OFFSET                                               0XFF5E0050
+#undef CRL_APB_GEM1_REF_CTRL_OFFSET 
+#define CRL_APB_GEM1_REF_CTRL_OFFSET                                               0XFF5E0054
+#undef CRL_APB_GEM2_REF_CTRL_OFFSET 
+#define CRL_APB_GEM2_REF_CTRL_OFFSET                                               0XFF5E0058
+#undef CRL_APB_GEM3_REF_CTRL_OFFSET 
+#define CRL_APB_GEM3_REF_CTRL_OFFSET                                               0XFF5E005C
+#undef CRL_APB_GEM_TSU_REF_CTRL_OFFSET 
+#define CRL_APB_GEM_TSU_REF_CTRL_OFFSET                                            0XFF5E0100
+#undef CRL_APB_USB0_BUS_REF_CTRL_OFFSET 
+#define CRL_APB_USB0_BUS_REF_CTRL_OFFSET                                           0XFF5E0060
+#undef CRL_APB_USB1_BUS_REF_CTRL_OFFSET 
+#define CRL_APB_USB1_BUS_REF_CTRL_OFFSET                                           0XFF5E0064
+#undef CRL_APB_USB3_DUAL_REF_CTRL_OFFSET 
+#define CRL_APB_USB3_DUAL_REF_CTRL_OFFSET                                          0XFF5E004C
+#undef CRL_APB_QSPI_REF_CTRL_OFFSET 
+#define CRL_APB_QSPI_REF_CTRL_OFFSET                                               0XFF5E0068
+#undef CRL_APB_SDIO0_REF_CTRL_OFFSET 
+#define CRL_APB_SDIO0_REF_CTRL_OFFSET                                              0XFF5E006C
+#undef CRL_APB_SDIO1_REF_CTRL_OFFSET 
+#define CRL_APB_SDIO1_REF_CTRL_OFFSET                                              0XFF5E0070
+#undef IOU_SLCR_SDIO_CLK_CTRL_OFFSET 
+#define IOU_SLCR_SDIO_CLK_CTRL_OFFSET                                              0XFF18030C
+#undef CRL_APB_UART0_REF_CTRL_OFFSET 
+#define CRL_APB_UART0_REF_CTRL_OFFSET                                              0XFF5E0074
+#undef CRL_APB_UART1_REF_CTRL_OFFSET 
+#define CRL_APB_UART1_REF_CTRL_OFFSET                                              0XFF5E0078
+#undef CRL_APB_I2C0_REF_CTRL_OFFSET 
+#define CRL_APB_I2C0_REF_CTRL_OFFSET                                               0XFF5E0120
+#undef CRL_APB_I2C1_REF_CTRL_OFFSET 
+#define CRL_APB_I2C1_REF_CTRL_OFFSET                                               0XFF5E0124
+#undef CRL_APB_SPI0_REF_CTRL_OFFSET 
+#define CRL_APB_SPI0_REF_CTRL_OFFSET                                               0XFF5E007C
+#undef CRL_APB_SPI1_REF_CTRL_OFFSET 
+#define CRL_APB_SPI1_REF_CTRL_OFFSET                                               0XFF5E0080
+#undef CRL_APB_CAN0_REF_CTRL_OFFSET 
+#define CRL_APB_CAN0_REF_CTRL_OFFSET                                               0XFF5E0084
+#undef CRL_APB_CAN1_REF_CTRL_OFFSET 
+#define CRL_APB_CAN1_REF_CTRL_OFFSET                                               0XFF5E0088
+#undef CRL_APB_CPU_R5_CTRL_OFFSET 
+#define CRL_APB_CPU_R5_CTRL_OFFSET                                                 0XFF5E0090
+#undef CRL_APB_IOU_SWITCH_CTRL_OFFSET 
+#define CRL_APB_IOU_SWITCH_CTRL_OFFSET                                             0XFF5E009C
+#undef CRL_APB_CSU_PLL_CTRL_OFFSET 
+#define CRL_APB_CSU_PLL_CTRL_OFFSET                                                0XFF5E00A0
+#undef CRL_APB_PCAP_CTRL_OFFSET 
+#define CRL_APB_PCAP_CTRL_OFFSET                                                   0XFF5E00A4
+#undef CRL_APB_LPD_SWITCH_CTRL_OFFSET 
+#define CRL_APB_LPD_SWITCH_CTRL_OFFSET                                             0XFF5E00A8
+#undef CRL_APB_LPD_LSBUS_CTRL_OFFSET 
+#define CRL_APB_LPD_LSBUS_CTRL_OFFSET                                              0XFF5E00AC
+#undef CRL_APB_DBG_LPD_CTRL_OFFSET 
+#define CRL_APB_DBG_LPD_CTRL_OFFSET                                                0XFF5E00B0
+#undef CRL_APB_NAND_REF_CTRL_OFFSET 
+#define CRL_APB_NAND_REF_CTRL_OFFSET                                               0XFF5E00B4
+#undef CRL_APB_ADMA_REF_CTRL_OFFSET 
+#define CRL_APB_ADMA_REF_CTRL_OFFSET                                               0XFF5E00B8
+#undef CRL_APB_PL0_REF_CTRL_OFFSET 
+#define CRL_APB_PL0_REF_CTRL_OFFSET                                                0XFF5E00C0
+#undef CRL_APB_PL1_REF_CTRL_OFFSET 
+#define CRL_APB_PL1_REF_CTRL_OFFSET                                                0XFF5E00C4
+#undef CRL_APB_PL2_REF_CTRL_OFFSET 
+#define CRL_APB_PL2_REF_CTRL_OFFSET                                                0XFF5E00C8
+#undef CRL_APB_PL3_REF_CTRL_OFFSET 
+#define CRL_APB_PL3_REF_CTRL_OFFSET                                                0XFF5E00CC
+#undef CRL_APB_AMS_REF_CTRL_OFFSET 
+#define CRL_APB_AMS_REF_CTRL_OFFSET                                                0XFF5E0108
+#undef CRL_APB_DLL_REF_CTRL_OFFSET 
+#define CRL_APB_DLL_REF_CTRL_OFFSET                                                0XFF5E0104
+#undef CRL_APB_TIMESTAMP_REF_CTRL_OFFSET 
+#define CRL_APB_TIMESTAMP_REF_CTRL_OFFSET                                          0XFF5E0128
+#undef CRF_APB_SATA_REF_CTRL_OFFSET 
+#define CRF_APB_SATA_REF_CTRL_OFFSET                                               0XFD1A00A0
+#undef CRF_APB_PCIE_REF_CTRL_OFFSET 
+#define CRF_APB_PCIE_REF_CTRL_OFFSET                                               0XFD1A00B4
+#undef CRF_APB_DP_VIDEO_REF_CTRL_OFFSET 
+#define CRF_APB_DP_VIDEO_REF_CTRL_OFFSET                                           0XFD1A0070
+#undef CRF_APB_DP_AUDIO_REF_CTRL_OFFSET 
+#define CRF_APB_DP_AUDIO_REF_CTRL_OFFSET                                           0XFD1A0074
+#undef CRF_APB_DP_STC_REF_CTRL_OFFSET 
+#define CRF_APB_DP_STC_REF_CTRL_OFFSET                                             0XFD1A007C
+#undef CRF_APB_ACPU_CTRL_OFFSET 
+#define CRF_APB_ACPU_CTRL_OFFSET                                                   0XFD1A0060
+#undef CRF_APB_DBG_TRACE_CTRL_OFFSET 
+#define CRF_APB_DBG_TRACE_CTRL_OFFSET                                              0XFD1A0064
+#undef CRF_APB_DBG_FPD_CTRL_OFFSET 
+#define CRF_APB_DBG_FPD_CTRL_OFFSET                                                0XFD1A0068
+#undef CRF_APB_DDR_CTRL_OFFSET 
+#define CRF_APB_DDR_CTRL_OFFSET                                                    0XFD1A0080
+#undef CRF_APB_GPU_REF_CTRL_OFFSET 
+#define CRF_APB_GPU_REF_CTRL_OFFSET                                                0XFD1A0084
+#undef CRF_APB_GDMA_REF_CTRL_OFFSET 
+#define CRF_APB_GDMA_REF_CTRL_OFFSET                                               0XFD1A00B8
+#undef CRF_APB_DPDMA_REF_CTRL_OFFSET 
+#define CRF_APB_DPDMA_REF_CTRL_OFFSET                                              0XFD1A00BC
+#undef CRF_APB_TOPSW_MAIN_CTRL_OFFSET 
+#define CRF_APB_TOPSW_MAIN_CTRL_OFFSET                                             0XFD1A00C0
+#undef CRF_APB_TOPSW_LSBUS_CTRL_OFFSET 
+#define CRF_APB_TOPSW_LSBUS_CTRL_OFFSET                                            0XFD1A00C4
+#undef CRF_APB_GTGREF0_REF_CTRL_OFFSET 
+#define CRF_APB_GTGREF0_REF_CTRL_OFFSET                                            0XFD1A00C8
+#undef CRF_APB_DBG_TSTMP_CTRL_OFFSET 
+#define CRF_APB_DBG_TSTMP_CTRL_OFFSET                                              0XFD1A00F8
+#undef IOU_SLCR_IOU_TTC_APB_CLK_OFFSET 
+#define IOU_SLCR_IOU_TTC_APB_CLK_OFFSET                                            0XFF180380
+#undef FPD_SLCR_WDT_CLK_SEL_OFFSET 
+#define FPD_SLCR_WDT_CLK_SEL_OFFSET                                                0XFD610100
+#undef IOU_SLCR_WDT_CLK_SEL_OFFSET 
+#define IOU_SLCR_WDT_CLK_SEL_OFFSET                                                0XFF180300
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET 
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_OFFSET                                         0XFF410050
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM0_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM0_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM1_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM1_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM2_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM2_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM2_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM2_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active for the RX channel*/
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK 
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_DEFVAL                                     0x00002500
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_SHIFT                                      26
+#define CRL_APB_GEM3_REF_CTRL_RX_CLKACT_MASK                                       0x04000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_DEFVAL                                        0x00002500
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_SHIFT                                         25
+#define CRL_APB_GEM3_REF_CTRL_CLKACT_MASK                                          0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_DEFVAL                                      0x00002500
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002500
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_GEM3_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_DEFVAL                                        0x00002500
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_GEM3_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_DEFVAL                                   0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_SHIFT                                    8
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_DEFVAL                                     0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_SHIFT                                      0
+#define CRL_APB_GEM_TSU_REF_CTRL_SRCSEL_MASK                                       0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_DEFVAL                                   0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_SHIFT                                    16
+#define CRL_APB_GEM_TSU_REF_CTRL_DIVISOR1_MASK                                     0x003F0000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_DEFVAL                                     0x00051000
+#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_SHIFT                                      24
+#define CRL_APB_GEM_TSU_REF_CTRL_CLKACT_MASK                                       0x01000000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_DEFVAL                                    0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_SHIFT                                     25
+#define CRL_APB_USB0_BUS_REF_CTRL_CLKACT_MASK                                      0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_DEFVAL                                  0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_DEFVAL                                  0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRL_APB_USB0_BUS_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_DEFVAL                                    0x00052000
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRL_APB_USB0_BUS_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_DEFVAL                                    0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_SHIFT                                     25
+#define CRL_APB_USB1_BUS_REF_CTRL_CLKACT_MASK                                      0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_DEFVAL                                  0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_DEFVAL                                  0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRL_APB_USB1_BUS_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_DEFVAL                                    0x00052000
+#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRL_APB_USB1_BUS_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_DEFVAL                                   0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_SHIFT                                    25
+#define CRL_APB_USB3_DUAL_REF_CTRL_CLKACT_MASK                                     0x02000000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_DEFVAL                                 0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_SHIFT                                  16
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR1_MASK                                   0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_DEFVAL                                 0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_SHIFT                                  8
+#define CRL_APB_USB3_DUAL_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL. (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_DEFVAL                                   0x00052000
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_SHIFT                                    0
+#define CRL_APB_USB3_DUAL_REF_CTRL_SRCSEL_MASK                                     0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_DEFVAL                                        0x01000800
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_QSPI_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000800
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000800
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_QSPI_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_DEFVAL                                        0x01000800
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_QSPI_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_SDIO0_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_SDIO0_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_SDIO0_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_SDIO1_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_SDIO1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_DEFVAL                                       0x01000F00
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_SDIO1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*MIO pad selection for sdio1_rx_clk (feedback clock from the PAD) 0: MIO [51] 1: MIO [76]*/
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL 
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT 
+#undef IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK 
+#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_DEFVAL                             0x00000000
+#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_SHIFT                              17
+#define IOU_SLCR_SDIO_CLK_CTRL_SDIO1_RX_SRC_SEL_MASK                               0x00020000U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_UART0_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_UART0_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_UART0_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_UART0_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_UART0_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_UART0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_UART0_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_UART1_REF_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_UART1_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_UART1_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_DEFVAL                                     0x01001800
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_SHIFT                                      16
+#define CRL_APB_UART1_REF_CTRL_DIVISOR1_MASK                                       0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_UART1_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_UART1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_UART1_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_I2C0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_I2C0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_I2C0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_I2C1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01000500
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_I2C1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_I2C1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_SPI0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_SPI0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_SPI0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_SPI1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_SPI1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_SPI1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_CAN0_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_CAN0_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_CAN0_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_DEFVAL                                        0x01001800
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_CAN1_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_DEFVAL                                      0x01001800
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001800
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_CAN1_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_DEFVAL                                        0x01001800
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_CAN1_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Turing this off will shut down the OCM, some parts of the APM, and prevent transactions going from the FPD to the LPD and cou
+		d lead to system hang*/
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_CLKACT_MASK 
+#define CRL_APB_CPU_R5_CTRL_CLKACT_DEFVAL                                          0x03000600
+#define CRL_APB_CPU_R5_CTRL_CLKACT_SHIFT                                           24
+#define CRL_APB_CPU_R5_CTRL_CLKACT_MASK                                            0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_DEFVAL                                        0x03000600
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_SHIFT                                         8
+#define CRL_APB_CPU_R5_CTRL_DIVISOR0_MASK                                          0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CPU_R5_CTRL_SRCSEL_MASK 
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_DEFVAL                                          0x03000600
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_SHIFT                                           0
+#define CRL_APB_CPU_R5_CTRL_SRCSEL_MASK                                            0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_DEFVAL                                      0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_SHIFT                                       24
+#define CRL_APB_IOU_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
+#define CRL_APB_IOU_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK 
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x00001500
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_SHIFT                                       0
+#define CRL_APB_IOU_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_CSU_PLL_CTRL_CLKACT_MASK 
+#define CRL_APB_CSU_PLL_CTRL_CLKACT_DEFVAL                                         0x01001500
+#define CRL_APB_CSU_PLL_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_CSU_PLL_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK 
+#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_DEFVAL                                       0x01001500
+#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_CSU_PLL_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK 
+#define CRL_APB_CSU_PLL_CTRL_SRCSEL_DEFVAL                                         0x01001500
+#define CRL_APB_CSU_PLL_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_CSU_PLL_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PCAP_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PCAP_CTRL_CLKACT_MASK 
+#define CRL_APB_PCAP_CTRL_CLKACT_DEFVAL                                            0x00001500
+#define CRL_APB_PCAP_CTRL_CLKACT_SHIFT                                             24
+#define CRL_APB_PCAP_CTRL_CLKACT_MASK                                              0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PCAP_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PCAP_CTRL_DIVISOR0_DEFVAL                                          0x00001500
+#define CRL_APB_PCAP_CTRL_DIVISOR0_SHIFT                                           8
+#define CRL_APB_PCAP_CTRL_DIVISOR0_MASK                                            0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PCAP_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PCAP_CTRL_SRCSEL_MASK 
+#define CRL_APB_PCAP_CTRL_SRCSEL_DEFVAL                                            0x00001500
+#define CRL_APB_PCAP_CTRL_SRCSEL_SHIFT                                             0
+#define CRL_APB_PCAP_CTRL_SRCSEL_MASK                                              0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_DEFVAL                                      0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_SHIFT                                       24
+#define CRL_APB_LPD_SWITCH_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_DEFVAL                                    0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_SHIFT                                     8
+#define CRL_APB_LPD_SWITCH_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK 
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_DEFVAL                                      0x01000500
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_SHIFT                                       0
+#define CRL_APB_LPD_SWITCH_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_DEFVAL                                       0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_SHIFT                                        24
+#define CRL_APB_LPD_LSBUS_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_DEFVAL                                     0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_SHIFT                                      8
+#define CRL_APB_LPD_LSBUS_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK 
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_DEFVAL                                       0x01001800
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_SHIFT                                        0
+#define CRL_APB_LPD_LSBUS_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_CLKACT_MASK 
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_DEFVAL                                         0x01002000
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_DBG_LPD_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK 
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_DEFVAL                                       0x01002000
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_DBG_LPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK 
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_DEFVAL                                         0x01002000
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_DBG_LPD_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_NAND_REF_CTRL_CLKACT_DEFVAL                                        0x00052000
+#define CRL_APB_NAND_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_NAND_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_DEFVAL                                      0x00052000
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_SHIFT                                       16
+#define CRL_APB_NAND_REF_CTRL_DIVISOR1_MASK                                        0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_DEFVAL                                      0x00052000
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_NAND_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_NAND_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_DEFVAL                                        0x00052000
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_NAND_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_DEFVAL                                        0x00002000
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRL_APB_ADMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x00002000
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRL_APB_ADMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_DEFVAL                                        0x00002000
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRL_APB_ADMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_PL0_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
+#define CRL_APB_PL0_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_PL0_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_PL0_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
+#define CRL_APB_PL0_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_PL0_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PL0_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
+#define CRL_APB_PL0_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_PL0_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PL0_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_PL0_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
+#define CRL_APB_PL0_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_PL0_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PL1_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_PL1_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
+#define CRL_APB_PL1_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_PL1_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_PL1_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
+#define CRL_APB_PL1_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_PL1_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PL1_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
+#define CRL_APB_PL1_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_PL1_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PL1_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_PL1_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
+#define CRL_APB_PL1_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_PL1_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PL2_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_PL2_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
+#define CRL_APB_PL2_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_PL2_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_PL2_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
+#define CRL_APB_PL2_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_PL2_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PL2_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
+#define CRL_APB_PL2_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_PL2_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PL2_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_PL2_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
+#define CRL_APB_PL2_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_PL2_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_PL3_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_PL3_REF_CTRL_CLKACT_DEFVAL                                         0x00052000
+#define CRL_APB_PL3_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_PL3_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_PL3_REF_CTRL_DIVISOR1_DEFVAL                                       0x00052000
+#define CRL_APB_PL3_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_PL3_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_PL3_REF_CTRL_DIVISOR0_DEFVAL                                       0x00052000
+#define CRL_APB_PL3_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_PL3_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_PL3_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_PL3_REF_CTRL_SRCSEL_DEFVAL                                         0x00052000
+#define CRL_APB_PL3_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_PL3_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_DEFVAL                                       0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_SHIFT                                        16
+#define CRL_APB_AMS_REF_CTRL_DIVISOR1_MASK                                         0x003F0000U
+
+/*6 bit divider*/
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_DEFVAL                                       0x01001800
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRL_APB_AMS_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = RPLL; 010 = IOPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new
+		clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_DEFVAL                                         0x01001800
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_AMS_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_AMS_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_AMS_REF_CTRL_CLKACT_DEFVAL                                         0x01001800
+#define CRL_APB_AMS_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRL_APB_AMS_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*000 = IOPLL; 001 = RPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This
+		is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_DLL_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_DEFVAL                                         0x00000000
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRL_APB_DLL_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*6 bit divider*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_DEFVAL                                 0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_SHIFT                                  8
+#define CRL_APB_TIMESTAMP_REF_CTRL_DIVISOR0_MASK                                   0x00003F00U
+
+/*1XX = pss_ref_clk; 000 = IOPLL; 010 = RPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 
+		 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_DEFVAL                                   0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_SHIFT                                    0
+#define CRL_APB_TIMESTAMP_REF_CTRL_SRCSEL_MASK                                     0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT 
+#undef CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK 
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_DEFVAL                                   0x00001800
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_SHIFT                                    24
+#define CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_MASK                                     0x01000000U
+
+/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_SATA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_SATA_REF_CTRL_SRCSEL_DEFVAL                                        0x01001600
+#define CRF_APB_SATA_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRF_APB_SATA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_SATA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_SATA_REF_CTRL_CLKACT_DEFVAL                                        0x01001600
+#define CRF_APB_SATA_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRF_APB_SATA_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_SATA_REF_CTRL_DIVISOR0_DEFVAL                                      0x01001600
+#define CRF_APB_SATA_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRF_APB_SATA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = RPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cyc
+		es of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_DEFVAL                                        0x00001500
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRF_APB_PCIE_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_DEFVAL                                        0x00001500
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRF_APB_PCIE_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_DEFVAL                                      0x00001500
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRF_APB_PCIE_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRF_APB_DP_VIDEO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 
+		ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_DEFVAL                                    0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRF_APB_DP_VIDEO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_DEFVAL                                    0x01002300
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_SHIFT                                     24
+#define CRF_APB_DP_VIDEO_REF_CTRL_CLKACT_MASK                                      0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_DEFVAL                                  0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_SHIFT                                   16
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR1_MASK                                    0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_DEFVAL                                  0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_SHIFT                                   8
+#define CRF_APB_DP_AUDIO_REF_CTRL_DIVISOR0_MASK                                    0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD - might be using extra mux; (This signal may only be toggled after 4 cycles of the 
+		ld clock and 4 cycles of the new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_DEFVAL                                    0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_SHIFT                                     0
+#define CRF_APB_DP_AUDIO_REF_CTRL_SRCSEL_MASK                                      0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_DEFVAL                                    0x01032300
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_SHIFT                                     24
+#define CRF_APB_DP_AUDIO_REF_CTRL_CLKACT_MASK                                      0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_DEFVAL                                    0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_SHIFT                                     16
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR1_MASK                                      0x003F0000U
+
+/*6 bit divider*/
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_DEFVAL                                    0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_SHIFT                                     8
+#define CRF_APB_DP_STC_REF_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = VPLL; 010 = DPLL; 011 = RPLL_TO_FPD; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of t
+		e new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_DEFVAL                                      0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_SHIFT                                       0
+#define CRF_APB_DP_STC_REF_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_DEFVAL                                      0x01203200
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_SHIFT                                       24
+#define CRF_APB_DP_STC_REF_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_ACPU_CTRL_DIVISOR0_MASK 
+#define CRF_APB_ACPU_CTRL_DIVISOR0_DEFVAL                                          0x03000400
+#define CRF_APB_ACPU_CTRL_DIVISOR0_SHIFT                                           8
+#define CRF_APB_ACPU_CTRL_DIVISOR0_MASK                                            0x00003F00U
+
+/*000 = APLL; 010 = DPLL; 011 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_ACPU_CTRL_SRCSEL_MASK 
+#define CRF_APB_ACPU_CTRL_SRCSEL_DEFVAL                                            0x03000400
+#define CRF_APB_ACPU_CTRL_SRCSEL_SHIFT                                             0
+#define CRF_APB_ACPU_CTRL_SRCSEL_MASK                                              0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock. For the half speed APU Clock*/
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT 
+#undef CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK 
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_DEFVAL                                       0x03000400
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_SHIFT                                        25
+#define CRF_APB_ACPU_CTRL_CLKACT_HALF_MASK                                         0x02000000U
+
+/*Clock active signal. Switch to 0 to disable the clock. For the full speed ACPUX Clock. This will shut off the high speed cloc
+		 to the entire APU*/
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL 
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT 
+#undef CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK 
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_DEFVAL                                       0x03000400
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_SHIFT                                        24
+#define CRF_APB_ACPU_CTRL_CLKACT_FULL_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_DEFVAL                                     0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DBG_TRACE_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_DEFVAL                                       0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DBG_TRACE_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK 
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_DEFVAL                                       0x00002500
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_SHIFT                                        24
+#define CRF_APB_DBG_TRACE_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_DEFVAL                                       0x01002500
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_SHIFT                                        8
+#define CRF_APB_DBG_FPD_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_DEFVAL                                         0x01002500
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_SHIFT                                          0
+#define CRF_APB_DBG_FPD_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DBG_FPD_CTRL_CLKACT_MASK 
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_DEFVAL                                         0x01002500
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_SHIFT                                          24
+#define CRF_APB_DBG_FPD_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DDR_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DDR_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DDR_CTRL_DIVISOR0_DEFVAL                                           0x01000500
+#define CRF_APB_DDR_CTRL_DIVISOR0_SHIFT                                            8
+#define CRF_APB_DDR_CTRL_DIVISOR0_MASK                                             0x00003F00U
+
+/*000 = DPLL; 001 = VPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new clock. This 
+		s not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DDR_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DDR_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DDR_CTRL_SRCSEL_MASK 
+#define CRF_APB_DDR_CTRL_SRCSEL_DEFVAL                                             0x01000500
+#define CRF_APB_DDR_CTRL_SRCSEL_SHIFT                                              0
+#define CRF_APB_DDR_CTRL_SRCSEL_MASK                                               0x00000007U
+
+/*6 bit divider*/
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_DEFVAL                                       0x00001500
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_SHIFT                                        8
+#define CRF_APB_GPU_REF_CTRL_DIVISOR0_MASK                                         0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_DEFVAL                                         0x00001500
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_SHIFT                                          0
+#define CRF_APB_GPU_REF_CTRL_SRCSEL_MASK                                           0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock, which will stop clock for GPU (and both Pixel Processors).*/
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_CLKACT_DEFVAL                                         0x00001500
+#define CRF_APB_GPU_REF_CTRL_CLKACT_SHIFT                                          24
+#define CRF_APB_GPU_REF_CTRL_CLKACT_MASK                                           0x01000000U
+
+/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_DEFVAL                                     0x00001500
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_SHIFT                                      25
+#define CRF_APB_GPU_REF_CTRL_PP0_CLKACT_MASK                                       0x02000000U
+
+/*Clock active signal for Pixel Processor. Switch to 0 to disable the clock only to this Pixel Processor*/
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL 
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT 
+#undef CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK 
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_DEFVAL                                     0x00001500
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_SHIFT                                      26
+#define CRF_APB_GPU_REF_CTRL_PP1_CLKACT_MASK                                       0x04000000U
+
+/*6 bit divider*/
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_DEFVAL                                      0x01000500
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_SHIFT                                       8
+#define CRF_APB_GDMA_REF_CTRL_DIVISOR0_MASK                                        0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_DEFVAL                                        0x01000500
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_SHIFT                                         0
+#define CRF_APB_GDMA_REF_CTRL_SRCSEL_MASK                                          0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GDMA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_DEFVAL                                        0x01000500
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_SHIFT                                         24
+#define CRF_APB_GDMA_REF_CTRL_CLKACT_MASK                                          0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_DEFVAL                                     0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DPDMA_REF_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_DEFVAL                                       0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DPDMA_REF_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_DEFVAL                                       0x01000500
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_SHIFT                                        24
+#define CRF_APB_DPDMA_REF_CTRL_CLKACT_MASK                                         0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_DEFVAL                                    0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_SHIFT                                     8
+#define CRF_APB_TOPSW_MAIN_CTRL_DIVISOR0_MASK                                      0x00003F00U
+
+/*000 = APLL; 010 = VPLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of the new 
+		lock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_DEFVAL                                      0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_SHIFT                                       0
+#define CRF_APB_TOPSW_MAIN_CTRL_SRCSEL_MASK                                        0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK 
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_DEFVAL                                      0x01000400
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_SHIFT                                       24
+#define CRF_APB_TOPSW_MAIN_CTRL_CLKACT_MASK                                        0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_DEFVAL                                   0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_TOPSW_LSBUS_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*000 = APLL; 010 = IOPLL_TO_FPD; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_DEFVAL                                     0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_SHIFT                                      0
+#define CRF_APB_TOPSW_LSBUS_CTRL_SRCSEL_MASK                                       0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK 
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_DEFVAL                                     0x01000800
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_SHIFT                                      24
+#define CRF_APB_TOPSW_LSBUS_CTRL_CLKACT_MASK                                       0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_DEFVAL                                   0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_SHIFT                                    8
+#define CRF_APB_GTGREF0_REF_CTRL_DIVISOR0_MASK                                     0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = APLL; 011 = DPLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_DEFVAL                                     0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_SHIFT                                      0
+#define CRF_APB_GTGREF0_REF_CTRL_SRCSEL_MASK                                       0x00000007U
+
+/*Clock active signal. Switch to 0 to disable the clock*/
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL 
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT 
+#undef CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK 
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_DEFVAL                                     0x00000800
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_SHIFT                                      24
+#define CRF_APB_GTGREF0_REF_CTRL_CLKACT_MASK                                       0x01000000U
+
+/*6 bit divider*/
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL 
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT 
+#undef CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK 
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_DEFVAL                                     0x00000A00
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_SHIFT                                      8
+#define CRF_APB_DBG_TSTMP_CTRL_DIVISOR0_MASK                                       0x00003F00U
+
+/*000 = IOPLL_TO_FPD; 010 = DPLL; 011 = APLL; (This signal may only be toggled after 4 cycles of the old clock and 4 cycles of 
+		he new clock. This is not usually an issue, but designers must be aware.)*/
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL 
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT 
+#undef CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK 
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_DEFVAL                                       0x00000A00
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_SHIFT                                        0
+#define CRF_APB_DBG_TSTMP_CTRL_SRCSEL_MASK                                         0x00000007U
+
+/*00" = Select the APB switch clock for the APB interface of TTC0'01" = Select the PLL ref clock for the APB interface of TTC0'
+		0" = Select the R5 clock for the APB interface of TTC0*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_SHIFT                                    0
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC0_SEL_MASK                                     0x00000003U
+
+/*00" = Select the APB switch clock for the APB interface of TTC1'01" = Select the PLL ref clock for the APB interface of TTC1'
+		0" = Select the R5 clock for the APB interface of TTC1*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_SHIFT                                    2
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC1_SEL_MASK                                     0x0000000CU
+
+/*00" = Select the APB switch clock for the APB interface of TTC2'01" = Select the PLL ref clock for the APB interface of TTC2'
+		0" = Select the R5 clock for the APB interface of TTC2*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_SHIFT                                    4
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC2_SEL_MASK                                     0x00000030U
+
+/*00" = Select the APB switch clock for the APB interface of TTC3'01" = Select the PLL ref clock for the APB interface of TTC3'
+		0" = Select the R5 clock for the APB interface of TTC3*/
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT 
+#undef IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK 
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_SHIFT                                    6
+#define IOU_SLCR_IOU_TTC_APB_CLK_TTC3_SEL_MASK                                     0x000000C0U
+
+/*System watchdog timer clock source selection: 0: Internal APB clock 1: External (PL clock via EMIO or Pinout clock via MIO)*/
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT 
+#undef FPD_SLCR_WDT_CLK_SEL_SELECT_MASK 
+#define FPD_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                                         0x00000000
+#define FPD_SLCR_WDT_CLK_SEL_SELECT_SHIFT                                          0
+#define FPD_SLCR_WDT_CLK_SEL_SELECT_MASK                                           0x00000001U
+
+/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock from PL via EMIO, or from pinout 
+		ia MIO*/
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL 
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT 
+#undef IOU_SLCR_WDT_CLK_SEL_SELECT_MASK 
+#define IOU_SLCR_WDT_CLK_SEL_SELECT_DEFVAL                                         0x00000000
+#define IOU_SLCR_WDT_CLK_SEL_SELECT_SHIFT                                          0
+#define IOU_SLCR_WDT_CLK_SEL_SELECT_MASK                                           0x00000001U
+
+/*System watchdog timer clock source selection: 0: internal clock APB clock 1: external clock pss_ref_clk*/
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL 
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT 
+#undef LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK 
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_DEFVAL                                  0x00000000
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_SHIFT                                   0
+#define LPD_SLCR_CSUPMU_WDT_CLK_SEL_SELECT_MASK                                    0x00000001U
+#undef CRF_APB_RST_DDR_SS_OFFSET 
+#define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
+#undef DDRC_MSTR_OFFSET 
+#define DDRC_MSTR_OFFSET                                                           0XFD070000
+#undef DDRC_MRCTRL0_OFFSET 
+#define DDRC_MRCTRL0_OFFSET                                                        0XFD070010
+#undef DDRC_DERATEEN_OFFSET 
+#define DDRC_DERATEEN_OFFSET                                                       0XFD070020
+#undef DDRC_DERATEINT_OFFSET 
+#define DDRC_DERATEINT_OFFSET                                                      0XFD070024
+#undef DDRC_PWRCTL_OFFSET 
+#define DDRC_PWRCTL_OFFSET                                                         0XFD070030
+#undef DDRC_PWRTMG_OFFSET 
+#define DDRC_PWRTMG_OFFSET                                                         0XFD070034
+#undef DDRC_RFSHCTL0_OFFSET 
+#define DDRC_RFSHCTL0_OFFSET                                                       0XFD070050
+#undef DDRC_RFSHCTL3_OFFSET 
+#define DDRC_RFSHCTL3_OFFSET                                                       0XFD070060
+#undef DDRC_RFSHTMG_OFFSET 
+#define DDRC_RFSHTMG_OFFSET                                                        0XFD070064
+#undef DDRC_ECCCFG0_OFFSET 
+#define DDRC_ECCCFG0_OFFSET                                                        0XFD070070
+#undef DDRC_ECCCFG1_OFFSET 
+#define DDRC_ECCCFG1_OFFSET                                                        0XFD070074
+#undef DDRC_CRCPARCTL1_OFFSET 
+#define DDRC_CRCPARCTL1_OFFSET                                                     0XFD0700C4
+#undef DDRC_CRCPARCTL2_OFFSET 
+#define DDRC_CRCPARCTL2_OFFSET                                                     0XFD0700C8
+#undef DDRC_INIT0_OFFSET 
+#define DDRC_INIT0_OFFSET                                                          0XFD0700D0
+#undef DDRC_INIT1_OFFSET 
+#define DDRC_INIT1_OFFSET                                                          0XFD0700D4
+#undef DDRC_INIT2_OFFSET 
+#define DDRC_INIT2_OFFSET                                                          0XFD0700D8
+#undef DDRC_INIT3_OFFSET 
+#define DDRC_INIT3_OFFSET                                                          0XFD0700DC
+#undef DDRC_INIT4_OFFSET 
+#define DDRC_INIT4_OFFSET                                                          0XFD0700E0
+#undef DDRC_INIT5_OFFSET 
+#define DDRC_INIT5_OFFSET                                                          0XFD0700E4
+#undef DDRC_INIT6_OFFSET 
+#define DDRC_INIT6_OFFSET                                                          0XFD0700E8
+#undef DDRC_INIT7_OFFSET 
+#define DDRC_INIT7_OFFSET                                                          0XFD0700EC
+#undef DDRC_DIMMCTL_OFFSET 
+#define DDRC_DIMMCTL_OFFSET                                                        0XFD0700F0
+#undef DDRC_RANKCTL_OFFSET 
+#define DDRC_RANKCTL_OFFSET                                                        0XFD0700F4
+#undef DDRC_DRAMTMG0_OFFSET 
+#define DDRC_DRAMTMG0_OFFSET                                                       0XFD070100
+#undef DDRC_DRAMTMG1_OFFSET 
+#define DDRC_DRAMTMG1_OFFSET                                                       0XFD070104
+#undef DDRC_DRAMTMG2_OFFSET 
+#define DDRC_DRAMTMG2_OFFSET                                                       0XFD070108
+#undef DDRC_DRAMTMG3_OFFSET 
+#define DDRC_DRAMTMG3_OFFSET                                                       0XFD07010C
+#undef DDRC_DRAMTMG4_OFFSET 
+#define DDRC_DRAMTMG4_OFFSET                                                       0XFD070110
+#undef DDRC_DRAMTMG5_OFFSET 
+#define DDRC_DRAMTMG5_OFFSET                                                       0XFD070114
+#undef DDRC_DRAMTMG6_OFFSET 
+#define DDRC_DRAMTMG6_OFFSET                                                       0XFD070118
+#undef DDRC_DRAMTMG7_OFFSET 
+#define DDRC_DRAMTMG7_OFFSET                                                       0XFD07011C
+#undef DDRC_DRAMTMG8_OFFSET 
+#define DDRC_DRAMTMG8_OFFSET                                                       0XFD070120
+#undef DDRC_DRAMTMG9_OFFSET 
+#define DDRC_DRAMTMG9_OFFSET                                                       0XFD070124
+#undef DDRC_DRAMTMG11_OFFSET 
+#define DDRC_DRAMTMG11_OFFSET                                                      0XFD07012C
+#undef DDRC_DRAMTMG12_OFFSET 
+#define DDRC_DRAMTMG12_OFFSET                                                      0XFD070130
+#undef DDRC_ZQCTL0_OFFSET 
+#define DDRC_ZQCTL0_OFFSET                                                         0XFD070180
+#undef DDRC_ZQCTL1_OFFSET 
+#define DDRC_ZQCTL1_OFFSET                                                         0XFD070184
+#undef DDRC_DFITMG0_OFFSET 
+#define DDRC_DFITMG0_OFFSET                                                        0XFD070190
+#undef DDRC_DFITMG1_OFFSET 
+#define DDRC_DFITMG1_OFFSET                                                        0XFD070194
+#undef DDRC_DFILPCFG0_OFFSET 
+#define DDRC_DFILPCFG0_OFFSET                                                      0XFD070198
+#undef DDRC_DFILPCFG1_OFFSET 
+#define DDRC_DFILPCFG1_OFFSET                                                      0XFD07019C
+#undef DDRC_DFIUPD1_OFFSET 
+#define DDRC_DFIUPD1_OFFSET                                                        0XFD0701A4
+#undef DDRC_DFIMISC_OFFSET 
+#define DDRC_DFIMISC_OFFSET                                                        0XFD0701B0
+#undef DDRC_DFITMG2_OFFSET 
+#define DDRC_DFITMG2_OFFSET                                                        0XFD0701B4
+#undef DDRC_DBICTL_OFFSET 
+#define DDRC_DBICTL_OFFSET                                                         0XFD0701C0
+#undef DDRC_ADDRMAP0_OFFSET 
+#define DDRC_ADDRMAP0_OFFSET                                                       0XFD070200
+#undef DDRC_ADDRMAP1_OFFSET 
+#define DDRC_ADDRMAP1_OFFSET                                                       0XFD070204
+#undef DDRC_ADDRMAP2_OFFSET 
+#define DDRC_ADDRMAP2_OFFSET                                                       0XFD070208
+#undef DDRC_ADDRMAP3_OFFSET 
+#define DDRC_ADDRMAP3_OFFSET                                                       0XFD07020C
+#undef DDRC_ADDRMAP4_OFFSET 
+#define DDRC_ADDRMAP4_OFFSET                                                       0XFD070210
+#undef DDRC_ADDRMAP5_OFFSET 
+#define DDRC_ADDRMAP5_OFFSET                                                       0XFD070214
+#undef DDRC_ADDRMAP6_OFFSET 
+#define DDRC_ADDRMAP6_OFFSET                                                       0XFD070218
+#undef DDRC_ADDRMAP7_OFFSET 
+#define DDRC_ADDRMAP7_OFFSET                                                       0XFD07021C
+#undef DDRC_ADDRMAP8_OFFSET 
+#define DDRC_ADDRMAP8_OFFSET                                                       0XFD070220
+#undef DDRC_ADDRMAP9_OFFSET 
+#define DDRC_ADDRMAP9_OFFSET                                                       0XFD070224
+#undef DDRC_ADDRMAP10_OFFSET 
+#define DDRC_ADDRMAP10_OFFSET                                                      0XFD070228
+#undef DDRC_ADDRMAP11_OFFSET 
+#define DDRC_ADDRMAP11_OFFSET                                                      0XFD07022C
+#undef DDRC_ODTCFG_OFFSET 
+#define DDRC_ODTCFG_OFFSET                                                         0XFD070240
+#undef DDRC_ODTMAP_OFFSET 
+#define DDRC_ODTMAP_OFFSET                                                         0XFD070244
+#undef DDRC_SCHED_OFFSET 
+#define DDRC_SCHED_OFFSET                                                          0XFD070250
+#undef DDRC_PERFLPR1_OFFSET 
+#define DDRC_PERFLPR1_OFFSET                                                       0XFD070264
+#undef DDRC_PERFWR1_OFFSET 
+#define DDRC_PERFWR1_OFFSET                                                        0XFD07026C
+#undef DDRC_DQMAP5_OFFSET 
+#define DDRC_DQMAP5_OFFSET                                                         0XFD070294
+#undef DDRC_DBG0_OFFSET 
+#define DDRC_DBG0_OFFSET                                                           0XFD070300
+#undef DDRC_DBGCMD_OFFSET 
+#define DDRC_DBGCMD_OFFSET                                                         0XFD07030C
+#undef DDRC_SWCTL_OFFSET 
+#define DDRC_SWCTL_OFFSET                                                          0XFD070320
+#undef DDRC_PCCFG_OFFSET 
+#define DDRC_PCCFG_OFFSET                                                          0XFD070400
+#undef DDRC_PCFGR_0_OFFSET 
+#define DDRC_PCFGR_0_OFFSET                                                        0XFD070404
+#undef DDRC_PCFGW_0_OFFSET 
+#define DDRC_PCFGW_0_OFFSET                                                        0XFD070408
+#undef DDRC_PCTRL_0_OFFSET 
+#define DDRC_PCTRL_0_OFFSET                                                        0XFD070490
+#undef DDRC_PCFGQOS0_0_OFFSET 
+#define DDRC_PCFGQOS0_0_OFFSET                                                     0XFD070494
+#undef DDRC_PCFGQOS1_0_OFFSET 
+#define DDRC_PCFGQOS1_0_OFFSET                                                     0XFD070498
+#undef DDRC_PCFGR_1_OFFSET 
+#define DDRC_PCFGR_1_OFFSET                                                        0XFD0704B4
+#undef DDRC_PCFGW_1_OFFSET 
+#define DDRC_PCFGW_1_OFFSET                                                        0XFD0704B8
+#undef DDRC_PCTRL_1_OFFSET 
+#define DDRC_PCTRL_1_OFFSET                                                        0XFD070540
+#undef DDRC_PCFGQOS0_1_OFFSET 
+#define DDRC_PCFGQOS0_1_OFFSET                                                     0XFD070544
+#undef DDRC_PCFGQOS1_1_OFFSET 
+#define DDRC_PCFGQOS1_1_OFFSET                                                     0XFD070548
+#undef DDRC_PCFGR_2_OFFSET 
+#define DDRC_PCFGR_2_OFFSET                                                        0XFD070564
+#undef DDRC_PCFGW_2_OFFSET 
+#define DDRC_PCFGW_2_OFFSET                                                        0XFD070568
+#undef DDRC_PCTRL_2_OFFSET 
+#define DDRC_PCTRL_2_OFFSET                                                        0XFD0705F0
+#undef DDRC_PCFGQOS0_2_OFFSET 
+#define DDRC_PCFGQOS0_2_OFFSET                                                     0XFD0705F4
+#undef DDRC_PCFGQOS1_2_OFFSET 
+#define DDRC_PCFGQOS1_2_OFFSET                                                     0XFD0705F8
+#undef DDRC_PCFGR_3_OFFSET 
+#define DDRC_PCFGR_3_OFFSET                                                        0XFD070614
+#undef DDRC_PCFGW_3_OFFSET 
+#define DDRC_PCFGW_3_OFFSET                                                        0XFD070618
+#undef DDRC_PCTRL_3_OFFSET 
+#define DDRC_PCTRL_3_OFFSET                                                        0XFD0706A0
+#undef DDRC_PCFGQOS0_3_OFFSET 
+#define DDRC_PCFGQOS0_3_OFFSET                                                     0XFD0706A4
+#undef DDRC_PCFGQOS1_3_OFFSET 
+#define DDRC_PCFGQOS1_3_OFFSET                                                     0XFD0706A8
+#undef DDRC_PCFGWQOS0_3_OFFSET 
+#define DDRC_PCFGWQOS0_3_OFFSET                                                    0XFD0706AC
+#undef DDRC_PCFGWQOS1_3_OFFSET 
+#define DDRC_PCFGWQOS1_3_OFFSET                                                    0XFD0706B0
+#undef DDRC_PCFGR_4_OFFSET 
+#define DDRC_PCFGR_4_OFFSET                                                        0XFD0706C4
+#undef DDRC_PCFGW_4_OFFSET 
+#define DDRC_PCFGW_4_OFFSET                                                        0XFD0706C8
+#undef DDRC_PCTRL_4_OFFSET 
+#define DDRC_PCTRL_4_OFFSET                                                        0XFD070750
+#undef DDRC_PCFGQOS0_4_OFFSET 
+#define DDRC_PCFGQOS0_4_OFFSET                                                     0XFD070754
+#undef DDRC_PCFGQOS1_4_OFFSET 
+#define DDRC_PCFGQOS1_4_OFFSET                                                     0XFD070758
+#undef DDRC_PCFGWQOS0_4_OFFSET 
+#define DDRC_PCFGWQOS0_4_OFFSET                                                    0XFD07075C
+#undef DDRC_PCFGWQOS1_4_OFFSET 
+#define DDRC_PCFGWQOS1_4_OFFSET                                                    0XFD070760
+#undef DDRC_PCFGR_5_OFFSET 
+#define DDRC_PCFGR_5_OFFSET                                                        0XFD070774
+#undef DDRC_PCFGW_5_OFFSET 
+#define DDRC_PCFGW_5_OFFSET                                                        0XFD070778
+#undef DDRC_PCTRL_5_OFFSET 
+#define DDRC_PCTRL_5_OFFSET                                                        0XFD070800
+#undef DDRC_PCFGQOS0_5_OFFSET 
+#define DDRC_PCFGQOS0_5_OFFSET                                                     0XFD070804
+#undef DDRC_PCFGQOS1_5_OFFSET 
+#define DDRC_PCFGQOS1_5_OFFSET                                                     0XFD070808
+#undef DDRC_PCFGWQOS0_5_OFFSET 
+#define DDRC_PCFGWQOS0_5_OFFSET                                                    0XFD07080C
+#undef DDRC_PCFGWQOS1_5_OFFSET 
+#define DDRC_PCFGWQOS1_5_OFFSET                                                    0XFD070810
+#undef DDRC_SARBASE0_OFFSET 
+#define DDRC_SARBASE0_OFFSET                                                       0XFD070F04
+#undef DDRC_SARSIZE0_OFFSET 
+#define DDRC_SARSIZE0_OFFSET                                                       0XFD070F08
+#undef DDRC_SARBASE1_OFFSET 
+#define DDRC_SARBASE1_OFFSET                                                       0XFD070F0C
+#undef DDRC_SARSIZE1_OFFSET 
+#define DDRC_SARSIZE1_OFFSET                                                       0XFD070F10
+#undef DDRC_DFITMG0_SHADOW_OFFSET 
+#define DDRC_DFITMG0_SHADOW_OFFSET                                                 0XFD072190
+#undef CRF_APB_RST_DDR_SS_OFFSET 
+#define CRF_APB_RST_DDR_SS_OFFSET                                                  0XFD1A0108
+#undef DDR_PHY_PGCR0_OFFSET 
+#define DDR_PHY_PGCR0_OFFSET                                                       0XFD080010
+#undef DDR_PHY_PGCR2_OFFSET 
+#define DDR_PHY_PGCR2_OFFSET                                                       0XFD080018
+#undef DDR_PHY_PGCR5_OFFSET 
+#define DDR_PHY_PGCR5_OFFSET                                                       0XFD080024
+#undef DDR_PHY_PTR0_OFFSET 
+#define DDR_PHY_PTR0_OFFSET                                                        0XFD080040
+#undef DDR_PHY_PTR1_OFFSET 
+#define DDR_PHY_PTR1_OFFSET                                                        0XFD080044
+#undef DDR_PHY_DSGCR_OFFSET 
+#define DDR_PHY_DSGCR_OFFSET                                                       0XFD080090
+#undef DDR_PHY_DCR_OFFSET 
+#define DDR_PHY_DCR_OFFSET                                                         0XFD080100
+#undef DDR_PHY_DTPR0_OFFSET 
+#define DDR_PHY_DTPR0_OFFSET                                                       0XFD080110
+#undef DDR_PHY_DTPR1_OFFSET 
+#define DDR_PHY_DTPR1_OFFSET                                                       0XFD080114
+#undef DDR_PHY_DTPR2_OFFSET 
+#define DDR_PHY_DTPR2_OFFSET                                                       0XFD080118
+#undef DDR_PHY_DTPR3_OFFSET 
+#define DDR_PHY_DTPR3_OFFSET                                                       0XFD08011C
+#undef DDR_PHY_DTPR4_OFFSET 
+#define DDR_PHY_DTPR4_OFFSET                                                       0XFD080120
+#undef DDR_PHY_DTPR5_OFFSET 
+#define DDR_PHY_DTPR5_OFFSET                                                       0XFD080124
+#undef DDR_PHY_DTPR6_OFFSET 
+#define DDR_PHY_DTPR6_OFFSET                                                       0XFD080128
+#undef DDR_PHY_RDIMMGCR0_OFFSET 
+#define DDR_PHY_RDIMMGCR0_OFFSET                                                   0XFD080140
+#undef DDR_PHY_RDIMMGCR1_OFFSET 
+#define DDR_PHY_RDIMMGCR1_OFFSET                                                   0XFD080144
+#undef DDR_PHY_RDIMMCR1_OFFSET 
+#define DDR_PHY_RDIMMCR1_OFFSET                                                    0XFD080154
+#undef DDR_PHY_MR0_OFFSET 
+#define DDR_PHY_MR0_OFFSET                                                         0XFD080180
+#undef DDR_PHY_MR1_OFFSET 
+#define DDR_PHY_MR1_OFFSET                                                         0XFD080184
+#undef DDR_PHY_MR2_OFFSET 
+#define DDR_PHY_MR2_OFFSET                                                         0XFD080188
+#undef DDR_PHY_MR3_OFFSET 
+#define DDR_PHY_MR3_OFFSET                                                         0XFD08018C
+#undef DDR_PHY_MR4_OFFSET 
+#define DDR_PHY_MR4_OFFSET                                                         0XFD080190
+#undef DDR_PHY_MR5_OFFSET 
+#define DDR_PHY_MR5_OFFSET                                                         0XFD080194
+#undef DDR_PHY_MR6_OFFSET 
+#define DDR_PHY_MR6_OFFSET                                                         0XFD080198
+#undef DDR_PHY_MR11_OFFSET 
+#define DDR_PHY_MR11_OFFSET                                                        0XFD0801AC
+#undef DDR_PHY_MR12_OFFSET 
+#define DDR_PHY_MR12_OFFSET                                                        0XFD0801B0
+#undef DDR_PHY_MR13_OFFSET 
+#define DDR_PHY_MR13_OFFSET                                                        0XFD0801B4
+#undef DDR_PHY_MR14_OFFSET 
+#define DDR_PHY_MR14_OFFSET                                                        0XFD0801B8
+#undef DDR_PHY_MR22_OFFSET 
+#define DDR_PHY_MR22_OFFSET                                                        0XFD0801D8
+#undef DDR_PHY_DTCR0_OFFSET 
+#define DDR_PHY_DTCR0_OFFSET                                                       0XFD080200
+#undef DDR_PHY_DTCR1_OFFSET 
+#define DDR_PHY_DTCR1_OFFSET                                                       0XFD080204
+#undef DDR_PHY_CATR0_OFFSET 
+#define DDR_PHY_CATR0_OFFSET                                                       0XFD080240
+#undef DDR_PHY_RIOCR5_OFFSET 
+#define DDR_PHY_RIOCR5_OFFSET                                                      0XFD0804F4
+#undef DDR_PHY_ACIOCR0_OFFSET 
+#define DDR_PHY_ACIOCR0_OFFSET                                                     0XFD080500
+#undef DDR_PHY_ACIOCR2_OFFSET 
+#define DDR_PHY_ACIOCR2_OFFSET                                                     0XFD080508
+#undef DDR_PHY_ACIOCR3_OFFSET 
+#define DDR_PHY_ACIOCR3_OFFSET                                                     0XFD08050C
+#undef DDR_PHY_ACIOCR4_OFFSET 
+#define DDR_PHY_ACIOCR4_OFFSET                                                     0XFD080510
+#undef DDR_PHY_IOVCR0_OFFSET 
+#define DDR_PHY_IOVCR0_OFFSET                                                      0XFD080520
+#undef DDR_PHY_VTCR0_OFFSET 
+#define DDR_PHY_VTCR0_OFFSET                                                       0XFD080528
+#undef DDR_PHY_VTCR1_OFFSET 
+#define DDR_PHY_VTCR1_OFFSET                                                       0XFD08052C
+#undef DDR_PHY_ACBDLR6_OFFSET 
+#define DDR_PHY_ACBDLR6_OFFSET                                                     0XFD080558
+#undef DDR_PHY_ACBDLR7_OFFSET 
+#define DDR_PHY_ACBDLR7_OFFSET                                                     0XFD08055C
+#undef DDR_PHY_ACBDLR8_OFFSET 
+#define DDR_PHY_ACBDLR8_OFFSET                                                     0XFD080560
+#undef DDR_PHY_ZQCR_OFFSET 
+#define DDR_PHY_ZQCR_OFFSET                                                        0XFD080680
+#undef DDR_PHY_ZQ0PR0_OFFSET 
+#define DDR_PHY_ZQ0PR0_OFFSET                                                      0XFD080684
+#undef DDR_PHY_ZQ0OR0_OFFSET 
+#define DDR_PHY_ZQ0OR0_OFFSET                                                      0XFD080694
+#undef DDR_PHY_ZQ0OR1_OFFSET 
+#define DDR_PHY_ZQ0OR1_OFFSET                                                      0XFD080698
+#undef DDR_PHY_ZQ1PR0_OFFSET 
+#define DDR_PHY_ZQ1PR0_OFFSET                                                      0XFD0806A4
+#undef DDR_PHY_DX0GCR0_OFFSET 
+#define DDR_PHY_DX0GCR0_OFFSET                                                     0XFD080700
+#undef DDR_PHY_DX0GCR4_OFFSET 
+#define DDR_PHY_DX0GCR4_OFFSET                                                     0XFD080710
+#undef DDR_PHY_DX0GCR5_OFFSET 
+#define DDR_PHY_DX0GCR5_OFFSET                                                     0XFD080714
+#undef DDR_PHY_DX0GCR6_OFFSET 
+#define DDR_PHY_DX0GCR6_OFFSET                                                     0XFD080718
+#undef DDR_PHY_DX0LCDLR2_OFFSET 
+#define DDR_PHY_DX0LCDLR2_OFFSET                                                   0XFD080788
+#undef DDR_PHY_DX0GTR0_OFFSET 
+#define DDR_PHY_DX0GTR0_OFFSET                                                     0XFD0807C0
+#undef DDR_PHY_DX1GCR0_OFFSET 
+#define DDR_PHY_DX1GCR0_OFFSET                                                     0XFD080800
+#undef DDR_PHY_DX1GCR4_OFFSET 
+#define DDR_PHY_DX1GCR4_OFFSET                                                     0XFD080810
+#undef DDR_PHY_DX1GCR5_OFFSET 
+#define DDR_PHY_DX1GCR5_OFFSET                                                     0XFD080814
+#undef DDR_PHY_DX1GCR6_OFFSET 
+#define DDR_PHY_DX1GCR6_OFFSET                                                     0XFD080818
+#undef DDR_PHY_DX1LCDLR2_OFFSET 
+#define DDR_PHY_DX1LCDLR2_OFFSET                                                   0XFD080888
+#undef DDR_PHY_DX1GTR0_OFFSET 
+#define DDR_PHY_DX1GTR0_OFFSET                                                     0XFD0808C0
+#undef DDR_PHY_DX2GCR0_OFFSET 
+#define DDR_PHY_DX2GCR0_OFFSET                                                     0XFD080900
+#undef DDR_PHY_DX2GCR1_OFFSET 
+#define DDR_PHY_DX2GCR1_OFFSET                                                     0XFD080904
+#undef DDR_PHY_DX2GCR4_OFFSET 
+#define DDR_PHY_DX2GCR4_OFFSET                                                     0XFD080910
+#undef DDR_PHY_DX2GCR5_OFFSET 
+#define DDR_PHY_DX2GCR5_OFFSET                                                     0XFD080914
+#undef DDR_PHY_DX2GCR6_OFFSET 
+#define DDR_PHY_DX2GCR6_OFFSET                                                     0XFD080918
+#undef DDR_PHY_DX2LCDLR2_OFFSET 
+#define DDR_PHY_DX2LCDLR2_OFFSET                                                   0XFD080988
+#undef DDR_PHY_DX2GTR0_OFFSET 
+#define DDR_PHY_DX2GTR0_OFFSET                                                     0XFD0809C0
+#undef DDR_PHY_DX3GCR0_OFFSET 
+#define DDR_PHY_DX3GCR0_OFFSET                                                     0XFD080A00
+#undef DDR_PHY_DX3GCR1_OFFSET 
+#define DDR_PHY_DX3GCR1_OFFSET                                                     0XFD080A04
+#undef DDR_PHY_DX3GCR4_OFFSET 
+#define DDR_PHY_DX3GCR4_OFFSET                                                     0XFD080A10
+#undef DDR_PHY_DX3GCR5_OFFSET 
+#define DDR_PHY_DX3GCR5_OFFSET                                                     0XFD080A14
+#undef DDR_PHY_DX3GCR6_OFFSET 
+#define DDR_PHY_DX3GCR6_OFFSET                                                     0XFD080A18
+#undef DDR_PHY_DX3LCDLR2_OFFSET 
+#define DDR_PHY_DX3LCDLR2_OFFSET                                                   0XFD080A88
+#undef DDR_PHY_DX3GTR0_OFFSET 
+#define DDR_PHY_DX3GTR0_OFFSET                                                     0XFD080AC0
+#undef DDR_PHY_DX4GCR0_OFFSET 
+#define DDR_PHY_DX4GCR0_OFFSET                                                     0XFD080B00
+#undef DDR_PHY_DX4GCR1_OFFSET 
+#define DDR_PHY_DX4GCR1_OFFSET                                                     0XFD080B04
+#undef DDR_PHY_DX4GCR4_OFFSET 
+#define DDR_PHY_DX4GCR4_OFFSET                                                     0XFD080B10
+#undef DDR_PHY_DX4GCR5_OFFSET 
+#define DDR_PHY_DX4GCR5_OFFSET                                                     0XFD080B14
+#undef DDR_PHY_DX4GCR6_OFFSET 
+#define DDR_PHY_DX4GCR6_OFFSET                                                     0XFD080B18
+#undef DDR_PHY_DX4LCDLR2_OFFSET 
+#define DDR_PHY_DX4LCDLR2_OFFSET                                                   0XFD080B88
+#undef DDR_PHY_DX4GTR0_OFFSET 
+#define DDR_PHY_DX4GTR0_OFFSET                                                     0XFD080BC0
+#undef DDR_PHY_DX5GCR0_OFFSET 
+#define DDR_PHY_DX5GCR0_OFFSET                                                     0XFD080C00
+#undef DDR_PHY_DX5GCR1_OFFSET 
+#define DDR_PHY_DX5GCR1_OFFSET                                                     0XFD080C04
+#undef DDR_PHY_DX5GCR4_OFFSET 
+#define DDR_PHY_DX5GCR4_OFFSET                                                     0XFD080C10
+#undef DDR_PHY_DX5GCR5_OFFSET 
+#define DDR_PHY_DX5GCR5_OFFSET                                                     0XFD080C14
+#undef DDR_PHY_DX5GCR6_OFFSET 
+#define DDR_PHY_DX5GCR6_OFFSET                                                     0XFD080C18
+#undef DDR_PHY_DX5LCDLR2_OFFSET 
+#define DDR_PHY_DX5LCDLR2_OFFSET                                                   0XFD080C88
+#undef DDR_PHY_DX5GTR0_OFFSET 
+#define DDR_PHY_DX5GTR0_OFFSET                                                     0XFD080CC0
+#undef DDR_PHY_DX6GCR0_OFFSET 
+#define DDR_PHY_DX6GCR0_OFFSET                                                     0XFD080D00
+#undef DDR_PHY_DX6GCR1_OFFSET 
+#define DDR_PHY_DX6GCR1_OFFSET                                                     0XFD080D04
+#undef DDR_PHY_DX6GCR4_OFFSET 
+#define DDR_PHY_DX6GCR4_OFFSET                                                     0XFD080D10
+#undef DDR_PHY_DX6GCR5_OFFSET 
+#define DDR_PHY_DX6GCR5_OFFSET                                                     0XFD080D14
+#undef DDR_PHY_DX6GCR6_OFFSET 
+#define DDR_PHY_DX6GCR6_OFFSET                                                     0XFD080D18
+#undef DDR_PHY_DX6LCDLR2_OFFSET 
+#define DDR_PHY_DX6LCDLR2_OFFSET                                                   0XFD080D88
+#undef DDR_PHY_DX6GTR0_OFFSET 
+#define DDR_PHY_DX6GTR0_OFFSET                                                     0XFD080DC0
+#undef DDR_PHY_DX7GCR0_OFFSET 
+#define DDR_PHY_DX7GCR0_OFFSET                                                     0XFD080E00
+#undef DDR_PHY_DX7GCR1_OFFSET 
+#define DDR_PHY_DX7GCR1_OFFSET                                                     0XFD080E04
+#undef DDR_PHY_DX7GCR4_OFFSET 
+#define DDR_PHY_DX7GCR4_OFFSET                                                     0XFD080E10
+#undef DDR_PHY_DX7GCR5_OFFSET 
+#define DDR_PHY_DX7GCR5_OFFSET                                                     0XFD080E14
+#undef DDR_PHY_DX7GCR6_OFFSET 
+#define DDR_PHY_DX7GCR6_OFFSET                                                     0XFD080E18
+#undef DDR_PHY_DX7LCDLR2_OFFSET 
+#define DDR_PHY_DX7LCDLR2_OFFSET                                                   0XFD080E88
+#undef DDR_PHY_DX7GTR0_OFFSET 
+#define DDR_PHY_DX7GTR0_OFFSET                                                     0XFD080EC0
+#undef DDR_PHY_DX8GCR0_OFFSET 
+#define DDR_PHY_DX8GCR0_OFFSET                                                     0XFD080F00
+#undef DDR_PHY_DX8GCR1_OFFSET 
+#define DDR_PHY_DX8GCR1_OFFSET                                                     0XFD080F04
+#undef DDR_PHY_DX8GCR4_OFFSET 
+#define DDR_PHY_DX8GCR4_OFFSET                                                     0XFD080F10
+#undef DDR_PHY_DX8GCR5_OFFSET 
+#define DDR_PHY_DX8GCR5_OFFSET                                                     0XFD080F14
+#undef DDR_PHY_DX8GCR6_OFFSET 
+#define DDR_PHY_DX8GCR6_OFFSET                                                     0XFD080F18
+#undef DDR_PHY_DX8LCDLR2_OFFSET 
+#define DDR_PHY_DX8LCDLR2_OFFSET                                                   0XFD080F88
+#undef DDR_PHY_DX8GTR0_OFFSET 
+#define DDR_PHY_DX8GTR0_OFFSET                                                     0XFD080FC0
+#undef DDR_PHY_DX8SL0DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL0DQSCTL_OFFSET                                                0XFD08141C
+#undef DDR_PHY_DX8SL0DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL0DXCTL2_OFFSET                                                0XFD08142C
+#undef DDR_PHY_DX8SL0IOCR_OFFSET 
+#define DDR_PHY_DX8SL0IOCR_OFFSET                                                  0XFD081430
+#undef DDR_PHY_DX8SL1DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL1DQSCTL_OFFSET                                                0XFD08145C
+#undef DDR_PHY_DX8SL1DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL1DXCTL2_OFFSET                                                0XFD08146C
+#undef DDR_PHY_DX8SL1IOCR_OFFSET 
+#define DDR_PHY_DX8SL1IOCR_OFFSET                                                  0XFD081470
+#undef DDR_PHY_DX8SL2DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL2DQSCTL_OFFSET                                                0XFD08149C
+#undef DDR_PHY_DX8SL2DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL2DXCTL2_OFFSET                                                0XFD0814AC
+#undef DDR_PHY_DX8SL2IOCR_OFFSET 
+#define DDR_PHY_DX8SL2IOCR_OFFSET                                                  0XFD0814B0
+#undef DDR_PHY_DX8SL3DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL3DQSCTL_OFFSET                                                0XFD0814DC
+#undef DDR_PHY_DX8SL3DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL3DXCTL2_OFFSET                                                0XFD0814EC
+#undef DDR_PHY_DX8SL3IOCR_OFFSET 
+#define DDR_PHY_DX8SL3IOCR_OFFSET                                                  0XFD0814F0
+#undef DDR_PHY_DX8SL4DQSCTL_OFFSET 
+#define DDR_PHY_DX8SL4DQSCTL_OFFSET                                                0XFD08151C
+#undef DDR_PHY_DX8SL4DXCTL2_OFFSET 
+#define DDR_PHY_DX8SL4DXCTL2_OFFSET                                                0XFD08152C
+#undef DDR_PHY_DX8SL4IOCR_OFFSET 
+#define DDR_PHY_DX8SL4IOCR_OFFSET                                                  0XFD081530
+#undef DDR_PHY_DX8SLBDQSCTL_OFFSET 
+#define DDR_PHY_DX8SLBDQSCTL_OFFSET                                                0XFD0817DC
+#undef DDR_PHY_PIR_OFFSET 
+#define DDR_PHY_PIR_OFFSET                                                         0XFD080004
+
+/*DDR block level reset inside of the DDR Sub System*/
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 
+#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                                        0x0000000F
+#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                                         3
+#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                                          0x00000008U
+
+/*Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 
+		evice*/
+#undef DDRC_MSTR_DEVICE_CONFIG_DEFVAL 
+#undef DDRC_MSTR_DEVICE_CONFIG_SHIFT 
+#undef DDRC_MSTR_DEVICE_CONFIG_MASK 
+#define DDRC_MSTR_DEVICE_CONFIG_DEFVAL                                             0x03040001
+#define DDRC_MSTR_DEVICE_CONFIG_SHIFT                                              30
+#define DDRC_MSTR_DEVICE_CONFIG_MASK                                               0xC0000000U
+
+/*Choose which registers are used. - 0 - Original registers - 1 - Shadow registers*/
+#undef DDRC_MSTR_FREQUENCY_MODE_DEFVAL 
+#undef DDRC_MSTR_FREQUENCY_MODE_SHIFT 
+#undef DDRC_MSTR_FREQUENCY_MODE_MASK 
+#define DDRC_MSTR_FREQUENCY_MODE_DEFVAL                                            0x03040001
+#define DDRC_MSTR_FREQUENCY_MODE_SHIFT                                             29
+#define DDRC_MSTR_FREQUENCY_MODE_MASK                                              0x20000000U
+
+/*Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations, only bits[25:24] are p
+		esent. - 1 - populated - 0 - unpopulated LSB is the lowest rank number. For 2 ranks following combinations are legal: - 01 - 
+		ne rank - 11 - Two ranks - Others - Reserved. For 4 ranks following combinations are legal: - 0001 - One rank - 0011 - Two ra
+		ks - 1111 - Four ranks*/
+#undef DDRC_MSTR_ACTIVE_RANKS_DEFVAL 
+#undef DDRC_MSTR_ACTIVE_RANKS_SHIFT 
+#undef DDRC_MSTR_ACTIVE_RANKS_MASK 
+#define DDRC_MSTR_ACTIVE_RANKS_DEFVAL                                              0x03040001
+#define DDRC_MSTR_ACTIVE_RANKS_SHIFT                                               24
+#define DDRC_MSTR_ACTIVE_RANKS_MASK                                                0x03000000U
+
+/*SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst lengt
+		 of 8 - 1000 - Burst length of 16 (only supported for mDDR, LPDDR2, and LPDDR4) All other values are reserved. This controls 
+		he burst size used to access the SDRAM. This must match the burst length mode register setting in the SDRAM. (For BC4/8 on-th
+		-fly mode of DDR3 and DDR4, set this field to 0x0100) Burst length of 2 is not supported with AXI ports when MEMC_BURST_LENGT
+		 is 8. Burst length of 2 is only supported with MEMC_FREQ_RATIO = 1*/
+#undef DDRC_MSTR_BURST_RDWR_DEFVAL 
+#undef DDRC_MSTR_BURST_RDWR_SHIFT 
+#undef DDRC_MSTR_BURST_RDWR_MASK 
+#define DDRC_MSTR_BURST_RDWR_DEFVAL                                                0x03040001
+#define DDRC_MSTR_BURST_RDWR_SHIFT                                                 16
+#define DDRC_MSTR_BURST_RDWR_MASK                                                  0x000F0000U
+
+/*Set to 1 when the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation. Set to 0 to put uMCTL2 and DRAM 
+		n DLL-on mode for normal frequency operation. If DDR4 CRC/parity retry is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), d
+		l_off_mode is not supported, and this bit must be set to '0'.*/
+#undef DDRC_MSTR_DLL_OFF_MODE_DEFVAL 
+#undef DDRC_MSTR_DLL_OFF_MODE_SHIFT 
+#undef DDRC_MSTR_DLL_OFF_MODE_MASK 
+#define DDRC_MSTR_DLL_OFF_MODE_DEFVAL                                              0x03040001
+#define DDRC_MSTR_DLL_OFF_MODE_SHIFT                                               15
+#define DDRC_MSTR_DLL_OFF_MODE_MASK                                                0x00008000U
+
+/*Selects proportion of DQ bus width that is used by the SDRAM - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SD
+		AM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved. Note that half bus width mode is only supported when the SDRAM bus w
+		dth is a multiple of 16, and quarter bus width mode is only supported when the SDRAM bus width is a multiple of 32 and the co
+		figuration parameter MEMC_QBUS_SUPPORT is set. Bus width refers to DQ bus width (excluding any ECC width).*/
+#undef DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL 
+#undef DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 
+#undef DDRC_MSTR_DATA_BUS_WIDTH_MASK 
+#define DDRC_MSTR_DATA_BUS_WIDTH_DEFVAL                                            0x03040001
+#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT                                             12
+#define DDRC_MSTR_DATA_BUS_WIDTH_MASK                                              0x00003000U
+
+/*1 indicates put the DRAM in geardown mode (2N) and 0 indicates put the DRAM in normal mode (1N). This register can be changed
+		 only when the Controller is in self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: Geardown mode 
+		s not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set*/
+#undef DDRC_MSTR_GEARDOWN_MODE_DEFVAL 
+#undef DDRC_MSTR_GEARDOWN_MODE_SHIFT 
+#undef DDRC_MSTR_GEARDOWN_MODE_MASK 
+#define DDRC_MSTR_GEARDOWN_MODE_DEFVAL                                             0x03040001
+#define DDRC_MSTR_GEARDOWN_MODE_SHIFT                                              11
+#define DDRC_MSTR_GEARDOWN_MODE_MASK                                               0x00000800U
+
+/*If 1, then uMCTL2 uses 2T timing. Otherwise, uses 1T timing. In 2T timing, all command signals (except chip select) are held 
+		or 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command Note: 2T timing is not supported in 
+		PDDR2/LPDDR3/LPDDR4 mode Note: 2T timing is not supported if the configuration parameter MEMC_CMD_RTN2IDLE is set Note: 2T ti
+		ing is not supported in DDR4 geardown mode.*/
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL 
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT 
+#undef DDRC_MSTR_EN_2T_TIMING_MODE_MASK 
+#define DDRC_MSTR_EN_2T_TIMING_MODE_DEFVAL                                         0x03040001
+#define DDRC_MSTR_EN_2T_TIMING_MODE_SHIFT                                          10
+#define DDRC_MSTR_EN_2T_TIMING_MODE_MASK                                           0x00000400U
+
+/*When set, enable burst-chop in DDR3/DDR4. Burst Chop for Reads is exercised only in HIF configurations (UMCTL2_INCL_ARB not s
+		t) and if in full bus width mode (MSTR.data_bus_width = 00). Burst Chop for Writes is exercised only if Partial Writes enable
+		 (UMCTL2_PARTIAL_WR=1) and if CRC is disabled (CRCPARCTL1.crc_enable = 0). If DDR4 CRC/parity retry is enabled (CRCPARCTL1.cr
+		_parity_retry_enable = 1), burst chop is not supported, and this bit must be set to '0'*/
+#undef DDRC_MSTR_BURSTCHOP_DEFVAL 
+#undef DDRC_MSTR_BURSTCHOP_SHIFT 
+#undef DDRC_MSTR_BURSTCHOP_MASK 
+#define DDRC_MSTR_BURSTCHOP_DEFVAL                                                 0x03040001
+#define DDRC_MSTR_BURSTCHOP_SHIFT                                                  9
+#define DDRC_MSTR_BURSTCHOP_MASK                                                   0x00000200U
+
+/*Select LPDDR4 SDRAM - 1 - LPDDR4 SDRAM device in use. - 0 - non-LPDDR4 device in use Present only in designs configured to su
+		port LPDDR4.*/
+#undef DDRC_MSTR_LPDDR4_DEFVAL 
+#undef DDRC_MSTR_LPDDR4_SHIFT 
+#undef DDRC_MSTR_LPDDR4_MASK 
+#define DDRC_MSTR_LPDDR4_DEFVAL                                                    0x03040001
+#define DDRC_MSTR_LPDDR4_SHIFT                                                     5
+#define DDRC_MSTR_LPDDR4_MASK                                                      0x00000020U
+
+/*Select DDR4 SDRAM - 1 - DDR4 SDRAM device in use. - 0 - non-DDR4 device in use Present only in designs configured to support 
+		DR4.*/
+#undef DDRC_MSTR_DDR4_DEFVAL 
+#undef DDRC_MSTR_DDR4_SHIFT 
+#undef DDRC_MSTR_DDR4_MASK 
+#define DDRC_MSTR_DDR4_DEFVAL                                                      0x03040001
+#define DDRC_MSTR_DDR4_SHIFT                                                       4
+#define DDRC_MSTR_DDR4_MASK                                                        0x00000010U
+
+/*Select LPDDR3 SDRAM - 1 - LPDDR3 SDRAM device in use. - 0 - non-LPDDR3 device in use Present only in designs configured to su
+		port LPDDR3.*/
+#undef DDRC_MSTR_LPDDR3_DEFVAL 
+#undef DDRC_MSTR_LPDDR3_SHIFT 
+#undef DDRC_MSTR_LPDDR3_MASK 
+#define DDRC_MSTR_LPDDR3_DEFVAL                                                    0x03040001
+#define DDRC_MSTR_LPDDR3_SHIFT                                                     3
+#define DDRC_MSTR_LPDDR3_MASK                                                      0x00000008U
+
+/*Select LPDDR2 SDRAM - 1 - LPDDR2 SDRAM device in use. - 0 - non-LPDDR2 device in use Present only in designs configured to su
+		port LPDDR2.*/
+#undef DDRC_MSTR_LPDDR2_DEFVAL 
+#undef DDRC_MSTR_LPDDR2_SHIFT 
+#undef DDRC_MSTR_LPDDR2_MASK 
+#define DDRC_MSTR_LPDDR2_DEFVAL                                                    0x03040001
+#define DDRC_MSTR_LPDDR2_SHIFT                                                     2
+#define DDRC_MSTR_LPDDR2_MASK                                                      0x00000004U
+
+/*Select DDR3 SDRAM - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Only present in designs that support DDR3
+		*/
+#undef DDRC_MSTR_DDR3_DEFVAL 
+#undef DDRC_MSTR_DDR3_SHIFT 
+#undef DDRC_MSTR_DDR3_MASK 
+#define DDRC_MSTR_DDR3_DEFVAL                                                      0x03040001
+#define DDRC_MSTR_DDR3_SHIFT                                                       0
+#define DDRC_MSTR_DDR3_MASK                                                        0x00000001U
+
+/*Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete, the uMCTL
+		 automatically clears this bit. The other register fields of this register must be written in a separate APB transaction, bef
+		re setting this mr_wr bit. It is recommended NOT to set this signal if in Init, Deep power-down or MPSM operating modes.*/
+#undef DDRC_MRCTRL0_MR_WR_DEFVAL 
+#undef DDRC_MRCTRL0_MR_WR_SHIFT 
+#undef DDRC_MRCTRL0_MR_WR_MASK 
+#define DDRC_MRCTRL0_MR_WR_DEFVAL                                                  0x00000030
+#define DDRC_MRCTRL0_MR_WR_SHIFT                                                   31
+#define DDRC_MRCTRL0_MR_WR_MASK                                                    0x80000000U
+
+/*Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 010
+		 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing in LPD
+		R2/LPDDR3/LPDDR4) This signal is also used for writing to control words of RDIMMs. In that case, it corresponds to the bank a
+		dress bits sent to the RDIMM In case of DDR4, the bit[3:2] corresponds to the bank group bits. Therefore, the bit[3] as well 
+		s the bit[2:0] must be set to an appropriate value which is considered both the Address Mirroring of UDIMMs/RDIMMs and the Ou
+		put Inversion of RDIMMs.*/
+#undef DDRC_MRCTRL0_MR_ADDR_DEFVAL 
+#undef DDRC_MRCTRL0_MR_ADDR_SHIFT 
+#undef DDRC_MRCTRL0_MR_ADDR_MASK 
+#define DDRC_MRCTRL0_MR_ADDR_DEFVAL                                                0x00000030
+#define DDRC_MRCTRL0_MR_ADDR_SHIFT                                                 12
+#define DDRC_MRCTRL0_MR_ADDR_MASK                                                  0x0000F000U
+
+/*Controls which rank is accessed by MRCTRL0.mr_wr. Normally, it is desired to access all ranks, so all bits should be set to 1
+		 However, for multi-rank UDIMMs/RDIMMs which implement address mirroring, it may be necessary to access ranks individually. E
+		amples (assume uMCTL2 is configured for 4 ranks): - 0x1 - select rank 0 only - 0x2 - select rank 1 only - 0x5 - select ranks 
+		 and 2 - 0xA - select ranks 1 and 3 - 0xF - select ranks 0, 1, 2 and 3*/
+#undef DDRC_MRCTRL0_MR_RANK_DEFVAL 
+#undef DDRC_MRCTRL0_MR_RANK_SHIFT 
+#undef DDRC_MRCTRL0_MR_RANK_MASK 
+#define DDRC_MRCTRL0_MR_RANK_DEFVAL                                                0x00000030
+#define DDRC_MRCTRL0_MR_RANK_SHIFT                                                 4
+#define DDRC_MRCTRL0_MR_RANK_MASK                                                  0x00000030U
+
+/*Indicates whether Software intervention is allowed via MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. 
+		or DDR4, this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4, this bit ca
+		 be used to program additional mode registers before automatic SDRAM initialization if necessary. Note: This must be cleared 
+		o 0 after completing Software operation. Otherwise, SDRAM initialization routine will not re-start. - 0 - Software interventi
+		n is not allowed - 1 - Software intervention is allowed*/
+#undef DDRC_MRCTRL0_SW_INIT_INT_DEFVAL 
+#undef DDRC_MRCTRL0_SW_INIT_INT_SHIFT 
+#undef DDRC_MRCTRL0_SW_INIT_INT_MASK 
+#define DDRC_MRCTRL0_SW_INIT_INT_DEFVAL                                            0x00000030
+#define DDRC_MRCTRL0_SW_INIT_INT_SHIFT                                             3
+#define DDRC_MRCTRL0_SW_INIT_INT_MASK                                              0x00000008U
+
+/*Indicates whether the mode register operation is MRS in PDA mode or not - 0 - MRS - 1 - MRS in Per DRAM Addressability mode*/
+#undef DDRC_MRCTRL0_PDA_EN_DEFVAL 
+#undef DDRC_MRCTRL0_PDA_EN_SHIFT 
+#undef DDRC_MRCTRL0_PDA_EN_MASK 
+#define DDRC_MRCTRL0_PDA_EN_DEFVAL                                                 0x00000030
+#define DDRC_MRCTRL0_PDA_EN_SHIFT                                                  2
+#define DDRC_MRCTRL0_PDA_EN_MASK                                                   0x00000004U
+
+/*Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4) - 0 - MRS - 1 - WR/RD for MPR*/
+#undef DDRC_MRCTRL0_MPR_EN_DEFVAL 
+#undef DDRC_MRCTRL0_MPR_EN_SHIFT 
+#undef DDRC_MRCTRL0_MPR_EN_MASK 
+#define DDRC_MRCTRL0_MPR_EN_DEFVAL                                                 0x00000030
+#define DDRC_MRCTRL0_MPR_EN_SHIFT                                                  1
+#define DDRC_MRCTRL0_MPR_EN_MASK                                                   0x00000002U
+
+/*Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Re
+		d*/
+#undef DDRC_MRCTRL0_MR_TYPE_DEFVAL 
+#undef DDRC_MRCTRL0_MR_TYPE_SHIFT 
+#undef DDRC_MRCTRL0_MR_TYPE_MASK 
+#define DDRC_MRCTRL0_MR_TYPE_DEFVAL                                                0x00000030
+#define DDRC_MRCTRL0_MR_TYPE_SHIFT                                                 0
+#define DDRC_MRCTRL0_MR_TYPE_MASK                                                  0x00000001U
+
+/*Derate value of tRC for LPDDR4 - 0 - Derating uses +1. - 1 - Derating uses +2. - 2 - Derating uses +3. - 3 - Derating uses +4
+		 Present only in designs configured to support LPDDR4. The required number of cycles for derating can be determined by dividi
+		g 3.75ns by the core_ddrc_core_clk period, and rounding up the next integer.*/
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL 
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT 
+#undef DDRC_DERATEEN_RC_DERATE_VALUE_MASK 
+#define DDRC_DERATEEN_RC_DERATE_VALUE_DEFVAL                                       0x00000000
+#define DDRC_DERATEEN_RC_DERATE_VALUE_SHIFT                                        8
+#define DDRC_DERATEEN_RC_DERATE_VALUE_MASK                                         0x00000300U
+
+/*Derate byte Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 Indicates which byte of the MRR data is used f
+		r derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH.*/
+#undef DDRC_DERATEEN_DERATE_BYTE_DEFVAL 
+#undef DDRC_DERATEEN_DERATE_BYTE_SHIFT 
+#undef DDRC_DERATEEN_DERATE_BYTE_MASK 
+#define DDRC_DERATEEN_DERATE_BYTE_DEFVAL                                           0x00000000
+#define DDRC_DERATEEN_DERATE_BYTE_SHIFT                                            4
+#define DDRC_DERATEEN_DERATE_BYTE_MASK                                             0x000000F0U
+
+/*Derate value - 0 - Derating uses +1. - 1 - Derating uses +2. Present only in designs configured to support LPDDR2/LPDDR3/LPDD
+		4 Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. Can be 0 or 1
+		for LPDDR3/LPDDR4, depending if +1.875 ns is less than a core_ddrc_core_clk period or not.*/
+#undef DDRC_DERATEEN_DERATE_VALUE_DEFVAL 
+#undef DDRC_DERATEEN_DERATE_VALUE_SHIFT 
+#undef DDRC_DERATEEN_DERATE_VALUE_MASK 
+#define DDRC_DERATEEN_DERATE_VALUE_DEFVAL                                          0x00000000
+#define DDRC_DERATEEN_DERATE_VALUE_SHIFT                                           1
+#define DDRC_DERATEEN_DERATE_VALUE_MASK                                            0x00000002U
+
+/*Enables derating - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value.
+		Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4 This field must be set to '0' for non-LPDDR2/LPDDR3/LPDDR4
+		mode.*/
+#undef DDRC_DERATEEN_DERATE_ENABLE_DEFVAL 
+#undef DDRC_DERATEEN_DERATE_ENABLE_SHIFT 
+#undef DDRC_DERATEEN_DERATE_ENABLE_MASK 
+#define DDRC_DERATEEN_DERATE_ENABLE_DEFVAL                                         0x00000000
+#define DDRC_DERATEEN_DERATE_ENABLE_SHIFT                                          0
+#define DDRC_DERATEEN_DERATE_ENABLE_MASK                                           0x00000001U
+
+/*Interval between two MR4 reads, used to derate the timing parameters. Present only in designs configured to support LPDDR2/LP
+		DR3/LPDDR4. This register must not be set to zero*/
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL 
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT 
+#undef DDRC_DERATEINT_MR4_READ_INTERVAL_MASK 
+#define DDRC_DERATEINT_MR4_READ_INTERVAL_DEFVAL                                    
+#define DDRC_DERATEINT_MR4_READ_INTERVAL_SHIFT                                     0
+#define DDRC_DERATEINT_MR4_READ_INTERVAL_MASK                                      0xFFFFFFFFU
+
+/*Self refresh state is an intermediate state to enter to Self refresh power down state or exit Self refresh power down state f
+		r LPDDR4. This register controls transition from the Self refresh state. - 1 - Prohibit transition from Self refresh state - 
+		 - Allow transition from Self refresh state*/
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL 
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT 
+#undef DDRC_PWRCTL_STAY_IN_SELFREF_MASK 
+#define DDRC_PWRCTL_STAY_IN_SELFREF_DEFVAL                                         0x00000000
+#define DDRC_PWRCTL_STAY_IN_SELFREF_SHIFT                                          6
+#define DDRC_PWRCTL_STAY_IN_SELFREF_MASK                                           0x00000040U
+
+/*A value of 1 to this register causes system to move to Self Refresh state immediately, as long as it is not in INIT or DPD/MP
+		M operating_mode. This is referred to as Software Entry/Exit to Self Refresh. - 1 - Software Entry to Self Refresh - 0 - Soft
+		are Exit from Self Refresh*/
+#undef DDRC_PWRCTL_SELFREF_SW_DEFVAL 
+#undef DDRC_PWRCTL_SELFREF_SW_SHIFT 
+#undef DDRC_PWRCTL_SELFREF_SW_MASK 
+#define DDRC_PWRCTL_SELFREF_SW_DEFVAL                                              0x00000000
+#define DDRC_PWRCTL_SELFREF_SW_SHIFT                                               5
+#define DDRC_PWRCTL_SELFREF_SW_MASK                                                0x00000020U
+
+/*When this is 1, the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register m
+		st be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support DDR4. For 
+		on-DDR4, this register should not be set to 1. Note that MPSM is not supported when using a DWC DDR PHY, if the PHY parameter
+		DWC_AC_CS_USE is disabled, as the MPSM exit sequence requires the chip-select signal to toggle. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PWRCTL_MPSM_EN_DEFVAL 
+#undef DDRC_PWRCTL_MPSM_EN_SHIFT 
+#undef DDRC_PWRCTL_MPSM_EN_MASK 
+#define DDRC_PWRCTL_MPSM_EN_DEFVAL                                                 0x00000000
+#define DDRC_PWRCTL_MPSM_EN_SHIFT                                                  4
+#define DDRC_PWRCTL_MPSM_EN_MASK                                                   0x00000010U
+
+/*Enable the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0, dfi_dram_clk_disable
+		is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3, can only be asserted in Self Refresh. In DD
+		4, can be asserted in following: - in Self Refresh. - in Maximum Power Saving Mode In mDDR/LPDDR2/LPDDR3, can be asserted in 
+		ollowing: - in Self Refresh - in Power Down - in Deep Power Down - during Normal operation (Clock Stop) In LPDDR4, can be ass
+		rted in following: - in Self Refresh Power Down - in Power Down - during Normal operation (Clock Stop)*/
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL 
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT 
+#undef DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK 
+#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_DEFVAL                                 0x00000000
+#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_SHIFT                                  3
+#define DDRC_PWRCTL_EN_DFI_DRAM_CLK_DISABLE_MASK                                   0x00000008U
+
+/*When this is 1, uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be re
+		et to '0' to bring uMCTL2 out of deep power-down mode. Controller performs automatic SDRAM initialization on deep power-down 
+		xit. Present only in designs configured to support mDDR or LPDDR2 or LPDDR3. For non-mDDR/non-LPDDR2/non-LPDDR3, this registe
+		 should not be set to 1. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL 
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT 
+#undef DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK 
+#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_DEFVAL                                        0x00000000
+#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_SHIFT                                         2
+#define DDRC_PWRCTL_DEEPPOWERDOWN_EN_MASK                                          0x00000004U
+
+/*If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (P
+		RTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation.*/
+#undef DDRC_PWRCTL_POWERDOWN_EN_DEFVAL 
+#undef DDRC_PWRCTL_POWERDOWN_EN_SHIFT 
+#undef DDRC_PWRCTL_POWERDOWN_EN_MASK 
+#define DDRC_PWRCTL_POWERDOWN_EN_DEFVAL                                            0x00000000
+#define DDRC_PWRCTL_POWERDOWN_EN_SHIFT                                             1
+#define DDRC_PWRCTL_POWERDOWN_EN_MASK                                              0x00000002U
+
+/*If true then the uMCTL2 puts the SDRAM into Self Refresh after a programmable number of cycles 'maximum idle clocks before Se
+		f Refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation.*/
+#undef DDRC_PWRCTL_SELFREF_EN_DEFVAL 
+#undef DDRC_PWRCTL_SELFREF_EN_SHIFT 
+#undef DDRC_PWRCTL_SELFREF_EN_MASK 
+#define DDRC_PWRCTL_SELFREF_EN_DEFVAL                                              0x00000000
+#define DDRC_PWRCTL_SELFREF_EN_SHIFT                                               0
+#define DDRC_PWRCTL_SELFREF_EN_MASK                                                0x00000001U
+
+/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into Self Refresh. This must be enabled in 
+		he PWRCTL.selfref_en. Unit: Multiples of 32 clocks. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL 
+#undef DDRC_PWRTMG_SELFREF_TO_X32_SHIFT 
+#undef DDRC_PWRTMG_SELFREF_TO_X32_MASK 
+#define DDRC_PWRTMG_SELFREF_TO_X32_DEFVAL                                          0x00402010
+#define DDRC_PWRTMG_SELFREF_TO_X32_SHIFT                                           16
+#define DDRC_PWRTMG_SELFREF_TO_X32_MASK                                            0x00FF0000U
+
+/*Minimum deep power-down time. For mDDR, value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immed
+		ately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3, value from the JEDEC specification is 500us. Unit: Mul
+		iples of 4096 clocks. Present only in designs configured to support mDDR, LPDDR2 or LPDDR3. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PWRTMG_T_DPD_X4096_DEFVAL 
+#undef DDRC_PWRTMG_T_DPD_X4096_SHIFT 
+#undef DDRC_PWRTMG_T_DPD_X4096_MASK 
+#define DDRC_PWRTMG_T_DPD_X4096_DEFVAL                                             0x00402010
+#define DDRC_PWRTMG_T_DPD_X4096_SHIFT                                              8
+#define DDRC_PWRTMG_T_DPD_X4096_MASK                                               0x0000FF00U
+
+/*After this many clocks of NOP or deselect the uMCTL2 automatically puts the SDRAM into power-down. This must be enabled in th
+		 PWRCTL.powerdown_en. Unit: Multiples of 32 clocks FOR PERFORMANCE ONLY.*/
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL 
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT 
+#undef DDRC_PWRTMG_POWERDOWN_TO_X32_MASK 
+#define DDRC_PWRTMG_POWERDOWN_TO_X32_DEFVAL                                        0x00402010
+#define DDRC_PWRTMG_POWERDOWN_TO_X32_SHIFT                                         0
+#define DDRC_PWRTMG_POWERDOWN_TO_X32_MASK                                          0x0000001FU
+
+/*Threshold value in number of clock cycles before the critical refresh or page timer expires. A critical refresh is to be issu
+		d before this threshold is reached. It is recommended that this not be changed from the default value, currently shown as 0x2
+		 It must always be less than internally used t_rfc_nom_x32. Note that, in LPDDR2/LPDDR3/LPDDR4, internally used t_rfc_nom_x32
+		may be equal to RFSHTMG.t_rfc_nom_x32>>2 if derating is enabled (DERATEEN.derate_enable=1). Otherwise, internally used t_rfc_
+		om_x32 will be equal to RFSHTMG.t_rfc_nom_x32. Unit: Multiples of 32 clocks.*/
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL 
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT 
+#undef DDRC_RFSHCTL0_REFRESH_MARGIN_MASK 
+#define DDRC_RFSHCTL0_REFRESH_MARGIN_DEFVAL                                        0x00210000
+#define DDRC_RFSHCTL0_REFRESH_MARGIN_SHIFT                                         20
+#define DDRC_RFSHCTL0_REFRESH_MARGIN_MASK                                          0x00F00000U
+
+/*If the refresh timer (tRFCnom, also known as tREFI) has expired at least once, but it has not expired (RFSHCTL0.refresh_burst
+		1) times yet, then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refres
+		 would be useful, but before it is absolutely required. When the SDRAM bus is idle for a period of time determined by this RF
+		HCTL0.refresh_to_x32 and the refresh timer has expired at least once since the last refresh, then a speculative refresh is pe
+		formed. Speculative refreshes continues successively until there are no refreshes pending or until new reads or writes are is
+		ued to the uMCTL2. FOR PERFORMANCE ONLY.*/
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL 
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT 
+#undef DDRC_RFSHCTL0_REFRESH_TO_X32_MASK 
+#define DDRC_RFSHCTL0_REFRESH_TO_X32_DEFVAL                                        0x00210000
+#define DDRC_RFSHCTL0_REFRESH_TO_X32_SHIFT                                         12
+#define DDRC_RFSHCTL0_REFRESH_TO_X32_MASK                                          0x0001F000U
+
+/*The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the re
+		reshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each group of re
+		reshes. Therefore, performing refreshes in a burst reduces the per-refresh penalty of these page closings. Higher numbers for
+		RFSHCTL.refresh_burst slightly increases utilization; lower numbers decreases the worst-case latency associated with refreshe
+		. - 0 - single refresh - 1 - burst-of-2 refresh - 7 - burst-of-8 refresh For information on burst refresh feature refer to se
+		tion 3.9 of DDR2 JEDEC specification - JESD79-2F.pdf. For DDR2/3, the refresh is always per-rank and not per-bank. The rank r
+		fresh can be accumulated over 8*tREFI cycles using the burst refresh feature. In DDR4 mode, according to Fine Granularity fea
+		ure, 8 refreshes can be postponed in 1X mode, 16 refreshes in 2X mode and 32 refreshes in 4X mode. If using PHY-initiated upd
+		tes, care must be taken in the setting of RFSHCTL0.refresh_burst, to ensure that tRFCmax is not violated due to a PHY-initiat
+		d update occurring shortly before a refresh burst was due. In this situation, the refresh burst will be delayed until the PHY
+		initiated update is complete.*/
+#undef DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL 
+#undef DDRC_RFSHCTL0_REFRESH_BURST_SHIFT 
+#undef DDRC_RFSHCTL0_REFRESH_BURST_MASK 
+#define DDRC_RFSHCTL0_REFRESH_BURST_DEFVAL                                         0x00210000
+#define DDRC_RFSHCTL0_REFRESH_BURST_SHIFT                                          4
+#define DDRC_RFSHCTL0_REFRESH_BURST_MASK                                           0x000001F0U
+
+/*- 1 - Per bank refresh; - 0 - All bank refresh. Per bank refresh allows traffic to flow to other banks. Per bank refresh is n
+		t supported by all LPDDR2 devices but should be supported by all LPDDR3/LPDDR4 devices. Present only in designs configured to
+		support LPDDR2/LPDDR3/LPDDR4*/
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL 
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT 
+#undef DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK 
+#define DDRC_RFSHCTL0_PER_BANK_REFRESH_DEFVAL                                      0x00210000
+#define DDRC_RFSHCTL0_PER_BANK_REFRESH_SHIFT                                       2
+#define DDRC_RFSHCTL0_PER_BANK_REFRESH_MASK                                        0x00000004U
+
+/*Fine Granularity Refresh Mode - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (
+		ot supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: The on-the-fly modes is not sup
+		orted in this version of the uMCTL2. Note: This must be set up while the Controller is in reset or while the Controller is in
+		self-refresh mode. Changing this during normal operation is not allowed. Making this a dynamic register will be supported in 
+		uture version of the uMCTL2.*/
+#undef DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL 
+#undef DDRC_RFSHCTL3_REFRESH_MODE_SHIFT 
+#undef DDRC_RFSHCTL3_REFRESH_MODE_MASK 
+#define DDRC_RFSHCTL3_REFRESH_MODE_DEFVAL                                          0x00000000
+#define DDRC_RFSHCTL3_REFRESH_MODE_SHIFT                                           4
+#define DDRC_RFSHCTL3_REFRESH_MODE_MASK                                            0x00000070U
+
+/*Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh register(s) have been updated. The value 
+		s automatically updated when exiting reset, so it does not need to be toggled initially.*/
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL 
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT 
+#undef DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK 
+#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_DEFVAL                                  0x00000000
+#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_SHIFT                                   1
+#define DDRC_RFSHCTL3_REFRESH_UPDATE_LEVEL_MASK                                    0x00000002U
+
+/*When '1', disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled, the SoC core must generate refreshes u
+		ing the registers reg_ddrc_rank0_refresh, reg_ddrc_rank1_refresh, reg_ddrc_rank2_refresh and reg_ddrc_rank3_refresh. When dis
+		auto_refresh transitions from 0 to 1, any pending refreshes are immediately scheduled by the uMCTL2. If DDR4 CRC/parity retry
+		is enabled (CRCPARCTL1.crc_parity_retry_enable = 1), disable auto-refresh is not supported, and this bit must be set to '0'. 
+		his register field is changeable on the fly.*/
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL 
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT 
+#undef DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK 
+#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_DEFVAL                                      0x00000000
+#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_SHIFT                                       0
+#define DDRC_RFSHCTL3_DIS_AUTO_REFRESH_MASK                                        0x00000001U
+
+/*tREFI: Average time interval between refreshes per rank (Specification: 7.8us for DDR2, DDR3 and DDR4. See JEDEC specificatio
+		 for mDDR, LPDDR2, LPDDR3 and LPDDR4). For LPDDR2/LPDDR3/LPDDR4: - if using all-bank refreshes (RFSHCTL0.per_bank_refresh = 0
+		, this register should be set to tREFIab - if using per-bank refreshes (RFSHCTL0.per_bank_refresh = 1), this register should 
+		e set to tREFIpb For configurations with MEMC_FREQ_RATIO=2, program this to (tREFI/2), no rounding up. In DDR4 mode, tREFI va
+		ue is different depending on the refresh mode. The user should program the appropriate value from the spec based on the value
+		programmed in the refresh mode register. Note that RFSHTMG.t_rfc_nom_x32 * 32 must be greater than RFSHTMG.t_rfc_min, and RFS
+		TMG.t_rfc_nom_x32 must be greater than 0x1. Unit: Multiples of 32 clocks.*/
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL 
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT 
+#undef DDRC_RFSHTMG_T_RFC_NOM_X32_MASK 
+#define DDRC_RFSHTMG_T_RFC_NOM_X32_DEFVAL                                          0x0062008C
+#define DDRC_RFSHTMG_T_RFC_NOM_X32_SHIFT                                           16
+#define DDRC_RFSHTMG_T_RFC_NOM_X32_MASK                                            0x0FFF0000U
+
+/*Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the 
+		REFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC specification) or not
+		 - 0 - tREFBW parameter not used - 1 - tREFBW parameter used*/
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL 
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT 
+#undef DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK 
+#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_DEFVAL                                       0x0062008C
+#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_SHIFT                                        15
+#define DDRC_RFSHTMG_LPDDR3_TREFBW_EN_MASK                                         0x00008000U
+
+/*tRFC (min): Minimum time from refresh to refresh or activate. For MEMC_FREQ_RATIO=1 configurations, t_rfc_min should be set t
+		 RoundUp(tRFCmin/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rfc_min should be set to RoundUp(RoundUp(tRFCmin/tCK)/2). In L
+		DDR2/LPDDR3/LPDDR4 mode: - if using all-bank refreshes, the tRFCmin value in the above equations is equal to tRFCab - if usin
+		 per-bank refreshes, the tRFCmin value in the above equations is equal to tRFCpb In DDR4 mode, the tRFCmin value in the above
+		equations is different depending on the refresh mode (fixed 1X,2X,4X) and the device density. The user should program the app
+		opriate value from the spec based on the 'refresh_mode' and the device density that is used. Unit: Clocks.*/
+#undef DDRC_RFSHTMG_T_RFC_MIN_DEFVAL 
+#undef DDRC_RFSHTMG_T_RFC_MIN_SHIFT 
+#undef DDRC_RFSHTMG_T_RFC_MIN_MASK 
+#define DDRC_RFSHTMG_T_RFC_MIN_DEFVAL                                              0x0062008C
+#define DDRC_RFSHTMG_T_RFC_MIN_SHIFT                                               0
+#define DDRC_RFSHTMG_T_RFC_MIN_MASK                                                0x000003FFU
+
+/*Disable ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 and MEMC_USE_RMW is defined*/
+#undef DDRC_ECCCFG0_DIS_SCRUB_DEFVAL 
+#undef DDRC_ECCCFG0_DIS_SCRUB_SHIFT 
+#undef DDRC_ECCCFG0_DIS_SCRUB_MASK 
+#define DDRC_ECCCFG0_DIS_SCRUB_DEFVAL                                              0x00000000
+#define DDRC_ECCCFG0_DIS_SCRUB_SHIFT                                               4
+#define DDRC_ECCCFG0_DIS_SCRUB_MASK                                                0x00000010U
+
+/*ECC mode indicator - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - all other settings are reserved for futur
+		 use*/
+#undef DDRC_ECCCFG0_ECC_MODE_DEFVAL 
+#undef DDRC_ECCCFG0_ECC_MODE_SHIFT 
+#undef DDRC_ECCCFG0_ECC_MODE_MASK 
+#define DDRC_ECCCFG0_ECC_MODE_DEFVAL                                               0x00000000
+#define DDRC_ECCCFG0_ECC_MODE_SHIFT                                                0
+#define DDRC_ECCCFG0_ECC_MODE_MASK                                                 0x00000007U
+
+/*Selects whether to poison 1 or 2 bits - if 0 -> 2-bit (uncorrectable) data poisoning, if 1 -> 1-bit (correctable) data poison
+		ng, if ECCCFG1.data_poison_en=1*/
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL 
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT 
+#undef DDRC_ECCCFG1_DATA_POISON_BIT_MASK 
+#define DDRC_ECCCFG1_DATA_POISON_BIT_DEFVAL                                        0x00000000
+#define DDRC_ECCCFG1_DATA_POISON_BIT_SHIFT                                         1
+#define DDRC_ECCCFG1_DATA_POISON_BIT_MASK                                          0x00000002U
+
+/*Enable ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers*/
+#undef DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL 
+#undef DDRC_ECCCFG1_DATA_POISON_EN_SHIFT 
+#undef DDRC_ECCCFG1_DATA_POISON_EN_MASK 
+#define DDRC_ECCCFG1_DATA_POISON_EN_DEFVAL                                         0x00000000
+#define DDRC_ECCCFG1_DATA_POISON_EN_SHIFT                                          0
+#define DDRC_ECCCFG1_DATA_POISON_EN_MASK                                           0x00000001U
+
+/*The maximum number of DFI PHY clock cycles allowed from the assertion of the dfi_rddata_en signal to the assertion of each of
+		the corresponding bits of the dfi_rddata_valid signal. This corresponds to the DFI timing parameter tphy_rdlat. Refer to PHY 
+		pecification for correct value. This value it only used for detecting read data timeout when DDR4 retry is enabled by CRCPARC
+		L1.crc_parity_retry_enable=1. Maximum supported value: - 1:1 Frequency mode : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_
+		dlat < 'd114 - 1:2 Frequency mode ANDAND DFITMG0.dfi_rddata_use_sdr == 1 : CRCPARCTL1.dfi_t_phy_rdlat < 64 - 1:2 Frequency mo
+		e ANDAND DFITMG0.dfi_rddata_use_sdr == 0 : DFITMG0.dfi_t_rddata_en + CRCPARCTL1.dfi_t_phy_rdlat < 'd114 Unit: DFI Clocks*/
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL 
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT 
+#undef DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK 
+#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_DEFVAL                                     0x10000200
+#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_SHIFT                                      24
+#define DDRC_CRCPARCTL1_DFI_T_PHY_RDLAT_MASK                                       0x3F000000U
+
+/*After a Parity or CRC error is flagged on dfi_alert_n signal, the software has an option to read the mode registers in the DR
+		M before the hardware begins the retry process - 1: Wait for software to read/write the mode registers before hardware begins
+		the retry. After software is done with its operations, it will clear the alert interrupt register bit - 0: Hardware can begin
+		the retry right away after the dfi_alert_n pulse goes away. The value on this register is valid only when retry is enabled (P
+		RCTRL.crc_parity_retry_enable = 1) If this register is set to 1 and if the software doesn't clear the interrupt register afte
+		 handling the parity/CRC error, then the hardware will not begin the retry process and the system will hang. In the case of P
+		rity/CRC error, there are two possibilities when the software doesn't reset MR5[4] to 0. - (i) If 'Persistent parity' mode re
+		ister bit is NOT set: the commands sent during retry and normal operation are executed without parity checking. The value in 
+		he Parity error log register MPR Page 1 is valid. - (ii) If 'Persistent parity' mode register bit is SET: Parity checking is 
+		one for commands sent during retry and normal operation. If multiple errors occur before MR5[4] is cleared, the error log in 
+		PR Page 1 should be treated as 'Don't care'.*/
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL 
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT 
+#undef DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK 
+#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_DEFVAL                                   0x10000200
+#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_SHIFT                                    9
+#define DDRC_CRCPARCTL1_ALERT_WAIT_FOR_SW_MASK                                     0x00000200U
+
+/*- 1: Enable command retry mechanism in case of C/A Parity or CRC error - 0: Disable command retry mechanism when C/A Parity o
+		 CRC features are enabled. Note that retry functionality is not supported if burst chop is enabled (MSTR.burstchop = 1) and/o
+		 disable auto-refresh is enabled (RFSHCTL3.dis_auto_refresh = 1)*/
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL 
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT 
+#undef DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK 
+#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_DEFVAL                             0x10000200
+#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_SHIFT                              8
+#define DDRC_CRCPARCTL1_CRC_PARITY_RETRY_ENABLE_MASK                               0x00000100U
+
+/*CRC Calculation setting register - 1: CRC includes DM signal - 0: CRC not includes DM signal Present only in designs configur
+		d to support DDR4.*/
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL 
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT 
+#undef DDRC_CRCPARCTL1_CRC_INC_DM_MASK 
+#define DDRC_CRCPARCTL1_CRC_INC_DM_DEFVAL                                          0x10000200
+#define DDRC_CRCPARCTL1_CRC_INC_DM_SHIFT                                           7
+#define DDRC_CRCPARCTL1_CRC_INC_DM_MASK                                            0x00000080U
+
+/*CRC enable Register - 1: Enable generation of CRC - 0: Disable generation of CRC The setting of this register should match th
+		 CRC mode register setting in the DRAM.*/
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL 
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT 
+#undef DDRC_CRCPARCTL1_CRC_ENABLE_MASK 
+#define DDRC_CRCPARCTL1_CRC_ENABLE_DEFVAL                                          0x10000200
+#define DDRC_CRCPARCTL1_CRC_ENABLE_SHIFT                                           4
+#define DDRC_CRCPARCTL1_CRC_ENABLE_MASK                                            0x00000010U
+
+/*C/A Parity enable register - 1: Enable generation of C/A parity and detection of C/A parity error - 0: Disable generation of 
+		/A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection is enabled, t
+		is register should be 1.*/
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL 
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT 
+#undef DDRC_CRCPARCTL1_PARITY_ENABLE_MASK 
+#define DDRC_CRCPARCTL1_PARITY_ENABLE_DEFVAL                                       0x10000200
+#define DDRC_CRCPARCTL1_PARITY_ENABLE_SHIFT                                        0
+#define DDRC_CRCPARCTL1_PARITY_ENABLE_MASK                                         0x00000001U
+
+/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a parity error occurs. Recommended values
+		 - tPAR_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tPAR_ALERT_PW.MAX/2 and round up to next inte
+		er value. Values of 0, 1 and 2 are illegal. This value must be greater than CRCPARCTL2.t_crc_alert_pw_max.*/
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL 
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT 
+#undef DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK 
+#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_DEFVAL                                  0x0030050C
+#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_SHIFT                                   16
+#define DDRC_CRCPARCTL2_T_PAR_ALERT_PW_MAX_MASK                                    0x01FF0000U
+
+/*Value from the DRAM spec indicating the maximum width of the dfi_alert_n pulse when a CRC error occurs. Recommended values: -
+		tCRC_ALERT_PW.MAX For configurations with MEMC_FREQ_RATIO=2, program this to tCRC_ALERT_PW.MAX/2 and round up to next integer
+		value. Values of 0, 1 and 2 are illegal. This value must be less than CRCPARCTL2.t_par_alert_pw_max.*/
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL 
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT 
+#undef DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK 
+#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_DEFVAL                                  0x0030050C
+#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_SHIFT                                   8
+#define DDRC_CRCPARCTL2_T_CRC_ALERT_PW_MAX_MASK                                    0x00001F00U
+
+/*Indicates the maximum duration in number of DRAM clock cycles for which a command should be held in the Command Retry FIFO be
+		ore it is popped out. Every location in the Command Retry FIFO has an associated down counting timer that will use this regis
+		er as the start value. The down counting starts when a command is loaded into the FIFO. The timer counts down every 4 DRAM cy
+		les. When the counter reaches zero, the entry is popped from the FIFO. All the counters are frozen, if a C/A Parity or CRC er
+		or occurs before the counter reaches zero. The counter is reset to 0, after all the commands in the FIFO are retried. Recomme
+		ded(minimum) values: - Only C/A Parity is enabled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + tPAR_ALERT_ON
+		max + tPAR_UNKNOWN + PHY Alert Latency(DRAM CLK) + board delay) / 4) + 2 - Both C/A Parity and CRC is enabled/ Only CRC is en
+		bled. RoundUp((PHY Command Latency(DRAM CLK) + CAL + RDIMM delay + WL + 5(BL10)+ tCRC_ALERT.max + PHY Alert Latency(DRAM CLK)
+		+ board delay) / 4) + 2 Note 1: All value (e.g. tPAR_ALERT_ON) should be in terms of DRAM Clock and round up Note 2: Board de
+		ay(Command/Alert_n) should be considered. Note 3: Use the worst case(longer) value for PHY Latencies/Board delay Note 4: The 
+		ecommended values are minimum value to be set. For mode detail, See 'Calculation of FIFO Depth' section. Max value can be set
+		to this register is defined below: - MEMC_BURST_LENGTH == 16 Full bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-
+		 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Half bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_D
+		PTH-4 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-6 Quarter bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CM
+		_FIFO_DEPTH-8 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-12 - MEMC_BURST_LENGTH != 16 Full bus Mode (C
+		C=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-1 Full bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mo
+		e (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-2 Half bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-3 Quarte
+		 bus Mode (CRC=OFF) Max value = UMCTL2_RETRY_CMD_FIFO_DEPTH-4 Quarter bus Mode (CRC=ON) Max value = UMCTL2_RETRY_CMD_FIFO_DEP
+		H-6 Values of 0, 1 and 2 are illegal.*/
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL 
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT 
+#undef DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK 
+#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_DEFVAL                        0x0030050C
+#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_SHIFT                         0
+#define DDRC_CRCPARCTL2_RETRY_FIFO_MAX_HOLD_TIMER_X4_MASK                          0x0000003FU
+
+/*If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts u
+		 in when reset is removed - 00 - SDRAM Intialization routine is run after power-up - 01 - SDRAM Intialization routine is skip
+		ed after power-up. Controller starts up in Normal Mode - 11 - SDRAM Intialization routine is skipped after power-up. Controll
+		r starts up in Self-refresh Mode - 10 - SDRAM Intialization routine is run after power-up. Note: The only 2'b00 is supported 
+		or LPDDR4 in this version of the uMCTL2.*/
+#undef DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL 
+#undef DDRC_INIT0_SKIP_DRAM_INIT_SHIFT 
+#undef DDRC_INIT0_SKIP_DRAM_INIT_MASK 
+#define DDRC_INIT0_SKIP_DRAM_INIT_DEFVAL                                           0x0002004E
+#define DDRC_INIT0_SKIP_DRAM_INIT_SHIFT                                            30
+#define DDRC_INIT0_SKIP_DRAM_INIT_MASK                                             0xC0000000U
+
+/*Cycles to wait after driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clocks. DDR2 typically requires 
+		 400 ns delay, requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically requires this to be pr
+		grammed for a delay of 200 us. LPDDR4 typically requires this to be programmed for a delay of 2 us. For configurations with M
+		MC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it up to next integer value.*/
+#undef DDRC_INIT0_POST_CKE_X1024_DEFVAL 
+#undef DDRC_INIT0_POST_CKE_X1024_SHIFT 
+#undef DDRC_INIT0_POST_CKE_X1024_MASK 
+#define DDRC_INIT0_POST_CKE_X1024_DEFVAL                                           0x0002004E
+#define DDRC_INIT0_POST_CKE_X1024_SHIFT                                            16
+#define DDRC_INIT0_POST_CKE_X1024_MASK                                             0x03FF0000U
+
+/*Cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. Unit: 1024 clock cycles. DDR2 
+		pecifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns (min) LPDDR4:
+		tINIT3 of 2 ms (min) For configurations with MEMC_FREQ_RATIO=2, program this to JEDEC spec value divided by 2, and round it u
+		 to next integer value.*/
+#undef DDRC_INIT0_PRE_CKE_X1024_DEFVAL 
+#undef DDRC_INIT0_PRE_CKE_X1024_SHIFT 
+#undef DDRC_INIT0_PRE_CKE_X1024_MASK 
+#define DDRC_INIT0_PRE_CKE_X1024_DEFVAL                                            0x0002004E
+#define DDRC_INIT0_PRE_CKE_X1024_SHIFT                                             0
+#define DDRC_INIT0_PRE_CKE_X1024_MASK                                              0x00000FFFU
+
+/*Number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3, DDR4 or
+		LPDDR4 devices. For use with a DDR PHY, this should be set to a minimum of 1*/
+#undef DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL 
+#undef DDRC_INIT1_DRAM_RSTN_X1024_SHIFT 
+#undef DDRC_INIT1_DRAM_RSTN_X1024_MASK 
+#define DDRC_INIT1_DRAM_RSTN_X1024_DEFVAL                                          0x00000000
+#define DDRC_INIT1_DRAM_RSTN_X1024_SHIFT                                           16
+#define DDRC_INIT1_DRAM_RSTN_X1024_MASK                                            0x01FF0000U
+
+/*Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a gl
+		bal timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero.*/
+#undef DDRC_INIT1_FINAL_WAIT_X32_DEFVAL 
+#undef DDRC_INIT1_FINAL_WAIT_X32_SHIFT 
+#undef DDRC_INIT1_FINAL_WAIT_X32_MASK 
+#define DDRC_INIT1_FINAL_WAIT_X32_DEFVAL                                           0x00000000
+#define DDRC_INIT1_FINAL_WAIT_X32_SHIFT                                            8
+#define DDRC_INIT1_FINAL_WAIT_X32_MASK                                             0x00007F00U
+
+/*Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycle
+		. There is no known specific requirement for this; it may be set to zero.*/
+#undef DDRC_INIT1_PRE_OCD_X32_DEFVAL 
+#undef DDRC_INIT1_PRE_OCD_X32_SHIFT 
+#undef DDRC_INIT1_PRE_OCD_X32_MASK 
+#define DDRC_INIT1_PRE_OCD_X32_DEFVAL                                              0x00000000
+#define DDRC_INIT1_PRE_OCD_X32_SHIFT                                               0
+#define DDRC_INIT1_PRE_OCD_X32_MASK                                                0x0000000FU
+
+/*Idle time after the reset command, tINIT4. Present only in designs configured to support LPDDR2. Unit: 32 clock cycles.*/
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL 
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT 
+#undef DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK 
+#define DDRC_INIT2_IDLE_AFTER_RESET_X32_DEFVAL                                     0x00000D05
+#define DDRC_INIT2_IDLE_AFTER_RESET_X32_SHIFT                                      8
+#define DDRC_INIT2_IDLE_AFTER_RESET_X32_MASK                                       0x0000FF00U
+
+/*Time to wait after the first CKE high, tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. Unit: 1 clock cyc
+		e. LPDDR2/LPDDR3 typically requires 5 x tCK delay.*/
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL 
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT 
+#undef DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK 
+#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_DEFVAL                                      0x00000D05
+#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_SHIFT                                       0
+#define DDRC_INIT2_MIN_STABLE_CLOCK_X1_MASK                                        0x0000000FU
+
+/*DDR2: Value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately
+		 DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to write to MR1
+		register*/
+#undef DDRC_INIT3_MR_DEFVAL 
+#undef DDRC_INIT3_MR_SHIFT 
+#undef DDRC_INIT3_MR_MASK 
+#define DDRC_INIT3_MR_DEFVAL                                                       0x00000510
+#define DDRC_INIT3_MR_SHIFT                                                        16
+#define DDRC_INIT3_MR_MASK                                                         0xFFFF0000U
+
+/*DDR2: Value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those
+		bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. If PHY-evaluation mode training is enabled, thi
+		 bit is set appropriately by the uMCTL2 during write leveling. mDDR: Value to write to EMR register. LPDDR2/LPDDR3/LPDDR4 - V
+		lue to write to MR2 register*/
+#undef DDRC_INIT3_EMR_DEFVAL 
+#undef DDRC_INIT3_EMR_SHIFT 
+#undef DDRC_INIT3_EMR_MASK 
+#define DDRC_INIT3_EMR_DEFVAL                                                      0x00000510
+#define DDRC_INIT3_EMR_SHIFT                                                       0
+#define DDRC_INIT3_EMR_MASK                                                        0x0000FFFFU
+
+/*DDR2: Value to write to EMR2 register. DDR3/DDR4: Value to write to MR2 register LPDDR2/LPDDR3/LPDDR4: Value to write to MR3 
+		egister mDDR: Unused*/
+#undef DDRC_INIT4_EMR2_DEFVAL 
+#undef DDRC_INIT4_EMR2_SHIFT 
+#undef DDRC_INIT4_EMR2_MASK 
+#define DDRC_INIT4_EMR2_DEFVAL                                                     0x00000000
+#define DDRC_INIT4_EMR2_SHIFT                                                      16
+#define DDRC_INIT4_EMR2_MASK                                                       0xFFFF0000U
+
+/*DDR2: Value to write to EMR3 register. DDR3/DDR4: Value to write to MR3 register mDDR/LPDDR2/LPDDR3: Unused LPDDR4: Value to 
+		rite to MR13 register*/
+#undef DDRC_INIT4_EMR3_DEFVAL 
+#undef DDRC_INIT4_EMR3_SHIFT 
+#undef DDRC_INIT4_EMR3_MASK 
+#define DDRC_INIT4_EMR3_DEFVAL                                                     0x00000000
+#define DDRC_INIT4_EMR3_SHIFT                                                      0
+#define DDRC_INIT4_EMR3_MASK                                                       0x0000FFFFU
+
+/*ZQ initial calibration, tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. Unit: 32 clock 
+		ycles. DDR3 typically requires 512 clocks. DDR4 requires 1024 clocks. LPDDR2/LPDDR3 requires 1 us.*/
+#undef DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL 
+#undef DDRC_INIT5_DEV_ZQINIT_X32_SHIFT 
+#undef DDRC_INIT5_DEV_ZQINIT_X32_MASK 
+#define DDRC_INIT5_DEV_ZQINIT_X32_DEFVAL                                           0x00100004
+#define DDRC_INIT5_DEV_ZQINIT_X32_SHIFT                                            16
+#define DDRC_INIT5_DEV_ZQINIT_X32_MASK                                             0x00FF0000U
+
+/*Maximum duration of the auto initialization, tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDD
+		3 typically requires 10 us.*/
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL 
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT 
+#undef DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK 
+#define DDRC_INIT5_MAX_AUTO_INIT_X1024_DEFVAL                                      0x00100004
+#define DDRC_INIT5_MAX_AUTO_INIT_X1024_SHIFT                                       0
+#define DDRC_INIT5_MAX_AUTO_INIT_X1024_MASK                                        0x000003FFU
+
+/*DDR4- Value to be loaded into SDRAM MR4 registers. Used in DDR4 designs only.*/
+#undef DDRC_INIT6_MR4_DEFVAL 
+#undef DDRC_INIT6_MR4_SHIFT 
+#undef DDRC_INIT6_MR4_MASK 
+#define DDRC_INIT6_MR4_DEFVAL                                                      0x00000000
+#define DDRC_INIT6_MR4_SHIFT                                                       16
+#define DDRC_INIT6_MR4_MASK                                                        0xFFFF0000U
+
+/*DDR4- Value to be loaded into SDRAM MR5 registers. Used in DDR4 designs only.*/
+#undef DDRC_INIT6_MR5_DEFVAL 
+#undef DDRC_INIT6_MR5_SHIFT 
+#undef DDRC_INIT6_MR5_MASK 
+#define DDRC_INIT6_MR5_DEFVAL                                                      0x00000000
+#define DDRC_INIT6_MR5_SHIFT                                                       0
+#define DDRC_INIT6_MR5_MASK                                                        0x0000FFFFU
+
+/*DDR4- Value to be loaded into SDRAM MR6 registers. Used in DDR4 designs only.*/
+#undef DDRC_INIT7_MR6_DEFVAL 
+#undef DDRC_INIT7_MR6_SHIFT 
+#undef DDRC_INIT7_MR6_MASK 
+#define DDRC_INIT7_MR6_DEFVAL                                                      
+#define DDRC_INIT7_MR6_SHIFT                                                       16
+#define DDRC_INIT7_MR6_MASK                                                        0xFFFF0000U
+
+/*Disabling Address Mirroring for BG bits. When this is set to 1, BG0 and BG1 are NOT swapped even if Address Mirroring is enab
+		ed. This will be required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped. - 0 - BG0 and BG1 are swapped i
+		 address mirroring is enabled.*/
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK 
+#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_DEFVAL                                  0x00000000
+#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_SHIFT                                   5
+#define DDRC_DIMMCTL_DIMM_DIS_BG_MIRRORING_MASK                                    0x00000020U
+
+/*Enable for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
+		 be programmed to 0 during MRS. In case where DRAMs which do not have BG1 are attached and both the CA parity and the Output 
+		nversion are enabled, this must be set to 0, so that the calculation of CA parity will not include BG1 bit. Note: This has no
+		effect on the address of any other memory accesses, or of software-driven mode register accesses. If address mirroring is ena
+		led, this is applied to BG1 of even ranks and BG0 of odd ranks. - 1 - Enabled - 0 - Disabled*/
+#undef DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL 
+#undef DDRC_DIMMCTL_MRS_BG1_EN_SHIFT 
+#undef DDRC_DIMMCTL_MRS_BG1_EN_MASK 
+#define DDRC_DIMMCTL_MRS_BG1_EN_DEFVAL                                             0x00000000
+#define DDRC_DIMMCTL_MRS_BG1_EN_SHIFT                                              4
+#define DDRC_DIMMCTL_MRS_BG1_EN_MASK                                               0x00000010U
+
+/*Enable for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and mus
+		 be programmed to 0 during MRS. In case where DRAMs which do not have A17 are attached and the Output Inversion are enabled, 
+		his must be set to 0, so that the calculation of CA parity will not include A17 bit. Note: This has no effect on the address 
+		f any other memory accesses, or of software-driven mode register accesses. - 1 - Enabled - 0 - Disabled*/
+#undef DDRC_DIMMCTL_MRS_A17_EN_DEFVAL 
+#undef DDRC_DIMMCTL_MRS_A17_EN_SHIFT 
+#undef DDRC_DIMMCTL_MRS_A17_EN_MASK 
+#define DDRC_DIMMCTL_MRS_A17_EN_DEFVAL                                             0x00000000
+#define DDRC_DIMMCTL_MRS_A17_EN_SHIFT                                              3
+#define DDRC_DIMMCTL_MRS_A17_EN_MASK                                               0x00000008U
+
+/*Output Inversion Enable (for DDR4 RDIMM implementations only). DDR4 RDIMM implements the Output Inversion feature by default,
+		which means that the following address, bank address and bank group bits of B-side DRAMs are inverted: A3-A9, A11, A13, A17, 
+		A0-BA1, BG0-BG1. Setting this bit ensures that, for mode register accesses generated by the uMCTL2 during the automatic initi
+		lization routine and enabling of a particular DDR4 feature, separate A-side and B-side mode register accesses are generated. 
+		or B-side mode register accesses, these bits are inverted within the uMCTL2 to compensate for this RDIMM inversion. Note: Thi
+		 has no effect on the address of any other memory accesses, or of software-driven mode register accesses. - 1 - Implement out
+		ut inversion for B-side DRAMs. - 0 - Do not implement output inversion for B-side DRAMs.*/
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK 
+#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_DEFVAL                                     0x00000000
+#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_SHIFT                                      2
+#define DDRC_DIMMCTL_DIMM_OUTPUT_INV_EN_MASK                                       0x00000004U
+
+/*Address Mirroring Enable (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM implementations). Some UDIMMs and DD
+		4 RDIMMs implement address mirroring for odd ranks, which means that the following address, bank address and bank group bits 
+		re swapped: (A3, A4), (A5, A6), (A7, A8), (BA0, BA1) and also (A11, A13), (BG0, BG1) for the DDR4. Setting this bit ensures t
+		at, for mode register accesses during the automatic initialization routine, these bits are swapped within the uMCTL2 to compe
+		sate for this UDIMM/RDIMM swapping. In addition to the automatic initialization routine, in case of DDR4 UDIMM/RDIMM, they ar
+		 swapped during the automatic MRS access to enable/disable of a particular DDR4 feature. Note: This has no effect on the addr
+		ss of any other memory accesses, or of software-driven mode register accesses. This is not supported for mDDR, LPDDR2, LPDDR3
+		or LPDDR4 SDRAMs. Note: In case of x16 DDR4 DIMMs, BG1 output of MRS for the odd ranks is same as BG0 because BG1 is invalid,
+		hence dimm_dis_bg_mirroring register must be set to 1. - 1 - For odd ranks, implement address mirroring for MRS commands to d
+		ring initialization and for any automatic DDR4 MRS commands (to be used if UDIMM/RDIMM implements address mirroring) - 0 - Do
+		not implement address mirroring*/
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK 
+#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_DEFVAL                                      0x00000000
+#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_SHIFT                                       1
+#define DDRC_DIMMCTL_DIMM_ADDR_MIRR_EN_MASK                                        0x00000002U
+
+/*Staggering enable for multi-rank accesses (for multi-rank UDIMM and RDIMM implementations only). This is not supported for mD
+		R, LPDDR2, LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software driven MR commands (via M
+		CTRL0/MRCTRL1), where software is responsible to send them to seperate ranks as appropriate. - 1 - (DDR4) Send MRS commands t
+		 each ranks seperately - 1 - (non-DDR4) Send all commands to even and odd ranks seperately - 0 - Do not stagger accesses*/
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL 
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT 
+#undef DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK 
+#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_DEFVAL                                     0x00000000
+#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_SHIFT                                      0
+#define DDRC_DIMMCTL_DIMM_STAGGER_CS_EN_MASK                                       0x00000001U
+
+/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
+		e writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should c
+		nsider both PHY requirement and ODT requirement. - PHY requirement: tphy_wrcsgap + 1 (see PHY databook for value of tphy_wrcs
+		ap) If CRC feature is enabled, should be increased by 1. If write preamble is set to 2tCK(DDR4/LPDDR4 only), should be increa
+		ed by 1. If write postamble is set to 1.5tCK(LPDDR4 only), should be increased by 1. - ODT requirement: The value programmed 
+		n this register takes care of the ODT switch off timing requirement when switching ranks during writes. For LPDDR4, the requi
+		ement is ODTLoff - ODTLon - BL/2 + 1 For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY requirement
+		or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and round it u
+		 to the next integer.*/
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL 
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT 
+#undef DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK 
+#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_DEFVAL                                       0x0000066F
+#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_SHIFT                                        8
+#define DDRC_RANKCTL_DIFF_RANK_WR_GAP_MASK                                         0x00000F00U
+
+/*Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecuti
+		e reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This value should co
+		sider both PHY requirement and ODT requirement. - PHY requirement: tphy_rdcsgap + 1 (see PHY databook for value of tphy_rdcsg
+		p) If read preamble is set to 2tCK(DDR4/LPDDR4 only), should be increased by 1. If read postamble is set to 1.5tCK(LPDDR4 onl
+		), should be increased by 1. - ODT requirement: The value programmed in this register takes care of the ODT switch off timing
+		requirement when switching ranks during reads. For configurations with MEMC_FREQ_RATIO=1, program this to the larger of PHY r
+		quirement or ODT requirement. For configurations with MEMC_FREQ_RATIO=2, program this to the larger value divided by two and 
+		ound it up to the next integer.*/
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL 
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT 
+#undef DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK 
+#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_DEFVAL                                       0x0000066F
+#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_SHIFT                                        4
+#define DDRC_RANKCTL_DIFF_RANK_RD_GAP_MASK                                         0x000000F0U
+
+/*Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to differ
+		nt ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data bus content
+		on as well as to give PHY enough time to switch the delay when changing ranks. The uMCTL2 arbitrates for bus access on a cycl
+		-by-cycle basis; therefore after a read is scheduled, there are few clock cycles (determined by the value on RANKCTL.diff_ran
+		_rd_gap register) in which only reads from the same rank are eligible to be scheduled. This prevents reads from other ranks f
+		om having fair access to the data bus. This parameter represents the maximum number of reads that can be scheduled consecutiv
+		ly to the same rank. After this number is reached, a delay equal to RANKCTL.diff_rank_rd_gap is inserted by the scheduler to 
+		llow all ranks a fair opportunity to be scheduled. Higher numbers increase bandwidth utilization, lower numbers increase fair
+		ess. This feature can be DISABLED by setting this register to 0. When set to 0, the Controller will stay on the same rank as 
+		ong as commands are available for it. Minimum programmable value is 0 (feature disabled) and maximum programmable value is 0x
+		. FOR PERFORMANCE ONLY.*/
+#undef DDRC_RANKCTL_MAX_RANK_RD_DEFVAL 
+#undef DDRC_RANKCTL_MAX_RANK_RD_SHIFT 
+#undef DDRC_RANKCTL_MAX_RANK_RD_MASK 
+#define DDRC_RANKCTL_MAX_RANK_RD_DEFVAL                                            0x0000066F
+#define DDRC_RANKCTL_MAX_RANK_RD_SHIFT                                             0
+#define DDRC_RANKCTL_MAX_RANK_RD_MASK                                              0x0000000FU
+
+/*Minimum time between write and precharge to same bank. Unit: Clocks Specifications: WL + BL/2 + tWR = approximately 8 cycles 
+		 15 ns = 14 clocks @400MHz and less for lower frequencies where: - WL = write latency - BL = burst length. This must match th
+		 value programmed in the BL bit of the mode register to the SDRAM. BST (burst terminate) is not supported at present. - tWR =
+		Write recovery time. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 for this 
+		arameter. For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For configurations
+		with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer value.*/
+#undef DDRC_DRAMTMG0_WR2PRE_DEFVAL 
+#undef DDRC_DRAMTMG0_WR2PRE_SHIFT 
+#undef DDRC_DRAMTMG0_WR2PRE_MASK 
+#define DDRC_DRAMTMG0_WR2PRE_DEFVAL                                                0x0F101B0F
+#define DDRC_DRAMTMG0_WR2PRE_SHIFT                                                 24
+#define DDRC_DRAMTMG0_WR2PRE_MASK                                                  0x7F000000U
+
+/*tFAW Valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design, at most 4 banks must be activated
+		in a rolling window of tFAW cycles. For configurations with MEMC_FREQ_RATIO=2, program this to (tFAW/2) and round up to next 
+		nteger value. In a 4-bank design, set this register to 0x1 independent of the MEMC_FREQ_RATIO configuration. Unit: Clocks*/
+#undef DDRC_DRAMTMG0_T_FAW_DEFVAL 
+#undef DDRC_DRAMTMG0_T_FAW_SHIFT 
+#undef DDRC_DRAMTMG0_T_FAW_MASK 
+#define DDRC_DRAMTMG0_T_FAW_DEFVAL                                                 0x0F101B0F
+#define DDRC_DRAMTMG0_T_FAW_SHIFT                                                  16
+#define DDRC_DRAMTMG0_T_FAW_MASK                                                   0x003F0000U
+
+/*tRAS(max): Maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Mi
+		imum value of this register is 1. Zero is invalid. For configurations with MEMC_FREQ_RATIO=2, program this to (tRAS(max)-1)/2
+		 No rounding up. Unit: Multiples of 1024 clocks.*/
+#undef DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL 
+#undef DDRC_DRAMTMG0_T_RAS_MAX_SHIFT 
+#undef DDRC_DRAMTMG0_T_RAS_MAX_MASK 
+#define DDRC_DRAMTMG0_T_RAS_MAX_DEFVAL                                             0x0F101B0F
+#define DDRC_DRAMTMG0_T_RAS_MAX_SHIFT                                              8
+#define DDRC_DRAMTMG0_T_RAS_MAX_MASK                                               0x00007F00U
+
+/*tRAS(min): Minimum time between activate and precharge to the same bank. For configurations with MEMC_FREQ_RATIO=2, 1T mode, 
+		rogram this to tRAS(min)/2. No rounding up. For configurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, program this t
+		 (tRAS(min)/2) and round it up to the next integer value. Unit: Clocks*/
+#undef DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL 
+#undef DDRC_DRAMTMG0_T_RAS_MIN_SHIFT 
+#undef DDRC_DRAMTMG0_T_RAS_MIN_MASK 
+#define DDRC_DRAMTMG0_T_RAS_MIN_DEFVAL                                             0x0F101B0F
+#define DDRC_DRAMTMG0_T_RAS_MIN_SHIFT                                              0
+#define DDRC_DRAMTMG0_T_RAS_MIN_MASK                                               0x0000003FU
+
+/*tXP: Minimum time after power-down exit to any operation. For DDR3, this should be programmed to tXPDLL if slow powerdown exi
+		 is selected in MR0[12]. If C/A parity for DDR4 is used, set to (tXP+PL) instead. For configurations with MEMC_FREQ_RATIO=2, 
+		rogram this to (tXP/2) and round it up to the next integer value. Units: Clocks*/
+#undef DDRC_DRAMTMG1_T_XP_DEFVAL 
+#undef DDRC_DRAMTMG1_T_XP_SHIFT 
+#undef DDRC_DRAMTMG1_T_XP_MASK 
+#define DDRC_DRAMTMG1_T_XP_DEFVAL                                                  0x00080414
+#define DDRC_DRAMTMG1_T_XP_SHIFT                                                   16
+#define DDRC_DRAMTMG1_T_XP_MASK                                                    0x001F0000U
+
+/*tRTP: Minimum time from read to precharge of same bank. - DDR2: tAL + BL/2 + max(tRTP, 2) - 2 - DDR3: tAL + max (tRTP, 4) - D
+		R4: Max of following two equations: tAL + max (tRTP, 4) or, RL + BL/2 - tRP. - mDDR: BL/2 - LPDDR2: Depends on if it's LPDDR2
+		S2 or LPDDR2-S4: LPDDR2-S2: BL/2 + tRTP - 1. LPDDR2-S4: BL/2 + max(tRTP,2) - 2. - LPDDR3: BL/2 + max(tRTP,4) - 4 - LPDDR4: BL
+		2 + max(tRTP,8) - 8 For configurations with MEMC_FREQ_RATIO=2, 1T mode, divide the above value by 2. No rounding up. For conf
+		gurations with MEMC_FREQ_RATIO=2, 2T mode or LPDDR4 mode, divide the above value by 2 and round it up to the next integer val
+		e. Unit: Clocks.*/
+#undef DDRC_DRAMTMG1_RD2PRE_DEFVAL 
+#undef DDRC_DRAMTMG1_RD2PRE_SHIFT 
+#undef DDRC_DRAMTMG1_RD2PRE_MASK 
+#define DDRC_DRAMTMG1_RD2PRE_DEFVAL                                                0x00080414
+#define DDRC_DRAMTMG1_RD2PRE_SHIFT                                                 8
+#define DDRC_DRAMTMG1_RD2PRE_MASK                                                  0x00001F00U
+
+/*tRC: Minimum time between activates to same bank. For configurations with MEMC_FREQ_RATIO=2, program this to (tRC/2) and roun
+		 up to next integer value. Unit: Clocks.*/
+#undef DDRC_DRAMTMG1_T_RC_DEFVAL 
+#undef DDRC_DRAMTMG1_T_RC_SHIFT 
+#undef DDRC_DRAMTMG1_T_RC_MASK 
+#define DDRC_DRAMTMG1_T_RC_DEFVAL                                                  0x00080414
+#define DDRC_DRAMTMG1_T_RC_SHIFT                                                   0
+#define DDRC_DRAMTMG1_T_RC_MASK                                                    0x0000007FU
+
+/*Set to WL Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR, it should normally be s
+		t to 1. Note that, depending on the PHY, if using RDIMM, it may be necessary to use a value of WL + 1 to compensate for the e
+		tra cycle of latency through the RDIMM For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above
+		equation by 2, and round it up to next integer. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAININ
+		 is set), as the DFI read and write latencies defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL 
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT 
+#undef DDRC_DRAMTMG2_WRITE_LATENCY_MASK 
+#define DDRC_DRAMTMG2_WRITE_LATENCY_DEFVAL                                         0x0305060D
+#define DDRC_DRAMTMG2_WRITE_LATENCY_SHIFT                                          24
+#define DDRC_DRAMTMG2_WRITE_LATENCY_MASK                                           0x3F000000U
+
+/*Set to RL Time from read command to read data on SDRAM interface. This must be set to RL. Note that, depending on the PHY, if
+		using RDIMM, it mat be necessary to use a value of RL + 1 to compensate for the extra cycle of latency through the RDIMM For 
+		onfigurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next inte
+		er. This register field is not required for DDR2 and DDR3 (except if MEMC_TRAINING is set), as the DFI read and write latenci
+		s defined in DFITMG0 and DFITMG1 are sufficient for those protocols Unit: clocks*/
+#undef DDRC_DRAMTMG2_READ_LATENCY_DEFVAL 
+#undef DDRC_DRAMTMG2_READ_LATENCY_SHIFT 
+#undef DDRC_DRAMTMG2_READ_LATENCY_MASK 
+#define DDRC_DRAMTMG2_READ_LATENCY_DEFVAL                                          0x0305060D
+#define DDRC_DRAMTMG2_READ_LATENCY_SHIFT                                           16
+#define DDRC_DRAMTMG2_READ_LATENCY_MASK                                            0x003F0000U
+
+/*DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL 
+		PDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled) : RL + B
+		/2 + RU(tDQSCKmax/tCK) + RD_POSTAMBLE - ODTLon - RU(tODTon(min)/tCK) Minimum time from read command to write command. Include
+		time for bus turnaround and all per-bank, per-rank, and global constraints. Unit: Clocks. Where: - WL = write latency - BL = 
+		urst length. This must match the value programmed in the BL bit of the mode register to the SDRAM - RL = read latency = CAS l
+		tency - WR_PREAMBLE = write preamble. This is unique to DDR4 and LPDDR4. - RD_POSTAMBLE = read postamble. This is unique to L
+		DDR4. For LPDDR2/LPDDR3/LPDDR4, if derating is enabled (DERATEEN.derate_enable=1), derated tDQSCKmax should be used. For conf
+		gurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/
+#undef DDRC_DRAMTMG2_RD2WR_DEFVAL 
+#undef DDRC_DRAMTMG2_RD2WR_SHIFT 
+#undef DDRC_DRAMTMG2_RD2WR_MASK 
+#define DDRC_DRAMTMG2_RD2WR_DEFVAL                                                 0x0305060D
+#define DDRC_DRAMTMG2_RD2WR_SHIFT                                                  8
+#define DDRC_DRAMTMG2_RD2WR_MASK                                                   0x00003F00U
+
+/*DDR4: CWL + PL + BL/2 + tWTR_L Others: CWL + BL/2 + tWTR In DDR4, minimum time from write command to read command for same ba
+		k group. In others, minimum time from write command to read command. Includes time for bus turnaround, recovery times, and al
+		 per-bank, per-rank, and global constraints. Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burs
+		 length. This must match the value programmed in the BL bit of the mode register to the SDRAM - tWTR_L = internal write to re
+		d command delay for same bank group. This comes directly from the SDRAM specification. - tWTR = internal write to read comman
+		 delay. This comes directly from the SDRAM specification. Add one extra cycle for LPDDR2/LPDDR3/LPDDR4 operation. For configu
+		ations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next integer.*/
+#undef DDRC_DRAMTMG2_WR2RD_DEFVAL 
+#undef DDRC_DRAMTMG2_WR2RD_SHIFT 
+#undef DDRC_DRAMTMG2_WR2RD_MASK 
+#define DDRC_DRAMTMG2_WR2RD_DEFVAL                                                 0x0305060D
+#define DDRC_DRAMTMG2_WR2RD_SHIFT                                                  0
+#define DDRC_DRAMTMG2_WR2RD_MASK                                                   0x0000003FU
+
+/*Time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2, LPDDR3 o
+		 LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to the larger of tMRW 
+		nd tMRWCKEL. For LPDDR2, this register is used for the time from a MRW/MRR to all other commands. For LDPDR3, this register i
+		 used for the time from a MRW/MRR to a MRW/MRR.*/
+#undef DDRC_DRAMTMG3_T_MRW_DEFVAL 
+#undef DDRC_DRAMTMG3_T_MRW_SHIFT 
+#undef DDRC_DRAMTMG3_T_MRW_MASK 
+#define DDRC_DRAMTMG3_T_MRW_DEFVAL                                                 0x0050400C
+#define DDRC_DRAMTMG3_T_MRW_SHIFT                                                  20
+#define DDRC_DRAMTMG3_T_MRW_MASK                                                   0x3FF00000U
+
+/*tMRD: Cycles to wait after a mode register write or read. Depending on the connected SDRAM, tMRD represents: DDR2/mDDR: Time 
+		rom MRS to any command DDR3/4: Time from MRS to MRS command LPDDR2: not used LPDDR3/4: Time from MRS to non-MRS command For c
+		nfigurations with MEMC_FREQ_RATIO=2, program this to (tMRD/2) and round it up to the next integer value. If C/A parity for DD
+		4 is used, set to tMRD_PAR(tMOD+PL) instead.*/
+#undef DDRC_DRAMTMG3_T_MRD_DEFVAL 
+#undef DDRC_DRAMTMG3_T_MRD_SHIFT 
+#undef DDRC_DRAMTMG3_T_MRD_MASK 
+#define DDRC_DRAMTMG3_T_MRD_DEFVAL                                                 0x0050400C
+#define DDRC_DRAMTMG3_T_MRD_SHIFT                                                  12
+#define DDRC_DRAMTMG3_T_MRD_MASK                                                   0x0003F000U
+
+/*tMOD: Parameter used only in DDR3 and DDR4. Cycles between load mode command and following non-load mode command. If C/A pari
+		y for DDR4 is used, set to tMOD_PAR(tMOD+PL) instead. Set to tMOD if MEMC_FREQ_RATIO=1, or tMOD/2 (rounded up to next integer
+		 if MEMC_FREQ_RATIO=2. Note that if using RDIMM, depending on the PHY, it may be necessary to use a value of tMOD + 1 or (tMO
+		 + 1)/2 to compensate for the extra cycle of latency applied to mode register writes by the RDIMM chip.*/
+#undef DDRC_DRAMTMG3_T_MOD_DEFVAL 
+#undef DDRC_DRAMTMG3_T_MOD_SHIFT 
+#undef DDRC_DRAMTMG3_T_MOD_MASK 
+#define DDRC_DRAMTMG3_T_MOD_DEFVAL                                                 0x0050400C
+#define DDRC_DRAMTMG3_T_MOD_SHIFT                                                  0
+#define DDRC_DRAMTMG3_T_MOD_MASK                                                   0x000003FFU
+
+/*tRCD - tAL: Minimum time from activate to read or write command to same bank. For configurations with MEMC_FREQ_RATIO=2, prog
+		am this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value allowed for this register is 1, which im
+		lies minimum (tRCD - tAL) value to be 2 in configurations with MEMC_FREQ_RATIO=2. Unit: Clocks.*/
+#undef DDRC_DRAMTMG4_T_RCD_DEFVAL 
+#undef DDRC_DRAMTMG4_T_RCD_SHIFT 
+#undef DDRC_DRAMTMG4_T_RCD_MASK 
+#define DDRC_DRAMTMG4_T_RCD_DEFVAL                                                 0x05040405
+#define DDRC_DRAMTMG4_T_RCD_SHIFT                                                  24
+#define DDRC_DRAMTMG4_T_RCD_MASK                                                   0x1F000000U
+
+/*DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum
+		time between two reads or two writes. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_L/2 or tCCD/2) and rou
+		d it up to the next integer value. Unit: clocks.*/
+#undef DDRC_DRAMTMG4_T_CCD_DEFVAL 
+#undef DDRC_DRAMTMG4_T_CCD_SHIFT 
+#undef DDRC_DRAMTMG4_T_CCD_MASK 
+#define DDRC_DRAMTMG4_T_CCD_DEFVAL                                                 0x05040405
+#define DDRC_DRAMTMG4_T_CCD_SHIFT                                                  16
+#define DDRC_DRAMTMG4_T_CCD_MASK                                                   0x000F0000U
+
+/*DDR4: tRRD_L: Minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time betwee
+		 activates from bank 'a' to bank 'b'For configurations with MEMC_FREQ_RATIO=2, program this to (tRRD_L/2 or tRRD/2) and round
+		it up to the next integer value. Unit: Clocks.*/
+#undef DDRC_DRAMTMG4_T_RRD_DEFVAL 
+#undef DDRC_DRAMTMG4_T_RRD_SHIFT 
+#undef DDRC_DRAMTMG4_T_RRD_MASK 
+#define DDRC_DRAMTMG4_T_RRD_DEFVAL                                                 0x05040405
+#define DDRC_DRAMTMG4_T_RRD_SHIFT                                                  8
+#define DDRC_DRAMTMG4_T_RRD_MASK                                                   0x00000F00U
+
+/*tRP: Minimum time from precharge to activate of same bank. For MEMC_FREQ_RATIO=1 configurations, t_rp should be set to RoundU
+		(tRP/tCK). For MEMC_FREQ_RATIO=2 configurations, t_rp should be set to RoundDown(RoundUp(tRP/tCK)/2) + 1. For MEMC_FREQ_RATIO
+		2 configurations in LPDDR4, t_rp should be set to RoundUp(RoundUp(tRP/tCK)/2). Unit: Clocks.*/
+#undef DDRC_DRAMTMG4_T_RP_DEFVAL 
+#undef DDRC_DRAMTMG4_T_RP_SHIFT 
+#undef DDRC_DRAMTMG4_T_RP_MASK 
+#define DDRC_DRAMTMG4_T_RP_DEFVAL                                                  0x05040405
+#define DDRC_DRAMTMG4_T_RP_SHIFT                                                   0
+#define DDRC_DRAMTMG4_T_RP_MASK                                                    0x0000001FU
+
+/*This is the time before Self Refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stab
+		e time before SRX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEH - DDR2: 1 - DDR3: tCKSRX - DDR4:
+		tCKSRX For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next in
+		eger.*/
+#undef DDRC_DRAMTMG5_T_CKSRX_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKSRX_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKSRX_MASK 
+#define DDRC_DRAMTMG5_T_CKSRX_DEFVAL                                               0x05050403
+#define DDRC_DRAMTMG5_T_CKSRX_SHIFT                                                24
+#define DDRC_DRAMTMG5_T_CKSRX_MASK                                                 0x0F000000U
+
+/*This is the time after Self Refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay afte
+		 SRE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL - DDR2: 1 - DDR3: max (10 ns, 5 tCK) - DDR4: 
+		ax (10 ns, 5 tCK) For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up
+		to next integer.*/
+#undef DDRC_DRAMTMG5_T_CKSRE_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKSRE_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKSRE_MASK 
+#define DDRC_DRAMTMG5_T_CKSRE_DEFVAL                                               0x05050403
+#define DDRC_DRAMTMG5_T_CKSRE_SHIFT                                                16
+#define DDRC_DRAMTMG5_T_CKSRE_MASK                                                 0x000F0000U
+
+/*Minimum CKE low width for Self refresh or Self refresh power down entry to exit timing in memory clock cycles. Recommended se
+		tings: - mDDR: tRFC - LPDDR2: tCKESR - LPDDR3: tCKESR - LPDDR4: max(tCKELPD, tSR) - DDR2: tCKE - DDR3: tCKE + 1 - DDR4: tCKE 
+		 1 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it up to next intege
+		.*/
+#undef DDRC_DRAMTMG5_T_CKESR_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKESR_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKESR_MASK 
+#define DDRC_DRAMTMG5_T_CKESR_DEFVAL                                               0x05050403
+#define DDRC_DRAMTMG5_T_CKESR_SHIFT                                                8
+#define DDRC_DRAMTMG5_T_CKESR_MASK                                                 0x00003F00U
+
+/*Minimum number of cycles of CKE HIGH/LOW during power-down and self refresh. - LPDDR2/LPDDR3 mode: Set this to the larger of 
+		CKE or tCKESR - LPDDR4 mode: Set this to the larger of tCKE, tCKELPD or tSR. - Non-LPDDR2/non-LPDDR3/non-LPDDR4 designs: Set 
+		his to tCKE value. For configurations with MEMC_FREQ_RATIO=2, program this to (value described above)/2 and round it up to th
+		 next integer value. Unit: Clocks.*/
+#undef DDRC_DRAMTMG5_T_CKE_DEFVAL 
+#undef DDRC_DRAMTMG5_T_CKE_SHIFT 
+#undef DDRC_DRAMTMG5_T_CKE_MASK 
+#define DDRC_DRAMTMG5_T_CKE_DEFVAL                                                 0x05050403
+#define DDRC_DRAMTMG5_T_CKE_SHIFT                                                  0
+#define DDRC_DRAMTMG5_T_CKE_MASK                                                   0x0000001FU
+
+/*This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after 
+		PDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, program this to recom
+		ended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3
+		devices.*/
+#undef DDRC_DRAMTMG6_T_CKDPDE_DEFVAL 
+#undef DDRC_DRAMTMG6_T_CKDPDE_SHIFT 
+#undef DDRC_DRAMTMG6_T_CKDPDE_MASK 
+#define DDRC_DRAMTMG6_T_CKDPDE_DEFVAL                                              0x02020005
+#define DDRC_DRAMTMG6_T_CKDPDE_SHIFT                                               24
+#define DDRC_DRAMTMG6_T_CKDPDE_MASK                                                0x0F000000U
+
+/*This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock 
+		table time before DPDX. Recommended settings: - mDDR: 1 - LPDDR2: 2 - LPDDR3: 2 For configurations with MEMC_FREQ_RATIO=2, pr
+		gram this to recommended value divided by two and round it up to next integer. This is only present for designs supporting mD
+		R or LPDDR2 devices.*/
+#undef DDRC_DRAMTMG6_T_CKDPDX_DEFVAL 
+#undef DDRC_DRAMTMG6_T_CKDPDX_SHIFT 
+#undef DDRC_DRAMTMG6_T_CKDPDX_MASK 
+#define DDRC_DRAMTMG6_T_CKDPDX_DEFVAL                                              0x02020005
+#define DDRC_DRAMTMG6_T_CKDPDX_SHIFT                                               16
+#define DDRC_DRAMTMG6_T_CKDPDX_MASK                                                0x000F0000U
+
+/*This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the 
+		lock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR: 1 - LPDDR2: tXP + 2 - LPDDR3: tXP +
+		2 - LPDDR4: tXP + 2 For configurations with MEMC_FREQ_RATIO=2, program this to recommended value divided by two and round it 
+		p to next integer. This is only present for designs supporting mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_DRAMTMG6_T_CKCSX_DEFVAL 
+#undef DDRC_DRAMTMG6_T_CKCSX_SHIFT 
+#undef DDRC_DRAMTMG6_T_CKCSX_MASK 
+#define DDRC_DRAMTMG6_T_CKCSX_DEFVAL                                               0x02020005
+#define DDRC_DRAMTMG6_T_CKCSX_SHIFT                                                0
+#define DDRC_DRAMTMG6_T_CKCSX_MASK                                                 0x0000000FU
+
+/*This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. 
+		ecommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: tCKCKEL For configurations with MEMC_FREQ_RATIO=2, program t
+		is to recommended value divided by two and round it up to next integer. This is only present for designs supporting mDDR or L
+		DDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_DRAMTMG7_T_CKPDE_DEFVAL 
+#undef DDRC_DRAMTMG7_T_CKPDE_SHIFT 
+#undef DDRC_DRAMTMG7_T_CKPDE_MASK 
+#define DDRC_DRAMTMG7_T_CKPDE_DEFVAL                                               0x00000202
+#define DDRC_DRAMTMG7_T_CKPDE_SHIFT                                                8
+#define DDRC_DRAMTMG7_T_CKPDE_MASK                                                 0x00000F00U
+
+/*This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable
+		time before PDX. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 - LPDDR4: 2 For configurations with MEMC_FREQ_RATIO=
+		, program this to recommended value divided by two and round it up to next integer. This is only present for designs supporti
+		g mDDR or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_DRAMTMG7_T_CKPDX_DEFVAL 
+#undef DDRC_DRAMTMG7_T_CKPDX_SHIFT 
+#undef DDRC_DRAMTMG7_T_CKPDX_MASK 
+#define DDRC_DRAMTMG7_T_CKPDX_DEFVAL                                               0x00000202
+#define DDRC_DRAMTMG7_T_CKPDX_SHIFT                                                0
+#define DDRC_DRAMTMG7_T_CKPDX_MASK                                                 0x0000000FU
+
+/*tXS_FAST: Exit Self Refresh to ZQCL, ZQCS and MRS (only CL, WR, RTP and Geardown mode). For configurations with MEMC_FREQ_RAT
+		O=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Thi
+		 is applicable to only ZQCL/ZQCS commands. Note: Ensure this is less than or equal to t_xs_x32.*/
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_FAST_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_FAST_X32_DEFVAL                                         0x03034405
+#define DDRC_DRAMTMG8_T_XS_FAST_X32_SHIFT                                          24
+#define DDRC_DRAMTMG8_T_XS_FAST_X32_MASK                                           0x7F000000U
+
+/*tXS_ABORT: Exit Self Refresh to commands not requiring a locked DLL in Self Refresh Abort. For configurations with MEMC_FREQ_
+		ATIO=2, program this to the above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: 
+		nsure this is less than or equal to t_xs_x32.*/
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_ABORT_X32_DEFVAL                                        0x03034405
+#define DDRC_DRAMTMG8_T_XS_ABORT_X32_SHIFT                                         16
+#define DDRC_DRAMTMG8_T_XS_ABORT_X32_MASK                                          0x007F0000U
+
+/*tXSDLL: Exit Self Refresh to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the 
+		bove value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and 
+		DR4 SDRAMs.*/
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_DLL_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_DLL_X32_DEFVAL                                          0x03034405
+#define DDRC_DRAMTMG8_T_XS_DLL_X32_SHIFT                                           8
+#define DDRC_DRAMTMG8_T_XS_DLL_X32_MASK                                            0x00007F00U
+
+/*tXS: Exit Self Refresh to commands not requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program this to the
+		above value divided by 2 and round up to next integer value. Unit: Multiples of 32 clocks. Note: Used only for DDR2, DDR3 and
+		DDR4 SDRAMs.*/
+#undef DDRC_DRAMTMG8_T_XS_X32_DEFVAL 
+#undef DDRC_DRAMTMG8_T_XS_X32_SHIFT 
+#undef DDRC_DRAMTMG8_T_XS_X32_MASK 
+#define DDRC_DRAMTMG8_T_XS_X32_DEFVAL                                              0x03034405
+#define DDRC_DRAMTMG8_T_XS_X32_SHIFT                                               0
+#define DDRC_DRAMTMG8_T_XS_X32_MASK                                                0x0000007FU
+
+/*DDR4 Write preamble mode - 0: 1tCK preamble - 1: 2tCK preamble Present only with MEMC_FREQ_RATIO=2*/
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL 
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT 
+#undef DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK 
+#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_DEFVAL                                      0x0004040D
+#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_SHIFT                                       30
+#define DDRC_DRAMTMG9_DDR4_WR_PREAMBLE_MASK                                        0x40000000U
+
+/*tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' 
+		o bank 'b'), the minimum time is this value + 1. For configurations with MEMC_FREQ_RATIO=2, program this to (tCCD_S/2) and ro
+		nd it up to the next integer value. Present only in designs configured to support DDR4. Unit: clocks.*/
+#undef DDRC_DRAMTMG9_T_CCD_S_DEFVAL 
+#undef DDRC_DRAMTMG9_T_CCD_S_SHIFT 
+#undef DDRC_DRAMTMG9_T_CCD_S_MASK 
+#define DDRC_DRAMTMG9_T_CCD_S_DEFVAL                                               0x0004040D
+#define DDRC_DRAMTMG9_T_CCD_S_SHIFT                                                16
+#define DDRC_DRAMTMG9_T_CCD_S_MASK                                                 0x00070000U
+
+/*tRRD_S: Minimum time between activates from bank 'a' to bank 'b' for different bank group. For configurations with MEMC_FREQ_
+		ATIO=2, program this to (tRRD_S/2) and round it up to the next integer value. Present only in designs configured to support D
+		R4. Unit: Clocks.*/
+#undef DDRC_DRAMTMG9_T_RRD_S_DEFVAL 
+#undef DDRC_DRAMTMG9_T_RRD_S_SHIFT 
+#undef DDRC_DRAMTMG9_T_RRD_S_MASK 
+#define DDRC_DRAMTMG9_T_RRD_S_DEFVAL                                               0x0004040D
+#define DDRC_DRAMTMG9_T_RRD_S_SHIFT                                                8
+#define DDRC_DRAMTMG9_T_RRD_S_MASK                                                 0x00000F00U
+
+/*CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turn
+		round, recovery times, and all per-bank, per-rank, and global constraints. Present only in designs configured to support DDR4
+		 Unit: Clocks. Where: - CWL = CAS write latency - PL = Parity latency - BL = burst length. This must match the value programm
+		d in the BL bit of the mode register to the SDRAM - tWTR_S = internal write to read command delay for different bank group. T
+		is comes directly from the SDRAM specification. For configurations with MEMC_FREQ_RATIO=2, divide the value calculated using 
+		he above equation by 2, and round it up to next integer.*/
+#undef DDRC_DRAMTMG9_WR2RD_S_DEFVAL 
+#undef DDRC_DRAMTMG9_WR2RD_S_SHIFT 
+#undef DDRC_DRAMTMG9_WR2RD_S_MASK 
+#define DDRC_DRAMTMG9_WR2RD_S_DEFVAL                                               0x0004040D
+#define DDRC_DRAMTMG9_WR2RD_S_SHIFT                                                0
+#define DDRC_DRAMTMG9_WR2RD_S_MASK                                                 0x0000003FU
+
+/*tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. For configurations with MEMC_FREQ_RATIO=2, program
+		this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit: Mult
+		ples of 32 clocks.*/
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL 
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT 
+#undef DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK 
+#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_DEFVAL                                    0x440C021C
+#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_SHIFT                                     24
+#define DDRC_DRAMTMG11_POST_MPSM_GAP_X32_MASK                                      0x7F000000U
+
+/*tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. For configurations with MEMC_FREQ_RATIO=2, program this t
+		 RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: clocks.*/
+#undef DDRC_DRAMTMG11_T_MPX_LH_DEFVAL 
+#undef DDRC_DRAMTMG11_T_MPX_LH_SHIFT 
+#undef DDRC_DRAMTMG11_T_MPX_LH_MASK 
+#define DDRC_DRAMTMG11_T_MPX_LH_DEFVAL                                             0x440C021C
+#define DDRC_DRAMTMG11_T_MPX_LH_SHIFT                                              16
+#define DDRC_DRAMTMG11_T_MPX_LH_MASK                                               0x001F0000U
+
+/*tMPX_S: Minimum time CS setup time to CKE. For configurations with MEMC_FREQ_RATIO=2, program this to (tMPX_S/2) and round it
+		up to the next integer value. Present only in designs configured to support DDR4. Unit: Clocks.*/
+#undef DDRC_DRAMTMG11_T_MPX_S_DEFVAL 
+#undef DDRC_DRAMTMG11_T_MPX_S_SHIFT 
+#undef DDRC_DRAMTMG11_T_MPX_S_MASK 
+#define DDRC_DRAMTMG11_T_MPX_S_DEFVAL                                              0x440C021C
+#define DDRC_DRAMTMG11_T_MPX_S_SHIFT                                               8
+#define DDRC_DRAMTMG11_T_MPX_S_MASK                                                0x00000300U
+
+/*tCKMPE: Minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. Unit: Clocks. F
+		r configurations with MEMC_FREQ_RATIO=2, divide the value calculated using the above equation by 2, and round it up to next i
+		teger.*/
+#undef DDRC_DRAMTMG11_T_CKMPE_DEFVAL 
+#undef DDRC_DRAMTMG11_T_CKMPE_SHIFT 
+#undef DDRC_DRAMTMG11_T_CKMPE_MASK 
+#define DDRC_DRAMTMG11_T_CKMPE_DEFVAL                                              0x440C021C
+#define DDRC_DRAMTMG11_T_CKMPE_SHIFT                                               0
+#define DDRC_DRAMTMG11_T_CKMPE_MASK                                                0x0000001FU
+
+/*tCMDCKE: Delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE For configurations with MEMC_
+		REQ_RATIO=2, program this to (max(tESCKE, tCMDCKE)/2) and round it up to next integer value.*/
+#undef DDRC_DRAMTMG12_T_CMDCKE_DEFVAL 
+#undef DDRC_DRAMTMG12_T_CMDCKE_SHIFT 
+#undef DDRC_DRAMTMG12_T_CMDCKE_MASK 
+#define DDRC_DRAMTMG12_T_CMDCKE_DEFVAL                                             0x00020610
+#define DDRC_DRAMTMG12_T_CMDCKE_SHIFT                                              16
+#define DDRC_DRAMTMG12_T_CMDCKE_MASK                                               0x00030000U
+
+/*tCKEHCMD: Valid command requirement after CKE input HIGH. For configurations with MEMC_FREQ_RATIO=2, program this to (tCKEHCM
+		/2) and round it up to next integer value.*/
+#undef DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL 
+#undef DDRC_DRAMTMG12_T_CKEHCMD_SHIFT 
+#undef DDRC_DRAMTMG12_T_CKEHCMD_MASK 
+#define DDRC_DRAMTMG12_T_CKEHCMD_DEFVAL                                            0x00020610
+#define DDRC_DRAMTMG12_T_CKEHCMD_SHIFT                                             8
+#define DDRC_DRAMTMG12_T_CKEHCMD_MASK                                              0x00000F00U
+
+/*tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. For configurations with MEMC_FREQ_RATIO=2, program th
+		s to (tMRD_PDA/2) and round it up to next integer value.*/
+#undef DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL 
+#undef DDRC_DRAMTMG12_T_MRD_PDA_SHIFT 
+#undef DDRC_DRAMTMG12_T_MRD_PDA_MASK 
+#define DDRC_DRAMTMG12_T_MRD_PDA_DEFVAL                                            0x00020610
+#define DDRC_DRAMTMG12_T_MRD_PDA_SHIFT                                             0
+#define DDRC_DRAMTMG12_T_MRD_PDA_MASK                                              0x0000001FU
+
+/*- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to is
+		ue ZQ calibration request from APB module. - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on ZQCTL1.t_zq_s
+		ort_interval_x1024. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL 
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT 
+#undef DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK 
+#define DDRC_ZQCTL0_DIS_AUTO_ZQ_DEFVAL                                             0x02000040
+#define DDRC_ZQCTL0_DIS_AUTO_ZQ_SHIFT                                              31
+#define DDRC_ZQCTL0_DIS_AUTO_ZQ_MASK                                               0x80000000U
+
+/*- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Powerdown exit. Only applicable when run in DDR3
+		or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at Self-Refresh/SR-Power
+		own exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode. This is only present for designs suppo
+		ting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL 
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT 
+#undef DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK 
+#define DDRC_ZQCTL0_DIS_SRX_ZQCL_DEFVAL                                            0x02000040
+#define DDRC_ZQCTL0_DIS_SRX_ZQCL_SHIFT                                             30
+#define DDRC_ZQCTL0_DIS_SRX_ZQCL_MASK                                              0x40000000U
+
+/*- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one r
+		nk at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different ranks do not ov
+		rlap. - 0 - ZQ resistor is not shared. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL 
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT 
+#undef DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK 
+#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_DEFVAL                                      0x02000040
+#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_SHIFT                                       29
+#define DDRC_ZQCTL0_ZQ_RESISTOR_SHARED_MASK                                        0x20000000U
+
+/*- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. - 0 - Enable 
+		ssuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode. This is only present for des
+		gns supporting DDR4 devices.*/
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL 
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT 
+#undef DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK 
+#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_DEFVAL                                          0x02000040
+#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_SHIFT                                           28
+#define DDRC_ZQCTL0_DIS_MPSMX_ZQCL_MASK                                            0x10000000U
+
+/*tZQoper for DDR3/DDR4, tZQCL for LPDDR2/LPDDR3, tZQCAL for LPDDR4: Number of cycles of NOP required after a ZQCL (ZQ calibrat
+		on long)/MPC(ZQ Start) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2: DDR3/DDR4: program this to tZQo
+		er/2 and round it up to the next integer value. LPDDR2/LPDDR3: program this to tZQCL/2 and round it up to the next integer va
+		ue. LPDDR4: program this to tZQCAL/2 and round it up to the next integer value. Unit: Clock cycles. This is only present for 
+		esigns supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL 
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT 
+#undef DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK 
+#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_DEFVAL                                           0x02000040
+#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_SHIFT                                            16
+#define DDRC_ZQCTL0_T_ZQ_LONG_NOP_MASK                                             0x07FF0000U
+
+/*tZQCS for DDR3/DD4/LPDDR2/LPDDR3, tZQLAT for LPDDR4: Number of cycles of NOP required after a ZQCS (ZQ calibration short)/MPC
+		ZQ Latch) command is issued to SDRAM. For configurations with MEMC_FREQ_RATIO=2, program this to tZQCS/2 and round it up to t
+		e next integer value. Unit: Clock cycles. This is only present for designs supporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devic
+		s.*/
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL 
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT 
+#undef DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK 
+#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_DEFVAL                                          0x02000040
+#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_SHIFT                                           0
+#define DDRC_ZQCTL0_T_ZQ_SHORT_NOP_MASK                                            0x000003FFU
+
+/*tZQReset: Number of cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. For configurati
+		ns with MEMC_FREQ_RATIO=2, program this to tZQReset/2 and round it up to the next integer value. Unit: Clock cycles. This is 
+		nly present for designs supporting LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL 
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT 
+#undef DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK 
+#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_DEFVAL                                          0x02000100
+#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_SHIFT                                           20
+#define DDRC_ZQCTL1_T_ZQ_RESET_NOP_MASK                                            0x3FF00000U
+
+/*Average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/
+		PDDR2/LPDDR3/LPDDR4 devices. Meaningless, if ZQCTL0.dis_auto_zq=1. Unit: 1024 clock cycles. This is only present for designs 
+		upporting DDR3/DDR4 or LPDDR2/LPDDR3/LPDDR4 devices.*/
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL 
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT 
+#undef DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK 
+#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_DEFVAL                               0x02000100
+#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_SHIFT                                0
+#define DDRC_ZQCTL1_T_ZQ_SHORT_INTERVAL_X1024_MASK                                 0x000FFFFFU
+
+/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
+		s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
+		, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
+		 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL 
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT 
+#undef DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK 
+#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_DEFVAL                                       0x07020002
+#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_SHIFT                                        24
+#define DDRC_DFITMG0_DFI_T_CTRL_DELAY_MASK                                         0x1F000000U
+
+/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
+		0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
+		fer to PHY specification for correct value.*/
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_DEFVAL                                     0x07020002
+#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_SHIFT                                      23
+#define DDRC_DFITMG0_DFI_RDDATA_USE_SDR_MASK                                       0x00800000U
+
+/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
+		ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
+		, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
+		 latency through the RDIMM. Unit: Clocks*/
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL 
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT 
+#undef DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK 
+#define DDRC_DFITMG0_DFI_T_RDDATA_EN_DEFVAL                                        0x07020002
+#define DDRC_DFITMG0_DFI_T_RDDATA_EN_SHIFT                                         16
+#define DDRC_DFITMG0_DFI_T_RDDATA_EN_MASK                                          0x003F0000U
+
+/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
+		.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
+		HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
+		e.*/
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_DEFVAL                                     0x07020002
+#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_SHIFT                                      15
+#define DDRC_DFITMG0_DFI_WRDATA_USE_SDR_MASK                                       0x00008000U
+
+/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
+		 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
+		te, max supported value is 8. Unit: Clocks*/
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL 
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT 
+#undef DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK 
+#define DDRC_DFITMG0_DFI_TPHY_WRDATA_DEFVAL                                        0x07020002
+#define DDRC_DFITMG0_DFI_TPHY_WRDATA_SHIFT                                         8
+#define DDRC_DFITMG0_DFI_TPHY_WRDATA_MASK                                          0x00003F00U
+
+/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
+		 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
+		 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
+		rough the RDIMM.*/
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL 
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT 
+#undef DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK 
+#define DDRC_DFITMG0_DFI_TPHY_WRLAT_DEFVAL                                         0x07020002
+#define DDRC_DFITMG0_DFI_TPHY_WRLAT_SHIFT                                          0
+#define DDRC_DFITMG0_DFI_TPHY_WRLAT_MASK                                           0x0000003FU
+
+/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated command is driven. 
+		his field is used for CAL mode, should be set to '0' or the value which matches the CAL mode register setting in the DRAM. If
+		the PHY can add the latency for CAL mode, this should be set to '0'. Valid Range: 0, 3, 4, 5, 6, and 8*/
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_CMD_LAT_MASK 
+#define DDRC_DFITMG1_DFI_T_CMD_LAT_DEFVAL                                          0x00000404
+#define DDRC_DFITMG1_DFI_T_CMD_LAT_SHIFT                                           28
+#define DDRC_DFITMG1_DFI_T_CMD_LAT_MASK                                            0xF0000000U
+
+/*Specifies the number of DFI PHY clocks between when the dfi_cs signal is asserted and when the associated dfi_parity_in signa
+		 is driven.*/
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK 
+#define DDRC_DFITMG1_DFI_T_PARIN_LAT_DEFVAL                                        0x00000404
+#define DDRC_DFITMG1_DFI_T_PARIN_LAT_SHIFT                                         24
+#define DDRC_DFITMG1_DFI_T_PARIN_LAT_MASK                                          0x03000000U
+
+/*Specifies the number of DFI clocks between when the dfi_wrdata_en signal is asserted and when the corresponding write data tr
+		nsfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. Refer to PHY specification fo
+		 correct value. For DFI 3.0 PHY, set to twrdata_delay, a new timing parameter introduced in DFI 3.0. For DFI 2.1 PHY, set to 
+		phy_wrdata + (delay of DFI write data to the DRAM). Value to be programmed is in terms of DFI clocks, not PHY clocks. In FREQ
+		RATIO=2, divide PHY's value by 2 and round up to next integer. If using DFITMG0.dfi_wrdata_use_sdr=1, add 1 to the value. Uni
+		: Clocks*/
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK 
+#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_DEFVAL                                     0x00000404
+#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_SHIFT                                      16
+#define DDRC_DFITMG1_DFI_T_WRDATA_DELAY_MASK                                       0x001F0000U
+
+/*Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to 
+		he DRAM memory devices, at the PHY-DRAM boundary, maintains a low value. If the DFI clock and the memory clock are not phase 
+		ligned, this timing parameter should be rounded up to the next integer value.*/
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK 
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_DEFVAL                                 0x00000404
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_SHIFT                                  8
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_DISABLE_MASK                                   0x00000F00U
+
+/*Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first 
+		alid rising edge of the clock to the DRAM memory devices, at the PHY-DRAM boundary. If the DFI clock and the memory clock are
+		not phase aligned, this timing parameter should be rounded up to the next integer value.*/
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT 
+#undef DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK 
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_DEFVAL                                  0x00000404
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_SHIFT                                   0
+#define DDRC_DFITMG1_DFI_T_DRAM_CLK_ENABLE_MASK                                    0x0000000FU
+
+/*Setting for DFI's tlp_resp time. Same value is used for both Power Down, Self Refresh, Deep Power Down and Maximum Power Savi
+		g modes. DFI 2.1 specification onwards, recommends using a fixed value of 7 always.*/
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_TLP_RESP_MASK 
+#define DDRC_DFILPCFG0_DFI_TLP_RESP_DEFVAL                                         0x07000000
+#define DDRC_DFILPCFG0_DFI_TLP_RESP_SHIFT                                          24
+#define DDRC_DFILPCFG0_DFI_TLP_RESP_MASK                                           0x0F000000U
+
+/*Value to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16
+		cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7
+		- 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 
+		31072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting mDDR or LPDDR2/LPDDR3 device
+		.*/
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_DEFVAL                                    0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_SHIFT                                     20
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_DPD_MASK                                      0x00F00000U
+
+/*Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only pres
+		nt for designs supporting mDDR or LPDDR2/LPDDR3 devices.*/
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_DEFVAL                                        0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_SHIFT                                         16
+#define DDRC_DFILPCFG0_DFI_LP_EN_DPD_MASK                                          0x00010000U
+
+/*Value to drive on dfi_lp_wakeup signal when Self Refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cy
+		les - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 
+		048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 131
+		72 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_DEFVAL                                     0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_SHIFT                                      12
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_SR_MASK                                       0x0000F000U
+
+/*Enables DFI Low Power interface handshaking during Self Refresh Entry/Exit. - 0 - Disabled - 1 - Enabled*/
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_EN_SR_DEFVAL                                         0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_EN_SR_SHIFT                                          8
+#define DDRC_DFILPCFG0_DFI_LP_EN_SR_MASK                                           0x00000100U
+
+/*Value to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycl
+		s - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles - 0x7 - 20
+		8 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0xD - 13107
+		 cycles - 0xE - 262144 cycles - 0xF - Unlimited*/
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_DEFVAL                                     0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_SHIFT                                      4
+#define DDRC_DFILPCFG0_DFI_LP_WAKEUP_PD_MASK                                       0x000000F0U
+
+/*Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled*/
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT 
+#undef DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK 
+#define DDRC_DFILPCFG0_DFI_LP_EN_PD_DEFVAL                                         0x07000000
+#define DDRC_DFILPCFG0_DFI_LP_EN_PD_SHIFT                                          0
+#define DDRC_DFILPCFG0_DFI_LP_EN_PD_MASK                                           0x00000001U
+
+/*Value to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0
+		- 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles - 0x5 - 512 cycles - 0x6 - 1024 cycles 
+		 0x7 - 2048 cycles - 0x8 - 4096 cycles - 0x9 - 8192 cycles - 0xA - 16384 cycles - 0xB - 32768 cycles - 0xC - 65536 cycles - 0
+		D - 131072 cycles - 0xE - 262144 cycles - 0xF - Unlimited This is only present for designs supporting DDR4 devices.*/
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL 
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT 
+#undef DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK 
+#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_DEFVAL                                   0x00000000
+#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_SHIFT                                    4
+#define DDRC_DFILPCFG1_DFI_LP_WAKEUP_MPSM_MASK                                     0x000000F0U
+
+/*Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is
+		only present for designs supporting DDR4 devices.*/
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL 
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT 
+#undef DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK 
+#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_DEFVAL                                       0x00000000
+#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_SHIFT                                        0
+#define DDRC_DFILPCFG1_DFI_LP_EN_MPSM_MASK                                         0x00000001U
+
+/*This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idl
+		). Set this number higher to reduce the frequency of update requests, which can have a small impact on the latency of the fir
+		t read request when the uMCTL2 is idle. Unit: 1024 clocks*/
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK 
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_DEFVAL                       0x00000000
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_SHIFT                        16
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MIN_X1024_MASK                         0x00FF0000U
+
+/*This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; 
+		hen the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx is received. PHY can use this
+		idle time to recalibrate the delay lines to the DLLs. The DFI controller update is also used to reset PHY FIFO pointers in ca
+		e of data capture errors. Updates are required to maintain calibration over PVT, but frequent updates may impact performance.
+		Note: Value programmed for DFIUPD1.dfi_t_ctrlupd_interval_max_x1024 must be greater than DFIUPD1.dfi_t_ctrlupd_interval_min_x
+		024. Unit: 1024 clocks*/
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT 
+#undef DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK 
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_DEFVAL                       0x00000000
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_SHIFT                        0
+#define DDRC_DFIUPD1_DFI_T_CTRLUPD_INTERVAL_MAX_X1024_MASK                         0x000000FFU
+
+/*Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0: Signals are active low - 1: Signals are active high*/
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL 
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT 
+#undef DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK 
+#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_DEFVAL                                   0x00000001
+#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_SHIFT                                    2
+#define DDRC_DFIMISC_DFI_DATA_CS_POLARITY_MASK                                     0x00000004U
+
+/*DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality. - 1 - PHY implements DBI functionality. Present only
+		in designs configured to support DDR4 and LPDDR4.*/
+#undef DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL 
+#undef DDRC_DFIMISC_PHY_DBI_MODE_SHIFT 
+#undef DDRC_DFIMISC_PHY_DBI_MODE_MASK 
+#define DDRC_DFIMISC_PHY_DBI_MODE_DEFVAL                                           0x00000001
+#define DDRC_DFIMISC_PHY_DBI_MODE_SHIFT                                            1
+#define DDRC_DFIMISC_PHY_DBI_MODE_MASK                                             0x00000002U
+
+/*PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisa
+		ion*/
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL 
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT 
+#undef DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK 
+#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_DEFVAL                                   0x00000001
+#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_SHIFT                                    0
+#define DDRC_DFIMISC_DFI_INIT_COMPLETE_EN_MASK                                     0x00000001U
+
+/*>Number of clocks between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs sign
+		l is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to PHY specification for correct value.*/
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL 
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT 
+#undef DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK 
+#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_DEFVAL                                       0x00000202
+#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_SHIFT                                        8
+#define DDRC_DFITMG2_DFI_TPHY_RDCSLAT_MASK                                         0x00003F00U
+
+/*Number of clocks between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs sign
+		l is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. Refer to PHY specification for correct value.*/
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL 
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT 
+#undef DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK 
+#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_DEFVAL                                       0x00000202
+#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_SHIFT                                        0
+#define DDRC_DFITMG2_DFI_TPHY_WRCSLAT_MASK                                         0x0000003FU
+
+/*Read DBI enable signal in DDRC. - 0 - Read DBI is disabled. - 1 - Read DBI is enabled. This signal must be set the same value
+		as DRAM's mode register. - DDR4: MR5 bit A12. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[6]*/
+#undef DDRC_DBICTL_RD_DBI_EN_DEFVAL 
+#undef DDRC_DBICTL_RD_DBI_EN_SHIFT 
+#undef DDRC_DBICTL_RD_DBI_EN_MASK 
+#define DDRC_DBICTL_RD_DBI_EN_DEFVAL                                               0x00000001
+#define DDRC_DBICTL_RD_DBI_EN_SHIFT                                                2
+#define DDRC_DBICTL_RD_DBI_EN_MASK                                                 0x00000004U
+
+/*Write DBI enable signal in DDRC. - 0 - Write DBI is disabled. - 1 - Write DBI is enabled. This signal must be set the same va
+		ue as DRAM's mode register. - DDR4: MR5 bit A11. When x4 devices are used, this signal must be set to 0. - LPDDR4: MR3[7]*/
+#undef DDRC_DBICTL_WR_DBI_EN_DEFVAL 
+#undef DDRC_DBICTL_WR_DBI_EN_SHIFT 
+#undef DDRC_DBICTL_WR_DBI_EN_MASK 
+#define DDRC_DBICTL_WR_DBI_EN_DEFVAL                                               0x00000001
+#define DDRC_DBICTL_WR_DBI_EN_SHIFT                                                1
+#define DDRC_DBICTL_WR_DBI_EN_MASK                                                 0x00000002U
+
+/*DM enable signal in DDRC. - 0 - DM is disabled. - 1 - DM is enabled. This signal must be set the same logical value as DRAM's
+		mode register. - DDR4: Set this to same value as MR5 bit A10. When x4 devices are used, this signal must be set to 0. - LPDDR
+		: Set this to inverted value of MR13[5] which is opposite polarity from this signal*/
+#undef DDRC_DBICTL_DM_EN_DEFVAL 
+#undef DDRC_DBICTL_DM_EN_SHIFT 
+#undef DDRC_DBICTL_DM_EN_MASK 
+#define DDRC_DBICTL_DM_EN_DEFVAL                                                   0x00000001
+#define DDRC_DBICTL_DM_EN_SHIFT                                                    0
+#define DDRC_DBICTL_DM_EN_MASK                                                     0x00000001U
+
+/*Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 27, and 31 Internal Base: 6 The selected HIF addres
+		 bit is determined by adding the internal base to the value of this field. If set to 31, rank address bit 0 is set to 0.*/
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL 
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT 
+#undef DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK 
+#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_DEFVAL                                       
+#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_SHIFT                                        0
+#define DDRC_ADDRMAP0_ADDRMAP_CS_BIT0_MASK                                         0x0000001FU
+
+/*Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 29 and 31 Internal Base: 4 The selected HIF address
+		bit is determined by adding the internal base to the value of this field. If set to 31, bank address bit 2 is set to 0.*/
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK 
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_SHIFT                                        16
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B2_MASK                                         0x001F0000U
+
+/*Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 30 Internal Base: 3 The selected HIF address bit f
+		r each of the bank address bits is determined by adding the internal base to the value of this field.*/
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK 
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_SHIFT                                        8
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B1_MASK                                         0x00001F00U
+
+/*Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address bit f
+		r each of the bank address bits is determined by adding the internal base to the value of this field.*/
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT 
+#undef DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK 
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_SHIFT                                        0
+#define DDRC_ADDRMAP1_ADDRMAP_BANK_B0_MASK                                         0x0000001FU
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 5. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 6. - Quarter bus width mode: Selects the HIF address bit used as column address bit 7 . Vali
+		 Range: 0 to 7, and 15 Internal Base: 5 The selected HIF address bit is determined by adding the internal base to the value o
+		 this field. If set to 15, this column address bit is set to 0.*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_SHIFT                                         24
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B5_MASK                                          0x0F000000U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 4. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 5. - Quarter bus width mode: Selects the HIF address bit used as column address bit 6. Valid
+		Range: 0 to 7, and 15 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_SHIFT                                         16
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B4_MASK                                          0x000F0000U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 3. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 4. - Quarter bus width mode: Selects the HIF address bit used as column address bit 5. Valid
+		Range: 0 to 7 Internal Base: 3 The selected HIF address bit is determined by adding the internal base to the value of this fi
+		ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=16, it is required to program this to 0, hence register does not exist i
+		 this case.*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_SHIFT                                         8
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B3_MASK                                          0x00000F00U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 2. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 3. - Quarter bus width mode: Selects the HIF address bit used as column address bit 4. Valid
+		Range: 0 to 7 Internal Base: 2 The selected HIF address bit is determined by adding the internal base to the value of this fi
+		ld. Note, if UMCTL2_INCL_ARB=1 and MEMC_BURST_LENGTH=8 or 16, it is required to program this to 0.*/
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT 
+#undef DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK 
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_SHIFT                                         0
+#define DDRC_ADDRMAP2_ADDRMAP_COL_B2_MASK                                          0x0000000FU
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 9. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: Selects the HIF address bit used as
+		column address bit 13 (11 in LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 9 The selected HIF address bit i
+		 determined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: 
+		er JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source addr
+		ss bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus an
+		 hence column bit 10 is used.*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_SHIFT                                         24
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B9_MASK                                          0x0F000000U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 8. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 9. - Quarter bus width mode: Selects the HIF address bit used as column address bit 11 (10 i
+		 LPDDR2/LPDDR3 mode). Valid Range: 0 to 7, and 15 Internal Base: 8 The selected HIF address bit is determined by adding the i
+		ternal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specif
+		cation, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to col
+		mn address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is use
+		.*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_SHIFT                                         16
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B8_MASK                                          0x000F0000U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 7. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 8. - Quarter bus width mode: Selects the HIF address bit used as column address bit 9. Valid
+		Range: 0 to 7, and 15 Internal Base: 7 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_SHIFT                                         8
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B7_MASK                                          0x00000F00U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 6. - Half bus width mode: Selects the HIF addre
+		s bit used as column address bit 7. - Quarter bus width mode: Selects the HIF address bit used as column address bit 8. Valid
+		Range: 0 to 7, and 15 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of
+		this field. If set to 15, this column address bit is set to 0.*/
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT 
+#undef DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK 
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_SHIFT                                         0
+#define DDRC_ADDRMAP3_ADDRMAP_COL_B6_MASK                                          0x0000000FU
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Half bus width
+		mode: Unused. To make it unused, this should be tied to 4'hF. - Quarter bus width mode: Unused. To make it unused, this must 
+		e tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 11 The selected HIF address bit is determined by adding the intern
+		l base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per JEDEC DDR2/3/mDDR specificati
+		n, column address bit 10 is reserved for indicating auto-precharge, and hence no source address bit can be mapped to column a
+		dress bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and hence column bit 10 is used.*/
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK 
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_SHIFT                                        8
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B11_MASK                                         0x00000F00U
+
+/*- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode). - Half bus width
+		mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode). - Quarter bus width mode: UNUSED.
+		To make it unused, this must be tied to 4'hF. Valid Range: 0 to 7, and 15 Internal Base: 10 The selected HIF address bit is d
+		termined by adding the internal base to the value of this field. If set to 15, this column address bit is set to 0. Note: Per
+		JEDEC DDR2/3/mDDR specification, column address bit 10 is reserved for indicating auto-precharge, and hence no source address
+		bit can be mapped to column address bit 10. In LPDDR2/LPDDR3, there is a dedicated bit for auto-precharge in the CA bus and h
+		nce column bit 10 is used.*/
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT 
+#undef DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK 
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_SHIFT                                        0
+#define DDRC_ADDRMAP4_ADDRMAP_COL_B10_MASK                                         0x0000000FU
+
+/*Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11, and 15 Internal Base: 17 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 11 is set to 0.*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_SHIFT                                        24
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B11_MASK                                         0x0F000000U
+
+/*Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11, and 15 Internal Base: 8 (for row address
+		bit 2), 9 (for row address bit 3), 10 (for row address bit 4) etc increasing to 16 (for row address bit 10) The selected HIF 
+		ddress bit for each of the row address bits is determined by adding the internal base to the value of this field. When value 
+		5 is used the values of row address bits 2 to 10 are defined by registers ADDRMAP9, ADDRMAP10, ADDRMAP11.*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_DEFVAL                                     0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_SHIFT                                      16
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B2_10_MASK                                       0x000F0000U
+
+/*Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field.*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_SHIFT                                         8
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B1_MASK                                          0x00000F00U
+
+/*Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field.*/
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT 
+#undef DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK 
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_SHIFT                                         0
+#define DDRC_ADDRMAP5_ADDRMAP_ROW_B0_MASK                                          0x0000000FU
+
+/*Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address
+		having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are valid Present on
+		y in designs configured to support LPDDR3.*/
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL 
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT 
+#undef DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK 
+#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_SHIFT                                        31
+#define DDRC_ADDRMAP6_LPDDR3_6GB_12GB_MASK                                         0x80000000U
+
+/*Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11, and 15 Internal Base: 21 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 15 is set to 0.*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_SHIFT                                        24
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B15_MASK                                         0x0F000000U
+
+/*Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11, and 15 Internal Base: 20 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 14 is set to 0.*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_SHIFT                                        16
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B14_MASK                                         0x000F0000U
+
+/*Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11, and 15 Internal Base: 19 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 13 is set to 0.*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_SHIFT                                        8
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B13_MASK                                         0x00000F00U
+
+/*Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11, and 15 Internal Base: 18 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 12 is set to 0.*/
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT 
+#undef DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK 
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_SHIFT                                        0
+#define DDRC_ADDRMAP6_ADDRMAP_ROW_B12_MASK                                         0x0000000FU
+
+/*Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 10, and 15 Internal Base: 23 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 17 is set to 0.*/
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK 
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_SHIFT                                        8
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B17_MASK                                         0x00000F00U
+
+/*Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11, and 15 Internal Base: 22 The selected HIF addre
+		s bit is determined by adding the internal base to the value of this field. If set to 15, row address bit 16 is set to 0.*/
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT 
+#undef DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK 
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_SHIFT                                        0
+#define DDRC_ADDRMAP7_ADDRMAP_ROW_B16_MASK                                         0x0000000FU
+
+/*Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 30, and 31 Internal Base: 3 The selected HIF
+		address bit for each of the bank group address bits is determined by adding the internal base to the value of this field. If 
+		et to 31, bank group address bit 1 is set to 0.*/
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK 
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_DEFVAL                                         0x00000000
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_SHIFT                                          8
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B1_MASK                                           0x00001F00U
+
+/*Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 30 Internal Base: 2 The selected HIF address
+		bit for each of the bank group address bits is determined by adding the internal base to the value of this field.*/
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT 
+#undef DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK 
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_DEFVAL                                         0x00000000
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_SHIFT                                          0
+#define DDRC_ADDRMAP8_ADDRMAP_BG_B0_MASK                                           0x0000001FU
+
+/*Selects the HIF address bits used as row address bit 5. Valid Range: 0 to 11 Internal Base: 11 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_SHIFT                                         24
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B5_MASK                                          0x0F000000U
+
+/*Selects the HIF address bits used as row address bit 4. Valid Range: 0 to 11 Internal Base: 10 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_SHIFT                                         16
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B4_MASK                                          0x000F0000U
+
+/*Selects the HIF address bits used as row address bit 3. Valid Range: 0 to 11 Internal Base: 9 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
+		d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_SHIFT                                         8
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B3_MASK                                          0x00000F00U
+
+/*Selects the HIF address bits used as row address bit 2. Valid Range: 0 to 11 Internal Base: 8 The selected HIF address bit fo
+		 each of the row address bits is determined by adding the internal base to the value of this field. This register field is us
+		d only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT 
+#undef DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK 
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_DEFVAL                                        0x00000000
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_SHIFT                                         0
+#define DDRC_ADDRMAP9_ADDRMAP_ROW_B2_MASK                                          0x0000000FU
+
+/*Selects the HIF address bits used as row address bit 9. Valid Range: 0 to 11 Internal Base: 15 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_SHIFT                                        24
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B9_MASK                                         0x0F000000U
+
+/*Selects the HIF address bits used as row address bit 8. Valid Range: 0 to 11 Internal Base: 14 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_SHIFT                                        16
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B8_MASK                                         0x000F0000U
+
+/*Selects the HIF address bits used as row address bit 7. Valid Range: 0 to 11 Internal Base: 13 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_SHIFT                                        8
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B7_MASK                                         0x00000F00U
+
+/*Selects the HIF address bits used as row address bit 6. Valid Range: 0 to 11 Internal Base: 12 The selected HIF address bit f
+		r each of the row address bits is determined by adding the internal base to the value of this field. This register field is u
+		ed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT 
+#undef DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK 
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_DEFVAL                                       0x00000000
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_SHIFT                                        0
+#define DDRC_ADDRMAP10_ADDRMAP_ROW_B6_MASK                                         0x0000000FU
+
+/*Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit 
+		or each of the row address bits is determined by adding the internal base to the value of this field. This register field is 
+		sed only when ADDRMAP5.addrmap_row_b2_10 is set to value 15.*/
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL 
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT 
+#undef DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK 
+#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_DEFVAL                                      
+#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_SHIFT                                       0
+#define DDRC_ADDRMAP11_ADDRMAP_ROW_B10_MASK                                        0x0000000FU
+
+/*Cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x5 (DDR2-400/533/
+		67), 0x6 (DDR2-800), 0x7 (DDR2-1066) - BL4: 0x3 (DDR2-400/533/667), 0x4 (DDR2-800), 0x5 (DDR2-1066) DDR3: - BL8: 0x6 DDR4: - 
+		L8: 5 + WR_PREAMBLE + CRC_MODE WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) CRC_MODE = 0 (not CRC mode), 1 
+		CRC mode) LPDDR3: - BL8: 7 + RU(tODTon(max)/tCK)*/
+#undef DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL 
+#undef DDRC_ODTCFG_WR_ODT_HOLD_SHIFT 
+#undef DDRC_ODTCFG_WR_ODT_HOLD_MASK 
+#define DDRC_ODTCFG_WR_ODT_HOLD_DEFVAL                                             0x04000400
+#define DDRC_ODTCFG_WR_ODT_HOLD_SHIFT                                              24
+#define DDRC_ODTCFG_WR_ODT_HOLD_MASK                                               0x0F000000U
+
+/*The delay, in clock cycles, from issuing a write command to setting ODT values associated with that command. ODT setting must
+		remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CWL + AL - 3 (DDR2-400/533/
+		67), CWL + AL - 4 (DDR2-800), CWL + AL - 5 (DDR2-1066) If (CWL + AL - 3 < 0), uMCTL2 does not support ODT for write operation
+		 DDR3: - 0x0 DDR4: - DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) LPDDR3: - WL - 1 - RU(tODTon(max)/tCK))*/
+#undef DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL 
+#undef DDRC_ODTCFG_WR_ODT_DELAY_SHIFT 
+#undef DDRC_ODTCFG_WR_ODT_DELAY_MASK 
+#define DDRC_ODTCFG_WR_ODT_DELAY_DEFVAL                                            0x04000400
+#define DDRC_ODTCFG_WR_ODT_DELAY_SHIFT                                             16
+#define DDRC_ODTCFG_WR_ODT_DELAY_MASK                                              0x001F0000U
+
+/*Cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8: 0x6 (not DDR2-1066)
+		 0x7 (DDR2-1066) - BL4: 0x4 (not DDR2-1066), 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8: 5 + RD_PREAMBLE RD_PREAMBLE = 1 (
+		tCK write preamble), 2 (2tCK write preamble) LPDDR3: - BL8: 5 + RU(tDQSCK(max)/tCK) - RD(tDQSCK(min)/tCK) + RU(tODTon(max)/tC
+		)*/
+#undef DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL 
+#undef DDRC_ODTCFG_RD_ODT_HOLD_SHIFT 
+#undef DDRC_ODTCFG_RD_ODT_HOLD_MASK 
+#define DDRC_ODTCFG_RD_ODT_HOLD_DEFVAL                                             0x04000400
+#define DDRC_ODTCFG_RD_ODT_HOLD_SHIFT                                              8
+#define DDRC_ODTCFG_RD_ODT_HOLD_MASK                                               0x00000F00U
+
+/*The delay, in clock cycles, from issuing a read command to setting ODT values associated with that command. ODT setting must 
+		emain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: - CL + AL - 4 (not DDR2-1066),
+		CL + AL - 5 (DDR2-1066) If (CL + AL - 4 < 0), uMCTL2 does not support ODT for read operation. DDR3: - CL - CWL DDR4: - CL - C
+		L - RD_PREAMBLE + WR_PREAMBLE + DFITMG1.dfi_t_cmd_lat (to adjust for CAL mode) WR_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK
+		write preamble) RD_PREAMBLE = 1 (1tCK write preamble), 2 (2tCK write preamble) If (CL - CWL - RD_PREAMBLE + WR_PREAMBLE) < 0,
+		uMCTL2 does not support ODT for read operation. LPDDR3: - RL + RD(tDQSCK(min)/tCK) - 1 - RU(tODTon(max)/tCK)*/
+#undef DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL 
+#undef DDRC_ODTCFG_RD_ODT_DELAY_SHIFT 
+#undef DDRC_ODTCFG_RD_ODT_DELAY_MASK 
+#define DDRC_ODTCFG_RD_ODT_DELAY_DEFVAL                                            0x04000400
+#define DDRC_ODTCFG_RD_ODT_DELAY_SHIFT                                             2
+#define DDRC_ODTCFG_RD_ODT_DELAY_MASK                                              0x0000007CU
+
+/*Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can 
+		e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
+		 etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/
+#undef DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK1_RD_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK1_RD_ODT_MASK 
+#define DDRC_ODTMAP_RANK1_RD_ODT_DEFVAL                                            0x00002211
+#define DDRC_ODTMAP_RANK1_RD_ODT_SHIFT                                             12
+#define DDRC_ODTMAP_RANK1_RD_ODT_MASK                                              0x00003000U
+
+/*Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can b
+		 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
+		etc. For each rank, set its bit to 1 to enable its ODT. Present only in configurations that have 2 or more ranks*/
+#undef DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK1_WR_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK1_WR_ODT_MASK 
+#define DDRC_ODTMAP_RANK1_WR_ODT_DEFVAL                                            0x00002211
+#define DDRC_ODTMAP_RANK1_WR_ODT_SHIFT                                             8
+#define DDRC_ODTMAP_RANK1_WR_ODT_MASK                                              0x00000300U
+
+/*Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can 
+		e turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB
+		 etc. For each rank, set its bit to 1 to enable its ODT.*/
+#undef DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK0_RD_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK0_RD_ODT_MASK 
+#define DDRC_ODTMAP_RANK0_RD_ODT_DEFVAL                                            0x00002211
+#define DDRC_ODTMAP_RANK0_RD_ODT_SHIFT                                             4
+#define DDRC_ODTMAP_RANK0_RD_ODT_MASK                                              0x00000030U
+
+/*Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can b
+		 turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next to the LSB,
+		etc. For each rank, set its bit to 1 to enable its ODT.*/
+#undef DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL 
+#undef DDRC_ODTMAP_RANK0_WR_ODT_SHIFT 
+#undef DDRC_ODTMAP_RANK0_WR_ODT_MASK 
+#define DDRC_ODTMAP_RANK0_WR_ODT_DEFVAL                                            0x00002211
+#define DDRC_ODTMAP_RANK0_WR_ODT_SHIFT                                             0
+#define DDRC_ODTMAP_RANK0_WR_ODT_MASK                                              0x00000003U
+
+/*When the preferred transaction store is empty for these many clock cycles, switch to the alternate transaction store if it is
+		non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and the write t
+		ansaction store is the alternative store. When prefer write over read is set this is reversed. 0x0 is a legal value for this 
+		egister. When set to 0x0, the transaction store switching will happen immediately when the switching conditions become true. 
+		OR PERFORMANCE ONLY*/
+#undef DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL 
+#undef DDRC_SCHED_RDWR_IDLE_GAP_SHIFT 
+#undef DDRC_SCHED_RDWR_IDLE_GAP_MASK 
+#define DDRC_SCHED_RDWR_IDLE_GAP_DEFVAL                                            0x00002005
+#define DDRC_SCHED_RDWR_IDLE_GAP_SHIFT                                             24
+#define DDRC_SCHED_RDWR_IDLE_GAP_MASK                                              0x7F000000U
+
+/*UNUSED*/
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL 
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT 
+#undef DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK 
+#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_DEFVAL                                   0x00002005
+#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_SHIFT                                    16
+#define DDRC_SCHED_GO2CRITICAL_HYSTERESIS_MASK                                     0x00FF0000U
+
+/*Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) i
+		 the number of entries available for the high priority transaction store. Setting this to maximum value allocates all entries
+		to low priority transaction store. Setting this to 0 allocates 1 entry to low priority transaction store and the rest to high
+		priority transaction store. Note: In ECC configurations, the numbers of write and low priority read credits issued is one les
+		 than in the non-ECC case. One entry each is reserved in the write and low-priority read CAMs for storing the RMW requests ar
+		sing out of single bit error correction RMW operation.*/
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL 
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT 
+#undef DDRC_SCHED_LPR_NUM_ENTRIES_MASK 
+#define DDRC_SCHED_LPR_NUM_ENTRIES_DEFVAL                                          0x00002005
+#define DDRC_SCHED_LPR_NUM_ENTRIES_SHIFT                                           8
+#define DDRC_SCHED_LPR_NUM_ENTRIES_MASK                                            0x00003F00U
+
+/*If true, bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or wri
+		e command in the CAM with a bank and page hit will be executed with auto-precharge if SCHED1.pageclose_timer=0. Even if this 
+		egister set to 1 and SCHED1.pageclose_timer is set to 0, explicit precharge (and not auto-precharge) may be issued in some ca
+		es where there is a mode switch between Write and Read or between LPR and HPR. The Read and Write commands that are executed 
+		s part of the ECC scrub requests are also executed without auto-precharge. If false, the bank remains open until there is a n
+		ed to close it (to open a different page, or for page timeout or refresh timeout) - also known as open page policy. The open 
+		age policy can be overridden by setting the per-command-autopre bit on the HIF interface (hif_cmd_autopre). The pageclose fea
+		ure provids a midway between Open and Close page policies. FOR PERFORMANCE ONLY.*/
+#undef DDRC_SCHED_PAGECLOSE_DEFVAL 
+#undef DDRC_SCHED_PAGECLOSE_SHIFT 
+#undef DDRC_SCHED_PAGECLOSE_MASK 
+#define DDRC_SCHED_PAGECLOSE_DEFVAL                                                0x00002005
+#define DDRC_SCHED_PAGECLOSE_SHIFT                                                 2
+#define DDRC_SCHED_PAGECLOSE_MASK                                                  0x00000004U
+
+/*If set then the bank selector prefers writes over reads. FOR DEBUG ONLY.*/
+#undef DDRC_SCHED_PREFER_WRITE_DEFVAL 
+#undef DDRC_SCHED_PREFER_WRITE_SHIFT 
+#undef DDRC_SCHED_PREFER_WRITE_MASK 
+#define DDRC_SCHED_PREFER_WRITE_DEFVAL                                             0x00002005
+#define DDRC_SCHED_PREFER_WRITE_SHIFT                                              1
+#define DDRC_SCHED_PREFER_WRITE_MASK                                               0x00000002U
+
+/*Active low signal. When asserted ('0'), all incoming transactions are forced to low priority. This implies that all High Prio
+		ity Read (HPR) and Variable Priority Read commands (VPR) will be treated as Low Priority Read (LPR) commands. On the write si
+		e, all Variable Priority Write (VPW) commands will be treated as Normal Priority Write (NPW) commands. Forcing the incoming t
+		ansactions to low priority implicitly turns off Bypass path for read commands. FOR PERFORMANCE ONLY.*/
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL 
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT 
+#undef DDRC_SCHED_FORCE_LOW_PRI_N_MASK 
+#define DDRC_SCHED_FORCE_LOW_PRI_N_DEFVAL                                          0x00002005
+#define DDRC_SCHED_FORCE_LOW_PRI_N_SHIFT                                           0
+#define DDRC_SCHED_FORCE_LOW_PRI_N_MASK                                            0x00000001U
+
+/*Number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number o
+		 transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL 
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT 
+#undef DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK 
+#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_DEFVAL                                   0x0F00007F
+#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_SHIFT                                    24
+#define DDRC_PERFLPR1_LPR_XACT_RUN_LENGTH_MASK                                     0xFF000000U
+
+/*Number of clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this regis
+		er is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not
+		be disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL 
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT 
+#undef DDRC_PERFLPR1_LPR_MAX_STARVE_MASK 
+#define DDRC_PERFLPR1_LPR_MAX_STARVE_DEFVAL                                        0x0F00007F
+#define DDRC_PERFLPR1_LPR_MAX_STARVE_SHIFT                                         0
+#define DDRC_PERFLPR1_LPR_MAX_STARVE_MASK                                          0x0000FFFFU
+
+/*Number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of
+		transactions available. Unit: Transaction. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL 
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT 
+#undef DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK 
+#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_DEFVAL                                      0x0F00007F
+#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_SHIFT                                       24
+#define DDRC_PERFWR1_W_XACT_RUN_LENGTH_MASK                                        0xFF000000U
+
+/*Number of clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this regist
+		r is 0x1. Programming it to 0x0 will disable the starvation functionality; during normal operation, this function should not 
+		e disabled as it will cause excessive latencies. Unit: Clock cycles. FOR PERFORMANCE ONLY.*/
+#undef DDRC_PERFWR1_W_MAX_STARVE_DEFVAL 
+#undef DDRC_PERFWR1_W_MAX_STARVE_SHIFT 
+#undef DDRC_PERFWR1_W_MAX_STARVE_MASK 
+#define DDRC_PERFWR1_W_MAX_STARVE_DEFVAL                                           0x0F00007F
+#define DDRC_PERFWR1_W_MAX_STARVE_SHIFT                                            0
+#define DDRC_PERFWR1_W_MAX_STARVE_MASK                                             0x0000FFFFU
+
+/*All even ranks have the same DQ mapping controled by DQMAP0-4 register as rank 0. This register provides DQ swap function for
+		all odd ranks to support CRC feature. rank based DQ swapping is: swap bit 0 with 1, swap bit 2 with 3, swap bit 4 with 5 and 
+		wap bit 6 with 7. 1: Disable rank based DQ swapping 0: Enable rank based DQ swapping Present only in designs configured to su
+		port DDR4.*/
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL 
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT 
+#undef DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK 
+#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_DEFVAL                                        
+#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_SHIFT                                         0
+#define DDRC_DQMAP5_DIS_DQ_RANK_SWAP_MASK                                          0x00000001U
+
+/*When this is set to '0', auto-precharge is disabled for the flushed command in a collision case. Collision cases are write fo
+		lowed by read to same address, read followed by write to same address, or write followed by write to same address with DBG0.d
+		s_wc bit = 1 (where same address comparisons exclude the two address bits representing critical word). FOR DEBUG ONLY.*/
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL 
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT 
+#undef DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK 
+#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_DEFVAL                                    0x00000000
+#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_SHIFT                                     4
+#define DDRC_DBG0_DIS_COLLISION_PAGE_OPT_MASK                                      0x00000010U
+
+/*When 1, disable write combine. FOR DEBUG ONLY*/
+#undef DDRC_DBG0_DIS_WC_DEFVAL 
+#undef DDRC_DBG0_DIS_WC_SHIFT 
+#undef DDRC_DBG0_DIS_WC_MASK 
+#define DDRC_DBG0_DIS_WC_DEFVAL                                                    0x00000000
+#define DDRC_DBG0_DIS_WC_SHIFT                                                     0
+#define DDRC_DBG0_DIS_WC_MASK                                                      0x00000001U
+
+/*Setting this register bit to 1 allows refresh and ZQCS commands to be triggered from hardware via the IOs ext_*. If set to 1,
+		the fields DBGCMD.zq_calib_short and DBGCMD.rank*_refresh have no function, and are ignored by the uMCTL2 logic. Setting this
+		register bit to 0 allows refresh and ZQCS to be triggered from software, via the fields DBGCMD.zq_calib_short and DBGCMD.rank
+		_refresh. If set to 0, the hardware pins ext_* have no function, and are ignored by the uMCTL2 logic. This register is static
+		 and may only be changed when the DDRC reset signal, core_ddrc_rstn, is asserted (0).*/
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL 
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT 
+#undef DDRC_DBGCMD_HW_REF_ZQ_EN_MASK 
+#define DDRC_DBGCMD_HW_REF_ZQ_EN_DEFVAL                                            0x00000000
+#define DDRC_DBGCMD_HW_REF_ZQ_EN_SHIFT                                             31
+#define DDRC_DBGCMD_HW_REF_ZQ_EN_MASK                                              0x80000000U
+
+/*Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in 
+		he uMCTL2, the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1.*/
+#undef DDRC_DBGCMD_CTRLUPD_DEFVAL 
+#undef DDRC_DBGCMD_CTRLUPD_SHIFT 
+#undef DDRC_DBGCMD_CTRLUPD_MASK 
+#define DDRC_DBGCMD_CTRLUPD_DEFVAL                                                 0x00000000
+#define DDRC_DBGCMD_CTRLUPD_SHIFT                                                  5
+#define DDRC_DBGCMD_CTRLUPD_MASK                                                   0x00000020U
+
+/*Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to 
+		he SDRAM. When this request is stored in the uMCTL2, the bit is automatically cleared. This operation can be performed only w
+		en ZQCTL0.dis_auto_zq=1. It is recommended NOT to set this register bit if in Init operating mode. This register bit is ignor
+		d when in Self-Refresh(except LPDDR4) and SR-Powerdown(LPDDR4) and Deep power-down operating modes and Maximum Power Saving M
+		de.*/
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL 
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT 
+#undef DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK 
+#define DDRC_DBGCMD_ZQ_CALIB_SHORT_DEFVAL                                          0x00000000
+#define DDRC_DBGCMD_ZQ_CALIB_SHORT_SHIFT                                           4
+#define DDRC_DBGCMD_ZQ_CALIB_SHORT_MASK                                            0x00000010U
+
+/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1
+		refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
+		be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
+		wn operating modes or Maximum Power Saving Mode.*/
+#undef DDRC_DBGCMD_RANK1_REFRESH_DEFVAL 
+#undef DDRC_DBGCMD_RANK1_REFRESH_SHIFT 
+#undef DDRC_DBGCMD_RANK1_REFRESH_MASK 
+#define DDRC_DBGCMD_RANK1_REFRESH_DEFVAL                                           0x00000000
+#define DDRC_DBGCMD_RANK1_REFRESH_SHIFT                                            1
+#define DDRC_DBGCMD_RANK1_REFRESH_MASK                                             0x00000002U
+
+/*Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0
+		refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared, the command has been stored in uMCTL2. This operation can
+		be performed only when RFSHCTL3.dis_auto_refresh=1. It is recommended NOT to set this register bit if in Init or Deep power-d
+		wn operating modes or Maximum Power Saving Mode.*/
+#undef DDRC_DBGCMD_RANK0_REFRESH_DEFVAL 
+#undef DDRC_DBGCMD_RANK0_REFRESH_SHIFT 
+#undef DDRC_DBGCMD_RANK0_REFRESH_MASK 
+#define DDRC_DBGCMD_RANK0_REFRESH_DEFVAL                                           0x00000000
+#define DDRC_DBGCMD_RANK0_REFRESH_SHIFT                                            0
+#define DDRC_DBGCMD_RANK0_REFRESH_MASK                                             0x00000001U
+
+/*Enable quasi-dynamic register programming outside reset. Program register to 0 to enable quasi-dynamic programming. Set back 
+		egister to 1 once programming is done.*/
+#undef DDRC_SWCTL_SW_DONE_DEFVAL 
+#undef DDRC_SWCTL_SW_DONE_SHIFT 
+#undef DDRC_SWCTL_SW_DONE_MASK 
+#define DDRC_SWCTL_SW_DONE_DEFVAL                                                  
+#define DDRC_SWCTL_SW_DONE_SHIFT                                                   0
+#define DDRC_SWCTL_SW_DONE_MASK                                                    0x00000001U
+
+/*Burst length expansion mode. By default (i.e. bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands, using t
+		e memory burst length as a unit. If set to 1, then XPI will use half of the memory burst length as a unit. This applies to bo
+		h reads and writes. When MSTR.data_bus_width==00, setting bl_exp_mode to 1 has no effect. This can be used in cases where Par
+		ial Writes is enabled (UMCTL2_PARTIAL_WR=1) and DBG0.dis_wc=1, in order to avoid or minimize t_ccd_l penalty in DDR4 and t_cc
+		_mw penalty in LPDDR4. Note that if DBICTL.reg_ddrc_dm_en=0, functionality is not supported in the following cases: - UMCTL2_
+		ARTIAL_WR=0 - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=8 and MSTR.reg_ddrc_burst_rdwr=1000 (LP
+		DR4 only) - UMCTL2_PARTIAL_WR=1, MSTR.reg_ddrc_data_bus_width=01, MEMC_BURST_LENGTH=4 and MSTR.reg_ddrc_burst_rdwr=0100 (DDR4
+		only), with either MSTR.reg_ddrc_burstchop=0 or CRCPARCTL1.reg_ddrc_crc_enable=1 Functionality is also not supported if Share
+		-AC is enabled*/
+#undef DDRC_PCCFG_BL_EXP_MODE_DEFVAL 
+#undef DDRC_PCCFG_BL_EXP_MODE_SHIFT 
+#undef DDRC_PCCFG_BL_EXP_MODE_MASK 
+#define DDRC_PCCFG_BL_EXP_MODE_DEFVAL                                              0x00000000
+#define DDRC_PCCFG_BL_EXP_MODE_SHIFT                                               8
+#define DDRC_PCCFG_BL_EXP_MODE_MASK                                                0x00000100U
+
+/*Page match four limit. If set to 1, limits the number of consecutive same page DDRC transactions that can be granted by the P
+		rt Arbiter to four when Page Match feature is enabled. If set to 0, there is no limit imposed on number of consecutive same p
+		ge DDRC transactions.*/
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL 
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT 
+#undef DDRC_PCCFG_PAGEMATCH_LIMIT_MASK 
+#define DDRC_PCCFG_PAGEMATCH_LIMIT_DEFVAL                                          0x00000000
+#define DDRC_PCCFG_PAGEMATCH_LIMIT_SHIFT                                           4
+#define DDRC_PCCFG_PAGEMATCH_LIMIT_MASK                                            0x00000010U
+
+/*If set to 1 (enabled), sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based 
+		n urgent input (awurgent, arurgent) coming from AXI master. If set to 0 (disabled), co_gs_go2critical_wr and co_gs_go2critica
+		_lpr/co_gs_go2critical_hpr signals at DDRC are driven to 1b'0.*/
+#undef DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL 
+#undef DDRC_PCCFG_GO2CRITICAL_EN_SHIFT 
+#undef DDRC_PCCFG_GO2CRITICAL_EN_MASK 
+#define DDRC_PCCFG_GO2CRITICAL_EN_DEFVAL                                           0x00000000
+#define DDRC_PCCFG_GO2CRITICAL_EN_SHIFT                                            0
+#define DDRC_PCCFG_GO2CRITICAL_EN_MASK                                             0x00000001U
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_0_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_0_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_0_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_0_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_0_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_0_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_0_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_0_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_0_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_0_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_0_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_0_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_0_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_0_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_0_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_0_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_0_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_0_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_0_PORT_EN_MASK 
+#define DDRC_PCTRL_0_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_0_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_0_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_0_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
+#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_0_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_0_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_1_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_1_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_1_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_1_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_1_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_1_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_1_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_1_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_1_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_1_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_1_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_1_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_1_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_1_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_1_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_1_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_1_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_1_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_1_PORT_EN_MASK 
+#define DDRC_PCTRL_1_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_1_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_1_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 
+		ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 
+		s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_SHIFT                                     24
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION2_MASK                                      0x03000000U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_1_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
+		el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
+		directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 
+		ust be set to distinct values.*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_DEFVAL                                     0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_SHIFT                                      8
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL2_MASK                                       0x00000F00U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_DEFVAL                                     0x02000E00
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_1_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_1_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_2_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_2_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_2_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_2_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_2_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_2_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_2_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_2_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_2_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_2_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_2_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_2_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_2_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_2_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_2_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_2_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_2_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_2_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_2_PORT_EN_MASK 
+#define DDRC_PCTRL_2_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_2_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_2_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region2. For dual address queue configurations, region2 maps to the red address 
+		ueue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic class of region2 
+		s set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_SHIFT                                     24
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION2_MASK                                      0x03000000U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_DEFVAL                                    0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_2_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (le
+		el1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA, arqos values are used
+		directly as port priorities, where the higher the value corresponds to higher port priority. All of the map_level* registers 
+		ust be set to distinct values.*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_DEFVAL                                     0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_SHIFT                                      8
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL2_MASK                                       0x00000F00U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_DEFVAL                                     0x02000E00
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_2_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_2_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_3_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_3_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_3_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_3_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_3_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_3_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_3_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_3_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_3_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_3_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_3_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_3_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_3_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_3_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_3_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_3_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_3_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_3_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_3_PORT_EN_MASK 
+#define DDRC_PCTRL_3_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_3_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_3_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_3_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
+#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_3_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_3_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_SHIFT                                    20
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION1_MASK                                     0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_SHIFT                                    16
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_REGION0_MASK                                     0x00030000U
+
+/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.*/
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT 
+#undef DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK 
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_SHIFT                                      0
+#define DDRC_PCFGWQOS0_3_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for write transactions.*/
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL 
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT 
+#undef DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK 
+#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_DEFVAL                                   
+#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_SHIFT                                    0
+#define DDRC_PCFGWQOS1_3_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_4_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_4_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_4_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_4_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_4_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_4_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_4_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_4_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_4_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_4_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_4_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_4_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_4_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_4_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_4_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_4_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_4_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_4_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_4_PORT_EN_MASK 
+#define DDRC_PCTRL_4_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_4_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_4_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_4_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
+#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_4_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_4_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_SHIFT                                    20
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION1_MASK                                     0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_SHIFT                                    16
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_REGION0_MASK                                     0x00030000U
+
+/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.*/
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT 
+#undef DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK 
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_SHIFT                                      0
+#define DDRC_PCFGWQOS0_4_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for write transactions.*/
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL 
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT 
+#undef DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK 
+#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_DEFVAL                                   
+#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_SHIFT                                    0
+#define DDRC_PCFGWQOS1_4_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_DEFVAL                                   0x00000000
+#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGR_5_RD_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if enabled in PCCFG.
+		o2critical_en register. Note that arurgent signal can be asserted anytime and as long as required which is independent of add
+		ess handshaking (it is not associated with any particular command).*/
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_DEFVAL                                      0x00000000
+#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGR_5_RD_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the read channel of the port.*/
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK 
+#define DDRC_PCFGR_5_RD_PORT_AGING_EN_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_5_RD_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGR_5_RD_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of read aging counters. These counters will be parallel loaded after reset, or after each g
+		ant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted. 
+		he higher significant 5-bits of the read aging counter sets the priority of the read channel of a given port. Port's priority
+		will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0, the corre
+		ponding port channel will have the highest priority level (timeout condition - Priority0). For multi-port configurations, the
+		aging counters cannot be used to set port priorities when external dynamic priority inputs (arqos) are enabled (timeout is st
+		ll applicable). For single port configurations, the aging counters are only used when they timeout (become 0) to force read-w
+		ite direction switching. In this case, external dynamic priority input, arqos (for reads only) can still be used to set the D
+		RC read priority (2 priority levels: low priority read - LPR, high priority read - HPR) on a command by command basis. Note: 
+		he two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK 
+#define DDRC_PCFGR_5_RD_PORT_PRIORITY_DEFVAL                                       0x00000000
+#define DDRC_PCFGR_5_RD_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGR_5_RD_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*If set to 1, enables the Page Match feature. If enabled, once a requesting port is granted, the port is continued to be grant
+		d if the following immediate commands are to the same memory page (same bank and same row). See also related PCCFG.pagematch_
+		imit register.*/
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK 
+#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_DEFVAL                                   0x00004000
+#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_SHIFT                                    14
+#define DDRC_PCFGW_5_WR_PORT_PAGEMATCH_EN_MASK                                     0x00004000U
+
+/*If set to 1, enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master, that por
+		 becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in PCCFG.go2critical_en register
+		 Note that awurgent signal can be asserted anytime and as long as required which is independent of address handshaking (it is
+		not associated with any particular command).*/
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK 
+#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_DEFVAL                                      0x00004000
+#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_SHIFT                                       13
+#define DDRC_PCFGW_5_WR_PORT_URGENT_EN_MASK                                        0x00002000U
+
+/*If set to 1, enables aging function for the write channel of the port.*/
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK 
+#define DDRC_PCFGW_5_WR_PORT_AGING_EN_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_5_WR_PORT_AGING_EN_SHIFT                                        12
+#define DDRC_PCFGW_5_WR_PORT_AGING_EN_MASK                                         0x00001000U
+
+/*Determines the initial load value of write aging counters. These counters will be parallel loaded after reset, or after each 
+		rant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not granted.
+		The higher significant 5-bits of the write aging counter sets the initial priority of the write channel of a given port. Port
+		s priority will increase as the higher significant 5-bits of the counter starts to decrease. When the aging counter becomes 0
+		 the corresponding port channel will have the highest priority level. For multi-port configurations, the aging counters canno
+		 be used to set port priorities when external dynamic priority inputs (awqos) are enabled (timeout is still applicable). For 
+		ingle port configurations, the aging counters are only used when they timeout (become 0) to force read-write direction switch
+		ng. Note: The two LSBs of this register field are tied internally to 2'b00.*/
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL 
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT 
+#undef DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK 
+#define DDRC_PCFGW_5_WR_PORT_PRIORITY_DEFVAL                                       0x00004000
+#define DDRC_PCFGW_5_WR_PORT_PRIORITY_SHIFT                                        0
+#define DDRC_PCFGW_5_WR_PORT_PRIORITY_MASK                                         0x000003FFU
+
+/*Enables port n.*/
+#undef DDRC_PCTRL_5_PORT_EN_DEFVAL 
+#undef DDRC_PCTRL_5_PORT_EN_SHIFT 
+#undef DDRC_PCTRL_5_PORT_EN_MASK 
+#define DDRC_PCTRL_5_PORT_EN_DEFVAL                                                
+#define DDRC_PCTRL_5_PORT_EN_SHIFT                                                 0
+#define DDRC_PCTRL_5_PORT_EN_MASK                                                  0x00000001U
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0 : LPR, 1: VPR, 2: HPR. For dual address queue conf
+		gurations, region1 maps to the blue address queue. In this case, valid values are 0: LPR and 1: VPR only. When VPR support is
+		disabled (UMCTL2_VPR_EN = 0) and traffic class of region 1 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_SHIFT                                     20
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION1_MASK                                      0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: LPR, 1: VPR, 2: HPR. For dual address queue confi
+		urations, region 0 maps to the blue address queue. In this case, valid values are: 0: LPR and 1: VPR only. When VPR support i
+		 disabled (UMCTL2_VPR_EN = 0) and traffic class of region0 is set to 1 (VPR), VPR traffic is aliased to LPR traffic.*/
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_DEFVAL                                    0x00000000
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_SHIFT                                     16
+#define DDRC_PCFGQOS0_5_RQOS_MAP_REGION0_MASK                                      0x00030000U
+
+/*Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for d
+		al RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA, arqos values are used directly as port prio
+		ities, where the higher the value corresponds to higher port priority. All of the map_level* registers must be set to distinc
+		 values.*/
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT 
+#undef DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK 
+#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_DEFVAL                                     0x00000000
+#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_SHIFT                                      0
+#define DDRC_PCFGQOS0_5_RQOS_MAP_LEVEL1_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for transactions mapped to the red address queue.*/
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK 
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_SHIFT                                    16
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTR_MASK                                     0x07FF0000U
+
+/*Specifies the timeout value for transactions mapped to the blue address queue.*/
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT 
+#undef DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK 
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_DEFVAL                                   0x00000000
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_SHIFT                                    0
+#define DDRC_PCFGQOS1_5_RQOS_MAP_TIMEOUTB_MASK                                     0x000007FFU
+
+/*This bitfield indicates the traffic class of region 1. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW), VPW traffic is aliased to LPW traffic.*/
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK 
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_SHIFT                                    20
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION1_MASK                                     0x00300000U
+
+/*This bitfield indicates the traffic class of region 0. Valid values are: 0: NPW, 1: VPW. When VPW support is disabled (UMCTL2
+		VPW_EN = 0) and traffic class of region0 is set to 1 (VPW), VPW traffic is aliased to NPW traffic.*/
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK 
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_DEFVAL                                   0x00000000
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_SHIFT                                    16
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_REGION0_MASK                                     0x00030000U
+
+/*Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 14 which c
+		rresponds to awqos. Note that for PA, awqos values are used directly as port priorities, where the higher the value correspon
+		s to higher port priority.*/
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT 
+#undef DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK 
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_DEFVAL                                     0x00000000
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_SHIFT                                      0
+#define DDRC_PCFGWQOS0_5_WQOS_MAP_LEVEL_MASK                                       0x0000000FU
+
+/*Specifies the timeout value for write transactions.*/
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL 
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT 
+#undef DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK 
+#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_DEFVAL                                   
+#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_SHIFT                                    0
+#define DDRC_PCFGWQOS1_5_WQOS_MAP_TIMEOUT_MASK                                     0x000007FFU
+
+/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
+		 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/
+#undef DDRC_SARBASE0_BASE_ADDR_DEFVAL 
+#undef DDRC_SARBASE0_BASE_ADDR_SHIFT 
+#undef DDRC_SARBASE0_BASE_ADDR_MASK 
+#define DDRC_SARBASE0_BASE_ADDR_DEFVAL                                             
+#define DDRC_SARBASE0_BASE_ADDR_SHIFT                                              0
+#define DDRC_SARBASE0_BASE_ADDR_MASK                                               0x000001FFU
+
+/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
+		e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 
+		or example, if register is programmed to 0, region will have 1 block.*/
+#undef DDRC_SARSIZE0_NBLOCKS_DEFVAL 
+#undef DDRC_SARSIZE0_NBLOCKS_SHIFT 
+#undef DDRC_SARSIZE0_NBLOCKS_MASK 
+#define DDRC_SARSIZE0_NBLOCKS_DEFVAL                                               
+#define DDRC_SARSIZE0_NBLOCKS_SHIFT                                                0
+#define DDRC_SARSIZE0_NBLOCKS_MASK                                                 0x000000FFU
+
+/*Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determine
+		 by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)).*/
+#undef DDRC_SARBASE1_BASE_ADDR_DEFVAL 
+#undef DDRC_SARBASE1_BASE_ADDR_SHIFT 
+#undef DDRC_SARBASE1_BASE_ADDR_MASK 
+#define DDRC_SARBASE1_BASE_ADDR_DEFVAL                                             
+#define DDRC_SARBASE1_BASE_ADDR_SHIFT                                              0
+#define DDRC_SARBASE1_BASE_ADDR_MASK                                               0x000001FFU
+
+/*Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block si
+		e as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks + 1. 
+		or example, if register is programmed to 0, region will have 1 block.*/
+#undef DDRC_SARSIZE1_NBLOCKS_DEFVAL 
+#undef DDRC_SARSIZE1_NBLOCKS_SHIFT 
+#undef DDRC_SARSIZE1_NBLOCKS_MASK 
+#define DDRC_SARSIZE1_NBLOCKS_DEFVAL                                               
+#define DDRC_SARSIZE1_NBLOCKS_SHIFT                                                0
+#define DDRC_SARSIZE1_NBLOCKS_MASK                                                 0x000000FFU
+
+/*Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signa
+		s at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are not phase-aligne
+		, this timing parameter should be rounded up to the next integer value. Note that if using RDIMM, it is necessary to incremen
+		 this parameter by RDIMM's extra cycle of latency in terms of DFI clock.*/
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_DEFVAL                                0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_SHIFT                                 24
+#define DDRC_DFITMG0_SHADOW_DFI_T_CTRL_DELAY_MASK                                  0x1F000000U
+
+/*Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR or SDR values Selects whether value in DFITM
+		0.dfi_t_rddata_en is in terms of SDR or HDR clock cycles: - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles R
+		fer to PHY specification for correct value.*/
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_DEFVAL                              0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_SHIFT                               23
+#define DDRC_DFITMG0_SHADOW_DFI_RDDATA_USE_SDR_MASK                                0x00800000U
+
+/*Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY spe
+		ification for correct value. This corresponds to the DFI parameter trddata_en. Note that, depending on the PHY, if using RDIM
+		, it may be necessary to use the value (CL + 1) in the calculation of trddata_en. This is to compensate for the extra cycle o
+		 latency through the RDIMM. Unit: Clocks*/
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_DEFVAL                                 0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_SHIFT                                  16
+#define DDRC_DFITMG0_SHADOW_DFI_T_RDDATA_EN_MASK                                   0x003F0000U
+
+/*Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR or SDR values Selects whether value in DFITMG
+		.dfi_tphy_wrlat is in terms of SDR or HDR clock cycles Selects whether value in DFITMG0.dfi_tphy_wrdata is in terms of SDR or
+		HDR clock cycles - 0 in terms of HDR clock cycles - 1 in terms of SDR clock cycles Refer to PHY specification for correct val
+		e.*/
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_DEFVAL                              0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_SHIFT                               15
+#define DDRC_DFITMG0_SHADOW_DFI_WRDATA_USE_SDR_MASK                                0x00008000U
+
+/*Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on th
+		 dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. Refer to PHY specification for correct value. N
+		te, max supported value is 8. Unit: Clocks*/
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_DEFVAL                                 0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_SHIFT                                  8
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRDATA_MASK                                   0x00003F00U
+
+/*Write latency Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timin
+		 parameter tphy_wrlat. Refer to PHY specification for correct value.Note that, depending on the PHY, if using RDIMM, it may b
+		 necessary to use the value (CL + 1) in the calculation of tphy_wrlat. This is to compensate for the extra cycle of latency t
+		rough the RDIMM.*/
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT 
+#undef DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK 
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_DEFVAL                                  0x07020002
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_SHIFT                                   0
+#define DDRC_DFITMG0_SHADOW_DFI_TPHY_WRLAT_MASK                                    0x0000003FU
+
+/*DDR block level reset inside of the DDR Sub System*/
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT 
+#undef CRF_APB_RST_DDR_SS_DDR_RESET_MASK 
+#define CRF_APB_RST_DDR_SS_DDR_RESET_DEFVAL                                        0x0000000F
+#define CRF_APB_RST_DDR_SS_DDR_RESET_SHIFT                                         3
+#define CRF_APB_RST_DDR_SS_DDR_RESET_MASK                                          0x00000008U
+
+/*Address Copy*/
+#undef DDR_PHY_PGCR0_ADCP_DEFVAL 
+#undef DDR_PHY_PGCR0_ADCP_SHIFT 
+#undef DDR_PHY_PGCR0_ADCP_MASK 
+#define DDR_PHY_PGCR0_ADCP_DEFVAL                                                  0x07001E00
+#define DDR_PHY_PGCR0_ADCP_SHIFT                                                   31
+#define DDR_PHY_PGCR0_ADCP_MASK                                                    0x80000000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_30_27_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_30_27_MASK 
+#define DDR_PHY_PGCR0_RESERVED_30_27_DEFVAL                                        0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_30_27_SHIFT                                         27
+#define DDR_PHY_PGCR0_RESERVED_30_27_MASK                                          0x78000000U
+
+/*PHY FIFO Reset*/
+#undef DDR_PHY_PGCR0_PHYFRST_DEFVAL 
+#undef DDR_PHY_PGCR0_PHYFRST_SHIFT 
+#undef DDR_PHY_PGCR0_PHYFRST_MASK 
+#define DDR_PHY_PGCR0_PHYFRST_DEFVAL                                               0x07001E00
+#define DDR_PHY_PGCR0_PHYFRST_SHIFT                                                26
+#define DDR_PHY_PGCR0_PHYFRST_MASK                                                 0x04000000U
+
+/*Oscillator Mode Address/Command Delay Line Select*/
+#undef DDR_PHY_PGCR0_OSCACDL_DEFVAL 
+#undef DDR_PHY_PGCR0_OSCACDL_SHIFT 
+#undef DDR_PHY_PGCR0_OSCACDL_MASK 
+#define DDR_PHY_PGCR0_OSCACDL_DEFVAL                                               0x07001E00
+#define DDR_PHY_PGCR0_OSCACDL_SHIFT                                                24
+#define DDR_PHY_PGCR0_OSCACDL_MASK                                                 0x03000000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_23_19_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_23_19_MASK 
+#define DDR_PHY_PGCR0_RESERVED_23_19_DEFVAL                                        0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_23_19_SHIFT                                         19
+#define DDR_PHY_PGCR0_RESERVED_23_19_MASK                                          0x00F80000U
+
+/*Digital Test Output Select*/
+#undef DDR_PHY_PGCR0_DTOSEL_DEFVAL 
+#undef DDR_PHY_PGCR0_DTOSEL_SHIFT 
+#undef DDR_PHY_PGCR0_DTOSEL_MASK 
+#define DDR_PHY_PGCR0_DTOSEL_DEFVAL                                                0x07001E00
+#define DDR_PHY_PGCR0_DTOSEL_SHIFT                                                 14
+#define DDR_PHY_PGCR0_DTOSEL_MASK                                                  0x0007C000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_PGCR0_RESERVED_13_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_13_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_13_MASK 
+#define DDR_PHY_PGCR0_RESERVED_13_DEFVAL                                           0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_13_SHIFT                                            13
+#define DDR_PHY_PGCR0_RESERVED_13_MASK                                             0x00002000U
+
+/*Oscillator Mode Division*/
+#undef DDR_PHY_PGCR0_OSCDIV_DEFVAL 
+#undef DDR_PHY_PGCR0_OSCDIV_SHIFT 
+#undef DDR_PHY_PGCR0_OSCDIV_MASK 
+#define DDR_PHY_PGCR0_OSCDIV_DEFVAL                                                0x07001E00
+#define DDR_PHY_PGCR0_OSCDIV_SHIFT                                                 9
+#define DDR_PHY_PGCR0_OSCDIV_MASK                                                  0x00001E00U
+
+/*Oscillator Enable*/
+#undef DDR_PHY_PGCR0_OSCEN_DEFVAL 
+#undef DDR_PHY_PGCR0_OSCEN_SHIFT 
+#undef DDR_PHY_PGCR0_OSCEN_MASK 
+#define DDR_PHY_PGCR0_OSCEN_DEFVAL                                                 0x07001E00
+#define DDR_PHY_PGCR0_OSCEN_SHIFT                                                  8
+#define DDR_PHY_PGCR0_OSCEN_MASK                                                   0x00000100U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL 
+#undef DDR_PHY_PGCR0_RESERVED_7_0_SHIFT 
+#undef DDR_PHY_PGCR0_RESERVED_7_0_MASK 
+#define DDR_PHY_PGCR0_RESERVED_7_0_DEFVAL                                          0x07001E00
+#define DDR_PHY_PGCR0_RESERVED_7_0_SHIFT                                           0
+#define DDR_PHY_PGCR0_RESERVED_7_0_MASK                                            0x000000FFU
+
+/*Clear Training Status Registers*/
+#undef DDR_PHY_PGCR2_CLRTSTAT_DEFVAL 
+#undef DDR_PHY_PGCR2_CLRTSTAT_SHIFT 
+#undef DDR_PHY_PGCR2_CLRTSTAT_MASK 
+#define DDR_PHY_PGCR2_CLRTSTAT_DEFVAL                                              0x00F12480
+#define DDR_PHY_PGCR2_CLRTSTAT_SHIFT                                               31
+#define DDR_PHY_PGCR2_CLRTSTAT_MASK                                                0x80000000U
+
+/*Clear Impedance Calibration*/
+#undef DDR_PHY_PGCR2_CLRZCAL_DEFVAL 
+#undef DDR_PHY_PGCR2_CLRZCAL_SHIFT 
+#undef DDR_PHY_PGCR2_CLRZCAL_MASK 
+#define DDR_PHY_PGCR2_CLRZCAL_DEFVAL                                               0x00F12480
+#define DDR_PHY_PGCR2_CLRZCAL_SHIFT                                                30
+#define DDR_PHY_PGCR2_CLRZCAL_MASK                                                 0x40000000U
+
+/*Clear Parity Error*/
+#undef DDR_PHY_PGCR2_CLRPERR_DEFVAL 
+#undef DDR_PHY_PGCR2_CLRPERR_SHIFT 
+#undef DDR_PHY_PGCR2_CLRPERR_MASK 
+#define DDR_PHY_PGCR2_CLRPERR_DEFVAL                                               0x00F12480
+#define DDR_PHY_PGCR2_CLRPERR_SHIFT                                                29
+#define DDR_PHY_PGCR2_CLRPERR_MASK                                                 0x20000000U
+
+/*Initialization Complete Pin Configuration*/
+#undef DDR_PHY_PGCR2_ICPC_DEFVAL 
+#undef DDR_PHY_PGCR2_ICPC_SHIFT 
+#undef DDR_PHY_PGCR2_ICPC_MASK 
+#define DDR_PHY_PGCR2_ICPC_DEFVAL                                                  0x00F12480
+#define DDR_PHY_PGCR2_ICPC_SHIFT                                                   28
+#define DDR_PHY_PGCR2_ICPC_MASK                                                    0x10000000U
+
+/*Data Training PUB Mode Exit Timer*/
+#undef DDR_PHY_PGCR2_DTPMXTMR_DEFVAL 
+#undef DDR_PHY_PGCR2_DTPMXTMR_SHIFT 
+#undef DDR_PHY_PGCR2_DTPMXTMR_MASK 
+#define DDR_PHY_PGCR2_DTPMXTMR_DEFVAL                                              0x00F12480
+#define DDR_PHY_PGCR2_DTPMXTMR_SHIFT                                               20
+#define DDR_PHY_PGCR2_DTPMXTMR_MASK                                                0x0FF00000U
+
+/*Initialization Bypass*/
+#undef DDR_PHY_PGCR2_INITFSMBYP_DEFVAL 
+#undef DDR_PHY_PGCR2_INITFSMBYP_SHIFT 
+#undef DDR_PHY_PGCR2_INITFSMBYP_MASK 
+#define DDR_PHY_PGCR2_INITFSMBYP_DEFVAL                                            0x00F12480
+#define DDR_PHY_PGCR2_INITFSMBYP_SHIFT                                             19
+#define DDR_PHY_PGCR2_INITFSMBYP_MASK                                              0x00080000U
+
+/*PLL FSM Bypass*/
+#undef DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL 
+#undef DDR_PHY_PGCR2_PLLFSMBYP_SHIFT 
+#undef DDR_PHY_PGCR2_PLLFSMBYP_MASK 
+#define DDR_PHY_PGCR2_PLLFSMBYP_DEFVAL                                             0x00F12480
+#define DDR_PHY_PGCR2_PLLFSMBYP_SHIFT                                              18
+#define DDR_PHY_PGCR2_PLLFSMBYP_MASK                                               0x00040000U
+
+/*Refresh Period*/
+#undef DDR_PHY_PGCR2_TREFPRD_DEFVAL 
+#undef DDR_PHY_PGCR2_TREFPRD_SHIFT 
+#undef DDR_PHY_PGCR2_TREFPRD_MASK 
+#define DDR_PHY_PGCR2_TREFPRD_DEFVAL                                               0x00F12480
+#define DDR_PHY_PGCR2_TREFPRD_SHIFT                                                0
+#define DDR_PHY_PGCR2_TREFPRD_MASK                                                 0x0003FFFFU
+
+/*Frequency B Ratio Term*/
+#undef DDR_PHY_PGCR5_FRQBT_DEFVAL 
+#undef DDR_PHY_PGCR5_FRQBT_SHIFT 
+#undef DDR_PHY_PGCR5_FRQBT_MASK 
+#define DDR_PHY_PGCR5_FRQBT_DEFVAL                                                 0x01010000
+#define DDR_PHY_PGCR5_FRQBT_SHIFT                                                  24
+#define DDR_PHY_PGCR5_FRQBT_MASK                                                   0xFF000000U
+
+/*Frequency A Ratio Term*/
+#undef DDR_PHY_PGCR5_FRQAT_DEFVAL 
+#undef DDR_PHY_PGCR5_FRQAT_SHIFT 
+#undef DDR_PHY_PGCR5_FRQAT_MASK 
+#define DDR_PHY_PGCR5_FRQAT_DEFVAL                                                 0x01010000
+#define DDR_PHY_PGCR5_FRQAT_SHIFT                                                  16
+#define DDR_PHY_PGCR5_FRQAT_MASK                                                   0x00FF0000U
+
+/*DFI Disconnect Time Period*/
+#undef DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL 
+#undef DDR_PHY_PGCR5_DISCNPERIOD_SHIFT 
+#undef DDR_PHY_PGCR5_DISCNPERIOD_MASK 
+#define DDR_PHY_PGCR5_DISCNPERIOD_DEFVAL                                           0x01010000
+#define DDR_PHY_PGCR5_DISCNPERIOD_SHIFT                                            8
+#define DDR_PHY_PGCR5_DISCNPERIOD_MASK                                             0x0000FF00U
+
+/*Receiver bias core side control*/
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL 
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT 
+#undef DDR_PHY_PGCR5_VREF_RBCTRL_MASK 
+#define DDR_PHY_PGCR5_VREF_RBCTRL_DEFVAL                                           0x01010000
+#define DDR_PHY_PGCR5_VREF_RBCTRL_SHIFT                                            4
+#define DDR_PHY_PGCR5_VREF_RBCTRL_MASK                                             0x000000F0U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PGCR5_RESERVED_3_DEFVAL 
+#undef DDR_PHY_PGCR5_RESERVED_3_SHIFT 
+#undef DDR_PHY_PGCR5_RESERVED_3_MASK 
+#define DDR_PHY_PGCR5_RESERVED_3_DEFVAL                                            0x01010000
+#define DDR_PHY_PGCR5_RESERVED_3_SHIFT                                             3
+#define DDR_PHY_PGCR5_RESERVED_3_MASK                                              0x00000008U
+
+/*Internal VREF generator REFSEL ragne select*/
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL 
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT 
+#undef DDR_PHY_PGCR5_DXREFISELRANGE_MASK 
+#define DDR_PHY_PGCR5_DXREFISELRANGE_DEFVAL                                        0x01010000
+#define DDR_PHY_PGCR5_DXREFISELRANGE_SHIFT                                         2
+#define DDR_PHY_PGCR5_DXREFISELRANGE_MASK                                          0x00000004U
+
+/*DDL Page Read Write select*/
+#undef DDR_PHY_PGCR5_DDLPGACT_DEFVAL 
+#undef DDR_PHY_PGCR5_DDLPGACT_SHIFT 
+#undef DDR_PHY_PGCR5_DDLPGACT_MASK 
+#define DDR_PHY_PGCR5_DDLPGACT_DEFVAL                                              0x01010000
+#define DDR_PHY_PGCR5_DDLPGACT_SHIFT                                               1
+#define DDR_PHY_PGCR5_DDLPGACT_MASK                                                0x00000002U
+
+/*DDL Page Read Write select*/
+#undef DDR_PHY_PGCR5_DDLPGRW_DEFVAL 
+#undef DDR_PHY_PGCR5_DDLPGRW_SHIFT 
+#undef DDR_PHY_PGCR5_DDLPGRW_MASK 
+#define DDR_PHY_PGCR5_DDLPGRW_DEFVAL                                               0x01010000
+#define DDR_PHY_PGCR5_DDLPGRW_SHIFT                                                0
+#define DDR_PHY_PGCR5_DDLPGRW_MASK                                                 0x00000001U
+
+/*PLL Power-Down Time*/
+#undef DDR_PHY_PTR0_TPLLPD_DEFVAL 
+#undef DDR_PHY_PTR0_TPLLPD_SHIFT 
+#undef DDR_PHY_PTR0_TPLLPD_MASK 
+#define DDR_PHY_PTR0_TPLLPD_DEFVAL                                                 0x42C21590
+#define DDR_PHY_PTR0_TPLLPD_SHIFT                                                  21
+#define DDR_PHY_PTR0_TPLLPD_MASK                                                   0xFFE00000U
+
+/*PLL Gear Shift Time*/
+#undef DDR_PHY_PTR0_TPLLGS_DEFVAL 
+#undef DDR_PHY_PTR0_TPLLGS_SHIFT 
+#undef DDR_PHY_PTR0_TPLLGS_MASK 
+#define DDR_PHY_PTR0_TPLLGS_DEFVAL                                                 0x42C21590
+#define DDR_PHY_PTR0_TPLLGS_SHIFT                                                  6
+#define DDR_PHY_PTR0_TPLLGS_MASK                                                   0x001FFFC0U
+
+/*PHY Reset Time*/
+#undef DDR_PHY_PTR0_TPHYRST_DEFVAL 
+#undef DDR_PHY_PTR0_TPHYRST_SHIFT 
+#undef DDR_PHY_PTR0_TPHYRST_MASK 
+#define DDR_PHY_PTR0_TPHYRST_DEFVAL                                                0x42C21590
+#define DDR_PHY_PTR0_TPHYRST_SHIFT                                                 0
+#define DDR_PHY_PTR0_TPHYRST_MASK                                                  0x0000003FU
+
+/*PLL Lock Time*/
+#undef DDR_PHY_PTR1_TPLLLOCK_DEFVAL 
+#undef DDR_PHY_PTR1_TPLLLOCK_SHIFT 
+#undef DDR_PHY_PTR1_TPLLLOCK_MASK 
+#define DDR_PHY_PTR1_TPLLLOCK_DEFVAL                                               0xD05612C0
+#define DDR_PHY_PTR1_TPLLLOCK_SHIFT                                                16
+#define DDR_PHY_PTR1_TPLLLOCK_MASK                                                 0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_PTR1_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_PTR1_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_PTR1_RESERVED_15_13_MASK 
+#define DDR_PHY_PTR1_RESERVED_15_13_DEFVAL                                         0xD05612C0
+#define DDR_PHY_PTR1_RESERVED_15_13_SHIFT                                          13
+#define DDR_PHY_PTR1_RESERVED_15_13_MASK                                           0x0000E000U
+
+/*PLL Reset Time*/
+#undef DDR_PHY_PTR1_TPLLRST_DEFVAL 
+#undef DDR_PHY_PTR1_TPLLRST_SHIFT 
+#undef DDR_PHY_PTR1_TPLLRST_MASK 
+#define DDR_PHY_PTR1_TPLLRST_DEFVAL                                                0xD05612C0
+#define DDR_PHY_PTR1_TPLLRST_SHIFT                                                 0
+#define DDR_PHY_PTR1_TPLLRST_MASK                                                  0x00001FFFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_31_28_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_31_28_MASK 
+#define DDR_PHY_DSGCR_RESERVED_31_28_DEFVAL                                        0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_31_28_SHIFT                                         28
+#define DDR_PHY_DSGCR_RESERVED_31_28_MASK                                          0xF0000000U
+
+/*When RDBI enabled, this bit is used to select RDBI CL calculation, if it is 1b1, calculation will use RDBICL, otherwise use d
+		fault calculation.*/
+#undef DDR_PHY_DSGCR_RDBICLSEL_DEFVAL 
+#undef DDR_PHY_DSGCR_RDBICLSEL_SHIFT 
+#undef DDR_PHY_DSGCR_RDBICLSEL_MASK 
+#define DDR_PHY_DSGCR_RDBICLSEL_DEFVAL                                             0x02A04101
+#define DDR_PHY_DSGCR_RDBICLSEL_SHIFT                                              27
+#define DDR_PHY_DSGCR_RDBICLSEL_MASK                                               0x08000000U
+
+/*When RDBI enabled, if RDBICLSEL is asserted, RDBI CL adjust using this value.*/
+#undef DDR_PHY_DSGCR_RDBICL_DEFVAL 
+#undef DDR_PHY_DSGCR_RDBICL_SHIFT 
+#undef DDR_PHY_DSGCR_RDBICL_MASK 
+#define DDR_PHY_DSGCR_RDBICL_DEFVAL                                                0x02A04101
+#define DDR_PHY_DSGCR_RDBICL_SHIFT                                                 24
+#define DDR_PHY_DSGCR_RDBICL_MASK                                                  0x07000000U
+
+/*PHY Impedance Update Enable*/
+#undef DDR_PHY_DSGCR_PHYZUEN_DEFVAL 
+#undef DDR_PHY_DSGCR_PHYZUEN_SHIFT 
+#undef DDR_PHY_DSGCR_PHYZUEN_MASK 
+#define DDR_PHY_DSGCR_PHYZUEN_DEFVAL                                               0x02A04101
+#define DDR_PHY_DSGCR_PHYZUEN_SHIFT                                                23
+#define DDR_PHY_DSGCR_PHYZUEN_MASK                                                 0x00800000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DSGCR_RESERVED_22_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_22_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_22_MASK 
+#define DDR_PHY_DSGCR_RESERVED_22_DEFVAL                                           0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_22_SHIFT                                            22
+#define DDR_PHY_DSGCR_RESERVED_22_MASK                                             0x00400000U
+
+/*SDRAM Reset Output Enable*/
+#undef DDR_PHY_DSGCR_RSTOE_DEFVAL 
+#undef DDR_PHY_DSGCR_RSTOE_SHIFT 
+#undef DDR_PHY_DSGCR_RSTOE_MASK 
+#define DDR_PHY_DSGCR_RSTOE_DEFVAL                                                 0x02A04101
+#define DDR_PHY_DSGCR_RSTOE_SHIFT                                                  21
+#define DDR_PHY_DSGCR_RSTOE_MASK                                                   0x00200000U
+
+/*Single Data Rate Mode*/
+#undef DDR_PHY_DSGCR_SDRMODE_DEFVAL 
+#undef DDR_PHY_DSGCR_SDRMODE_SHIFT 
+#undef DDR_PHY_DSGCR_SDRMODE_MASK 
+#define DDR_PHY_DSGCR_SDRMODE_DEFVAL                                               0x02A04101
+#define DDR_PHY_DSGCR_SDRMODE_SHIFT                                                19
+#define DDR_PHY_DSGCR_SDRMODE_MASK                                                 0x00180000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DSGCR_RESERVED_18_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_18_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_18_MASK 
+#define DDR_PHY_DSGCR_RESERVED_18_DEFVAL                                           0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_18_SHIFT                                            18
+#define DDR_PHY_DSGCR_RESERVED_18_MASK                                             0x00040000U
+
+/*ATO Analog Test Enable*/
+#undef DDR_PHY_DSGCR_ATOAE_DEFVAL 
+#undef DDR_PHY_DSGCR_ATOAE_SHIFT 
+#undef DDR_PHY_DSGCR_ATOAE_MASK 
+#define DDR_PHY_DSGCR_ATOAE_DEFVAL                                                 0x02A04101
+#define DDR_PHY_DSGCR_ATOAE_SHIFT                                                  17
+#define DDR_PHY_DSGCR_ATOAE_MASK                                                   0x00020000U
+
+/*DTO Output Enable*/
+#undef DDR_PHY_DSGCR_DTOOE_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOOE_SHIFT 
+#undef DDR_PHY_DSGCR_DTOOE_MASK 
+#define DDR_PHY_DSGCR_DTOOE_DEFVAL                                                 0x02A04101
+#define DDR_PHY_DSGCR_DTOOE_SHIFT                                                  16
+#define DDR_PHY_DSGCR_DTOOE_MASK                                                   0x00010000U
+
+/*DTO I/O Mode*/
+#undef DDR_PHY_DSGCR_DTOIOM_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOIOM_SHIFT 
+#undef DDR_PHY_DSGCR_DTOIOM_MASK 
+#define DDR_PHY_DSGCR_DTOIOM_DEFVAL                                                0x02A04101
+#define DDR_PHY_DSGCR_DTOIOM_SHIFT                                                 15
+#define DDR_PHY_DSGCR_DTOIOM_MASK                                                  0x00008000U
+
+/*DTO Power Down Receiver*/
+#undef DDR_PHY_DSGCR_DTOPDR_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOPDR_SHIFT 
+#undef DDR_PHY_DSGCR_DTOPDR_MASK 
+#define DDR_PHY_DSGCR_DTOPDR_DEFVAL                                                0x02A04101
+#define DDR_PHY_DSGCR_DTOPDR_SHIFT                                                 14
+#define DDR_PHY_DSGCR_DTOPDR_MASK                                                  0x00004000U
+
+/*Reserved. Return zeroes on reads*/
+#undef DDR_PHY_DSGCR_RESERVED_13_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_13_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_13_MASK 
+#define DDR_PHY_DSGCR_RESERVED_13_DEFVAL                                           0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_13_SHIFT                                            13
+#define DDR_PHY_DSGCR_RESERVED_13_MASK                                             0x00002000U
+
+/*DTO On-Die Termination*/
+#undef DDR_PHY_DSGCR_DTOODT_DEFVAL 
+#undef DDR_PHY_DSGCR_DTOODT_SHIFT 
+#undef DDR_PHY_DSGCR_DTOODT_MASK 
+#define DDR_PHY_DSGCR_DTOODT_DEFVAL                                                0x02A04101
+#define DDR_PHY_DSGCR_DTOODT_SHIFT                                                 12
+#define DDR_PHY_DSGCR_DTOODT_MASK                                                  0x00001000U
+
+/*PHY Update Acknowledge Delay*/
+#undef DDR_PHY_DSGCR_PUAD_DEFVAL 
+#undef DDR_PHY_DSGCR_PUAD_SHIFT 
+#undef DDR_PHY_DSGCR_PUAD_MASK 
+#define DDR_PHY_DSGCR_PUAD_DEFVAL                                                  0x02A04101
+#define DDR_PHY_DSGCR_PUAD_SHIFT                                                   6
+#define DDR_PHY_DSGCR_PUAD_MASK                                                    0x00000FC0U
+
+/*Controller Update Acknowledge Enable*/
+#undef DDR_PHY_DSGCR_CUAEN_DEFVAL 
+#undef DDR_PHY_DSGCR_CUAEN_SHIFT 
+#undef DDR_PHY_DSGCR_CUAEN_MASK 
+#define DDR_PHY_DSGCR_CUAEN_DEFVAL                                                 0x02A04101
+#define DDR_PHY_DSGCR_CUAEN_SHIFT                                                  5
+#define DDR_PHY_DSGCR_CUAEN_MASK                                                   0x00000020U
+
+/*Reserved. Return zeroes on reads*/
+#undef DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_4_3_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_4_3_MASK 
+#define DDR_PHY_DSGCR_RESERVED_4_3_DEFVAL                                          0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_4_3_SHIFT                                           3
+#define DDR_PHY_DSGCR_RESERVED_4_3_MASK                                            0x00000018U
+
+/*Controller Impedance Update Enable*/
+#undef DDR_PHY_DSGCR_CTLZUEN_DEFVAL 
+#undef DDR_PHY_DSGCR_CTLZUEN_SHIFT 
+#undef DDR_PHY_DSGCR_CTLZUEN_MASK 
+#define DDR_PHY_DSGCR_CTLZUEN_DEFVAL                                               0x02A04101
+#define DDR_PHY_DSGCR_CTLZUEN_SHIFT                                                2
+#define DDR_PHY_DSGCR_CTLZUEN_MASK                                                 0x00000004U
+
+/*Reserved. Return zeroes on reads*/
+#undef DDR_PHY_DSGCR_RESERVED_1_DEFVAL 
+#undef DDR_PHY_DSGCR_RESERVED_1_SHIFT 
+#undef DDR_PHY_DSGCR_RESERVED_1_MASK 
+#define DDR_PHY_DSGCR_RESERVED_1_DEFVAL                                            0x02A04101
+#define DDR_PHY_DSGCR_RESERVED_1_SHIFT                                             1
+#define DDR_PHY_DSGCR_RESERVED_1_MASK                                              0x00000002U
+
+/*PHY Update Request Enable*/
+#undef DDR_PHY_DSGCR_PUREN_DEFVAL 
+#undef DDR_PHY_DSGCR_PUREN_SHIFT 
+#undef DDR_PHY_DSGCR_PUREN_MASK 
+#define DDR_PHY_DSGCR_PUREN_DEFVAL                                                 0x02A04101
+#define DDR_PHY_DSGCR_PUREN_SHIFT                                                  0
+#define DDR_PHY_DSGCR_PUREN_MASK                                                   0x00000001U
+
+/*DDR4 Gear Down Timing.*/
+#undef DDR_PHY_DCR_GEARDN_DEFVAL 
+#undef DDR_PHY_DCR_GEARDN_SHIFT 
+#undef DDR_PHY_DCR_GEARDN_MASK 
+#define DDR_PHY_DCR_GEARDN_DEFVAL                                                  0x0000040D
+#define DDR_PHY_DCR_GEARDN_SHIFT                                                   31
+#define DDR_PHY_DCR_GEARDN_MASK                                                    0x80000000U
+
+/*Un-used Bank Group*/
+#undef DDR_PHY_DCR_UBG_DEFVAL 
+#undef DDR_PHY_DCR_UBG_SHIFT 
+#undef DDR_PHY_DCR_UBG_MASK 
+#define DDR_PHY_DCR_UBG_DEFVAL                                                     0x0000040D
+#define DDR_PHY_DCR_UBG_SHIFT                                                      30
+#define DDR_PHY_DCR_UBG_MASK                                                       0x40000000U
+
+/*Un-buffered DIMM Address Mirroring*/
+#undef DDR_PHY_DCR_UDIMM_DEFVAL 
+#undef DDR_PHY_DCR_UDIMM_SHIFT 
+#undef DDR_PHY_DCR_UDIMM_MASK 
+#define DDR_PHY_DCR_UDIMM_DEFVAL                                                   0x0000040D
+#define DDR_PHY_DCR_UDIMM_SHIFT                                                    29
+#define DDR_PHY_DCR_UDIMM_MASK                                                     0x20000000U
+
+/*DDR 2T Timing*/
+#undef DDR_PHY_DCR_DDR2T_DEFVAL 
+#undef DDR_PHY_DCR_DDR2T_SHIFT 
+#undef DDR_PHY_DCR_DDR2T_MASK 
+#define DDR_PHY_DCR_DDR2T_DEFVAL                                                   0x0000040D
+#define DDR_PHY_DCR_DDR2T_SHIFT                                                    28
+#define DDR_PHY_DCR_DDR2T_MASK                                                     0x10000000U
+
+/*No Simultaneous Rank Access*/
+#undef DDR_PHY_DCR_NOSRA_DEFVAL 
+#undef DDR_PHY_DCR_NOSRA_SHIFT 
+#undef DDR_PHY_DCR_NOSRA_MASK 
+#define DDR_PHY_DCR_NOSRA_DEFVAL                                                   0x0000040D
+#define DDR_PHY_DCR_NOSRA_SHIFT                                                    27
+#define DDR_PHY_DCR_NOSRA_MASK                                                     0x08000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DCR_RESERVED_26_18_DEFVAL 
+#undef DDR_PHY_DCR_RESERVED_26_18_SHIFT 
+#undef DDR_PHY_DCR_RESERVED_26_18_MASK 
+#define DDR_PHY_DCR_RESERVED_26_18_DEFVAL                                          0x0000040D
+#define DDR_PHY_DCR_RESERVED_26_18_SHIFT                                           18
+#define DDR_PHY_DCR_RESERVED_26_18_MASK                                            0x07FC0000U
+
+/*Byte Mask*/
+#undef DDR_PHY_DCR_BYTEMASK_DEFVAL 
+#undef DDR_PHY_DCR_BYTEMASK_SHIFT 
+#undef DDR_PHY_DCR_BYTEMASK_MASK 
+#define DDR_PHY_DCR_BYTEMASK_DEFVAL                                                0x0000040D
+#define DDR_PHY_DCR_BYTEMASK_SHIFT                                                 10
+#define DDR_PHY_DCR_BYTEMASK_MASK                                                  0x0003FC00U
+
+/*DDR Type*/
+#undef DDR_PHY_DCR_DDRTYPE_DEFVAL 
+#undef DDR_PHY_DCR_DDRTYPE_SHIFT 
+#undef DDR_PHY_DCR_DDRTYPE_MASK 
+#define DDR_PHY_DCR_DDRTYPE_DEFVAL                                                 0x0000040D
+#define DDR_PHY_DCR_DDRTYPE_SHIFT                                                  8
+#define DDR_PHY_DCR_DDRTYPE_MASK                                                   0x00000300U
+
+/*Multi-Purpose Register (MPR) DQ (DDR3 Only)*/
+#undef DDR_PHY_DCR_MPRDQ_DEFVAL 
+#undef DDR_PHY_DCR_MPRDQ_SHIFT 
+#undef DDR_PHY_DCR_MPRDQ_MASK 
+#define DDR_PHY_DCR_MPRDQ_DEFVAL                                                   0x0000040D
+#define DDR_PHY_DCR_MPRDQ_SHIFT                                                    7
+#define DDR_PHY_DCR_MPRDQ_MASK                                                     0x00000080U
+
+/*Primary DQ (DDR3 Only)*/
+#undef DDR_PHY_DCR_PDQ_DEFVAL 
+#undef DDR_PHY_DCR_PDQ_SHIFT 
+#undef DDR_PHY_DCR_PDQ_MASK 
+#define DDR_PHY_DCR_PDQ_DEFVAL                                                     0x0000040D
+#define DDR_PHY_DCR_PDQ_SHIFT                                                      4
+#define DDR_PHY_DCR_PDQ_MASK                                                       0x00000070U
+
+/*DDR 8-Bank*/
+#undef DDR_PHY_DCR_DDR8BNK_DEFVAL 
+#undef DDR_PHY_DCR_DDR8BNK_SHIFT 
+#undef DDR_PHY_DCR_DDR8BNK_MASK 
+#define DDR_PHY_DCR_DDR8BNK_DEFVAL                                                 0x0000040D
+#define DDR_PHY_DCR_DDR8BNK_SHIFT                                                  3
+#define DDR_PHY_DCR_DDR8BNK_MASK                                                   0x00000008U
+
+/*DDR Mode*/
+#undef DDR_PHY_DCR_DDRMD_DEFVAL 
+#undef DDR_PHY_DCR_DDRMD_SHIFT 
+#undef DDR_PHY_DCR_DDRMD_MASK 
+#define DDR_PHY_DCR_DDRMD_DEFVAL                                                   0x0000040D
+#define DDR_PHY_DCR_DDRMD_SHIFT                                                    0
+#define DDR_PHY_DCR_DDRMD_MASK                                                     0x00000007U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_31_29_MASK 
+#define DDR_PHY_DTPR0_RESERVED_31_29_DEFVAL                                        0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_31_29_SHIFT                                         29
+#define DDR_PHY_DTPR0_RESERVED_31_29_MASK                                          0xE0000000U
+
+/*Activate to activate command delay (different banks)*/
+#undef DDR_PHY_DTPR0_TRRD_DEFVAL 
+#undef DDR_PHY_DTPR0_TRRD_SHIFT 
+#undef DDR_PHY_DTPR0_TRRD_MASK 
+#define DDR_PHY_DTPR0_TRRD_DEFVAL                                                  0x105A2D08
+#define DDR_PHY_DTPR0_TRRD_SHIFT                                                   24
+#define DDR_PHY_DTPR0_TRRD_MASK                                                    0x1F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR0_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_23_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_23_MASK 
+#define DDR_PHY_DTPR0_RESERVED_23_DEFVAL                                           0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_23_SHIFT                                            23
+#define DDR_PHY_DTPR0_RESERVED_23_MASK                                             0x00800000U
+
+/*Activate to precharge command delay*/
+#undef DDR_PHY_DTPR0_TRAS_DEFVAL 
+#undef DDR_PHY_DTPR0_TRAS_SHIFT 
+#undef DDR_PHY_DTPR0_TRAS_MASK 
+#define DDR_PHY_DTPR0_TRAS_DEFVAL                                                  0x105A2D08
+#define DDR_PHY_DTPR0_TRAS_SHIFT                                                   16
+#define DDR_PHY_DTPR0_TRAS_MASK                                                    0x007F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR0_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_15_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_15_MASK 
+#define DDR_PHY_DTPR0_RESERVED_15_DEFVAL                                           0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_15_SHIFT                                            15
+#define DDR_PHY_DTPR0_RESERVED_15_MASK                                             0x00008000U
+
+/*Precharge command period*/
+#undef DDR_PHY_DTPR0_TRP_DEFVAL 
+#undef DDR_PHY_DTPR0_TRP_SHIFT 
+#undef DDR_PHY_DTPR0_TRP_MASK 
+#define DDR_PHY_DTPR0_TRP_DEFVAL                                                   0x105A2D08
+#define DDR_PHY_DTPR0_TRP_SHIFT                                                    8
+#define DDR_PHY_DTPR0_TRP_MASK                                                     0x00007F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR0_RESERVED_7_5_DEFVAL                                          0x105A2D08
+#define DDR_PHY_DTPR0_RESERVED_7_5_SHIFT                                           5
+#define DDR_PHY_DTPR0_RESERVED_7_5_MASK                                            0x000000E0U
+
+/*Internal read to precharge command delay*/
+#undef DDR_PHY_DTPR0_TRTP_DEFVAL 
+#undef DDR_PHY_DTPR0_TRTP_SHIFT 
+#undef DDR_PHY_DTPR0_TRTP_MASK 
+#define DDR_PHY_DTPR0_TRTP_DEFVAL                                                  0x105A2D08
+#define DDR_PHY_DTPR0_TRTP_SHIFT                                                   0
+#define DDR_PHY_DTPR0_TRTP_MASK                                                    0x0000001FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR1_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_31_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_31_MASK 
+#define DDR_PHY_DTPR1_RESERVED_31_DEFVAL                                           0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_31_SHIFT                                            31
+#define DDR_PHY_DTPR1_RESERVED_31_MASK                                             0x80000000U
+
+/*Minimum delay from when write leveling mode is programmed to the first DQS/DQS# rising edge.*/
+#undef DDR_PHY_DTPR1_TWLMRD_DEFVAL 
+#undef DDR_PHY_DTPR1_TWLMRD_SHIFT 
+#undef DDR_PHY_DTPR1_TWLMRD_MASK 
+#define DDR_PHY_DTPR1_TWLMRD_DEFVAL                                                0x5656041E
+#define DDR_PHY_DTPR1_TWLMRD_SHIFT                                                 24
+#define DDR_PHY_DTPR1_TWLMRD_MASK                                                  0x7F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR1_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_23_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_23_MASK 
+#define DDR_PHY_DTPR1_RESERVED_23_DEFVAL                                           0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_23_SHIFT                                            23
+#define DDR_PHY_DTPR1_RESERVED_23_MASK                                             0x00800000U
+
+/*4-bank activate period*/
+#undef DDR_PHY_DTPR1_TFAW_DEFVAL 
+#undef DDR_PHY_DTPR1_TFAW_SHIFT 
+#undef DDR_PHY_DTPR1_TFAW_MASK 
+#define DDR_PHY_DTPR1_TFAW_DEFVAL                                                  0x5656041E
+#define DDR_PHY_DTPR1_TFAW_SHIFT                                                   16
+#define DDR_PHY_DTPR1_TFAW_MASK                                                    0x007F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_15_11_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_15_11_MASK 
+#define DDR_PHY_DTPR1_RESERVED_15_11_DEFVAL                                        0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_15_11_SHIFT                                         11
+#define DDR_PHY_DTPR1_RESERVED_15_11_MASK                                          0x0000F800U
+
+/*Load mode update delay (DDR4 and DDR3 only)*/
+#undef DDR_PHY_DTPR1_TMOD_DEFVAL 
+#undef DDR_PHY_DTPR1_TMOD_SHIFT 
+#undef DDR_PHY_DTPR1_TMOD_MASK 
+#define DDR_PHY_DTPR1_TMOD_DEFVAL                                                  0x5656041E
+#define DDR_PHY_DTPR1_TMOD_SHIFT                                                   8
+#define DDR_PHY_DTPR1_TMOD_MASK                                                    0x00000700U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR1_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR1_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR1_RESERVED_7_5_DEFVAL                                          0x5656041E
+#define DDR_PHY_DTPR1_RESERVED_7_5_SHIFT                                           5
+#define DDR_PHY_DTPR1_RESERVED_7_5_MASK                                            0x000000E0U
+
+/*Load mode cycle time*/
+#undef DDR_PHY_DTPR1_TMRD_DEFVAL 
+#undef DDR_PHY_DTPR1_TMRD_SHIFT 
+#undef DDR_PHY_DTPR1_TMRD_MASK 
+#define DDR_PHY_DTPR1_TMRD_DEFVAL                                                  0x5656041E
+#define DDR_PHY_DTPR1_TMRD_SHIFT                                                   0
+#define DDR_PHY_DTPR1_TMRD_MASK                                                    0x0000001FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_31_29_MASK 
+#define DDR_PHY_DTPR2_RESERVED_31_29_DEFVAL                                        0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_31_29_SHIFT                                         29
+#define DDR_PHY_DTPR2_RESERVED_31_29_MASK                                          0xE0000000U
+
+/*Read to Write command delay. Valid values are*/
+#undef DDR_PHY_DTPR2_TRTW_DEFVAL 
+#undef DDR_PHY_DTPR2_TRTW_SHIFT 
+#undef DDR_PHY_DTPR2_TRTW_MASK 
+#define DDR_PHY_DTPR2_TRTW_DEFVAL                                                  0x000B01D0
+#define DDR_PHY_DTPR2_TRTW_SHIFT                                                   28
+#define DDR_PHY_DTPR2_TRTW_MASK                                                    0x10000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_27_25_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_27_25_MASK 
+#define DDR_PHY_DTPR2_RESERVED_27_25_DEFVAL                                        0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_27_25_SHIFT                                         25
+#define DDR_PHY_DTPR2_RESERVED_27_25_MASK                                          0x0E000000U
+
+/*Read to ODT delay (DDR3 only)*/
+#undef DDR_PHY_DTPR2_TRTODT_DEFVAL 
+#undef DDR_PHY_DTPR2_TRTODT_SHIFT 
+#undef DDR_PHY_DTPR2_TRTODT_MASK 
+#define DDR_PHY_DTPR2_TRTODT_DEFVAL                                                0x000B01D0
+#define DDR_PHY_DTPR2_TRTODT_SHIFT                                                 24
+#define DDR_PHY_DTPR2_TRTODT_MASK                                                  0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_23_20_MASK 
+#define DDR_PHY_DTPR2_RESERVED_23_20_DEFVAL                                        0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_23_20_SHIFT                                         20
+#define DDR_PHY_DTPR2_RESERVED_23_20_MASK                                          0x00F00000U
+
+/*CKE minimum pulse width*/
+#undef DDR_PHY_DTPR2_TCKE_DEFVAL 
+#undef DDR_PHY_DTPR2_TCKE_SHIFT 
+#undef DDR_PHY_DTPR2_TCKE_MASK 
+#define DDR_PHY_DTPR2_TCKE_DEFVAL                                                  0x000B01D0
+#define DDR_PHY_DTPR2_TCKE_SHIFT                                                   16
+#define DDR_PHY_DTPR2_TCKE_MASK                                                    0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL 
+#undef DDR_PHY_DTPR2_RESERVED_15_10_SHIFT 
+#undef DDR_PHY_DTPR2_RESERVED_15_10_MASK 
+#define DDR_PHY_DTPR2_RESERVED_15_10_DEFVAL                                        0x000B01D0
+#define DDR_PHY_DTPR2_RESERVED_15_10_SHIFT                                         10
+#define DDR_PHY_DTPR2_RESERVED_15_10_MASK                                          0x0000FC00U
+
+/*Self refresh exit delay*/
+#undef DDR_PHY_DTPR2_TXS_DEFVAL 
+#undef DDR_PHY_DTPR2_TXS_SHIFT 
+#undef DDR_PHY_DTPR2_TXS_MASK 
+#define DDR_PHY_DTPR2_TXS_DEFVAL                                                   0x000B01D0
+#define DDR_PHY_DTPR2_TXS_SHIFT                                                    0
+#define DDR_PHY_DTPR2_TXS_MASK                                                     0x000003FFU
+
+/*ODT turn-off delay extension*/
+#undef DDR_PHY_DTPR3_TOFDX_DEFVAL 
+#undef DDR_PHY_DTPR3_TOFDX_SHIFT 
+#undef DDR_PHY_DTPR3_TOFDX_MASK 
+#define DDR_PHY_DTPR3_TOFDX_DEFVAL                                                 0x02000804
+#define DDR_PHY_DTPR3_TOFDX_SHIFT                                                  29
+#define DDR_PHY_DTPR3_TOFDX_MASK                                                   0xE0000000U
+
+/*Read to read and write to write command delay*/
+#undef DDR_PHY_DTPR3_TCCD_DEFVAL 
+#undef DDR_PHY_DTPR3_TCCD_SHIFT 
+#undef DDR_PHY_DTPR3_TCCD_MASK 
+#define DDR_PHY_DTPR3_TCCD_DEFVAL                                                  0x02000804
+#define DDR_PHY_DTPR3_TCCD_SHIFT                                                   26
+#define DDR_PHY_DTPR3_TCCD_MASK                                                    0x1C000000U
+
+/*DLL locking time*/
+#undef DDR_PHY_DTPR3_TDLLK_DEFVAL 
+#undef DDR_PHY_DTPR3_TDLLK_SHIFT 
+#undef DDR_PHY_DTPR3_TDLLK_MASK 
+#define DDR_PHY_DTPR3_TDLLK_DEFVAL                                                 0x02000804
+#define DDR_PHY_DTPR3_TDLLK_SHIFT                                                  16
+#define DDR_PHY_DTPR3_TDLLK_MASK                                                   0x03FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL 
+#undef DDR_PHY_DTPR3_RESERVED_15_12_SHIFT 
+#undef DDR_PHY_DTPR3_RESERVED_15_12_MASK 
+#define DDR_PHY_DTPR3_RESERVED_15_12_DEFVAL                                        0x02000804
+#define DDR_PHY_DTPR3_RESERVED_15_12_SHIFT                                         12
+#define DDR_PHY_DTPR3_RESERVED_15_12_MASK                                          0x0000F000U
+
+/*Maximum DQS output access time from CK/CK# (LPDDR2/3 only)*/
+#undef DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL 
+#undef DDR_PHY_DTPR3_TDQSCKMAX_SHIFT 
+#undef DDR_PHY_DTPR3_TDQSCKMAX_MASK 
+#define DDR_PHY_DTPR3_TDQSCKMAX_DEFVAL                                             0x02000804
+#define DDR_PHY_DTPR3_TDQSCKMAX_SHIFT                                              8
+#define DDR_PHY_DTPR3_TDQSCKMAX_MASK                                               0x00000F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL 
+#undef DDR_PHY_DTPR3_RESERVED_7_3_SHIFT 
+#undef DDR_PHY_DTPR3_RESERVED_7_3_MASK 
+#define DDR_PHY_DTPR3_RESERVED_7_3_DEFVAL                                          0x02000804
+#define DDR_PHY_DTPR3_RESERVED_7_3_SHIFT                                           3
+#define DDR_PHY_DTPR3_RESERVED_7_3_MASK                                            0x000000F8U
+
+/*DQS output access time from CK/CK# (LPDDR2/3 only)*/
+#undef DDR_PHY_DTPR3_TDQSCK_DEFVAL 
+#undef DDR_PHY_DTPR3_TDQSCK_SHIFT 
+#undef DDR_PHY_DTPR3_TDQSCK_MASK 
+#define DDR_PHY_DTPR3_TDQSCK_DEFVAL                                                0x02000804
+#define DDR_PHY_DTPR3_TDQSCK_SHIFT                                                 0
+#define DDR_PHY_DTPR3_TDQSCK_MASK                                                  0x00000007U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_31_30_MASK 
+#define DDR_PHY_DTPR4_RESERVED_31_30_DEFVAL                                        0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_31_30_SHIFT                                         30
+#define DDR_PHY_DTPR4_RESERVED_31_30_MASK                                          0xC0000000U
+
+/*ODT turn-on/turn-off delays (DDR2 only)*/
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL 
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT 
+#undef DDR_PHY_DTPR4_TAOND_TAOFD_MASK 
+#define DDR_PHY_DTPR4_TAOND_TAOFD_DEFVAL                                           0x01C02B10
+#define DDR_PHY_DTPR4_TAOND_TAOFD_SHIFT                                            28
+#define DDR_PHY_DTPR4_TAOND_TAOFD_MASK                                             0x30000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_27_26_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_27_26_MASK 
+#define DDR_PHY_DTPR4_RESERVED_27_26_DEFVAL                                        0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_27_26_SHIFT                                         26
+#define DDR_PHY_DTPR4_RESERVED_27_26_MASK                                          0x0C000000U
+
+/*Refresh-to-Refresh*/
+#undef DDR_PHY_DTPR4_TRFC_DEFVAL 
+#undef DDR_PHY_DTPR4_TRFC_SHIFT 
+#undef DDR_PHY_DTPR4_TRFC_MASK 
+#define DDR_PHY_DTPR4_TRFC_DEFVAL                                                  0x01C02B10
+#define DDR_PHY_DTPR4_TRFC_SHIFT                                                   16
+#define DDR_PHY_DTPR4_TRFC_MASK                                                    0x03FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_15_14_MASK 
+#define DDR_PHY_DTPR4_RESERVED_15_14_DEFVAL                                        0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_15_14_SHIFT                                         14
+#define DDR_PHY_DTPR4_RESERVED_15_14_MASK                                          0x0000C000U
+
+/*Write leveling output delay*/
+#undef DDR_PHY_DTPR4_TWLO_DEFVAL 
+#undef DDR_PHY_DTPR4_TWLO_SHIFT 
+#undef DDR_PHY_DTPR4_TWLO_MASK 
+#define DDR_PHY_DTPR4_TWLO_DEFVAL                                                  0x01C02B10
+#define DDR_PHY_DTPR4_TWLO_SHIFT                                                   8
+#define DDR_PHY_DTPR4_TWLO_MASK                                                    0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR4_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR4_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR4_RESERVED_7_5_DEFVAL                                          0x01C02B10
+#define DDR_PHY_DTPR4_RESERVED_7_5_SHIFT                                           5
+#define DDR_PHY_DTPR4_RESERVED_7_5_MASK                                            0x000000E0U
+
+/*Power down exit delay*/
+#undef DDR_PHY_DTPR4_TXP_DEFVAL 
+#undef DDR_PHY_DTPR4_TXP_SHIFT 
+#undef DDR_PHY_DTPR4_TXP_MASK 
+#define DDR_PHY_DTPR4_TXP_DEFVAL                                                   0x01C02B10
+#define DDR_PHY_DTPR4_TXP_SHIFT                                                    0
+#define DDR_PHY_DTPR4_TXP_MASK                                                     0x0000001FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DTPR5_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DTPR5_RESERVED_31_24_MASK 
+#define DDR_PHY_DTPR5_RESERVED_31_24_DEFVAL                                        0x00872716
+#define DDR_PHY_DTPR5_RESERVED_31_24_SHIFT                                         24
+#define DDR_PHY_DTPR5_RESERVED_31_24_MASK                                          0xFF000000U
+
+/*Activate to activate command delay (same bank)*/
+#undef DDR_PHY_DTPR5_TRC_DEFVAL 
+#undef DDR_PHY_DTPR5_TRC_SHIFT 
+#undef DDR_PHY_DTPR5_TRC_MASK 
+#define DDR_PHY_DTPR5_TRC_DEFVAL                                                   0x00872716
+#define DDR_PHY_DTPR5_TRC_SHIFT                                                    16
+#define DDR_PHY_DTPR5_TRC_MASK                                                     0x00FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DTPR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DTPR5_RESERVED_15_MASK 
+#define DDR_PHY_DTPR5_RESERVED_15_DEFVAL                                           0x00872716
+#define DDR_PHY_DTPR5_RESERVED_15_SHIFT                                            15
+#define DDR_PHY_DTPR5_RESERVED_15_MASK                                             0x00008000U
+
+/*Activate to read or write delay*/
+#undef DDR_PHY_DTPR5_TRCD_DEFVAL 
+#undef DDR_PHY_DTPR5_TRCD_SHIFT 
+#undef DDR_PHY_DTPR5_TRCD_MASK 
+#define DDR_PHY_DTPR5_TRCD_DEFVAL                                                  0x00872716
+#define DDR_PHY_DTPR5_TRCD_SHIFT                                                   8
+#define DDR_PHY_DTPR5_TRCD_MASK                                                    0x00007F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DTPR5_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DTPR5_RESERVED_7_5_MASK 
+#define DDR_PHY_DTPR5_RESERVED_7_5_DEFVAL                                          0x00872716
+#define DDR_PHY_DTPR5_RESERVED_7_5_SHIFT                                           5
+#define DDR_PHY_DTPR5_RESERVED_7_5_MASK                                            0x000000E0U
+
+/*Internal write to read command delay*/
+#undef DDR_PHY_DTPR5_TWTR_DEFVAL 
+#undef DDR_PHY_DTPR5_TWTR_SHIFT 
+#undef DDR_PHY_DTPR5_TWTR_MASK 
+#define DDR_PHY_DTPR5_TWTR_DEFVAL                                                  0x00872716
+#define DDR_PHY_DTPR5_TWTR_SHIFT                                                   0
+#define DDR_PHY_DTPR5_TWTR_MASK                                                    0x0000001FU
+
+/*PUB Write Latency Enable*/
+#undef DDR_PHY_DTPR6_PUBWLEN_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBWLEN_SHIFT 
+#undef DDR_PHY_DTPR6_PUBWLEN_MASK 
+#define DDR_PHY_DTPR6_PUBWLEN_DEFVAL                                               0x00000505
+#define DDR_PHY_DTPR6_PUBWLEN_SHIFT                                                31
+#define DDR_PHY_DTPR6_PUBWLEN_MASK                                                 0x80000000U
+
+/*PUB Read Latency Enable*/
+#undef DDR_PHY_DTPR6_PUBRLEN_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBRLEN_SHIFT 
+#undef DDR_PHY_DTPR6_PUBRLEN_MASK 
+#define DDR_PHY_DTPR6_PUBRLEN_DEFVAL                                               0x00000505
+#define DDR_PHY_DTPR6_PUBRLEN_SHIFT                                                30
+#define DDR_PHY_DTPR6_PUBRLEN_MASK                                                 0x40000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL 
+#undef DDR_PHY_DTPR6_RESERVED_29_14_SHIFT 
+#undef DDR_PHY_DTPR6_RESERVED_29_14_MASK 
+#define DDR_PHY_DTPR6_RESERVED_29_14_DEFVAL                                        0x00000505
+#define DDR_PHY_DTPR6_RESERVED_29_14_SHIFT                                         14
+#define DDR_PHY_DTPR6_RESERVED_29_14_MASK                                          0x3FFFC000U
+
+/*Write Latency*/
+#undef DDR_PHY_DTPR6_PUBWL_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBWL_SHIFT 
+#undef DDR_PHY_DTPR6_PUBWL_MASK 
+#define DDR_PHY_DTPR6_PUBWL_DEFVAL                                                 0x00000505
+#define DDR_PHY_DTPR6_PUBWL_SHIFT                                                  8
+#define DDR_PHY_DTPR6_PUBWL_MASK                                                   0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DTPR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DTPR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DTPR6_RESERVED_7_6_DEFVAL                                          0x00000505
+#define DDR_PHY_DTPR6_RESERVED_7_6_SHIFT                                           6
+#define DDR_PHY_DTPR6_RESERVED_7_6_MASK                                            0x000000C0U
+
+/*Read Latency*/
+#undef DDR_PHY_DTPR6_PUBRL_DEFVAL 
+#undef DDR_PHY_DTPR6_PUBRL_SHIFT 
+#undef DDR_PHY_DTPR6_PUBRL_MASK 
+#define DDR_PHY_DTPR6_PUBRL_DEFVAL                                                 0x00000505
+#define DDR_PHY_DTPR6_PUBRL_SHIFT                                                  0
+#define DDR_PHY_DTPR6_PUBRL_MASK                                                   0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_31_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_31_DEFVAL                                       0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_31_SHIFT                                        31
+#define DDR_PHY_RDIMMGCR0_RESERVED_31_MASK                                         0x80000000U
+
+/*RDMIMM Quad CS Enable*/
+#undef DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_QCSEN_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_QCSEN_MASK 
+#define DDR_PHY_RDIMMGCR0_QCSEN_DEFVAL                                             0x08400020
+#define DDR_PHY_RDIMMGCR0_QCSEN_SHIFT                                              30
+#define DDR_PHY_RDIMMGCR0_QCSEN_MASK                                               0x40000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_DEFVAL                                    0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_SHIFT                                     28
+#define DDR_PHY_RDIMMGCR0_RESERVED_29_28_MASK                                      0x30000000U
+
+/*RDIMM Outputs I/O Mode*/
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK 
+#define DDR_PHY_RDIMMGCR0_RDIMMIOM_DEFVAL                                          0x08400020
+#define DDR_PHY_RDIMMGCR0_RDIMMIOM_SHIFT                                           27
+#define DDR_PHY_RDIMMGCR0_RDIMMIOM_MASK                                            0x08000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_DEFVAL                                    0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_SHIFT                                     24
+#define DDR_PHY_RDIMMGCR0_RESERVED_26_24_MASK                                      0x07000000U
+
+/*ERROUT# Output Enable*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTOE_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTOE_DEFVAL                                          0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTOE_SHIFT                                           23
+#define DDR_PHY_RDIMMGCR0_ERROUTOE_MASK                                            0x00800000U
+
+/*ERROUT# I/O Mode*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTIOM_DEFVAL                                         0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTIOM_SHIFT                                          22
+#define DDR_PHY_RDIMMGCR0_ERROUTIOM_MASK                                           0x00400000U
+
+/*ERROUT# Power Down Receiver*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTPDR_DEFVAL                                         0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTPDR_SHIFT                                          21
+#define DDR_PHY_RDIMMGCR0_ERROUTPDR_MASK                                           0x00200000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_20_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_20_DEFVAL                                       0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_20_SHIFT                                        20
+#define DDR_PHY_RDIMMGCR0_RESERVED_20_MASK                                         0x00100000U
+
+/*ERROUT# On-Die Termination*/
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERROUTODT_MASK 
+#define DDR_PHY_RDIMMGCR0_ERROUTODT_DEFVAL                                         0x08400020
+#define DDR_PHY_RDIMMGCR0_ERROUTODT_SHIFT                                          19
+#define DDR_PHY_RDIMMGCR0_ERROUTODT_MASK                                           0x00080000U
+
+/*Load Reduced DIMM*/
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_LRDIMM_MASK 
+#define DDR_PHY_RDIMMGCR0_LRDIMM_DEFVAL                                            0x08400020
+#define DDR_PHY_RDIMMGCR0_LRDIMM_SHIFT                                             18
+#define DDR_PHY_RDIMMGCR0_LRDIMM_MASK                                              0x00040000U
+
+/*PAR_IN I/O Mode*/
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_PARINIOM_MASK 
+#define DDR_PHY_RDIMMGCR0_PARINIOM_DEFVAL                                          0x08400020
+#define DDR_PHY_RDIMMGCR0_PARINIOM_SHIFT                                           17
+#define DDR_PHY_RDIMMGCR0_PARINIOM_MASK                                            0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_DEFVAL                                     0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_SHIFT                                      8
+#define DDR_PHY_RDIMMGCR0_RESERVED_16_8_MASK                                       0x0001FF00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK 
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_DEFVAL                                     0x08400020
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_SHIFT                                      6
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_RSVD_MASK                                       0x000000C0U
+
+/*Rank Mirror Enable.*/
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RNKMRREN_MASK 
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_DEFVAL                                          0x08400020
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_SHIFT                                           4
+#define DDR_PHY_RDIMMGCR0_RNKMRREN_MASK                                            0x00000030U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RESERVED_3_MASK 
+#define DDR_PHY_RDIMMGCR0_RESERVED_3_DEFVAL                                        0x08400020
+#define DDR_PHY_RDIMMGCR0_RESERVED_3_SHIFT                                         3
+#define DDR_PHY_RDIMMGCR0_RESERVED_3_MASK                                          0x00000008U
+
+/*Stop on Parity Error*/
+#undef DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_SOPERR_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_SOPERR_MASK 
+#define DDR_PHY_RDIMMGCR0_SOPERR_DEFVAL                                            0x08400020
+#define DDR_PHY_RDIMMGCR0_SOPERR_SHIFT                                             2
+#define DDR_PHY_RDIMMGCR0_SOPERR_MASK                                              0x00000004U
+
+/*Parity Error No Registering*/
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_ERRNOREG_MASK 
+#define DDR_PHY_RDIMMGCR0_ERRNOREG_DEFVAL                                          0x08400020
+#define DDR_PHY_RDIMMGCR0_ERRNOREG_SHIFT                                           1
+#define DDR_PHY_RDIMMGCR0_ERRNOREG_MASK                                            0x00000002U
+
+/*Registered DIMM*/
+#undef DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL 
+#undef DDR_PHY_RDIMMGCR0_RDIMM_SHIFT 
+#undef DDR_PHY_RDIMMGCR0_RDIMM_MASK 
+#define DDR_PHY_RDIMMGCR0_RDIMM_DEFVAL                                             0x08400020
+#define DDR_PHY_RDIMMGCR0_RDIMM_SHIFT                                              0
+#define DDR_PHY_RDIMMGCR0_RDIMM_MASK                                               0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_DEFVAL                                    0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_SHIFT                                     29
+#define DDR_PHY_RDIMMGCR1_RESERVED_31_29_MASK                                      0xE0000000U
+
+/*Address [17] B-side Inversion Disable*/
+#undef DDR_PHY_RDIMMGCR1_A17BID_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_A17BID_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_A17BID_MASK 
+#define DDR_PHY_RDIMMGCR1_A17BID_DEFVAL                                            0x00000C80
+#define DDR_PHY_RDIMMGCR1_A17BID_SHIFT                                             28
+#define DDR_PHY_RDIMMGCR1_A17BID_MASK                                              0x10000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_27_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_27_DEFVAL                                       0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_27_SHIFT                                        27
+#define DDR_PHY_RDIMMGCR1_RESERVED_27_MASK                                         0x08000000U
+
+/*Command word to command word programming delay*/
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_DEFVAL                                         0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_SHIFT                                          24
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L2_MASK                                           0x07000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_23_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_23_DEFVAL                                       0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_23_SHIFT                                        23
+#define DDR_PHY_RDIMMGCR1_RESERVED_23_MASK                                         0x00800000U
+
+/*Command word to command word programming delay*/
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L_DEFVAL                                          0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L_SHIFT                                           20
+#define DDR_PHY_RDIMMGCR1_TBCMRD_L_MASK                                            0x00700000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_19_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_19_DEFVAL                                       0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_19_SHIFT                                        19
+#define DDR_PHY_RDIMMGCR1_RESERVED_19_MASK                                         0x00080000U
+
+/*Command word to command word programming delay*/
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCMRD_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCMRD_DEFVAL                                            0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCMRD_SHIFT                                             16
+#define DDR_PHY_RDIMMGCR1_TBCMRD_MASK                                              0x00070000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK 
+#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_DEFVAL                                    0x00000C80
+#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_SHIFT                                     14
+#define DDR_PHY_RDIMMGCR1_RESERVED_15_14_MASK                                      0x0000C000U
+
+/*Stabilization time*/
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL 
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT 
+#undef DDR_PHY_RDIMMGCR1_TBCSTAB_MASK 
+#define DDR_PHY_RDIMMGCR1_TBCSTAB_DEFVAL                                           0x00000C80
+#define DDR_PHY_RDIMMGCR1_TBCSTAB_SHIFT                                            0
+#define DDR_PHY_RDIMMGCR1_TBCSTAB_MASK                                             0x00003FFFU
+
+/*Control Word 15*/
+#undef DDR_PHY_RDIMMCR1_RC15_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC15_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC15_MASK 
+#define DDR_PHY_RDIMMCR1_RC15_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC15_SHIFT                                                28
+#define DDR_PHY_RDIMMCR1_RC15_MASK                                                 0xF0000000U
+
+/*DDR4 Control Word 14 (Parity Control Word) / DDR3 Reserved*/
+#undef DDR_PHY_RDIMMCR1_RC14_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC14_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC14_MASK 
+#define DDR_PHY_RDIMMCR1_RC14_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC14_SHIFT                                                24
+#define DDR_PHY_RDIMMCR1_RC14_MASK                                                 0x0F000000U
+
+/*DDR4 Control Word 13 (DIMM Configuration Control Word) / DDR3 Reserved*/
+#undef DDR_PHY_RDIMMCR1_RC13_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC13_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC13_MASK 
+#define DDR_PHY_RDIMMCR1_RC13_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC13_SHIFT                                                20
+#define DDR_PHY_RDIMMCR1_RC13_MASK                                                 0x00F00000U
+
+/*DDR4 Control Word 12 (Training Control Word) / DDR3 Reserved*/
+#undef DDR_PHY_RDIMMCR1_RC12_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC12_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC12_MASK 
+#define DDR_PHY_RDIMMCR1_RC12_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC12_SHIFT                                                16
+#define DDR_PHY_RDIMMCR1_RC12_MASK                                                 0x000F0000U
+
+/*DDR4 Control Word 11 (Operating Voltage VDD and VREFCA Source Control Word) / DDR3 Control Word 11 (Operation Voltage VDD Con
+		rol Word)*/
+#undef DDR_PHY_RDIMMCR1_RC11_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC11_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC11_MASK 
+#define DDR_PHY_RDIMMCR1_RC11_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC11_SHIFT                                                12
+#define DDR_PHY_RDIMMCR1_RC11_MASK                                                 0x0000F000U
+
+/*DDR4/DDR3 Control Word 10 (RDIMM Operating Speed Control Word)*/
+#undef DDR_PHY_RDIMMCR1_RC10_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC10_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC10_MASK 
+#define DDR_PHY_RDIMMCR1_RC10_DEFVAL                                               0x00000000
+#define DDR_PHY_RDIMMCR1_RC10_SHIFT                                                8
+#define DDR_PHY_RDIMMCR1_RC10_MASK                                                 0x00000F00U
+
+/*DDR4/DDR3 Control Word 9 (Power Saving Settings Control Word)*/
+#undef DDR_PHY_RDIMMCR1_RC9_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC9_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC9_MASK 
+#define DDR_PHY_RDIMMCR1_RC9_DEFVAL                                                0x00000000
+#define DDR_PHY_RDIMMCR1_RC9_SHIFT                                                 4
+#define DDR_PHY_RDIMMCR1_RC9_MASK                                                  0x000000F0U
+
+/*DDR4 Control Word 8 (Input/Output Configuration Control Word) / DDR3 Control Word 8 (Additional Input Bus Termination Setting
+		Control Word)*/
+#undef DDR_PHY_RDIMMCR1_RC8_DEFVAL 
+#undef DDR_PHY_RDIMMCR1_RC8_SHIFT 
+#undef DDR_PHY_RDIMMCR1_RC8_MASK 
+#define DDR_PHY_RDIMMCR1_RC8_DEFVAL                                                0x00000000
+#define DDR_PHY_RDIMMCR1_RC8_SHIFT                                                 0
+#define DDR_PHY_RDIMMCR1_RC8_MASK                                                  0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR0_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR0_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR0_RESERVED_31_8_MASK 
+#define DDR_PHY_MR0_RESERVED_31_8_DEFVAL                                           0x00000052
+#define DDR_PHY_MR0_RESERVED_31_8_SHIFT                                            8
+#define DDR_PHY_MR0_RESERVED_31_8_MASK                                             0xFFFFFF00U
+
+/*CA Terminating Rank*/
+#undef DDR_PHY_MR0_CATR_DEFVAL 
+#undef DDR_PHY_MR0_CATR_SHIFT 
+#undef DDR_PHY_MR0_CATR_MASK 
+#define DDR_PHY_MR0_CATR_DEFVAL                                                    0x00000052
+#define DDR_PHY_MR0_CATR_SHIFT                                                     7
+#define DDR_PHY_MR0_CATR_MASK                                                      0x00000080U
+
+/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR0_RSVD_6_5_DEFVAL 
+#undef DDR_PHY_MR0_RSVD_6_5_SHIFT 
+#undef DDR_PHY_MR0_RSVD_6_5_MASK 
+#define DDR_PHY_MR0_RSVD_6_5_DEFVAL                                                0x00000052
+#define DDR_PHY_MR0_RSVD_6_5_SHIFT                                                 5
+#define DDR_PHY_MR0_RSVD_6_5_MASK                                                  0x00000060U
+
+/*Built-in Self-Test for RZQ*/
+#undef DDR_PHY_MR0_RZQI_DEFVAL 
+#undef DDR_PHY_MR0_RZQI_SHIFT 
+#undef DDR_PHY_MR0_RZQI_MASK 
+#define DDR_PHY_MR0_RZQI_DEFVAL                                                    0x00000052
+#define DDR_PHY_MR0_RZQI_SHIFT                                                     3
+#define DDR_PHY_MR0_RZQI_MASK                                                      0x00000018U
+
+/*Reserved. These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR0_RSVD_2_0_DEFVAL 
+#undef DDR_PHY_MR0_RSVD_2_0_SHIFT 
+#undef DDR_PHY_MR0_RSVD_2_0_MASK 
+#define DDR_PHY_MR0_RSVD_2_0_DEFVAL                                                0x00000052
+#define DDR_PHY_MR0_RSVD_2_0_SHIFT                                                 0
+#define DDR_PHY_MR0_RSVD_2_0_MASK                                                  0x00000007U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR1_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR1_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR1_RESERVED_31_8_MASK 
+#define DDR_PHY_MR1_RESERVED_31_8_DEFVAL                                           0x00000004
+#define DDR_PHY_MR1_RESERVED_31_8_SHIFT                                            8
+#define DDR_PHY_MR1_RESERVED_31_8_MASK                                             0xFFFFFF00U
+
+/*Read Postamble Length*/
+#undef DDR_PHY_MR1_RDPST_DEFVAL 
+#undef DDR_PHY_MR1_RDPST_SHIFT 
+#undef DDR_PHY_MR1_RDPST_MASK 
+#define DDR_PHY_MR1_RDPST_DEFVAL                                                   0x00000004
+#define DDR_PHY_MR1_RDPST_SHIFT                                                    7
+#define DDR_PHY_MR1_RDPST_MASK                                                     0x00000080U
+
+/*Write-recovery for auto-precharge command*/
+#undef DDR_PHY_MR1_NWR_DEFVAL 
+#undef DDR_PHY_MR1_NWR_SHIFT 
+#undef DDR_PHY_MR1_NWR_MASK 
+#define DDR_PHY_MR1_NWR_DEFVAL                                                     0x00000004
+#define DDR_PHY_MR1_NWR_SHIFT                                                      4
+#define DDR_PHY_MR1_NWR_MASK                                                       0x00000070U
+
+/*Read Preamble Length*/
+#undef DDR_PHY_MR1_RDPRE_DEFVAL 
+#undef DDR_PHY_MR1_RDPRE_SHIFT 
+#undef DDR_PHY_MR1_RDPRE_MASK 
+#define DDR_PHY_MR1_RDPRE_DEFVAL                                                   0x00000004
+#define DDR_PHY_MR1_RDPRE_SHIFT                                                    3
+#define DDR_PHY_MR1_RDPRE_MASK                                                     0x00000008U
+
+/*Write Preamble Length*/
+#undef DDR_PHY_MR1_WRPRE_DEFVAL 
+#undef DDR_PHY_MR1_WRPRE_SHIFT 
+#undef DDR_PHY_MR1_WRPRE_MASK 
+#define DDR_PHY_MR1_WRPRE_DEFVAL                                                   0x00000004
+#define DDR_PHY_MR1_WRPRE_SHIFT                                                    2
+#define DDR_PHY_MR1_WRPRE_MASK                                                     0x00000004U
+
+/*Burst Length*/
+#undef DDR_PHY_MR1_BL_DEFVAL 
+#undef DDR_PHY_MR1_BL_SHIFT 
+#undef DDR_PHY_MR1_BL_MASK 
+#define DDR_PHY_MR1_BL_DEFVAL                                                      0x00000004
+#define DDR_PHY_MR1_BL_SHIFT                                                       0
+#define DDR_PHY_MR1_BL_MASK                                                        0x00000003U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR2_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR2_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR2_RESERVED_31_8_MASK 
+#define DDR_PHY_MR2_RESERVED_31_8_DEFVAL                                           0x00000000
+#define DDR_PHY_MR2_RESERVED_31_8_SHIFT                                            8
+#define DDR_PHY_MR2_RESERVED_31_8_MASK                                             0xFFFFFF00U
+
+/*Write Leveling*/
+#undef DDR_PHY_MR2_WRL_DEFVAL 
+#undef DDR_PHY_MR2_WRL_SHIFT 
+#undef DDR_PHY_MR2_WRL_MASK 
+#define DDR_PHY_MR2_WRL_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR2_WRL_SHIFT                                                      7
+#define DDR_PHY_MR2_WRL_MASK                                                       0x00000080U
+
+/*Write Latency Set*/
+#undef DDR_PHY_MR2_WLS_DEFVAL 
+#undef DDR_PHY_MR2_WLS_SHIFT 
+#undef DDR_PHY_MR2_WLS_MASK 
+#define DDR_PHY_MR2_WLS_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR2_WLS_SHIFT                                                      6
+#define DDR_PHY_MR2_WLS_MASK                                                       0x00000040U
+
+/*Write Latency*/
+#undef DDR_PHY_MR2_WL_DEFVAL 
+#undef DDR_PHY_MR2_WL_SHIFT 
+#undef DDR_PHY_MR2_WL_MASK 
+#define DDR_PHY_MR2_WL_DEFVAL                                                      0x00000000
+#define DDR_PHY_MR2_WL_SHIFT                                                       3
+#define DDR_PHY_MR2_WL_MASK                                                        0x00000038U
+
+/*Read Latency*/
+#undef DDR_PHY_MR2_RL_DEFVAL 
+#undef DDR_PHY_MR2_RL_SHIFT 
+#undef DDR_PHY_MR2_RL_MASK 
+#define DDR_PHY_MR2_RL_DEFVAL                                                      0x00000000
+#define DDR_PHY_MR2_RL_SHIFT                                                       0
+#define DDR_PHY_MR2_RL_MASK                                                        0x00000007U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR3_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR3_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR3_RESERVED_31_8_MASK 
+#define DDR_PHY_MR3_RESERVED_31_8_DEFVAL                                           0x00000031
+#define DDR_PHY_MR3_RESERVED_31_8_SHIFT                                            8
+#define DDR_PHY_MR3_RESERVED_31_8_MASK                                             0xFFFFFF00U
+
+/*DBI-Write Enable*/
+#undef DDR_PHY_MR3_DBIWR_DEFVAL 
+#undef DDR_PHY_MR3_DBIWR_SHIFT 
+#undef DDR_PHY_MR3_DBIWR_MASK 
+#define DDR_PHY_MR3_DBIWR_DEFVAL                                                   0x00000031
+#define DDR_PHY_MR3_DBIWR_SHIFT                                                    7
+#define DDR_PHY_MR3_DBIWR_MASK                                                     0x00000080U
+
+/*DBI-Read Enable*/
+#undef DDR_PHY_MR3_DBIRD_DEFVAL 
+#undef DDR_PHY_MR3_DBIRD_SHIFT 
+#undef DDR_PHY_MR3_DBIRD_MASK 
+#define DDR_PHY_MR3_DBIRD_DEFVAL                                                   0x00000031
+#define DDR_PHY_MR3_DBIRD_SHIFT                                                    6
+#define DDR_PHY_MR3_DBIRD_MASK                                                     0x00000040U
+
+/*Pull-down Drive Strength*/
+#undef DDR_PHY_MR3_PDDS_DEFVAL 
+#undef DDR_PHY_MR3_PDDS_SHIFT 
+#undef DDR_PHY_MR3_PDDS_MASK 
+#define DDR_PHY_MR3_PDDS_DEFVAL                                                    0x00000031
+#define DDR_PHY_MR3_PDDS_SHIFT                                                     3
+#define DDR_PHY_MR3_PDDS_MASK                                                      0x00000038U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR3_RSVD_DEFVAL 
+#undef DDR_PHY_MR3_RSVD_SHIFT 
+#undef DDR_PHY_MR3_RSVD_MASK 
+#define DDR_PHY_MR3_RSVD_DEFVAL                                                    0x00000031
+#define DDR_PHY_MR3_RSVD_SHIFT                                                     2
+#define DDR_PHY_MR3_RSVD_MASK                                                      0x00000004U
+
+/*Write Postamble Length*/
+#undef DDR_PHY_MR3_WRPST_DEFVAL 
+#undef DDR_PHY_MR3_WRPST_SHIFT 
+#undef DDR_PHY_MR3_WRPST_MASK 
+#define DDR_PHY_MR3_WRPST_DEFVAL                                                   0x00000031
+#define DDR_PHY_MR3_WRPST_SHIFT                                                    1
+#define DDR_PHY_MR3_WRPST_MASK                                                     0x00000002U
+
+/*Pull-up Calibration Point*/
+#undef DDR_PHY_MR3_PUCAL_DEFVAL 
+#undef DDR_PHY_MR3_PUCAL_SHIFT 
+#undef DDR_PHY_MR3_PUCAL_MASK 
+#define DDR_PHY_MR3_PUCAL_DEFVAL                                                   0x00000031
+#define DDR_PHY_MR3_PUCAL_SHIFT                                                    0
+#define DDR_PHY_MR3_PUCAL_MASK                                                     0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR4_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_MR4_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_MR4_RESERVED_31_16_MASK 
+#define DDR_PHY_MR4_RESERVED_31_16_DEFVAL                                          0x00000000
+#define DDR_PHY_MR4_RESERVED_31_16_SHIFT                                           16
+#define DDR_PHY_MR4_RESERVED_31_16_MASK                                            0xFFFF0000U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR4_RSVD_15_13_DEFVAL 
+#undef DDR_PHY_MR4_RSVD_15_13_SHIFT 
+#undef DDR_PHY_MR4_RSVD_15_13_MASK 
+#define DDR_PHY_MR4_RSVD_15_13_DEFVAL                                              0x00000000
+#define DDR_PHY_MR4_RSVD_15_13_SHIFT                                               13
+#define DDR_PHY_MR4_RSVD_15_13_MASK                                                0x0000E000U
+
+/*Write Preamble*/
+#undef DDR_PHY_MR4_WRP_DEFVAL 
+#undef DDR_PHY_MR4_WRP_SHIFT 
+#undef DDR_PHY_MR4_WRP_MASK 
+#define DDR_PHY_MR4_WRP_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR4_WRP_SHIFT                                                      12
+#define DDR_PHY_MR4_WRP_MASK                                                       0x00001000U
+
+/*Read Preamble*/
+#undef DDR_PHY_MR4_RDP_DEFVAL 
+#undef DDR_PHY_MR4_RDP_SHIFT 
+#undef DDR_PHY_MR4_RDP_MASK 
+#define DDR_PHY_MR4_RDP_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR4_RDP_SHIFT                                                      11
+#define DDR_PHY_MR4_RDP_MASK                                                       0x00000800U
+
+/*Read Preamble Training Mode*/
+#undef DDR_PHY_MR4_RPTM_DEFVAL 
+#undef DDR_PHY_MR4_RPTM_SHIFT 
+#undef DDR_PHY_MR4_RPTM_MASK 
+#define DDR_PHY_MR4_RPTM_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR4_RPTM_SHIFT                                                     10
+#define DDR_PHY_MR4_RPTM_MASK                                                      0x00000400U
+
+/*Self Refresh Abort*/
+#undef DDR_PHY_MR4_SRA_DEFVAL 
+#undef DDR_PHY_MR4_SRA_SHIFT 
+#undef DDR_PHY_MR4_SRA_MASK 
+#define DDR_PHY_MR4_SRA_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR4_SRA_SHIFT                                                      9
+#define DDR_PHY_MR4_SRA_MASK                                                       0x00000200U
+
+/*CS to Command Latency Mode*/
+#undef DDR_PHY_MR4_CS2CMDL_DEFVAL 
+#undef DDR_PHY_MR4_CS2CMDL_SHIFT 
+#undef DDR_PHY_MR4_CS2CMDL_MASK 
+#define DDR_PHY_MR4_CS2CMDL_DEFVAL                                                 0x00000000
+#define DDR_PHY_MR4_CS2CMDL_SHIFT                                                  6
+#define DDR_PHY_MR4_CS2CMDL_MASK                                                   0x000001C0U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR4_RSVD1_DEFVAL 
+#undef DDR_PHY_MR4_RSVD1_SHIFT 
+#undef DDR_PHY_MR4_RSVD1_MASK 
+#define DDR_PHY_MR4_RSVD1_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR4_RSVD1_SHIFT                                                    5
+#define DDR_PHY_MR4_RSVD1_MASK                                                     0x00000020U
+
+/*Internal VREF Monitor*/
+#undef DDR_PHY_MR4_IVM_DEFVAL 
+#undef DDR_PHY_MR4_IVM_SHIFT 
+#undef DDR_PHY_MR4_IVM_MASK 
+#define DDR_PHY_MR4_IVM_DEFVAL                                                     0x00000000
+#define DDR_PHY_MR4_IVM_SHIFT                                                      4
+#define DDR_PHY_MR4_IVM_MASK                                                       0x00000010U
+
+/*Temperature Controlled Refresh Mode*/
+#undef DDR_PHY_MR4_TCRM_DEFVAL 
+#undef DDR_PHY_MR4_TCRM_SHIFT 
+#undef DDR_PHY_MR4_TCRM_MASK 
+#define DDR_PHY_MR4_TCRM_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR4_TCRM_SHIFT                                                     3
+#define DDR_PHY_MR4_TCRM_MASK                                                      0x00000008U
+
+/*Temperature Controlled Refresh Range*/
+#undef DDR_PHY_MR4_TCRR_DEFVAL 
+#undef DDR_PHY_MR4_TCRR_SHIFT 
+#undef DDR_PHY_MR4_TCRR_MASK 
+#define DDR_PHY_MR4_TCRR_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR4_TCRR_SHIFT                                                     2
+#define DDR_PHY_MR4_TCRR_MASK                                                      0x00000004U
+
+/*Maximum Power Down Mode*/
+#undef DDR_PHY_MR4_MPDM_DEFVAL 
+#undef DDR_PHY_MR4_MPDM_SHIFT 
+#undef DDR_PHY_MR4_MPDM_MASK 
+#define DDR_PHY_MR4_MPDM_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR4_MPDM_SHIFT                                                     1
+#define DDR_PHY_MR4_MPDM_MASK                                                      0x00000002U
+
+/*This is a JEDEC reserved bit and is recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR4_RSVD_0_DEFVAL 
+#undef DDR_PHY_MR4_RSVD_0_SHIFT 
+#undef DDR_PHY_MR4_RSVD_0_MASK 
+#define DDR_PHY_MR4_RSVD_0_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR4_RSVD_0_SHIFT                                                   0
+#define DDR_PHY_MR4_RSVD_0_MASK                                                    0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR5_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_MR5_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_MR5_RESERVED_31_16_MASK 
+#define DDR_PHY_MR5_RESERVED_31_16_DEFVAL                                          0x00000000
+#define DDR_PHY_MR5_RESERVED_31_16_SHIFT                                           16
+#define DDR_PHY_MR5_RESERVED_31_16_MASK                                            0xFFFF0000U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR5_RSVD_DEFVAL 
+#undef DDR_PHY_MR5_RSVD_SHIFT 
+#undef DDR_PHY_MR5_RSVD_MASK 
+#define DDR_PHY_MR5_RSVD_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR5_RSVD_SHIFT                                                     13
+#define DDR_PHY_MR5_RSVD_MASK                                                      0x0000E000U
+
+/*Read DBI*/
+#undef DDR_PHY_MR5_RDBI_DEFVAL 
+#undef DDR_PHY_MR5_RDBI_SHIFT 
+#undef DDR_PHY_MR5_RDBI_MASK 
+#define DDR_PHY_MR5_RDBI_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR5_RDBI_SHIFT                                                     12
+#define DDR_PHY_MR5_RDBI_MASK                                                      0x00001000U
+
+/*Write DBI*/
+#undef DDR_PHY_MR5_WDBI_DEFVAL 
+#undef DDR_PHY_MR5_WDBI_SHIFT 
+#undef DDR_PHY_MR5_WDBI_MASK 
+#define DDR_PHY_MR5_WDBI_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR5_WDBI_SHIFT                                                     11
+#define DDR_PHY_MR5_WDBI_MASK                                                      0x00000800U
+
+/*Data Mask*/
+#undef DDR_PHY_MR5_DM_DEFVAL 
+#undef DDR_PHY_MR5_DM_SHIFT 
+#undef DDR_PHY_MR5_DM_MASK 
+#define DDR_PHY_MR5_DM_DEFVAL                                                      0x00000000
+#define DDR_PHY_MR5_DM_SHIFT                                                       10
+#define DDR_PHY_MR5_DM_MASK                                                        0x00000400U
+
+/*CA Parity Persistent Error*/
+#undef DDR_PHY_MR5_CAPPE_DEFVAL 
+#undef DDR_PHY_MR5_CAPPE_SHIFT 
+#undef DDR_PHY_MR5_CAPPE_MASK 
+#define DDR_PHY_MR5_CAPPE_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR5_CAPPE_SHIFT                                                    9
+#define DDR_PHY_MR5_CAPPE_MASK                                                     0x00000200U
+
+/*RTT_PARK*/
+#undef DDR_PHY_MR5_RTTPARK_DEFVAL 
+#undef DDR_PHY_MR5_RTTPARK_SHIFT 
+#undef DDR_PHY_MR5_RTTPARK_MASK 
+#define DDR_PHY_MR5_RTTPARK_DEFVAL                                                 0x00000000
+#define DDR_PHY_MR5_RTTPARK_SHIFT                                                  6
+#define DDR_PHY_MR5_RTTPARK_MASK                                                   0x000001C0U
+
+/*ODT Input Buffer during Power Down mode*/
+#undef DDR_PHY_MR5_ODTIBPD_DEFVAL 
+#undef DDR_PHY_MR5_ODTIBPD_SHIFT 
+#undef DDR_PHY_MR5_ODTIBPD_MASK 
+#define DDR_PHY_MR5_ODTIBPD_DEFVAL                                                 0x00000000
+#define DDR_PHY_MR5_ODTIBPD_SHIFT                                                  5
+#define DDR_PHY_MR5_ODTIBPD_MASK                                                   0x00000020U
+
+/*C/A Parity Error Status*/
+#undef DDR_PHY_MR5_CAPES_DEFVAL 
+#undef DDR_PHY_MR5_CAPES_SHIFT 
+#undef DDR_PHY_MR5_CAPES_MASK 
+#define DDR_PHY_MR5_CAPES_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR5_CAPES_SHIFT                                                    4
+#define DDR_PHY_MR5_CAPES_MASK                                                     0x00000010U
+
+/*CRC Error Clear*/
+#undef DDR_PHY_MR5_CRCEC_DEFVAL 
+#undef DDR_PHY_MR5_CRCEC_SHIFT 
+#undef DDR_PHY_MR5_CRCEC_MASK 
+#define DDR_PHY_MR5_CRCEC_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR5_CRCEC_SHIFT                                                    3
+#define DDR_PHY_MR5_CRCEC_MASK                                                     0x00000008U
+
+/*C/A Parity Latency Mode*/
+#undef DDR_PHY_MR5_CAPM_DEFVAL 
+#undef DDR_PHY_MR5_CAPM_SHIFT 
+#undef DDR_PHY_MR5_CAPM_MASK 
+#define DDR_PHY_MR5_CAPM_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR5_CAPM_SHIFT                                                     0
+#define DDR_PHY_MR5_CAPM_MASK                                                      0x00000007U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR6_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_MR6_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_MR6_RESERVED_31_16_MASK 
+#define DDR_PHY_MR6_RESERVED_31_16_DEFVAL                                          0x00000000
+#define DDR_PHY_MR6_RESERVED_31_16_SHIFT                                           16
+#define DDR_PHY_MR6_RESERVED_31_16_MASK                                            0xFFFF0000U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR6_RSVD_15_13_DEFVAL 
+#undef DDR_PHY_MR6_RSVD_15_13_SHIFT 
+#undef DDR_PHY_MR6_RSVD_15_13_MASK 
+#define DDR_PHY_MR6_RSVD_15_13_DEFVAL                                              0x00000000
+#define DDR_PHY_MR6_RSVD_15_13_SHIFT                                               13
+#define DDR_PHY_MR6_RSVD_15_13_MASK                                                0x0000E000U
+
+/*CAS_n to CAS_n command delay for same bank group (tCCD_L)*/
+#undef DDR_PHY_MR6_TCCDL_DEFVAL 
+#undef DDR_PHY_MR6_TCCDL_SHIFT 
+#undef DDR_PHY_MR6_TCCDL_MASK 
+#define DDR_PHY_MR6_TCCDL_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR6_TCCDL_SHIFT                                                    10
+#define DDR_PHY_MR6_TCCDL_MASK                                                     0x00001C00U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR6_RSVD_9_8_DEFVAL 
+#undef DDR_PHY_MR6_RSVD_9_8_SHIFT 
+#undef DDR_PHY_MR6_RSVD_9_8_MASK 
+#define DDR_PHY_MR6_RSVD_9_8_DEFVAL                                                0x00000000
+#define DDR_PHY_MR6_RSVD_9_8_SHIFT                                                 8
+#define DDR_PHY_MR6_RSVD_9_8_MASK                                                  0x00000300U
+
+/*VrefDQ Training Enable*/
+#undef DDR_PHY_MR6_VDDQTEN_DEFVAL 
+#undef DDR_PHY_MR6_VDDQTEN_SHIFT 
+#undef DDR_PHY_MR6_VDDQTEN_MASK 
+#define DDR_PHY_MR6_VDDQTEN_DEFVAL                                                 0x00000000
+#define DDR_PHY_MR6_VDDQTEN_SHIFT                                                  7
+#define DDR_PHY_MR6_VDDQTEN_MASK                                                   0x00000080U
+
+/*VrefDQ Training Range*/
+#undef DDR_PHY_MR6_VDQTRG_DEFVAL 
+#undef DDR_PHY_MR6_VDQTRG_SHIFT 
+#undef DDR_PHY_MR6_VDQTRG_MASK 
+#define DDR_PHY_MR6_VDQTRG_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR6_VDQTRG_SHIFT                                                   6
+#define DDR_PHY_MR6_VDQTRG_MASK                                                    0x00000040U
+
+/*VrefDQ Training Values*/
+#undef DDR_PHY_MR6_VDQTVAL_DEFVAL 
+#undef DDR_PHY_MR6_VDQTVAL_SHIFT 
+#undef DDR_PHY_MR6_VDQTVAL_MASK 
+#define DDR_PHY_MR6_VDQTVAL_DEFVAL                                                 0x00000000
+#define DDR_PHY_MR6_VDQTVAL_SHIFT                                                  0
+#define DDR_PHY_MR6_VDQTVAL_MASK                                                   0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR11_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR11_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR11_RESERVED_31_8_MASK 
+#define DDR_PHY_MR11_RESERVED_31_8_DEFVAL                                          0x00000000
+#define DDR_PHY_MR11_RESERVED_31_8_SHIFT                                           8
+#define DDR_PHY_MR11_RESERVED_31_8_MASK                                            0xFFFFFF00U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR11_RSVD_DEFVAL 
+#undef DDR_PHY_MR11_RSVD_SHIFT 
+#undef DDR_PHY_MR11_RSVD_MASK 
+#define DDR_PHY_MR11_RSVD_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR11_RSVD_SHIFT                                                    3
+#define DDR_PHY_MR11_RSVD_MASK                                                     0x000000F8U
+
+/*Power Down Control*/
+#undef DDR_PHY_MR11_PDCTL_DEFVAL 
+#undef DDR_PHY_MR11_PDCTL_SHIFT 
+#undef DDR_PHY_MR11_PDCTL_MASK 
+#define DDR_PHY_MR11_PDCTL_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR11_PDCTL_SHIFT                                                   2
+#define DDR_PHY_MR11_PDCTL_MASK                                                    0x00000004U
+
+/*DQ Bus Receiver On-Die-Termination*/
+#undef DDR_PHY_MR11_DQODT_DEFVAL 
+#undef DDR_PHY_MR11_DQODT_SHIFT 
+#undef DDR_PHY_MR11_DQODT_MASK 
+#define DDR_PHY_MR11_DQODT_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR11_DQODT_SHIFT                                                   0
+#define DDR_PHY_MR11_DQODT_MASK                                                    0x00000003U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR12_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR12_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR12_RESERVED_31_8_MASK 
+#define DDR_PHY_MR12_RESERVED_31_8_DEFVAL                                          0x0000004D
+#define DDR_PHY_MR12_RESERVED_31_8_SHIFT                                           8
+#define DDR_PHY_MR12_RESERVED_31_8_MASK                                            0xFFFFFF00U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR12_RSVD_DEFVAL 
+#undef DDR_PHY_MR12_RSVD_SHIFT 
+#undef DDR_PHY_MR12_RSVD_MASK 
+#define DDR_PHY_MR12_RSVD_DEFVAL                                                   0x0000004D
+#define DDR_PHY_MR12_RSVD_SHIFT                                                    7
+#define DDR_PHY_MR12_RSVD_MASK                                                     0x00000080U
+
+/*VREF_CA Range Select.*/
+#undef DDR_PHY_MR12_VR_CA_DEFVAL 
+#undef DDR_PHY_MR12_VR_CA_SHIFT 
+#undef DDR_PHY_MR12_VR_CA_MASK 
+#define DDR_PHY_MR12_VR_CA_DEFVAL                                                  0x0000004D
+#define DDR_PHY_MR12_VR_CA_SHIFT                                                   6
+#define DDR_PHY_MR12_VR_CA_MASK                                                    0x00000040U
+
+/*Controls the VREF(ca) levels for Frequency-Set-Point[1:0].*/
+#undef DDR_PHY_MR12_VREF_CA_DEFVAL 
+#undef DDR_PHY_MR12_VREF_CA_SHIFT 
+#undef DDR_PHY_MR12_VREF_CA_MASK 
+#define DDR_PHY_MR12_VREF_CA_DEFVAL                                                0x0000004D
+#define DDR_PHY_MR12_VREF_CA_SHIFT                                                 0
+#define DDR_PHY_MR12_VREF_CA_MASK                                                  0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR13_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR13_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR13_RESERVED_31_8_MASK 
+#define DDR_PHY_MR13_RESERVED_31_8_DEFVAL                                          0x00000000
+#define DDR_PHY_MR13_RESERVED_31_8_SHIFT                                           8
+#define DDR_PHY_MR13_RESERVED_31_8_MASK                                            0xFFFFFF00U
+
+/*Frequency Set Point Operation Mode*/
+#undef DDR_PHY_MR13_FSPOP_DEFVAL 
+#undef DDR_PHY_MR13_FSPOP_SHIFT 
+#undef DDR_PHY_MR13_FSPOP_MASK 
+#define DDR_PHY_MR13_FSPOP_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR13_FSPOP_SHIFT                                                   7
+#define DDR_PHY_MR13_FSPOP_MASK                                                    0x00000080U
+
+/*Frequency Set Point Write Enable*/
+#undef DDR_PHY_MR13_FSPWR_DEFVAL 
+#undef DDR_PHY_MR13_FSPWR_SHIFT 
+#undef DDR_PHY_MR13_FSPWR_MASK 
+#define DDR_PHY_MR13_FSPWR_DEFVAL                                                  0x00000000
+#define DDR_PHY_MR13_FSPWR_SHIFT                                                   6
+#define DDR_PHY_MR13_FSPWR_MASK                                                    0x00000040U
+
+/*Data Mask Enable*/
+#undef DDR_PHY_MR13_DMD_DEFVAL 
+#undef DDR_PHY_MR13_DMD_SHIFT 
+#undef DDR_PHY_MR13_DMD_MASK 
+#define DDR_PHY_MR13_DMD_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR13_DMD_SHIFT                                                     5
+#define DDR_PHY_MR13_DMD_MASK                                                      0x00000020U
+
+/*Refresh Rate Option*/
+#undef DDR_PHY_MR13_RRO_DEFVAL 
+#undef DDR_PHY_MR13_RRO_SHIFT 
+#undef DDR_PHY_MR13_RRO_MASK 
+#define DDR_PHY_MR13_RRO_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR13_RRO_SHIFT                                                     4
+#define DDR_PHY_MR13_RRO_MASK                                                      0x00000010U
+
+/*VREF Current Generator*/
+#undef DDR_PHY_MR13_VRCG_DEFVAL 
+#undef DDR_PHY_MR13_VRCG_SHIFT 
+#undef DDR_PHY_MR13_VRCG_MASK 
+#define DDR_PHY_MR13_VRCG_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR13_VRCG_SHIFT                                                    3
+#define DDR_PHY_MR13_VRCG_MASK                                                     0x00000008U
+
+/*VREF Output*/
+#undef DDR_PHY_MR13_VRO_DEFVAL 
+#undef DDR_PHY_MR13_VRO_SHIFT 
+#undef DDR_PHY_MR13_VRO_MASK 
+#define DDR_PHY_MR13_VRO_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR13_VRO_SHIFT                                                     2
+#define DDR_PHY_MR13_VRO_MASK                                                      0x00000004U
+
+/*Read Preamble Training Mode*/
+#undef DDR_PHY_MR13_RPT_DEFVAL 
+#undef DDR_PHY_MR13_RPT_SHIFT 
+#undef DDR_PHY_MR13_RPT_MASK 
+#define DDR_PHY_MR13_RPT_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR13_RPT_SHIFT                                                     1
+#define DDR_PHY_MR13_RPT_MASK                                                      0x00000002U
+
+/*Command Bus Training*/
+#undef DDR_PHY_MR13_CBT_DEFVAL 
+#undef DDR_PHY_MR13_CBT_SHIFT 
+#undef DDR_PHY_MR13_CBT_MASK 
+#define DDR_PHY_MR13_CBT_DEFVAL                                                    0x00000000
+#define DDR_PHY_MR13_CBT_SHIFT                                                     0
+#define DDR_PHY_MR13_CBT_MASK                                                      0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR14_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR14_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR14_RESERVED_31_8_MASK 
+#define DDR_PHY_MR14_RESERVED_31_8_DEFVAL                                          0x0000004D
+#define DDR_PHY_MR14_RESERVED_31_8_SHIFT                                           8
+#define DDR_PHY_MR14_RESERVED_31_8_MASK                                            0xFFFFFF00U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR14_RSVD_DEFVAL 
+#undef DDR_PHY_MR14_RSVD_SHIFT 
+#undef DDR_PHY_MR14_RSVD_MASK 
+#define DDR_PHY_MR14_RSVD_DEFVAL                                                   0x0000004D
+#define DDR_PHY_MR14_RSVD_SHIFT                                                    7
+#define DDR_PHY_MR14_RSVD_MASK                                                     0x00000080U
+
+/*VREFDQ Range Selects.*/
+#undef DDR_PHY_MR14_VR_DQ_DEFVAL 
+#undef DDR_PHY_MR14_VR_DQ_SHIFT 
+#undef DDR_PHY_MR14_VR_DQ_MASK 
+#define DDR_PHY_MR14_VR_DQ_DEFVAL                                                  0x0000004D
+#define DDR_PHY_MR14_VR_DQ_SHIFT                                                   6
+#define DDR_PHY_MR14_VR_DQ_MASK                                                    0x00000040U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR14_VREF_DQ_DEFVAL 
+#undef DDR_PHY_MR14_VREF_DQ_SHIFT 
+#undef DDR_PHY_MR14_VREF_DQ_MASK 
+#define DDR_PHY_MR14_VREF_DQ_DEFVAL                                                0x0000004D
+#define DDR_PHY_MR14_VREF_DQ_SHIFT                                                 0
+#define DDR_PHY_MR14_VREF_DQ_MASK                                                  0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_MR22_RESERVED_31_8_DEFVAL 
+#undef DDR_PHY_MR22_RESERVED_31_8_SHIFT 
+#undef DDR_PHY_MR22_RESERVED_31_8_MASK 
+#define DDR_PHY_MR22_RESERVED_31_8_DEFVAL                                          0x00000000
+#define DDR_PHY_MR22_RESERVED_31_8_SHIFT                                           8
+#define DDR_PHY_MR22_RESERVED_31_8_MASK                                            0xFFFFFF00U
+
+/*These are JEDEC reserved bits and are recommended by JEDEC to be programmed to 0x0.*/
+#undef DDR_PHY_MR22_RSVD_DEFVAL 
+#undef DDR_PHY_MR22_RSVD_SHIFT 
+#undef DDR_PHY_MR22_RSVD_MASK 
+#define DDR_PHY_MR22_RSVD_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR22_RSVD_SHIFT                                                    6
+#define DDR_PHY_MR22_RSVD_MASK                                                     0x000000C0U
+
+/*CA ODT termination disable.*/
+#undef DDR_PHY_MR22_ODTD_CA_DEFVAL 
+#undef DDR_PHY_MR22_ODTD_CA_SHIFT 
+#undef DDR_PHY_MR22_ODTD_CA_MASK 
+#define DDR_PHY_MR22_ODTD_CA_DEFVAL                                                0x00000000
+#define DDR_PHY_MR22_ODTD_CA_SHIFT                                                 5
+#define DDR_PHY_MR22_ODTD_CA_MASK                                                  0x00000020U
+
+/*ODT CS override.*/
+#undef DDR_PHY_MR22_ODTE_CS_DEFVAL 
+#undef DDR_PHY_MR22_ODTE_CS_SHIFT 
+#undef DDR_PHY_MR22_ODTE_CS_MASK 
+#define DDR_PHY_MR22_ODTE_CS_DEFVAL                                                0x00000000
+#define DDR_PHY_MR22_ODTE_CS_SHIFT                                                 4
+#define DDR_PHY_MR22_ODTE_CS_MASK                                                  0x00000010U
+
+/*ODT CK override.*/
+#undef DDR_PHY_MR22_ODTE_CK_DEFVAL 
+#undef DDR_PHY_MR22_ODTE_CK_SHIFT 
+#undef DDR_PHY_MR22_ODTE_CK_MASK 
+#define DDR_PHY_MR22_ODTE_CK_DEFVAL                                                0x00000000
+#define DDR_PHY_MR22_ODTE_CK_SHIFT                                                 3
+#define DDR_PHY_MR22_ODTE_CK_MASK                                                  0x00000008U
+
+/*Controller ODT value for VOH calibration.*/
+#undef DDR_PHY_MR22_CODT_DEFVAL 
+#undef DDR_PHY_MR22_CODT_SHIFT 
+#undef DDR_PHY_MR22_CODT_MASK 
+#define DDR_PHY_MR22_CODT_DEFVAL                                                   0x00000000
+#define DDR_PHY_MR22_CODT_SHIFT                                                    0
+#define DDR_PHY_MR22_CODT_MASK                                                     0x00000007U
+
+/*Refresh During Training*/
+#undef DDR_PHY_DTCR0_RFSHDT_DEFVAL 
+#undef DDR_PHY_DTCR0_RFSHDT_SHIFT 
+#undef DDR_PHY_DTCR0_RFSHDT_MASK 
+#define DDR_PHY_DTCR0_RFSHDT_DEFVAL                                                0x800091C7
+#define DDR_PHY_DTCR0_RFSHDT_SHIFT                                                 28
+#define DDR_PHY_DTCR0_RFSHDT_MASK                                                  0xF0000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL 
+#undef DDR_PHY_DTCR0_RESERVED_27_26_SHIFT 
+#undef DDR_PHY_DTCR0_RESERVED_27_26_MASK 
+#define DDR_PHY_DTCR0_RESERVED_27_26_DEFVAL                                        0x800091C7
+#define DDR_PHY_DTCR0_RESERVED_27_26_SHIFT                                         26
+#define DDR_PHY_DTCR0_RESERVED_27_26_MASK                                          0x0C000000U
+
+/*Data Training Debug Rank Select*/
+#undef DDR_PHY_DTCR0_DTDRS_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDRS_SHIFT 
+#undef DDR_PHY_DTCR0_DTDRS_MASK 
+#define DDR_PHY_DTCR0_DTDRS_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTDRS_SHIFT                                                  24
+#define DDR_PHY_DTCR0_DTDRS_MASK                                                   0x03000000U
+
+/*Data Training with Early/Extended Gate*/
+#undef DDR_PHY_DTCR0_DTEXG_DEFVAL 
+#undef DDR_PHY_DTCR0_DTEXG_SHIFT 
+#undef DDR_PHY_DTCR0_DTEXG_MASK 
+#define DDR_PHY_DTCR0_DTEXG_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTEXG_SHIFT                                                  23
+#define DDR_PHY_DTCR0_DTEXG_MASK                                                   0x00800000U
+
+/*Data Training Extended Write DQS*/
+#undef DDR_PHY_DTCR0_DTEXD_DEFVAL 
+#undef DDR_PHY_DTCR0_DTEXD_SHIFT 
+#undef DDR_PHY_DTCR0_DTEXD_MASK 
+#define DDR_PHY_DTCR0_DTEXD_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTEXD_SHIFT                                                  22
+#define DDR_PHY_DTCR0_DTEXD_MASK                                                   0x00400000U
+
+/*Data Training Debug Step*/
+#undef DDR_PHY_DTCR0_DTDSTP_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDSTP_SHIFT 
+#undef DDR_PHY_DTCR0_DTDSTP_MASK 
+#define DDR_PHY_DTCR0_DTDSTP_DEFVAL                                                0x800091C7
+#define DDR_PHY_DTCR0_DTDSTP_SHIFT                                                 21
+#define DDR_PHY_DTCR0_DTDSTP_MASK                                                  0x00200000U
+
+/*Data Training Debug Enable*/
+#undef DDR_PHY_DTCR0_DTDEN_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDEN_SHIFT 
+#undef DDR_PHY_DTCR0_DTDEN_MASK 
+#define DDR_PHY_DTCR0_DTDEN_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTDEN_SHIFT                                                  20
+#define DDR_PHY_DTCR0_DTDEN_MASK                                                   0x00100000U
+
+/*Data Training Debug Byte Select*/
+#undef DDR_PHY_DTCR0_DTDBS_DEFVAL 
+#undef DDR_PHY_DTCR0_DTDBS_SHIFT 
+#undef DDR_PHY_DTCR0_DTDBS_MASK 
+#define DDR_PHY_DTCR0_DTDBS_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTDBS_SHIFT                                                  16
+#define DDR_PHY_DTCR0_DTDBS_MASK                                                   0x000F0000U
+
+/*Data Training read DBI deskewing configuration*/
+#undef DDR_PHY_DTCR0_DTRDBITR_DEFVAL 
+#undef DDR_PHY_DTCR0_DTRDBITR_SHIFT 
+#undef DDR_PHY_DTCR0_DTRDBITR_MASK 
+#define DDR_PHY_DTCR0_DTRDBITR_DEFVAL                                              0x800091C7
+#define DDR_PHY_DTCR0_DTRDBITR_SHIFT                                               14
+#define DDR_PHY_DTCR0_DTRDBITR_MASK                                                0x0000C000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR0_RESERVED_13_DEFVAL 
+#undef DDR_PHY_DTCR0_RESERVED_13_SHIFT 
+#undef DDR_PHY_DTCR0_RESERVED_13_MASK 
+#define DDR_PHY_DTCR0_RESERVED_13_DEFVAL                                           0x800091C7
+#define DDR_PHY_DTCR0_RESERVED_13_SHIFT                                            13
+#define DDR_PHY_DTCR0_RESERVED_13_MASK                                             0x00002000U
+
+/*Data Training Write Bit Deskew Data Mask*/
+#undef DDR_PHY_DTCR0_DTWBDDM_DEFVAL 
+#undef DDR_PHY_DTCR0_DTWBDDM_SHIFT 
+#undef DDR_PHY_DTCR0_DTWBDDM_MASK 
+#define DDR_PHY_DTCR0_DTWBDDM_DEFVAL                                               0x800091C7
+#define DDR_PHY_DTCR0_DTWBDDM_SHIFT                                                12
+#define DDR_PHY_DTCR0_DTWBDDM_MASK                                                 0x00001000U
+
+/*Refreshes Issued During Entry to Training*/
+#undef DDR_PHY_DTCR0_RFSHEN_DEFVAL 
+#undef DDR_PHY_DTCR0_RFSHEN_SHIFT 
+#undef DDR_PHY_DTCR0_RFSHEN_MASK 
+#define DDR_PHY_DTCR0_RFSHEN_DEFVAL                                                0x800091C7
+#define DDR_PHY_DTCR0_RFSHEN_SHIFT                                                 8
+#define DDR_PHY_DTCR0_RFSHEN_MASK                                                  0x00000F00U
+
+/*Data Training Compare Data*/
+#undef DDR_PHY_DTCR0_DTCMPD_DEFVAL 
+#undef DDR_PHY_DTCR0_DTCMPD_SHIFT 
+#undef DDR_PHY_DTCR0_DTCMPD_MASK 
+#define DDR_PHY_DTCR0_DTCMPD_DEFVAL                                                0x800091C7
+#define DDR_PHY_DTCR0_DTCMPD_SHIFT                                                 7
+#define DDR_PHY_DTCR0_DTCMPD_MASK                                                  0x00000080U
+
+/*Data Training Using MPR*/
+#undef DDR_PHY_DTCR0_DTMPR_DEFVAL 
+#undef DDR_PHY_DTCR0_DTMPR_SHIFT 
+#undef DDR_PHY_DTCR0_DTMPR_MASK 
+#define DDR_PHY_DTCR0_DTMPR_DEFVAL                                                 0x800091C7
+#define DDR_PHY_DTCR0_DTMPR_SHIFT                                                  6
+#define DDR_PHY_DTCR0_DTMPR_MASK                                                   0x00000040U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL 
+#undef DDR_PHY_DTCR0_RESERVED_5_4_SHIFT 
+#undef DDR_PHY_DTCR0_RESERVED_5_4_MASK 
+#define DDR_PHY_DTCR0_RESERVED_5_4_DEFVAL                                          0x800091C7
+#define DDR_PHY_DTCR0_RESERVED_5_4_SHIFT                                           4
+#define DDR_PHY_DTCR0_RESERVED_5_4_MASK                                            0x00000030U
+
+/*Data Training Repeat Number*/
+#undef DDR_PHY_DTCR0_DTRPTN_DEFVAL 
+#undef DDR_PHY_DTCR0_DTRPTN_SHIFT 
+#undef DDR_PHY_DTCR0_DTRPTN_MASK 
+#define DDR_PHY_DTCR0_DTRPTN_DEFVAL                                                0x800091C7
+#define DDR_PHY_DTCR0_DTRPTN_SHIFT                                                 0
+#define DDR_PHY_DTCR0_DTRPTN_MASK                                                  0x0000000FU
+
+/*Rank Enable.*/
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL 
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT 
+#undef DDR_PHY_DTCR1_RANKEN_RSVD_MASK 
+#define DDR_PHY_DTCR1_RANKEN_RSVD_DEFVAL                                           0x00030237
+#define DDR_PHY_DTCR1_RANKEN_RSVD_SHIFT                                            18
+#define DDR_PHY_DTCR1_RANKEN_RSVD_MASK                                             0xFFFC0000U
+
+/*Rank Enable.*/
+#undef DDR_PHY_DTCR1_RANKEN_DEFVAL 
+#undef DDR_PHY_DTCR1_RANKEN_SHIFT 
+#undef DDR_PHY_DTCR1_RANKEN_MASK 
+#define DDR_PHY_DTCR1_RANKEN_DEFVAL                                                0x00030237
+#define DDR_PHY_DTCR1_RANKEN_SHIFT                                                 16
+#define DDR_PHY_DTCR1_RANKEN_MASK                                                  0x00030000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_15_14_MASK 
+#define DDR_PHY_DTCR1_RESERVED_15_14_DEFVAL                                        0x00030237
+#define DDR_PHY_DTCR1_RESERVED_15_14_SHIFT                                         14
+#define DDR_PHY_DTCR1_RESERVED_15_14_MASK                                          0x0000C000U
+
+/*Data Training Rank*/
+#undef DDR_PHY_DTCR1_DTRANK_DEFVAL 
+#undef DDR_PHY_DTCR1_DTRANK_SHIFT 
+#undef DDR_PHY_DTCR1_DTRANK_MASK 
+#define DDR_PHY_DTCR1_DTRANK_DEFVAL                                                0x00030237
+#define DDR_PHY_DTCR1_DTRANK_SHIFT                                                 12
+#define DDR_PHY_DTCR1_DTRANK_MASK                                                  0x00003000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR1_RESERVED_11_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_11_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_11_MASK 
+#define DDR_PHY_DTCR1_RESERVED_11_DEFVAL                                           0x00030237
+#define DDR_PHY_DTCR1_RESERVED_11_SHIFT                                            11
+#define DDR_PHY_DTCR1_RESERVED_11_MASK                                             0x00000800U
+
+/*Read Leveling Gate Sampling Difference*/
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL 
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT 
+#undef DDR_PHY_DTCR1_RDLVLGDIFF_MASK 
+#define DDR_PHY_DTCR1_RDLVLGDIFF_DEFVAL                                            0x00030237
+#define DDR_PHY_DTCR1_RDLVLGDIFF_SHIFT                                             8
+#define DDR_PHY_DTCR1_RDLVLGDIFF_MASK                                              0x00000700U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR1_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_7_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_7_MASK 
+#define DDR_PHY_DTCR1_RESERVED_7_DEFVAL                                            0x00030237
+#define DDR_PHY_DTCR1_RESERVED_7_SHIFT                                             7
+#define DDR_PHY_DTCR1_RESERVED_7_MASK                                              0x00000080U
+
+/*Read Leveling Gate Shift*/
+#undef DDR_PHY_DTCR1_RDLVLGS_DEFVAL 
+#undef DDR_PHY_DTCR1_RDLVLGS_SHIFT 
+#undef DDR_PHY_DTCR1_RDLVLGS_MASK 
+#define DDR_PHY_DTCR1_RDLVLGS_DEFVAL                                               0x00030237
+#define DDR_PHY_DTCR1_RDLVLGS_SHIFT                                                4
+#define DDR_PHY_DTCR1_RDLVLGS_MASK                                                 0x00000070U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DTCR1_RESERVED_3_DEFVAL 
+#undef DDR_PHY_DTCR1_RESERVED_3_SHIFT 
+#undef DDR_PHY_DTCR1_RESERVED_3_MASK 
+#define DDR_PHY_DTCR1_RESERVED_3_DEFVAL                                            0x00030237
+#define DDR_PHY_DTCR1_RESERVED_3_SHIFT                                             3
+#define DDR_PHY_DTCR1_RESERVED_3_MASK                                              0x00000008U
+
+/*Read Preamble Training enable*/
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL 
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT 
+#undef DDR_PHY_DTCR1_RDPRMVL_TRN_MASK 
+#define DDR_PHY_DTCR1_RDPRMVL_TRN_DEFVAL                                           0x00030237
+#define DDR_PHY_DTCR1_RDPRMVL_TRN_SHIFT                                            2
+#define DDR_PHY_DTCR1_RDPRMVL_TRN_MASK                                             0x00000004U
+
+/*Read Leveling Enable*/
+#undef DDR_PHY_DTCR1_RDLVLEN_DEFVAL 
+#undef DDR_PHY_DTCR1_RDLVLEN_SHIFT 
+#undef DDR_PHY_DTCR1_RDLVLEN_MASK 
+#define DDR_PHY_DTCR1_RDLVLEN_DEFVAL                                               0x00030237
+#define DDR_PHY_DTCR1_RDLVLEN_SHIFT                                                1
+#define DDR_PHY_DTCR1_RDLVLEN_MASK                                                 0x00000002U
+
+/*Basic Gate Training Enable*/
+#undef DDR_PHY_DTCR1_BSTEN_DEFVAL 
+#undef DDR_PHY_DTCR1_BSTEN_SHIFT 
+#undef DDR_PHY_DTCR1_BSTEN_MASK 
+#define DDR_PHY_DTCR1_BSTEN_DEFVAL                                                 0x00030237
+#define DDR_PHY_DTCR1_BSTEN_SHIFT                                                  0
+#define DDR_PHY_DTCR1_BSTEN_MASK                                                   0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_CATR0_RESERVED_31_21_DEFVAL 
+#undef DDR_PHY_CATR0_RESERVED_31_21_SHIFT 
+#undef DDR_PHY_CATR0_RESERVED_31_21_MASK 
+#define DDR_PHY_CATR0_RESERVED_31_21_DEFVAL                                        0x00141054
+#define DDR_PHY_CATR0_RESERVED_31_21_SHIFT                                         21
+#define DDR_PHY_CATR0_RESERVED_31_21_MASK                                          0xFFE00000U
+
+/*Minimum time (in terms of number of dram clocks) between two consectuve CA calibration command*/
+#undef DDR_PHY_CATR0_CACD_DEFVAL 
+#undef DDR_PHY_CATR0_CACD_SHIFT 
+#undef DDR_PHY_CATR0_CACD_MASK 
+#define DDR_PHY_CATR0_CACD_DEFVAL                                                  0x00141054
+#define DDR_PHY_CATR0_CACD_SHIFT                                                   16
+#define DDR_PHY_CATR0_CACD_MASK                                                    0x001F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_CATR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_CATR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_CATR0_RESERVED_15_13_MASK 
+#define DDR_PHY_CATR0_RESERVED_15_13_DEFVAL                                        0x00141054
+#define DDR_PHY_CATR0_RESERVED_15_13_SHIFT                                         13
+#define DDR_PHY_CATR0_RESERVED_15_13_MASK                                          0x0000E000U
+
+/*Minimum time (in terms of number of dram clocks) PUB should wait before sampling the CA response after Calibration command ha
+		 been sent to the memory*/
+#undef DDR_PHY_CATR0_CAADR_DEFVAL 
+#undef DDR_PHY_CATR0_CAADR_SHIFT 
+#undef DDR_PHY_CATR0_CAADR_MASK 
+#define DDR_PHY_CATR0_CAADR_DEFVAL                                                 0x00141054
+#define DDR_PHY_CATR0_CAADR_SHIFT                                                  8
+#define DDR_PHY_CATR0_CAADR_MASK                                                   0x00001F00U
+
+/*CA_1 Response Byte Lane 1*/
+#undef DDR_PHY_CATR0_CA1BYTE1_DEFVAL 
+#undef DDR_PHY_CATR0_CA1BYTE1_SHIFT 
+#undef DDR_PHY_CATR0_CA1BYTE1_MASK 
+#define DDR_PHY_CATR0_CA1BYTE1_DEFVAL                                              0x00141054
+#define DDR_PHY_CATR0_CA1BYTE1_SHIFT                                               4
+#define DDR_PHY_CATR0_CA1BYTE1_MASK                                                0x000000F0U
+
+/*CA_1 Response Byte Lane 0*/
+#undef DDR_PHY_CATR0_CA1BYTE0_DEFVAL 
+#undef DDR_PHY_CATR0_CA1BYTE0_SHIFT 
+#undef DDR_PHY_CATR0_CA1BYTE0_MASK 
+#define DDR_PHY_CATR0_CA1BYTE0_DEFVAL                                              0x00141054
+#define DDR_PHY_CATR0_CA1BYTE0_SHIFT                                               0
+#define DDR_PHY_CATR0_CA1BYTE0_MASK                                                0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL 
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT 
+#undef DDR_PHY_RIOCR5_RESERVED_31_16_MASK 
+#define DDR_PHY_RIOCR5_RESERVED_31_16_DEFVAL                                       0x00000005
+#define DDR_PHY_RIOCR5_RESERVED_31_16_SHIFT                                        16
+#define DDR_PHY_RIOCR5_RESERVED_31_16_MASK                                         0xFFFF0000U
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK 
+#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_DEFVAL                                       0x00000005
+#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_SHIFT                                        4
+#define DDR_PHY_RIOCR5_ODTOEMODE_RSVD_MASK                                         0x0000FFF0U
+
+/*SDRAM On-die Termination Output Enable (OE) Mode Selection.*/
+#undef DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_SHIFT 
+#undef DDR_PHY_RIOCR5_ODTOEMODE_MASK 
+#define DDR_PHY_RIOCR5_ODTOEMODE_DEFVAL                                            0x00000005
+#define DDR_PHY_RIOCR5_ODTOEMODE_SHIFT                                             0
+#define DDR_PHY_RIOCR5_ODTOEMODE_MASK                                              0x0000000FU
+
+/*Address/Command Slew Rate (D3F I/O Only)*/
+#undef DDR_PHY_ACIOCR0_ACSR_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACSR_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACSR_MASK 
+#define DDR_PHY_ACIOCR0_ACSR_DEFVAL                                                0x30000000
+#define DDR_PHY_ACIOCR0_ACSR_SHIFT                                                 30
+#define DDR_PHY_ACIOCR0_ACSR_MASK                                                  0xC0000000U
+
+/*SDRAM Reset I/O Mode*/
+#undef DDR_PHY_ACIOCR0_RSTIOM_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RSTIOM_SHIFT 
+#undef DDR_PHY_ACIOCR0_RSTIOM_MASK 
+#define DDR_PHY_ACIOCR0_RSTIOM_DEFVAL                                              0x30000000
+#define DDR_PHY_ACIOCR0_RSTIOM_SHIFT                                               29
+#define DDR_PHY_ACIOCR0_RSTIOM_MASK                                                0x20000000U
+
+/*SDRAM Reset Power Down Receiver*/
+#undef DDR_PHY_ACIOCR0_RSTPDR_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RSTPDR_SHIFT 
+#undef DDR_PHY_ACIOCR0_RSTPDR_MASK 
+#define DDR_PHY_ACIOCR0_RSTPDR_DEFVAL                                              0x30000000
+#define DDR_PHY_ACIOCR0_RSTPDR_SHIFT                                               28
+#define DDR_PHY_ACIOCR0_RSTPDR_MASK                                                0x10000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RESERVED_27_SHIFT 
+#undef DDR_PHY_ACIOCR0_RESERVED_27_MASK 
+#define DDR_PHY_ACIOCR0_RESERVED_27_DEFVAL                                         0x30000000
+#define DDR_PHY_ACIOCR0_RESERVED_27_SHIFT                                          27
+#define DDR_PHY_ACIOCR0_RESERVED_27_MASK                                           0x08000000U
+
+/*SDRAM Reset On-Die Termination*/
+#undef DDR_PHY_ACIOCR0_RSTODT_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RSTODT_SHIFT 
+#undef DDR_PHY_ACIOCR0_RSTODT_MASK 
+#define DDR_PHY_ACIOCR0_RSTODT_DEFVAL                                              0x30000000
+#define DDR_PHY_ACIOCR0_RSTODT_SHIFT                                               26
+#define DDR_PHY_ACIOCR0_RSTODT_MASK                                                0x04000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT 
+#undef DDR_PHY_ACIOCR0_RESERVED_25_10_MASK 
+#define DDR_PHY_ACIOCR0_RESERVED_25_10_DEFVAL                                      0x30000000
+#define DDR_PHY_ACIOCR0_RESERVED_25_10_SHIFT                                       10
+#define DDR_PHY_ACIOCR0_RESERVED_25_10_MASK                                        0x03FFFC00U
+
+/*CK Duty Cycle Correction*/
+#undef DDR_PHY_ACIOCR0_CKDCC_DEFVAL 
+#undef DDR_PHY_ACIOCR0_CKDCC_SHIFT 
+#undef DDR_PHY_ACIOCR0_CKDCC_MASK 
+#define DDR_PHY_ACIOCR0_CKDCC_DEFVAL                                               0x30000000
+#define DDR_PHY_ACIOCR0_CKDCC_SHIFT                                                6
+#define DDR_PHY_ACIOCR0_CKDCC_MASK                                                 0x000003C0U
+
+/*AC Power Down Receiver Mode*/
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACPDRMODE_MASK 
+#define DDR_PHY_ACIOCR0_ACPDRMODE_DEFVAL                                           0x30000000
+#define DDR_PHY_ACIOCR0_ACPDRMODE_SHIFT                                            4
+#define DDR_PHY_ACIOCR0_ACPDRMODE_MASK                                             0x00000030U
+
+/*AC On-die Termination Mode*/
+#undef DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACODTMODE_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACODTMODE_MASK 
+#define DDR_PHY_ACIOCR0_ACODTMODE_DEFVAL                                           0x30000000
+#define DDR_PHY_ACIOCR0_ACODTMODE_SHIFT                                            2
+#define DDR_PHY_ACIOCR0_ACODTMODE_MASK                                             0x0000000CU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL 
+#undef DDR_PHY_ACIOCR0_RESERVED_1_SHIFT 
+#undef DDR_PHY_ACIOCR0_RESERVED_1_MASK 
+#define DDR_PHY_ACIOCR0_RESERVED_1_DEFVAL                                          0x30000000
+#define DDR_PHY_ACIOCR0_RESERVED_1_SHIFT                                           1
+#define DDR_PHY_ACIOCR0_RESERVED_1_MASK                                            0x00000002U
+
+/*Control delayed or non-delayed clock to CS_N/ODT?CKE AC slices.*/
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL 
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT 
+#undef DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK 
+#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_DEFVAL                                        0x30000000
+#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_SHIFT                                         0
+#define DDR_PHY_ACIOCR0_ACRANKCLKSEL_MASK                                          0x00000001U
+
+/*Clock gating for glue logic inside CLKGEN and glue logic inside CONTROL slice*/
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL 
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT 
+#undef DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK 
+#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_DEFVAL                                       0x00000000
+#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_SHIFT                                        31
+#define DDR_PHY_ACIOCR2_CLKGENCLKGATE_MASK                                         0x80000000U
+
+/*Clock gating for Output Enable D slices [0]*/
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACOECLKGATE0_DEFVAL                                        0x00000000
+#define DDR_PHY_ACIOCR2_ACOECLKGATE0_SHIFT                                         30
+#define DDR_PHY_ACIOCR2_ACOECLKGATE0_MASK                                          0x40000000U
+
+/*Clock gating for Power Down Receiver D slices [0]*/
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_DEFVAL                                       0x00000000
+#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_SHIFT                                        29
+#define DDR_PHY_ACIOCR2_ACPDRCLKGATE0_MASK                                         0x20000000U
+
+/*Clock gating for Termination Enable D slices [0]*/
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACTECLKGATE0_DEFVAL                                        0x00000000
+#define DDR_PHY_ACIOCR2_ACTECLKGATE0_SHIFT                                         28
+#define DDR_PHY_ACIOCR2_ACTECLKGATE0_MASK                                          0x10000000U
+
+/*Clock gating for CK# D slices [1:0]*/
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_CKNCLKGATE0_DEFVAL                                         0x00000000
+#define DDR_PHY_ACIOCR2_CKNCLKGATE0_SHIFT                                          26
+#define DDR_PHY_ACIOCR2_CKNCLKGATE0_MASK                                           0x0C000000U
+
+/*Clock gating for CK D slices [1:0]*/
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_CKCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_CKCLKGATE0_DEFVAL                                          0x00000000
+#define DDR_PHY_ACIOCR2_CKCLKGATE0_SHIFT                                           24
+#define DDR_PHY_ACIOCR2_CKCLKGATE0_MASK                                            0x03000000U
+
+/*Clock gating for AC D slices [23:0]*/
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL 
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT 
+#undef DDR_PHY_ACIOCR2_ACCLKGATE0_MASK 
+#define DDR_PHY_ACIOCR2_ACCLKGATE0_DEFVAL                                          0x00000000
+#define DDR_PHY_ACIOCR2_ACCLKGATE0_SHIFT                                           0
+#define DDR_PHY_ACIOCR2_ACCLKGATE0_MASK                                            0x00FFFFFFU
+
+/*SDRAM Parity Output Enable (OE) Mode Selection*/
+#undef DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_PAROEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_PAROEMODE_MASK 
+#define DDR_PHY_ACIOCR3_PAROEMODE_DEFVAL                                           0x00000005
+#define DDR_PHY_ACIOCR3_PAROEMODE_SHIFT                                            30
+#define DDR_PHY_ACIOCR3_PAROEMODE_MASK                                             0xC0000000U
+
+/*SDRAM Bank Group Output Enable (OE) Mode Selection*/
+#undef DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_BGOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_BGOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_BGOEMODE_DEFVAL                                            0x00000005
+#define DDR_PHY_ACIOCR3_BGOEMODE_SHIFT                                             26
+#define DDR_PHY_ACIOCR3_BGOEMODE_MASK                                              0x3C000000U
+
+/*SDRAM Bank Address Output Enable (OE) Mode Selection*/
+#undef DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_BAOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_BAOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_BAOEMODE_DEFVAL                                            0x00000005
+#define DDR_PHY_ACIOCR3_BAOEMODE_SHIFT                                             22
+#define DDR_PHY_ACIOCR3_BAOEMODE_MASK                                              0x03C00000U
+
+/*SDRAM A[17] Output Enable (OE) Mode Selection*/
+#undef DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_A17OEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_A17OEMODE_MASK 
+#define DDR_PHY_ACIOCR3_A17OEMODE_DEFVAL                                           0x00000005
+#define DDR_PHY_ACIOCR3_A17OEMODE_SHIFT                                            20
+#define DDR_PHY_ACIOCR3_A17OEMODE_MASK                                             0x00300000U
+
+/*SDRAM A[16] / RAS_n Output Enable (OE) Mode Selection*/
+#undef DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_A16OEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_A16OEMODE_MASK 
+#define DDR_PHY_ACIOCR3_A16OEMODE_DEFVAL                                           0x00000005
+#define DDR_PHY_ACIOCR3_A16OEMODE_SHIFT                                            18
+#define DDR_PHY_ACIOCR3_A16OEMODE_MASK                                             0x000C0000U
+
+/*SDRAM ACT_n Output Enable (OE) Mode Selection (DDR4 only)*/
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_ACTOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_ACTOEMODE_DEFVAL                                           0x00000005
+#define DDR_PHY_ACIOCR3_ACTOEMODE_SHIFT                                            16
+#define DDR_PHY_ACIOCR3_ACTOEMODE_MASK                                             0x00030000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL 
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT 
+#undef DDR_PHY_ACIOCR3_RESERVED_15_8_MASK 
+#define DDR_PHY_ACIOCR3_RESERVED_15_8_DEFVAL                                       0x00000005
+#define DDR_PHY_ACIOCR3_RESERVED_15_8_SHIFT                                        8
+#define DDR_PHY_ACIOCR3_RESERVED_15_8_MASK                                         0x0000FF00U
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK 
+#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_DEFVAL                                       0x00000005
+#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_SHIFT                                        4
+#define DDR_PHY_ACIOCR3_CKOEMODE_RSVD_MASK                                         0x000000F0U
+
+/*SDRAM CK Output Enable (OE) Mode Selection.*/
+#undef DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_SHIFT 
+#undef DDR_PHY_ACIOCR3_CKOEMODE_MASK 
+#define DDR_PHY_ACIOCR3_CKOEMODE_DEFVAL                                            0x00000005
+#define DDR_PHY_ACIOCR3_CKOEMODE_SHIFT                                             0
+#define DDR_PHY_ACIOCR3_CKOEMODE_MASK                                              0x0000000FU
+
+/*Clock gating for AC LB slices and loopback read valid slices*/
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL 
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT 
+#undef DDR_PHY_ACIOCR4_LBCLKGATE_MASK 
+#define DDR_PHY_ACIOCR4_LBCLKGATE_DEFVAL                                           0x00000000
+#define DDR_PHY_ACIOCR4_LBCLKGATE_SHIFT                                            31
+#define DDR_PHY_ACIOCR4_LBCLKGATE_MASK                                             0x80000000U
+
+/*Clock gating for Output Enable D slices [1]*/
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACOECLKGATE1_DEFVAL                                        0x00000000
+#define DDR_PHY_ACIOCR4_ACOECLKGATE1_SHIFT                                         30
+#define DDR_PHY_ACIOCR4_ACOECLKGATE1_MASK                                          0x40000000U
+
+/*Clock gating for Power Down Receiver D slices [1]*/
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_DEFVAL                                       0x00000000
+#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_SHIFT                                        29
+#define DDR_PHY_ACIOCR4_ACPDRCLKGATE1_MASK                                         0x20000000U
+
+/*Clock gating for Termination Enable D slices [1]*/
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACTECLKGATE1_DEFVAL                                        0x00000000
+#define DDR_PHY_ACIOCR4_ACTECLKGATE1_SHIFT                                         28
+#define DDR_PHY_ACIOCR4_ACTECLKGATE1_MASK                                          0x10000000U
+
+/*Clock gating for CK# D slices [3:2]*/
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_CKNCLKGATE1_DEFVAL                                         0x00000000
+#define DDR_PHY_ACIOCR4_CKNCLKGATE1_SHIFT                                          26
+#define DDR_PHY_ACIOCR4_CKNCLKGATE1_MASK                                           0x0C000000U
+
+/*Clock gating for CK D slices [3:2]*/
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_CKCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_CKCLKGATE1_DEFVAL                                          0x00000000
+#define DDR_PHY_ACIOCR4_CKCLKGATE1_SHIFT                                           24
+#define DDR_PHY_ACIOCR4_CKCLKGATE1_MASK                                            0x03000000U
+
+/*Clock gating for AC D slices [47:24]*/
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL 
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT 
+#undef DDR_PHY_ACIOCR4_ACCLKGATE1_MASK 
+#define DDR_PHY_ACIOCR4_ACCLKGATE1_DEFVAL                                          0x00000000
+#define DDR_PHY_ACIOCR4_ACCLKGATE1_SHIFT                                           0
+#define DDR_PHY_ACIOCR4_ACCLKGATE1_MASK                                            0x00FFFFFFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_IOVCR0_RESERVED_31_29_MASK 
+#define DDR_PHY_IOVCR0_RESERVED_31_29_DEFVAL                                       0x0F000000
+#define DDR_PHY_IOVCR0_RESERVED_31_29_SHIFT                                        29
+#define DDR_PHY_IOVCR0_RESERVED_31_29_MASK                                         0xE0000000U
+
+/*Address/command lane VREF Pad Enable*/
+#undef DDR_PHY_IOVCR0_ACREFPEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFPEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFPEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFPEN_DEFVAL                                             0x0F000000
+#define DDR_PHY_IOVCR0_ACREFPEN_SHIFT                                              28
+#define DDR_PHY_IOVCR0_ACREFPEN_MASK                                               0x10000000U
+
+/*Address/command lane Internal VREF Enable*/
+#undef DDR_PHY_IOVCR0_ACREFEEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFEEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFEEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFEEN_DEFVAL                                             0x0F000000
+#define DDR_PHY_IOVCR0_ACREFEEN_SHIFT                                              26
+#define DDR_PHY_IOVCR0_ACREFEEN_MASK                                               0x0C000000U
+
+/*Address/command lane Single-End VREF Enable*/
+#undef DDR_PHY_IOVCR0_ACREFSEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFSEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFSEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFSEN_DEFVAL                                             0x0F000000
+#define DDR_PHY_IOVCR0_ACREFSEN_SHIFT                                              25
+#define DDR_PHY_IOVCR0_ACREFSEN_MASK                                               0x02000000U
+
+/*Address/command lane Internal VREF Enable*/
+#undef DDR_PHY_IOVCR0_ACREFIEN_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFIEN_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFIEN_MASK 
+#define DDR_PHY_IOVCR0_ACREFIEN_DEFVAL                                             0x0F000000
+#define DDR_PHY_IOVCR0_ACREFIEN_SHIFT                                              24
+#define DDR_PHY_IOVCR0_ACREFIEN_MASK                                               0x01000000U
+
+/*External VREF generato REFSEL range select*/
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFESELRANGE_MASK 
+#define DDR_PHY_IOVCR0_ACREFESELRANGE_DEFVAL                                       0x0F000000
+#define DDR_PHY_IOVCR0_ACREFESELRANGE_SHIFT                                        23
+#define DDR_PHY_IOVCR0_ACREFESELRANGE_MASK                                         0x00800000U
+
+/*Address/command lane External VREF Select*/
+#undef DDR_PHY_IOVCR0_ACREFESEL_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFESEL_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFESEL_MASK 
+#define DDR_PHY_IOVCR0_ACREFESEL_DEFVAL                                            0x0F000000
+#define DDR_PHY_IOVCR0_ACREFESEL_SHIFT                                             16
+#define DDR_PHY_IOVCR0_ACREFESEL_MASK                                              0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK 
+#define DDR_PHY_IOVCR0_ACREFSSELRANGE_DEFVAL                                       0x0F000000
+#define DDR_PHY_IOVCR0_ACREFSSELRANGE_SHIFT                                        15
+#define DDR_PHY_IOVCR0_ACREFSSELRANGE_MASK                                         0x00008000U
+
+/*Address/command lane Single-End VREF Select*/
+#undef DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACREFSSEL_SHIFT 
+#undef DDR_PHY_IOVCR0_ACREFSSEL_MASK 
+#define DDR_PHY_IOVCR0_ACREFSSEL_DEFVAL                                            0x0F000000
+#define DDR_PHY_IOVCR0_ACREFSSEL_SHIFT                                             8
+#define DDR_PHY_IOVCR0_ACREFSSEL_MASK                                              0x00007F00U
+
+/*Internal VREF generator REFSEL ragne select*/
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT 
+#undef DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK 
+#define DDR_PHY_IOVCR0_ACVREFISELRANGE_DEFVAL                                      0x0F000000
+#define DDR_PHY_IOVCR0_ACVREFISELRANGE_SHIFT                                       7
+#define DDR_PHY_IOVCR0_ACVREFISELRANGE_MASK                                        0x00000080U
+
+/*REFSEL Control for internal AC IOs*/
+#undef DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL 
+#undef DDR_PHY_IOVCR0_ACVREFISEL_SHIFT 
+#undef DDR_PHY_IOVCR0_ACVREFISEL_MASK 
+#define DDR_PHY_IOVCR0_ACVREFISEL_DEFVAL                                           0x0F000000
+#define DDR_PHY_IOVCR0_ACVREFISEL_SHIFT                                            0
+#define DDR_PHY_IOVCR0_ACVREFISEL_MASK                                             0x0000007FU
+
+/*Number of ctl_clk required to meet (> 150ns) timing requirements during DRAM DQ VREF training*/
+#undef DDR_PHY_VTCR0_TVREF_DEFVAL 
+#undef DDR_PHY_VTCR0_TVREF_SHIFT 
+#undef DDR_PHY_VTCR0_TVREF_MASK 
+#define DDR_PHY_VTCR0_TVREF_DEFVAL                                                 0x70032019
+#define DDR_PHY_VTCR0_TVREF_SHIFT                                                  29
+#define DDR_PHY_VTCR0_TVREF_MASK                                                   0xE0000000U
+
+/*DRM DQ VREF training Enable*/
+#undef DDR_PHY_VTCR0_DVEN_DEFVAL 
+#undef DDR_PHY_VTCR0_DVEN_SHIFT 
+#undef DDR_PHY_VTCR0_DVEN_MASK 
+#define DDR_PHY_VTCR0_DVEN_DEFVAL                                                  0x70032019
+#define DDR_PHY_VTCR0_DVEN_SHIFT                                                   28
+#define DDR_PHY_VTCR0_DVEN_MASK                                                    0x10000000U
+
+/*Per Device Addressability Enable*/
+#undef DDR_PHY_VTCR0_PDAEN_DEFVAL 
+#undef DDR_PHY_VTCR0_PDAEN_SHIFT 
+#undef DDR_PHY_VTCR0_PDAEN_MASK 
+#define DDR_PHY_VTCR0_PDAEN_DEFVAL                                                 0x70032019
+#define DDR_PHY_VTCR0_PDAEN_SHIFT                                                  27
+#define DDR_PHY_VTCR0_PDAEN_MASK                                                   0x08000000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_VTCR0_RESERVED_26_DEFVAL 
+#undef DDR_PHY_VTCR0_RESERVED_26_SHIFT 
+#undef DDR_PHY_VTCR0_RESERVED_26_MASK 
+#define DDR_PHY_VTCR0_RESERVED_26_DEFVAL                                           0x70032019
+#define DDR_PHY_VTCR0_RESERVED_26_SHIFT                                            26
+#define DDR_PHY_VTCR0_RESERVED_26_MASK                                             0x04000000U
+
+/*VREF Word Count*/
+#undef DDR_PHY_VTCR0_VWCR_DEFVAL 
+#undef DDR_PHY_VTCR0_VWCR_SHIFT 
+#undef DDR_PHY_VTCR0_VWCR_MASK 
+#define DDR_PHY_VTCR0_VWCR_DEFVAL                                                  0x70032019
+#define DDR_PHY_VTCR0_VWCR_SHIFT                                                   22
+#define DDR_PHY_VTCR0_VWCR_MASK                                                    0x03C00000U
+
+/*DRAM DQ VREF step size used during DRAM VREF training*/
+#undef DDR_PHY_VTCR0_DVSS_DEFVAL 
+#undef DDR_PHY_VTCR0_DVSS_SHIFT 
+#undef DDR_PHY_VTCR0_DVSS_MASK 
+#define DDR_PHY_VTCR0_DVSS_DEFVAL                                                  0x70032019
+#define DDR_PHY_VTCR0_DVSS_SHIFT                                                   18
+#define DDR_PHY_VTCR0_DVSS_MASK                                                    0x003C0000U
+
+/*Maximum VREF limit value used during DRAM VREF training*/
+#undef DDR_PHY_VTCR0_DVMAX_DEFVAL 
+#undef DDR_PHY_VTCR0_DVMAX_SHIFT 
+#undef DDR_PHY_VTCR0_DVMAX_MASK 
+#define DDR_PHY_VTCR0_DVMAX_DEFVAL                                                 0x70032019
+#define DDR_PHY_VTCR0_DVMAX_SHIFT                                                  12
+#define DDR_PHY_VTCR0_DVMAX_MASK                                                   0x0003F000U
+
+/*Minimum VREF limit value used during DRAM VREF training*/
+#undef DDR_PHY_VTCR0_DVMIN_DEFVAL 
+#undef DDR_PHY_VTCR0_DVMIN_SHIFT 
+#undef DDR_PHY_VTCR0_DVMIN_MASK 
+#define DDR_PHY_VTCR0_DVMIN_DEFVAL                                                 0x70032019
+#define DDR_PHY_VTCR0_DVMIN_SHIFT                                                  6
+#define DDR_PHY_VTCR0_DVMIN_MASK                                                   0x00000FC0U
+
+/*Initial DRAM DQ VREF value used during DRAM VREF training*/
+#undef DDR_PHY_VTCR0_DVINIT_DEFVAL 
+#undef DDR_PHY_VTCR0_DVINIT_SHIFT 
+#undef DDR_PHY_VTCR0_DVINIT_MASK 
+#define DDR_PHY_VTCR0_DVINIT_DEFVAL                                                0x70032019
+#define DDR_PHY_VTCR0_DVINIT_SHIFT                                                 0
+#define DDR_PHY_VTCR0_DVINIT_MASK                                                  0x0000003FU
+
+/*Host VREF step size used during VREF training. The register value of N indicates step size of (N+1)*/
+#undef DDR_PHY_VTCR1_HVSS_DEFVAL 
+#undef DDR_PHY_VTCR1_HVSS_SHIFT 
+#undef DDR_PHY_VTCR1_HVSS_MASK 
+#define DDR_PHY_VTCR1_HVSS_DEFVAL                                                  0x07F00072
+#define DDR_PHY_VTCR1_HVSS_SHIFT                                                   28
+#define DDR_PHY_VTCR1_HVSS_MASK                                                    0xF0000000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_VTCR1_RESERVED_27_DEFVAL 
+#undef DDR_PHY_VTCR1_RESERVED_27_SHIFT 
+#undef DDR_PHY_VTCR1_RESERVED_27_MASK 
+#define DDR_PHY_VTCR1_RESERVED_27_DEFVAL                                           0x07F00072
+#define DDR_PHY_VTCR1_RESERVED_27_SHIFT                                            27
+#define DDR_PHY_VTCR1_RESERVED_27_MASK                                             0x08000000U
+
+/*Maximum VREF limit value used during DRAM VREF training.*/
+#undef DDR_PHY_VTCR1_HVMAX_DEFVAL 
+#undef DDR_PHY_VTCR1_HVMAX_SHIFT 
+#undef DDR_PHY_VTCR1_HVMAX_MASK 
+#define DDR_PHY_VTCR1_HVMAX_DEFVAL                                                 0x07F00072
+#define DDR_PHY_VTCR1_HVMAX_SHIFT                                                  20
+#define DDR_PHY_VTCR1_HVMAX_MASK                                                   0x07F00000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_VTCR1_RESERVED_19_DEFVAL 
+#undef DDR_PHY_VTCR1_RESERVED_19_SHIFT 
+#undef DDR_PHY_VTCR1_RESERVED_19_MASK 
+#define DDR_PHY_VTCR1_RESERVED_19_DEFVAL                                           0x07F00072
+#define DDR_PHY_VTCR1_RESERVED_19_SHIFT                                            19
+#define DDR_PHY_VTCR1_RESERVED_19_MASK                                             0x00080000U
+
+/*Minimum VREF limit value used during DRAM VREF training.*/
+#undef DDR_PHY_VTCR1_HVMIN_DEFVAL 
+#undef DDR_PHY_VTCR1_HVMIN_SHIFT 
+#undef DDR_PHY_VTCR1_HVMIN_MASK 
+#define DDR_PHY_VTCR1_HVMIN_DEFVAL                                                 0x07F00072
+#define DDR_PHY_VTCR1_HVMIN_SHIFT                                                  12
+#define DDR_PHY_VTCR1_HVMIN_MASK                                                   0x0007F000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_VTCR1_RESERVED_11_DEFVAL 
+#undef DDR_PHY_VTCR1_RESERVED_11_SHIFT 
+#undef DDR_PHY_VTCR1_RESERVED_11_MASK 
+#define DDR_PHY_VTCR1_RESERVED_11_DEFVAL                                           0x07F00072
+#define DDR_PHY_VTCR1_RESERVED_11_SHIFT                                            11
+#define DDR_PHY_VTCR1_RESERVED_11_MASK                                             0x00000800U
+
+/*Static Host Vref Rank Value*/
+#undef DDR_PHY_VTCR1_SHRNK_DEFVAL 
+#undef DDR_PHY_VTCR1_SHRNK_SHIFT 
+#undef DDR_PHY_VTCR1_SHRNK_MASK 
+#define DDR_PHY_VTCR1_SHRNK_DEFVAL                                                 0x07F00072
+#define DDR_PHY_VTCR1_SHRNK_SHIFT                                                  9
+#define DDR_PHY_VTCR1_SHRNK_MASK                                                   0x00000600U
+
+/*Static Host Vref Rank Enable*/
+#undef DDR_PHY_VTCR1_SHREN_DEFVAL 
+#undef DDR_PHY_VTCR1_SHREN_SHIFT 
+#undef DDR_PHY_VTCR1_SHREN_MASK 
+#define DDR_PHY_VTCR1_SHREN_DEFVAL                                                 0x07F00072
+#define DDR_PHY_VTCR1_SHREN_SHIFT                                                  8
+#define DDR_PHY_VTCR1_SHREN_MASK                                                   0x00000100U
+
+/*Number of ctl_clk required to meet (> 200ns) VREF Settling timing requirements during Host IO VREF training*/
+#undef DDR_PHY_VTCR1_TVREFIO_DEFVAL 
+#undef DDR_PHY_VTCR1_TVREFIO_SHIFT 
+#undef DDR_PHY_VTCR1_TVREFIO_MASK 
+#define DDR_PHY_VTCR1_TVREFIO_DEFVAL                                               0x07F00072
+#define DDR_PHY_VTCR1_TVREFIO_SHIFT                                                5
+#define DDR_PHY_VTCR1_TVREFIO_MASK                                                 0x000000E0U
+
+/*Eye LCDL Offset value for VREF training*/
+#undef DDR_PHY_VTCR1_EOFF_DEFVAL 
+#undef DDR_PHY_VTCR1_EOFF_SHIFT 
+#undef DDR_PHY_VTCR1_EOFF_MASK 
+#define DDR_PHY_VTCR1_EOFF_DEFVAL                                                  0x07F00072
+#define DDR_PHY_VTCR1_EOFF_SHIFT                                                   3
+#define DDR_PHY_VTCR1_EOFF_MASK                                                    0x00000018U
+
+/*Number of LCDL Eye points for which VREF training is repeated*/
+#undef DDR_PHY_VTCR1_ENUM_DEFVAL 
+#undef DDR_PHY_VTCR1_ENUM_SHIFT 
+#undef DDR_PHY_VTCR1_ENUM_MASK 
+#define DDR_PHY_VTCR1_ENUM_DEFVAL                                                  0x07F00072
+#define DDR_PHY_VTCR1_ENUM_SHIFT                                                   2
+#define DDR_PHY_VTCR1_ENUM_MASK                                                    0x00000004U
+
+/*HOST (IO) internal VREF training Enable*/
+#undef DDR_PHY_VTCR1_HVEN_DEFVAL 
+#undef DDR_PHY_VTCR1_HVEN_SHIFT 
+#undef DDR_PHY_VTCR1_HVEN_MASK 
+#define DDR_PHY_VTCR1_HVEN_DEFVAL                                                  0x07F00072
+#define DDR_PHY_VTCR1_HVEN_SHIFT                                                   1
+#define DDR_PHY_VTCR1_HVEN_MASK                                                    0x00000002U
+
+/*Host IO Type Control*/
+#undef DDR_PHY_VTCR1_HVIO_DEFVAL 
+#undef DDR_PHY_VTCR1_HVIO_SHIFT 
+#undef DDR_PHY_VTCR1_HVIO_MASK 
+#define DDR_PHY_VTCR1_HVIO_DEFVAL                                                  0x07F00072
+#define DDR_PHY_VTCR1_HVIO_SHIFT                                                   0
+#define DDR_PHY_VTCR1_HVIO_MASK                                                    0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_31_30_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_ACBDLR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*Delay select for the BDL on Address A[3].*/
+#undef DDR_PHY_ACBDLR6_A03BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A03BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A03BD_MASK 
+#define DDR_PHY_ACBDLR6_A03BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR6_A03BD_SHIFT                                                24
+#define DDR_PHY_ACBDLR6_A03BD_MASK                                                 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_23_22_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_ACBDLR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*Delay select for the BDL on Address A[2].*/
+#undef DDR_PHY_ACBDLR6_A02BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A02BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A02BD_MASK 
+#define DDR_PHY_ACBDLR6_A02BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR6_A02BD_SHIFT                                                16
+#define DDR_PHY_ACBDLR6_A02BD_MASK                                                 0x003F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_15_14_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_ACBDLR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*Delay select for the BDL on Address A[1].*/
+#undef DDR_PHY_ACBDLR6_A01BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A01BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A01BD_MASK 
+#define DDR_PHY_ACBDLR6_A01BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR6_A01BD_SHIFT                                                8
+#define DDR_PHY_ACBDLR6_A01BD_MASK                                                 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR6_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR6_RESERVED_7_6_DEFVAL                                        0x00000000
+#define DDR_PHY_ACBDLR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_ACBDLR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*Delay select for the BDL on Address A[0].*/
+#undef DDR_PHY_ACBDLR6_A00BD_DEFVAL 
+#undef DDR_PHY_ACBDLR6_A00BD_SHIFT 
+#undef DDR_PHY_ACBDLR6_A00BD_MASK 
+#define DDR_PHY_ACBDLR6_A00BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR6_A00BD_SHIFT                                                0
+#define DDR_PHY_ACBDLR6_A00BD_MASK                                                 0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_31_30_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_ACBDLR7_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*Delay select for the BDL on Address A[7].*/
+#undef DDR_PHY_ACBDLR7_A07BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A07BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A07BD_MASK 
+#define DDR_PHY_ACBDLR7_A07BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR7_A07BD_SHIFT                                                24
+#define DDR_PHY_ACBDLR7_A07BD_MASK                                                 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_23_22_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_ACBDLR7_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*Delay select for the BDL on Address A[6].*/
+#undef DDR_PHY_ACBDLR7_A06BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A06BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A06BD_MASK 
+#define DDR_PHY_ACBDLR7_A06BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR7_A06BD_SHIFT                                                16
+#define DDR_PHY_ACBDLR7_A06BD_MASK                                                 0x003F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_15_14_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_ACBDLR7_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*Delay select for the BDL on Address A[5].*/
+#undef DDR_PHY_ACBDLR7_A05BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A05BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A05BD_MASK 
+#define DDR_PHY_ACBDLR7_A05BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR7_A05BD_SHIFT                                                8
+#define DDR_PHY_ACBDLR7_A05BD_MASK                                                 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR7_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR7_RESERVED_7_6_DEFVAL                                        0x00000000
+#define DDR_PHY_ACBDLR7_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_ACBDLR7_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*Delay select for the BDL on Address A[4].*/
+#undef DDR_PHY_ACBDLR7_A04BD_DEFVAL 
+#undef DDR_PHY_ACBDLR7_A04BD_SHIFT 
+#undef DDR_PHY_ACBDLR7_A04BD_MASK 
+#define DDR_PHY_ACBDLR7_A04BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR7_A04BD_SHIFT                                                0
+#define DDR_PHY_ACBDLR7_A04BD_MASK                                                 0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_31_30_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_31_30_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_ACBDLR8_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*Delay select for the BDL on Address A[11].*/
+#undef DDR_PHY_ACBDLR8_A11BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A11BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A11BD_MASK 
+#define DDR_PHY_ACBDLR8_A11BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR8_A11BD_SHIFT                                                24
+#define DDR_PHY_ACBDLR8_A11BD_MASK                                                 0x3F000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_23_22_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_23_22_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_ACBDLR8_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*Delay select for the BDL on Address A[10].*/
+#undef DDR_PHY_ACBDLR8_A10BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A10BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A10BD_MASK 
+#define DDR_PHY_ACBDLR8_A10BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR8_A10BD_SHIFT                                                16
+#define DDR_PHY_ACBDLR8_A10BD_MASK                                                 0x003F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_15_14_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_15_14_DEFVAL                                      0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_ACBDLR8_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*Delay select for the BDL on Address A[9].*/
+#undef DDR_PHY_ACBDLR8_A09BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A09BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A09BD_MASK 
+#define DDR_PHY_ACBDLR8_A09BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR8_A09BD_SHIFT                                                8
+#define DDR_PHY_ACBDLR8_A09BD_MASK                                                 0x00003F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_ACBDLR8_RESERVED_7_6_MASK 
+#define DDR_PHY_ACBDLR8_RESERVED_7_6_DEFVAL                                        0x00000000
+#define DDR_PHY_ACBDLR8_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_ACBDLR8_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*Delay select for the BDL on Address A[8].*/
+#undef DDR_PHY_ACBDLR8_A08BD_DEFVAL 
+#undef DDR_PHY_ACBDLR8_A08BD_SHIFT 
+#undef DDR_PHY_ACBDLR8_A08BD_MASK 
+#define DDR_PHY_ACBDLR8_A08BD_DEFVAL                                               0x00000000
+#define DDR_PHY_ACBDLR8_A08BD_SHIFT                                                0
+#define DDR_PHY_ACBDLR8_A08BD_MASK                                                 0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL 
+#undef DDR_PHY_ZQCR_RESERVED_31_26_SHIFT 
+#undef DDR_PHY_ZQCR_RESERVED_31_26_MASK 
+#define DDR_PHY_ZQCR_RESERVED_31_26_DEFVAL                                         0x008A2858
+#define DDR_PHY_ZQCR_RESERVED_31_26_SHIFT                                          26
+#define DDR_PHY_ZQCR_RESERVED_31_26_MASK                                           0xFC000000U
+
+/*ZQ VREF Range*/
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT 
+#undef DDR_PHY_ZQCR_ZQREFISELRANGE_MASK 
+#define DDR_PHY_ZQCR_ZQREFISELRANGE_DEFVAL                                         0x008A2858
+#define DDR_PHY_ZQCR_ZQREFISELRANGE_SHIFT                                          25
+#define DDR_PHY_ZQCR_ZQREFISELRANGE_MASK                                           0x02000000U
+
+/*Programmable Wait for Frequency B*/
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQB_MASK 
+#define DDR_PHY_ZQCR_PGWAIT_FRQB_DEFVAL                                            0x008A2858
+#define DDR_PHY_ZQCR_PGWAIT_FRQB_SHIFT                                             19
+#define DDR_PHY_ZQCR_PGWAIT_FRQB_MASK                                              0x01F80000U
+
+/*Programmable Wait for Frequency A*/
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT 
+#undef DDR_PHY_ZQCR_PGWAIT_FRQA_MASK 
+#define DDR_PHY_ZQCR_PGWAIT_FRQA_DEFVAL                                            0x008A2858
+#define DDR_PHY_ZQCR_PGWAIT_FRQA_SHIFT                                             13
+#define DDR_PHY_ZQCR_PGWAIT_FRQA_MASK                                              0x0007E000U
+
+/*ZQ VREF Pad Enable*/
+#undef DDR_PHY_ZQCR_ZQREFPEN_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQREFPEN_SHIFT 
+#undef DDR_PHY_ZQCR_ZQREFPEN_MASK 
+#define DDR_PHY_ZQCR_ZQREFPEN_DEFVAL                                               0x008A2858
+#define DDR_PHY_ZQCR_ZQREFPEN_SHIFT                                                12
+#define DDR_PHY_ZQCR_ZQREFPEN_MASK                                                 0x00001000U
+
+/*ZQ Internal VREF Enable*/
+#undef DDR_PHY_ZQCR_ZQREFIEN_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQREFIEN_SHIFT 
+#undef DDR_PHY_ZQCR_ZQREFIEN_MASK 
+#define DDR_PHY_ZQCR_ZQREFIEN_DEFVAL                                               0x008A2858
+#define DDR_PHY_ZQCR_ZQREFIEN_SHIFT                                                11
+#define DDR_PHY_ZQCR_ZQREFIEN_MASK                                                 0x00000800U
+
+/*Choice of termination mode*/
+#undef DDR_PHY_ZQCR_ODT_MODE_DEFVAL 
+#undef DDR_PHY_ZQCR_ODT_MODE_SHIFT 
+#undef DDR_PHY_ZQCR_ODT_MODE_MASK 
+#define DDR_PHY_ZQCR_ODT_MODE_DEFVAL                                               0x008A2858
+#define DDR_PHY_ZQCR_ODT_MODE_SHIFT                                                9
+#define DDR_PHY_ZQCR_ODT_MODE_MASK                                                 0x00000600U
+
+/*Force ZCAL VT update*/
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL 
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT 
+#undef DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK 
+#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_DEFVAL                                   0x008A2858
+#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_SHIFT                                    8
+#define DDR_PHY_ZQCR_FORCE_ZCAL_VT_UPDATE_MASK                                     0x00000100U
+
+/*IO VT Drift Limit*/
+#undef DDR_PHY_ZQCR_IODLMT_DEFVAL 
+#undef DDR_PHY_ZQCR_IODLMT_SHIFT 
+#undef DDR_PHY_ZQCR_IODLMT_MASK 
+#define DDR_PHY_ZQCR_IODLMT_DEFVAL                                                 0x008A2858
+#define DDR_PHY_ZQCR_IODLMT_SHIFT                                                  5
+#define DDR_PHY_ZQCR_IODLMT_MASK                                                   0x000000E0U
+
+/*Averaging algorithm enable, if set, enables averaging algorithm*/
+#undef DDR_PHY_ZQCR_AVGEN_DEFVAL 
+#undef DDR_PHY_ZQCR_AVGEN_SHIFT 
+#undef DDR_PHY_ZQCR_AVGEN_MASK 
+#define DDR_PHY_ZQCR_AVGEN_DEFVAL                                                  0x008A2858
+#define DDR_PHY_ZQCR_AVGEN_SHIFT                                                   4
+#define DDR_PHY_ZQCR_AVGEN_MASK                                                    0x00000010U
+
+/*Maximum number of averaging rounds to be used by averaging algorithm*/
+#undef DDR_PHY_ZQCR_AVGMAX_DEFVAL 
+#undef DDR_PHY_ZQCR_AVGMAX_SHIFT 
+#undef DDR_PHY_ZQCR_AVGMAX_MASK 
+#define DDR_PHY_ZQCR_AVGMAX_DEFVAL                                                 0x008A2858
+#define DDR_PHY_ZQCR_AVGMAX_SHIFT                                                  2
+#define DDR_PHY_ZQCR_AVGMAX_MASK                                                   0x0000000CU
+
+/*ZQ Calibration Type*/
+#undef DDR_PHY_ZQCR_ZCALT_DEFVAL 
+#undef DDR_PHY_ZQCR_ZCALT_SHIFT 
+#undef DDR_PHY_ZQCR_ZCALT_MASK 
+#define DDR_PHY_ZQCR_ZCALT_DEFVAL                                                  0x008A2858
+#define DDR_PHY_ZQCR_ZCALT_SHIFT                                                   1
+#define DDR_PHY_ZQCR_ZCALT_MASK                                                    0x00000002U
+
+/*ZQ Power Down*/
+#undef DDR_PHY_ZQCR_ZQPD_DEFVAL 
+#undef DDR_PHY_ZQCR_ZQPD_SHIFT 
+#undef DDR_PHY_ZQCR_ZQPD_MASK 
+#define DDR_PHY_ZQCR_ZQPD_DEFVAL                                                   0x008A2858
+#define DDR_PHY_ZQCR_ZQPD_SHIFT                                                    0
+#define DDR_PHY_ZQCR_ZQPD_MASK                                                     0x00000001U
+
+/*Pull-down drive strength ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_SHIFT                                           31
+#define DDR_PHY_ZQ0PR0_PD_DRV_ZDEN_MASK                                            0x80000000U
+
+/*Pull-up drive strength ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_SHIFT                                           30
+#define DDR_PHY_ZQ0PR0_PU_DRV_ZDEN_MASK                                            0x40000000U
+
+/*Pull-down termination ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_SHIFT                                           29
+#define DDR_PHY_ZQ0PR0_PD_ODT_ZDEN_MASK                                            0x20000000U
+
+/*Pull-up termination ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_SHIFT                                           28
+#define DDR_PHY_ZQ0PR0_PU_ODT_ZDEN_MASK                                            0x10000000U
+
+/*Calibration segment bypass*/
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZSEGBYP_MASK 
+#define DDR_PHY_ZQ0PR0_ZSEGBYP_DEFVAL                                              0x000077BB
+#define DDR_PHY_ZQ0PR0_ZSEGBYP_SHIFT                                               27
+#define DDR_PHY_ZQ0PR0_ZSEGBYP_MASK                                                0x08000000U
+
+/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZLE_MODE_MASK 
+#define DDR_PHY_ZQ0PR0_ZLE_MODE_DEFVAL                                             0x000077BB
+#define DDR_PHY_ZQ0PR0_ZLE_MODE_SHIFT                                              25
+#define DDR_PHY_ZQ0PR0_ZLE_MODE_MASK                                               0x06000000U
+
+/*Termination adjustment*/
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK 
+#define DDR_PHY_ZQ0PR0_ODT_ADJUST_DEFVAL                                           0x000077BB
+#define DDR_PHY_ZQ0PR0_ODT_ADJUST_SHIFT                                            22
+#define DDR_PHY_ZQ0PR0_ODT_ADJUST_MASK                                             0x01C00000U
+
+/*Pulldown drive strength adjustment*/
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_DEFVAL                                        0x000077BB
+#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_SHIFT                                         19
+#define DDR_PHY_ZQ0PR0_PD_DRV_ADJUST_MASK                                          0x00380000U
+
+/*Pullup drive strength adjustment*/
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_DEFVAL                                        0x000077BB
+#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_SHIFT                                         16
+#define DDR_PHY_ZQ0PR0_PU_DRV_ADJUST_MASK                                          0x00070000U
+
+/*DRAM Impedance Divide Ratio*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_DEFVAL                                       0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_SHIFT                                        12
+#define DDR_PHY_ZQ0PR0_ZPROG_DRAM_ODT_MASK                                         0x0000F000U
+
+/*HOST Impedance Divide Ratio*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_DEFVAL                                       0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_SHIFT                                        8
+#define DDR_PHY_ZQ0PR0_ZPROG_HOST_ODT_MASK                                         0x00000F00U
+
+/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_DEFVAL                                    0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_SHIFT                                     4
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PD_MASK                                      0x000000F0U
+
+/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT 
+#undef DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK 
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_DEFVAL                                    0x000077BB
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_SHIFT                                     0
+#define DDR_PHY_ZQ0PR0_ZPROG_ASYM_DRV_PU_MASK                                      0x0000000FU
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT 
+#undef DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK 
+#define DDR_PHY_ZQ0OR0_RESERVED_31_26_DEFVAL                                       0x00000000
+#define DDR_PHY_ZQ0OR0_RESERVED_31_26_SHIFT                                        26
+#define DDR_PHY_ZQ0OR0_RESERVED_31_26_MASK                                         0xFC000000U
+
+/*Override value for the pull-up output impedance*/
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK 
+#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_DEFVAL                                    0x00000000
+#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_SHIFT                                     16
+#define DDR_PHY_ZQ0OR0_ZDATA_PU_DRV_OVRD_MASK                                      0x03FF0000U
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT 
+#undef DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK 
+#define DDR_PHY_ZQ0OR0_RESERVED_15_10_DEFVAL                                       0x00000000
+#define DDR_PHY_ZQ0OR0_RESERVED_15_10_SHIFT                                        10
+#define DDR_PHY_ZQ0OR0_RESERVED_15_10_MASK                                         0x0000FC00U
+
+/*Override value for the pull-down output impedance*/
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK 
+#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_DEFVAL                                    0x00000000
+#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_SHIFT                                     0
+#define DDR_PHY_ZQ0OR0_ZDATA_PD_DRV_OVRD_MASK                                      0x000003FFU
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT 
+#undef DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK 
+#define DDR_PHY_ZQ0OR1_RESERVED_31_26_DEFVAL                                       0x00000000
+#define DDR_PHY_ZQ0OR1_RESERVED_31_26_SHIFT                                        26
+#define DDR_PHY_ZQ0OR1_RESERVED_31_26_MASK                                         0xFC000000U
+
+/*Override value for the pull-up termination*/
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK 
+#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_DEFVAL                                    0x00000000
+#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_SHIFT                                     16
+#define DDR_PHY_ZQ0OR1_ZDATA_PU_ODT_OVRD_MASK                                      0x03FF0000U
+
+/*Reserved. Return zeros on reads.*/
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT 
+#undef DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK 
+#define DDR_PHY_ZQ0OR1_RESERVED_15_10_DEFVAL                                       0x00000000
+#define DDR_PHY_ZQ0OR1_RESERVED_15_10_SHIFT                                        10
+#define DDR_PHY_ZQ0OR1_RESERVED_15_10_MASK                                         0x0000FC00U
+
+/*Override value for the pull-down termination*/
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT 
+#undef DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK 
+#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_DEFVAL                                    0x00000000
+#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_SHIFT                                     0
+#define DDR_PHY_ZQ0OR1_ZDATA_PD_ODT_OVRD_MASK                                      0x000003FFU
+
+/*Pull-down drive strength ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_SHIFT                                           31
+#define DDR_PHY_ZQ1PR0_PD_DRV_ZDEN_MASK                                            0x80000000U
+
+/*Pull-up drive strength ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_SHIFT                                           30
+#define DDR_PHY_ZQ1PR0_PU_DRV_ZDEN_MASK                                            0x40000000U
+
+/*Pull-down termination ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_SHIFT                                           29
+#define DDR_PHY_ZQ1PR0_PD_ODT_ZDEN_MASK                                            0x20000000U
+
+/*Pull-up termination ZCTRL over-ride enable*/
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK 
+#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_DEFVAL                                          0x000077BB
+#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_SHIFT                                           28
+#define DDR_PHY_ZQ1PR0_PU_ODT_ZDEN_MASK                                            0x10000000U
+
+/*Calibration segment bypass*/
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZSEGBYP_MASK 
+#define DDR_PHY_ZQ1PR0_ZSEGBYP_DEFVAL                                              0x000077BB
+#define DDR_PHY_ZQ1PR0_ZSEGBYP_SHIFT                                               27
+#define DDR_PHY_ZQ1PR0_ZSEGBYP_MASK                                                0x08000000U
+
+/*VREF latch mode controls the mode in which the ZLE pin of the PVREF cell is driven by the PUB*/
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZLE_MODE_MASK 
+#define DDR_PHY_ZQ1PR0_ZLE_MODE_DEFVAL                                             0x000077BB
+#define DDR_PHY_ZQ1PR0_ZLE_MODE_SHIFT                                              25
+#define DDR_PHY_ZQ1PR0_ZLE_MODE_MASK                                               0x06000000U
+
+/*Termination adjustment*/
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK 
+#define DDR_PHY_ZQ1PR0_ODT_ADJUST_DEFVAL                                           0x000077BB
+#define DDR_PHY_ZQ1PR0_ODT_ADJUST_SHIFT                                            22
+#define DDR_PHY_ZQ1PR0_ODT_ADJUST_MASK                                             0x01C00000U
+
+/*Pulldown drive strength adjustment*/
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_DEFVAL                                        0x000077BB
+#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_SHIFT                                         19
+#define DDR_PHY_ZQ1PR0_PD_DRV_ADJUST_MASK                                          0x00380000U
+
+/*Pullup drive strength adjustment*/
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT 
+#undef DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK 
+#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_DEFVAL                                        0x000077BB
+#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_SHIFT                                         16
+#define DDR_PHY_ZQ1PR0_PU_DRV_ADJUST_MASK                                          0x00070000U
+
+/*DRAM Impedance Divide Ratio*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_DEFVAL                                       0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_SHIFT                                        12
+#define DDR_PHY_ZQ1PR0_ZPROG_DRAM_ODT_MASK                                         0x0000F000U
+
+/*HOST Impedance Divide Ratio*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_DEFVAL                                       0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_SHIFT                                        8
+#define DDR_PHY_ZQ1PR0_ZPROG_HOST_ODT_MASK                                         0x00000F00U
+
+/*Impedance Divide Ratio (pulldown drive calibration during asymmetric drive strength calibration)*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_DEFVAL                                    0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_SHIFT                                     4
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PD_MASK                                      0x000000F0U
+
+/*Impedance Divide Ratio (pullup drive calibration during asymmetric drive strength calibration)*/
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT 
+#undef DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK 
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_DEFVAL                                    0x000077BB
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_SHIFT                                     0
+#define DDR_PHY_ZQ1PR0_ZPROG_ASYM_DRV_PU_MASK                                      0x0000000FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX0GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX0GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX0GCR0_CALBYP_MASK 
+#define DDR_PHY_DX0GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX0GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX0GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX0GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX0GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX0GCR0_MDLEN_MASK 
+#define DDR_PHY_DX0GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX0GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX0GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX0GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX0GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX0GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX0GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX0GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX0GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX0GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX0GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX0GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX0GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX0GCR0_RDDLY_MASK 
+#define DDR_PHY_DX0GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX0GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX0GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX0GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX0GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX0GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX0GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX0GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX0GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX0GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX0GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX0GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX0GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX0GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX0GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX0GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX0GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX0GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX0GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX0GCR0_RTTOH_MASK 
+#define DDR_PHY_DX0GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX0GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX0GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX0GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX0GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX0GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX0GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX0GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX0GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX0GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX0GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX0GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX0GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX0GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX0GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX0GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX0GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX0GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX0GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX0GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX0GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX0GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX0GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX0GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX0GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX0GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX0GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX0GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX0GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX0GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX0GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX0GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX0GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX0GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX0GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX0GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX0GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX0GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX0GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX0GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX0GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX0GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX0GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX0GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX0GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX0GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX0GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX0GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX0GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX0GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX0GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX0GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX0GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX0GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX0GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX0GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX0GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX0GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX0GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX0GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX0GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX0GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX0GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX0GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX0GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX0GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX0GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX0GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX0GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX0GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX0GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX0GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX0GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX0GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX0GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX0GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX0GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX0GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX0GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX0GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX0GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX0GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX0GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX0GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX0GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX0GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX0GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX0GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX0GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX0GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX0GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX0LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX0LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX0LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX0LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX0LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX0LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX0LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX0LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX0GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX0GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX0GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX0GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX0GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX0GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX0GTR0_WDQSL_MASK 
+#define DDR_PHY_DX0GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX0GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX0GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX0GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX0GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX0GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX0GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX0GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX0GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX0GTR0_WLSL_MASK 
+#define DDR_PHY_DX0GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX0GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX0GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX0GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX0GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX0GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX0GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX0GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX0GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX0GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX0GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX0GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX0GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX0GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX0GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX0GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX0GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX0GTR0_DGSL_MASK 
+#define DDR_PHY_DX0GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX0GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX0GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX1GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX1GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX1GCR0_CALBYP_MASK 
+#define DDR_PHY_DX1GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX1GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX1GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX1GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX1GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX1GCR0_MDLEN_MASK 
+#define DDR_PHY_DX1GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX1GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX1GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX1GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX1GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX1GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX1GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX1GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX1GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX1GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX1GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX1GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX1GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX1GCR0_RDDLY_MASK 
+#define DDR_PHY_DX1GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX1GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX1GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX1GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX1GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX1GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX1GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX1GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX1GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX1GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX1GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX1GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX1GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX1GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX1GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX1GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX1GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX1GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX1GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX1GCR0_RTTOH_MASK 
+#define DDR_PHY_DX1GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX1GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX1GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX1GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX1GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX1GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX1GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX1GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX1GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX1GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX1GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX1GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX1GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX1GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX1GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX1GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX1GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX1GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX1GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX1GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX1GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX1GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX1GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX1GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX1GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX1GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX1GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX1GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX1GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX1GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX1GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX1GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX1GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX1GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX1GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX1GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX1GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX1GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX1GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX1GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX1GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX1GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX1GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX1GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX1GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX1GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX1GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX1GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX1GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX1GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX1GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX1GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX1GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX1GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX1GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX1GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX1GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX1GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX1GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX1GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX1GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX1GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX1GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX1GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX1GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX1GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX1GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX1GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX1GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX1GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX1GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX1GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX1GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX1GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX1GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX1GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX1GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX1GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX1GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX1GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX1GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX1GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX1GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX1GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX1GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX1GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX1GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX1GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX1GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX1GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX1GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX1LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX1LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX1LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX1LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX1LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX1LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX1LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX1LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX1GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX1GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX1GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX1GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX1GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX1GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX1GTR0_WDQSL_MASK 
+#define DDR_PHY_DX1GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX1GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX1GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX1GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX1GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX1GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX1GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX1GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX1GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX1GTR0_WLSL_MASK 
+#define DDR_PHY_DX1GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX1GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX1GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX1GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX1GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX1GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX1GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX1GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX1GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX1GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX1GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX1GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX1GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX1GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX1GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX1GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX1GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX1GTR0_DGSL_MASK 
+#define DDR_PHY_DX1GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX1GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX1GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX2GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX2GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX2GCR0_CALBYP_MASK 
+#define DDR_PHY_DX2GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX2GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX2GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX2GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX2GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX2GCR0_MDLEN_MASK 
+#define DDR_PHY_DX2GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX2GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX2GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX2GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX2GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX2GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX2GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX2GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX2GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX2GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX2GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX2GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX2GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX2GCR0_RDDLY_MASK 
+#define DDR_PHY_DX2GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX2GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX2GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX2GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX2GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX2GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX2GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX2GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX2GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX2GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX2GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX2GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX2GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX2GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX2GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX2GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX2GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX2GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX2GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX2GCR0_RTTOH_MASK 
+#define DDR_PHY_DX2GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX2GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX2GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX2GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX2GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX2GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX2GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX2GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX2GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX2GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX2GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX2GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX2GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX2GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX2GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX2GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX2GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX2GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX2GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX2GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX2GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX2GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX2GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX2GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX2GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX2GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX2GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX2GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX2GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX2GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX2GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX2GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX2GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX2GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX2GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX2GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX2GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX2GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX2GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX2GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX2GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX2GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX2GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX2GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX2GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX2GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX2GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX2GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX2GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX2GCR1_QSSEL_MASK 
+#define DDR_PHY_DX2GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX2GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX2GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX2GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_OEEN_MASK 
+#define DDR_PHY_DX2GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX2GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX2GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX2GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX2GCR1_PDREN_MASK 
+#define DDR_PHY_DX2GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX2GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX2GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX2GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_TEEN_MASK 
+#define DDR_PHY_DX2GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX2GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX2GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX2GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_DSEN_MASK 
+#define DDR_PHY_DX2GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX2GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX2GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX2GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_DMEN_MASK 
+#define DDR_PHY_DX2GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX2GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX2GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX2GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX2GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX2GCR1_DQEN_MASK 
+#define DDR_PHY_DX2GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX2GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX2GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX2GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX2GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX2GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX2GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX2GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX2GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX2GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX2GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX2GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX2GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX2GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX2GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX2GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX2GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX2GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX2GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX2GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX2GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX2GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX2GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX2GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX2GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX2GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX2GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX2GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX2GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX2GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX2GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX2GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX2GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX2GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX2GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX2GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX2GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX2GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX2GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX2GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX2GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX2GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX2GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX2GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX2GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX2GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX2GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX2GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX2GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX2GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX2GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX2GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX2GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX2GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX2GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX2GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX2GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX2GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX2GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX2GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX2GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX2GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX2LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX2LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX2LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX2LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX2LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX2LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX2LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX2LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX2GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX2GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX2GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX2GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX2GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX2GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX2GTR0_WDQSL_MASK 
+#define DDR_PHY_DX2GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX2GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX2GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX2GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX2GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX2GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX2GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX2GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX2GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX2GTR0_WLSL_MASK 
+#define DDR_PHY_DX2GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX2GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX2GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX2GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX2GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX2GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX2GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX2GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX2GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX2GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX2GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX2GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX2GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX2GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX2GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX2GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX2GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX2GTR0_DGSL_MASK 
+#define DDR_PHY_DX2GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX2GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX2GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX3GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX3GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX3GCR0_CALBYP_MASK 
+#define DDR_PHY_DX3GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX3GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX3GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX3GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX3GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX3GCR0_MDLEN_MASK 
+#define DDR_PHY_DX3GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX3GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX3GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX3GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX3GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX3GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX3GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX3GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX3GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX3GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX3GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX3GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX3GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX3GCR0_RDDLY_MASK 
+#define DDR_PHY_DX3GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX3GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX3GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX3GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX3GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX3GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX3GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX3GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX3GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX3GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX3GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX3GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX3GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX3GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX3GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX3GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX3GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX3GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX3GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX3GCR0_RTTOH_MASK 
+#define DDR_PHY_DX3GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX3GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX3GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX3GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX3GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX3GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX3GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX3GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX3GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX3GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX3GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX3GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX3GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX3GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX3GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX3GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX3GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX3GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX3GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX3GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX3GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX3GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX3GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX3GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX3GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX3GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX3GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX3GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX3GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX3GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX3GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX3GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX3GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX3GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX3GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX3GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX3GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX3GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX3GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX3GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX3GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX3GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX3GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX3GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX3GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX3GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX3GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX3GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX3GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX3GCR1_QSSEL_MASK 
+#define DDR_PHY_DX3GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX3GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX3GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX3GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_OEEN_MASK 
+#define DDR_PHY_DX3GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX3GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX3GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX3GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX3GCR1_PDREN_MASK 
+#define DDR_PHY_DX3GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX3GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX3GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX3GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_TEEN_MASK 
+#define DDR_PHY_DX3GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX3GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX3GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX3GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_DSEN_MASK 
+#define DDR_PHY_DX3GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX3GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX3GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX3GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_DMEN_MASK 
+#define DDR_PHY_DX3GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX3GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX3GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX3GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX3GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX3GCR1_DQEN_MASK 
+#define DDR_PHY_DX3GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX3GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX3GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX3GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX3GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX3GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX3GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX3GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX3GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX3GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX3GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX3GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX3GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX3GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX3GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX3GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX3GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX3GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX3GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX3GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX3GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX3GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX3GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX3GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX3GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX3GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX3GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX3GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX3GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX3GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX3GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX3GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX3GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX3GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX3GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX3GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX3GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX3GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX3GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX3GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX3GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX3GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX3GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX3GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX3GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX3GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX3GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX3GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX3GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX3GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX3GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX3GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX3GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX3GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX3GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX3GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX3GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX3GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX3GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX3GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX3GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX3GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX3LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX3LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX3LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX3LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX3LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX3LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX3LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX3LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX3GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX3GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX3GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX3GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX3GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX3GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX3GTR0_WDQSL_MASK 
+#define DDR_PHY_DX3GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX3GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX3GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX3GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX3GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX3GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX3GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX3GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX3GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX3GTR0_WLSL_MASK 
+#define DDR_PHY_DX3GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX3GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX3GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX3GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX3GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX3GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX3GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX3GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX3GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX3GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX3GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX3GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX3GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX3GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX3GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX3GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX3GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX3GTR0_DGSL_MASK 
+#define DDR_PHY_DX3GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX3GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX3GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX4GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX4GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX4GCR0_CALBYP_MASK 
+#define DDR_PHY_DX4GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX4GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX4GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX4GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX4GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX4GCR0_MDLEN_MASK 
+#define DDR_PHY_DX4GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX4GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX4GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX4GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX4GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX4GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX4GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX4GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX4GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX4GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX4GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX4GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX4GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX4GCR0_RDDLY_MASK 
+#define DDR_PHY_DX4GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX4GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX4GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX4GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX4GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX4GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX4GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX4GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX4GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX4GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX4GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX4GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX4GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX4GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX4GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX4GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX4GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX4GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX4GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX4GCR0_RTTOH_MASK 
+#define DDR_PHY_DX4GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX4GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX4GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX4GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX4GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX4GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX4GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX4GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX4GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX4GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX4GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX4GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX4GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX4GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX4GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX4GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX4GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX4GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX4GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX4GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX4GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX4GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX4GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX4GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX4GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX4GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX4GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX4GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX4GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX4GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX4GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX4GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX4GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX4GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX4GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX4GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX4GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX4GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX4GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX4GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX4GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX4GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX4GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX4GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX4GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX4GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX4GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX4GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX4GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX4GCR1_QSSEL_MASK 
+#define DDR_PHY_DX4GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX4GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX4GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX4GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_OEEN_MASK 
+#define DDR_PHY_DX4GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX4GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX4GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX4GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX4GCR1_PDREN_MASK 
+#define DDR_PHY_DX4GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX4GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX4GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX4GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_TEEN_MASK 
+#define DDR_PHY_DX4GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX4GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX4GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX4GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_DSEN_MASK 
+#define DDR_PHY_DX4GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX4GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX4GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX4GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_DMEN_MASK 
+#define DDR_PHY_DX4GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX4GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX4GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX4GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX4GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX4GCR1_DQEN_MASK 
+#define DDR_PHY_DX4GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX4GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX4GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX4GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX4GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX4GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX4GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX4GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX4GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX4GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX4GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX4GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX4GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX4GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX4GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX4GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX4GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX4GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX4GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX4GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX4GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX4GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX4GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX4GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX4GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX4GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX4GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX4GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX4GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX4GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX4GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX4GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX4GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX4GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX4GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX4GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX4GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX4GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX4GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX4GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX4GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX4GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX4GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX4GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX4GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX4GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX4GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX4GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX4GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX4GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX4GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX4GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX4GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX4GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX4GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX4GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX4GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX4GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX4GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX4GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX4GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX4GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX4LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX4LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX4LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX4LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX4LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX4LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX4LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX4LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX4GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX4GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX4GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX4GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX4GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX4GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX4GTR0_WDQSL_MASK 
+#define DDR_PHY_DX4GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX4GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX4GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX4GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX4GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX4GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX4GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX4GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX4GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX4GTR0_WLSL_MASK 
+#define DDR_PHY_DX4GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX4GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX4GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX4GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX4GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX4GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX4GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX4GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX4GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX4GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX4GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX4GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX4GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX4GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX4GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX4GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX4GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX4GTR0_DGSL_MASK 
+#define DDR_PHY_DX4GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX4GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX4GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX5GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX5GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX5GCR0_CALBYP_MASK 
+#define DDR_PHY_DX5GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX5GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX5GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX5GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX5GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX5GCR0_MDLEN_MASK 
+#define DDR_PHY_DX5GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX5GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX5GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX5GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX5GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX5GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX5GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX5GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX5GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX5GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX5GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX5GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX5GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX5GCR0_RDDLY_MASK 
+#define DDR_PHY_DX5GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX5GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX5GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX5GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX5GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX5GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX5GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX5GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX5GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX5GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX5GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX5GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX5GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX5GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX5GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX5GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX5GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX5GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX5GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX5GCR0_RTTOH_MASK 
+#define DDR_PHY_DX5GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX5GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX5GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX5GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX5GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX5GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX5GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX5GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX5GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX5GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX5GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX5GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX5GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX5GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX5GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX5GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX5GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX5GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX5GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX5GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX5GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX5GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX5GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX5GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX5GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX5GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX5GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX5GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX5GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX5GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX5GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX5GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX5GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX5GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX5GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX5GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX5GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX5GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX5GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX5GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX5GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX5GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX5GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX5GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX5GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX5GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX5GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX5GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX5GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX5GCR1_QSSEL_MASK 
+#define DDR_PHY_DX5GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX5GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX5GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX5GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_OEEN_MASK 
+#define DDR_PHY_DX5GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX5GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX5GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX5GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX5GCR1_PDREN_MASK 
+#define DDR_PHY_DX5GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX5GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX5GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX5GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_TEEN_MASK 
+#define DDR_PHY_DX5GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX5GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX5GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX5GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_DSEN_MASK 
+#define DDR_PHY_DX5GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX5GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX5GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX5GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_DMEN_MASK 
+#define DDR_PHY_DX5GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX5GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX5GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX5GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX5GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX5GCR1_DQEN_MASK 
+#define DDR_PHY_DX5GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX5GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX5GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX5GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX5GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX5GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX5GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX5GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX5GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX5GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX5GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX5GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX5GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX5GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX5GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX5GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX5GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX5GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX5GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX5GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX5GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX5GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX5GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX5GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX5GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX5GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX5GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX5GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX5GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX5GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX5GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX5GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX5GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX5GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX5GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX5GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX5GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX5GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX5GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX5GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX5GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX5GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX5GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX5GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX5GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX5GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX5GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX5GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX5GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX5GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX5GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX5GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX5GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX5GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX5GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX5GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX5GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX5GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX5GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX5GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX5GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX5GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX5LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX5LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX5LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX5LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX5LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX5LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX5LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX5LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX5GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX5GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX5GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX5GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX5GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX5GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX5GTR0_WDQSL_MASK 
+#define DDR_PHY_DX5GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX5GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX5GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX5GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX5GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX5GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX5GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX5GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX5GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX5GTR0_WLSL_MASK 
+#define DDR_PHY_DX5GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX5GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX5GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX5GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX5GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX5GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX5GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX5GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX5GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX5GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX5GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX5GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX5GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX5GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX5GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX5GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX5GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX5GTR0_DGSL_MASK 
+#define DDR_PHY_DX5GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX5GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX5GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX6GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX6GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX6GCR0_CALBYP_MASK 
+#define DDR_PHY_DX6GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX6GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX6GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX6GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX6GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX6GCR0_MDLEN_MASK 
+#define DDR_PHY_DX6GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX6GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX6GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX6GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX6GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX6GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX6GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX6GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX6GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX6GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX6GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX6GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX6GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX6GCR0_RDDLY_MASK 
+#define DDR_PHY_DX6GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX6GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX6GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX6GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX6GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX6GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX6GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX6GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX6GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX6GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX6GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX6GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX6GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX6GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX6GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX6GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX6GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX6GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX6GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX6GCR0_RTTOH_MASK 
+#define DDR_PHY_DX6GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX6GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX6GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX6GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX6GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX6GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX6GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX6GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX6GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX6GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX6GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX6GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX6GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX6GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX6GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX6GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX6GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX6GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX6GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX6GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX6GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX6GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX6GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX6GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX6GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX6GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX6GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX6GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX6GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX6GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX6GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX6GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX6GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX6GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX6GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX6GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX6GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX6GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX6GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX6GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX6GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX6GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX6GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX6GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX6GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX6GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX6GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX6GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX6GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX6GCR1_QSSEL_MASK 
+#define DDR_PHY_DX6GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX6GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX6GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX6GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_OEEN_MASK 
+#define DDR_PHY_DX6GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX6GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX6GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX6GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX6GCR1_PDREN_MASK 
+#define DDR_PHY_DX6GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX6GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX6GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX6GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_TEEN_MASK 
+#define DDR_PHY_DX6GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX6GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX6GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX6GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_DSEN_MASK 
+#define DDR_PHY_DX6GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX6GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX6GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX6GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_DMEN_MASK 
+#define DDR_PHY_DX6GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX6GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX6GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX6GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX6GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX6GCR1_DQEN_MASK 
+#define DDR_PHY_DX6GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX6GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX6GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX6GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX6GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX6GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX6GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX6GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX6GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX6GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX6GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX6GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX6GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX6GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX6GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX6GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX6GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX6GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX6GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX6GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX6GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX6GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX6GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX6GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX6GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX6GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX6GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX6GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX6GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX6GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX6GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX6GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX6GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX6GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX6GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX6GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX6GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX6GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX6GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX6GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX6GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX6GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX6GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX6GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX6GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX6GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX6GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX6GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX6GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX6GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX6GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX6GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX6GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX6GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX6GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX6GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX6GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX6GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX6GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX6GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX6GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX6GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX6LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX6LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX6LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX6LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX6LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX6LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX6LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX6LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX6GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX6GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX6GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX6GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX6GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX6GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX6GTR0_WDQSL_MASK 
+#define DDR_PHY_DX6GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX6GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX6GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX6GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX6GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX6GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX6GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX6GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX6GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX6GTR0_WLSL_MASK 
+#define DDR_PHY_DX6GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX6GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX6GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX6GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX6GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX6GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX6GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX6GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX6GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX6GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX6GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX6GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX6GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX6GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX6GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX6GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX6GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX6GTR0_DGSL_MASK 
+#define DDR_PHY_DX6GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX6GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX6GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX7GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX7GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX7GCR0_CALBYP_MASK 
+#define DDR_PHY_DX7GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX7GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX7GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX7GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX7GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX7GCR0_MDLEN_MASK 
+#define DDR_PHY_DX7GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX7GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX7GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX7GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX7GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX7GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX7GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX7GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX7GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX7GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX7GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX7GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX7GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX7GCR0_RDDLY_MASK 
+#define DDR_PHY_DX7GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX7GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX7GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX7GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX7GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX7GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX7GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX7GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX7GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX7GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX7GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX7GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX7GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX7GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX7GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX7GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX7GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX7GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX7GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX7GCR0_RTTOH_MASK 
+#define DDR_PHY_DX7GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX7GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX7GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX7GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX7GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX7GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX7GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX7GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX7GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX7GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX7GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX7GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX7GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX7GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX7GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX7GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX7GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX7GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX7GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX7GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX7GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX7GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX7GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX7GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX7GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX7GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX7GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX7GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX7GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX7GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX7GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX7GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX7GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX7GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX7GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX7GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX7GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX7GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX7GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX7GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX7GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX7GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX7GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX7GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX7GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX7GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX7GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX7GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX7GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX7GCR1_QSSEL_MASK 
+#define DDR_PHY_DX7GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX7GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX7GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX7GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_OEEN_MASK 
+#define DDR_PHY_DX7GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX7GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX7GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX7GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX7GCR1_PDREN_MASK 
+#define DDR_PHY_DX7GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX7GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX7GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX7GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_TEEN_MASK 
+#define DDR_PHY_DX7GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX7GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX7GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX7GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_DSEN_MASK 
+#define DDR_PHY_DX7GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX7GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX7GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX7GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_DMEN_MASK 
+#define DDR_PHY_DX7GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX7GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX7GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX7GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX7GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX7GCR1_DQEN_MASK 
+#define DDR_PHY_DX7GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX7GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX7GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX7GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX7GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX7GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX7GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX7GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX7GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX7GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX7GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX7GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX7GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX7GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX7GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX7GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX7GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX7GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX7GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX7GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX7GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX7GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX7GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX7GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX7GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX7GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX7GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX7GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX7GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX7GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX7GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX7GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX7GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX7GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX7GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX7GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX7GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX7GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX7GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX7GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX7GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX7GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX7GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX7GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX7GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX7GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX7GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX7GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX7GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX7GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX7GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX7GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX7GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX7GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX7GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX7GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX7GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX7GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX7GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX7GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX7GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX7GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX7LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX7LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX7LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX7LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX7LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX7LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX7LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX7LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX7GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX7GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX7GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX7GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX7GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX7GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX7GTR0_WDQSL_MASK 
+#define DDR_PHY_DX7GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX7GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX7GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX7GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX7GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX7GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX7GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX7GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX7GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX7GTR0_WLSL_MASK 
+#define DDR_PHY_DX7GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX7GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX7GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX7GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX7GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX7GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX7GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX7GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX7GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX7GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX7GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX7GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX7GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX7GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX7GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX7GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX7GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX7GTR0_DGSL_MASK 
+#define DDR_PHY_DX7GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX7GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX7GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Calibration Bypass*/
+#undef DDR_PHY_DX8GCR0_CALBYP_DEFVAL 
+#undef DDR_PHY_DX8GCR0_CALBYP_SHIFT 
+#undef DDR_PHY_DX8GCR0_CALBYP_MASK 
+#define DDR_PHY_DX8GCR0_CALBYP_DEFVAL                                              0x40200204
+#define DDR_PHY_DX8GCR0_CALBYP_SHIFT                                               31
+#define DDR_PHY_DX8GCR0_CALBYP_MASK                                                0x80000000U
+
+/*Master Delay Line Enable*/
+#undef DDR_PHY_DX8GCR0_MDLEN_DEFVAL 
+#undef DDR_PHY_DX8GCR0_MDLEN_SHIFT 
+#undef DDR_PHY_DX8GCR0_MDLEN_MASK 
+#define DDR_PHY_DX8GCR0_MDLEN_DEFVAL                                               0x40200204
+#define DDR_PHY_DX8GCR0_MDLEN_SHIFT                                                30
+#define DDR_PHY_DX8GCR0_MDLEN_MASK                                                 0x40000000U
+
+/*Configurable ODT(TE) Phase Shift*/
+#undef DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL 
+#undef DDR_PHY_DX8GCR0_CODTSHFT_SHIFT 
+#undef DDR_PHY_DX8GCR0_CODTSHFT_MASK 
+#define DDR_PHY_DX8GCR0_CODTSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX8GCR0_CODTSHFT_SHIFT                                             28
+#define DDR_PHY_DX8GCR0_CODTSHFT_MASK                                              0x30000000U
+
+/*DQS Duty Cycle Correction*/
+#undef DDR_PHY_DX8GCR0_DQSDCC_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSDCC_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSDCC_MASK 
+#define DDR_PHY_DX8GCR0_DQSDCC_DEFVAL                                              0x40200204
+#define DDR_PHY_DX8GCR0_DQSDCC_SHIFT                                               24
+#define DDR_PHY_DX8GCR0_DQSDCC_MASK                                                0x0F000000U
+
+/*Number of Cycles ( in terms of ctl_clk) to generate ctl_dx_get_static_rd input for the respective bypte lane of the PHY*/
+#undef DDR_PHY_DX8GCR0_RDDLY_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RDDLY_SHIFT 
+#undef DDR_PHY_DX8GCR0_RDDLY_MASK 
+#define DDR_PHY_DX8GCR0_RDDLY_DEFVAL                                               0x40200204
+#define DDR_PHY_DX8GCR0_RDDLY_SHIFT                                                20
+#define DDR_PHY_DX8GCR0_RDDLY_MASK                                                 0x00F00000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT 
+#undef DDR_PHY_DX8GCR0_RESERVED_19_14_MASK 
+#define DDR_PHY_DX8GCR0_RESERVED_19_14_DEFVAL                                      0x40200204
+#define DDR_PHY_DX8GCR0_RESERVED_19_14_SHIFT                                       14
+#define DDR_PHY_DX8GCR0_RESERVED_19_14_MASK                                        0x000FC000U
+
+/*DQSNSE Power Down Receiver*/
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSNSEPDR_MASK 
+#define DDR_PHY_DX8GCR0_DQSNSEPDR_DEFVAL                                           0x40200204
+#define DDR_PHY_DX8GCR0_DQSNSEPDR_SHIFT                                            13
+#define DDR_PHY_DX8GCR0_DQSNSEPDR_MASK                                             0x00002000U
+
+/*DQSSE Power Down Receiver*/
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSSEPDR_MASK 
+#define DDR_PHY_DX8GCR0_DQSSEPDR_DEFVAL                                            0x40200204
+#define DDR_PHY_DX8GCR0_DQSSEPDR_SHIFT                                             12
+#define DDR_PHY_DX8GCR0_DQSSEPDR_MASK                                              0x00001000U
+
+/*RTT On Additive Latency*/
+#undef DDR_PHY_DX8GCR0_RTTOAL_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RTTOAL_SHIFT 
+#undef DDR_PHY_DX8GCR0_RTTOAL_MASK 
+#define DDR_PHY_DX8GCR0_RTTOAL_DEFVAL                                              0x40200204
+#define DDR_PHY_DX8GCR0_RTTOAL_SHIFT                                               11
+#define DDR_PHY_DX8GCR0_RTTOAL_MASK                                                0x00000800U
+
+/*RTT Output Hold*/
+#undef DDR_PHY_DX8GCR0_RTTOH_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RTTOH_SHIFT 
+#undef DDR_PHY_DX8GCR0_RTTOH_MASK 
+#define DDR_PHY_DX8GCR0_RTTOH_DEFVAL                                               0x40200204
+#define DDR_PHY_DX8GCR0_RTTOH_SHIFT                                                9
+#define DDR_PHY_DX8GCR0_RTTOH_MASK                                                 0x00000600U
+
+/*Configurable PDR Phase Shift*/
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL 
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT 
+#undef DDR_PHY_DX8GCR0_CPDRSHFT_MASK 
+#define DDR_PHY_DX8GCR0_CPDRSHFT_DEFVAL                                            0x40200204
+#define DDR_PHY_DX8GCR0_CPDRSHFT_SHIFT                                             7
+#define DDR_PHY_DX8GCR0_CPDRSHFT_MASK                                              0x00000180U
+
+/*DQSR Power Down*/
+#undef DDR_PHY_DX8GCR0_DQSRPD_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSRPD_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSRPD_MASK 
+#define DDR_PHY_DX8GCR0_DQSRPD_DEFVAL                                              0x40200204
+#define DDR_PHY_DX8GCR0_DQSRPD_SHIFT                                               6
+#define DDR_PHY_DX8GCR0_DQSRPD_MASK                                                0x00000040U
+
+/*DQSG Power Down Receiver*/
+#undef DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSGPDR_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSGPDR_MASK 
+#define DDR_PHY_DX8GCR0_DQSGPDR_DEFVAL                                             0x40200204
+#define DDR_PHY_DX8GCR0_DQSGPDR_SHIFT                                              5
+#define DDR_PHY_DX8GCR0_DQSGPDR_MASK                                               0x00000020U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RESERVED_4_SHIFT 
+#undef DDR_PHY_DX8GCR0_RESERVED_4_MASK 
+#define DDR_PHY_DX8GCR0_RESERVED_4_DEFVAL                                          0x40200204
+#define DDR_PHY_DX8GCR0_RESERVED_4_SHIFT                                           4
+#define DDR_PHY_DX8GCR0_RESERVED_4_MASK                                            0x00000010U
+
+/*DQSG On-Die Termination*/
+#undef DDR_PHY_DX8GCR0_DQSGODT_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSGODT_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSGODT_MASK 
+#define DDR_PHY_DX8GCR0_DQSGODT_DEFVAL                                             0x40200204
+#define DDR_PHY_DX8GCR0_DQSGODT_SHIFT                                              3
+#define DDR_PHY_DX8GCR0_DQSGODT_MASK                                               0x00000008U
+
+/*DQSG Output Enable*/
+#undef DDR_PHY_DX8GCR0_DQSGOE_DEFVAL 
+#undef DDR_PHY_DX8GCR0_DQSGOE_SHIFT 
+#undef DDR_PHY_DX8GCR0_DQSGOE_MASK 
+#define DDR_PHY_DX8GCR0_DQSGOE_DEFVAL                                              0x40200204
+#define DDR_PHY_DX8GCR0_DQSGOE_SHIFT                                               2
+#define DDR_PHY_DX8GCR0_DQSGOE_MASK                                                0x00000004U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL 
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT 
+#undef DDR_PHY_DX8GCR0_RESERVED_1_0_MASK 
+#define DDR_PHY_DX8GCR0_RESERVED_1_0_DEFVAL                                        0x40200204
+#define DDR_PHY_DX8GCR0_RESERVED_1_0_SHIFT                                         0
+#define DDR_PHY_DX8GCR0_RESERVED_1_0_MASK                                          0x00000003U
+
+/*Enables the PDR mode for DQ[7:0]*/
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT 
+#undef DDR_PHY_DX8GCR1_DXPDRMODE_MASK 
+#define DDR_PHY_DX8GCR1_DXPDRMODE_DEFVAL                                           0x00007FFF
+#define DDR_PHY_DX8GCR1_DXPDRMODE_SHIFT                                            16
+#define DDR_PHY_DX8GCR1_DXPDRMODE_MASK                                             0xFFFF0000U
+
+/*Reserved. Returns zeroes on reads.*/
+#undef DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX8GCR1_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX8GCR1_RESERVED_15_MASK 
+#define DDR_PHY_DX8GCR1_RESERVED_15_DEFVAL                                         0x00007FFF
+#define DDR_PHY_DX8GCR1_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX8GCR1_RESERVED_15_MASK                                           0x00008000U
+
+/*Select the delayed or non-delayed read data strobe #*/
+#undef DDR_PHY_DX8GCR1_QSNSEL_DEFVAL 
+#undef DDR_PHY_DX8GCR1_QSNSEL_SHIFT 
+#undef DDR_PHY_DX8GCR1_QSNSEL_MASK 
+#define DDR_PHY_DX8GCR1_QSNSEL_DEFVAL                                              0x00007FFF
+#define DDR_PHY_DX8GCR1_QSNSEL_SHIFT                                               14
+#define DDR_PHY_DX8GCR1_QSNSEL_MASK                                                0x00004000U
+
+/*Select the delayed or non-delayed read data strobe*/
+#undef DDR_PHY_DX8GCR1_QSSEL_DEFVAL 
+#undef DDR_PHY_DX8GCR1_QSSEL_SHIFT 
+#undef DDR_PHY_DX8GCR1_QSSEL_MASK 
+#define DDR_PHY_DX8GCR1_QSSEL_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX8GCR1_QSSEL_SHIFT                                                13
+#define DDR_PHY_DX8GCR1_QSSEL_MASK                                                 0x00002000U
+
+/*Enables Read Data Strobe in a byte lane*/
+#undef DDR_PHY_DX8GCR1_OEEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_OEEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_OEEN_MASK 
+#define DDR_PHY_DX8GCR1_OEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX8GCR1_OEEN_SHIFT                                                 12
+#define DDR_PHY_DX8GCR1_OEEN_MASK                                                  0x00001000U
+
+/*Enables PDR in a byte lane*/
+#undef DDR_PHY_DX8GCR1_PDREN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_PDREN_SHIFT 
+#undef DDR_PHY_DX8GCR1_PDREN_MASK 
+#define DDR_PHY_DX8GCR1_PDREN_DEFVAL                                               0x00007FFF
+#define DDR_PHY_DX8GCR1_PDREN_SHIFT                                                11
+#define DDR_PHY_DX8GCR1_PDREN_MASK                                                 0x00000800U
+
+/*Enables ODT/TE in a byte lane*/
+#undef DDR_PHY_DX8GCR1_TEEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_TEEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_TEEN_MASK 
+#define DDR_PHY_DX8GCR1_TEEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX8GCR1_TEEN_SHIFT                                                 10
+#define DDR_PHY_DX8GCR1_TEEN_MASK                                                  0x00000400U
+
+/*Enables Write Data strobe in a byte lane*/
+#undef DDR_PHY_DX8GCR1_DSEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DSEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_DSEN_MASK 
+#define DDR_PHY_DX8GCR1_DSEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX8GCR1_DSEN_SHIFT                                                 9
+#define DDR_PHY_DX8GCR1_DSEN_MASK                                                  0x00000200U
+
+/*Enables DM pin in a byte lane*/
+#undef DDR_PHY_DX8GCR1_DMEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DMEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_DMEN_MASK 
+#define DDR_PHY_DX8GCR1_DMEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX8GCR1_DMEN_SHIFT                                                 8
+#define DDR_PHY_DX8GCR1_DMEN_MASK                                                  0x00000100U
+
+/*Enables DQ corresponding to each bit in a byte*/
+#undef DDR_PHY_DX8GCR1_DQEN_DEFVAL 
+#undef DDR_PHY_DX8GCR1_DQEN_SHIFT 
+#undef DDR_PHY_DX8GCR1_DQEN_MASK 
+#define DDR_PHY_DX8GCR1_DQEN_DEFVAL                                                0x00007FFF
+#define DDR_PHY_DX8GCR1_DQEN_SHIFT                                                 0
+#define DDR_PHY_DX8GCR1_DQEN_MASK                                                  0x000000FFU
+
+/*Byte lane VREF IOM (Used only by D4MU IOs)*/
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL 
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT 
+#undef DDR_PHY_DX8GCR4_RESERVED_31_29_MASK 
+#define DDR_PHY_DX8GCR4_RESERVED_31_29_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX8GCR4_RESERVED_31_29_SHIFT                                       29
+#define DDR_PHY_DX8GCR4_RESERVED_31_29_MASK                                        0xE0000000U
+
+/*Byte Lane VREF Pad Enable*/
+#undef DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFPEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFPEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFPEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFPEN_SHIFT                                             28
+#define DDR_PHY_DX8GCR4_DXREFPEN_MASK                                              0x10000000U
+
+/*Byte Lane Internal VREF Enable*/
+#undef DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFEEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFEEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFEEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFEEN_SHIFT                                             26
+#define DDR_PHY_DX8GCR4_DXREFEEN_MASK                                              0x0C000000U
+
+/*Byte Lane Single-End VREF Enable*/
+#undef DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFSEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFSEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFSEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFSEN_SHIFT                                             25
+#define DDR_PHY_DX8GCR4_DXREFSEN_MASK                                              0x02000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL 
+#undef DDR_PHY_DX8GCR4_RESERVED_24_SHIFT 
+#undef DDR_PHY_DX8GCR4_RESERVED_24_MASK 
+#define DDR_PHY_DX8GCR4_RESERVED_24_DEFVAL                                         0x0E00003C
+#define DDR_PHY_DX8GCR4_RESERVED_24_SHIFT                                          24
+#define DDR_PHY_DX8GCR4_RESERVED_24_MASK                                           0x01000000U
+
+/*External VREF generator REFSEL range select*/
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK 
+#define DDR_PHY_DX8GCR4_DXREFESELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFESELRANGE_SHIFT                                       23
+#define DDR_PHY_DX8GCR4_DXREFESELRANGE_MASK                                        0x00800000U
+
+/*Byte Lane External VREF Select*/
+#undef DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFESEL_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFESEL_MASK 
+#define DDR_PHY_DX8GCR4_DXREFESEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFESEL_SHIFT                                            16
+#define DDR_PHY_DX8GCR4_DXREFESEL_MASK                                             0x007F0000U
+
+/*Single ended VREF generator REFSEL range select*/
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK 
+#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_DEFVAL                                      0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_SHIFT                                       15
+#define DDR_PHY_DX8GCR4_DXREFSSELRANGE_MASK                                        0x00008000U
+
+/*Byte Lane Single-End VREF Select*/
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFSSEL_MASK 
+#define DDR_PHY_DX8GCR4_DXREFSSEL_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFSSEL_SHIFT                                            8
+#define DDR_PHY_DX8GCR4_DXREFSSEL_MASK                                             0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX8GCR4_RESERVED_7_6_MASK 
+#define DDR_PHY_DX8GCR4_RESERVED_7_6_DEFVAL                                        0x0E00003C
+#define DDR_PHY_DX8GCR4_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX8GCR4_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*VREF Enable control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFIEN_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFIEN_MASK 
+#define DDR_PHY_DX8GCR4_DXREFIEN_DEFVAL                                            0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFIEN_SHIFT                                             2
+#define DDR_PHY_DX8GCR4_DXREFIEN_MASK                                              0x0000003CU
+
+/*VRMON control for DQ IO (Single Ended) buffers of a byte lane.*/
+#undef DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL 
+#undef DDR_PHY_DX8GCR4_DXREFIMON_SHIFT 
+#undef DDR_PHY_DX8GCR4_DXREFIMON_MASK 
+#define DDR_PHY_DX8GCR4_DXREFIMON_DEFVAL                                           0x0E00003C
+#define DDR_PHY_DX8GCR4_DXREFIMON_SHIFT                                            0
+#define DDR_PHY_DX8GCR4_DXREFIMON_MASK                                             0x00000003U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_31_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_31_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_31_SHIFT                                          31
+#define DDR_PHY_DX8GCR5_RESERVED_31_MASK                                           0x80000000U
+
+/*Byte Lane internal VREF Select for Rank 3*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR3_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR3_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR3_SHIFT                                          24
+#define DDR_PHY_DX8GCR5_DXREFISELR3_MASK                                           0x7F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_23_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_23_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_23_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_23_SHIFT                                          23
+#define DDR_PHY_DX8GCR5_RESERVED_23_MASK                                           0x00800000U
+
+/*Byte Lane internal VREF Select for Rank 2*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR2_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR2_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR2_SHIFT                                          16
+#define DDR_PHY_DX8GCR5_DXREFISELR2_MASK                                           0x007F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_15_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_15_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_15_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_15_SHIFT                                          15
+#define DDR_PHY_DX8GCR5_RESERVED_15_MASK                                           0x00008000U
+
+/*Byte Lane internal VREF Select for Rank 1*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR1_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR1_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR1_SHIFT                                          8
+#define DDR_PHY_DX8GCR5_DXREFISELR1_MASK                                           0x00007F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL 
+#undef DDR_PHY_DX8GCR5_RESERVED_7_SHIFT 
+#undef DDR_PHY_DX8GCR5_RESERVED_7_MASK 
+#define DDR_PHY_DX8GCR5_RESERVED_7_DEFVAL                                          0x09090909
+#define DDR_PHY_DX8GCR5_RESERVED_7_SHIFT                                           7
+#define DDR_PHY_DX8GCR5_RESERVED_7_MASK                                            0x00000080U
+
+/*Byte Lane internal VREF Select for Rank 0*/
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL 
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT 
+#undef DDR_PHY_DX8GCR5_DXREFISELR0_MASK 
+#define DDR_PHY_DX8GCR5_DXREFISELR0_DEFVAL                                         0x09090909
+#define DDR_PHY_DX8GCR5_DXREFISELR0_SHIFT                                          0
+#define DDR_PHY_DX8GCR5_DXREFISELR0_MASK                                           0x0000007FU
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_31_30_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_31_30_DEFVAL                                      0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_31_30_SHIFT                                       30
+#define DDR_PHY_DX8GCR6_RESERVED_31_30_MASK                                        0xC0000000U
+
+/*DRAM DQ VREF Select for Rank3*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR3_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR3_DEFVAL                                          0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR3_SHIFT                                           24
+#define DDR_PHY_DX8GCR6_DXDQVREFR3_MASK                                            0x3F000000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_23_22_DEFVAL                                      0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_23_22_SHIFT                                       22
+#define DDR_PHY_DX8GCR6_RESERVED_23_22_MASK                                        0x00C00000U
+
+/*DRAM DQ VREF Select for Rank2*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR2_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR2_DEFVAL                                          0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR2_SHIFT                                           16
+#define DDR_PHY_DX8GCR6_DXDQVREFR2_MASK                                            0x003F0000U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_15_14_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_15_14_DEFVAL                                      0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_15_14_SHIFT                                       14
+#define DDR_PHY_DX8GCR6_RESERVED_15_14_MASK                                        0x0000C000U
+
+/*DRAM DQ VREF Select for Rank1*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR1_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR1_DEFVAL                                          0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR1_SHIFT                                           8
+#define DDR_PHY_DX8GCR6_DXDQVREFR1_MASK                                            0x00003F00U
+
+/*Reserved. Returns zeros on reads.*/
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL 
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT 
+#undef DDR_PHY_DX8GCR6_RESERVED_7_6_MASK 
+#define DDR_PHY_DX8GCR6_RESERVED_7_6_DEFVAL                                        0x09090909
+#define DDR_PHY_DX8GCR6_RESERVED_7_6_SHIFT                                         6
+#define DDR_PHY_DX8GCR6_RESERVED_7_6_MASK                                          0x000000C0U
+
+/*DRAM DQ VREF Select for Rank0*/
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT 
+#undef DDR_PHY_DX8GCR6_DXDQVREFR0_MASK 
+#define DDR_PHY_DX8GCR6_DXDQVREFR0_DEFVAL                                          0x09090909
+#define DDR_PHY_DX8GCR6_DXDQVREFR0_SHIFT                                           0
+#define DDR_PHY_DX8GCR6_DXDQVREFR0_MASK                                            0x0000003FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_DEFVAL                                    0x00000000
+#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_SHIFT                                     25
+#define DDR_PHY_DX8LCDLR2_RESERVED_31_25_MASK                                      0xFE000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK 
+#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_DEFVAL                                    0x00000000
+#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_SHIFT                                     16
+#define DDR_PHY_DX8LCDLR2_RESERVED_24_16_MASK                                      0x01FF0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT 
+#undef DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK 
+#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_DEFVAL                                     0x00000000
+#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_SHIFT                                      9
+#define DDR_PHY_DX8LCDLR2_RESERVED_15_9_MASK                                       0x0000FE00U
+
+/*Read DQS Gating Delay*/
+#undef DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL 
+#undef DDR_PHY_DX8LCDLR2_DQSGD_SHIFT 
+#undef DDR_PHY_DX8LCDLR2_DQSGD_MASK 
+#define DDR_PHY_DX8LCDLR2_DQSGD_DEFVAL                                             0x00000000
+#define DDR_PHY_DX8LCDLR2_DQSGD_SHIFT                                              0
+#define DDR_PHY_DX8LCDLR2_DQSGD_MASK                                               0x000001FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8GTR0_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8GTR0_RESERVED_31_24_DEFVAL                                      0x00020000
+#define DDR_PHY_DX8GTR0_RESERVED_31_24_SHIFT                                       27
+#define DDR_PHY_DX8GTR0_RESERVED_31_24_MASK                                        0xF8000000U
+
+/*DQ Write Path Latency Pipeline*/
+#undef DDR_PHY_DX8GTR0_WDQSL_DEFVAL 
+#undef DDR_PHY_DX8GTR0_WDQSL_SHIFT 
+#undef DDR_PHY_DX8GTR0_WDQSL_MASK 
+#define DDR_PHY_DX8GTR0_WDQSL_DEFVAL                                               0x00020000
+#define DDR_PHY_DX8GTR0_WDQSL_SHIFT                                                24
+#define DDR_PHY_DX8GTR0_WDQSL_MASK                                                 0x07000000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL 
+#undef DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT 
+#undef DDR_PHY_DX8GTR0_RESERVED_23_20_MASK 
+#define DDR_PHY_DX8GTR0_RESERVED_23_20_DEFVAL                                      0x00020000
+#define DDR_PHY_DX8GTR0_RESERVED_23_20_SHIFT                                       20
+#define DDR_PHY_DX8GTR0_RESERVED_23_20_MASK                                        0x00F00000U
+
+/*Write Leveling System Latency*/
+#undef DDR_PHY_DX8GTR0_WLSL_DEFVAL 
+#undef DDR_PHY_DX8GTR0_WLSL_SHIFT 
+#undef DDR_PHY_DX8GTR0_WLSL_MASK 
+#define DDR_PHY_DX8GTR0_WLSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX8GTR0_WLSL_SHIFT                                                 16
+#define DDR_PHY_DX8GTR0_WLSL_MASK                                                  0x000F0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL 
+#undef DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT 
+#undef DDR_PHY_DX8GTR0_RESERVED_15_13_MASK 
+#define DDR_PHY_DX8GTR0_RESERVED_15_13_DEFVAL                                      0x00020000
+#define DDR_PHY_DX8GTR0_RESERVED_15_13_SHIFT                                       13
+#define DDR_PHY_DX8GTR0_RESERVED_15_13_MASK                                        0x0000E000U
+
+/*Reserved. Caution, do not write to this register field.*/
+#undef DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL 
+#undef DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT 
+#undef DDR_PHY_DX8GTR0_RESERVED_12_8_MASK 
+#define DDR_PHY_DX8GTR0_RESERVED_12_8_DEFVAL                                       0x00020000
+#define DDR_PHY_DX8GTR0_RESERVED_12_8_SHIFT                                        8
+#define DDR_PHY_DX8GTR0_RESERVED_12_8_MASK                                         0x00001F00U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL 
+#undef DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT 
+#undef DDR_PHY_DX8GTR0_RESERVED_7_5_MASK 
+#define DDR_PHY_DX8GTR0_RESERVED_7_5_DEFVAL                                        0x00020000
+#define DDR_PHY_DX8GTR0_RESERVED_7_5_SHIFT                                         5
+#define DDR_PHY_DX8GTR0_RESERVED_7_5_MASK                                          0x000000E0U
+
+/*DQS Gating System Latency*/
+#undef DDR_PHY_DX8GTR0_DGSL_DEFVAL 
+#undef DDR_PHY_DX8GTR0_DGSL_SHIFT 
+#undef DDR_PHY_DX8GTR0_DGSL_MASK 
+#define DDR_PHY_DX8GTR0_DGSL_DEFVAL                                                0x00020000
+#define DDR_PHY_DX8GTR0_DGSL_SHIFT                                                 0
+#define DDR_PHY_DX8GTR0_DGSL_MASK                                                  0x0000001FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SL0DQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SL0DQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DQSGX_DEFVAL                                          0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SL0DQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SL0DQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SL0DQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SL0DQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SL0DQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SL0DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DXSR_DEFVAL                                           0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SL0DQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS_N Resistor*/
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SL0DQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SL0DQSCTL_DQSRES_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL0DQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SL0DQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_SHIFT                                  24
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
+
+/*Configurable Read Data Enable*/
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_CRDEN_DEFVAL                                          0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_CRDEN_SHIFT                                           23
+#define DDR_PHY_DX8SL0DXCTL2_CRDEN_MASK                                            0x00800000U
+
+/*OX Extension during Post-amble*/
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_POSOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_POSOEX_SHIFT                                          20
+#define DDR_PHY_DX8SL0DXCTL2_POSOEX_MASK                                           0x00700000U
+
+/*OE Extension during Pre-amble*/
+#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_PREOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_PREOEX_SHIFT                                          18
+#define DDR_PHY_DX8SL0DXCTL2_PREOEX_MASK                                           0x000C0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_SHIFT                                     17
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_17_MASK                                      0x00020000U
+
+/*I/O Assisted Gate Select*/
+#undef DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_IOAG_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_IOAG_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_IOAG_SHIFT                                            16
+#define DDR_PHY_DX8SL0DXCTL2_IOAG_MASK                                             0x00010000U
+
+/*I/O Loopback Select*/
+#undef DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_IOLB_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_IOLB_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_IOLB_SHIFT                                            15
+#define DDR_PHY_DX8SL0DXCTL2_IOLB_MASK                                             0x00008000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_SHIFT                                  13
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
+
+/*Low Power Wakeup Threshold*/
+#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
+#define DDR_PHY_DX8SL0DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
+
+/*Read Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RDBI_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RDBI_SHIFT                                            8
+#define DDR_PHY_DX8SL0DXCTL2_RDBI_MASK                                             0x00000100U
+
+/*Write Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_WDBI_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_WDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_WDBI_SHIFT                                            7
+#define DDR_PHY_DX8SL0DXCTL2_WDBI_MASK                                             0x00000080U
+
+/*PUB Read FIFO Bypass*/
+#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_SHIFT                                          6
+#define DDR_PHY_DX8SL0DXCTL2_PRFBYP_MASK                                           0x00000040U
+
+/*DATX8 Receive FIFO Read Mode*/
+#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RDMODE_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RDMODE_SHIFT                                          4
+#define DDR_PHY_DX8SL0DXCTL2_RDMODE_MASK                                           0x00000030U
+
+/*Disables the Read FIFO Reset*/
+#undef DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_DISRST_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_DISRST_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_DISRST_SHIFT                                          3
+#define DDR_PHY_DX8SL0DXCTL2_DISRST_MASK                                           0x00000008U
+
+/*Read DQS Gate I/O Loopback*/
+#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_SHIFT                                          1
+#define DDR_PHY_DX8SL0DXCTL2_DQSGLB_MASK                                           0x00000006U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT 
+#undef DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK 
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_SHIFT                                      0
+#define DDR_PHY_DX8SL0DXCTL2_RESERVED_0_MASK                                       0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK 
+#define DDR_PHY_DX8SL0IOCR_RESERVED_31_DEFVAL                                      0x00000000
+#define DDR_PHY_DX8SL0IOCR_RESERVED_31_SHIFT                                       31
+#define DDR_PHY_DX8SL0IOCR_RESERVED_31_MASK                                        0x80000000U
+
+/*PVREF_DAC REFSEL range select*/
+#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK 
+#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_DEFVAL                                       0x00000000
+#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_SHIFT                                        28
+#define DDR_PHY_DX8SL0IOCR_DXDACRANGE_MASK                                         0x70000000U
+
+/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
+#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK 
+#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_SHIFT                                         25
+#define DDR_PHY_DX8SL0IOCR_DXVREFIOM_MASK                                          0x0E000000U
+
+/*DX IO Mode*/
+#undef DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_DXIOM_MASK 
+#define DDR_PHY_DX8SL0IOCR_DXIOM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL0IOCR_DXIOM_SHIFT                                             22
+#define DDR_PHY_DX8SL0IOCR_DXIOM_MASK                                              0x01C00000U
+
+/*DX IO Transmitter Mode*/
+#undef DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_DXTXM_MASK 
+#define DDR_PHY_DX8SL0IOCR_DXTXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL0IOCR_DXTXM_SHIFT                                             11
+#define DDR_PHY_DX8SL0IOCR_DXTXM_MASK                                              0x003FF800U
+
+/*DX IO Receiver Mode*/
+#undef DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL 
+#undef DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT 
+#undef DDR_PHY_DX8SL0IOCR_DXRXM_MASK 
+#define DDR_PHY_DX8SL0IOCR_DXRXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL0IOCR_DXRXM_SHIFT                                             0
+#define DDR_PHY_DX8SL0IOCR_DXRXM_MASK                                              0x000007FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SL1DQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SL1DQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_DQSGX_DEFVAL                                          0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SL1DQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SL1DQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SL1DQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SL1DQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SL1DQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SL1DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_DXSR_DEFVAL                                           0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SL1DQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS_N Resistor*/
+#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SL1DQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SL1DQSCTL_DQSRES_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL1DQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SL1DQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_SHIFT                                  24
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
+
+/*Configurable Read Data Enable*/
+#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_CRDEN_DEFVAL                                          0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_CRDEN_SHIFT                                           23
+#define DDR_PHY_DX8SL1DXCTL2_CRDEN_MASK                                            0x00800000U
+
+/*OX Extension during Post-amble*/
+#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_POSOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_POSOEX_SHIFT                                          20
+#define DDR_PHY_DX8SL1DXCTL2_POSOEX_MASK                                           0x00700000U
+
+/*OE Extension during Pre-amble*/
+#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_PREOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_PREOEX_SHIFT                                          18
+#define DDR_PHY_DX8SL1DXCTL2_PREOEX_MASK                                           0x000C0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_SHIFT                                     17
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_17_MASK                                      0x00020000U
+
+/*I/O Assisted Gate Select*/
+#undef DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_IOAG_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_IOAG_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_IOAG_SHIFT                                            16
+#define DDR_PHY_DX8SL1DXCTL2_IOAG_MASK                                             0x00010000U
+
+/*I/O Loopback Select*/
+#undef DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_IOLB_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_IOLB_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_IOLB_SHIFT                                            15
+#define DDR_PHY_DX8SL1DXCTL2_IOLB_MASK                                             0x00008000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_SHIFT                                  13
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
+
+/*Low Power Wakeup Threshold*/
+#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
+#define DDR_PHY_DX8SL1DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
+
+/*Read Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RDBI_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RDBI_SHIFT                                            8
+#define DDR_PHY_DX8SL1DXCTL2_RDBI_MASK                                             0x00000100U
+
+/*Write Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_WDBI_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_WDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_WDBI_SHIFT                                            7
+#define DDR_PHY_DX8SL1DXCTL2_WDBI_MASK                                             0x00000080U
+
+/*PUB Read FIFO Bypass*/
+#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_SHIFT                                          6
+#define DDR_PHY_DX8SL1DXCTL2_PRFBYP_MASK                                           0x00000040U
+
+/*DATX8 Receive FIFO Read Mode*/
+#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RDMODE_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RDMODE_SHIFT                                          4
+#define DDR_PHY_DX8SL1DXCTL2_RDMODE_MASK                                           0x00000030U
+
+/*Disables the Read FIFO Reset*/
+#undef DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_DISRST_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_DISRST_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_DISRST_SHIFT                                          3
+#define DDR_PHY_DX8SL1DXCTL2_DISRST_MASK                                           0x00000008U
+
+/*Read DQS Gate I/O Loopback*/
+#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_SHIFT                                          1
+#define DDR_PHY_DX8SL1DXCTL2_DQSGLB_MASK                                           0x00000006U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT 
+#undef DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK 
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_SHIFT                                      0
+#define DDR_PHY_DX8SL1DXCTL2_RESERVED_0_MASK                                       0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK 
+#define DDR_PHY_DX8SL1IOCR_RESERVED_31_DEFVAL                                      0x00000000
+#define DDR_PHY_DX8SL1IOCR_RESERVED_31_SHIFT                                       31
+#define DDR_PHY_DX8SL1IOCR_RESERVED_31_MASK                                        0x80000000U
+
+/*PVREF_DAC REFSEL range select*/
+#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK 
+#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_DEFVAL                                       0x00000000
+#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_SHIFT                                        28
+#define DDR_PHY_DX8SL1IOCR_DXDACRANGE_MASK                                         0x70000000U
+
+/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
+#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK 
+#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_SHIFT                                         25
+#define DDR_PHY_DX8SL1IOCR_DXVREFIOM_MASK                                          0x0E000000U
+
+/*DX IO Mode*/
+#undef DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_DXIOM_MASK 
+#define DDR_PHY_DX8SL1IOCR_DXIOM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL1IOCR_DXIOM_SHIFT                                             22
+#define DDR_PHY_DX8SL1IOCR_DXIOM_MASK                                              0x01C00000U
+
+/*DX IO Transmitter Mode*/
+#undef DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_DXTXM_MASK 
+#define DDR_PHY_DX8SL1IOCR_DXTXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL1IOCR_DXTXM_SHIFT                                             11
+#define DDR_PHY_DX8SL1IOCR_DXTXM_MASK                                              0x003FF800U
+
+/*DX IO Receiver Mode*/
+#undef DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL 
+#undef DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT 
+#undef DDR_PHY_DX8SL1IOCR_DXRXM_MASK 
+#define DDR_PHY_DX8SL1IOCR_DXRXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL1IOCR_DXRXM_SHIFT                                             0
+#define DDR_PHY_DX8SL1IOCR_DXRXM_MASK                                              0x000007FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SL2DQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SL2DQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_DQSGX_DEFVAL                                          0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SL2DQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SL2DQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SL2DQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SL2DQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SL2DQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SL2DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_DXSR_DEFVAL                                           0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SL2DQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS_N Resistor*/
+#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SL2DQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SL2DQSCTL_DQSRES_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL2DQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SL2DQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_SHIFT                                  24
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
+
+/*Configurable Read Data Enable*/
+#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_CRDEN_DEFVAL                                          0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_CRDEN_SHIFT                                           23
+#define DDR_PHY_DX8SL2DXCTL2_CRDEN_MASK                                            0x00800000U
+
+/*OX Extension during Post-amble*/
+#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_POSOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_POSOEX_SHIFT                                          20
+#define DDR_PHY_DX8SL2DXCTL2_POSOEX_MASK                                           0x00700000U
+
+/*OE Extension during Pre-amble*/
+#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_PREOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_PREOEX_SHIFT                                          18
+#define DDR_PHY_DX8SL2DXCTL2_PREOEX_MASK                                           0x000C0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_SHIFT                                     17
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_17_MASK                                      0x00020000U
+
+/*I/O Assisted Gate Select*/
+#undef DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_IOAG_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_IOAG_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_IOAG_SHIFT                                            16
+#define DDR_PHY_DX8SL2DXCTL2_IOAG_MASK                                             0x00010000U
+
+/*I/O Loopback Select*/
+#undef DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_IOLB_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_IOLB_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_IOLB_SHIFT                                            15
+#define DDR_PHY_DX8SL2DXCTL2_IOLB_MASK                                             0x00008000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_SHIFT                                  13
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
+
+/*Low Power Wakeup Threshold*/
+#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
+#define DDR_PHY_DX8SL2DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
+
+/*Read Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RDBI_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RDBI_SHIFT                                            8
+#define DDR_PHY_DX8SL2DXCTL2_RDBI_MASK                                             0x00000100U
+
+/*Write Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_WDBI_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_WDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_WDBI_SHIFT                                            7
+#define DDR_PHY_DX8SL2DXCTL2_WDBI_MASK                                             0x00000080U
+
+/*PUB Read FIFO Bypass*/
+#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_SHIFT                                          6
+#define DDR_PHY_DX8SL2DXCTL2_PRFBYP_MASK                                           0x00000040U
+
+/*DATX8 Receive FIFO Read Mode*/
+#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RDMODE_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RDMODE_SHIFT                                          4
+#define DDR_PHY_DX8SL2DXCTL2_RDMODE_MASK                                           0x00000030U
+
+/*Disables the Read FIFO Reset*/
+#undef DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_DISRST_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_DISRST_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_DISRST_SHIFT                                          3
+#define DDR_PHY_DX8SL2DXCTL2_DISRST_MASK                                           0x00000008U
+
+/*Read DQS Gate I/O Loopback*/
+#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_SHIFT                                          1
+#define DDR_PHY_DX8SL2DXCTL2_DQSGLB_MASK                                           0x00000006U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT 
+#undef DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK 
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_SHIFT                                      0
+#define DDR_PHY_DX8SL2DXCTL2_RESERVED_0_MASK                                       0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK 
+#define DDR_PHY_DX8SL2IOCR_RESERVED_31_DEFVAL                                      0x00000000
+#define DDR_PHY_DX8SL2IOCR_RESERVED_31_SHIFT                                       31
+#define DDR_PHY_DX8SL2IOCR_RESERVED_31_MASK                                        0x80000000U
+
+/*PVREF_DAC REFSEL range select*/
+#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK 
+#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_DEFVAL                                       0x00000000
+#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_SHIFT                                        28
+#define DDR_PHY_DX8SL2IOCR_DXDACRANGE_MASK                                         0x70000000U
+
+/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
+#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK 
+#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_SHIFT                                         25
+#define DDR_PHY_DX8SL2IOCR_DXVREFIOM_MASK                                          0x0E000000U
+
+/*DX IO Mode*/
+#undef DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_DXIOM_MASK 
+#define DDR_PHY_DX8SL2IOCR_DXIOM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL2IOCR_DXIOM_SHIFT                                             22
+#define DDR_PHY_DX8SL2IOCR_DXIOM_MASK                                              0x01C00000U
+
+/*DX IO Transmitter Mode*/
+#undef DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_DXTXM_MASK 
+#define DDR_PHY_DX8SL2IOCR_DXTXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL2IOCR_DXTXM_SHIFT                                             11
+#define DDR_PHY_DX8SL2IOCR_DXTXM_MASK                                              0x003FF800U
+
+/*DX IO Receiver Mode*/
+#undef DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL 
+#undef DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT 
+#undef DDR_PHY_DX8SL2IOCR_DXRXM_MASK 
+#define DDR_PHY_DX8SL2IOCR_DXRXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL2IOCR_DXRXM_SHIFT                                             0
+#define DDR_PHY_DX8SL2IOCR_DXRXM_MASK                                              0x000007FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SL3DQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SL3DQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_DQSGX_DEFVAL                                          0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SL3DQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SL3DQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SL3DQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SL3DQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SL3DQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SL3DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_DXSR_DEFVAL                                           0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SL3DQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS_N Resistor*/
+#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SL3DQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SL3DQSCTL_DQSRES_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL3DQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SL3DQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_SHIFT                                  24
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
+
+/*Configurable Read Data Enable*/
+#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_CRDEN_DEFVAL                                          0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_CRDEN_SHIFT                                           23
+#define DDR_PHY_DX8SL3DXCTL2_CRDEN_MASK                                            0x00800000U
+
+/*OX Extension during Post-amble*/
+#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_POSOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_POSOEX_SHIFT                                          20
+#define DDR_PHY_DX8SL3DXCTL2_POSOEX_MASK                                           0x00700000U
+
+/*OE Extension during Pre-amble*/
+#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_PREOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_PREOEX_SHIFT                                          18
+#define DDR_PHY_DX8SL3DXCTL2_PREOEX_MASK                                           0x000C0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_SHIFT                                     17
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_17_MASK                                      0x00020000U
+
+/*I/O Assisted Gate Select*/
+#undef DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_IOAG_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_IOAG_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_IOAG_SHIFT                                            16
+#define DDR_PHY_DX8SL3DXCTL2_IOAG_MASK                                             0x00010000U
+
+/*I/O Loopback Select*/
+#undef DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_IOLB_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_IOLB_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_IOLB_SHIFT                                            15
+#define DDR_PHY_DX8SL3DXCTL2_IOLB_MASK                                             0x00008000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_SHIFT                                  13
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
+
+/*Low Power Wakeup Threshold*/
+#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
+#define DDR_PHY_DX8SL3DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
+
+/*Read Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RDBI_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RDBI_SHIFT                                            8
+#define DDR_PHY_DX8SL3DXCTL2_RDBI_MASK                                             0x00000100U
+
+/*Write Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_WDBI_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_WDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_WDBI_SHIFT                                            7
+#define DDR_PHY_DX8SL3DXCTL2_WDBI_MASK                                             0x00000080U
+
+/*PUB Read FIFO Bypass*/
+#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_SHIFT                                          6
+#define DDR_PHY_DX8SL3DXCTL2_PRFBYP_MASK                                           0x00000040U
+
+/*DATX8 Receive FIFO Read Mode*/
+#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RDMODE_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RDMODE_SHIFT                                          4
+#define DDR_PHY_DX8SL3DXCTL2_RDMODE_MASK                                           0x00000030U
+
+/*Disables the Read FIFO Reset*/
+#undef DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_DISRST_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_DISRST_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_DISRST_SHIFT                                          3
+#define DDR_PHY_DX8SL3DXCTL2_DISRST_MASK                                           0x00000008U
+
+/*Read DQS Gate I/O Loopback*/
+#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_SHIFT                                          1
+#define DDR_PHY_DX8SL3DXCTL2_DQSGLB_MASK                                           0x00000006U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT 
+#undef DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK 
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_SHIFT                                      0
+#define DDR_PHY_DX8SL3DXCTL2_RESERVED_0_MASK                                       0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK 
+#define DDR_PHY_DX8SL3IOCR_RESERVED_31_DEFVAL                                      0x00000000
+#define DDR_PHY_DX8SL3IOCR_RESERVED_31_SHIFT                                       31
+#define DDR_PHY_DX8SL3IOCR_RESERVED_31_MASK                                        0x80000000U
+
+/*PVREF_DAC REFSEL range select*/
+#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK 
+#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_DEFVAL                                       0x00000000
+#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_SHIFT                                        28
+#define DDR_PHY_DX8SL3IOCR_DXDACRANGE_MASK                                         0x70000000U
+
+/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
+#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK 
+#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_SHIFT                                         25
+#define DDR_PHY_DX8SL3IOCR_DXVREFIOM_MASK                                          0x0E000000U
+
+/*DX IO Mode*/
+#undef DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_DXIOM_MASK 
+#define DDR_PHY_DX8SL3IOCR_DXIOM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL3IOCR_DXIOM_SHIFT                                             22
+#define DDR_PHY_DX8SL3IOCR_DXIOM_MASK                                              0x01C00000U
+
+/*DX IO Transmitter Mode*/
+#undef DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_DXTXM_MASK 
+#define DDR_PHY_DX8SL3IOCR_DXTXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL3IOCR_DXTXM_SHIFT                                             11
+#define DDR_PHY_DX8SL3IOCR_DXTXM_MASK                                              0x003FF800U
+
+/*DX IO Receiver Mode*/
+#undef DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL 
+#undef DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT 
+#undef DDR_PHY_DX8SL3IOCR_DXRXM_MASK 
+#define DDR_PHY_DX8SL3IOCR_DXRXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL3IOCR_DXRXM_SHIFT                                             0
+#define DDR_PHY_DX8SL3IOCR_DXRXM_MASK                                              0x000007FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SL4DQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SL4DQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_DQSGX_DEFVAL                                          0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SL4DQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SL4DQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SL4DQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SL4DQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SL4DQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_DEFVAL                                 0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SL4DQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_DXSR_DEFVAL                                           0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SL4DQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS_N Resistor*/
+#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_DEFVAL                                        0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SL4DQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SL4DQSCTL_DQSRES_DEFVAL                                         0x01264000
+#define DDR_PHY_DX8SL4DQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SL4DQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_SHIFT                                  24
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_31_24_MASK                                   0xFF000000U
+
+/*Configurable Read Data Enable*/
+#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_CRDEN_DEFVAL                                          0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_CRDEN_SHIFT                                           23
+#define DDR_PHY_DX8SL4DXCTL2_CRDEN_MASK                                            0x00800000U
+
+/*OX Extension during Post-amble*/
+#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_POSOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_POSOEX_SHIFT                                          20
+#define DDR_PHY_DX8SL4DXCTL2_POSOEX_MASK                                           0x00700000U
+
+/*OE Extension during Pre-amble*/
+#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_PREOEX_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_PREOEX_SHIFT                                          18
+#define DDR_PHY_DX8SL4DXCTL2_PREOEX_MASK                                           0x000C0000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_DEFVAL                                    0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_SHIFT                                     17
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_17_MASK                                      0x00020000U
+
+/*I/O Assisted Gate Select*/
+#undef DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_IOAG_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_IOAG_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_IOAG_SHIFT                                            16
+#define DDR_PHY_DX8SL4DXCTL2_IOAG_MASK                                             0x00010000U
+
+/*I/O Loopback Select*/
+#undef DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_IOLB_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_IOLB_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_IOLB_SHIFT                                            15
+#define DDR_PHY_DX8SL4DXCTL2_IOLB_MASK                                             0x00008000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_SHIFT                                  13
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_14_13_MASK                                   0x00006000U
+
+/*Low Power Wakeup Threshold*/
+#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_DEFVAL                                 0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_SHIFT                                  9
+#define DDR_PHY_DX8SL4DXCTL2_LPWAKEUP_THRSH_MASK                                   0x00001E00U
+
+/*Read Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RDBI_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RDBI_SHIFT                                            8
+#define DDR_PHY_DX8SL4DXCTL2_RDBI_MASK                                             0x00000100U
+
+/*Write Data Bus Inversion Enable*/
+#undef DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_WDBI_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_WDBI_DEFVAL                                           0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_WDBI_SHIFT                                            7
+#define DDR_PHY_DX8SL4DXCTL2_WDBI_MASK                                             0x00000080U
+
+/*PUB Read FIFO Bypass*/
+#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_SHIFT                                          6
+#define DDR_PHY_DX8SL4DXCTL2_PRFBYP_MASK                                           0x00000040U
+
+/*DATX8 Receive FIFO Read Mode*/
+#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RDMODE_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RDMODE_SHIFT                                          4
+#define DDR_PHY_DX8SL4DXCTL2_RDMODE_MASK                                           0x00000030U
+
+/*Disables the Read FIFO Reset*/
+#undef DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_DISRST_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_DISRST_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_DISRST_SHIFT                                          3
+#define DDR_PHY_DX8SL4DXCTL2_DISRST_MASK                                           0x00000008U
+
+/*Read DQS Gate I/O Loopback*/
+#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_DEFVAL                                         0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_SHIFT                                          1
+#define DDR_PHY_DX8SL4DXCTL2_DQSGLB_MASK                                           0x00000006U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT 
+#undef DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK 
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_DEFVAL                                     0x00141800
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_SHIFT                                      0
+#define DDR_PHY_DX8SL4DXCTL2_RESERVED_0_MASK                                       0x00000001U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK 
+#define DDR_PHY_DX8SL4IOCR_RESERVED_31_DEFVAL                                      0x00000000
+#define DDR_PHY_DX8SL4IOCR_RESERVED_31_SHIFT                                       31
+#define DDR_PHY_DX8SL4IOCR_RESERVED_31_MASK                                        0x80000000U
+
+/*PVREF_DAC REFSEL range select*/
+#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK 
+#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_DEFVAL                                       0x00000000
+#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_SHIFT                                        28
+#define DDR_PHY_DX8SL4IOCR_DXDACRANGE_MASK                                         0x70000000U
+
+/*IOM bits for PVREF, PVREF_DAC and PVREFE cells in DX IO ring*/
+#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK 
+#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_SHIFT                                         25
+#define DDR_PHY_DX8SL4IOCR_DXVREFIOM_MASK                                          0x0E000000U
+
+/*DX IO Mode*/
+#undef DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_DXIOM_MASK 
+#define DDR_PHY_DX8SL4IOCR_DXIOM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL4IOCR_DXIOM_SHIFT                                             22
+#define DDR_PHY_DX8SL4IOCR_DXIOM_MASK                                              0x01C00000U
+
+/*DX IO Transmitter Mode*/
+#undef DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_DXTXM_MASK 
+#define DDR_PHY_DX8SL4IOCR_DXTXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL4IOCR_DXTXM_SHIFT                                             11
+#define DDR_PHY_DX8SL4IOCR_DXTXM_MASK                                              0x003FF800U
+
+/*DX IO Receiver Mode*/
+#undef DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL 
+#undef DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT 
+#undef DDR_PHY_DX8SL4IOCR_DXRXM_MASK 
+#define DDR_PHY_DX8SL4IOCR_DXRXM_DEFVAL                                            0x00000000
+#define DDR_PHY_DX8SL4IOCR_DXRXM_SHIFT                                             0
+#define DDR_PHY_DX8SL4IOCR_DXRXM_MASK                                              0x000007FFU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_DEFVAL                                 0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_SHIFT                                  25
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_31_25_MASK                                   0xFE000000U
+
+/*Read Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_SHIFT                                         24
+#define DDR_PHY_DX8SLBDQSCTL_RRRMODE_MASK                                          0x01000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_DEFVAL                                 0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_SHIFT                                  22
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_23_22_MASK                                   0x00C00000U
+
+/*Write Path Rise-to-Rise Mode*/
+#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_SHIFT                                         21
+#define DDR_PHY_DX8SLBDQSCTL_WRRMODE_MASK                                          0x00200000U
+
+/*DQS Gate Extension*/
+#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_DQSGX_DEFVAL                                          0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_DQSGX_SHIFT                                           19
+#define DDR_PHY_DX8SLBDQSCTL_DQSGX_MASK                                            0x00180000U
+
+/*Low Power PLL Power Down*/
+#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_SHIFT                                         18
+#define DDR_PHY_DX8SLBDQSCTL_LPPLLPD_MASK                                          0x00040000U
+
+/*Low Power I/O Power Down*/
+#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_DEFVAL                                         0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_SHIFT                                          17
+#define DDR_PHY_DX8SLBDQSCTL_LPIOPD_MASK                                           0x00020000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_DEFVAL                                 0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_SHIFT                                  15
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_16_15_MASK                                   0x00018000U
+
+/*QS Counter Enable*/
+#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_SHIFT                                         14
+#define DDR_PHY_DX8SLBDQSCTL_QSCNTEN_MASK                                          0x00004000U
+
+/*Unused DQ I/O Mode*/
+#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_DEFVAL                                         0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_SHIFT                                          13
+#define DDR_PHY_DX8SLBDQSCTL_UDQIOM_MASK                                           0x00002000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_DEFVAL                                 0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_SHIFT                                  10
+#define DDR_PHY_DX8SLBDQSCTL_RESERVED_12_10_MASK                                   0x00001C00U
+
+/*Data Slew Rate*/
+#undef DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_DXSR_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_DXSR_DEFVAL                                           0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_DXSR_SHIFT                                            8
+#define DDR_PHY_DX8SLBDQSCTL_DXSR_MASK                                             0x00000300U
+
+/*DQS# Resistor*/
+#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_DEFVAL                                        0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_SHIFT                                         4
+#define DDR_PHY_DX8SLBDQSCTL_DQSNRES_MASK                                          0x000000F0U
+
+/*DQS Resistor*/
+#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT 
+#undef DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK 
+#define DDR_PHY_DX8SLBDQSCTL_DQSRES_DEFVAL                                         0x00000000
+#define DDR_PHY_DX8SLBDQSCTL_DQSRES_SHIFT                                          0
+#define DDR_PHY_DX8SLBDQSCTL_DQSRES_MASK                                           0x0000000FU
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PIR_RESERVED_31_DEFVAL 
+#undef DDR_PHY_PIR_RESERVED_31_SHIFT 
+#undef DDR_PHY_PIR_RESERVED_31_MASK 
+#define DDR_PHY_PIR_RESERVED_31_DEFVAL                                             0x00000000
+#define DDR_PHY_PIR_RESERVED_31_SHIFT                                              31
+#define DDR_PHY_PIR_RESERVED_31_MASK                                               0x80000000U
+
+/*Impedance Calibration Bypass*/
+#undef DDR_PHY_PIR_ZCALBYP_DEFVAL 
+#undef DDR_PHY_PIR_ZCALBYP_SHIFT 
+#undef DDR_PHY_PIR_ZCALBYP_MASK 
+#define DDR_PHY_PIR_ZCALBYP_DEFVAL                                                 0x00000000
+#define DDR_PHY_PIR_ZCALBYP_SHIFT                                                  30
+#define DDR_PHY_PIR_ZCALBYP_MASK                                                   0x40000000U
+
+/*Digital Delay Line (DDL) Calibration Pause*/
+#undef DDR_PHY_PIR_DCALPSE_DEFVAL 
+#undef DDR_PHY_PIR_DCALPSE_SHIFT 
+#undef DDR_PHY_PIR_DCALPSE_MASK 
+#define DDR_PHY_PIR_DCALPSE_DEFVAL                                                 0x00000000
+#define DDR_PHY_PIR_DCALPSE_SHIFT                                                  29
+#define DDR_PHY_PIR_DCALPSE_MASK                                                   0x20000000U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PIR_RESERVED_28_21_DEFVAL 
+#undef DDR_PHY_PIR_RESERVED_28_21_SHIFT 
+#undef DDR_PHY_PIR_RESERVED_28_21_MASK 
+#define DDR_PHY_PIR_RESERVED_28_21_DEFVAL                                          0x00000000
+#define DDR_PHY_PIR_RESERVED_28_21_SHIFT                                           21
+#define DDR_PHY_PIR_RESERVED_28_21_MASK                                            0x1FE00000U
+
+/*Write DQS2DQ Training*/
+#undef DDR_PHY_PIR_DQS2DQ_DEFVAL 
+#undef DDR_PHY_PIR_DQS2DQ_SHIFT 
+#undef DDR_PHY_PIR_DQS2DQ_MASK 
+#define DDR_PHY_PIR_DQS2DQ_DEFVAL                                                  0x00000000
+#define DDR_PHY_PIR_DQS2DQ_SHIFT                                                   20
+#define DDR_PHY_PIR_DQS2DQ_MASK                                                    0x00100000U
+
+/*RDIMM Initialization*/
+#undef DDR_PHY_PIR_RDIMMINIT_DEFVAL 
+#undef DDR_PHY_PIR_RDIMMINIT_SHIFT 
+#undef DDR_PHY_PIR_RDIMMINIT_MASK 
+#define DDR_PHY_PIR_RDIMMINIT_DEFVAL                                               0x00000000
+#define DDR_PHY_PIR_RDIMMINIT_SHIFT                                                19
+#define DDR_PHY_PIR_RDIMMINIT_MASK                                                 0x00080000U
+
+/*Controller DRAM Initialization*/
+#undef DDR_PHY_PIR_CTLDINIT_DEFVAL 
+#undef DDR_PHY_PIR_CTLDINIT_SHIFT 
+#undef DDR_PHY_PIR_CTLDINIT_MASK 
+#define DDR_PHY_PIR_CTLDINIT_DEFVAL                                                0x00000000
+#define DDR_PHY_PIR_CTLDINIT_SHIFT                                                 18
+#define DDR_PHY_PIR_CTLDINIT_MASK                                                  0x00040000U
+
+/*VREF Training*/
+#undef DDR_PHY_PIR_VREF_DEFVAL 
+#undef DDR_PHY_PIR_VREF_SHIFT 
+#undef DDR_PHY_PIR_VREF_MASK 
+#define DDR_PHY_PIR_VREF_DEFVAL                                                    0x00000000
+#define DDR_PHY_PIR_VREF_SHIFT                                                     17
+#define DDR_PHY_PIR_VREF_MASK                                                      0x00020000U
+
+/*Static Read Training*/
+#undef DDR_PHY_PIR_SRD_DEFVAL 
+#undef DDR_PHY_PIR_SRD_SHIFT 
+#undef DDR_PHY_PIR_SRD_MASK 
+#define DDR_PHY_PIR_SRD_DEFVAL                                                     0x00000000
+#define DDR_PHY_PIR_SRD_SHIFT                                                      16
+#define DDR_PHY_PIR_SRD_MASK                                                       0x00010000U
+
+/*Write Data Eye Training*/
+#undef DDR_PHY_PIR_WREYE_DEFVAL 
+#undef DDR_PHY_PIR_WREYE_SHIFT 
+#undef DDR_PHY_PIR_WREYE_MASK 
+#define DDR_PHY_PIR_WREYE_DEFVAL                                                   0x00000000
+#define DDR_PHY_PIR_WREYE_SHIFT                                                    15
+#define DDR_PHY_PIR_WREYE_MASK                                                     0x00008000U
+
+/*Read Data Eye Training*/
+#undef DDR_PHY_PIR_RDEYE_DEFVAL 
+#undef DDR_PHY_PIR_RDEYE_SHIFT 
+#undef DDR_PHY_PIR_RDEYE_MASK 
+#define DDR_PHY_PIR_RDEYE_DEFVAL                                                   0x00000000
+#define DDR_PHY_PIR_RDEYE_SHIFT                                                    14
+#define DDR_PHY_PIR_RDEYE_MASK                                                     0x00004000U
+
+/*Write Data Bit Deskew*/
+#undef DDR_PHY_PIR_WRDSKW_DEFVAL 
+#undef DDR_PHY_PIR_WRDSKW_SHIFT 
+#undef DDR_PHY_PIR_WRDSKW_MASK 
+#define DDR_PHY_PIR_WRDSKW_DEFVAL                                                  0x00000000
+#define DDR_PHY_PIR_WRDSKW_SHIFT                                                   13
+#define DDR_PHY_PIR_WRDSKW_MASK                                                    0x00002000U
+
+/*Read Data Bit Deskew*/
+#undef DDR_PHY_PIR_RDDSKW_DEFVAL 
+#undef DDR_PHY_PIR_RDDSKW_SHIFT 
+#undef DDR_PHY_PIR_RDDSKW_MASK 
+#define DDR_PHY_PIR_RDDSKW_DEFVAL                                                  0x00000000
+#define DDR_PHY_PIR_RDDSKW_SHIFT                                                   12
+#define DDR_PHY_PIR_RDDSKW_MASK                                                    0x00001000U
+
+/*Write Leveling Adjust*/
+#undef DDR_PHY_PIR_WLADJ_DEFVAL 
+#undef DDR_PHY_PIR_WLADJ_SHIFT 
+#undef DDR_PHY_PIR_WLADJ_MASK 
+#define DDR_PHY_PIR_WLADJ_DEFVAL                                                   0x00000000
+#define DDR_PHY_PIR_WLADJ_SHIFT                                                    11
+#define DDR_PHY_PIR_WLADJ_MASK                                                     0x00000800U
+
+/*Read DQS Gate Training*/
+#undef DDR_PHY_PIR_QSGATE_DEFVAL 
+#undef DDR_PHY_PIR_QSGATE_SHIFT 
+#undef DDR_PHY_PIR_QSGATE_MASK 
+#define DDR_PHY_PIR_QSGATE_DEFVAL                                                  0x00000000
+#define DDR_PHY_PIR_QSGATE_SHIFT                                                   10
+#define DDR_PHY_PIR_QSGATE_MASK                                                    0x00000400U
+
+/*Write Leveling*/
+#undef DDR_PHY_PIR_WL_DEFVAL 
+#undef DDR_PHY_PIR_WL_SHIFT 
+#undef DDR_PHY_PIR_WL_MASK 
+#define DDR_PHY_PIR_WL_DEFVAL                                                      0x00000000
+#define DDR_PHY_PIR_WL_SHIFT                                                       9
+#define DDR_PHY_PIR_WL_MASK                                                        0x00000200U
+
+/*DRAM Initialization*/
+#undef DDR_PHY_PIR_DRAMINIT_DEFVAL 
+#undef DDR_PHY_PIR_DRAMINIT_SHIFT 
+#undef DDR_PHY_PIR_DRAMINIT_MASK 
+#define DDR_PHY_PIR_DRAMINIT_DEFVAL                                                0x00000000
+#define DDR_PHY_PIR_DRAMINIT_SHIFT                                                 8
+#define DDR_PHY_PIR_DRAMINIT_MASK                                                  0x00000100U
+
+/*DRAM Reset (DDR3/DDR4/LPDDR4 Only)*/
+#undef DDR_PHY_PIR_DRAMRST_DEFVAL 
+#undef DDR_PHY_PIR_DRAMRST_SHIFT 
+#undef DDR_PHY_PIR_DRAMRST_MASK 
+#define DDR_PHY_PIR_DRAMRST_DEFVAL                                                 0x00000000
+#define DDR_PHY_PIR_DRAMRST_SHIFT                                                  7
+#define DDR_PHY_PIR_DRAMRST_MASK                                                   0x00000080U
+
+/*PHY Reset*/
+#undef DDR_PHY_PIR_PHYRST_DEFVAL 
+#undef DDR_PHY_PIR_PHYRST_SHIFT 
+#undef DDR_PHY_PIR_PHYRST_MASK 
+#define DDR_PHY_PIR_PHYRST_DEFVAL                                                  0x00000000
+#define DDR_PHY_PIR_PHYRST_SHIFT                                                   6
+#define DDR_PHY_PIR_PHYRST_MASK                                                    0x00000040U
+
+/*Digital Delay Line (DDL) Calibration*/
+#undef DDR_PHY_PIR_DCAL_DEFVAL 
+#undef DDR_PHY_PIR_DCAL_SHIFT 
+#undef DDR_PHY_PIR_DCAL_MASK 
+#define DDR_PHY_PIR_DCAL_DEFVAL                                                    0x00000000
+#define DDR_PHY_PIR_DCAL_SHIFT                                                     5
+#define DDR_PHY_PIR_DCAL_MASK                                                      0x00000020U
+
+/*PLL Initialiazation*/
+#undef DDR_PHY_PIR_PLLINIT_DEFVAL 
+#undef DDR_PHY_PIR_PLLINIT_SHIFT 
+#undef DDR_PHY_PIR_PLLINIT_MASK 
+#define DDR_PHY_PIR_PLLINIT_DEFVAL                                                 0x00000000
+#define DDR_PHY_PIR_PLLINIT_SHIFT                                                  4
+#define DDR_PHY_PIR_PLLINIT_MASK                                                   0x00000010U
+
+/*Reserved. Return zeroes on reads.*/
+#undef DDR_PHY_PIR_RESERVED_3_DEFVAL 
+#undef DDR_PHY_PIR_RESERVED_3_SHIFT 
+#undef DDR_PHY_PIR_RESERVED_3_MASK 
+#define DDR_PHY_PIR_RESERVED_3_DEFVAL                                              0x00000000
+#define DDR_PHY_PIR_RESERVED_3_SHIFT                                               3
+#define DDR_PHY_PIR_RESERVED_3_MASK                                                0x00000008U
+
+/*CA Training*/
+#undef DDR_PHY_PIR_CA_DEFVAL 
+#undef DDR_PHY_PIR_CA_SHIFT 
+#undef DDR_PHY_PIR_CA_MASK 
+#define DDR_PHY_PIR_CA_DEFVAL                                                      0x00000000
+#define DDR_PHY_PIR_CA_SHIFT                                                       2
+#define DDR_PHY_PIR_CA_MASK                                                        0x00000004U
+
+/*Impedance Calibration*/
+#undef DDR_PHY_PIR_ZCAL_DEFVAL 
+#undef DDR_PHY_PIR_ZCAL_SHIFT 
+#undef DDR_PHY_PIR_ZCAL_MASK 
+#define DDR_PHY_PIR_ZCAL_DEFVAL                                                    0x00000000
+#define DDR_PHY_PIR_ZCAL_SHIFT                                                     1
+#define DDR_PHY_PIR_ZCAL_MASK                                                      0x00000002U
+
+/*Initialization Trigger*/
+#undef DDR_PHY_PIR_INIT_DEFVAL 
+#undef DDR_PHY_PIR_INIT_SHIFT 
+#undef DDR_PHY_PIR_INIT_MASK 
+#define DDR_PHY_PIR_INIT_DEFVAL                                                    0x00000000
+#define DDR_PHY_PIR_INIT_SHIFT                                                     0
+#define DDR_PHY_PIR_INIT_MASK                                                      0x00000001U
+#undef IOU_SLCR_MIO_PIN_0_OFFSET 
+#define IOU_SLCR_MIO_PIN_0_OFFSET                                                  0XFF180000
+#undef IOU_SLCR_MIO_PIN_1_OFFSET 
+#define IOU_SLCR_MIO_PIN_1_OFFSET                                                  0XFF180004
+#undef IOU_SLCR_MIO_PIN_2_OFFSET 
+#define IOU_SLCR_MIO_PIN_2_OFFSET                                                  0XFF180008
+#undef IOU_SLCR_MIO_PIN_3_OFFSET 
+#define IOU_SLCR_MIO_PIN_3_OFFSET                                                  0XFF18000C
+#undef IOU_SLCR_MIO_PIN_4_OFFSET 
+#define IOU_SLCR_MIO_PIN_4_OFFSET                                                  0XFF180010
+#undef IOU_SLCR_MIO_PIN_5_OFFSET 
+#define IOU_SLCR_MIO_PIN_5_OFFSET                                                  0XFF180014
+#undef IOU_SLCR_MIO_PIN_6_OFFSET 
+#define IOU_SLCR_MIO_PIN_6_OFFSET                                                  0XFF180018
+#undef IOU_SLCR_MIO_PIN_7_OFFSET 
+#define IOU_SLCR_MIO_PIN_7_OFFSET                                                  0XFF18001C
+#undef IOU_SLCR_MIO_PIN_8_OFFSET 
+#define IOU_SLCR_MIO_PIN_8_OFFSET                                                  0XFF180020
+#undef IOU_SLCR_MIO_PIN_9_OFFSET 
+#define IOU_SLCR_MIO_PIN_9_OFFSET                                                  0XFF180024
+#undef IOU_SLCR_MIO_PIN_10_OFFSET 
+#define IOU_SLCR_MIO_PIN_10_OFFSET                                                 0XFF180028
+#undef IOU_SLCR_MIO_PIN_11_OFFSET 
+#define IOU_SLCR_MIO_PIN_11_OFFSET                                                 0XFF18002C
+#undef IOU_SLCR_MIO_PIN_12_OFFSET 
+#define IOU_SLCR_MIO_PIN_12_OFFSET                                                 0XFF180030
+#undef IOU_SLCR_MIO_PIN_13_OFFSET 
+#define IOU_SLCR_MIO_PIN_13_OFFSET                                                 0XFF180034
+#undef IOU_SLCR_MIO_PIN_14_OFFSET 
+#define IOU_SLCR_MIO_PIN_14_OFFSET                                                 0XFF180038
+#undef IOU_SLCR_MIO_PIN_15_OFFSET 
+#define IOU_SLCR_MIO_PIN_15_OFFSET                                                 0XFF18003C
+#undef IOU_SLCR_MIO_PIN_16_OFFSET 
+#define IOU_SLCR_MIO_PIN_16_OFFSET                                                 0XFF180040
+#undef IOU_SLCR_MIO_PIN_17_OFFSET 
+#define IOU_SLCR_MIO_PIN_17_OFFSET                                                 0XFF180044
+#undef IOU_SLCR_MIO_PIN_18_OFFSET 
+#define IOU_SLCR_MIO_PIN_18_OFFSET                                                 0XFF180048
+#undef IOU_SLCR_MIO_PIN_19_OFFSET 
+#define IOU_SLCR_MIO_PIN_19_OFFSET                                                 0XFF18004C
+#undef IOU_SLCR_MIO_PIN_20_OFFSET 
+#define IOU_SLCR_MIO_PIN_20_OFFSET                                                 0XFF180050
+#undef IOU_SLCR_MIO_PIN_21_OFFSET 
+#define IOU_SLCR_MIO_PIN_21_OFFSET                                                 0XFF180054
+#undef IOU_SLCR_MIO_PIN_22_OFFSET 
+#define IOU_SLCR_MIO_PIN_22_OFFSET                                                 0XFF180058
+#undef IOU_SLCR_MIO_PIN_23_OFFSET 
+#define IOU_SLCR_MIO_PIN_23_OFFSET                                                 0XFF18005C
+#undef IOU_SLCR_MIO_PIN_24_OFFSET 
+#define IOU_SLCR_MIO_PIN_24_OFFSET                                                 0XFF180060
+#undef IOU_SLCR_MIO_PIN_25_OFFSET 
+#define IOU_SLCR_MIO_PIN_25_OFFSET                                                 0XFF180064
+#undef IOU_SLCR_MIO_PIN_26_OFFSET 
+#define IOU_SLCR_MIO_PIN_26_OFFSET                                                 0XFF180068
+#undef IOU_SLCR_MIO_PIN_27_OFFSET 
+#define IOU_SLCR_MIO_PIN_27_OFFSET                                                 0XFF18006C
+#undef IOU_SLCR_MIO_PIN_28_OFFSET 
+#define IOU_SLCR_MIO_PIN_28_OFFSET                                                 0XFF180070
+#undef IOU_SLCR_MIO_PIN_29_OFFSET 
+#define IOU_SLCR_MIO_PIN_29_OFFSET                                                 0XFF180074
+#undef IOU_SLCR_MIO_PIN_30_OFFSET 
+#define IOU_SLCR_MIO_PIN_30_OFFSET                                                 0XFF180078
+#undef IOU_SLCR_MIO_PIN_31_OFFSET 
+#define IOU_SLCR_MIO_PIN_31_OFFSET                                                 0XFF18007C
+#undef IOU_SLCR_MIO_PIN_32_OFFSET 
+#define IOU_SLCR_MIO_PIN_32_OFFSET                                                 0XFF180080
+#undef IOU_SLCR_MIO_PIN_33_OFFSET 
+#define IOU_SLCR_MIO_PIN_33_OFFSET                                                 0XFF180084
+#undef IOU_SLCR_MIO_PIN_34_OFFSET 
+#define IOU_SLCR_MIO_PIN_34_OFFSET                                                 0XFF180088
+#undef IOU_SLCR_MIO_PIN_35_OFFSET 
+#define IOU_SLCR_MIO_PIN_35_OFFSET                                                 0XFF18008C
+#undef IOU_SLCR_MIO_PIN_36_OFFSET 
+#define IOU_SLCR_MIO_PIN_36_OFFSET                                                 0XFF180090
+#undef IOU_SLCR_MIO_PIN_37_OFFSET 
+#define IOU_SLCR_MIO_PIN_37_OFFSET                                                 0XFF180094
+#undef IOU_SLCR_MIO_PIN_38_OFFSET 
+#define IOU_SLCR_MIO_PIN_38_OFFSET                                                 0XFF180098
+#undef IOU_SLCR_MIO_PIN_39_OFFSET 
+#define IOU_SLCR_MIO_PIN_39_OFFSET                                                 0XFF18009C
+#undef IOU_SLCR_MIO_PIN_40_OFFSET 
+#define IOU_SLCR_MIO_PIN_40_OFFSET                                                 0XFF1800A0
+#undef IOU_SLCR_MIO_PIN_41_OFFSET 
+#define IOU_SLCR_MIO_PIN_41_OFFSET                                                 0XFF1800A4
+#undef IOU_SLCR_MIO_PIN_42_OFFSET 
+#define IOU_SLCR_MIO_PIN_42_OFFSET                                                 0XFF1800A8
+#undef IOU_SLCR_MIO_PIN_43_OFFSET 
+#define IOU_SLCR_MIO_PIN_43_OFFSET                                                 0XFF1800AC
+#undef IOU_SLCR_MIO_PIN_44_OFFSET 
+#define IOU_SLCR_MIO_PIN_44_OFFSET                                                 0XFF1800B0
+#undef IOU_SLCR_MIO_PIN_45_OFFSET 
+#define IOU_SLCR_MIO_PIN_45_OFFSET                                                 0XFF1800B4
+#undef IOU_SLCR_MIO_PIN_46_OFFSET 
+#define IOU_SLCR_MIO_PIN_46_OFFSET                                                 0XFF1800B8
+#undef IOU_SLCR_MIO_PIN_47_OFFSET 
+#define IOU_SLCR_MIO_PIN_47_OFFSET                                                 0XFF1800BC
+#undef IOU_SLCR_MIO_PIN_48_OFFSET 
+#define IOU_SLCR_MIO_PIN_48_OFFSET                                                 0XFF1800C0
+#undef IOU_SLCR_MIO_PIN_49_OFFSET 
+#define IOU_SLCR_MIO_PIN_49_OFFSET                                                 0XFF1800C4
+#undef IOU_SLCR_MIO_PIN_50_OFFSET 
+#define IOU_SLCR_MIO_PIN_50_OFFSET                                                 0XFF1800C8
+#undef IOU_SLCR_MIO_PIN_51_OFFSET 
+#define IOU_SLCR_MIO_PIN_51_OFFSET                                                 0XFF1800CC
+#undef IOU_SLCR_MIO_PIN_52_OFFSET 
+#define IOU_SLCR_MIO_PIN_52_OFFSET                                                 0XFF1800D0
+#undef IOU_SLCR_MIO_PIN_53_OFFSET 
+#define IOU_SLCR_MIO_PIN_53_OFFSET                                                 0XFF1800D4
+#undef IOU_SLCR_MIO_PIN_54_OFFSET 
+#define IOU_SLCR_MIO_PIN_54_OFFSET                                                 0XFF1800D8
+#undef IOU_SLCR_MIO_PIN_55_OFFSET 
+#define IOU_SLCR_MIO_PIN_55_OFFSET                                                 0XFF1800DC
+#undef IOU_SLCR_MIO_PIN_56_OFFSET 
+#define IOU_SLCR_MIO_PIN_56_OFFSET                                                 0XFF1800E0
+#undef IOU_SLCR_MIO_PIN_57_OFFSET 
+#define IOU_SLCR_MIO_PIN_57_OFFSET                                                 0XFF1800E4
+#undef IOU_SLCR_MIO_PIN_58_OFFSET 
+#define IOU_SLCR_MIO_PIN_58_OFFSET                                                 0XFF1800E8
+#undef IOU_SLCR_MIO_PIN_59_OFFSET 
+#define IOU_SLCR_MIO_PIN_59_OFFSET                                                 0XFF1800EC
+#undef IOU_SLCR_MIO_PIN_60_OFFSET 
+#define IOU_SLCR_MIO_PIN_60_OFFSET                                                 0XFF1800F0
+#undef IOU_SLCR_MIO_PIN_61_OFFSET 
+#define IOU_SLCR_MIO_PIN_61_OFFSET                                                 0XFF1800F4
+#undef IOU_SLCR_MIO_PIN_62_OFFSET 
+#define IOU_SLCR_MIO_PIN_62_OFFSET                                                 0XFF1800F8
+#undef IOU_SLCR_MIO_PIN_63_OFFSET 
+#define IOU_SLCR_MIO_PIN_63_OFFSET                                                 0XFF1800FC
+#undef IOU_SLCR_MIO_PIN_64_OFFSET 
+#define IOU_SLCR_MIO_PIN_64_OFFSET                                                 0XFF180100
+#undef IOU_SLCR_MIO_PIN_65_OFFSET 
+#define IOU_SLCR_MIO_PIN_65_OFFSET                                                 0XFF180104
+#undef IOU_SLCR_MIO_PIN_66_OFFSET 
+#define IOU_SLCR_MIO_PIN_66_OFFSET                                                 0XFF180108
+#undef IOU_SLCR_MIO_PIN_67_OFFSET 
+#define IOU_SLCR_MIO_PIN_67_OFFSET                                                 0XFF18010C
+#undef IOU_SLCR_MIO_PIN_68_OFFSET 
+#define IOU_SLCR_MIO_PIN_68_OFFSET                                                 0XFF180110
+#undef IOU_SLCR_MIO_PIN_69_OFFSET 
+#define IOU_SLCR_MIO_PIN_69_OFFSET                                                 0XFF180114
+#undef IOU_SLCR_MIO_PIN_70_OFFSET 
+#define IOU_SLCR_MIO_PIN_70_OFFSET                                                 0XFF180118
+#undef IOU_SLCR_MIO_PIN_71_OFFSET 
+#define IOU_SLCR_MIO_PIN_71_OFFSET                                                 0XFF18011C
+#undef IOU_SLCR_MIO_PIN_72_OFFSET 
+#define IOU_SLCR_MIO_PIN_72_OFFSET                                                 0XFF180120
+#undef IOU_SLCR_MIO_PIN_73_OFFSET 
+#define IOU_SLCR_MIO_PIN_73_OFFSET                                                 0XFF180124
+#undef IOU_SLCR_MIO_PIN_74_OFFSET 
+#define IOU_SLCR_MIO_PIN_74_OFFSET                                                 0XFF180128
+#undef IOU_SLCR_MIO_PIN_75_OFFSET 
+#define IOU_SLCR_MIO_PIN_75_OFFSET                                                 0XFF18012C
+#undef IOU_SLCR_MIO_PIN_76_OFFSET 
+#define IOU_SLCR_MIO_PIN_76_OFFSET                                                 0XFF180130
+#undef IOU_SLCR_MIO_PIN_77_OFFSET 
+#define IOU_SLCR_MIO_PIN_77_OFFSET                                                 0XFF180134
+#undef IOU_SLCR_MIO_MST_TRI0_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI0_OFFSET                                               0XFF180204
+#undef IOU_SLCR_MIO_MST_TRI1_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI1_OFFSET                                               0XFF180208
+#undef IOU_SLCR_MIO_MST_TRI2_OFFSET 
+#define IOU_SLCR_MIO_MST_TRI2_OFFSET                                               0XFF18020C
+#undef IOU_SLCR_BANK0_CTRL0_OFFSET 
+#define IOU_SLCR_BANK0_CTRL0_OFFSET                                                0XFF180138
+#undef IOU_SLCR_BANK0_CTRL1_OFFSET 
+#define IOU_SLCR_BANK0_CTRL1_OFFSET                                                0XFF18013C
+#undef IOU_SLCR_BANK0_CTRL3_OFFSET 
+#define IOU_SLCR_BANK0_CTRL3_OFFSET                                                0XFF180140
+#undef IOU_SLCR_BANK0_CTRL4_OFFSET 
+#define IOU_SLCR_BANK0_CTRL4_OFFSET                                                0XFF180144
+#undef IOU_SLCR_BANK0_CTRL5_OFFSET 
+#define IOU_SLCR_BANK0_CTRL5_OFFSET                                                0XFF180148
+#undef IOU_SLCR_BANK0_CTRL6_OFFSET 
+#define IOU_SLCR_BANK0_CTRL6_OFFSET                                                0XFF18014C
+#undef IOU_SLCR_BANK1_CTRL0_OFFSET 
+#define IOU_SLCR_BANK1_CTRL0_OFFSET                                                0XFF180154
+#undef IOU_SLCR_BANK1_CTRL1_OFFSET 
+#define IOU_SLCR_BANK1_CTRL1_OFFSET                                                0XFF180158
+#undef IOU_SLCR_BANK1_CTRL3_OFFSET 
+#define IOU_SLCR_BANK1_CTRL3_OFFSET                                                0XFF18015C
+#undef IOU_SLCR_BANK1_CTRL4_OFFSET 
+#define IOU_SLCR_BANK1_CTRL4_OFFSET                                                0XFF180160
+#undef IOU_SLCR_BANK1_CTRL5_OFFSET 
+#define IOU_SLCR_BANK1_CTRL5_OFFSET                                                0XFF180164
+#undef IOU_SLCR_BANK1_CTRL6_OFFSET 
+#define IOU_SLCR_BANK1_CTRL6_OFFSET                                                0XFF180168
+#undef IOU_SLCR_BANK2_CTRL0_OFFSET 
+#define IOU_SLCR_BANK2_CTRL0_OFFSET                                                0XFF180170
+#undef IOU_SLCR_BANK2_CTRL1_OFFSET 
+#define IOU_SLCR_BANK2_CTRL1_OFFSET                                                0XFF180174
+#undef IOU_SLCR_BANK2_CTRL3_OFFSET 
+#define IOU_SLCR_BANK2_CTRL3_OFFSET                                                0XFF180178
+#undef IOU_SLCR_BANK2_CTRL4_OFFSET 
+#define IOU_SLCR_BANK2_CTRL4_OFFSET                                                0XFF18017C
+#undef IOU_SLCR_BANK2_CTRL5_OFFSET 
+#define IOU_SLCR_BANK2_CTRL5_OFFSET                                                0XFF180180
+#undef IOU_SLCR_BANK2_CTRL6_OFFSET 
+#define IOU_SLCR_BANK2_CTRL6_OFFSET                                                0XFF180184
+#undef IOU_SLCR_MIO_LOOPBACK_OFFSET 
+#define IOU_SLCR_MIO_LOOPBACK_OFFSET                                               0XFF180200
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out- (QSPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_0_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_0_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[0]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[0]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_0_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[0]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[0]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_0_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_0_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_mi1- (QSPI Databus) 1= qspi, Output, qspi_so_mo1- (QSPI Data
+		us)*/
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_1_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_1_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[1]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[1]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_1_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[1]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[1]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)*/
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_1_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_1_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi2- (QSPI Databus) 1= qspi, Output, qspi_mo2- (QSPI Databus)*/
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_2_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_2_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[2]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[2]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_2_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[2]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[2]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc2, Input, ttc2_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_2_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_2_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi3- (QSPI Databus) 1= qspi, Output, qspi_mo3- (QSPI Databus)*/
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_3_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_3_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[3]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[3]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_3_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[3]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[3]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_3_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_3_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_mo_mo0- (QSPI Databus) 1= qspi, Input, qspi_si_mi0- (QSPI Data
+		us)*/
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_4_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_4_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[4]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[4]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_4_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[4]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[4]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_4_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_4_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out- (QSPI Slave Select)*/
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_5_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_5_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[5]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[5]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_5_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[5]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[5]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_5_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_5_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_clk_for_lpbk- (QSPI Clock to be fed-back)*/
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_6_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_6_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[6]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[6]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_6_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[6]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[6]- (GPIO bank 0) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1
+		sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace,
+		Output, tracedq[4]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_6_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_6_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_n_ss_out_upper- (QSPI Slave Select upper)*/
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_7_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_7_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[7]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[7]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_7_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[7]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[7]- (GPIO bank 0) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= 
+		tc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, 
+		racedq[5]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_7_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_7_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[0]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[0]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_8_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_8_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[8]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[8]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_8_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[8]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[8]- (GPIO bank 0) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc
+		, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Tr
+		ce Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_8_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_8_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[1]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[1]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_SHIFT                                            1
+#define IOU_SLCR_MIO_PIN_9_L0_SEL_MASK                                             0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_SHIFT                                            2
+#define IOU_SLCR_MIO_PIN_9_L1_SEL_MASK                                             0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[9]- (Test Scan Port) = test_scan, Outp
+		t, test_scan_out[9]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_SHIFT                                            3
+#define IOU_SLCR_MIO_PIN_9_L2_SEL_MASK                                             0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[9]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[9]- (GPIO bank 0) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, 
+		utput, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (U
+		RT receiver serial input) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_9_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_DEFVAL                                           0x00000000
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_SHIFT                                            5
+#define IOU_SLCR_MIO_PIN_9_L3_SEL_MASK                                             0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[2]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[2]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_10_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_10_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[10]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[10]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_10_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[10]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[10]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_10_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_10_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Input, qspi_mi_upper[3]- (QSPI Upper Databus) 1= qspi, Output, qspi_mo_uppe
+		[3]- (QSPI Upper Databus)*/
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_11_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_11_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[11]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[11]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_11_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[11]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[11]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_11_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_11_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= qspi, Output, qspi_sclk_out_upper- (QSPI Upper Clock)*/
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_12_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		*/
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_12_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= test_scan, Input, test_scan_in[12]- (Test Scan Port) = test_scan, Out
+		ut, test_scan_out[12]- (Test Scan Port) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_12_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[12]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[12]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cl
+		ck) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trac
+		dq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_12_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_12_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_13_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[0]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_13_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[13]- (Test Scan Port) = test_scan, Output, test_scan_out[13]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_13_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[13]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[13]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave
+		out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, tracedq[11]- (Trace Port Dat
+		bus)*/
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_13_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_13_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_14_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_cle- (NAND Command Latch Enable)*/
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_14_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[14]- (Test Scan Port) = test_scan, Output, test_scan_out[14]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_14_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[14]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[14]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_
+		n- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_14_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_14_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_15_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ale- (NAND Address Latch Enable)*/
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_15_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[15]- (Test Scan Port) = test_scan, Output, test_scan_out[15]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_15_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[15]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[15]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out
+		0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter seri
+		l output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_15_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_15_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_16_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[0]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[0]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_16_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[16]- (Test Scan Port) = test_scan, Output, test_scan_out[16]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_16_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[16]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[16]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_16_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_16_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_17_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[1]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[1]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_17_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[17]- (Test Scan Port) = test_scan, Output, test_scan_out[17]- (Test Scan Port
+		 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_17_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[17]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[17]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_17_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_17_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_18_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[2]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[2]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_18_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[18]- (Test Scan Port) = test_scan, Output, test_scan_out[18]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_18_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[18]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[18]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_18_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_18_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_19_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[3]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[3]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_19_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[19]- (Test Scan Port) = test_scan, Output, test_scan_out[19]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_19_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[19]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[19]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_19_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_19_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_20_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[4]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[4]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_20_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= test_scan, Input, test_scan_in[20]- (Test Scan Port) = test_scan, Output, test_scan_out[20]- (Test Scan Port
+		 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_20_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[20]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[20]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= t
+		c1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_20_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_20_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_21_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[5]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[5]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_21_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= test_scan, Input, test_scan_in[21]- (Test Scan Port) = test_scan, Output, test_scan_out[21]- (Test Scan Port) 
+		= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_21_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[21]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[21]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- 
+		UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_21_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_21_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_22_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_we_b- (NAND Write Enable)*/
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_22_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= test_scan, Input, test_scan_in[22]-
+		(Test Scan Port) = test_scan, Output, test_scan_out[22]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_22_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[22]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[22]- (GPIO bank 0) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed*/
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_22_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_22_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_23_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[6]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[6]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_23_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= test_scan, Input, test_scan_in
+		23]- (Test Scan Port) = test_scan, Output, test_scan_out[23]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper
+		*/
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_23_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[23]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[23]- (GPIO bank 0) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_23_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_23_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_24_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dq_in[7]- (NAND Data Bus) 1= nand, Output, nfc_dq_out[7]- (NAND 
+		ata Bus)*/
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_24_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= test_scan, Input, test
+		scan_in[24]- (Test Scan Port) = test_scan, Output, test_scan_out[24]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ex
+		 Tamper)*/
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_24_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[24]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[24]- (GPIO bank 0) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= Not Used 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1,
+		Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_24_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_24_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_25_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_re_n- (NAND Read Enable)*/
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_25_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= test_scan, Input,
+		test_scan_in[25]- (Test Scan Port) = test_scan, Output, test_scan_out[25]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (C
+		U Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_25_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio0, Input, gpio_0_pin_in[25]- (GPIO bank 0) 0= gpio0, Output, gpio_0_pin_out[25]- (GPIO bank 0) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= Not Used 5= ttc3, Output, ttc3_wave_out- (TTC Waveform 
+		lock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_25_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_25_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_26_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Output, nfc_ce[1]- (NAND chip enable)*/
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_26_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[26]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[26]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_26_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[0]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[0]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_26_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_26_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_27_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[0]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_27_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[27]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[27]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_27_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[1]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[1]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)*/
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_27_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_27_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_28_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_rb_n[1]- (NAND Ready/Busy)*/
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_28_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[28]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[28]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_28_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[2]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[2]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_28_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_28_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_29_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_29_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[29]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[29]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Outp
+		t, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_29_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[3]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[3]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_29_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_29_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_30_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_30_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[30]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[30]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_30_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[4]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[4]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_so
+		 (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output
+		 tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_30_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_30_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Output, gem0_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_31_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_31_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Input, pmu_gpi[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[31]- (Test Sc
+		n Port) = test_scan, Output, test_scan_out[31]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_31_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[5]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[5]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi
+		_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial out
+		ut) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_31_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_31_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_32_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= nand, Input, nfc_dqs_in- (NAND Strobe) 1= nand, Output, nfc_dqs_out- (NAND Strobe
+		*/
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_32_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[0]- (PMU GPI) 2= test_scan, Input, test_scan_in[32]- (Test S
+		an Port) = test_scan, Output, test_scan_out[32]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_32_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[6]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[6]- (GPIO bank 1) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi
+		_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= 
+		race, Output, tracedq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_32_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_32_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_33_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_33_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[1]- (PMU GPI) 2= test_scan, Input, test_scan_in[33]- (Test S
+		an Port) = test_scan, Output, test_scan_out[33]- (Test Scan Port) 3= csu, Input, csu_ext_tamper- (CSU Ext Tamper)*/
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_33_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[7]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[7]- (GPIO bank 1) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= t
+		c3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, traced
+		[11]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_33_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_33_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_34_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_34_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[2]- (PMU GPI) 2= test_scan, Input, test_scan_in[34]- (Test S
+		an Port) = test_scan, Output, test_scan_out[34]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
+		ut, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_34_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[8]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[8]- (GPIO bank 1) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc2
+		 Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace P
+		rt Databus)*/
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_34_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_34_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_35_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_35_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[3]- (PMU GPI) 2= test_scan, Input, test_scan_in[35]- (Test S
+		an Port) = test_scan, Output, test_scan_out[35]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_35_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[9]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[9]- (GPIO bank 1) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1,
+		Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- 
+		UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_35_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_35_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_36_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_36_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[4]- (PMU GPI) 2= test_scan, Input, test_scan_in[36]- (Test S
+		an Port) = test_scan, Output, test_scan_out[36]- (Test Scan Port) 3= dpaux, Input, dp_aux_data_in- (Dp Aux Data) = dpaux, Out
+		ut, dp_aux_data_out- (Dp Aux Data)*/
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_36_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[10]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[10]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_36_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_36_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem0, Input, gem0_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_37_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= pcie, Input, pcie_reset_n- (PCIE Reset signal)*/
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_37_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= pmu, Output, pmu_gpo[5]- (PMU GPI) 2= test_scan, Input, test_scan_in[37]- (Test S
+		an Port) = test_scan, Output, test_scan_out[37]- (Test Scan Port) 3= dpaux, Input, dp_hot_plug_detect- (Dp Aux Hot Plug)*/
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_37_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[11]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[11]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_37_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_37_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_38_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_38_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_38_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[12]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[12]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Clo
+		k) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, trace_clk-
+		(Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_38_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_38_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_39_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_39_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= sd1, Input, sd1_data_i
+		[4]- (8-bit Data bus) = sd1, Output, sdio1_data_out[4]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_39_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[13]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[13]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc0, Output, ttc0_wav
+		_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, trace_ctl- (Trace Port
+		Control Signal)*/
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_39_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_39_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_40_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_40_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= sd1, Input, sd1_data_in[5]- (8-bit Data bus) = sd1, Output, sdio1_data_out[5]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_40_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[14]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[14]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc3, Input, ttc3_clk
+		in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_40_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_40_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_41_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_41_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[6]- (8-bit Data bus) = sd1, Output, sdio1_data_out[6]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_41_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[15]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[15]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[
+		]- (SPI Master Selects) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial in
+		ut) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_41_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_41_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_42_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_42_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[7]- (8-bit Data bus) = sd1, Output, sdio1_data_out[7]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_42_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[16]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[16]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_
+		o- (MISO signal) 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_42_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_42_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Output, gem1_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_43_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_43_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_43_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[17]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[17]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, s
+		i0_si- (MOSI signal) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_43_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_43_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_44_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_44_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_44_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[18]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[18]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, s
+		i1_sclk_out- (SPI Clock) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 Not Used*/
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_44_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_44_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_45_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_45_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_45_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[19]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[19]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_45_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_45_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_46_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_46_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_46_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[20]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[20]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= tt
+		0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_46_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_46_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_47_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_47_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_47_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[21]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[21]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_47_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_47_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_48_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_48_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_48_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[22]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[22]- (GPIO bank 1) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1
+		so- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not U
+		ed*/
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_48_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_48_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem1, Input, gem1_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_49_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_49_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_data_in[3]- (8
+		bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_49_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[23]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[23]- (GPIO bank 1) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, sp
+		1_si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_49_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_49_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_50_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_50_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Input, sd1_c
+		d_in- (Command Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_50_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[24]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[24]- (GPIO bank 1) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= ttc2, Input, ttc2
+		clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_50_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_50_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem_tsu, Input, gem_tsu_clk- (TSU clock)*/
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_51_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_51_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Output, sdio1_clk_out- (SDSDIO clock) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_51_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio1, Input, gpio_1_pin_in[25]- (GPIO bank 1) 0= gpio1, Output, gpio_1_pin_out[25]- (GPIO bank 1) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= mdio1, Input, gem1_mdio_in- (MDIO Data) 4= mdio1, Outp
+		t, gem1_mdio_out- (MDIO Data) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter
+		serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_51_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_51_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_52_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_clk_in- (ULPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_52_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_52_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[0]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[0]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, spi0_sclk_out- (SPI Cloc
+		) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, trace_
+		lk- (Trace Port Clock)*/
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_52_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_52_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_53_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_dir- (Data bus direction control)*/
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_53_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_53_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[1]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[1]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5= ttc1, Output, ttc1_wave_o
+		t- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trace_ctl- (Trace Port Control
+		Signal)*/
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_53_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_53_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_54_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[2]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[2]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_54_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_54_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[2]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[2]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= ttc0, Input, ttc0_clk_in
+		 (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[0]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_54_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_54_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_55_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_nxt- (Data flow control signal from the PHY)*/
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_55_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_55_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[3]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[3]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi0, Output, spi0_n_ss_out[0
+		- (SPI Master Selects) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial
+		output) 7= trace, Output, tracedq[1]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_55_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_55_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_56_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[0]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[0]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_56_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_56_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[4]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[4]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0_s
+		- (MISO signal) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, 
+		utput, tracedq[2]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_56_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_56_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Output, gem2_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_57_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[1]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[1]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_57_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_57_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[5]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[5]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, spi0
+		si- (MOSI signal) 5= ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7
+		 trace, Output, tracedq[3]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_57_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_57_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_58_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Output, usb0_ulpi_stp- (Asserted to end or interrupt transfers)*/
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_58_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_58_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[6]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[6]- (GPIO bank 2) 1= can
+		, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL signal
+		 3= pjtag, Input, pjtag_tck- (PJTAG TCK) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, spi1_sclk_out- (SPI Clock
+		 5= ttc2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[4]- 
+		Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_58_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_58_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_59_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[3]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[3]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_59_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_59_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[7]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[7]- (GPIO bank 2) 1= can
+		, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA signa
+		) 3= pjtag, Input, pjtag_tdi- (PJTAG TDI) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_
+		ut- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= trace, Output, tracedq[5]- (Trace Port 
+		atabus)*/
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_59_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_59_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_60_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[4]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[4]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_60_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_60_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[8]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[8]- (GPIO bank 2) 1= can
+		, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL signa
+		) 3= pjtag, Output, pjtag_tdo- (PJTAG TDO) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= ttc1, Input, ttc1_clk_i
+		- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace, Output, tracedq[6]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_60_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_60_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_61_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[5]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[5]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_61_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_61_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[9]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[9]- (GPIO bank 2) 1= can
+		, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA signal
+		 3= pjtag, Input, pjtag_tms- (PJTAG TMS) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1, Output, spi1_n_ss_out[0]
+		 (SPI Master Selects) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial inpu
+		) 7= trace, Output, tracedq[7]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_61_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_61_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_62_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[6]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[6]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_62_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_62_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[10]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[10]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Outp
+		t, tracedq[8]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_62_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_62_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem2, Input, gem2_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_63_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb0, Input, usb0_ulpi_rx_data[7]- (ULPI data bus) 1= usb0, Output, usb0_ulpi_tx_
+		ata[7]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_63_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_63_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[11]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[11]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial o
+		tput) 7= trace, Output, tracedq[9]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_63_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_63_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_clk- (TX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_64_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_clk_in- (ULPI Clock)*/
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_64_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_clk_out- (SDSDIO clock) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_64_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[12]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[12]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_sclk_in- (SPI Clock) 4= spi0, Output, s
+		i0_sclk_out- (SPI Clock) 5= ttc3, Input, ttc3_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7
+		 trace, Output, tracedq[10]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_64_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_64_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[0]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_65_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_dir- (Data bus direction control)*/
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_65_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_cd_n- (SD card detect from connector) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_65_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[13]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[13]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_n_ss_out[2]- (SPI Master Selects) 5=
+		ttc3, Output, ttc3_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= trace, Output, trac
+		dq[11]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_65_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_65_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[1]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_66_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[2]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[2]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_66_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_cmd_in- (Command Indicator) = sd0, Output, sdio0_cmd_out- (Comman
+		 Indicator) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_66_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[14]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[14]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi0, Output, spi0_n_ss_out[1]- (SPI Master Selects) 5= tt
+		2, Input, ttc2_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= trace, Output, tracedq[12]- (Trace
+		Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_66_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_66_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[2]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_67_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_nxt- (Data flow control signal from the PHY)*/
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_67_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[0]- (8-bit Data bus) = sd0, Output, sdio0_data_out[0]- (8
+		bit Data bus) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_67_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[15]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[15]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi0, Input, spi0_n_ss_in- (SPI Master Selects) 4= spi
+		, Output, spi0_n_ss_out[0]- (SPI Master Selects) 5= ttc2, Output, ttc2_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd
+		 (UART transmitter serial output) 7= trace, Output, tracedq[13]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_67_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_67_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_txd[3]- (TX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_68_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[0]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[0]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_68_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[1]- (8-bit Data bus) = sd0, Output, sdio0_data_out[1]- (8
+		bit Data bus) 2= Not Used 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_68_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[16]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[16]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi0, Input, spi0_mi- (MISO signal) 4= spi0, Output, spi0
+		so- (MISO signal) 5= ttc1, Input, ttc1_clk_in- (TTC Clock) 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= trace
+		 Output, tracedq[14]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_68_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_68_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Output, gem3_rgmii_tx_ctl- (TX RGMII control)*/
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_69_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[1]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[1]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_69_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[2]- (8-bit Data bus) = sd0, Output, sdio0_data_out[2]- (8
+		bit Data bus) 2= sd1, Input, sdio1_wp- (SD card write protect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_69_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[17]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[17]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi0, Output, spi0_mo- (MOSI signal) 4= spi0, Input, sp
+		0_si- (MOSI signal) 5= ttc1, Output, ttc1_wave_out- (TTC Waveform Clock) 6= ua1, Input, ua1_rxd- (UART receiver serial input)
+		7= trace, Output, tracedq[15]- (Trace Port Databus)*/
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_69_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_69_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_clk- (RX RGMII clock)*/
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_70_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Output, usb1_ulpi_stp- (Asserted to end or interrupt transfers)*/
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_70_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[3]- (8-bit Data bus) = sd0, Output, sdio0_data_out[3]- (8
+		bit Data bus) 2= sd1, Output, sdio1_bus_pow- (SD card bus power) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_70_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[18]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[18]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_sclk_in- (SPI Clock) 4= spi1, Output, sp
+		1_sclk_out- (SPI Clock) 5= ttc0, Input, ttc0_clk_in- (TTC Clock) 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not 
+		sed*/
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_70_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_70_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[0]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_71_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[3]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[3]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_71_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[4]- (8-bit Data bus) = sd0, Output, sdio0_data_out[4]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[0]- (8-bit Data bus) = sd1, Output, sdio1_data_out[0]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_71_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[19]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[19]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_n_ss_out[2]- (SPI Master Selects) 5
+		 ttc0, Output, ttc0_wave_out- (TTC Waveform Clock) 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_71_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_71_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[1]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_72_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[4]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[4]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_72_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[5]- (8-bit Data bus) = sd0, Output, sdio0_data_out[5]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[1]- (8-bit Data bus) = sd1, Output, sdio1_data_out[1]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_72_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[20]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[20]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= swdt1, Input, swdt1_clk_in- (Watch Dog Timer Input clock) 4= spi1, Output, spi1_n_ss_out[1]- (SPI Master Selects) 5= N
+		t Used 6= ua1, Output, ua1_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_72_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_72_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[2]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_73_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[5]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[5]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_73_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[6]- (8-bit Data bus) = sd0, Output, sdio0_data_out[6]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[2]- (8-bit Data bus) = sd1, Output, sdio1_data_out[2]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_73_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[21]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[21]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= swdt1, Output, swdt1_rst_out- (Watch Dog Timer Output clock) 4= spi1, Input, spi1_n_ss_in- (SPI Master Selects) 4= spi1
+		 Output, spi1_n_ss_out[0]- (SPI Master Selects) 5= Not Used 6= ua1, Input, ua1_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_73_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_73_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rxd[3]- (RX RGMII data)*/
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_74_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[6]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[6]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_74_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sd0_data_in[7]- (8-bit Data bus) = sd0, Output, sdio0_data_out[7]- (8
+		bit Data bus) 2= sd1, Input, sd1_data_in[3]- (8-bit Data bus) = sd1, Output, sdio1_data_out[3]- (8-bit Data bus) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_74_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[22]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[22]- (GPIO bank 2) 1= c
+		n0, Input, can0_phy_rx- (Can RX signal) 2= i2c0, Input, i2c0_scl_input- (SCL signal) 2= i2c0, Output, i2c0_scl_out- (SCL sign
+		l) 3= swdt0, Input, swdt0_clk_in- (Watch Dog Timer Input clock) 4= spi1, Input, spi1_mi- (MISO signal) 4= spi1, Output, spi1_
+		o- (MISO signal) 5= Not Used 6= ua0, Input, ua0_rxd- (UART receiver serial input) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_74_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_74_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= gem3, Input, gem3_rgmii_rx_ctl- (RX RGMII control )*/
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_75_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= usb1, Input, usb1_ulpi_rx_data[7]- (ULPI data bus) 1= usb1, Output, usb1_ulpi_tx_
+		ata[7]- (ULPI data bus)*/
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_75_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Output, sdio0_bus_pow- (SD card bus power) 2= sd1, Input, sd1_cmd_in- (Comma
+		d Indicator) = sd1, Output, sdio1_cmd_out- (Command Indicator) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_75_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[23]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[23]- (GPIO bank 2) 1= c
+		n0, Output, can0_phy_tx- (Can TX signal) 2= i2c0, Input, i2c0_sda_input- (SDA signal) 2= i2c0, Output, i2c0_sda_out- (SDA sig
+		al) 3= swdt0, Output, swdt0_rst_out- (Watch Dog Timer Output clock) 4= spi1, Output, spi1_mo- (MOSI signal) 4= spi1, Input, s
+		i1_si- (MOSI signal) 5= Not Used 6= ua0, Output, ua0_txd- (UART transmitter serial output) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_75_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_75_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_76_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_76_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= sd0, Input, sdio0_wp- (SD card write protect from connector) 2= sd1, Output, sdio
+		_clk_out- (SDSDIO clock) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_76_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[24]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[24]- (GPIO bank 2) 1= c
+		n1, Output, can1_phy_tx- (Can TX signal) 2= i2c1, Input, i2c1_scl_input- (SCL signal) 2= i2c1, Output, i2c1_scl_out- (SCL sig
+		al) 3= mdio0, Output, gem0_mdc- (MDIO Clock) 4= mdio1, Output, gem1_mdc- (MDIO Clock) 5= mdio2, Output, gem2_mdc- (MDIO Clock
+		 6= mdio3, Output, gem3_mdc- (MDIO Clock) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_76_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_76_L3_SEL_MASK                                            0x000000E0U
+
+/*Level 0 Mux Select 0= Level 1 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L0_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_SHIFT                                           1
+#define IOU_SLCR_MIO_PIN_77_L0_SEL_MASK                                            0x00000002U
+
+/*Level 1 Mux Select 0= Level 2 Mux Output 1= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L1_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_SHIFT                                           2
+#define IOU_SLCR_MIO_PIN_77_L1_SEL_MASK                                            0x00000004U
+
+/*Level 2 Mux Select 0= Level 3 Mux Output 1= Not Used 2= sd1, Input, sdio1_cd_n- (SD card detect from connector) 3= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L2_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_SHIFT                                           3
+#define IOU_SLCR_MIO_PIN_77_L2_SEL_MASK                                            0x00000018U
+
+/*Level 3 Mux Select 0= gpio2, Input, gpio_2_pin_in[25]- (GPIO bank 2) 0= gpio2, Output, gpio_2_pin_out[25]- (GPIO bank 2) 1= c
+		n1, Input, can1_phy_rx- (Can RX signal) 2= i2c1, Input, i2c1_sda_input- (SDA signal) 2= i2c1, Output, i2c1_sda_out- (SDA sign
+		l) 3= mdio0, Input, gem0_mdio_in- (MDIO Data) 3= mdio0, Output, gem0_mdio_out- (MDIO Data) 4= mdio1, Input, gem1_mdio_in- (MD
+		O Data) 4= mdio1, Output, gem1_mdio_out- (MDIO Data) 5= mdio2, Input, gem2_mdio_in- (MDIO Data) 5= mdio2, Output, gem2_mdio_o
+		t- (MDIO Data) 6= mdio3, Input, gem3_mdio_in- (MDIO Data) 6= mdio3, Output, gem3_mdio_out- (MDIO Data) 7= Not Used*/
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL 
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT 
+#undef IOU_SLCR_MIO_PIN_77_L3_SEL_MASK 
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_DEFVAL                                          0x00000000
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_SHIFT                                           5
+#define IOU_SLCR_MIO_PIN_77_L3_SEL_MASK                                            0x000000E0U
+
+/*Master Tri-state Enable for pin 0, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI0_PIN_00_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 1, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI0_PIN_01_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 2, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI0_PIN_02_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 3, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI0_PIN_03_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 4, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI0_PIN_04_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 5, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI0_PIN_05_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 6, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI0_PIN_06_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 7, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI0_PIN_07_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 8, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI0_PIN_08_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 9, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI0_PIN_09_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 10, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI0_PIN_10_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 11, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI0_PIN_11_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 12, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI0_PIN_12_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 13, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI0_PIN_13_TRI_MASK                                      0x00002000U
+
+/*Master Tri-state Enable for pin 14, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_SHIFT                                     14
+#define IOU_SLCR_MIO_MST_TRI0_PIN_14_TRI_MASK                                      0x00004000U
+
+/*Master Tri-state Enable for pin 15, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_SHIFT                                     15
+#define IOU_SLCR_MIO_MST_TRI0_PIN_15_TRI_MASK                                      0x00008000U
+
+/*Master Tri-state Enable for pin 16, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_SHIFT                                     16
+#define IOU_SLCR_MIO_MST_TRI0_PIN_16_TRI_MASK                                      0x00010000U
+
+/*Master Tri-state Enable for pin 17, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_SHIFT                                     17
+#define IOU_SLCR_MIO_MST_TRI0_PIN_17_TRI_MASK                                      0x00020000U
+
+/*Master Tri-state Enable for pin 18, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_SHIFT                                     18
+#define IOU_SLCR_MIO_MST_TRI0_PIN_18_TRI_MASK                                      0x00040000U
+
+/*Master Tri-state Enable for pin 19, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_SHIFT                                     19
+#define IOU_SLCR_MIO_MST_TRI0_PIN_19_TRI_MASK                                      0x00080000U
+
+/*Master Tri-state Enable for pin 20, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_SHIFT                                     20
+#define IOU_SLCR_MIO_MST_TRI0_PIN_20_TRI_MASK                                      0x00100000U
+
+/*Master Tri-state Enable for pin 21, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_SHIFT                                     21
+#define IOU_SLCR_MIO_MST_TRI0_PIN_21_TRI_MASK                                      0x00200000U
+
+/*Master Tri-state Enable for pin 22, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_SHIFT                                     22
+#define IOU_SLCR_MIO_MST_TRI0_PIN_22_TRI_MASK                                      0x00400000U
+
+/*Master Tri-state Enable for pin 23, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_SHIFT                                     23
+#define IOU_SLCR_MIO_MST_TRI0_PIN_23_TRI_MASK                                      0x00800000U
+
+/*Master Tri-state Enable for pin 24, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_SHIFT                                     24
+#define IOU_SLCR_MIO_MST_TRI0_PIN_24_TRI_MASK                                      0x01000000U
+
+/*Master Tri-state Enable for pin 25, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_SHIFT                                     25
+#define IOU_SLCR_MIO_MST_TRI0_PIN_25_TRI_MASK                                      0x02000000U
+
+/*Master Tri-state Enable for pin 26, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_SHIFT                                     26
+#define IOU_SLCR_MIO_MST_TRI0_PIN_26_TRI_MASK                                      0x04000000U
+
+/*Master Tri-state Enable for pin 27, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_SHIFT                                     27
+#define IOU_SLCR_MIO_MST_TRI0_PIN_27_TRI_MASK                                      0x08000000U
+
+/*Master Tri-state Enable for pin 28, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_SHIFT                                     28
+#define IOU_SLCR_MIO_MST_TRI0_PIN_28_TRI_MASK                                      0x10000000U
+
+/*Master Tri-state Enable for pin 29, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_SHIFT                                     29
+#define IOU_SLCR_MIO_MST_TRI0_PIN_29_TRI_MASK                                      0x20000000U
+
+/*Master Tri-state Enable for pin 30, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_SHIFT                                     30
+#define IOU_SLCR_MIO_MST_TRI0_PIN_30_TRI_MASK                                      0x40000000U
+
+/*Master Tri-state Enable for pin 31, active high*/
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_SHIFT                                     31
+#define IOU_SLCR_MIO_MST_TRI0_PIN_31_TRI_MASK                                      0x80000000U
+
+/*Master Tri-state Enable for pin 32, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI1_PIN_32_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 33, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI1_PIN_33_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 34, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI1_PIN_34_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 35, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI1_PIN_35_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 36, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI1_PIN_36_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 37, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI1_PIN_37_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 38, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI1_PIN_38_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 39, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI1_PIN_39_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 40, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI1_PIN_40_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 41, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI1_PIN_41_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 42, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI1_PIN_42_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 43, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI1_PIN_43_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 44, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI1_PIN_44_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 45, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI1_PIN_45_TRI_MASK                                      0x00002000U
+
+/*Master Tri-state Enable for pin 46, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_SHIFT                                     14
+#define IOU_SLCR_MIO_MST_TRI1_PIN_46_TRI_MASK                                      0x00004000U
+
+/*Master Tri-state Enable for pin 47, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_SHIFT                                     15
+#define IOU_SLCR_MIO_MST_TRI1_PIN_47_TRI_MASK                                      0x00008000U
+
+/*Master Tri-state Enable for pin 48, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_SHIFT                                     16
+#define IOU_SLCR_MIO_MST_TRI1_PIN_48_TRI_MASK                                      0x00010000U
+
+/*Master Tri-state Enable for pin 49, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_SHIFT                                     17
+#define IOU_SLCR_MIO_MST_TRI1_PIN_49_TRI_MASK                                      0x00020000U
+
+/*Master Tri-state Enable for pin 50, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_SHIFT                                     18
+#define IOU_SLCR_MIO_MST_TRI1_PIN_50_TRI_MASK                                      0x00040000U
+
+/*Master Tri-state Enable for pin 51, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_SHIFT                                     19
+#define IOU_SLCR_MIO_MST_TRI1_PIN_51_TRI_MASK                                      0x00080000U
+
+/*Master Tri-state Enable for pin 52, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_SHIFT                                     20
+#define IOU_SLCR_MIO_MST_TRI1_PIN_52_TRI_MASK                                      0x00100000U
+
+/*Master Tri-state Enable for pin 53, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_SHIFT                                     21
+#define IOU_SLCR_MIO_MST_TRI1_PIN_53_TRI_MASK                                      0x00200000U
+
+/*Master Tri-state Enable for pin 54, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_SHIFT                                     22
+#define IOU_SLCR_MIO_MST_TRI1_PIN_54_TRI_MASK                                      0x00400000U
+
+/*Master Tri-state Enable for pin 55, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_SHIFT                                     23
+#define IOU_SLCR_MIO_MST_TRI1_PIN_55_TRI_MASK                                      0x00800000U
+
+/*Master Tri-state Enable for pin 56, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_SHIFT                                     24
+#define IOU_SLCR_MIO_MST_TRI1_PIN_56_TRI_MASK                                      0x01000000U
+
+/*Master Tri-state Enable for pin 57, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_SHIFT                                     25
+#define IOU_SLCR_MIO_MST_TRI1_PIN_57_TRI_MASK                                      0x02000000U
+
+/*Master Tri-state Enable for pin 58, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_SHIFT                                     26
+#define IOU_SLCR_MIO_MST_TRI1_PIN_58_TRI_MASK                                      0x04000000U
+
+/*Master Tri-state Enable for pin 59, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_SHIFT                                     27
+#define IOU_SLCR_MIO_MST_TRI1_PIN_59_TRI_MASK                                      0x08000000U
+
+/*Master Tri-state Enable for pin 60, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_SHIFT                                     28
+#define IOU_SLCR_MIO_MST_TRI1_PIN_60_TRI_MASK                                      0x10000000U
+
+/*Master Tri-state Enable for pin 61, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_SHIFT                                     29
+#define IOU_SLCR_MIO_MST_TRI1_PIN_61_TRI_MASK                                      0x20000000U
+
+/*Master Tri-state Enable for pin 62, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_SHIFT                                     30
+#define IOU_SLCR_MIO_MST_TRI1_PIN_62_TRI_MASK                                      0x40000000U
+
+/*Master Tri-state Enable for pin 63, active high*/
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_DEFVAL                                    0xFFFFFFFF
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_SHIFT                                     31
+#define IOU_SLCR_MIO_MST_TRI1_PIN_63_TRI_MASK                                      0x80000000U
+
+/*Master Tri-state Enable for pin 64, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_SHIFT                                     0
+#define IOU_SLCR_MIO_MST_TRI2_PIN_64_TRI_MASK                                      0x00000001U
+
+/*Master Tri-state Enable for pin 65, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_SHIFT                                     1
+#define IOU_SLCR_MIO_MST_TRI2_PIN_65_TRI_MASK                                      0x00000002U
+
+/*Master Tri-state Enable for pin 66, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_SHIFT                                     2
+#define IOU_SLCR_MIO_MST_TRI2_PIN_66_TRI_MASK                                      0x00000004U
+
+/*Master Tri-state Enable for pin 67, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_SHIFT                                     3
+#define IOU_SLCR_MIO_MST_TRI2_PIN_67_TRI_MASK                                      0x00000008U
+
+/*Master Tri-state Enable for pin 68, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_SHIFT                                     4
+#define IOU_SLCR_MIO_MST_TRI2_PIN_68_TRI_MASK                                      0x00000010U
+
+/*Master Tri-state Enable for pin 69, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_SHIFT                                     5
+#define IOU_SLCR_MIO_MST_TRI2_PIN_69_TRI_MASK                                      0x00000020U
+
+/*Master Tri-state Enable for pin 70, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_SHIFT                                     6
+#define IOU_SLCR_MIO_MST_TRI2_PIN_70_TRI_MASK                                      0x00000040U
+
+/*Master Tri-state Enable for pin 71, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_SHIFT                                     7
+#define IOU_SLCR_MIO_MST_TRI2_PIN_71_TRI_MASK                                      0x00000080U
+
+/*Master Tri-state Enable for pin 72, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_SHIFT                                     8
+#define IOU_SLCR_MIO_MST_TRI2_PIN_72_TRI_MASK                                      0x00000100U
+
+/*Master Tri-state Enable for pin 73, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_SHIFT                                     9
+#define IOU_SLCR_MIO_MST_TRI2_PIN_73_TRI_MASK                                      0x00000200U
+
+/*Master Tri-state Enable for pin 74, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_SHIFT                                     10
+#define IOU_SLCR_MIO_MST_TRI2_PIN_74_TRI_MASK                                      0x00000400U
+
+/*Master Tri-state Enable for pin 75, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_SHIFT                                     11
+#define IOU_SLCR_MIO_MST_TRI2_PIN_75_TRI_MASK                                      0x00000800U
+
+/*Master Tri-state Enable for pin 76, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_SHIFT                                     12
+#define IOU_SLCR_MIO_MST_TRI2_PIN_76_TRI_MASK                                      0x00001000U
+
+/*Master Tri-state Enable for pin 77, active high*/
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT 
+#undef IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK 
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_DEFVAL                                    0x00003FFF
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_SHIFT                                     13
+#define IOU_SLCR_MIO_MST_TRI2_PIN_77_TRI_MASK                                      0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK0_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK0_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL                           
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
+#define IOU_SLCR_BANK0_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL                          
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
+#define IOU_SLCR_BANK0_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               0
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               1
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               2
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               3
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               4
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               5
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               6
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               7
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               8
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_DEFVAL                              
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               9
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              10
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              11
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              12
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              13
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              14
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              15
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              16
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              17
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              18
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              19
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              20
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              21
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              22
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              23
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              24
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_DEFVAL                             
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              25
+#define IOU_SLCR_BANK0_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL                         
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[0].*/
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL                        
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
+#define IOU_SLCR_BANK0_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK1_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK1_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL                           
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
+#define IOU_SLCR_BANK1_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL                          
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
+#define IOU_SLCR_BANK1_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               0
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               1
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               2
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               3
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               4
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               5
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               6
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               7
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               8
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_DEFVAL                              
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               9
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              10
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              11
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              12
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              13
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              14
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              15
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              16
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              17
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              18
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              19
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              20
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              21
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              22
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              23
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              24
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_DEFVAL                             
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              25
+#define IOU_SLCR_BANK1_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL                         
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[26].*/
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL                        
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
+#define IOU_SLCR_BANK1_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK2_CTRL0_DRIVE0_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_SHIFT                                    0
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_0_MASK                                     0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_SHIFT                                    1
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_1_MASK                                     0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_SHIFT                                    2
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_2_MASK                                     0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_SHIFT                                    3
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_3_MASK                                     0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_SHIFT                                    4
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_4_MASK                                     0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_SHIFT                                    5
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_5_MASK                                     0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_SHIFT                                    6
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_6_MASK                                     0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_SHIFT                                    7
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_7_MASK                                     0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_SHIFT                                    8
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_8_MASK                                     0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_DEFVAL                                   
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_SHIFT                                    9
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_9_MASK                                     0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_SHIFT                                   10
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_10_MASK                                    0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_SHIFT                                   11
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_11_MASK                                    0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_SHIFT                                   12
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_12_MASK                                    0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_SHIFT                                   13
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_13_MASK                                    0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_SHIFT                                   14
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_14_MASK                                    0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_SHIFT                                   15
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_15_MASK                                    0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_SHIFT                                   16
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_16_MASK                                    0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_SHIFT                                   17
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_17_MASK                                    0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_SHIFT                                   18
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_18_MASK                                    0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_SHIFT                                   19
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_19_MASK                                    0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_SHIFT                                   20
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_20_MASK                                    0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_SHIFT                                   21
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_21_MASK                                    0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_SHIFT                                   22
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_22_MASK                                    0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_SHIFT                                   23
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_23_MASK                                    0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_SHIFT                                   24
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_24_MASK                                    0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_DEFVAL                                  
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_SHIFT                                   25
+#define IOU_SLCR_BANK2_CTRL1_DRIVE1_BIT_25_MASK                                    0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_SHIFT                            0
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_0_MASK                             0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_SHIFT                            1
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_1_MASK                             0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_SHIFT                            2
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_2_MASK                             0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_SHIFT                            3
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_3_MASK                             0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_SHIFT                            4
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_4_MASK                             0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_SHIFT                            5
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_5_MASK                             0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_SHIFT                            6
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_6_MASK                             0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_SHIFT                            7
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_7_MASK                             0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_SHIFT                            8
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_8_MASK                             0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_DEFVAL                           
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_SHIFT                            9
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_9_MASK                             0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_SHIFT                           10
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_10_MASK                            0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_SHIFT                           11
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_11_MASK                            0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_SHIFT                           12
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_12_MASK                            0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_SHIFT                           13
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_13_MASK                            0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_SHIFT                           14
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_14_MASK                            0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_SHIFT                           15
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_15_MASK                            0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_SHIFT                           16
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_16_MASK                            0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_SHIFT                           17
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_17_MASK                            0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_SHIFT                           18
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_18_MASK                            0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_SHIFT                           19
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_19_MASK                            0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_SHIFT                           20
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_20_MASK                            0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_SHIFT                           21
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_21_MASK                            0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_SHIFT                           22
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_22_MASK                            0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_SHIFT                           23
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_23_MASK                            0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_SHIFT                           24
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_24_MASK                            0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_SHIFT                           25
+#define IOU_SLCR_BANK2_CTRL3_SCHMITT_CMOS_N_BIT_25_MASK                            0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_SHIFT                           0
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_0_MASK                            0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_SHIFT                           1
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_1_MASK                            0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_SHIFT                           2
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_2_MASK                            0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_SHIFT                           3
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_3_MASK                            0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_SHIFT                           4
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_4_MASK                            0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_SHIFT                           5
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_5_MASK                            0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_SHIFT                           6
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_6_MASK                            0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_SHIFT                           7
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_7_MASK                            0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_SHIFT                           8
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_8_MASK                            0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_DEFVAL                          
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_SHIFT                           9
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_9_MASK                            0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_SHIFT                          10
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_10_MASK                           0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_SHIFT                          11
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_11_MASK                           0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_SHIFT                          12
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_12_MASK                           0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_SHIFT                          13
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_13_MASK                           0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_SHIFT                          14
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_14_MASK                           0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_SHIFT                          15
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_15_MASK                           0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_SHIFT                          16
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_16_MASK                           0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_SHIFT                          17
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_17_MASK                           0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_SHIFT                          18
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_18_MASK                           0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_SHIFT                          19
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_19_MASK                           0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_SHIFT                          20
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_20_MASK                           0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_SHIFT                          21
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_21_MASK                           0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_SHIFT                          22
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_22_MASK                           0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_SHIFT                          23
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_23_MASK                           0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_SHIFT                          24
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_24_MASK                           0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_SHIFT                          25
+#define IOU_SLCR_BANK2_CTRL4_PULL_HIGH_LOW_N_BIT_25_MASK                           0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_SHIFT                               0
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_0_MASK                                0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_SHIFT                               1
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_1_MASK                                0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_SHIFT                               2
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_2_MASK                                0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_SHIFT                               3
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_3_MASK                                0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_SHIFT                               4
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_4_MASK                                0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_SHIFT                               5
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_5_MASK                                0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_SHIFT                               6
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_6_MASK                                0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_SHIFT                               7
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_7_MASK                                0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_SHIFT                               8
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_8_MASK                                0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_DEFVAL                              
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_SHIFT                               9
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_9_MASK                                0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_SHIFT                              10
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_10_MASK                               0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_SHIFT                              11
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_11_MASK                               0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_SHIFT                              12
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_12_MASK                               0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_SHIFT                              13
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_13_MASK                               0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_SHIFT                              14
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_14_MASK                               0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_SHIFT                              15
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_15_MASK                               0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_SHIFT                              16
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_16_MASK                               0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_SHIFT                              17
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_17_MASK                               0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_SHIFT                              18
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_18_MASK                               0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_SHIFT                              19
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_19_MASK                               0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_SHIFT                              20
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_20_MASK                               0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_SHIFT                              21
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_21_MASK                               0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_SHIFT                              22
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_22_MASK                               0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_SHIFT                              23
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_23_MASK                               0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_SHIFT                              24
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_24_MASK                               0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_DEFVAL                             
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_SHIFT                              25
+#define IOU_SLCR_BANK2_CTRL5_PULL_ENABLE_BIT_25_MASK                               0x02000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_SHIFT                          0
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_0_MASK                           0x00000001U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_SHIFT                          1
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_1_MASK                           0x00000002U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_SHIFT                          2
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_2_MASK                           0x00000004U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_SHIFT                          3
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_3_MASK                           0x00000008U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_SHIFT                          4
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_4_MASK                           0x00000010U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_SHIFT                          5
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_5_MASK                           0x00000020U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_SHIFT                          6
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_6_MASK                           0x00000040U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_SHIFT                          7
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_7_MASK                           0x00000080U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_SHIFT                          8
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_8_MASK                           0x00000100U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_DEFVAL                         
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_SHIFT                          9
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_9_MASK                           0x00000200U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_SHIFT                         10
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_10_MASK                          0x00000400U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_SHIFT                         11
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_11_MASK                          0x00000800U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_SHIFT                         12
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_12_MASK                          0x00001000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_SHIFT                         13
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_13_MASK                          0x00002000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_SHIFT                         14
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_14_MASK                          0x00004000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_SHIFT                         15
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_15_MASK                          0x00008000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_SHIFT                         16
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_16_MASK                          0x00010000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_SHIFT                         17
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_17_MASK                          0x00020000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_SHIFT                         18
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_18_MASK                          0x00040000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_SHIFT                         19
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_19_MASK                          0x00080000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_SHIFT                         20
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_20_MASK                          0x00100000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_SHIFT                         21
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_21_MASK                          0x00200000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_SHIFT                         22
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_22_MASK                          0x00400000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_SHIFT                         23
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_23_MASK                          0x00800000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_SHIFT                         24
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_24_MASK                          0x01000000U
+
+/*Each bit applies to a single IO. Bit 0 for MIO[52].*/
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT 
+#undef IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK 
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_DEFVAL                        
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_SHIFT                         25
+#define IOU_SLCR_BANK2_CTRL6_SLOW_FAST_SLEW_N_BIT_25_MASK                          0x02000000U
+
+/*I2C Loopback Control. 0 = Connect I2C inputs according to MIO mapping. 1 = Loop I2C 0 outputs to I2C 1 inputs, and I2C 1 outp
+		ts to I2C 0 inputs.*/
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_SHIFT                                 3
+#define IOU_SLCR_MIO_LOOPBACK_I2C0_LOOP_I2C1_MASK                                  0x00000008U
+
+/*CAN Loopback Control. 0 = Connect CAN inputs according to MIO mapping. 1 = Loop CAN 0 Tx to CAN 1 Rx, and CAN 1 Tx to CAN 0 R
+		.*/
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_SHIFT                                 2
+#define IOU_SLCR_MIO_LOOPBACK_CAN0_LOOP_CAN1_MASK                                  0x00000004U
+
+/*UART Loopback Control. 0 = Connect UART inputs according to MIO mapping. 1 = Loop UART 0 outputs to UART 1 inputs, and UART 1
+		outputs to UART 0 inputs. RXD/TXD cross-connected. RTS/CTS cross-connected. DSR, DTR, DCD and RI not used.*/
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_DEFVAL                                  0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_SHIFT                                   1
+#define IOU_SLCR_MIO_LOOPBACK_UA0_LOOP_UA1_MASK                                    0x00000002U
+
+/*SPI Loopback Control. 0 = Connect SPI inputs according to MIO mapping. 1 = Loop SPI 0 outputs to SPI 1 inputs, and SPI 1 outp
+		ts to SPI 0 inputs. The other SPI core will appear on the LS Slave Select.*/
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL 
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT 
+#undef IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK 
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_DEFVAL                                0x00000000
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_SHIFT                                 0
+#define IOU_SLCR_MIO_LOOPBACK_SPI0_LOOP_SPI1_MASK                                  0x00000001U
+#undef CRL_APB_RST_LPD_IOU0_OFFSET 
+#define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef IOU_SLCR_CTRL_REG_SD_OFFSET 
+#define IOU_SLCR_CTRL_REG_SD_OFFSET                                                0XFF180310
+#undef IOU_SLCR_SD_CONFIG_REG2_OFFSET 
+#define IOU_SLCR_SD_CONFIG_REG2_OFFSET                                             0XFF180320
+#undef IOU_SLCR_SD_CONFIG_REG1_OFFSET 
+#define IOU_SLCR_SD_CONFIG_REG1_OFFSET                                             0XFF18031C
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef CRL_APB_RST_LPD_IOU2_OFFSET 
+#define CRL_APB_RST_LPD_IOU2_OFFSET                                                0XFF5E0238
+#undef UART0_BAUD_RATE_DIVIDER_REG0_OFFSET 
+#define UART0_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF000034
+#undef UART0_BAUD_RATE_GEN_REG0_OFFSET 
+#define UART0_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF000018
+#undef UART0_CONTROL_REG0_OFFSET 
+#define UART0_CONTROL_REG0_OFFSET                                                  0XFF000000
+#undef UART0_MODE_REG0_OFFSET 
+#define UART0_MODE_REG0_OFFSET                                                     0XFF000004
+#undef UART1_BAUD_RATE_DIVIDER_REG0_OFFSET 
+#define UART1_BAUD_RATE_DIVIDER_REG0_OFFSET                                        0XFF010034
+#undef UART1_BAUD_RATE_GEN_REG0_OFFSET 
+#define UART1_BAUD_RATE_GEN_REG0_OFFSET                                            0XFF010018
+#undef UART1_CONTROL_REG0_OFFSET 
+#define UART1_CONTROL_REG0_OFFSET                                                  0XFF010000
+#undef UART1_MODE_REG0_OFFSET 
+#define UART1_MODE_REG0_OFFSET                                                     0XFF010004
+#undef LPD_SLCR_SECURE_SLCR_ADMA_OFFSET 
+#define LPD_SLCR_SECURE_SLCR_ADMA_OFFSET                                           0XFF4B0024
+#undef CSU_TAMPER_STATUS_OFFSET 
+#define CSU_TAMPER_STATUS_OFFSET                                                   0XFFCA5000
+#undef APU_ACE_CTRL_OFFSET 
+#define APU_ACE_CTRL_OFFSET                                                        0XFD5C0060
+#undef RTC_CONTROL_OFFSET 
+#define RTC_CONTROL_OFFSET                                                         0XFFA60040
+
+/*GEM 3 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_SHIFT                                      0
+#define CRL_APB_RST_LPD_IOU2_QSPI_RESET_MASK                                       0x00000001U
+
+/*USB 0 reset for control registers*/
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
+
+/*USB 0 sleep circuit reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
+
+/*USB 0 reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
+
+/*PCIE config reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL                                  0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT                                   19
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                                    0x00080000U
+
+/*PCIE control block level reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL                                 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT                                  17
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK                                   0x00020000U
+
+/*PCIE bridge block level reset (AXI interface)*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL                               0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT                                18
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK                                 0x00040000U
+
+/*Display Port block level reset (includes DPDMA)*/
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
+#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
+
+/*FPD WDT reset*/
+#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_SWDT_RESET_DEFVAL                                      0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_SWDT_RESET_SHIFT                                       15
+#define CRF_APB_RST_FPD_TOP_SWDT_RESET_MASK                                        0x00008000U
+
+/*GDMA block level reset*/
+#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_GDMA_RESET_DEFVAL                                      0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_GDMA_RESET_SHIFT                                       6
+#define CRF_APB_RST_FPD_TOP_GDMA_RESET_MASK                                        0x00000040U
+
+/*Pixel Processor (submodule of GPU) block level reset*/
+#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_DEFVAL                                   0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_SHIFT                                    4
+#define CRF_APB_RST_FPD_TOP_GPU_PP0_RESET_MASK                                     0x00000010U
+
+/*Pixel Processor (submodule of GPU) block level reset*/
+#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_DEFVAL                                   0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_SHIFT                                    5
+#define CRF_APB_RST_FPD_TOP_GPU_PP1_RESET_MASK                                     0x00000020U
+
+/*GPU block level reset*/
+#undef CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_GPU_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_GPU_RESET_DEFVAL                                       0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_GPU_RESET_SHIFT                                        3
+#define CRF_APB_RST_FPD_TOP_GPU_RESET_MASK                                         0x00000008U
+
+/*GT block level reset*/
+#undef CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_GT_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_GT_RESET_DEFVAL                                        0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_GT_RESET_SHIFT                                         2
+#define CRF_APB_RST_FPD_TOP_GT_RESET_MASK                                          0x00000004U
+
+/*Sata block level reset*/
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_SHIFT                                     6
+#define CRL_APB_RST_LPD_IOU2_SDIO1_RESET_MASK                                      0x00000040U
+
+/*SD or eMMC selection on SDIO1 0: SD enabled 1: eMMC enabled*/
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL 
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT 
+#undef IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK 
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_DEFVAL                                   0x00000000
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_SHIFT                                    15
+#define IOU_SLCR_CTRL_REG_SD_SD1_EMMC_SEL_MASK                                     0x00008000U
+
+/*Should be set based on the final product usage 00 - Removable SCard Slot 01 - Embedded Slot for One Device 10 - Shared Bus Sl
+		t 11 - Reserved*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_DEFVAL                                0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_SHIFT                                 28
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_SLOTTYPE_MASK                                  0x30000000U
+
+/*1.8V Support 1: 1.8V supported 0: 1.8V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_SHIFT                                     25
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_1P8V_MASK                                      0x02000000U
+
+/*3.0V Support 1: 3.0V supported 0: 3.0V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_SHIFT                                     24
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P0V_MASK                                      0x01000000U
+
+/*3.3V Support 1: 3.3V supported 0: 3.3V not supported support*/
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK 
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_DEFVAL                                    0x0FFC0FFC
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_SHIFT                                     23
+#define IOU_SLCR_SD_CONFIG_REG2_SD1_3P3V_MASK                                      0x00800000U
+
+/*Base Clock Frequency for SD Clock. This is the frequency of the xin_clk.*/
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL 
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT 
+#undef IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK 
+#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_DEFVAL                                 0x32403240
+#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_SHIFT                                  23
+#define IOU_SLCR_SD_CONFIG_REG1_SD1_BASECLK_MASK                                   0x7F800000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_SHIFT                                      8
+#define CRL_APB_RST_LPD_IOU2_CAN1_RESET_MASK                                       0x00000100U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_SHIFT                                      9
+#define CRL_APB_RST_LPD_IOU2_I2C0_RESET_MASK                                       0x00000200U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_SHIFT                                      10
+#define CRL_APB_RST_LPD_IOU2_I2C1_RESET_MASK                                       0x00000400U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_SHIFT                                      15
+#define CRL_APB_RST_LPD_IOU2_SWDT_RESET_MASK                                       0x00008000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_SHIFT                                      11
+#define CRL_APB_RST_LPD_IOU2_TTC0_RESET_MASK                                       0x00000800U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_SHIFT                                      12
+#define CRL_APB_RST_LPD_IOU2_TTC1_RESET_MASK                                       0x00001000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_SHIFT                                      13
+#define CRL_APB_RST_LPD_IOU2_TTC2_RESET_MASK                                       0x00002000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_DEFVAL                                     0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_SHIFT                                      14
+#define CRL_APB_RST_LPD_IOU2_TTC3_RESET_MASK                                       0x00004000U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_SHIFT                                     1
+#define CRL_APB_RST_LPD_IOU2_UART0_RESET_MASK                                      0x00000002U
+
+/*Block level reset*/
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_DEFVAL                                    0x0017FFFF
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_SHIFT                                     2
+#define CRL_APB_RST_LPD_IOU2_UART1_RESET_MASK                                      0x00000004U
+
+/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
+#undef UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
+#define UART0_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
+
+/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
+#undef UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL 
+#undef UART0_BAUD_RATE_GEN_REG0_CD_SHIFT 
+#undef UART0_BAUD_RATE_GEN_REG0_CD_MASK 
+#define UART0_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
+#define UART0_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
+#define UART0_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
+
+/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
+#undef UART0_CONTROL_REG0_STPBRK_DEFVAL 
+#undef UART0_CONTROL_REG0_STPBRK_SHIFT 
+#undef UART0_CONTROL_REG0_STPBRK_MASK 
+#define UART0_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
+#define UART0_CONTROL_REG0_STPBRK_SHIFT                                            8
+#define UART0_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
+
+/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
+#undef UART0_CONTROL_REG0_STTBRK_DEFVAL 
+#undef UART0_CONTROL_REG0_STTBRK_SHIFT 
+#undef UART0_CONTROL_REG0_STTBRK_MASK 
+#define UART0_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
+#define UART0_CONTROL_REG0_STTBRK_SHIFT                                            7
+#define UART0_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
+
+/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.*/
+#undef UART0_CONTROL_REG0_RSTTO_DEFVAL 
+#undef UART0_CONTROL_REG0_RSTTO_SHIFT 
+#undef UART0_CONTROL_REG0_RSTTO_MASK 
+#define UART0_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RSTTO_SHIFT                                             6
+#define UART0_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
+
+/*Transmit disable: 0: enable transmitter 1: disable transmitter*/
+#undef UART0_CONTROL_REG0_TXDIS_DEFVAL 
+#undef UART0_CONTROL_REG0_TXDIS_SHIFT 
+#undef UART0_CONTROL_REG0_TXDIS_MASK 
+#define UART0_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_TXDIS_SHIFT                                             5
+#define UART0_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
+
+/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
+#undef UART0_CONTROL_REG0_TXEN_DEFVAL 
+#undef UART0_CONTROL_REG0_TXEN_SHIFT 
+#undef UART0_CONTROL_REG0_TXEN_MASK 
+#define UART0_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
+#define UART0_CONTROL_REG0_TXEN_SHIFT                                              4
+#define UART0_CONTROL_REG0_TXEN_MASK                                               0x00000010U
+
+/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
+#undef UART0_CONTROL_REG0_RXDIS_DEFVAL 
+#undef UART0_CONTROL_REG0_RXDIS_SHIFT 
+#undef UART0_CONTROL_REG0_RXDIS_MASK 
+#define UART0_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RXDIS_SHIFT                                             3
+#define UART0_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
+
+/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
+#undef UART0_CONTROL_REG0_RXEN_DEFVAL 
+#undef UART0_CONTROL_REG0_RXEN_SHIFT 
+#undef UART0_CONTROL_REG0_RXEN_MASK 
+#define UART0_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
+#define UART0_CONTROL_REG0_RXEN_SHIFT                                              2
+#define UART0_CONTROL_REG0_RXEN_MASK                                               0x00000004U
+
+/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.*/
+#undef UART0_CONTROL_REG0_TXRES_DEFVAL 
+#undef UART0_CONTROL_REG0_TXRES_SHIFT 
+#undef UART0_CONTROL_REG0_TXRES_MASK 
+#define UART0_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_TXRES_SHIFT                                             1
+#define UART0_CONTROL_REG0_TXRES_MASK                                              0x00000002U
+
+/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.*/
+#undef UART0_CONTROL_REG0_RXRES_DEFVAL 
+#undef UART0_CONTROL_REG0_RXRES_SHIFT 
+#undef UART0_CONTROL_REG0_RXRES_MASK 
+#define UART0_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
+#define UART0_CONTROL_REG0_RXRES_SHIFT                                             0
+#define UART0_CONTROL_REG0_RXRES_MASK                                              0x00000001U
+
+/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
+#undef UART0_MODE_REG0_CHMODE_DEFVAL 
+#undef UART0_MODE_REG0_CHMODE_SHIFT 
+#undef UART0_MODE_REG0_CHMODE_MASK 
+#define UART0_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
+#define UART0_MODE_REG0_CHMODE_SHIFT                                               8
+#define UART0_MODE_REG0_CHMODE_MASK                                                0x00000300U
+
+/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved*/
+#undef UART0_MODE_REG0_NBSTOP_DEFVAL 
+#undef UART0_MODE_REG0_NBSTOP_SHIFT 
+#undef UART0_MODE_REG0_NBSTOP_MASK 
+#define UART0_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
+#define UART0_MODE_REG0_NBSTOP_SHIFT                                               6
+#define UART0_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
+
+/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
+#undef UART0_MODE_REG0_PAR_DEFVAL 
+#undef UART0_MODE_REG0_PAR_SHIFT 
+#undef UART0_MODE_REG0_PAR_MASK 
+#define UART0_MODE_REG0_PAR_DEFVAL                                                 0x00000000
+#define UART0_MODE_REG0_PAR_SHIFT                                                  3
+#define UART0_MODE_REG0_PAR_MASK                                                   0x00000038U
+
+/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
+#undef UART0_MODE_REG0_CHRL_DEFVAL 
+#undef UART0_MODE_REG0_CHRL_SHIFT 
+#undef UART0_MODE_REG0_CHRL_MASK 
+#define UART0_MODE_REG0_CHRL_DEFVAL                                                0x00000000
+#define UART0_MODE_REG0_CHRL_SHIFT                                                 1
+#define UART0_MODE_REG0_CHRL_MASK                                                  0x00000006U
+
+/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
+#undef UART0_MODE_REG0_CLKS_DEFVAL 
+#undef UART0_MODE_REG0_CLKS_SHIFT 
+#undef UART0_MODE_REG0_CLKS_MASK 
+#define UART0_MODE_REG0_CLKS_DEFVAL                                                0x00000000
+#define UART0_MODE_REG0_CLKS_SHIFT                                                 0
+#define UART0_MODE_REG0_CLKS_MASK                                                  0x00000001U
+
+/*Baud rate divider value: 0 - 3: ignored 4 - 255: Baud rate*/
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL 
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT 
+#undef UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK 
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_DEFVAL                                   0x0000000F
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_SHIFT                                    0
+#define UART1_BAUD_RATE_DIVIDER_REG0_BDIV_MASK                                     0x000000FFU
+
+/*Baud Rate Clock Divisor Value: 0: Disables baud_sample 1: Clock divisor bypass (baud_sample = sel_clk) 2 - 65535: baud_sample*/
+#undef UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL 
+#undef UART1_BAUD_RATE_GEN_REG0_CD_SHIFT 
+#undef UART1_BAUD_RATE_GEN_REG0_CD_MASK 
+#define UART1_BAUD_RATE_GEN_REG0_CD_DEFVAL                                         0x0000028B
+#define UART1_BAUD_RATE_GEN_REG0_CD_SHIFT                                          0
+#define UART1_BAUD_RATE_GEN_REG0_CD_MASK                                           0x0000FFFFU
+
+/*Stop transmitter break: 0: no affect 1: stop transmission of the break after a minimum of one character length and transmit a
+		high level during 12 bit periods. It can be set regardless of the value of STTBRK.*/
+#undef UART1_CONTROL_REG0_STPBRK_DEFVAL 
+#undef UART1_CONTROL_REG0_STPBRK_SHIFT 
+#undef UART1_CONTROL_REG0_STPBRK_MASK 
+#define UART1_CONTROL_REG0_STPBRK_DEFVAL                                           0x00000128
+#define UART1_CONTROL_REG0_STPBRK_SHIFT                                            8
+#define UART1_CONTROL_REG0_STPBRK_MASK                                             0x00000100U
+
+/*Start transmitter break: 0: no affect 1: start to transmit a break after the characters currently present in the FIFO and the
+		transmit shift register have been transmitted. It can only be set if STPBRK (Stop transmitter break) is not high.*/
+#undef UART1_CONTROL_REG0_STTBRK_DEFVAL 
+#undef UART1_CONTROL_REG0_STTBRK_SHIFT 
+#undef UART1_CONTROL_REG0_STTBRK_MASK 
+#define UART1_CONTROL_REG0_STTBRK_DEFVAL                                           0x00000128
+#define UART1_CONTROL_REG0_STTBRK_SHIFT                                            7
+#define UART1_CONTROL_REG0_STTBRK_MASK                                             0x00000080U
+
+/*Restart receiver timeout counter: 1: receiver timeout counter is restarted. This bit is self clearing once the restart has co
+		pleted.*/
+#undef UART1_CONTROL_REG0_RSTTO_DEFVAL 
+#undef UART1_CONTROL_REG0_RSTTO_SHIFT 
+#undef UART1_CONTROL_REG0_RSTTO_MASK 
+#define UART1_CONTROL_REG0_RSTTO_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RSTTO_SHIFT                                             6
+#define UART1_CONTROL_REG0_RSTTO_MASK                                              0x00000040U
+
+/*Transmit disable: 0: enable transmitter 1: disable transmitter*/
+#undef UART1_CONTROL_REG0_TXDIS_DEFVAL 
+#undef UART1_CONTROL_REG0_TXDIS_SHIFT 
+#undef UART1_CONTROL_REG0_TXDIS_MASK 
+#define UART1_CONTROL_REG0_TXDIS_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_TXDIS_SHIFT                                             5
+#define UART1_CONTROL_REG0_TXDIS_MASK                                              0x00000020U
+
+/*Transmit enable: 0: disable transmitter 1: enable transmitter, provided the TXDIS field is set to 0.*/
+#undef UART1_CONTROL_REG0_TXEN_DEFVAL 
+#undef UART1_CONTROL_REG0_TXEN_SHIFT 
+#undef UART1_CONTROL_REG0_TXEN_MASK 
+#define UART1_CONTROL_REG0_TXEN_DEFVAL                                             0x00000128
+#define UART1_CONTROL_REG0_TXEN_SHIFT                                              4
+#define UART1_CONTROL_REG0_TXEN_MASK                                               0x00000010U
+
+/*Receive disable: 0: enable 1: disable, regardless of the value of RXEN*/
+#undef UART1_CONTROL_REG0_RXDIS_DEFVAL 
+#undef UART1_CONTROL_REG0_RXDIS_SHIFT 
+#undef UART1_CONTROL_REG0_RXDIS_MASK 
+#define UART1_CONTROL_REG0_RXDIS_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RXDIS_SHIFT                                             3
+#define UART1_CONTROL_REG0_RXDIS_MASK                                              0x00000008U
+
+/*Receive enable: 0: disable 1: enable When set to one, the receiver logic is enabled, provided the RXDIS field is set to zero.*/
+#undef UART1_CONTROL_REG0_RXEN_DEFVAL 
+#undef UART1_CONTROL_REG0_RXEN_SHIFT 
+#undef UART1_CONTROL_REG0_RXEN_MASK 
+#define UART1_CONTROL_REG0_RXEN_DEFVAL                                             0x00000128
+#define UART1_CONTROL_REG0_RXEN_SHIFT                                              2
+#define UART1_CONTROL_REG0_RXEN_MASK                                               0x00000004U
+
+/*Software reset for Tx data path: 0: no affect 1: transmitter logic is reset and all pending transmitter data is discarded Thi
+		 bit is self clearing once the reset has completed.*/
+#undef UART1_CONTROL_REG0_TXRES_DEFVAL 
+#undef UART1_CONTROL_REG0_TXRES_SHIFT 
+#undef UART1_CONTROL_REG0_TXRES_MASK 
+#define UART1_CONTROL_REG0_TXRES_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_TXRES_SHIFT                                             1
+#define UART1_CONTROL_REG0_TXRES_MASK                                              0x00000002U
+
+/*Software reset for Rx data path: 0: no affect 1: receiver logic is reset and all pending receiver data is discarded. This bit
+		is self clearing once the reset has completed.*/
+#undef UART1_CONTROL_REG0_RXRES_DEFVAL 
+#undef UART1_CONTROL_REG0_RXRES_SHIFT 
+#undef UART1_CONTROL_REG0_RXRES_MASK 
+#define UART1_CONTROL_REG0_RXRES_DEFVAL                                            0x00000128
+#define UART1_CONTROL_REG0_RXRES_SHIFT                                             0
+#define UART1_CONTROL_REG0_RXRES_MASK                                              0x00000001U
+
+/*Channel mode: Defines the mode of operation of the UART. 00: normal 01: automatic echo 10: local loopback 11: remote loopback*/
+#undef UART1_MODE_REG0_CHMODE_DEFVAL 
+#undef UART1_MODE_REG0_CHMODE_SHIFT 
+#undef UART1_MODE_REG0_CHMODE_MASK 
+#define UART1_MODE_REG0_CHMODE_DEFVAL                                              0x00000000
+#define UART1_MODE_REG0_CHMODE_SHIFT                                               8
+#define UART1_MODE_REG0_CHMODE_MASK                                                0x00000300U
+
+/*Number of stop bits: Defines the number of stop bits to detect on receive and to generate on transmit. 00: 1 stop bit 01: 1.5
+		stop bits 10: 2 stop bits 11: reserved*/
+#undef UART1_MODE_REG0_NBSTOP_DEFVAL 
+#undef UART1_MODE_REG0_NBSTOP_SHIFT 
+#undef UART1_MODE_REG0_NBSTOP_MASK 
+#define UART1_MODE_REG0_NBSTOP_DEFVAL                                              0x00000000
+#define UART1_MODE_REG0_NBSTOP_SHIFT                                               6
+#define UART1_MODE_REG0_NBSTOP_MASK                                                0x000000C0U
+
+/*Parity type select: Defines the expected parity to check on receive and the parity to generate on transmit. 000: even parity 
+		01: odd parity 010: forced to 0 parity (space) 011: forced to 1 parity (mark) 1xx: no parity*/
+#undef UART1_MODE_REG0_PAR_DEFVAL 
+#undef UART1_MODE_REG0_PAR_SHIFT 
+#undef UART1_MODE_REG0_PAR_MASK 
+#define UART1_MODE_REG0_PAR_DEFVAL                                                 0x00000000
+#define UART1_MODE_REG0_PAR_SHIFT                                                  3
+#define UART1_MODE_REG0_PAR_MASK                                                   0x00000038U
+
+/*Character length select: Defines the number of bits in each character. 11: 6 bits 10: 7 bits 0x: 8 bits*/
+#undef UART1_MODE_REG0_CHRL_DEFVAL 
+#undef UART1_MODE_REG0_CHRL_SHIFT 
+#undef UART1_MODE_REG0_CHRL_MASK 
+#define UART1_MODE_REG0_CHRL_DEFVAL                                                0x00000000
+#define UART1_MODE_REG0_CHRL_SHIFT                                                 1
+#define UART1_MODE_REG0_CHRL_MASK                                                  0x00000006U
+
+/*Clock source select: This field defines whether a pre-scalar of 8 is applied to the baud rate generator input clock. 0: clock
+		source is uart_ref_clk 1: clock source is uart_ref_clk/8*/
+#undef UART1_MODE_REG0_CLKS_DEFVAL 
+#undef UART1_MODE_REG0_CLKS_SHIFT 
+#undef UART1_MODE_REG0_CLKS_MASK 
+#define UART1_MODE_REG0_CLKS_DEFVAL                                                0x00000000
+#define UART1_MODE_REG0_CLKS_SHIFT                                                 0
+#define UART1_MODE_REG0_CLKS_MASK                                                  0x00000001U
+
+/*TrustZone Classification for ADMA*/
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL 
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT 
+#undef LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK 
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_DEFVAL                                        
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_SHIFT                                         0
+#define LPD_SLCR_SECURE_SLCR_ADMA_TZ_MASK                                          0x000000FFU
+
+/*CSU regsiter*/
+#undef CSU_TAMPER_STATUS_TAMPER_0_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_0_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_0_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_0_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_0_SHIFT                                           0
+#define CSU_TAMPER_STATUS_TAMPER_0_MASK                                            0x00000001U
+
+/*External MIO*/
+#undef CSU_TAMPER_STATUS_TAMPER_1_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_1_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_1_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_1_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_1_SHIFT                                           1
+#define CSU_TAMPER_STATUS_TAMPER_1_MASK                                            0x00000002U
+
+/*JTAG toggle detect*/
+#undef CSU_TAMPER_STATUS_TAMPER_2_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_2_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_2_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_2_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_2_SHIFT                                           2
+#define CSU_TAMPER_STATUS_TAMPER_2_MASK                                            0x00000004U
+
+/*PL SEU error*/
+#undef CSU_TAMPER_STATUS_TAMPER_3_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_3_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_3_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_3_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_3_SHIFT                                           3
+#define CSU_TAMPER_STATUS_TAMPER_3_MASK                                            0x00000008U
+
+/*AMS over temperature alarm for LPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_4_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_4_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_4_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_4_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_4_SHIFT                                           4
+#define CSU_TAMPER_STATUS_TAMPER_4_MASK                                            0x00000010U
+
+/*AMS over temperature alarm for APU*/
+#undef CSU_TAMPER_STATUS_TAMPER_5_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_5_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_5_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_5_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_5_SHIFT                                           5
+#define CSU_TAMPER_STATUS_TAMPER_5_MASK                                            0x00000020U
+
+/*AMS voltage alarm for VCCPINT_FPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_6_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_6_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_6_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_6_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_6_SHIFT                                           6
+#define CSU_TAMPER_STATUS_TAMPER_6_MASK                                            0x00000040U
+
+/*AMS voltage alarm for VCCPINT_LPD*/
+#undef CSU_TAMPER_STATUS_TAMPER_7_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_7_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_7_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_7_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_7_SHIFT                                           7
+#define CSU_TAMPER_STATUS_TAMPER_7_MASK                                            0x00000080U
+
+/*AMS voltage alarm for VCCPAUX*/
+#undef CSU_TAMPER_STATUS_TAMPER_8_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_8_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_8_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_8_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_8_SHIFT                                           8
+#define CSU_TAMPER_STATUS_TAMPER_8_MASK                                            0x00000100U
+
+/*AMS voltage alarm for DDRPHY*/
+#undef CSU_TAMPER_STATUS_TAMPER_9_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_9_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_9_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_9_DEFVAL                                          0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_9_SHIFT                                           9
+#define CSU_TAMPER_STATUS_TAMPER_9_MASK                                            0x00000200U
+
+/*AMS voltage alarm for PSIO bank 0/1/2*/
+#undef CSU_TAMPER_STATUS_TAMPER_10_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_10_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_10_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_10_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_10_SHIFT                                          10
+#define CSU_TAMPER_STATUS_TAMPER_10_MASK                                           0x00000400U
+
+/*AMS voltage alarm for PSIO bank 3 (dedicated pins)*/
+#undef CSU_TAMPER_STATUS_TAMPER_11_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_11_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_11_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_11_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_11_SHIFT                                          11
+#define CSU_TAMPER_STATUS_TAMPER_11_MASK                                           0x00000800U
+
+/*AMS voltaage alarm for GT*/
+#undef CSU_TAMPER_STATUS_TAMPER_12_DEFVAL 
+#undef CSU_TAMPER_STATUS_TAMPER_12_SHIFT 
+#undef CSU_TAMPER_STATUS_TAMPER_12_MASK 
+#define CSU_TAMPER_STATUS_TAMPER_12_DEFVAL                                         0x00000000
+#define CSU_TAMPER_STATUS_TAMPER_12_SHIFT                                          12
+#define CSU_TAMPER_STATUS_TAMPER_12_MASK                                           0x00001000U
+
+/*Set ACE outgoing AWQOS value*/
+#undef APU_ACE_CTRL_AWQOS_DEFVAL 
+#undef APU_ACE_CTRL_AWQOS_SHIFT 
+#undef APU_ACE_CTRL_AWQOS_MASK 
+#define APU_ACE_CTRL_AWQOS_DEFVAL                                                  0x000F000F
+#define APU_ACE_CTRL_AWQOS_SHIFT                                                   16
+#define APU_ACE_CTRL_AWQOS_MASK                                                    0x000F0000U
+
+/*Set ACE outgoing ARQOS value*/
+#undef APU_ACE_CTRL_ARQOS_DEFVAL 
+#undef APU_ACE_CTRL_ARQOS_SHIFT 
+#undef APU_ACE_CTRL_ARQOS_MASK 
+#define APU_ACE_CTRL_ARQOS_DEFVAL                                                  0x000F000F
+#define APU_ACE_CTRL_ARQOS_SHIFT                                                   0
+#define APU_ACE_CTRL_ARQOS_MASK                                                    0x0000000FU
+
+/*Enables the RTC. By writing a 0 to this bit, RTC will be powered off and the only module that potentially draws current from 
+		he battery will be BBRAM. The value read through this bit does not necessarily reflect whether RTC is enabled or not. It is e
+		pected that RTC is enabled every time it is being configured. If RTC is not used in the design, FSBL will disable it by writi
+		g a 0 to this bit.*/
+#undef RTC_CONTROL_BATTERY_DISABLE_DEFVAL 
+#undef RTC_CONTROL_BATTERY_DISABLE_SHIFT 
+#undef RTC_CONTROL_BATTERY_DISABLE_MASK 
+#define RTC_CONTROL_BATTERY_DISABLE_DEFVAL                                         0x01000000
+#define RTC_CONTROL_BATTERY_DISABLE_SHIFT                                          31
+#define RTC_CONTROL_BATTERY_DISABLE_MASK                                           0x80000000U
+#undef SERDES_PLL_REF_SEL0_OFFSET 
+#define SERDES_PLL_REF_SEL0_OFFSET                                                 0XFD410000
+#undef SERDES_PLL_REF_SEL1_OFFSET 
+#define SERDES_PLL_REF_SEL1_OFFSET                                                 0XFD410004
+#undef SERDES_PLL_REF_SEL2_OFFSET 
+#define SERDES_PLL_REF_SEL2_OFFSET                                                 0XFD410008
+#undef SERDES_PLL_REF_SEL3_OFFSET 
+#define SERDES_PLL_REF_SEL3_OFFSET                                                 0XFD41000C
+#undef SERDES_L0_L0_REF_CLK_SEL_OFFSET 
+#define SERDES_L0_L0_REF_CLK_SEL_OFFSET                                            0XFD402860
+#undef SERDES_L0_L1_REF_CLK_SEL_OFFSET 
+#define SERDES_L0_L1_REF_CLK_SEL_OFFSET                                            0XFD402864
+#undef SERDES_L0_L2_REF_CLK_SEL_OFFSET 
+#define SERDES_L0_L2_REF_CLK_SEL_OFFSET                                            0XFD402868
+#undef SERDES_L0_L3_REF_CLK_SEL_OFFSET 
+#define SERDES_L0_L3_REF_CLK_SEL_OFFSET                                            0XFD40286C
+#undef SERDES_L2_TM_PLL_DIG_37_OFFSET 
+#define SERDES_L2_TM_PLL_DIG_37_OFFSET                                             0XFD40A094
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET 
+#define SERDES_L2_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40A368
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET 
+#define SERDES_L2_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40A36C
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET 
+#define SERDES_L3_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD40E368
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET 
+#define SERDES_L3_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40E36C
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET 
+#define SERDES_L1_PLL_SS_STEPS_0_LSB_OFFSET                                        0XFD406368
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET 
+#define SERDES_L1_PLL_SS_STEPS_1_MSB_OFFSET                                        0XFD40636C
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
+#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD406370
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET 
+#define SERDES_L1_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD406374
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET 
+#define SERDES_L1_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD406378
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40637C
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
+#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40A370
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET 
+#define SERDES_L2_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40A374
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET 
+#define SERDES_L2_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40A378
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40A37C
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET 
+#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_OFFSET                                    0XFD40E370
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET 
+#define SERDES_L3_PLL_SS_STEP_SIZE_1_OFFSET                                        0XFD40E374
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET 
+#define SERDES_L3_PLL_SS_STEP_SIZE_2_OFFSET                                        0XFD40E378
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET 
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_OFFSET                                    0XFD40E37C
+#undef SERDES_L2_TM_DIG_6_OFFSET 
+#define SERDES_L2_TM_DIG_6_OFFSET                                                  0XFD40906C
+#undef SERDES_L2_TX_DIG_TM_61_OFFSET 
+#define SERDES_L2_TX_DIG_TM_61_OFFSET                                              0XFD4080F4
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET 
+#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_OFFSET                                      0XFD40E360
+#undef SERDES_L3_TM_DIG_6_OFFSET 
+#define SERDES_L3_TM_DIG_6_OFFSET                                                  0XFD40D06C
+#undef SERDES_L3_TX_DIG_TM_61_OFFSET 
+#define SERDES_L3_TX_DIG_TM_61_OFFSET                                              0XFD40C0F4
+#undef SERDES_L3_TXPMA_ST_0_OFFSET 
+#define SERDES_L3_TXPMA_ST_0_OFFSET                                                0XFD40CB00
+#undef SERDES_ICM_CFG0_OFFSET 
+#define SERDES_ICM_CFG0_OFFSET                                                     0XFD410010
+#undef SERDES_ICM_CFG1_OFFSET 
+#define SERDES_ICM_CFG1_OFFSET                                                     0XFD410014
+#undef SERDES_L1_TXPMD_TM_45_OFFSET 
+#define SERDES_L1_TXPMD_TM_45_OFFSET                                               0XFD404CB4
+#undef SERDES_L1_TX_ANA_TM_118_OFFSET 
+#define SERDES_L1_TX_ANA_TM_118_OFFSET                                             0XFD4041D8
+#undef SERDES_L1_TXPMD_TM_48_OFFSET 
+#define SERDES_L1_TXPMD_TM_48_OFFSET                                               0XFD404CC0
+#undef SERDES_L1_TX_ANA_TM_18_OFFSET 
+#define SERDES_L1_TX_ANA_TM_18_OFFSET                                              0XFD404048
+
+/*PLL0 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
+#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL 
+#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT 
+#undef SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK 
+#define SERDES_PLL_REF_SEL0_PLLREFSEL0_DEFVAL                                      0x0000000D
+#define SERDES_PLL_REF_SEL0_PLLREFSEL0_SHIFT                                       0
+#define SERDES_PLL_REF_SEL0_PLLREFSEL0_MASK                                        0x0000001FU
+
+/*PLL1 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
+#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL 
+#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT 
+#undef SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK 
+#define SERDES_PLL_REF_SEL1_PLLREFSEL1_DEFVAL                                      0x00000008
+#define SERDES_PLL_REF_SEL1_PLLREFSEL1_SHIFT                                       0
+#define SERDES_PLL_REF_SEL1_PLLREFSEL1_MASK                                        0x0000001FU
+
+/*PLL2 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
+#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL 
+#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT 
+#undef SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK 
+#define SERDES_PLL_REF_SEL2_PLLREFSEL2_DEFVAL                                      0x0000000F
+#define SERDES_PLL_REF_SEL2_PLLREFSEL2_SHIFT                                       0
+#define SERDES_PLL_REF_SEL2_PLLREFSEL2_MASK                                        0x0000001FU
+
+/*PLL3 Reference Selection. 0x0 - 5MHz, 0x1 - 9.6MHz, 0x2 - 10MHz, 0x3 - 12MHz, 0x4 - 13MHz, 0x5 - 19.2MHz, 0x6 - 20MHz, 0x7 - 
+		4MHz, 0x8 - 26MHz, 0x9 - 27MHz, 0xA - 38.4MHz, 0xB - 40MHz, 0xC - 52MHz, 0xD - 100MHz, 0xE - 108MHz, 0xF - 125MHz, 0x10 - 135
+		Hz, 0x11 - 150 MHz. 0x12 to 0x1F - Reserved*/
+#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL 
+#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT 
+#undef SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK 
+#define SERDES_PLL_REF_SEL3_PLLREFSEL3_DEFVAL                                      0x0000000E
+#define SERDES_PLL_REF_SEL3_PLLREFSEL3_SHIFT                                       0
+#define SERDES_PLL_REF_SEL3_PLLREFSEL3_MASK                                        0x0000001FU
+
+/*Sel of lane 0 ref clock local mux. Set to 1 to select lane 0 slicer output. Set to 0 to select lane0 ref clock mux output.*/
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL 
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT 
+#undef SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK 
+#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
+#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_SHIFT                          7
+#define SERDES_L0_L0_REF_CLK_SEL_L0_REF_CLK_LCL_SEL_MASK                           0x00000080U
+
+/*Sel of lane 1 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane1 ref clock mux output.*/
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL 
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT 
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK 
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_SHIFT                          7
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_LCL_SEL_MASK                           0x00000080U
+
+/*Bit 3 of lane 1 ref clock mux one hot sel. Set to 1 to select lane 3 slicer output from ref clock network*/
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL 
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT 
+#undef SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK 
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_DEFVAL                           0x00000080
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_SHIFT                            3
+#define SERDES_L0_L1_REF_CLK_SEL_L1_REF_CLK_SEL_3_MASK                             0x00000008U
+
+/*Sel of lane 2 ref clock local mux. Set to 1 to select lane 1 slicer output. Set to 0 to select lane2 ref clock mux output.*/
+#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL 
+#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT 
+#undef SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK 
+#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
+#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_SHIFT                          7
+#define SERDES_L0_L2_REF_CLK_SEL_L2_REF_CLK_LCL_SEL_MASK                           0x00000080U
+
+/*Sel of lane 3 ref clock local mux. Set to 1 to select lane 3 slicer output. Set to 0 to select lane3 ref clock mux output.*/
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL 
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT 
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK 
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_DEFVAL                         0x00000080
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_SHIFT                          7
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_LCL_SEL_MASK                           0x00000080U
+
+/*Bit 1 of lane 3 ref clock mux one hot sel. Set to 1 to select lane 1 slicer output from ref clock network*/
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL 
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT 
+#undef SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK 
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_DEFVAL                           0x00000080
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_SHIFT                            1
+#define SERDES_L0_L3_REF_CLK_SEL_L3_REF_CLK_SEL_1_MASK                             0x00000002U
+
+/*Enable/Disable coarse code satureation limiting logic*/
+#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL 
+#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT 
+#undef SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK 
+#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_DEFVAL                 0x00000000
+#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_SHIFT                  4
+#define SERDES_L2_TM_PLL_DIG_37_TM_ENABLE_COARSE_SATURATION_MASK                   0x00000010U
+
+/*Spread Spectrum No of Steps [7:0]*/
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
+#undef SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
+#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
+#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
+#define SERDES_L2_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
+
+/*Spread Spectrum No of Steps [10:8]*/
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
+#undef SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
+#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
+#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
+#define SERDES_L2_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
+
+/*Spread Spectrum No of Steps [7:0]*/
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
+#undef SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
+#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
+#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
+#define SERDES_L3_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
+
+/*Spread Spectrum No of Steps [10:8]*/
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
+#undef SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
+#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
+#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
+#define SERDES_L3_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
+
+/*Spread Spectrum No of Steps [7:0]*/
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT 
+#undef SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK 
+#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_DEFVAL                  0x00000000
+#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_SHIFT                   0
+#define SERDES_L1_PLL_SS_STEPS_0_LSB_SS_NUM_OF_STEPS_0_LSB_MASK                    0x000000FFU
+
+/*Spread Spectrum No of Steps [10:8]*/
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT 
+#undef SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK 
+#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_DEFVAL                  0x00000000
+#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_SHIFT                   0
+#define SERDES_L1_PLL_SS_STEPS_1_MSB_SS_NUM_OF_STEPS_1_MSB_MASK                    0x00000007U
+
+/*Step Size for Spread Spectrum [7:0]*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
+#define SERDES_L1_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
+
+/*Step Size for Spread Spectrum [15:8]*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
+#define SERDES_L1_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [23:16]*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
+#define SERDES_L1_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [25:24]*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
+
+/*Enable/Disable test mode force on SS step size*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
+
+/*Enable/Disable test mode force on SS no of steps*/
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
+#undef SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
+#define SERDES_L1_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
+
+/*Step Size for Spread Spectrum [7:0]*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
+#define SERDES_L2_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
+
+/*Step Size for Spread Spectrum [15:8]*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
+#define SERDES_L2_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [23:16]*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
+#define SERDES_L2_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [25:24]*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
+
+/*Enable/Disable test mode force on SS step size*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
+
+/*Enable/Disable test mode force on SS no of steps*/
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
+#undef SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
+#define SERDES_L2_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
+
+/*Step Size for Spread Spectrum [7:0]*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_DEFVAL                 0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_SHIFT                  0
+#define SERDES_L3_PLL_SS_STEP_SIZE_0_LSB_SS_STEP_SIZE_0_LSB_MASK                   0x000000FFU
+
+/*Step Size for Spread Spectrum [15:8]*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_DEFVAL                         0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_SHIFT                          0
+#define SERDES_L3_PLL_SS_STEP_SIZE_1_SS_STEP_SIZE_1_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [23:16]*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_DEFVAL                         0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_SHIFT                          0
+#define SERDES_L3_PLL_SS_STEP_SIZE_2_SS_STEP_SIZE_2_MASK                           0x000000FFU
+
+/*Step Size for Spread Spectrum [25:24]*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_DEFVAL                 0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_SHIFT                  0
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_SS_STEP_SIZE_3_MSB_MASK                   0x00000003U
+
+/*Enable/Disable test mode force on SS step size*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_DEFVAL                 0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_SHIFT                  4
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_STEP_SIZE_MASK                   0x00000010U
+
+/*Enable/Disable test mode force on SS no of steps*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_DEFVAL              0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_SHIFT               5
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_FORCE_SS_NUM_OF_STEPS_MASK                0x00000020U
+
+/*Enable test mode forcing on enable Spread Spectrum*/
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT 
+#undef SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK 
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_DEFVAL                     0x00000000
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_SHIFT                      7
+#define SERDES_L3_PLL_SS_STEP_SIZE_3_MSB_TM_FORCE_EN_SS_MASK                       0x00000080U
+
+/*Bypass Descrambler*/
+#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 
+#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT 
+#undef SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK 
+#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_DEFVAL                                   0x00000000
+#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_SHIFT                                    1
+#define SERDES_L2_TM_DIG_6_BYPASS_DESCRAM_MASK                                     0x00000002U
+
+/*Enable Bypass for <1> TM_DIG_CTRL_6*/
+#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 
+#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 
+#undef SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 
+#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL                             0x00000000
+#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT                              0
+#define SERDES_L2_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK                               0x00000001U
+
+/*Bypass scrambler signal*/
+#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 
+#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 
+#undef SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK 
+#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL                                 0x00000000
+#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT                                  1
+#define SERDES_L2_TX_DIG_TM_61_BYPASS_SCRAM_MASK                                   0x00000002U
+
+/*Enable/disable scrambler bypass signal*/
+#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 
+#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 
+#undef SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 
+#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL                           0x00000000
+#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT                            0
+#define SERDES_L2_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK                             0x00000001U
+
+/*Enable test mode force on fractional mode enable*/
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL 
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT 
+#undef SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK 
+#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_DEFVAL                     0x00000000
+#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_SHIFT                      6
+#define SERDES_L3_PLL_FBDIV_FRAC_3_MSB_TM_FORCE_EN_FRAC_MASK                       0x00000040U
+
+/*Bypass 8b10b decoder*/
+#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL 
+#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT 
+#undef SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK 
+#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_DEFVAL                                   0x00000000
+#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_SHIFT                                    3
+#define SERDES_L3_TM_DIG_6_BYPASS_DECODER_MASK                                     0x00000008U
+
+/*Enable Bypass for <3> TM_DIG_CTRL_6*/
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL 
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT 
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK 
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_DEFVAL                                 0x00000000
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_SHIFT                                  2
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DEC_MASK                                   0x00000004U
+
+/*Bypass Descrambler*/
+#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL 
+#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT 
+#undef SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK 
+#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_DEFVAL                                   0x00000000
+#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_SHIFT                                    1
+#define SERDES_L3_TM_DIG_6_BYPASS_DESCRAM_MASK                                     0x00000002U
+
+/*Enable Bypass for <1> TM_DIG_CTRL_6*/
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL 
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT 
+#undef SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK 
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_DEFVAL                             0x00000000
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_SHIFT                              0
+#define SERDES_L3_TM_DIG_6_FORCE_BYPASS_DESCRAM_MASK                               0x00000001U
+
+/*Enable/disable encoder bypass signal*/
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL 
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT 
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK 
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_DEFVAL                                   0x00000000
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_SHIFT                                    3
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_ENC_MASK                                     0x00000008U
+
+/*Bypass scrambler signal*/
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL 
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT 
+#undef SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK 
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_DEFVAL                                 0x00000000
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_SHIFT                                  1
+#define SERDES_L3_TX_DIG_TM_61_BYPASS_SCRAM_MASK                                   0x00000002U
+
+/*Enable/disable scrambler bypass signal*/
+#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL 
+#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT 
+#undef SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK 
+#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_DEFVAL                           0x00000000
+#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_SHIFT                            0
+#define SERDES_L3_TX_DIG_TM_61_FORCE_BYPASS_SCRAM_MASK                             0x00000001U
+
+/*PHY Mode: 4'b000 - PCIe, 4'b001 - USB3, 4'b0010 - SATA, 4'b0100 - SGMII, 4'b0101 - DP, 4'b1000 - MPHY*/
+#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL 
+#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT 
+#undef SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK 
+#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_DEFVAL                                    0x00000001
+#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_SHIFT                                     4
+#define SERDES_L3_TXPMA_ST_0_TX_PHY_MODE_MASK                                      0x000000F0U
+
+/*Controls UPHY Lane 0 protocol configuration. 0 - PowerDown, 1 - PCIe .0, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII0, 6 - Unuse
+		, 7 - Unused*/
+#undef SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL 
+#undef SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT 
+#undef SERDES_ICM_CFG0_L0_ICM_CFG_MASK 
+#define SERDES_ICM_CFG0_L0_ICM_CFG_DEFVAL                                          0x00000000
+#define SERDES_ICM_CFG0_L0_ICM_CFG_SHIFT                                           0
+#define SERDES_ICM_CFG0_L0_ICM_CFG_MASK                                            0x00000007U
+
+/*Controls UPHY Lane 1 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata1, 3 - USB0, 4 - DP.0, 5 - SGMII1, 6 - Unused
+		 7 - Unused*/
+#undef SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL 
+#undef SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT 
+#undef SERDES_ICM_CFG0_L1_ICM_CFG_MASK 
+#define SERDES_ICM_CFG0_L1_ICM_CFG_DEFVAL                                          0x00000000
+#define SERDES_ICM_CFG0_L1_ICM_CFG_SHIFT                                           4
+#define SERDES_ICM_CFG0_L1_ICM_CFG_MASK                                            0x00000070U
+
+/*Controls UPHY Lane 2 protocol configuration. 0 - PowerDown, 1 - PCIe.1, 2 - Sata0, 3 - USB0, 4 - DP.1, 5 - SGMII2, 6 - Unused
+		 7 - Unused*/
+#undef SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL 
+#undef SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT 
+#undef SERDES_ICM_CFG1_L2_ICM_CFG_MASK 
+#define SERDES_ICM_CFG1_L2_ICM_CFG_DEFVAL                                          0x00000000
+#define SERDES_ICM_CFG1_L2_ICM_CFG_SHIFT                                           0
+#define SERDES_ICM_CFG1_L2_ICM_CFG_MASK                                            0x00000007U
+
+/*Controls UPHY Lane 3 protocol configuration. 0 - PowerDown, 1 - PCIe.3, 2 - Sata1, 3 - USB1, 4 - DP.0, 5 - SGMII3, 6 - Unused
+		 7 - Unused*/
+#undef SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL 
+#undef SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT 
+#undef SERDES_ICM_CFG1_L3_ICM_CFG_MASK 
+#define SERDES_ICM_CFG1_L3_ICM_CFG_DEFVAL                                          0x00000000
+#define SERDES_ICM_CFG1_L3_ICM_CFG_SHIFT                                           4
+#define SERDES_ICM_CFG1_L3_ICM_CFG_MASK                                            0x00000070U
+
+/*Enable/disable DP post2 path*/
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK 
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_DEFVAL                 0x00000000
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_SHIFT                  5
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_POST2_PATH_MASK                   0x00000020U
+
+/*Override enable/disable of DP post2 path*/
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK 
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_DEFVAL            0x00000000
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_SHIFT             4
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST2_PATH_MASK              0x00000010U
+
+/*Override enable/disable of DP post1 path*/
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK 
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_DEFVAL            0x00000000
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_SHIFT             2
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_POST1_PATH_MASK              0x00000004U
+
+/*Enable/disable DP main path*/
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK 
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_DEFVAL                  0x00000000
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_SHIFT                   1
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_DP_ENABLE_MAIN_PATH_MASK                    0x00000002U
+
+/*Override enable/disable of DP main path*/
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT 
+#undef SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK 
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_DEFVAL             0x00000000
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_SHIFT              0
+#define SERDES_L1_TXPMD_TM_45_DP_TM_TX_OVRD_DP_ENABLE_MAIN_PATH_MASK               0x00000001U
+
+/*Test register force for enabling/disablign TX deemphasis bits <17:0>*/
+#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL 
+#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT 
+#undef SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK 
+#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_DEFVAL                        0x00000000
+#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_SHIFT                         0
+#define SERDES_L1_TX_ANA_TM_118_FORCE_TX_DEEMPH_17_0_MASK                          0x00000001U
+
+/*Margining factor value*/
+#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL 
+#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT 
+#undef SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK 
+#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_DEFVAL                 0x00000000
+#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_SHIFT                  0
+#define SERDES_L1_TXPMD_TM_48_TM_RESULTANT_MARGINING_FACTOR_MASK                   0x0000001FU
+
+/*pipe_TX_Deemph. 0: -6dB de-emphasis, 1: -3.5dB de-emphasis, 2 : No de-emphasis, Others: reserved*/
+#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL 
+#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT 
+#undef SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK 
+#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_DEFVAL                           0x00000002
+#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_SHIFT                            0
+#define SERDES_L1_TX_ANA_TM_18_PIPE_TX_DEEMPH_7_0_MASK                             0x000000FFU
+#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
+#undef USB3_0_FPD_POWER_PRSNT_OFFSET 
+#define USB3_0_FPD_POWER_PRSNT_OFFSET                                              0XFF9D0080
+#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
+#undef CRL_APB_RST_LPD_IOU0_OFFSET 
+#define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
+#undef SIOU_SATA_MISC_CTRL_OFFSET 
+#define SIOU_SATA_MISC_CTRL_OFFSET                                                 0XFD3D0100
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef DP_DP_PHY_RESET_OFFSET 
+#define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
+#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET 
+#define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
+#undef USB3_0_XHCI_GUSB2PHYCFG_OFFSET 
+#define USB3_0_XHCI_GUSB2PHYCFG_OFFSET                                             0XFE20C200
+#undef USB3_0_XHCI_GFLADJ_OFFSET 
+#define USB3_0_XHCI_GFLADJ_OFFSET                                                  0XFE20C630
+#undef PCIE_ATTRIB_ATTR_37_OFFSET 
+#define PCIE_ATTRIB_ATTR_37_OFFSET                                                 0XFD480094
+#undef PCIE_ATTRIB_ATTR_25_OFFSET 
+#define PCIE_ATTRIB_ATTR_25_OFFSET                                                 0XFD480064
+#undef PCIE_ATTRIB_ATTR_7_OFFSET 
+#define PCIE_ATTRIB_ATTR_7_OFFSET                                                  0XFD48001C
+#undef PCIE_ATTRIB_ATTR_8_OFFSET 
+#define PCIE_ATTRIB_ATTR_8_OFFSET                                                  0XFD480020
+#undef PCIE_ATTRIB_ATTR_9_OFFSET 
+#define PCIE_ATTRIB_ATTR_9_OFFSET                                                  0XFD480024
+#undef PCIE_ATTRIB_ATTR_10_OFFSET 
+#define PCIE_ATTRIB_ATTR_10_OFFSET                                                 0XFD480028
+#undef PCIE_ATTRIB_ATTR_11_OFFSET 
+#define PCIE_ATTRIB_ATTR_11_OFFSET                                                 0XFD48002C
+#undef PCIE_ATTRIB_ATTR_12_OFFSET 
+#define PCIE_ATTRIB_ATTR_12_OFFSET                                                 0XFD480030
+#undef PCIE_ATTRIB_ATTR_13_OFFSET 
+#define PCIE_ATTRIB_ATTR_13_OFFSET                                                 0XFD480034
+#undef PCIE_ATTRIB_ATTR_14_OFFSET 
+#define PCIE_ATTRIB_ATTR_14_OFFSET                                                 0XFD480038
+#undef PCIE_ATTRIB_ATTR_15_OFFSET 
+#define PCIE_ATTRIB_ATTR_15_OFFSET                                                 0XFD48003C
+#undef PCIE_ATTRIB_ATTR_16_OFFSET 
+#define PCIE_ATTRIB_ATTR_16_OFFSET                                                 0XFD480040
+#undef PCIE_ATTRIB_ATTR_17_OFFSET 
+#define PCIE_ATTRIB_ATTR_17_OFFSET                                                 0XFD480044
+#undef PCIE_ATTRIB_ATTR_18_OFFSET 
+#define PCIE_ATTRIB_ATTR_18_OFFSET                                                 0XFD480048
+#undef PCIE_ATTRIB_ATTR_27_OFFSET 
+#define PCIE_ATTRIB_ATTR_27_OFFSET                                                 0XFD48006C
+#undef PCIE_ATTRIB_ATTR_50_OFFSET 
+#define PCIE_ATTRIB_ATTR_50_OFFSET                                                 0XFD4800C8
+#undef PCIE_ATTRIB_ATTR_105_OFFSET 
+#define PCIE_ATTRIB_ATTR_105_OFFSET                                                0XFD4801A4
+#undef PCIE_ATTRIB_ATTR_106_OFFSET 
+#define PCIE_ATTRIB_ATTR_106_OFFSET                                                0XFD4801A8
+#undef PCIE_ATTRIB_ATTR_107_OFFSET 
+#define PCIE_ATTRIB_ATTR_107_OFFSET                                                0XFD4801AC
+#undef PCIE_ATTRIB_ATTR_108_OFFSET 
+#define PCIE_ATTRIB_ATTR_108_OFFSET                                                0XFD4801B0
+#undef PCIE_ATTRIB_ATTR_109_OFFSET 
+#define PCIE_ATTRIB_ATTR_109_OFFSET                                                0XFD4801B4
+#undef PCIE_ATTRIB_ATTR_34_OFFSET 
+#define PCIE_ATTRIB_ATTR_34_OFFSET                                                 0XFD480088
+#undef PCIE_ATTRIB_ATTR_53_OFFSET 
+#define PCIE_ATTRIB_ATTR_53_OFFSET                                                 0XFD4800D4
+#undef PCIE_ATTRIB_ATTR_41_OFFSET 
+#define PCIE_ATTRIB_ATTR_41_OFFSET                                                 0XFD4800A4
+#undef PCIE_ATTRIB_ATTR_97_OFFSET 
+#define PCIE_ATTRIB_ATTR_97_OFFSET                                                 0XFD480184
+#undef PCIE_ATTRIB_ATTR_100_OFFSET 
+#define PCIE_ATTRIB_ATTR_100_OFFSET                                                0XFD480190
+#undef PCIE_ATTRIB_ATTR_101_OFFSET 
+#define PCIE_ATTRIB_ATTR_101_OFFSET                                                0XFD480194
+#undef PCIE_ATTRIB_ATTR_37_OFFSET 
+#define PCIE_ATTRIB_ATTR_37_OFFSET                                                 0XFD480094
+#undef PCIE_ATTRIB_ATTR_93_OFFSET 
+#define PCIE_ATTRIB_ATTR_93_OFFSET                                                 0XFD480174
+#undef PCIE_ATTRIB_ID_OFFSET 
+#define PCIE_ATTRIB_ID_OFFSET                                                      0XFD480200
+#undef PCIE_ATTRIB_SUBSYS_ID_OFFSET 
+#define PCIE_ATTRIB_SUBSYS_ID_OFFSET                                               0XFD480204
+#undef PCIE_ATTRIB_REV_ID_OFFSET 
+#define PCIE_ATTRIB_REV_ID_OFFSET                                                  0XFD480208
+#undef PCIE_ATTRIB_ATTR_24_OFFSET 
+#define PCIE_ATTRIB_ATTR_24_OFFSET                                                 0XFD480060
+#undef PCIE_ATTRIB_ATTR_25_OFFSET 
+#define PCIE_ATTRIB_ATTR_25_OFFSET                                                 0XFD480064
+#undef PCIE_ATTRIB_ATTR_4_OFFSET 
+#define PCIE_ATTRIB_ATTR_4_OFFSET                                                  0XFD480010
+#undef PCIE_ATTRIB_ATTR_89_OFFSET 
+#define PCIE_ATTRIB_ATTR_89_OFFSET                                                 0XFD480164
+#undef PCIE_ATTRIB_ATTR_79_OFFSET 
+#define PCIE_ATTRIB_ATTR_79_OFFSET                                                 0XFD48013C
+#undef PCIE_ATTRIB_ATTR_43_OFFSET 
+#define PCIE_ATTRIB_ATTR_43_OFFSET                                                 0XFD4800AC
+
+/*USB 0 reset for control registers*/
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
+
+/*This bit is used to choose between PIPE power present and 1'b1*/
+#undef USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL 
+#undef USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT 
+#undef USB3_0_FPD_POWER_PRSNT_OPTION_MASK 
+#define USB3_0_FPD_POWER_PRSNT_OPTION_DEFVAL                                       
+#define USB3_0_FPD_POWER_PRSNT_OPTION_SHIFT                                        0
+#define USB3_0_FPD_POWER_PRSNT_OPTION_MASK                                         0x00000001U
+
+/*USB 0 sleep circuit reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
+
+/*USB 0 reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
+
+/*GEM 3 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
+
+/*Sata PM clock control select*/
+#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL 
+#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT 
+#undef SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK 
+#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_DEFVAL                                 
+#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_SHIFT                                  0
+#define SIOU_SATA_MISC_CTRL_SATA_PM_CLK_SEL_MASK                                   0x00000003U
+
+/*Sata block level reset*/
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
+
+/*PCIE config reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL                                  0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT                                   19
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                                    0x00080000U
+
+/*PCIE control block level reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL                                 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT                                  17
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK                                   0x00020000U
+
+/*PCIE bridge block level reset (AXI interface)*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL                               0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT                                18
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK                                 0x00040000U
+
+/*Display Port block level reset (includes DPDMA)*/
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
+#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
+
+/*Set to '1' to hold the GT in reset. Clear to release.*/
+#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL 
+#undef DP_DP_PHY_RESET_GT_RESET_SHIFT 
+#undef DP_DP_PHY_RESET_GT_RESET_MASK 
+#define DP_DP_PHY_RESET_GT_RESET_DEFVAL                                            0x00010003
+#define DP_DP_PHY_RESET_GT_RESET_SHIFT                                             1
+#define DP_DP_PHY_RESET_GT_RESET_MASK                                              0x00000002U
+
+/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 
+		ane0 Bits [3:2] - lane 1*/
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL                                   0x00000000
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                                    0
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                                     0x0000000FU
+
+/*USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to 
+		he Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the minimum S
+		C bus frequency of 60 MHz. USB turnaround time is a critical certification criteria when using long cables and five hub level
+		. The required values for this field: - 4'h5: When the MAC interface is 16-bit UTMI+. - 4'h9: When the MAC interface is 8-bit
+		UTMI+/ULPI. If SoC bus clock is less than 60 MHz, and USB turnaround time is not critical, this field can be set to a larger 
+		alue. Note: This field is valid only in device mode.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_DEFVAL                                   0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_SHIFT                                    10
+#define USB3_0_XHCI_GUSB2PHYCFG_USBTRDTIM_MASK                                     0x00003C00U
+
+/*Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertio
+		 of the TxValid signal during a HS Chirp. When this bit is set to 1, a delay (of approximately 2.5 us) is introduced from the
+		time when the Transceiver Select is set to 2'b00 (HS) to the time the TxValid is driven to 0 for sending the chirp-K. This de
+		ay is required for some UTMI/ULPI PHYs. Note: - If you enable the hibernation feature when the device core comes out of power
+		off, you must re-initialize this bit with the appropriate value because the core does not save and restore this bit value dur
+		ng hibernation. - This bit is valid only in device mode.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_DEFVAL                                     0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_SHIFT                                      9
+#define USB3_0_XHCI_GUSB2PHYCFG_XCVRDLY_MASK                                       0x00000200U
+
+/*Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspen
+		_n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is not transferre
+		 to the external PHY. - 1'b1: utmi_sleep_n and utmi_l1_suspend_n assertion from the core is transferred to the external PHY. 
+		ote: This bit must be set high for Port0 if PHY is used. Note: In Device mode - Before issuing any device endpoint command wh
+		n operating in 2.0 speeds, disable this bit and enable it after the command completes. Without disabling this bit, if a comma
+		d is issued when the device is in L1 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get complet
+		d.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_DEFVAL                                    0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_SHIFT                                     8
+#define USB3_0_XHCI_GUSB2PHYCFG_ENBLSLPM_MASK                                      0x00000100U
+
+/*USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed P
+		Y or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0, with Write Only access. - 
+		'b1: USB 1.1 full-speed serial transceiver. This bit is always 1, with Write Only access. If both interface types are selecte
+		 in coreConsultant (that is, parameters' values are not zero), the application uses this bit to select the active interface i
+		 active, with Read-Write bit access. Note: USB 1.1 full-serial transceiver is not supported. This bit always reads as 1'b0.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_DEFVAL                                      0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_SHIFT                                       7
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYSEL_MASK                                        0x00000080U
+
+/*Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set, USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD/OTG co
+		figurations, it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1, then the app
+		ication must clear this bit after power-on reset. Application needs to set it to 1 after the core initialization completes. F
+		r all other configurations, this bit can be set to 1 during core configuration. Note: - In host mode, on reset, this bit is s
+		t to 1. Software can override this bit after reset. - In device mode, before issuing any device endpoint command when operati
+		g in 2.0 speeds, disable this bit and enable it after the command completes. If you issue a command without disabling this bi
+		 when the device is in L2 state and if mac2_clk (utmi_clk/ulpi_clk) is gated off, the command will not get completed.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_DEFVAL                                0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_SHIFT                                 6
+#define USB3_0_XHCI_GUSB2PHYCFG_SUSPENDUSB20_MASK                                  0x00000040U
+
+/*Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1
+		full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0 with 
+		ead Only access. - 1'b1: 3-pin bidirectional full-speed serial interface. This bit is set to 0 with Read Only access. Note: U
+		B 1.1 full-speed serial interface is not supported. This bit always reads as 1'b0.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_DEFVAL                                      0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_SHIFT                                       5
+#define USB3_0_XHCI_GUSB2PHYCFG_FSINTF_MASK                                        0x00000020U
+
+/*ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interfa
+		e - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s) in coreCons
+		ltant configuration (DWC_USB3_HSPHY_INTERFACE = 3). Otherwise, this bit is read-only and the value depends on the interface s
+		lected through DWC_USB3_HSPHY_INTERFACE.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_DEFVAL                               0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_SHIFT                                4
+#define USB3_0_XHCI_GUSB2PHYCFG_ULPI_UTMI_SEL_MASK                                 0x00000010U
+
+/*PHY Interface (PHYIf) If UTMI+ is selected, the application uses this bit to configure the core to support a UTMI+ PHY with a
+		 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have the same 
+		lock frequency as Port0 clock frequency (utmi_clk[0]). - The UTMI 8-bit and 16-bit modes cannot be used together for differen
+		 ports at the same time (that is, all the ports must be in 8-bit mode, or all of them must be in 16-bit mode, at a time). - I
+		 any of the USB 2.0 ports is selected as ULPI port for operation, then all the USB 2.0 ports must be operating at 60 MHz.*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_DEFVAL                                       0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_SHIFT                                        3
+#define USB3_0_XHCI_GUSB2PHYCFG_PHYIF_MASK                                         0x00000008U
+
+/*HS/FS Timeout Calibration (TOutCal) The number of PHY clocks, as indicated by the application in this field, is multiplied by
+		a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the core to account for 
+		dditional delays introduced by the PHY. This may be required, since the delay introduced by the PHY in generating the linesta
+		e condition may vary among PHYs. The USB standard timeout value for high-speed operation is 736 to 816 (inclusive) bit times.
+		The USB standard timeout value for full-speed operation is 16 to 18 (inclusive) bit times. The application must program this 
+		ield based on the speed of connection. The number of bit times added per PHY clock are: High-speed operation: - One 30-MHz PH
+		 clock = 16 bit times - One 60-MHz PHY clock = 8 bit times Full-speed operation: - One 30-MHz PHY clock = 0.4 bit times - One
+		60-MHz PHY clock = 0.2 bit times - One 48-MHz PHY clock = 0.25 bit times*/
+#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL 
+#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT 
+#undef USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK 
+#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_DEFVAL                                     0x00000000
+#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_SHIFT                                      0
+#define USB3_0_XHCI_GUSB2PHYCFG_TOUTCAL_MASK                                       0x00000007U
+
+/*This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register 
+		alue is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when GLADJ.GFLADJ_REFCLK_LP
+		_SEL is set to '1'. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL is set to '1' or GCTL.SOF
+		TPSYNC is set to '1'. The value is derived as follows: FLADJ_REF_CLK_FLADJ=((125000/ref_clk_period_integer)-(125000/ref_clk_p
+		riod)) * ref_clk_period where - the ref_clk_period_integer is the integer value of the ref_clk period got by truncating the d
+		cimal (fractional) value that is programmed in the GUCTL.REF_CLK_PERIOD field. - the ref_clk_period is the ref_clk period inc
+		uding the fractional value. Examples: If the ref_clk is 24 MHz then - GUCTL.REF_CLK_PERIOD = 41 - GFLADJ.GLADJ_REFCLK_FLADJ =
+		((125000/41)-(125000/41.6666))*41.6666 = 2032 (ignoring the fractional value) If the ref_clk is 48 MHz then - GUCTL.REF_CLK_P
+		RIOD = 20 - GFLADJ.GLADJ_REFCLK_FLADJ = ((125000/20)-(125000/20.8333))*20.8333 = 5208 (ignoring the fractional value)*/
+#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL 
+#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT 
+#undef USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK 
+#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_DEFVAL                              0x00000000
+#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_SHIFT                               8
+#define USB3_0_XHCI_GFLADJ_GFLADJ_REFCLK_FLADJ_MASK                                0x003FFF00U
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
+#undef SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
+#define SERDES_L0_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
+#define SERDES_L0_PLL_STATUS_READ_1_OFFSET                                         0XFD4023E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
+#undef SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
+#define SERDES_L1_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
+#define SERDES_L1_PLL_STATUS_READ_1_OFFSET                                         0XFD4063E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
+#undef SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
+#define SERDES_L2_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
+#define SERDES_L2_PLL_STATUS_READ_1_OFFSET                                         0XFD40A3E4
+
+/*Status Read value of PLL Lock*/
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL 
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT 
+#undef SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK 
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_DEFVAL                    0x00000001
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_SHIFT                     4
+#define SERDES_L3_PLL_STATUS_READ_1_PLL_LOCK_STATUS_READ_MASK                      0x00000010U
+#define SERDES_L3_PLL_STATUS_READ_1_OFFSET                                         0XFD40E3E4
+
+/*Sets the ASPM Optionality Compliance bit, to comply with the 2.1 ASPM Optionality ECN. Transferred to the Link Capabilities r
+		gister.; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT 
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK 
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_DEFVAL                  0x000009FF
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_SHIFT                   14
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_ASPM_OPTIONALITY_MASK                    0x00004000U
+
+/*If TRUE Completion Timeout Disable is supported. This is required to be TRUE for Endpoint and either setting allowed for Root
+		ports. Drives Device Capability 2 [4]; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK 
+#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_DEFVAL              0x00000905
+#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_SHIFT               9
+#define PCIE_ATTRIB_ATTR_25_ATTR_CPL_TIMEOUT_DISABLE_SUPPORTED_MASK                0x00000200U
+
+/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
+		ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
+		Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
+		erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 
+		set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
+		re size in bytes.; EP=0x0004; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT 
+#undef PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK 
+#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_DEFVAL                                        
+#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_SHIFT                                         0
+#define PCIE_ATTRIB_ATTR_7_ATTR_BAR0_MASK                                          0x0000FFFFU
+
+/*Specifies mask/settings for Base Address Register (BAR) 0. If BAR is not to be implemented, set to 32'h00000000. Bits are def
+		ned as follows: Memory Space BAR [0] = Mem Space Indicator (set to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] =
+		Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory a
+		erture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR1,BAR0\'7d to 1. IO Space BAR 0] = IO Space Indicator 
+		set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o apert
+		re size in bytes.; EP=0xFFF0; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT 
+#undef PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK 
+#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_DEFVAL                                        
+#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_SHIFT                                         0
+#define PCIE_ATTRIB_ATTR_8_ATTR_BAR0_MASK                                          0x0000FFFFU
+
+/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 
+		AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
+		 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 
+		o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
+		32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 
+		'7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
+		ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT 
+#undef PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK 
+#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_DEFVAL                                        
+#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_SHIFT                                         0
+#define PCIE_ATTRIB_ATTR_9_ATTR_BAR1_MASK                                          0x0000FFFFU
+
+/*Specifies mask/settings for Base Address Register (BAR) 1 if BAR0 is a 32-bit BAR, or the upper bits of \'7bBAR1,BAR0\'7d if 
+		AR0 is a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR0 description if this functions as the uppe
+		 bits of a 64-bit BAR. Bits are defined as follows: Memory Space BAR (not upper bits of BAR0) [0] = Mem Space Indicator (set 
+		o 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if
+		32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of 
+		'7bBAR2,BAR1\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable b
+		ts of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT 
+#undef PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK 
+#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_10_ATTR_BAR1_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
+		AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFFF*/
+#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT 
+#undef PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK 
+#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_11_ATTR_BAR2_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 2 if BAR1 is a 32-bit BAR, or the upper bits of \'7b
+		AR2,BAR1\'7d if BAR1 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR1 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to 00FF_FFFF. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR1) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR3,BAR2\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0x00FF*/
+#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT 
+#undef PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK 
+#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_12_ATTR_BAR2_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
+		AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
+		 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
+		t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
+		t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
+		if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 
+		f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
+		 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT 
+#undef PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK 
+#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_13_ATTR_BAR3_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 3 if BAR2 is a 32-bit BAR, or the upper bits of \'7b
+		AR3,BAR2\'7d if BAR2 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR2 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: FFFF_0000 = IO Limit/Bas
+		 Registers not implemented FFFF_F0F0 = IO Limit/Base Registers use 16-bit decode FFFF_F1F1 = IO Limit/Base Registers use 32-b
+		t decode For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR2) [0] = Mem Space Indicator (s
+		t to 0) [2:1] = Type field (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR;
+		if 32-bit BAR, set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits 
+		f \'7bBAR4,BAR3\'7d to 1. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writabl
+		 bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFFF*/
+#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT 
+#undef PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK 
+#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_14_ATTR_BAR3_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
+		AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0x0004; RP=0xFFF0*/
+#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT 
+#undef PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK 
+#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_15_ATTR_BAR4_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 4 if BAR3 is a 32-bit BAR, or the upper bits of \'7b
+		AR4,BAR3\'7d if BAR3 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR3 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root: This must be set to FFF0_FFF0. For an endpoin
+		, bits are defined as follows: Memory Space BAR (not upper bits of BAR3) [0] = Mem Space Indicator (set to 0) [2:1] = Type fi
+		ld (10 for 64-bit, 00 for 32-bit) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; if 32-bit BAR, set uppe
+		most 31:n bits to 1, where 2^n=memory aperture size in bytes. If 64-bit BAR, set uppermost 63:n bits of \'7bBAR5,BAR4\'7d to 
+		. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set upper
+		ost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFF0; RP=0xFFF0*/
+#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT 
+#undef PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK 
+#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_16_ATTR_BAR4_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
+		AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
+		Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 
+		refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
+		R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 
+		refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 
+		ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
+		permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/
+#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT 
+#undef PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK 
+#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_17_ATTR_BAR5_MASK                                         0x0000FFFFU
+
+/*For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of \'7b
+		AR5,BAR4\'7d if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32'h00000000. See BAR4 descri
+		tion if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable
+		Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit 
+		refetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of B
+		R4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = 
+		refetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in 
+		ytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set u
+		permost 31:n bits to 1, where 2^n=i/o aperture size in bytes.; EP=0xFFFF; RP=0xFFF1*/
+#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT 
+#undef PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK 
+#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_DEFVAL                                       
+#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_SHIFT                                        0
+#define PCIE_ATTRIB_ATTR_18_ATTR_BAR5_MASK                                         0x0000FFFFU
+
+/*Specifies maximum payload supported. Valid settings are: 0- 128 bytes, 1- 256 bytes, 2- 512 bytes, 3- 1024 bytes. Transferred
+		to the Device Capabilities register. The values: 4-2048 bytes, 5- 4096 bytes are not supported; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT 
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK 
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_DEFVAL              0x00002138
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_SHIFT               8
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_MAX_PAYLOAD_SUPPORTED_MASK                0x00000700U
+
+/*Endpoint L1 Acceptable Latency. Records the latency that the endpoint can withstand on transitions from L1 state to L0 (if L1
+		state supported). Valid settings are: 0h less than 1us, 1h 1 to 2us, 2h 2 to 4us, 3h 4 to 8us, 4h 8 to 16us, 5h 16 to 32us, 6
+		 32 to 64us, 7h more than 64us. For Endpoints only. Must be 0h for other devices.; EP=0x0007; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT 
+#undef PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK 
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_DEFVAL                0x00002138
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_SHIFT                 3
+#define PCIE_ATTRIB_ATTR_27_ATTR_DEV_CAP_ENDPOINT_L1_LATENCY_MASK                  0x00000038U
+
+/*Identifies the type of device/port as follows: 0000b PCI Express Endpoint device, 0001b Legacy PCI Express Endpoint device, 0
+		00b Root Port of PCI Express Root Complex, 0101b Upstream Port of PCI Express Switch, 0110b Downstream Port of PCI Express Sw
+		tch, 0111b PCIE Express to PCI/PCI-X Bridge, 1000b PCI/PCI-X to PCI Express Bridge. Transferred to PCI Express Capabilities r
+		gister. Must be consistent with IS_SWITCH and UPSTREAM_FACING settings.; EP=0x0000; RP=0x0004*/
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK 
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_DEFVAL                  0x00009C02
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_SHIFT                   4
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_DEVICE_PORT_TYPE_MASK                    0x000000F0U
+
+/*PCIe Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capab
+		lity.; EP=0x009C; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT 
+#undef PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK 
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_DEFVAL                           0x00009C02
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_SHIFT                            8
+#define PCIE_ATTRIB_ATTR_50_ATTR_PCIE_CAP_NEXTPTR_MASK                             0x0000FF00U
+
+/*Number of credits that should be advertised for Completion data received on Virtual Channel 0. The bytes advertised must be l
+		ss than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0172; RP=0x00CD*/
+#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT 
+#undef PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK 
+#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_DEFVAL                      
+#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_SHIFT                       0
+#define PCIE_ATTRIB_ATTR_105_ATTR_VC0_TOTAL_CREDITS_CD_MASK                        0x000007FFU
+
+/*Number of credits that should be advertised for Completion headers received on Virtual Channel 0. The sum of the posted, non 
+		osted, and completion header credits must be <= 80; EP=0x0048; RP=0x0024*/
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT 
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK 
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_DEFVAL                      0x00000248
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_SHIFT                       0
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_CH_MASK                        0x0000007FU
+
+/*Number of credits that should be advertised for Non-Posted headers received on Virtual Channel 0. The number of non posted da
+		a credits advertised by the block is equal to the number of non posted header credits. The sum of the posted, non posted, and
+		completion header credits must be <= 80; EP=0x0004; RP=0x000C*/
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT 
+#undef PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK 
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_DEFVAL                     0x00000248
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_SHIFT                      7
+#define PCIE_ATTRIB_ATTR_106_ATTR_VC0_TOTAL_CREDITS_NPH_MASK                       0x00003F80U
+
+/*Number of credits that should be advertised for Non-Posted data received on Virtual Channel 0. The number of non posted data 
+		redits advertised by the block is equal to two times the number of non posted header credits if atomic operations are support
+		d or is equal to the number of non posted header credits if atomic operations are not supported. The bytes advertised must be
+		less than or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0008; RP=0x0018*/
+#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT 
+#undef PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK 
+#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_DEFVAL                     
+#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_SHIFT                      0
+#define PCIE_ATTRIB_ATTR_107_ATTR_VC0_TOTAL_CREDITS_NPD_MASK                       0x000007FFU
+
+/*Number of credits that should be advertised for Posted data received on Virtual Channel 0. The bytes advertised must be less 
+		han or equal to the bram bytes available. See VC0_RX_RAM_LIMIT; EP=0x0020; RP=0x00B5*/
+#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT 
+#undef PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK 
+#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_DEFVAL                      
+#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_SHIFT                       0
+#define PCIE_ATTRIB_ATTR_108_ATTR_VC0_TOTAL_CREDITS_PD_MASK                        0x000007FFU
+
+/*Not currently in use. Invert ECRC generated by block when trn_tecrc_gen_n and trn_terrfwd_n are asserted.; EP=0x0000; RP=0x00
+		0*/
+#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK 
+#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_DEFVAL                              0x00007E04
+#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_SHIFT                               15
+#define PCIE_ATTRIB_ATTR_109_ATTR_TECRC_EP_INV_MASK                                0x00008000U
+
+/*Enables td bit clear and ECRC trim on received TLP's FALSE == don't trim TRUE == trim.; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK 
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_DEFVAL                            0x00007E04
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_SHIFT                             14
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_TRIM_MASK                              0x00004000U
+
+/*Enables ECRC check on received TLP's 0 == don't check 1 == always check 3 == check if enabled by ECRC check enable bit of AER
+		cap structure; EP=0x0003; RP=0x0003*/
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK 
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_DEFVAL                                 0x00007E04
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_SHIFT                                  12
+#define PCIE_ATTRIB_ATTR_109_ATTR_RECRC_CHK_MASK                                   0x00003000U
+
+/*Index of last packet buffer used by TX TLM (i.e. number of buffers - 1). Calculated from max payload size supported and the n
+		mber of brams configured for transmit; EP=0x001C; RP=0x001C*/
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK 
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_DEFVAL                         0x00007E04
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_SHIFT                          7
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TX_LASTPACKET_MASK                           0x00000F80U
+
+/*Number of credits that should be advertised for Posted headers received on Virtual Channel 0. The sum of the posted, non post
+		d, and completion header credits must be <= 80; EP=0x0004; RP=0x0020*/
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT 
+#undef PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK 
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_DEFVAL                      0x00007E04
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_SHIFT                       0
+#define PCIE_ATTRIB_ATTR_109_ATTR_VC0_TOTAL_CREDITS_PH_MASK                        0x0000007FU
+
+/*Specifies values to be transferred to Header Type register. Bit 7 should be set to '0' indicating single-function device. Bit
+		0 identifies header as Type 0 or Type 1, with '0' indicating a Type 0 header.; EP=0x0000; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK 
+#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_DEFVAL                                0x00000100
+#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_SHIFT                                 0
+#define PCIE_ATTRIB_ATTR_34_ATTR_HEADER_TYPE_MASK                                  0x000000FFU
+
+/*PM Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabil
+		ty.; EP=0x0048; RP=0x0060*/
+#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT 
+#undef PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK 
+#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_DEFVAL                             0x00003D48
+#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_SHIFT                              0
+#define PCIE_ATTRIB_ATTR_53_ATTR_PM_CAP_NEXTPTR_MASK                               0x000000FFU
+
+/*MSI Per-Vector Masking Capable. The value is transferred to the MSI Control Register[8]. When set, adds Mask and Pending Dwor
+		 to Cap structure; EP=0x0000; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK 
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_DEFVAL         0x00000160
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_SHIFT          9
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_PER_VECTOR_MASKING_CAPABLE_MASK           0x00000200U
+
+/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 
+		he management port.; EP=0x0001; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL                                 0x00000160
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT                                  8
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK                                   0x00000100U
+
+/*MSI Capability's Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capabi
+		ity.; EP=0x0060; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK 
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_DEFVAL                            0x00000160
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_SHIFT                             0
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_NEXTPTR_MASK                              0x000000FFU
+
+/*Indicates that the MSI structures exists. If this is FALSE, then the MSI structure cannot be accessed via either the link or 
+		he management port.; EP=0x0001; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT 
+#undef PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK 
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_DEFVAL                                 0x00000160
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_SHIFT                                  8
+#define PCIE_ATTRIB_ATTR_41_ATTR_MSI_CAP_ON_MASK                                   0x00000100U
+
+/*Maximum Link Width. Valid settings are: 000001b x1, 000010b x2, 000100b x4, 001000b x8.; EP=0x0004; RP=0x0004*/
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT 
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK 
+#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_DEFVAL                    0x00000104
+#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_SHIFT                     0
+#define PCIE_ATTRIB_ATTR_97_ATTR_LINK_CAP_MAX_LINK_WIDTH_MASK                      0x0000003FU
+
+/*Used by LTSSM to set Maximum Link Width. Valid settings are: 000001b [x1], 000010b [x2], 000100b [x4], 001000b [x8].; EP=0x00
+		4; RP=0x0004*/
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT 
+#undef PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK 
+#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_DEFVAL                       0x00000104
+#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_SHIFT                        6
+#define PCIE_ATTRIB_ATTR_97_ATTR_LTSSM_MAX_LINK_WIDTH_MASK                         0x00000FC0U
+
+/*TRUE specifies upstream-facing port. FALSE specifies downstream-facing port.; EP=0x0001; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT 
+#undef PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK 
+#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_DEFVAL                           0x000000F0
+#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_SHIFT                            6
+#define PCIE_ATTRIB_ATTR_100_ATTR_UPSTREAM_FACING_MASK                             0x00000040U
+
+/*Enable the routing of message TLPs to the user through the TRN RX interface. A bit value of 1 enables routing of the message 
+		LP to the user. Messages are always decoded by the message decoder. Bit 0 - ERR COR, Bit 1 - ERR NONFATAL, Bit 2 - ERR FATAL,
+		Bit 3 - INTA Bit 4 - INTB, Bit 5 - INTC, Bit 6 - INTD, Bit 7 PM_PME, Bit 8 - PME_TO_ACK, Bit 9 - unlock, Bit 10 PME_Turn_Off;
+		EP=0x0000; RP=0x07FF*/
+#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK 
+#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_DEFVAL                          0x00000000
+#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_SHIFT                           5
+#define PCIE_ATTRIB_ATTR_101_ATTR_ENABLE_MSG_ROUTE_MASK                            0x0000FFE0U
+
+/*Disable BAR filtering. Does not change the behavior of the bar hit outputs; EP=0x0000; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT 
+#undef PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK 
+#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_DEFVAL                     0x00000000
+#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_SHIFT                      1
+#define PCIE_ATTRIB_ATTR_101_ATTR_DISABLE_BAR_FILTERING_MASK                       0x00000002U
+
+/*Link Bandwidth notification capability. Indicates support for the link bandwidth notification status and interrupt mechanism.
+		Required for Root.; EP=0x0000; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT 
+#undef PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK 
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_DEFVAL   0x000009FF
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_SHIFT    9
+#define PCIE_ATTRIB_ATTR_37_ATTR_LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP_MASK     0x00000200U
+
+/*Enables the Replay Timer to use the user-defined LL_REPLAY_TIMEOUT value (or combined with the built-in value, depending on L
+		_REPLAY_TIMEOUT_FUNC). If FALSE, the built-in value is used.; EP=0x0000; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT 
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK 
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_DEFVAL                       0x00000000
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_SHIFT                        15
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_EN_MASK                         0x00008000U
+
+/*Sets a user-defined timeout for the Replay Timer to force cause the retransmission of unacknowledged TLPs; refer to LL_REPLAY
+		TIMEOUT_EN and LL_REPLAY_TIMEOUT_FUNC to see how this value is used. The unit for this attribute is in symbol times, which is
+		4ns at GEN1 speeds and 2ns at GEN2.; EP=0x0000; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT 
+#undef PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK 
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_DEFVAL                          0x00000000
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_SHIFT                           0
+#define PCIE_ATTRIB_ATTR_93_ATTR_LL_REPLAY_TIMEOUT_MASK                            0x00007FFFU
+
+/*Device ID for the the PCIe Cap Structure Device ID field*/
+#undef PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL 
+#undef PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT 
+#undef PCIE_ATTRIB_ID_CFG_DEV_ID_MASK 
+#define PCIE_ATTRIB_ID_CFG_DEV_ID_DEFVAL                                           0x10EE7024
+#define PCIE_ATTRIB_ID_CFG_DEV_ID_SHIFT                                            0
+#define PCIE_ATTRIB_ID_CFG_DEV_ID_MASK                                             0x0000FFFFU
+
+/*Vendor ID for the PCIe Cap Structure Vendor ID field*/
+#undef PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL 
+#undef PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT 
+#undef PCIE_ATTRIB_ID_CFG_VEND_ID_MASK 
+#define PCIE_ATTRIB_ID_CFG_VEND_ID_DEFVAL                                          0x10EE7024
+#define PCIE_ATTRIB_ID_CFG_VEND_ID_SHIFT                                           16
+#define PCIE_ATTRIB_ID_CFG_VEND_ID_MASK                                            0xFFFF0000U
+
+/*Subsystem ID for the the PCIe Cap Structure Subsystem ID field*/
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL 
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT 
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK 
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_DEFVAL                                 0x10EE0007
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_SHIFT                                  0
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_ID_MASK                                   0x0000FFFFU
+
+/*Subsystem Vendor ID for the PCIe Cap Structure Subsystem Vendor ID field*/
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL 
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT 
+#undef PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK 
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_DEFVAL                            0x10EE0007
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_SHIFT                             16
+#define PCIE_ATTRIB_SUBSYS_ID_CFG_SUBSYS_VEND_ID_MASK                              0xFFFF0000U
+
+/*Revision ID for the the PCIe Cap Structure*/
+#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL 
+#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT 
+#undef PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK 
+#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_DEFVAL                                       
+#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_SHIFT                                        0
+#define PCIE_ATTRIB_REV_ID_CFG_REV_ID_MASK                                         0x000000FFU
+
+/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
+		8000; RP=0x8000*/
+#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK 
+#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_DEFVAL                                 
+#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_SHIFT                                  0
+#define PCIE_ATTRIB_ATTR_24_ATTR_CLASS_CODE_MASK                                   0x0000FFFFU
+
+/*Code identifying basic function, subclass and applicable programming interface. Transferred to the Class Code register.; EP=0
+		0005; RP=0x0006*/
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK 
+#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_DEFVAL                                 0x00000905
+#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_SHIFT                                  0
+#define PCIE_ATTRIB_ATTR_25_ATTR_CLASS_CODE_MASK                                   0x000000FFU
+
+/*INTX Interrupt Generation Capable. If FALSE, this will cause Command[10] to be hardwired to 0.; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT 
+#undef PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK 
+#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_DEFVAL                       0x00000905
+#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_SHIFT                        8
+#define PCIE_ATTRIB_ATTR_25_ATTR_CMD_INTX_IMPLEMENTED_MASK                         0x00000100U
+
+/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 
+		he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
+		ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL                                  0x00001000
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT                                   12
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK                                    0x00001000U
+
+/*Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or 
+		he management port, and AER will be considered to not be present for error management tasks (such as what types of error mess
+		ges are sent if an error is detected).; EP=0x0001; RP=0x0001*/
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT 
+#undef PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK 
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_DEFVAL                                  0x00001000
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_SHIFT                                   12
+#define PCIE_ATTRIB_ATTR_4_ATTR_AER_CAP_ON_MASK                                    0x00001000U
+
+/*VSEC's Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.; EP
+		0x0140; RP=0x0140*/
+#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT 
+#undef PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK 
+#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_DEFVAL                           0x00002281
+#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_SHIFT                            1
+#define PCIE_ATTRIB_ATTR_89_ATTR_VSEC_CAP_NEXTPTR_MASK                             0x00001FFEU
+
+/*CRS SW Visibility. Indicates RC can return CRS to SW. Transferred to the Root Capabilities register.; EP=0x0000; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT 
+#undef PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK 
+#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_DEFVAL                 0x00000000
+#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_SHIFT                  5
+#define PCIE_ATTRIB_ATTR_79_ATTR_ROOT_CAP_CRS_SW_VISIBILITY_MASK                   0x00000020U
+
+/*Indicates that the MSIX structures exists. If this is FALSE, then the MSIX structure cannot be accessed via either the link o
+		 the management port.; EP=0x0001; RP=0x0000*/
+#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL 
+#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT 
+#undef PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK 
+#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_DEFVAL                                0x00000100
+#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_SHIFT                                 8
+#define PCIE_ATTRIB_ATTR_43_ATTR_MSIX_CAP_ON_MASK                                  0x00000100U
+#undef CRL_APB_RST_LPD_TOP_OFFSET 
+#define CRL_APB_RST_LPD_TOP_OFFSET                                                 0XFF5E023C
+#undef CRL_APB_RST_LPD_IOU0_OFFSET 
+#define CRL_APB_RST_LPD_IOU0_OFFSET                                                0XFF5E0230
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+#undef DP_DP_TX_PHY_POWER_DOWN_OFFSET 
+#define DP_DP_TX_PHY_POWER_DOWN_OFFSET                                             0XFD4A0238
+#undef DP_DP_PHY_RESET_OFFSET 
+#define DP_DP_PHY_RESET_OFFSET                                                     0XFD4A0200
+#undef CRF_APB_RST_FPD_TOP_OFFSET 
+#define CRF_APB_RST_FPD_TOP_OFFSET                                                 0XFD1A0100
+
+/*USB 0 reset for control registers*/
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_SHIFT                                   10
+#define CRL_APB_RST_LPD_TOP_USB0_APB_RESET_MASK                                    0x00000400U
+
+/*USB 0 sleep circuit reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_DEFVAL                                 0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_SHIFT                                  8
+#define CRL_APB_RST_LPD_TOP_USB0_HIBERRESET_MASK                                   0x00000100U
+
+/*USB 0 reset*/
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT 
+#undef CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK 
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_DEFVAL                                  0x00188FDF
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_SHIFT                                   6
+#define CRL_APB_RST_LPD_TOP_USB0_CORERESET_MASK                                    0x00000040U
+
+/*GEM 3 reset*/
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT 
+#undef CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK 
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_DEFVAL                                     0x0000000F
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_SHIFT                                      3
+#define CRL_APB_RST_LPD_IOU0_GEM3_RESET_MASK                                       0x00000008U
+
+/*Sata block level reset*/
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_SATA_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_DEFVAL                                      0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_SHIFT                                       1
+#define CRF_APB_RST_FPD_TOP_SATA_RESET_MASK                                        0x00000002U
+
+/*PCIE config reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_DEFVAL                                  0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_SHIFT                                   19
+#define CRF_APB_RST_FPD_TOP_PCIE_CFG_RESET_MASK                                    0x00080000U
+
+/*PCIE control block level reset*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_DEFVAL                                 0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_SHIFT                                  17
+#define CRF_APB_RST_FPD_TOP_PCIE_CTRL_RESET_MASK                                   0x00020000U
+
+/*PCIE bridge block level reset (AXI interface)*/
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_DEFVAL                               0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_SHIFT                                18
+#define CRF_APB_RST_FPD_TOP_PCIE_BRIDGE_RESET_MASK                                 0x00040000U
+
+/*Two bits per lane. When set to 11, moves the GT to power down mode. When set to 00, GT will be in active state. bits [1:0] - 
+		ane0 Bits [3:2] - lane 1*/
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL 
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT 
+#undef DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK 
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_DEFVAL                                   0x00000000
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_SHIFT                                    0
+#define DP_DP_TX_PHY_POWER_DOWN_POWER_DWN_MASK                                     0x0000000FU
+
+/*Set to '1' to hold the GT in reset. Clear to release.*/
+#undef DP_DP_PHY_RESET_GT_RESET_DEFVAL 
+#undef DP_DP_PHY_RESET_GT_RESET_SHIFT 
+#undef DP_DP_PHY_RESET_GT_RESET_MASK 
+#define DP_DP_PHY_RESET_GT_RESET_DEFVAL                                            0x00010003
+#define DP_DP_PHY_RESET_GT_RESET_SHIFT                                             1
+#define DP_DP_PHY_RESET_GT_RESET_MASK                                              0x00000002U
+
+/*Display Port block level reset (includes DPDMA)*/
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT 
+#undef CRF_APB_RST_FPD_TOP_DP_RESET_MASK 
+#define CRF_APB_RST_FPD_TOP_DP_RESET_DEFVAL                                        0x000F9FFE
+#define CRF_APB_RST_FPD_TOP_DP_RESET_SHIFT                                         16
+#define CRF_APB_RST_FPD_TOP_DP_RESET_MASK                                          0x00010000U
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET 
+#define PMU_GLOBAL_REQ_PWRUP_INT_EN_OFFSET                                         0XFFD80118
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET 
+#define PMU_GLOBAL_REQ_PWRUP_TRIG_OFFSET                                           0XFFD80120
+
+/*Power-up Request Interrupt Enable for PL*/
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL 
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT 
+#undef PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK 
+#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_DEFVAL                                      0x00000000
+#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_SHIFT                                       23
+#define PMU_GLOBAL_REQ_PWRUP_INT_EN_PL_MASK                                        0x00800000U
+
+/*Power-up Request Trigger for PL*/
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL 
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT 
+#undef PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK 
+#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_DEFVAL                                        0x00000000
+#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_SHIFT                                         23
+#define PMU_GLOBAL_REQ_PWRUP_TRIG_PL_MASK                                          0x00800000U
+
+/*Power-up Request Status for PL*/
+#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL 
+#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT 
+#undef PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK 
+#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_DEFVAL                                      0x00000000
+#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_SHIFT                                       23
+#define PMU_GLOBAL_REQ_PWRUP_STATUS_PL_MASK                                        0x00800000U
+#define PMU_GLOBAL_REQ_PWRUP_STATUS_OFFSET                                         0XFFD80110
+#undef GPIO_MASK_DATA_5_MSW_OFFSET 
+#define GPIO_MASK_DATA_5_MSW_OFFSET                                                0XFF0A002C
+#undef GPIO_DIRM_5_OFFSET 
+#define GPIO_DIRM_5_OFFSET                                                         0XFF0A0344
+#undef GPIO_OEN_5_OFFSET 
+#define GPIO_OEN_5_OFFSET                                                          0XFF0A0348
+#undef GPIO_DATA_5_OFFSET 
+#define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
+#undef GPIO_DATA_5_OFFSET 
+#define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
+#undef GPIO_DATA_5_OFFSET 
+#define GPIO_DATA_5_OFFSET                                                         0XFF0A0054
+
+/*Operation is the same as MASK_DATA_0_LSW[MASK_0_LSW]*/
+#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL 
+#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT 
+#undef GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK 
+#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_DEFVAL                                     0x00000000
+#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_SHIFT                                      16
+#define GPIO_MASK_DATA_5_MSW_MASK_5_MSW_MASK                                       0xFFFF0000U
+
+/*Operation is the same as DIRM_0[DIRECTION_0]*/
+#undef GPIO_DIRM_5_DIRECTION_5_DEFVAL 
+#undef GPIO_DIRM_5_DIRECTION_5_SHIFT 
+#undef GPIO_DIRM_5_DIRECTION_5_MASK 
+#define GPIO_DIRM_5_DIRECTION_5_DEFVAL                                             
+#define GPIO_DIRM_5_DIRECTION_5_SHIFT                                              0
+#define GPIO_DIRM_5_DIRECTION_5_MASK                                               0xFFFFFFFFU
+
+/*Operation is the same as OEN_0[OP_ENABLE_0]*/
+#undef GPIO_OEN_5_OP_ENABLE_5_DEFVAL 
+#undef GPIO_OEN_5_OP_ENABLE_5_SHIFT 
+#undef GPIO_OEN_5_OP_ENABLE_5_MASK 
+#define GPIO_OEN_5_OP_ENABLE_5_DEFVAL                                              
+#define GPIO_OEN_5_OP_ENABLE_5_SHIFT                                               0
+#define GPIO_OEN_5_OP_ENABLE_5_MASK                                                0xFFFFFFFFU
+
+/*Output Data*/
+#undef GPIO_DATA_5_DATA_5_DEFVAL 
+#undef GPIO_DATA_5_DATA_5_SHIFT 
+#undef GPIO_DATA_5_DATA_5_MASK 
+#define GPIO_DATA_5_DATA_5_DEFVAL                                                  
+#define GPIO_DATA_5_DATA_5_SHIFT                                                   0
+#define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
+
+/*Output Data*/
+#undef GPIO_DATA_5_DATA_5_DEFVAL 
+#undef GPIO_DATA_5_DATA_5_SHIFT 
+#undef GPIO_DATA_5_DATA_5_MASK 
+#define GPIO_DATA_5_DATA_5_DEFVAL                                                  
+#define GPIO_DATA_5_DATA_5_SHIFT                                                   0
+#define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
+
+/*Output Data*/
+#undef GPIO_DATA_5_DATA_5_DEFVAL 
+#undef GPIO_DATA_5_DATA_5_SHIFT 
+#undef GPIO_DATA_5_DATA_5_MASK 
+#define GPIO_DATA_5_DATA_5_DEFVAL                                                  
+#define GPIO_DATA_5_DATA_5_SHIFT                                                   0
+#define GPIO_DATA_5_DATA_5_MASK                                                    0xFFFFFFFFU
+#ifdef __cplusplus
+extern "C" {
+#endif
+ int psu_init (); 
+ unsigned long psu_ps_pl_isolation_removal_data(); 
+ unsigned long psu_ps_pl_reset_config_data(); 
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf b/FreeRTOS/Demo/CORTEX_R5_UltraScale_MPSoC/ZynqMP_ZCU102_hw_platform/system.hdf
new file mode 100644
index 0000000000000000000000000000000000000000..be53aba197c7857edabb5683a33ec7106741c580
GIT binary patch
literal 809917
zcmafaV{|7`^JZ+@wr$(C?fhcf#>BR5+qN~C*qLzRY~J_$_w4Sc{dBwg^zEmrp6a@F
zPt{eD1qDL`0s?{pLU0I@`jR4Ya|8wg!T|*Wg8q4Gaz2nbh7-ewpX5a}3Sd1{
z-c@LBn?|W28ysYtTpa62*}tNR`eC3AFQfoixzb>hM6)#YbM1G!;-HEa9S5tl_Z3VM
z611>^xN@Zhjc32Cz!V$9gH8c|wW!kHs9KSsk){2sU}P6y8jn92Q!RmO0?Vc?!_~;6
z!1wOfxv5Se@De-Dbclq7Y>ZwhVqs_Bh=>8BuM7D4vM(%g-)Hy5HI3WtL!rNX=#hs_
z&^f6M?0dbkh8&LceSC+@tCtMva3PotJ1Tj2m}5}|>H#L1j?!>~!`^-~I6NOcrLy?N
zL36#8urOstK;V*~0t*g2D=F?@1<6_SC+Q!i5Io=#V``upy%X1mfBxyzGAjL-7Ks0$
z<c$m$vi25j%E+NS)F*6<@44$>eeS#XP-R7-hl)aLkMtZMFmp
z!s0&+>phVc|B7FI*>WQn^>)OY&n}ufa^WdrtUBlc7RqF0oCj|JrtY}5Q4<=7isH#ytVr8fAW-4WQGA>%MF)(0h-RqK2ot7!#d=B57OL>&%VR$_Z8(gT
z!&xi5+0nHF29$uSDx3h{!CkoGL9FXI3M)pGx8fHzogMjf*sKu~j;=C|Hsv$#9=s*4
z$J4tr|B|1sC{v
z$ND#_KI0iC&iAYpwyWpKdqdL7rS8~qC`leXU1HIYCv031jFeJ*_=oaq$l#ivoBBl
zSiUtwNCYHO@_ODFV;cnHh#j{v1_&=4+H$nxdO_X}(xB1z&c`;W?ZEAK!W=);8F4*=8uiup4OLpJAaOLsaeJodQ?z|*dM#X!V
zZ8;efFYuk5Haod)+n7Qra0G1g@jVt4FI(K!w#EBjjcOSUqrg7-8eF{*8IEG`5@(~I{e1z
zeSXEB1)~4Q^K!~Tv2mU`b-TU0)>h%MrC&7abc%NXQx
z0Hu71^1yy*-FA^NqgykVnU%}HpxN@|iO)|5#6*S#CNVR$58jY}cu&6p1&29JHv~
zV>5v+@)JVECkscSB>xYEa8kGG56;)
znA%1XztP#-VZaB`*Kdp`qtEAh!VwG}r0>CpGQ^dES7+q*270r@mlwg`z7LRjxFuH@
zp&d__Vd5Fbnadvl*W?Vo`Zd^~N|=wrusnFkn4p&+3Ms+K0FycIB;6H4_^nr(n9qof
zw*c>^p!x3uuMpm^d&~hiiQ;VLhtsk4PUg?+0I-(z#Z6ELp$YO
zx}VlE6}a0<86`;bPwhCTFd;h^eTLGw}g2Y4Nl5s
zjCHDBJL~vcs=XoJa&K1wjKz~rmQMVhSb7Q0a-T;pyH1mh6~A)i>I0D1i#MN8-u9nd
zrETC+CPqQB#c>7|=Wqp|aW^(&zJUh~2~fa${3$t$x5*RJ(HvHJnQ&|c%kG4`@e~AS
zCBI`?B3AfbJ6|FLN#8lyiaZvvrYeXG_Rs?}$R90v$c!9DDPmXOz>(T~_x-f!AT&3$
z09LAYNfqw5MOHx)ZF30;-Sk$3!O5&WIT7@ZjFP%1iWAlwtqAeGQ@YHQOz#Pra?A`>8{h^U6>NuqGSQB
z6O(9tA`v%4RDk>3^}Z|z
z15ZH6Hruqk_uMccpm166vUT|wE@IrKltdstd=afR`FE9`3zNYk^NQoA4Y>Dj($;v0
zudhFZ{_m?*9r};;mU?8|K&?YJRly*BIRkII3dLwp>XAGARJX24J>W={rnLgAC{c9~
zK*N6`PXw079TsTa_{Jr*8c>Rn6X!s~&k5)!K_q~3bV^%A-5HG{D~;vPj$|#Pxx-5&
zr)Ve8BUFv3a!ndK6#&PZN9AK)JJxg?Sri$cy!!ASCk}hGx0GcSC
zM{E!hk&}XmWW`4E04E-Fp3?~rolqpTMqfsPF%Mlutn=8rX8yYqTXg5BY1jC;SP4s+
z^FC-f!GO@dV1lu{z0GWc0FavH4P?>_=%ZjQXF*dK7Y&;*!{JA|S(kpKCLoCFMY}on
zos2jI*0w&C)gmy;1zUNjbl|}JM|N=LE5xzBi&+`$_sE*u5NcO1UZag0glD9xku_;d
z(3n;{N1kC#Qk@*dOKu1xCQMo`p(Ou
ze`nd0^h*%<)Sg~%COU*!o8<>kHF@N>{ILvyK6DHg0upblrkw3kkW3m#1vC2j6zXZmt8EB3&e4A+%REtDzIhiXy<3p6}grmF3
z5H1YvYT+i+)<1!DXan5ljG7dnH%LL`cD*L7kplUn3}Wa6&d$Jse7TVm39@UZDiX}>
z&Ty9)Crb_D6fAErypLzVefl|jW{Cf$$E_52Y#0*xQ`})*H0XH2zn)5RNyLiuWXuM_
zaqVo`-If4L9Ef0)UCQsA4g=$nvPh0v;GAG@XFg+a^@OTs(0Zi%5r7A@HqIt&E5=lw
z2O~>xXBpd^Mq-jksj;nrPEgwcv~gmDlFlgHlrIDU4)tpaIb^u>;9q9E`+vAeSiRk>
znFAGoEh`>xtWVg{<;~*T7+xr5_6ucEi+=M|lhTxE3yD=yv4J+-X`?j*g9Mk)R(!ZT
zLwV+bzaz#8y)vRpHD*$lQ{6UG4G(B>j}ht`dfPDGPgaa>F!N@Ku&L@7RoE}G6=BS{
zCt&f@H>_rQ@4VVf7;Qxx6Ng#hg2P_Bpll`<=k$AeD$!n2bH>%~)70}B*lxcr=iPS<
zOIT~Zdh;FMNlkT6#rRCs8pw7}Ena?kh~1;EiyAJe-oRI;RO5-hx$z&jh6I*>tX}FI
zs*~6HHg%peVsXMGqL-ZbCN~M0kh4Tdt#$fhg@KB#oiBD?EJAv_jJ0F3zlNs7PNEIXD~C{(C=niDz5wG*$tz#ng~;BsJ88cmA5DdCm&bE
zQlh8iSpF**|6HzYR;SSNWJl~8&Wx{T84kHg@Ma&=Thz6Nrx;BC3gw7qY|cHqYw6RQ
z)0-Slnajl1=*_TE$#ZtHs4Ba&bvmKw%s8`{ijH?R0BdR#JeE$cRv$_=n6<`s=Q|g`
zg2E0rm`FxY`dH#SZjk0rY7g{zf1nl9>6XopWGBIXbTTs|;PsHGI
z(zxx~$;-4J_Xn^wkvY&YLFis7dv9A`F#5OkcedhgsTg;8R})a$W2Fx%)v=mld_j+5
zuf|yUjl4*AS8q&)L1mJGTRr-2y7?Xu_ey>sxw4C20DFHIXEYXmAK19}=Rs5ciB5g9
zO37^jXZ4dzX{hCA#%;l6n}%ZzsR{WyzH9yPeY~4%#}>Y;1KBbDr8ik#1g|gT?rm#}
zX)aV>9`9KpajJ6-DzQKNeAmHCpe6q&LKmm1vpnwEL*J&q+imit#y>%do{K^duiT3_
zgsyc6c)rkLo!|G-f`3&0$&`Dp9P*y|d+{F*M9$zpD&;19xz<-=E%JMGS%kzb{bSiZ
zM+uMP)OUWl9mxjN({$noT=JfMdCKrE14l#lumS=(ck|V(EqN%^*LKS~czhvyF`mob
z57*+ah&;y?E?4Hm^v|t9p@jB?p_&hw!EG{r&=}1>&-{6r#ohpq7r?5%#Y8N_ae45G
z{idRo{RhXlc(vj+uWF}S=ph~p!^LYf+6
zAveh>y>4NQBuZgVPUcJFV2Y{96*OEIsToZz=}Uw%!IYnyc4&$g-Shn*b##|%&T2$s
z7?$`UdoKCtWQx@Al&CbV4}3dAE<~k**>ML`MRhI)H5-FscDR3YWDk<074{4xwBZ97
z|8POB@O$yAz)Kq@fI)JjopuzA;6IK)k!Or(uJ;SgdvSz+=n|TtGUxJ7U4~o^b4e1;
zggH%}_QFi0dSt&lW^VX=zS_Y}Z5p_wA$3SP`D}NEFaVFdAU$x;(g$n7;}8OXd+S=3
z@z!UPJr
zPJcJ!~1b$~#a-tnE}HJ5^IM!ikCOKP@))jkFh4w~C4ohn~?^-jv%IZeX!B{rnQQRmby
z5A6?xDsxeJ!=MDQcUiUG9JHja?xgKmiH_mFQ5PT5qTx@Aj;Yz`iI^Gi_z)-Mjw$Wq
z9V|^RzRKTo>U&V#Q^rrQdo$D^NUg3h<#5h0k5e!mfAN1hKn=yp!o$GSWY>S1Ya
zsRLd_eyao^q&%E9GgDc1Pi3N{8LptDfSPL49MJs3{h0az3<4!Ml6!9wcM<(RYkpc=
zw(Gy!0Wr?-=1Fx0xD4<1oK98VcRGUvLY6kXenZPH_e-%F=)3HWsoc{2_qj%Cw%gxH
zb8q)`_kIfKzYd;e(aiH>bz)nq`M6c}NtQ#A8&D~{n?iTEyqYdjdo>75vam2zBHNT3
z{;GCw@+i8ceUD@%Uea-H69UTsTXq62HC@uO5dvH+JFzG0FX$3{^e46bxwIt5+^MN=
z68q3BxoKJR(jU#Ah>q=D9Lj#C6pAcq|F~Ape_V^_nU5V1ReSPwCO~Zq8jA#=i
zSf=_M-y6rpIi-y!zs=?x-xn5!Ub=sG(^-1)0j{eNOzf(f`RWXpvb*0OUrwa@3(x^Ct+P0mzi
zbI9dy$$vuCq@87_aSUTR?awF6UChHtCz0ekyHY{a2B=Qk|6b|6rgBe5`FrIY%bgm|
zYWo}YuX+jHm5tt}7H_4e{n}-6K@$C{MQnp&Rfd5LLg^O~`v)M6s
zujag+UMhp(q+*J;?a^cU1chv6!_3w=O7M^s&#*4hm>5
zT50cbL@P``m_2+^&#+#f$>EFtIpG=U%YcIw0S~|T#N(M9M|uOKLTnlGZgOd%Yy>yr
zdLQk6-IEQ1OM5LA&W}f7L(VybW{Afe+mTfL4tNm!O-K2#cuj^g1TN5tj`(2yokgH@
zkw8%_9>Apq*Jcp;9fS4C?_U&^`Z)HgUGL&g(nT2;f7Y_s*4?WS5xtRpzP)A*4q0zX
zD>{8Qtx<|{TLOO}30H?%oban7b8ZC0Vbom!s>fI$Q_PgjbFug8a=kG3`7Iamb8Ir<
zNusg*QY~1s+%)UcsE4*IUn1s`w=u&cWFR2C_;ud~?=B;QD07&a8Dnn?o5diidJzQQ
z9}m7*+k&&fslEF&*9Q2>I1E4|-px%0$x9^iL6i^lYM@s2n1G;W`{silP;QiYJBsn{
zL3Td+x!;_jFqS`xKEdDHiywjw$r)osfiUuPdg;W5xr}QNdG1N&$vk4jBIlbcmcJkv
z@Ed&xm;f|e4%39&5Mj(JfN9X!wJ+AJE7y1=Rxmr}{n%GH7f}G-V(}(shWyMOXLn7S
zc`6YF(-1gUyuFxvRzdgyPjy(xa#5ZwhGP9!4lzU{Ik34dk}n`8|AI1|9#7+ZUgLPU
zF^Qs2>ec2Ot7^j5tHBSv3N%OrlUnh`JQPiNi3l%^Yw}>zoGsvlMtzcj9J+Se49EU)
zERnx^WDQ7RwyKgsuO+KcxPm0!ZS8XChNmJLT~}Kk%rC60g3A0UU2`11730<uy}s{*b^i5;Hh+^ITZ=s+aiKwD)4qmyw7GdF4D^RP
zNXu%>{7gV!Z`jtVHNWPVQO~xKzWlfEA>9S2LO;axAL=?}Gva##Z)m%Jxv+gA?`WY0
z4!)2-V3AcCacVIz%;dd9$?m~H=yqE>7Y0^shAg%5QL6e|&{IW3tT0ABocn923JIkf
zT%V~e))2rP;y0N)LVpIJ$OI&53Yc}#XHtjmYxI9x*;xX1$sEgYdv~%diV6)-v!iu6
zJL}QheLLWFBJocm;>50|Z|TsPr`I6Ab-5#8sY$aD9i@?^OFxMb5lS&R}In@2;v{A-va3o3?K+
zHygLF$5}MFnR;|&i){G)RVQE}!X>chfbK4ZDFDZ#fdFSdn
zC`Pw0tGK*Rmm@y`Y}v;Ww^N7kg*ItkARie^^8Sx?e0?*}d)Z|=moEL1reyEX;yw#yR{a|DEEE{xS7r+*9Ja&`XHJPwmm0iC)
zdCnkge5KLiRdxwdZzd%_)RB39I^up9?8vg68K18(jB^tSj^Xu9KQVtTvYR@p%a}UPcdUQe4
z28~MtSFOponZ4c?9K=>*>Ri)6D0SFl7VFFBt9s};y(diznVJEni`)o*(!D@mSPm{*
zd2pjNoH*yB=YD>)>O9cgP|Y>le2<2aZ3F305i+iOsdxO0B8sRrZ0!SmHB^_Sc{){})(sw2CI2HeNCud5n@z+R>b
zZQd-*hu&{L3iP*A87}!qH%_G7-z41$yCDO#N=f|YLkmpWS{2XTV-4z_A2KjBvXm(2
zH&IGNwMrLmsV5gS>gUzfVd}YIbBC+@8_)1A#h-&5Y6Vb=)OTi^i<*C8ZIv70OV6ei
zHtojjdd%D!iX9eD`HNJZn5C@*%mIj}4f;|JCdi#x<4DlFX+!G5=0zP6kM7fq-F=};
zlZAn6n@t^PZtY2*oGV}*hj_J9N4J`N?z|L_<8;yb$Eg+3L1veB(Ux--XV;Ej#xdoy`b91cCym=wPy5eHw+>{+)%5ph*BjbQYL0GoI&~(TL+Jh^!O(se9XqL_a
z(Z+|{s%wKT*A}h@mRxJ26B_L843eCTKK!4dHrjT;th$vEH5vD*xggKCLt{H^dHTV)
zX*##@6boVU2)dWgOldtUO!s4_I~
zD((MOc^3<={h%u2sx2*SvgZsJJ1B^It^c=Jqn=VTxA*xNG!&{$w?Jrxi*>F;7JWuai-0xw5Z8C{!Q{^
zjOc>k+#e0b*^Qc3bucKJO+8qdUqPgu4Y!P+AAA0Ij5#mr&PjMG|049r-rI>(EWXqF
zN$Wi?9Nw&l79UUJmhGAI_ar07^XX?;J)U4c6>K~ZXE=wxCM9R?ZRaavjee+P
zQTmcSOs7h)_7}p5xj1OOq0dU?OR)D}R85?;r-uQueI}cNAW;&*h9la#l)u)HWsE#j
zVAg>YxC>^_C0rzs^$r2g{R-Qqt#htU?6P@TknH73)?zL?
zlYy*?!p)}z+#H_aPi$=6dsRXwaQv{NTAF)O_}4|s{Zc|3I=y^l5lt_th(iYeHqH%@
zjN99I_cZ}c#kGLf`StM@>L|k=uzAsz8ra?sgJ(?@!Ygv
z@8ZUsH7cEM;AHd2Lzx!S-lyS`xh+p^H|VZ7pbWouRl&kT1!2*7b28^Y%!;sGj7{yopc`k2;!eJTQ$NHi%oL;XYL~$dWGZ7V
z=8$9&`|`QK{E%Co`XfGKjsiXFK>4qk%66J~?l|+pjgvgS`3uY01yp27+tyU>-jtC>
zyi*>RJvG1bqJuV&*S>o^rJh2;#Y=@-tA
zUzs+qC2m(n*(&N+G0v9C=(GfqzYi*6=@)X9vFLVLvPgX!TxCLT0cR=>ZHx0SbIUF``77FO!9te_n6N7q&p>fBVEGDscSLkxQUiVTXygpc~_%c
ztYPx}x=Fb+gal8#;BsoW#1#A43>pAIHH>(fy6AOIaz?2z)cqWdCay|>7Q5i$BJIac
zF-T=y?$b)Wd|9Qc4(e3yIL*H{)@eEaX^f9b`!bK-53#Lzue9@eX^_RAs@&({8wC??m4+=HR$vdV~>R7VanF)oTF+9o;Lx3++w
z=+>GMHNM+;TLrEfr4%NNXgKKL1wZZJx+?@!lQyzPx{_(w_7?Iu(Yp>f)I0?SIH7pl
z*GSp96_XbcAssbb^E5BkXm;R2eAM5FBSmnO{(8y0f{II_orly0cvwnUOX2NzlTA>-
zg1eejFThCIwI&6P^eNb_E-j&osSyq)KMnCT+U7e#b@QO;hDb>s*o3Wni~jNyj2y9z
zlk4J&`j3V`>tv4_7D>Ku_GG5KHCbB`Z$HgtXe$_Q#0Yg1D{C=t?y7>QiS1I>ZIVd;YWTNj;wM?S|r)Wat6Tp1>zq
z+?nxz_WH;_tzy{rF|;zmXv*J~l&+yovz+
z$xyU9VFu76ni_d3#9N-n$N@(fTh#e7$rY7gSC(D8AnZ(+m~wfr=SYskZ
z{Di^TGBA!2UjVE)frQ
z8z=6?;>My4^1oH6L+x*3hc-^qpiQ%NB~;76+B)Hn$2i(`0Cq0bna1fqm%WUr+gX^O
z`CGGVUQoXcvd=CX)b&Yxi@^N=^p52W5oN!&?zwJ{rw8vOL-wZBqYNsP)O+qbN_?YTyUKe!d9
zd#d{tpy&7MuOen_tXWn5n)Hf1iAhg?t|VOQCX`=ULX1v
zId4#Ws~zuj3txQH5@V|BB-3y0-;6u6n%b2dM0>3;W?wUP;PQT=?%%Ziwc97SDMRX5
zukp|buspj_u7~S-uuo?%?B>jo7x`y2;nDicGfk10NJbGlmowUR{a`mZ7-`o^GB
zePP#@26or>El4=z=FgO|>-x!B%ar)S?xp5z0J`fxof#pI$)A1s&8`7yMMw6)2xY@=
zor7mrhDru9g6W#TiafB{DH80Bq0
z;euSH$=oV&qV38KhynMl=|I~_2wdoOH*Z49IneQ$51RC_(Ulb>eJEb?oa)0SFr{m2
z()w)sx5NRRrG{TYIa8++WeMj`j4VQy{NZsKZ01a=$z?qk-L&!Lto}Y%0H!|VhX|-Y
zvQIIxgIuxDhD67G8VHAjG*Op8WP?cDbX*c
zb~8|(Jo7YqO(?QExNSY482?J#Af%8ttXFdCMA4Jv=Z;kx0P>amUtA5#detZB&8~I9
zm5w?=*z{o1A57|)g@$qC(emPerOe42fs;TISV$>*u(3Dp-0afThn3D-OAEwXQ=)V!#0|i|fEqGI&KoSEYrt&E
z&{=U{O<0I#S7^bk%GP-HXV{*@g0-6uK{t)-Onp_=>0nJt@VJD^9+~^JA7&&yc%IKg
zcuV|Rq5Q)xv+$BoVXFk1IzVclibo3JKnB8*B@GS<6{&>0B_t^PLKndGT&arY&oJaL
zxkn7vrK5d?^~E^NpaB^oxLzaPvJNu5m}?tYjv1GM=9&z&1M%?jw+C9k3e94cv
zQPeTd^X>wV6DvxT>WjkcViY}!FL{ZtHDk_0y68PYVe!W(+RnE2S6!Vb86*-Gwe)7n
z))##Ra%T;%ym4Y#(K}Dk$I4x0a|@8YOgGSX6^p?o`ZGkR?(+Xw33T8bDv-?$$M)T)
zk@e9z_Ab`vv46$H$Y9gkg^U^M8-L6BiTjN}sWM(JXPPvSkojgB|9j(X$6eMD1&*&=?PAbij$=Rl2zZe+c
za%-|i+mtQ0)--S|DrR?Nk|$5S82P8%iUMrc89Fn0q8qN~-_W0xg3Y=tffrg=4$$jc
zWlA^5Zy}u$PjDmU%51J!f6(6P8=u9p*i_beG<;me^9mYvsZ!#
zXcfot`A=z&B!KGj=zb`SE}vm=DnabgBrqPr#XUo>v|ssWuIc5EnYXmJ7U#5@kQ?2+
zDlw4jotSee7xP_ELfQQ#gK}A0X?C2W(EvI#;86}dC!LOQU88~#$yImZ*Ro{K0C(?E
z!-aNt@NxLldY>hN%?^X)@cN(l4EQ)L$W9fX&Q%N4qvUq@j
zJn)2w){}?1n5{t;4K75#NDH`O*@28Irkc_~f+u*hlOHw5kdt$xH10RZhDpSlSctaK
zxNPe$qwzoSy96lK-kj#~E?yWr7Z%j8Q+Jw#v>U8w48^ONT7ys7j|t>$p&>F!)b{E`
z$lz$>KWQ#T0;irHwNb;rE#_VAB3p$Z20c&qWFuv{quvv`AjD+{Qt&=M|IOP!7%ra&
zkvSh1qk|X5=7I=S)oNdn`xyYX_&Q8H#GoM)hGB9uD==`iM9p}CSPCfuKh}=;kw=Mw
z^QrdKDow)705Fw9ojc<5RAc+Q?%SRjRn<&utKi*aiSpao6pJ|Bj9QZPA}$dRb{jR#
zLW!sCrj?450*Jk|_tr{f-7uWirIm`~0*UMO^06y_z_HWcrZbf?cw+;L}YUe^Rx+A`Fl4fEjznq9w
zA}?5uRiDWvBzaqH?F_4uh3%lG%h}?5+f+lJd(+wN_@lP#wQYUnPX{ht6VtnI<1gH+
zcZ&oLjkNr4wEf$YYMQXBb4{GC{L`2-1794X7e}sM^q58dJp&~YR{gn#1er-}c}fSd
z<2bA3FBwM81q<3~_1}?e#cytx2V$RZPHafE%g>$rR^yXs^$ZgSkHGzx3<`^0tK7Px^>`sorz!8bO&5yb8;qsDfR&R~XbqdR=)
z&XocU^9g)`+h!NFjBjRb9$<|R9KaMN|L@}BhuM-+Z23g!JCosa#ISY%8#evh@SsV<
zlgNjmE=(WHrO
zF=6=Z5bEvTIi5_Y82XzG+Y~di!^;oH<(Sj^Qr)k@B`
zMh;w??W1+cr^RJC2RS^qATOYwerhBs`S>9$uKV1TppsUNl|0rZh;z|XfDaVz)|aCT
z{}%{4<|Z=R)XlCD*C*O{4%WF-`BVG!n)c!8*SS}-x<$p*u)9M2D1YLLB8G43g+I4J
zth+_XB;!rfjEA^wAg#J)G5A=i%|3UhG+9N1OvIx#P8E!O0%0jG{YgN5udgca3uN*^
z5JoT$h4(@WVHx5ybB9S}|MEROp*pYTmusJcDg568p9t`ae#5C=X|v#_z50GmGnA2N`S
z&=(o+(90y}0weWk?I->{#fpjRKUHk-mOzX0wzzS~i2GYeMlt-(c1Kub-QDp)PiQ`3
zY*P0$*f9h2foT&C{CVr%K>_Fchebj3j(v>%{VWDX78m9qwR;Bt*}r)R4b8#nd*GKJ`bN%w*zk(|;x4bZ23GXb>
zh->-v4SdN+`lJ%u%TW79V?bcPaw`I?L?bO?xC_2L?(mOTy~fzlBbaP0B!6wcVlshG$~2_U2`{->j#onY8E@~AGDwy?>m4^bxd
zvy7R3b%zXK&yu?fnjZq+<^_zHcw620k0~P#BYzMvX48_yiLLOxOw^mE$w~Rv2xWEm
za?{N)ZCEv!YCSzHvV^g16zMbJJwqnHJecFGSH8I~=`xcSD(Hzfdxk~z&i+`}?~=m+
z!y5+0M)VwisDq-k*(%=NL}sS+`RwF3k+f0EB2sL72d)wKiF1438=fr6A0X&AX7Wjw
zYPm2lQt+``s#C)zu!&$d%7KA^uQoiOAd4WA5j>b-(++`bhO;@w@G)rc!#_4C?|6zL
zqITuVD9fVXY{D~fc~t{@FM&QIv1-oJU%K#>YKL;&V#`X(PzP2->#C0q=Mww*gMMOU
zMuQ*Qi{|YKhkr-C$|Xg?coXd|)q`~7-I<_bMb~T3?tYGPp%}nZgmWx7)LO-7E*SkFhkN>eaqver()((L}@Ti$)M`l2N-F*H_^4{YlE=ljQY>8c$bY
zAa)_+>z)M|L{5I389NeWIx3*d9ZQM2Ls+3;n@kWH<__*cjCS}QbYE5CpAB{1>uJaE
zqWPxiNAaYAQsse8NmFlMbwqhSqFBo{
zncQw`^e*!S1ZWsct%3m0R&BS?p~l57z@8MXk&<#~nQLB%=1aKny-nv=-IYI+F+ep2
zR){`yQBtHmX2TwIo&if-b}xb=GcI-#>plPE&D$L4^Bk
zen!H=33uCHx)d0=}N9
z{Y8q(G>GhxeBDuS9p}cDH%9Mp$HjHcQIK1fy$byVdw)g8Iqi+ovh>RBC}?Gkd0J)bNMe%IQ)R8F~hE*
zxq$?PBBb5I4V5VlkM|S?9ew-}g!Q#%e1guqd>i;MZ*bzS4G}jx6%q@W4XfkFW@{gL
z|Mpte(fUhA&WA<*CWs-vJ>ToDGDLDds*OlfGk!U4j0FEY(Z8>c)NF+8-WPf_e(ApEKU{C@cyAd4LbsQIRa{fgARY@QA?>@oFEQCw}s5G?VMXdQ%h54QCjH7|yQ0Y-*Kd;IG!BZ$gVM7@)?
ztr(sS`V1xz`g#IC7qw$cCIQ|?9SX#gf8p3LXLfMDzU?)NeT&&N*kMZaT;Nl6t$&VVkHyXXY?3jJy)&IUKHc
z_=zoH3^ll5guhn!=tgSmUrKE?2Z7R(9B8clwmvxU)im3`G
zA+}Ba_QNfXAzx13quNo|eLGv9HQ&}0-GF9xyKvLb5(Y;b6Xt
zmOuY?F=nZ}17Dw2*|v>cprl;A7x`C90z1RcxI9)NI|V+M5$0%)Idw_}R{n%ih;l7c
z-lxfLzc9gOXt0%HsIDauu`ZA*@ID%T(M?zpDOl;7OuJg7!%#t1u9c*7Ptc5DXELr|>{3A4{
zu6@0T^7fA&h;cyF2(?$k==jc;CN5`%e=+bPgk)-*NI>3_3o67v*W&#VO`(}%lf@{g
zham9}Sd$ZfZqOKFgJy$yJl0!uk3HxkVB(cC9mhMY}xXbVl;3B30A=@K1o7jOI~y1+*%OZ$q7L4
z=4KjdBMS$hb~ATw3x#y^wDAsBzZ2y=CI!UhBzQutX!6l%)gw~{2A4g@7=rFB4dl?s
z-7+ZRT2%mKO##ZHE*-9aNx#I8Fdw?lQQ8!+sPxw<}}k~oLxyp
zg!d;!s7^*>rlK48vVIO8+4!UU;D2QD2cO{f
z?UE|UqQ*z?PWVd|>siK{dR_R|xjF7NWT*7_H6%YU1{B?h7eaPk%)`6+MGR=<&V;ZL
zXQXSIL|n+htRV8AD|9PDA%g_KvyY`7s=Ci_X!DOan37=-xbLsY$q1COU3j(*FWFK*hfxzyg6k%zp|3w6COe{LcA9tp7f!_kvmFJpO47rI+#S$<$U~^HlO*Y{s_}ToFwEF
z|9%(_;7G?`?jL6O3qIws3spHK{UJ2fV=AdS%b{Q&gN?Q@WR6{+t?D*?p|u@W!C2?>tamrSvQGidk}
zLxeFa)oVxr81RWhL&5QYHEM#STd}|U`XvGlRs0JMdJ#o+U-$WM*W+IVqLD_^q4d{5
z*@HGtlz8A%*92E)Sf_-|#5v+?qW58)mVfW_HOqpVu6om$35PS@XDn4-N1H`3-$ib#
zBlKPXx2w?nw9^rM_=Z9$cQH^YCZ{C*{ooN8e@~~$5p-t?;se1SU^L-401k5@g#;;b
zdT_`#$?(a+C}A2Y0v-L_E3?C?%}vor4o2>+9=~Pq?W#ltjo@X}!D_^Rbb^$dzj`+m
zS~yOfbZ|GUDaQ)JL!=I0zZ76YP#s4*I?~g@oeTtFc0_cAJW}8kH{(O8ky;%If$%h5
z5@J_q@5TGjM;c7dC?tljS77Q`A!%{MokbD3ZaofO5piUVp%}XVSN6d=Bjk;u5rJuw7XNkPvPiPl;D2ysM3|0t2@
zMfV&^xrElH#6wctD0&z}9?h#}9s`2n1?50r2*vZF$=eycWg0&5@K38YZXpW*G7B(-
zW|oiy(?v2BC`-vn9j&D=gmfuW&z?ZRI&w}0E2(K(wF;;+X4J7h!zyKRX*XD(p#!<4
z(3mHT+H^S^0uHmr;!}h}#saqkwB*CMr|lvPDboBRW94GFfzh?(egJWzXscLD0baT8
z3bIPX#>9U{Gl~`U&=pgIYv2G+HPxGBcxZLNBSj#f@<{q=g@X$M7+^@GkAito0EVW@
zCqiLhGueGKWM6>%0CObFp|Bv~FHSvnY6*5~$&yesqDL4rvrDm)O{zW!
zIppoph=6jqK)oTy9NQ!1g>o{7In8p9`kaAxs_sT)M)j*DtKgIYZpMG>WZ2D7!4^MB
z(SEmA{~2;eSAY?AQ1pFzV{NG`#Tfcsm594=oR`-FK1``=llXi;{RlWxYtV7m4*p19
zGIC%*f#mC__+L;2%Sw;}TOpY#Nn=Cu_Px^!Ov~~?^7RC@7z{}WG1u;od2E?&;mXbD
zy%w#pHxRuN#)Qg6{Zb%1*(a$G`X4~+;I=qr056rAR*2@3*8T4LB0v|HRT__SMq`fn
zKN%XW-6IHKm!2|hX(pPhbBtv5`QRg|iENgI<3PqUTP|cVUy%I^Ekmzbz!&2(_dTXH
zXLKj6l1WG^AiB9?FPd`GP!*&ck{t<=*--;
zV4pQ+Mn%m16?vscD$fJaeBU4_78mb+hT}@w{_yvB-$ef?)2}!Bjc)(4%i-@@TW7u{
zDd&zDM&|Oq4_(OOgS=cFiZ$Pv%jibs!UY8v)7#rIf>4jo(SNIh|2eInHCp2Q?Br)h
zfmR|+y{y3&th8ksH+*e~URNH@;mxQ&gjb~x`#@j6Q%5XAUO_sx@#SnqPGhIAuh?*`
zvEmXa*P#YMPHI6msbc4MMg7Tfpc1e_T4m>yt%g>uMn>oTZMKH6+Yd^JoDvKoKo46y
z+5g=n*E$$UnNRGp#^6h)-9%mf=~M~U1qDWkt`sabKVvv_4N>Yy`a~4$hS*u%2@P~4
zyO!-Y=^hIA%h4FlkHaMkpL76QPL{0(uTdATB)%XTNuA9e2>R#i3YcNmjD^!33OoPK
z(>*#e8ld7|L~%8b+kLj7Q0}5;yIbfWm;#3ifdjvvUiKc3
z{&o030(kS{ShLl_J+b#Kd0nWu&rb0{8)!X)jSfI2cQwTbw^O=oF#*6n#1Tx=b334$
zgXB5B=SMgbHr8+T1~wYv`VIr0aV2wOtT}!wwn!D}^iJRI@~@;$_7~Is<9;o1|BEy{
z6%7GDukIfBq=blI_!`%(WjKwxO%{8T(T^`itB{U#izmnzk|P^Pl@ojwQg%s<5SXO&
z!7bne(GnXZl=~Y^$!~pKWc{R6%5dpTRgv-pO1T6`-{**V<}pR>$EK*tYugE!YKjVL
z_4@n?ac}f>5u=2LzABv}^eF|dLq&aw4wbRlHuODS3;i|I&}F&j^hDhgjvXP3by9y~
z|DvuHlgB!7XH?J>%U3#$i1}(K=$fyZL+X50Eb3bo3fSKiIb*AXBzS_GH`VF@0J5zP
z#`IR_kRRRxagCH>dy%4u<0{W^X$`w4{2x-WCnQ%}klEMaFhNq2z#+{>RE2Ze(ys0M
z(7FI0XjGEcz+*Jo6_*ItdLvHNEpQ$V?rO`iIUEP>5&r-*PO
z&zY~Rzy?Xj8xV=qi*02(;FB{E>;G#tTMcp~U5{=k2ak$gLzvZ^E3jb(N;7bVPscRNN(i%`GL&e;jdFF-2e=T@nn3^RTn9@Z$O+2O
zVu96mov!}+SL8^#!RDhvcR(Dy!*6M)<*szxsXRQm=3R=pEP=XC7$IN1@mDmL3%bdDQX446>qBFirmwXh3x
z*?z&>9+_HBWt}1Bt+RIGm%|DUOeIsA#yQ}gq=i|wN?iI$-?o5r
z1gRwC6qMv(Ce+;3d^%pT7NZTTyF!`$?HoWT%9aTT9r{Aoh~eUhRm=|@W(R|@fOU@1
zKjVj?iZoN0%PxBEQuv9enxGEZaq$Sm=XD&@QmAT~ghUpB?+D)30UV^5(EiSuEBG#Opd1bQZj7WTM@@nS)N&djkSR>&W0a+B
z1-uRJp)gR~deL`azUS81x-YKxMjY3iB}jPtHZxyom-#
z?aN(&3SgEwi6EEV-~EoT0_tKdc=X!AuifVB?{;d(yAQ(~c|@Ypdu#)aht1r`8!j&l
zUl~NM971FIf$k9UQp+1zGxRT!Uwd5)`vSYjwRHF=MtvRVDqV9#=T$$b7Locf
zE{P8{`9a
z2&&YKcwZq%yrD^=f5J|H#+cZ=l_0QT$vnrHuL-1^q7=VkgjZDWC=l~);i7^*^H{@Q
zDr-0n$JJvTBsnm%MtNG(&c|i~uEMI1w|qiQl#yF{b{UyHL%rPVHsjMuH2tp
zkee8fRI;Bs8z-u%X;^1teFz7+(tDFL%UdfkS*v1!qqrHoa~KaT^Cln0_bo&5D-)iU
z*m|@aaD)K%f0=!B^ay;cK8h{nyr)e}r7s399rNefBS94B9gsg9&<}Xu2me*k8`$`1
zhol_7D7^*AvSVDR!7A5J7DroKv}YKwp~5Zf!=Hik(8i)Ml&T#7yv$szk^}b88QjF^
z)8q~2a3s|d^{?X!c)LJ*`sO^1Q`*J#{ktBS3-nG%@glf*f_vrAjHs;TC`U1Dku(&5
z9W?vYGU%VYhek^zs#2~-B;BMr@sO0m)pxP#Jya>!yW({4i>WgZ!_Sk!JydHGcBJ<@
zLq8fK`d_l%6`nUf`(V4TF}7TqMD4}xaSV~1po%QoilBXBCu6%gCmF`gclA$>*+Uv<
z>|}HUpAz4rE>0Lkc(p&8scy~bAdUm_6@?r_lOYvDYIgDjLsXAr7(hUr+hi$u1g3~6
zA|)>%ry#&_cS!DeVw*_>Nx(p`@ySRi(!x-I+6gHIF~u%%tFG5VCh4Dwyez1;Cq7nx
zTm2UCNuxQ30g$)GaLz5_o#^%$->9-#m+Lu2!JTm=7!~bK8+^G%^0sbC)0K`FpqS(>
zqPBb)gM+E%?JP=-P(ey&R+qP_MErX-<@cKYoz+vP%D(=jYzY`F`ll)A4^}9t^0P>O
zfmRJymp*2z0b%@nrjFw_#hh$>%W;xeu=!xOOlG8}`CIm{{5h#ZONEvkAfr)(qX=9$
zRKU)ZD>GBGLk*ub?Nxqr{330T%nmWMhPe=7Oa1yKw%w9S5@)~Hn?piLq6`vwl%!X7
z$bfZw1zB!VoCs?3jm3x_Y|vVZt=q&UY(Wc`^ogNMWoki5y(I3E2W4p&8Olst$r)#;
zvX#NhkRdU2t737TX5VozkgodLUzLs3X<)OqRT|^_=41IAQOBmH9Rz@A?i**#!J|pJkOWg7V>qe8G?du3|ezx8?asR_0U90Zip&
z6bT)1IKc8o-IK$v!j=gOjboEBM&75hoWVsT@WB;+eu=8mD2W{OT|@@!eF)CMe%V_yIIl=0@2zc3BwQVOig+
zp*ymr##erQdkU9>>jnM8n1JaIM>mM9r}Jif^-^J^T6?yeNX1|Ytx=z7;~~I?n@HDW
z!T=}$00(iIsTt!{7q`*BWinNk61zi#;+8Wf?1B-05(sb53g<0seS9^9Zle+!#4a0L
zrIworen$WC2jw;jw*kL!LFWn@hQl5(6J&y-1cf9-(2SJF|D6*g#bbgo(T$g%*21`iJb1
zWtF(r83$c3(>l+y1bI8y?eFVa==lvsif)L@4u`q1)579_$YqDqGZ{PKa_Y$&p~X#A*<
z(r*}HLwOs9hf_7H|Ci>en+LWqmYkq}!g&=}qwGzL5l}qK5QR+klEg;
zE0qO#2n#T5+D`&4`gb$qWkBt>iUIjD)wfE4_Ire^OD7ZwjfOgSjSvWzP?2M3!y5p_
z?1#EEZhBtH1ToTY(33akJH-+%zmicl2=zGJH*Y#0)($I&M;QuoJbZ=BTA>9;H-Ol@
zTO>dtSV#gqsGz@Q>BNVgWiUAoOFK0>v8UFC@GE3b1O*(!VB8sv*6OIB8cgk2mc20P
zH&P46%QKDRw|11xYh&1JsegjU0=&rlYS8U-(FE#
zQ96<`f1+{I*2791Ka&du>=C^R(Wb}_uRPS4fXaqfroZ0zWiI3!*mE!7MR`m3Ix{+K25
z^j5dN2(Ig!<+r8Kh`V)e))h>L<)l_OV@WL?T`LKiY_QZ;t+VTEb9P05H8fsFYkioG
z<~X>pHMAx(q4L2E`r}_kZHH_|TgwT&$;g(xAXCr_nKVe&gWZmAh(eqEtEkG-X=TCt
zs`XzAeeGyIkor#v#FhYaKJKAXz8
z3Jgr(zBIxZD2PDC%s?U4`CL_4c5K>11vxfKuvXctn&TH46+Ikt=TiKJm$q)xAX6lr
zD454i_F4toGFv+qnKWmjS~7n*v`Aa>?oU$}$&~tp5WB5l;q%G9TMhS2RzZNOy>BzA
zDn6|?5&>cZvIPPS0|GrL&-zMV9Akw`s1%nV1NC*(iE{tML8$VofVvyaS~%`U&xRyZ
zl;+X8#!bf)`vNluKusxS1XW{<;4Ir@`3K0D^DW(vRt>_Rg6JvPCh7NNkxpjkrh(%W
zN$tdGq!tf%pV7>CfLoy*dS;J&Dl|RxZ=2!Rn5FM8G?Nu2uCqM-luw*>YJM1YW=K<|8tsF
z4TBK<`EVwFz^j;ey*%bLs|zMOI(QXo9sMKkc%Jqv^tO7j$?2Zu)Z}FpVh?#LL)Qk8
zs}wc(eE@*>cut~efdG&4?%#DjIV;yhYsXULaOb}cz~xC5ZHyQ%UGrX-ZfnG
zwY111_*|#0rf5@`;HD28p2o%yFdE4WFSvHnur-Q)ZFVp(JQ=KG&hcd5U^e6o*jEw!
zyfRo&awJTL{E#j!x_CbTcawflX-@xB-8Qgz~Wfc|M9+y$b8`D&PHlT4+QL6$AD
zEaosmNOJ`g2M7&?X>&qp?vP0%&FQn{1BKK|e<1s=psl|V@AT|sv>Ik;_b>3M#T`P9
z5s0U*KGD!@qT>l`*y;E>G?gN8H%T!md;kMBo#O8jgW@wyLbT{L
z$8;xiATtS9b9sb@#N+vlhn?=_I#J|+3Vs8G!#GW$lXUAl&>w>G$T3Pexe!n|M^Yao
zs#X?L72u~?Ue8p9G~k7azvBgRFe6eE?})7tk~Z9kZ!aiz0z-ktUC!@YEfDCRKJe2X
zByIGR2Ppf7hfgnjU@Gdt1{LifXG$|n#68fMRSd9?~U$84~6E7{z<|}lnc%lYl-wU
z>b|5=d?^}I$&(=z6(OJp6)})77W)m$>{(#!;H3Xq_xAFz1;#<
zfk9uz8cREXG9TE!7|DA#I8qV7L&HHlF39Wn>iX-f8!+L$-RIpJD&6=S@|qj$Z^t
zjlo!6F2OFSj3u#*@X}E!M4jX9V>nitr&^oj^`LJ=qrms40zWY=4ynvuIwBR`t#jUwYf{TuZ0Gl&a1dP(5XL9fdku5F}e~SeS;E4VM%L6A=HI3p*
zv`P_OQyeR<_8%AqV9gjC*2`-VXs|_K{}{*I{qJCdLwGUA7S~e4i!G^XB7u>mLhBPh
z8wIRl35ZWCh&my}$to^|Hmih6qCA!uvjHU*8G)RN?Y{`_*JZ_$41%|=G|-)P0cpZ
z9R6kR;jiT6`-$_c8xJKR4_~^(_Q&z5TGQ8N9Qn{TZw{f;4l66T8fjx2UwVPlrei&V
z$Cd`NTw+UFV4eDsCokUbp4LCC5@(ZWY_G;=9*(%7Kxb(CCc!@Xr?>|q0sEBb8YHF$
z=Y%{cp(>PgoExLt!Pqg^1cO-&uheh_`5Ni|=zo1?-)XrvTUa$pSW##{fjo7(qT--^iXDhK7v{SDR&XF6DVb@p}uz5W_a8_
zKF8S${d4|NzU2BaeRv?_(Gs>yzLJ3BrA`bZ6}mth%8X=PzvT43NUBCRi(w~#(Go^c
z3SnSV01SKhmsVZSKfdDR#ufm2hD*yMDWh&n$lp7YE+zSlft)N_8c*>I0?iY`P3_R!
zdVh~#g38g`ZM|m2Uxegxh#f+GbN6`b3y5})lrl(+0qG0k;#Cj
z?5+;;5_PT`kjFBV`DcWnHXO4CtX(SQ$s7Zj{_%FwRRFyxf<7p9=H>j1IH
zJ_ACUK`3K{T6U4+7Dh_Fj
z4BeV1P7pkWi?~}%StOWzAz&FslJP&QXDj)3BK~DT^!XY32gmDQFVB8FJAZ$Me^SGB
zvR;Z%vsY8t=AgRcy5kG6C-AV>pZSrPBY4PdGLu>k`J_ctW8YKr(m$eqcp8Zwt4!%V
z&GO~e(Mh%P0uwZluq)@5F&Xs#XFQV`n$8&|(uMhy7>f~3Y(={;2|4t8VF^2}HQuA)
zJxneF0|gPmY=7Kn?Tt86U84WN=Pk8_dra~E#BLPPY3emkWn0*PBQ90^A>YDgE5{b4
zkB(-Ff7n7qla^}-Til-R4=W}!1RuO%dno!(s0F<1Dvne$hhWR_IvJhEhfbV}1|y_%
zp!nr)?K3~NaOU@B^su=57H3j6fUv_uHK*<$Lwe9Zg9b~JvV!67NP!}s^@(udl%#=U
zNaUrxlh)bW-aB?oyb{Mttj-m}t4}H3V+$+)1N6if3;h5p~|
zyrO`vY~>r}k`_ZPQ!G!=ocr(2Pn!K+`xN)6KOAJL&iDws!wuYodC2|AX(DvEJ!a(%4S+gX+90p
zMc2u)IoMgp&?k;43}MN`iXHY~%nmQ($SS9DV)WLTTvw)yY&tB6?tC=!K`M?A_wv~fa!U&4Fz
zm`X39;j=<36Bpv#j*4`V;E9Sfc=V5s-0DvLZ#~cl8m77j&f7PP#yR_-V^UfV=szX~
z_km!z_-?fBiLOmNF`FbAqz)!kCw3LrzP$oLY1yz;@(wuq$MJ$MQXI&$A3i^QF`Bul
z-~F+DAydTj+aFJ1X!1Mcm_hY3+;}+EO~ohj{!3a7XLxiRN5aOBEpZ3;Ieq5ENM}s_
zpo0#3uU2XY@&JrO8}PA4mux7X9xgwtt1t37aiA}~eaB}6y30$?K}cg3QG=~sQmM3V
zIpGJGeE5lHb;w2-UNl5cOig{IBGe_HXmx{F0nTy`CZXdwZn4uzg-lB@aw9lbwRiAj
zLo!))t!sq%N1};3C9jp4lr=@M6zFG%Zh?(`9s|RIjr4k_
zEz@6ra2H%N5CR5>T8MQr*$OOz(SlIDqvGW
zf6r2~>;y5vL0Ec?R*&oyHo(I=NN~P*JL$#_DP@iN=u~Q_4n2#m4=4um$F5VD{-b7rE|
zLdY`A$Nf&XcUBgjv(Wi^dXGfh(&h`zP>QokDWY{eO(bpV>*9T_#AiW7sD4f)kkV)AUE1=)u$AH-|@cJrjwuOH(H
zSD2I$s##dL0OI?kaP??17>IR3qe^Dx%8$V)Wd+LPYey=>T6E+)Q^4bBL(hdkbA@x%O
zOr^G8d6@w);U(2DVNfPGSzRg%Olr7Gq)lqXp(*`Y!fv!p%aSK+2Iy_WNpwvFP6v04n
ztd4~0WD+~U8PYbaCyBp0y5~M#pLPYW@V_dL-|e$)DUHT0pU89Z-J93!O(a5-9z|vi
zo6zhY2PyTipCI~_?^W|9GKcVNH`sT`?h-V6aFy;vWRsE+
zAMD*k(p%`xI3Zwk%6APYz8ldRQ+51I+Nm=Pvfa?^R3aI5I+5!-hIUN%Hg@@KpU|?q
z;ZSu%HW-Kp7?{!||KE1a|~8>91PZfiD@FOGw;D(EBwqltet)`I^i
zcDvo%?_+ZM*9-(k^DY8&Ye~GNAvj1aJFp5C#8*2j8a=u~f8?%YX1uZZdSIQ;TgJ1I
zA^R~CJ}HiIQC9;|_!g3mQ{+qob1ODiLUcL7+1yDa!5Sd3MTz&kEGdDC_7v3Z8<~4@
zx^Yn+x142cjFhv`#>W`iG2M7esK$->GJZhw-M2>0VTg{
zj<2AH^ceGa-LyO#DVNjJKWB(Jns>#QYu0T2NGVn{4oA>cALS+e!17_H%zI-c{iQAG
z#uE2me}nUiZNZ2z8jr4II3)JK|N0v(R?+hamJ{Z5PJu|KHdpTT`NSN)z-R1$kfN2e
z|IfusgqiSRM*5-XDz
zs$OG3Up>W;+24`su=?H8TgU6X>}rmd;88FKy_|v$_#fdgKmuo;M-IkBOD@03iskw3
zwa0IPL2o3#HQT3T3bQ!wI6fcpC0w$b)Q3Zu=Mk7aqBL9d3mJiq-jekMu=t+R^|BdF
zSyG@FRk!h7<_tV~iz{F-!f}d+Pq4B8>tR8`n^8A`mX(bLY$ANrwAJ9~mIDT8ta6Hq$f$RE%4zkE
z-ol#R>6~}kXK%B`#{Q}{rj|^5CP|E>g|JXT=j!b{TK>0e=J}6!0szEwBjlrrbX8S+(@np9?;@t#~?VB2xntJR3cWD
z{NNPINU4yAxDbfz{`}I0UiHCZ!SAQCz3_@ImC%SA=5n|;Bc3l8cwL)e-C$mGW_ahO*>aJDhY3P7>A50f`VB_h!Di$efGEBOp3@g0(cUsDb#spc!*M}zc|
zgv=YMl2YTrHi!kihz4S!fKCImLjhG_aBp2yX|_|Q@fP|Acd>br10NtR$SBQDE}|$p
zVbP)YH7MoKkeM96PKUUeBH!?m%rCi!qeLMJDl>*-U(sBPMeU>Q;u)eP@2Wf=7T4CR
zuQhi%Tx|7&E=G7N+v
zmuDbWa}yL+9JNJA#c1Cljuj&c-=HuPl|P$~2}su+DnZVjz|!fLC1K)M?=x?MfD*#)
zqXB2%Lg*^hy_wQurL^NIfyI-zkTU%*32O9%d?l3jLz2;>9lGeHu#xy_M0|s+^|*qz
zzf=EiThy!AA?sBHEP-;{1bg+$&QV=%n>!FkdQ3uku#AIBKAT9B8Z5SX3l0N}(C_tl
zFaKy1r-_mEf?nRlORHoVLjQ^2aY7e{Uz$E9#dpzBgC3-m$Q+L?VhA<}S^jG>WV$go)U^Sm$6F)imXRF7`edcMXJ(!hAq58Wb@Q6HzgcmSIc2
z(7)OMQY4J#zb^Qf^3~RSOqYbwKQ=#}5kEG@o4>_GT3>0(9oEPI)unASqb8aTD=O!g
zy^G5pye~f$m0YE$B-KJ&WI09E4(&2F7M=qeCz
zsb}#+;aeI4`1@P>{ubXQvjRI{3dzC%^#243D4i`J?TL#b3E9$mFvUuSMGO7A!o{nz
zCq;~_12$M$#F_wMNS%^b%01`_3wd|%8JR?|FEqzR+|Pfh(Wu94~?6*TIYfh^in
z`NA{d%z_226$U_o<}c$Y*98kb73)eWbbJMc_<^De)Pq5|Pr%knp|9_FZSum1Ke
zf*2d!qAaDha^9f*G-T*5kB9h}J;Y@3LgYsrsfX12X_jT`4OXYHy+oVuKtiPSQzfwk
z>WrHDS)M?GpQ)9;qwb^^vxPIgltXY`EUzV8Pl|^{?h-J3K
za;iV!8j46cYXs<4q^3j4A{AZgS~UxJ0W_WBTQ!m}2@c&zyKDzfmwR?uz0hYp}ZelA2TsVoGcA*pQ^iC7Zk$EeT**
zgNgp~Fl{tE+P{%%SZ(06w$zkb_~{LZClmeK>%=$OWf8J2$gR{4vc&3>hA4;6O21rF
znm^w$0_o7r3AN8-KfwV5CjS$pIHUEX%C0cTdtaQ)#JbK4gNvG-oE4UWW&jfh-PFX&
zd#r>0(XvM?Io3SgL4D8YPEy;tJxqzX2ViNLa|lWkX9Q4VG`aUMQpX*kzyq7-@iCs!
zJo~Z#zSDnOzp#A`IsOg@H2L#>d$@tLAQw1h9X~(!E1?Z(`JA$84QMkP7DF2@kNzdv
z5Df_QeKF6A8?mGVg=AxSKm+|lzfOm=ys*Kb&w9D^PK%tNf&TNt26IV%Nz5ns=s&*J
z_!|g5`ln=SbY7B~0|=Z72!5ye>j?hQ;QALbflpxJ?r3qPvCheoK+=j0V#1z9sZ`J=
zhB`ZVub%!FN#k@aDdd_T!L$iSoK<#cIHtj~8R7hf|3#HsIQ4ixh$hn|
zrQA@LzI+`==4;{iXwBxv7en=Jg24<&VX~LYYb(^PvQ$x@d|ev-?_7P};hWR+q%d8k
z#U$~@C8af#IY0(dkV%Qquh;WVNd@r#H_@l~ju>SS*`oB6_Bc=>e)W0FvPt3}*>Tt!zZPR^^h@lS611
zo@Aon&0qwJ4!cij9jG_GUb;QFAMR;(Xi%xfQsqU~K#tywRbSa7JB@YjIz2dAe5vMs
zME{tg>dY{)ekp~`8LCM}HFj|$)rVAa`E}PZ)%MA%Sy5Wj@WQmkznVt;>=E@3&l6{%
zlq4BQG9a%ga?>o~wBg~ow0(z6Fra}P8L8S*0VSW+P^KG(3a=eK+bXe9qBM~k{lm4b
zsH@dnMK2s#>6T!V-$k~aR7L_Zb6m&axRBTvO3T)ena(N45j*9fx5B3`PXva_ByP0+
zFr;r}BWA%KrKqf*M0FiD}t5x^>QL;5wrUDBX9(`P*sxti!Rj7mF
z3$5CE)gIA5_L6g?2xxWiKd1GxMoXNZo%|fsv?v~x6|GJ)hhmi|QhDU;X&r(|MIqp!
zxdoKV2%|!6amYoyo4GDodG#tSZJJ`ugqEnS8Ek(^7Lq$ku#iOs{XNqpV&&3E_9Io+
zpfx13o*JKJG%z+1kVW6!)cx5*wyG4cGw7B)J4132Hqy>O(L3}KSsVa{Bs%&6rWP&U
z=dPl~rwB#?d4i=w32+vB9L`AubS%8&8rSjv4Z59-_ivo+KX|~3(z~it+Twi&N&MLO
z3XsNj2*f?q$wDB2qWY5ZP9fQ(&Qm4+6S=5P-~E#hMVxLL+o6Inys*q!L)3FcGdMza
zsJkE3kjLl%Id%Dvh#%!sE#qi%ySP&@$F2%(kf8n(r(afM;R-p?@hyaDu7_J~864(}
zK&@_1Y{{XJ4)5IuQ!L;reD&97ABcw6l;LAEiv
zj}!wz6p~M#OKMV1EOJ!IGcE1zODJZ^<2w51L@oY-9bMF97nak3mLRi7?-b3s>uF@R
zDji6~rNsjW=o*qaB!D~T4+xRst0ar#`g^()2E~&#D7Jze(md`-t0VE5Z{c737u?pT
z|CNy?bL?6uVVI;n5r%_19k;Bl{cZzf?EMI?BZnE-7dj(CT8Qk3
zYC#rnGI8**WR9NDN`wt30ZYafHMCcg8>~r_41r)Oqkm}DasDfEQx3#|I}6qp$PenM
z5|8jaPKI!_;6FGO(2%iq9%s1b9v6ntckDP(kca02XgSLMsXShjb!5@0cekKqzIbCE
zfpp+flb;zd4KcORl+i>fCh~AW86qj}1|X}HuV11EPynQW=0i(Lx{s7BCW}ov{2f-u
z|3bzcscxd!2p8a!vQ}V)^>lZtFZL*vLqd|}1CFQaeKPit+qbws_{S}o{(!MckHYMYM)tT&;M7zUoE~F(393+t>5N-=p1?pT{eG>q`>t5tl?Ix
zl}7ELT1&Z1=ApONNu^`aL4mYSiY+rgx6kzFEM>Q9yYO`1a#soJxQ$p>HPc|g3YD%|
zchs!Xdi0iJt94<}%;>^?4NS&8xEe`92DCIlHf+oxjTI>
zkilyhsVGy$hWw$ZkHP{Wb#rym>G>M@yph|cjIjQ!FAeZ=%|zL^C-v!PBX*w_K8
zy$k4^6!}Bh@M$UGKjc#QOrT5O5i5dkAQWYbIsO0Hd-tX`k}Q4r@BJ1P@kYFjXN@h1
ztG(@wpOC=jZEh{$#xolm3LymO*C5f7XxkI};os*ud8y2*tWs48yX9HDJ2OD#J@cGA
zm*Y0l)gRJAx>gCi4
zE$_4vEXnBTM(7l)wR6Tx2sXZSG2t<9xde}yX6G_4uma~jxX&y9gGAxP8YU%*ItEw3
zW(MvqPYvL$fjVRgV>8>VZ6Z1_9AjuVkgUpF`=C$&mDHVXwl@5YlQv)SgoRrAK3Ck)
zy_n5a9xSX5Sg5!g`Dh0%16%6S_mUKbS9FyxeJ4+0y=EiXyXx+Q5eY{OCTF@jl>JK^
zrFo&KKZrj9{8(9F@O&2BT>XKu*BE77U&a?lN-R*gUfi5oC{Pbu!=OW}J`Sa%Kx$vB#|4^F$bk_G0C)J8}1lcWuuYs52>vs$tN8{-Kj2*1Ce~pOuf<|ScXklSm)QCF>zS`I0
zYYxdVxoxY^DR?JM+vs1gY@s10+7log;cqO9UnXODzQt*zj_SML>f5qSf-uxJVhM?kE
zto;tIi2ajS@^#o#AKo!kLj47rusQWc_5cT_!5}sdqyNRa)HmXiNkpR-RPjhzy8)+R
z)qfh%sMtnJ#Gf;(a^tbdi}OzJC_2Rnn$l7s1&q#&Z}eEO?o0bLfFh8fSm@oTyzI3e
zhGo@09a5UgCxF1Ld)Hze7Bt-!EtP^U!$iu5dK||gx=>V${-1(wxj2eYTrr5=RjlYc
z^9YM%i
zI&N`D!rj97q&P0;FWpw@qLeEaP9l})FQ)0y4FSZ;43+6{_}(-PD|j{7jIe>)mtnSV
zpsHz1;3PeV
z8_QsBL?r{Gavl=EOEi2C*J=xjnc+r}3t{cJb3u#mai@bg`7?y@h>M&6O$bBgnH-2>
z^0t}sHO$llciQ}GB8nrT-L)~-n1(~SC$0Sec`ijR*~l$b2NF=pL2o5tw|GG?L&|A!
zn8lpaK>v^)`6He^(>4+%`Do{fT?2|+gtRLy8bX(~&mcmybAi~<4h1m^sR~xA#a$Ct
z(msRcpK6rzFVw8*BV^s(fFFaCsrpa9qJULsLk0=G-IjYGkO@V+1CEIZn-ArhNK>&+
zVcKXLrw1Y|4+}&c@T-Pav*Z9`At=-^@Rh5GSZbp#pybADC|y!aZNJ$oxL
ztg@c!m;~!FTGp+5fU_)7Ug@{^(n@;TN{yMhX6hW|ym5Xb9wOyH!~D}OG_G3jtl3$c
zAD^~8UmA)hZ8ho?R6>L5Yfahs(bZc@QySeYt0~wa5I6Tiq&oZnJwcxp;{;&RO~pCP
zwom|!eNtTbR2k2oh-oR|i0xCsVDHwW$W;h0haz)OI7(Qnnjdq8P3Bi9xND+P()=f&
zEEkZ4{zKITPN5B={O;M4GVG)F8LB)hlZ==8KSsw*X8-sV0FEphY1s1QUFyDMJs*t7Q`c2IpDzUu;~(Jw9*YNjYqt2SIdg5#~A}gn>H<)B$)mevxfd
z0ZeuS6r0q17)*R{+JMt
z=1!p9svAL-Q=7TD6CH>bNg^`qW9Uf7TM6>_r~Xeo_3G!#pTcGgW6Waf2?AAZV^P`5Uc
z=vq>`0}sJHvT0nQc`zgTkzfokphNmWjV5o=hwz`;pGAE51*V!0D2byCgdywTCzOIS
z6@92*H{}_2^@k-c5;`=@aFv{%|jpHcMj5~X*Psl|%z=uu!t1?`H5XU6a)ZE=4E
z@(R^Nh4nvv$DKz1xSL(uK}cLPJ6$!7OYgK%6>#twdI&$t6*3Wl78NNYL|;fb
z`MV&xk@XHo07f?j$QlZ{E9D%QtxhYh$kqg8`CH1F`eZuq9JHK$#lGx!JLV6H5S>3@
zvjm+>1M68E_j?xo_A?{5SSg8t8V|{|QWdir!z-+9yA5#6Q}ncGRfQzgDE>90-S9P65+QdN>8}we?`_+iJI@Ci}WA1lofpH3irHVi6KR9SUGYV
z{=?1MM!u!YFr`l+nb3UP&;E!rpYzdt$`vQm-aOOqCs&TM0%dmj{b2dD@l9_ThVICT
zw*9ogs>{2j%S)BsOIzWMT4kxyd2Fj*w-DtFv7R9#~
z0mo3nYe{KP!jNOomH1P%GfeJr<2BWOQcBmvAd<6ccB)t@`ZrI`;K!t$Zd(LPcp59R
zCa9&f4yATjOYo^JuC6*@j2XHE`iJ(wB)W94nx3V&FP9Wo9!hOG`oDqi%bIwXPys4!
zI{J6E9q#l$M?fiuBoMpX)qaVRY^57&jEOy$i`hC7
zp>j;4RAa?Y1fmBaT3SVt(kB0c{_Wo=aOzT}PK+OfUGBV~e^+U&bYcQ*!sOOiczRmh
ziiZcM$9c9h>Fq1{L?CVzBf~I@kg|oYs9On>
zc4d(QqDT>|SEH~=1O2CS_t@e`JFu?3T|3
z)bpLRyN
z_x!DrRXrOx%z6L#wRQB8|J@Zs5Yc~YqJ#0z7ain5Kz;(6h~5wTQ!%a)Mg??hAtnt1
zIc1oC(hbck%1uP(_zqlyRGK^cb|^2ik$L1Euu}E(4wNLwjO{nA}q1!_7*ErymVP3{yR`gG}soXI^O}<{}qb%5V!HZ--Rt1RlgaYY@A>JTcrkVLJpAgk9I
z1oVw};sA$$Cyg1W)ZdYE3Fry$PiJntPB`BwNF`}me$!*OeAUASx|gC+Y_@Pf;v>NX
zT??~8vT7Ym<^0XVe#UQd2oO=;!BuyV{2ssYvL;|Ui(JICV(cOUlPR8gol~`@Jfv*<
z7PjVN;4*_4lhWUs0A0H=^bq|+!gSn^!DO%{1FEmIoc&T$AurSiKM+v|}7$1xo1|$Zk4kmI!
zEtcrarIyjet5@nLz0?`8;$1({s2uPVx?N!J#&S-1C%oi3>jDmaGM*btExz)si0*QE
z7)q`)4mA4D%HB{p3cO5O2lNj@EuGjwqQJY0!m+PZFt&30*~iRWR(6j5!G^Gd#Y4dh
zDXK~YUmR_X{;ld-G9wbIrtc0NdRvMP;=;8rmt;O+x$X_V6q4%%ErBqi9pWX738+zP
z)b{e_y7bLw#4fO2YYVarHtVCXgz!hbI_6`pG*?RrSb_05GLsdu(%DzzAr~*NW)UjC
z7Z{kCm{Y#I4EM&7;WD;wm1VfPo7}Zwy%_UP$4tH&mV^Y7dwkYC=Kb>xly8uX$T?^o
zSyg2q-}dTsWE2{+(EkHp2Li+`HfQ0FNybsHOAezRmx7N5Xvhj^W(Emy`vA|
z#l{1+h&ceL@^*5E3!hgZ)`hUR=|~dX4XuVWsS_&JXrwGEG3hi1V`!IzE&DYCvI^E
z9;%T>HP{+m*GOZ#NT*GpLz+f2am7C#qhKSt8IE;sJgPl($-h26Ypwm`SG=-xH@Z}r23{BvWmuhl
zwz$3b9_;PaKmX`S!5$KKPeID+XoCLzMkYk#O>Al!l#(Zq0K-s
z8?W(Sn*l&q{4ZMNe|P1-oAL`Xwex0|01{mJW>nUSG-Db(v}pf;zGC-)diVDV@sGeE
zO!y@6^p3AsD?X8!ILoNXe@FWM2ZYr9?qT=*l#yJ`4&DSV^$!;zjmf$6Z5D?sf2<$J
zQ%KXUdL3Fst3u=vq*3(mQ|UM8FptvE{|yeO6Kf;{910e|>B2Q9T$RR(s^p|s9fy@E
zV#W1gi5vO^PqO^ci*-^T@az#?Sn>rC8YhqUmuLa(Esm2tIX%;$8PK7!tn_&+9YyZ_
zido|Ui#xpW{KAl7cix}Q?WId%Ci_%=KM^5I$i$M;P~BT^(?~!}9Q_ZcS&^t=LzlN4
z!B)WmTqt3la~b_V;>tG*>02qm6|i7nAw^reV_Qy^9K9VmoPhJ6jnW6N`dxnx=H5Fx
zJ$c{b2`K*$cYRI45-|6!dnz}Tq+x*WauUf|tDZ!_O%o!Sh;ecdu`c*_)SnM-pXewC
zkf@ws#@=#Yf@aoIyK9{1K2s^Ox9Hz@q+_h)IkLOm4}gYN+g>0WWplB(E%gR`EL7Lf
zX%VmCt|)>4g27&>vk~qxIthTV3`I~6-VsBMA_s=oqBLUosS!>>-_y5Ts1!SixpJt4
zM>`^IxjLs~33O(oW$vIU&~aKiHSGKy1=6ai=_-LGDONGDO6f}2(Abiy2k0+c
zx(*M3wZ6J_;&Dk6?gcj&Ciy;-uzXYl#cb?w1$~t?>66OT#yB%uSn|w&+n%
zW*DC!ua7ADc!h*SJq`;thj(zLs>P3AeO@e$nDs~hDm6JZCOa&vV`q(v!|r}0C{puu
zy&a1D4^PhbJHIu77MCFvlT09uyxFPAds(3?tBx)UU0DKj!EGh~6wswnlcw{otmJVr
zS3#i}n!
zHADJ|+2Z^{sH4-gX$?wiOk?DGn+>OPJR!{Ee>Gfpe!qs*Ks`nWbmV+Gxr->u_wj<9
zSQGfs`+&m=dj_3T!wByMt}|7iVlaH85Zc=H9rDA=XQvmxSIG=+yOlHn4AJ6WytGv`
zo6r{Va0`p%I;^QTW2PsA&@P@aWej<+3C-i@kOkuiZ7&~faAKZ9OlAItwgr{Z%kMoJ
z52izS_|d=WKJFJexF!EKp3WVHvv?D6IGo-KFvjkZAA6-<`Rm~;y=Uj0qh5Res9E-5
zJ{|Pa9$q8QA1=n*Ar=*je?96=ulNQZ-fwyx|K|MIQyxi7+gOUtD~caf8Um=z3ST>;
z85DaQH;<|?P1DB7Szv`~uh<7tl$t(819ujIjo~P=X@R_Gw$6lsH8x~dD_H^s>Rti1
zyXrU$~asgVbtb
zEF~Ay3L$0RV`l%JgaVhb+!)2!s^toLsyL4Y*sAk%Gx~>^X=nma3yJ;p*jq~1qcUy6!QCAbQ7Cpyon6oBH9gwzGH?+X((O$e|I!vrws6!W3
z<8~NxqF{$v8yl?YL+Xu3D$8&1E+L_RaDm~_{JIqvu;O)x`R6(Kk
z_9GV_z=0_$sCP$FLA1qibDB%iK;OW>)D0=QoTwk#H`@hEL(?4GU;>E4yHmH5M+61n
zH5FJc$@qS%{X~T%7E3?hjs~~5;o!Uxc)-xshU~5pJgBSQ%T)noRE4S9@^-|nBl85B
zr+=kXTXRqOBN0_LG@Mr&_t@!=Z-#FpFflwb2NTfN%V=9Yz{<$?gzi!|3gof8m|d3J
zQgRi`;rH7=?l`W|(fli*MQY=Dv&Gw)JxRQuc6h>v!OKpwz$8VC%Q&F15Vz=@#bS_hCM-B&66nUO
z8V_&$I-A=pjvmC0&jyMTOF%F(PXRs~U>4X&-Hvjz^Owe}y4NWBj|EUDfNLrPJ>35+
z?JkwlgGpQv%YGA60|*wRs~z3jNj`)5Y`nQ;99WsGZFySci
z2{s+qVV=(9BQ`AcTpW5kKh|oIUMjGh-t21n4(~gW{Od-&mc~UqM*nz{Q3O@|m_f$+
zN-J*(GI^-ICmeDtg@PZ{>W8ruD$5}0^9pHGdxN{*d*-zOeeTU^#cDr}=c7AepGpD3
z4q;m0f?^-kRy~bF!I~uOhnIY|ra%2kl>+Ao|ABTS3GwxU;bBFN&hD$EbmCvK?S<@L
zEQWYyP?&5=1B$tBA$wu=HgS%<*3mCS(=_*viU-0}-lmWZxAab3kEVc*VpX)rOIUc(zqRq=kyYAwzvGVWpOo4#+>eqRl?O4YkJK@fB7U4V;>S5a
zn39{Ijn4#SrbZP8lepWBOz$Wori8s1bIQ1^C8t>OXcsA}*3^{D)j1s3k>a9e3P48l
zW)F(vnU&&sJMy^IQ`}VW-hz5dQL1KYbwah>j5}Vxwzgg{r*df}!u4}y9IaJVB96{l
z2k%|L{TrK+9J{256F;l8#xJNd3HMZG?>k1y6H26nmw
z*7mvo)yG4jRW*4fwI7`k0b3sLrbBzJXe4?NMM>TWSg+6h--i%j^rbCIRB{D4O$t#6
zSseoNj0r;=oxZPDlQYVG;}gS1(TUFU-Zgz3KjC
zgY_D_?w>aCr^eQ{`=>4ZX{+uvwato%J#dRLUnuI9u=+zkVFw!I(vX
zU(AeH_!SI~{>QT((({+mmb9j%LJ(#`28^gz
zm}!BPh}ReCC9eP&|DB_}dYtlqk|#`_s(Q@?2nKYn<7lq19y~9qkHCsxYGXvWfCU(6
zhXX~-Ta!Fu!;0*mlwA$3oL-SK#O9^2T$<8w?6D%uvhdeX8oEXQe;uXOH|prWG^L@A
zt7HX4`T^H}_M
zyfko>0SlucCcY>OTpGCtLG$@?Y#v-q)S3!>-Z>9Xb&yMr-8sk<)8hLH;PC6w&7+FI
ztl&4&Pgo$Q1pZIq?RMa`sBdQG77xmEMiDZKT9EbNUd}J4ZmawycFJe&b8EAK-0@yI7e{;PuBlp6t^#C+nc{?j~OqG`ED?Otiqjx
z{rSqFUn|~(&;%FshkbEsmD4BnFk-hwlwciW+t!#O=FU;i5E$+e>z1;
zh3hi=OclL7jmn6{ETS|PUkWg(lFPuw(qP9zH!lVELKf2aRS%@;Fex3u*Bgs&-q5}V
zuP|Fs&)O8qy~KR@fN)9Mj&qP)#%u4R0K2wz%@~$r*scjs-GQmKTUCbr@vQB#>!!sK
z81sm@dJu7c|9Btu@8K;%5IcMnMA#Y(flkN4uzUrd04}>H+Q-ekoMNKDROo=N
zVIPa;ujPNx^nm@6HCHu;UmixNCAQANe0qlpFcAMiW2R(Wkiddz{~BOu{_Rq~E)x4I
zX(Tlj`-9)VuoUdML!d2T2Q?rL1+J4UEI1k1bRIo9118IhIta>(eWwhk+H-w$B#wM9
z%Hj@_)pJ9C2)CHPatwQ*G>J8kjt>qGPNRp3*xAIvJ?LZpL!L1~g%0`;bH4R5oK7cG
z^zl(nJDS7acx13J(xP#yx*2JZ1Oh`i`|bQCfCfw;BL{e{2Q`Bu76D=EfFiIT*0=lq
zcp!jUA{Hen7cl>h3trpkdD1lc->j;P|4*ch!D&%xW1{;ElA7Wy+z1Vpuobx5&D?NU$)kGP~N
zn?};7B1?f@dl*vh__We<%z7zg>>{k(jsB_PbPNs*ZaB#>raX49q6=PmakK!C8QgG6
zIz3xOd-vS*VYo}?)6vZh_$xv^ButO8(H-)aaVaL_tbIN_IYbQF>G9do{`o%qB*l~>
zDP{HN_Tsh6DK?qO!nJ5U
z{eYaM7c{;M$pxQcK|fEQd_gZd)fRM{3kot$;msQOdm$F8MNlL?wec^c+c(({p9xGU
zeHaYWGwjnpF?xcgP%dYDnP@Yg>BrhX!*-{`zjq(L2Qc{-tO*LYelomRSHb=dcmYSJGW#NeSA-_TR
z0Cr3K#U^-yjpH04@!N4{E4oC)eY4)sqRtmUUzM#BZ|8e&N^4yLvIL6DA*G*>@9vN(E6t}ptB
zB4&(?=xQ{EWroTTOeWZD7<-O8^^O19`fqJV#8ONi9wsy3$6y@NYM}=37
z7AJdkZk3>no*YQ1ylYrd<<;1nvSs9P)r5axCAB21>PlW%O>EzB^UQ($Hfr|DGWkV#
zmwY%pUwI-Z(VK%3IUlA7NtMlh_(w~w5^W;UhY|)Mx8fw)
zKrB#t&}3}7K+Q8Ym<8(TA9}F6>>Zxh+#9LD&v4JlOG!<=gvb4d*oav$f*L#X5|X{>
zdNuvHiv1<5glCPu2pO`6pMMs+kePhV{9snW6%I>~j2%{zXi~FUWukFhW$@$w{QBWP
z67_0sz4CXBkID${
z$12}7j={81vvFDL(ZM4C42V!i?$s;AT2X_d7NhdQd{Hpake?7CK}L
z1m?f&knIxtQShV{I6Gx^J=!&RaRsIAf*v*qMj~xXK8Ko-wv~k>U)oL_{4FCQyK;1*
z%w~Zy8wJW(!9GtMcM%L)_D>9F%ax9?mik{x8c$T)tX6HKS~X8)C@;c$FByh6d6h-@
zjo2;NsM$c6rJ^QPY_iDu@jWC$&~Qk
zERg(pBR;8dxv1nXLcm+1sG%4AfBWtI7VWH!*Bh@Tklssg@e=vLQo0&*sgt&vq6_v35z*t)-LamU8tr4|_mKzfDQfI?Ev}
z^sh3qe?!tTezFi@q5p*Gr4Dl|65@HAvK(m{f)5cE`Y%9QyDr%j`T3iW*3Q$DmQd>x
zlNQJ|DE=$no3=^qEI~f{G2x)olcZ&nuDWi|qU3`Hl75H;%iSq*7Thx5xd^I!8yIjQ2a5_(4Qm4t1uOt#j`^0u
zyJ*c-=MsndO-NNsl-Vs%W~V@zZBwSC%9j|Jh*I6o`0-#r(;?VzJXG4LahyH1}2&sBWANx0_;eiF%d&!v6f>`#-?nY}g@H&lYF4%bSGJ2ExC>G%je1dg1
zSy8@izKDi%qz2*ho_)#P%t3933)gEe(zg=&cTNfi=fXCffwI3RLT##`lRqUu1pRMu
zp9PUhGq?O%-WpAHu9sZGs;=abP`NoxP}VHcUcNUk%}?Z)2KHAES?>}@sL{hpm-(j!
zsT}NBj22DIC(5A8B)}qz7_|@LdV(eV4x5Hvk|wUi;*}Lb;k~X*e~g+75ngif7FdQ>
zXYtA%I~-BHctJbR7B;JpIH7>Ho{3-=*W_+(H(#7c?tBnKn%7W0gD+pN>uN!m-x3|3c
zqFt)mCA6Uvhit#U6qrr}|Etm}(xr+Ehh`ZjVi5?H--F(hAPs!Um+neV%#8)cWYELwG$B@Kq_WfOiq3oP+{m$XrKNy~yb^8`7*
zOjAgZ6Ab6Bcejfew@8pnT?8QsElGz#q-U~F5bBvM6vTQa3snVsrso!t+0tgHWdC85
zXj;}w)(gW#7uO5pL>Jdv5-7UuNQoIIX_ckK9al=UK+zn4K7n0_$u%rAB8SPv)<=oJzrkCv
z4@S2X3v$p1xuJPoI*CG>)!~%7zJ{a)Io$128Itj`F8XKsA(f&e+#8g9DCK#|+pcAe
zd+*^$D5(uwW85+u5j1F)NgaTNFaUDbgdbj#C)xn?nKTOfOIg~inQPbNoAE_hV#B&g
z8L}R`Nf+8R{lN!Kk$#b?mPo&qupKfj@%gouvfWlrZyJ&dP!
zDL$^4AHuYVJZ<%@keTp}WsBlqEo;&;v|NZSCe|v-uxX_>CCip&++$dj@8Z+^t2U*q
zQEaJA$*_tgHzms$X7=PexhyjYh4%YzNhoElYD?`&hFLASCt23C|1En`)+}fCB&eIc
zDJqBr9jp*T7TM*JoHwMJCCUU1ZizBMdt0JRF>_m5I7u{9)M}QfR@7*gs8-ZwmZ-L*
z$?T0QLV3nl*GUU<}#ZSwl1eqyw=mE7SC|=ufHkf
z?bFraWEuA96#L4uOB*TbUryUdvaj+MZrPNe6jd*p!nYAfQDbk|JQH_v^ud6|WT9Zh
zVzN*$WHDK&n6W%9N+sI~2Q4nH7miw7TrX^#UtDiV<2dr!zr#R9Agew@*_rY{$*gw!ea}CR5zfWV7s>iue73{yHjX4i*Q7@XJwh=qs5LXgg
zm}`p^yY%RdYF84=8feIYH^0ZEwGj2Jnzf
z?F$k(NioyFwywUJsBSt^)lp@`8O64Kmu8)gF%E1i`u7MgOq_N0o5y=c`}nQZX{p!$
z+&{mAlWeU%Z~daz26>SB_m_7=47d@kH3A>vcHZH%tubXHT2@JM5V6Ak?e7|5Ysa~R
zVRSyO&9Nhs@fu!MeeoJSyg(J}PEy<2!x-^X@5AX)yR=u16|nk@@!<~3>$XS=IgSQ=
zCrv+O{}QjqPVV6#oIMiH+xO1~&kh`ibAICSkuxFBolOSnq2|vcWDv#+u!v;D2?0Xn
zl@v6U7)px%r$attE5P7+AMZcYP0DB&JS2&CZuNt_Y^42bm(I$oDW19<^Wg@TQV%BQ
zpTgF~5f-(1g!7a0Nmm68-a3$}t7#-JVdq3x-##?1Q`aS3Nuf7p-B*`&a*$Z|t(I7N*2F;TO&s!c_I+
zPU$n0bBNmeN6j+Ne%b@4b8cj^6VS?4y!}tYO~5lqQNj>}(7A}UFBz-@+v%4k+wr&3
zYyh|w7LQB`e*xdo{EKV?Z%kP>;r=YV0sRM=w><>zA0~(S4_F|2i5g
zJ`my#=s&cz80UB95AJ3^340I-!#8ISmOG@+3YNBIKl`Uf7=Zn@S&;r^i7ffQvc!*G
z)+6#0bM(|7&_6%8M=p71m1Gs=ZZ`Cz-L1sC)s`d`FRlPeli
zSBJY3qM=Lb4F!&uP-8FwYJC4r
z7a(kGJp3XkIyR5O=%110uc8BEJ>Udh3W$zz;H&~Ut_kFUoM%*>wX<_`s+5z#*tsKv
zg|~1eWw37R!+zTl!M3dZRvss&L;}U^dN^e~{Tz4ktUs8KCgW%}r|bZ0+3@~h{?*vj
zX0YY<$6pghz8UOv5W{epivV>esk9+J1=_n-@5X>+7^^RBD-*HYBIycimlK!(Z$~$`
z5+HVm>`Rc%CU|N4>kE#K9U@&#|M6~~I}z9prK}b^(0^d6?&x76RBNE0aaOBjtZ&Fy
z08tZ$DGWhkABY;p|4)bb!aVUX0*SQPkM4#y$k(Lo-O4hFa_E1k-o(+(OCxx%{0o#c
z4kNu1YLO`ie;y%+!7cORkE0O`=U0?fAr6WQh?V1_5D%|L+)qfAw6e3|M~JiN|FjdG
z?RO4N@!0N3Yd<>@)iE!#Y~!rRa(Gw`|nR1tm
z^4!tMDF_~~VxM>Z4(rL9tj4RmhiPy8c;7R9p!^G*LQG5c44)E%=>ORt-SuJVH}s=U
zvN^%&0lngT-(nD#VS%DxzZchu8e#tq)^+SQR2`fFJr4Abg84H|H(X;Ay0N-61$+3S
zW`qcN#E_^%loV1X`p=uu2{gO6aIHrBtrm^+j=rMKx>`3$OQpz@#Oh5)NDXPYaF$7C
zvqvy1Y~5r$1bI=n!TLk7(|bv0}AbW(_Vl^=@=6)29joB2|6n9Qv
z4T*bfI~9%wm4EnUIC$iv+p47ZW(d>J2pQI2u^!w^vte&Ox*ty8QNpE12PK4T*uQ>p
zO!HOskXg7oSI4m5ml(ps-DrS?0K-?0l|*YCD_sEo+aWJNn_p?DFb5KsCOPb&&;DuI
z;Nq$!Mi+hYv}oRpYV*%S4EX{#8Fm02baY@J`7I!Mgkq4I4FdIxCFWqB{ZtrHWFt}^ZBka#oGWK7iB+e3>lJlfIZXiIOr$@Ni
z?%a8fIe+zJ3pa^3KK)Ko7*Dc{t|4xKB4ztua>}GHISbrQp(5U{*WfV_D%79o%9Y{%
zKAwEWBcZx)sr4|yj(t^&B%Ppt9%uD;lLU2wn|V6Ay26MPb^^H4*7a(xbMn}EpEzGRmF)cJ>a&~`wdto^
zHtu9g)+e3>E-qMw0ync4K%}nbv*!E#*3oHqzr=0n71dWKIE9>kyv7r6@Jx~qaa%+<
z#9`(+#iAR*M~}0;zxVOI$PS?qcJ>eUJ5VeR&#MhmkFW{e32BTs!fbSdM_RPZ)SrQm
zlUuC)RQm~@Q(lS4);Iy$0DRixW7rKGvVl64?$yHG196V-LG_rQ*w5I`2TGi0xC*eB
zkTn%`u7MU`$j1HFhk=myI*U*kRRt_fuKmW6hON!P8#zv#+9OQDud@b1e_^;Kmi1I^
zgDg1aOIlJ>OZTZ50s6X#8whoJGC_peUEHs(cjDF)YvjP(aPcydmW)z>^+^Z_vTop(
zkUnXK!vVRzj`qGjU~51Uklabyax<8vDSW;`2Ceev_SpgM*EO+K$rO>$O^=R?E`c6@hxPv!{2f?_t?D
zP%t4B1WH(55c=j&Vc>IOnN5jY{ohfuLsNCsY*4WN7v~GioqeEg!?7Kxy2%9zRC3=Z
zRF&d2DpuTGwor}KA|zMRsZ_$+pavTo8#2z_N*WuePhxLeq~^AD`NS%k$C?$#1%IYY
zJ|c&nFmpIBUNjX!$VLS14d0C&fY0K=0`Pe9X;c7DBUw+b34~bdGXXC?X)O$YxqK0s
zPC@F48^K7nucD9R(fn<69^V%QSd^J5QvG#$pPH@nUgzV9ejT?Eb5eygT+)p4TG>_f
zHRLaWPUSwE_vLxL%ONn6+*(CdBIG%rr?+KFHLTy
z{d>7WsSSupLft7>qnTWJvi2N?@P94WwE>XSU^|CEy;e!J}UGYy{F90*vYMWVZ`Mkqt__x@9y@K(CO_^LC?*P)h
zW)g=zWbDPjZPt3Pt}}#c%+a2zWRH13QTBN8WZaSAPF}B8@2}1s
zG0)z`608vnav^uLEAY*jqrgl5LguKj3g3%4sy&OTw8TwjiW=sqRE%m2u|2k?}%lsBM?GMT^Zfh-bVXl5z8_P
zoWY7lW1CogVa2@~(uN{ww8apQX~;~`|HA|pLy*d*XUkC=)@vVjd+lEZG}P-}ly?Sc
zZ5&JQy3V7b+4SF7=Q$)Js9rA(k!3338RITQ@s4hn)l4+$Le
zgfr`X9thL6d}>p>Cw?)_we+jM|(%_^sE%LPa9kX8UW^{H%qSyCUH3$g9G~G!2GQf
z%MRnBWdwpM|Eq`59$r4)#0pixfM%Ra$`6XL>KD4prLL>-V?gBwx3TKlm
zI5>Kcts3aUVI^kVuKCJVMXyfL5)y;7kmNb3rCC*;(>itlEE_eeF?C%}xxM6hfr7H(
z@FTsGqLd$r?v{W2+UgocBerZ99)K3Oxq&|l9D<>0xBV$xHDE7)j{0I{Iy@!G&U=6J
zo~|bFQ@9uN!$F|fdyi4R`sW`#*r!I9Jyc^#{GpN`vsYZr
zFzZ-kv5s80o7{{57j`F%{*zNy4*k%Su^#D}&L-D$&h(|7swBHBI2rVBrsFP*Mz7da
zglMFfPlb1q&BG
z-pLBfuFV?pf-C3-`iGK)37j7}%l^+lu;S67>?)uOHlq6E^jsu-5P?1)&d~#60;l5;
z7H|Vgfqun^(4_9fbBg04{0aT*y+>W-pS)i0C?>l`TP7xcZ
ziVGVStcs#lO~C4`X_qTFFVTNEGJ@$8exR63iq3K1&_DW19yx*oItSekIC2{?rR#w%
zdG4l>dlb-r;4nZm51$1dRa9{$P~5~Owq^eSc)|}An9Vmk2{1|&JP8zc3!jAA^GV1#
z3BZgmdlFh2&F1SQ*rEam0?4e?NW`fF?7wTg$k9l6j9t;gXdFfp;dgzThCcbcFjPXv
zf2ozpDqxq+6eywaq-Nk~FByuCJE>x&6Z0%q$)9@hI`L{ab;>DXoMEhrWt@qXRK>a%
z;Qnza!AAT>g0?{Z@rY+~*RQ^g`}d4*`cZgBLPE0zDCVY
zhtZ|92}~*A{RmtcJpf2Zl&KcjW=H~~-kavxj_wiCjEbs~9tb45K7h9)NQDN!iL)1-6x0@;<#8x0Z|nD;Boi7^XjTU
z?^F2feI8xSZ!u*U03fT1r0c8&NxCj_C=38Y;C}}gxOAsg9C@J{+62wL2048u$odgr
zE0mbqh&YNrD-GsV#GnSODPZtWq1tHdJw5avPmm9s2Bvhq
zV~{9I)GgRJZQHhOcb~Rx+qP}nwr$())3$A6`hN2!-n@vJpH&f6QJJ-J@3k^Fz8Dj-
z!?<2ri$a9s!cw|pv#;Aj$h$X`&rw?ERFZ&K0^cm(VQ)t?{#e6&IdYV_Ao_hNbytEs
zhh9DE2)!hvSR#E%?$9OodxMu^wlK=s+i|(OsUB<(sD=vpUzLqAVfAem%FJ|nIO*-l
zdC2}z$yr4Y!t4uS`TKJ*o#J?V3sz|XK6`qF^YqM@U7n?TH!QbL<{g@aP!B5!y?64a79Z0ZO3BA#^`_p!z2kTMaFUm9=VBvcIgm*I0cgQseX
zhK&bHOy)^7TzBE%!QeS(&mc=7%d|280oYA}Ws@t@#g-H%sQu~(H;RY2FaO`wi$`5s
zJa{@{u_uhYNR5lsHHuz_lE}L7GnlW2!aHCC+Lia*Sb5RJXiz~m2*(Iz5Ecq1XBJ58j2p!G1RCF=>vn1
z$_`%Z6$%DLGTDfj(H4{hkHu(S!ofX(FWET<3)@xd)DeSt@JOWKP{VGEpK{;|jqpKC
z2;EcM%!s&R?EyJVhLMyr>xDYlbw1z(k6k_z*-7@qHS9EX1`a?hgD
zU57YZyP(>ff!TYFidRg`C6Is=je#e}<~Qms%FlsFp+|O03yCvA03fsX@59OS<*y`2
zjjc6l{n~L?`K-e%vJk`M
zjqwLg^hbnNm}Xeq58*`y1Vf+lfIvMV&@2O0PAs9t2E=CWXSEg&&+q)z9@0*2HhoY)-Z^(K(jiUb6n%VO?k2&o74q@
zAUITziD4XHk6Z+TtI(1iVg7c7vq%gy07AUDwAP5)CY^+-l{&l41L|WQCTP7L8mxuT
z>R2|6auLuqt(O{$aCr_)1<7=K!EQV3v0^cndzii6PgQ6+=$O=MSd(p%C@Cz`TZo(O
z-8EG+YZki|S_1pig_%~gJrHFVcCU_e4&_q!$kflpcmQZGIAu!D08=eB5@^^!9Q+uN
zdHM@YqOKIYau#QR1JN22DUiAHS%D6d2wS)eEKi?3cmfN)2ZC}Mb%wes~!Xg%bgst|(;-Tnv5lb`e^^r9c@6;%lkU0|q
zX;<;~dh18JU7)!R?XG5#&qga|CwD)&eLhH*DyF(KV?v~$Z$iKlcy9=Q#l45Nj>}m3
z+5q<~FweUamhNBo|9O0OJ+A9ePU9)Wnj_wg{
zTMZcAPnnZN%j7hDhSd`icc{$}m5)*w
z*+gsz8r@3d?9X=a64+csd0Qj=$QD1G56*%pImem~1J*D?&Ix$WPI86Y`~?qP&B(5n
zsEWnPj=hu#>n^A&CA3~Eg1qmk$cN)XxhoOb1=Uzea5ZI;&Lx>lz~7oX;uQM&=xSX8j}hcb~){=7F-TxYnk{lVa%aVeKE58c|cMelj#cz
z%s{dQJ~31rCKWL^?=V2sZQP2JKw0Q@dpsel0XzRr-sqOFNpYJI9^8XYR6)m%PLPnm#2|orF7168%e)tl8?LGi~`8haB
zaPj}Z&+T1(KEDHMhfrJrd@1tDAu`MECr-@LCekm+nUmT}PYTNU^u$plqvS1L*u*r|leWKNse$
z$9OmwBM4Ctm+^?}f>7*MNkIv6UjeS4n5>d|CHiM2-3cv7t2zKH-_nSsVKAyzN^Szw
z9+gw9;N!wJbllSqtO-+IV0D<#qPm>QRTW45@;Mu1i>6;GUnX~XAZ1X|k!
z?a`_X=3N8me(K?(hy=T-?)GK5W%*&v5|(u6>Heww<^n$>TvmWgE=~Kda
z3ql_RkBHnlBTgoC9QK_SuTlB^eWW>5u;OgVd9sZ>-LNeXWS`J#n=fIqRi1y^cF~NQ
z51ZAD*#O&MFHPR2jR;!~P4<VY5|606=yNdaS
z5@(_sQsB=K7nLhG5dN8%*DNjjAp({XVx8MI^+!RcgWSOMrxzsSZ1?C6RZ)a)MHX1u|U_}
z%8j9j4F9&v)nxvo>o=b%qA{gfDf}tFE*ArOcP`fZ-f0bdkKdrfN?>LQ10GsW#`K-p
z3_LnpetHEa>Nlvqf3n1nws0~3ZTlfwJciP7T}(9Mg6{iuQIrXI8U_jaY?FZvfCYZn
zd=oH$tW|k+gdVtj6=%SA+|Vp&(WYgs&(X|Xf*ylND{)DC__$*?uq|w9sbXgJy0T~&
z>->9)pdvk%xmVGwx7_`y^YmH?3768_c`sxas-o^w_HiHByyb!y0?f`DJ(Sn25Wy+_
zggXFx_>xy6ltAx&^SvCSxaS9Eyfv#aUz;Y4oxW^cOu#M*ETKFNhX`fGRov84-k9JyS=)R
zS`aUuyY>J$5kENC(@<41lFcMF$cWZDMneNhr`}UlZz!IFmZ%DWmt7_s$y*cQPukfw
znn1N8!LO(dL8*ThyDbJYW?A5oYWn*hiU%#vl>04N;fL+no1J|+$|BUQf;E~Go9OMq
zQ~T+H#(%t88yjrMT5Y&-L_1~~f!k27poN|gfA8dEH!0Q@vGyNh|Jpx{*|oAckN;&l
zm%nnA!@J<&tJaxppg?H3Uq>2)r4SL0^(ELEH7X$7hXy?O&bg
zCMpj*>r4Pa^Jbpu<_eRIrM=duZoo!FdRlx)f|g$Yjr+YL$>xfV@Ma2AA~)drQRM$v
zC&;<~!#W|`P#IpvXjvTXW_8>-38EmCJnjDXxj;>tvoh=DstSH4jvPRb69+BWnx88s
z_M0l+D0Z6Yb<@akpgh4lnedw_INooIGDFH*-RJG{)vqU@9sgp3H|}F%oDY=v-@zi{sQ_;5rXHEce(CDh!2yozsi*LEu>)UrXDGI%JSAw^JLx$Pxjo-68i
zSs!@m{JT9w77%1!hr~LTY*GS_&8$m+yb%mQ{zit1FuyjZW-vnb6XwP{t$^tc(!}LW
zm+~*LIK(>v3BVAZ9hTLYPhsP=&H^s85W8Rn_g9CwK7|c~P)Dd*6CeCVX9n{FqHlpg
z@}_H#R*HpL9y$nYYEVYk4gC%T=ORbk0nr`Z07Cc%ue?KWaf}v{;$Q^nJi6=zsFSES
z3as@Mk@HE#>4CeZd+uI>O*L3t-HR?2m9w#?Y@GtVbq50#5C=HYu{J~qSm3CG?AxL@
zs8vQw1k(iWhDw>_*Wmo36jWc`Oz@K`6=ISXdirB+tsy(tD(cVa*|tDF_sIU^fK2`@{`f-g
z#~|eU4}9#=iIdJigk@V@%B`p)#9
zb
z_&3^T&FnQ3aNdf+x8
z2Vp8UrO6Ca69Sx`i+D2|-XOwh}c?Dbo)S4G(#Bs2h4Gx9&a?8s%M5^7s~ibLM8
z3VY
zoJyPtzmG%|@Eelq7v&>kjr|Dad}@J!bTn%tfSgYeb+1&r?%BEi|9SXz
zYQXhsGgI`6)L%m2;j$ppodCp~Ir*E0f(vpEIR`c@pXW9ldo%Xgy!O!oOIg5wbvl{r
zvd?yKt~?uUG0exthYh*J#W_nZM_8n1=&pcFUL|B_e~`pm$S)njE)J#24!9$6q$qV|
zLg5y_Vv-}DSBSAw^EUZFQR4D|0rKAan>l{j8DMjCffioNIl0dS=@cxVH;zL)T+)jG
z`IyHExs)CQD2mJ0+57hgsTYEnzfY;X10l9r1A{izAIN!q5q(s6%Ywg;^
z!wdOz{S#z`99RI%>kmVe;}E0a~M|X&}Hr&
zF+yviCLc_Bd-tjm--+?`C2jQIVOmbuvJe11K0_WJux4z{_eFK8$h-q<79%+d?Zrve
zcLH`Ex>ix-^5DlR^7*sF4>{_$Fg7YFjjiqeU-%1%12Qs+;wefX!`{8-|BnbCJ6Zhq
zTkQ-wan}E%Z5jZpS%u#}cI0xh$#oq+jg;}F5?Xq*FyFHv*3^2;*C*WO@#Dabz!Nz;
zb~(bXNJ9;~!R2SSv7-o$80FO1ZkSND7BG0XDJ$@BKl}OQ52VvH4d~N0AH7VVCNP~;
zH^Ve9zaxjFK5=+)yPI_{+97{uTIYYDEbHfDYdhH*y=uAT{C{|Z|G4TgB(m^8
z+2*e|!1iaIbU#sP`fs^`&)M*BnV0H_17=JgfzMIJ0y%@6n%MvTGRi#u)=U)nJeS8K
zS+2WG`=^Q%k>>r}OgvbSbDUoaS{|U_Im7)1!zepY2Kd7(()-z$lYnl@@
z{#w3cCv$bIs0W+7V~4x7%VQe80|v9}dARJHMXWX#N9gYcj4W$L7khb9h$KlYzKkOQw2X^>pB8R?+H>
z8a~5?&7o~&Yeir@r5a8f%J~ujx6l>3H{+g(S)U|uE4MKN%;r8}4fVVZdCP%cYesdh
zF5f4atU3w@1NBpHw9E{xQ^iqDP9rl-t3&J!m9`Os3)S+rPJN#oTBDA;{+Op2y
zsh8N)?b=$=Kr_2gG%s_}TnW+(Cy$p%G`eDUMZjqyOAlYrMDA@!F2T`vNlJz$ofzDo
z)`Fxjn4nABHaCiRR^Kc7ga%7hk&@++FC%tg8`>vKym;_qh17NddydR06QUvX^fab-
z8mACv2)+l$l7n68(!sUCKRp;eXTINtKvnbOe;`nZbMY&4S#&GlN~BpI$ADX$2%R43
zzCeeSybc5JQ<_U=D#Hk3z}sI%b;p!e=5@)o%2+UTH^{gM6J01P^ua+8Wv$sXAsyh8
z^cj(4i;oS1+Ks9NMEaYu(kaQQjIPTRQ00dy6}t$`5Tx;e6$<4ZD2dHW&MPq3(R9Sc
z7nxrVA~Lf4=`63+nNA4R6*)lc0i#U4?+j-GS^-EvT!>ozP_0ps5^3Z=_Qfrr#w*Io
zTF^8_3Cz8sbT|iQBDESIrOUuEh>OX)pUa2s$MXjK4{tYt#g`;30;s4&oINsQz?U0B
z7ER|QaLqs}Te!cwW#m~LvmFJf7Dvxu@G;yBg^3sT)PxBYSDM5FDY#}#2G6ivKaN!E
zDYstI{qBkrK=FGEe7krU(>CFjsWKfLJGV_(+0z~o#a=o?&we-Xa_??%o>*f&*{hJ|
z@Baz%DfKlF_b;Z;u6GPF)l3KmMnIXHzi>d^JE9(*P>;D50=Cn+-2pyUVxazk%#?t>
zq9lZDzAcx$rg)YT0%GPQw+keQ0-Jq(u?_P5
z4H}%;Ge5cgykS_RdQ`;qDTVy*Mj7d)!WS)Bx@>TR14>j9*$Q~BU~Fh!UfxnT9vP!C
zil-JPJVla0Xl1g!j9E8R0^?OZ=ao8Ki7rK|NSkxmif{?Z_kb9z`d=h4ThFnFa_^`|
z$NY7s{{u=lxsEqU3gLGk4MqanUL(D!Vd>67Hujne2{nxqTq!d>B2NdLJs5>|0=`qC
zsMWknc)mw4R3q-Y+p2&+xVb=+?T}mSEporgUOj2*1LaoIh!Q5x+EW51u!#rlBR^^(
z5A^v_zERFipEpx6WnanAD;U90SNP<$bI0C^<&9ehPYPGw{`JJ}9mOYWeD}rd))_z?
zjuFd{>Qi5Gjb6>qLresgYr8(q7K51UOF@Ebiigt$ZH29xGM{YT}x6wvdzAvNd!hsys`QrEzX
zZGYn-I@)2M0}Fv9UZV*UeAX3(XBUL7_=p2L)ylKPc36;S5b2X3z=N)S!#Fsj~fD
zy_X_>X@XG&&*->v`Yss|oO5?W^@~y$HNYY$IdiR{P}1-{S9ha@85QTxPNr;Xy@U>7
z1+WdRi51K&>e7@^WGbR^QcXr8$7_44GSb6oyJf+$A|quUpVGwy!BU&KWW0dYdgT()qmaav6A-6+WNiOy_y;?GJP?%6>Aga5?pJ~S*>NntP_hRQoVc3(n)KJzO&|{B6G}7dtvFBzEqah>U78Ws`4y@8gjHEN(t&q5gY&H{@xp_
z(Uo~-Ztg)&NU30r+NGd~I01!-2`kHX;PEFHxWm{G-<^oN8!oODyLV`f@zGvenpj^n
zBDG(Jf3V}clmqg}$CCmQaSabxer6Q|qyeB|!ifHa!3S`1N7KisOBCk%Fu!|O!xtR<
z^No84NT(pxwipQ)>P*-XFu9*grKc{jyK}IIp?b8B;7-!i^bzH&8)X!4eRs>u5I0Q9
zvQ(COh{}87n;W~*7Hx
zC+E#xQKOEni22t&1ooolZ{+^LFdeX#@xN%*7@e3|B#j*Jy@882dwUo^HfXlh2y{h5
z=Cj*Cny(z+g;}@Gf9?lQMBvrVp|mRK;Njt)U_6aaQ;wVFjeS`c0JnC)e{dZ|fJbg$
zxA%4LZ@F-WXjbj4uycWKalnm06?X~pv6?k>0^nXi@A2uyjhAT5YAJ~{HJQr(x4v(m
zun^pH;(8dl7CRe}$r$M!#X^@QQ(`DpQw8Q*^
z62yhjII{h(cL?y^X&5tj>7qMkY5AMeBqpm=LwT3=vh|wjdn>{+S2Rvf^Z>A^0V7c8&u}k%CY?Wk*dlwT
z5E|;`;<6k|e&OA?1NZ#q$SMeW@y46k>kw+
z6}jKtvT*@)c;zw+@}JJdO59$>#-h3M(ftWHKK$>kM7*ji7X;FAVIt+hUM{Zsh1Zu~
z3GVUv@!zX?cyeR%^($NVjs8KH^!@B_sLR^QIe&U~RLh9bNE5a)j@Bd3J6OQZf5*ML
z##;O$g1#}WQA20q8&vQ)Hpo}DS{ox>1?we|Ap6(7dwq5`9utO86BzNLe0#UH{Q3QK
z*_1SKpz3+tb0iCm87Y(`6h>Diib%7zNsrTWh=U#ALFXD=sv=V2=_m|#7DgYe$mn##yI}EaxI5g3|vaJ-+815lh|e-|ToyOZzu8-oI;89i#1&?2=oYC3Wq0nb~3~73HZD
zhouoCX@3F3uu?V=MYcTI0IJwO=>CEe^BGx6SV;|%2JiG7hU-4nnPp_IwV78I
zKVQIY_49q_K5r#|aEZJyqL(t27qBrs(q!TmZohSeKLQ&qOW*_1&MoG3V}z+4xhr!}e5sli4wW+4LD)h?0ezSwq)mmqme00Kjb8=y>5dV4cqhF^1tlql(=A
z2^Gquu8fEe(n$Q=!csbDgNStS%4zUeQEECuj>E
zZg(a?*hc7J4#zgHgF-m8-LASt{?FnC~>IfKbt4o|C_;rI;j$
zYoGi#ixK-zQRQC8L#IR@jWXH6o0H&p?As^>)N{NuW{mcsa1h(F<1
zo@ac<6|K8NN$(ZU=Q`I-bC`q04IT>=-ie1EfAJarq#N*RLoqXvl`Q8z&Ij#Usm9qLjy@`cv;|gZRl7oOSm0x^ax*EQjP&~
z9P~MR0pq!F=A3zJ=E?N7XxY|f`5fOtl3vUA#o3`w*cd^GWza-KsDz9O}~m^d`SPJcuNG|k%L0>qUiL)09JIiN*1!}
zL3_eWN2@ot4Wi~;1i>9S-=c{&-|FCxwHeg?8!*$
zy!yN!HvysMhfdil`!c{$C1mv8&ddCDC{SDRVeJmYoSvaD18w#|0F{yZM@;b#0eSh0
z$HOj152vP`aL$jdFUQ-If4+?-53Ta0p4&q0I<1w?haQb8wd$hanR3_6;k-dz(?f)X
zcUDfp|EQXu!x^_mC(Axicmq7AyEL)`bsns0(OT)Y#?T`gX_OnD#iw$yC!xQligF+8
z<{k)3Gc&TBJC-dvp|k+p7s>x_o;#he9$;S>kTK0^{H}L|;oid`m215K#zfP*OYcg<
zFZ(t*gNL%ax)xG6-6z0!Q{z}=EuGF}PWH`3zB?5(o8h+uC+^5^jx3qe
zq60(6ugY{HFfQ*0DOaBj+ZR@g?h%as`b{
z-fS57_s!fv3p?mgy&~0TXUU7Xt34d0X`(cqrf)>-3G>!vtL9jRY~+tXSOhhfb}X#!
z_e=wxk>W>(R#7&h4%68?4Na$acG2U)uD6z1+0GB;Qp=%B;}gxDuu}O~GM=5omR3>U
z7?V14qbr+_+tvYXVn~a`_QgWT{i*YcARherMMauRnOf*=MYw_djTeKn&Pa{x!dVg$
zOMTa_G}uQzXND_3sB6>L5**aO&!#m*xeV`96j~xoDYv51=Xv;vsk2xqbHlF>gA?Ip0Nqk7xR%LExglX)ooo41-_}9IP
zt3cDn+(iF!2KqUh80&;3X&5U3|V->NZDd_E#n>
z9@T|2?k`sE7=HmEr^3||=d+(8%^u9a+vaa4r$->UUb&PuY))F^d
zr03w^2%8a4oPh~fxFSKJ{af6-WaY#n%-N%4&wZHr?pH6>{!QcxfS1MRWWf(1p9QhwyFP!2Ygs
z9rdE703GU@?H08IZT#!+7M$g2D(|k|RB&XBBNV*&&#KTgl~swrd!E%}#saMx(U!j<
zgwqx?V;`HLkxb_8Ue$3BFyKwKk>`}klVyV*KF(qg=mzfa%Z?D|xd4_9;j~oIP~LIe
zuF`ex&AGOM0w2h>aRTfNin8C-8<-dftn%pSPJa~}jl
z#DJh`hH^RGa6ylm&>;kdQ6@42t=+oUUA7E{5^n&%ID(AR#NE%0T)BIAVXo=Kmyd8>
z)Ncz`tY-poN6K;EhLAPH%M&Y)UmUZz9hr5;d}=*v5(c{9w`qwclP4a|;WO=as`qV0{8shRs?x97T%
zmQh>Xr5ZckINFtwER~%v%7(UXk+zlFc_p_llNYChJC&W3n!AxzxJKDkbt+_XA1?Cf145iAItas1rz2I_5|X
zmj_aR26|U|E+;T#BK#w>BTlkCs6kg+Jy1S*MVR}sAHbER9Vi617NEhY3B=2v0u*LV
z_|NkpehV2PMg*{cacvU{Il&5$rqZhgU8VwnNY8RGN8Y`P_}U;=J_H5*_8xDK4z;wk
zUt8j*nORj#k*32wWL(mmEzkh~c@(TAeroBYH{?>eWOpMHSBY$*GN&M|jP|Il?~DsU
z0%2Cx-UQ-XH^0HjII(xaA1;P;1)%G;m-h
zc+wE1D}>lxS)3*M4E8MsyzhuT)o)cmOvyWmKxm1n=%{WyiNJ@G(P6pjv(;TMf3E$$
zA=*5L9OgBR5@!_QHygk)F(`)msj!b;>Ngl27zN{32$i3^s^S!W^YyB_bX$SEP7tk|
zC+D7Q%iBgBlEc>$t9Oak8B3>W8#Onl*?ulJ-3V?xh3!XiqVHp6K^_&{-&Tr@?8nJ%
zsdOnbZ9CjwkwjuUuI#kQ$rX`SlO<(?#7$^yAYZTIl;6P1ss;^6SVWPaX$~ihs;eCQ
zSGwjI3KUv8>T)Cborf0J9d?ftes4%^*FPB0VA}Vj{HYp;7|1i)dWYDCDf8siwT%li
zti*-6Xp#AMnY@92e$hqvA%%y^$SI?n1*|ugEcYfvl`T)Ape3M@`(w4LMmKWNSVKC5+WYg#AxY8h-T-8Fp!WUVE&Lp#7jNTF{$
z*SQ-~;7py%w2JBTARfFui-z}ORoy3&pw0627U+k}M0@C?JOG*dsCUI|h4muZqeUYB
z2*J{?G|Ws1xKRC+QRI941N*y#B=%O+(+n#*3aD#*F!!+<>)Q;g#&k-Iw!u#OzB-Ec
z4x&}qgoXb3w$+WDVl{P=YA|_xen2;9BZzMew;y(Zgn2%MZ~gq~)|CM0fkHM~sw}vl
z=!D!OZ!9jC!yQtH#Y*q5#EJ`x_=dl&pbAb}Bc{c+suI#e-yO^{#1lb-d7V=knB$mG
zb?C(CM~h|~oG_%Yr`*zSFKP%(oKrf6VobW>t>=iF?o
zW>Ce!dW&%)uCu4UI(@%17FYinmBMKAd1m)co8x3(
zg7{vEd9!l*_-6+5WyO!y{qasnFP$Wqe*W_)ks~eoB6ZkM*V|a^(Rfaq>g<|rgqMcI
zdwrd)^fasXl;BN|Ou0FDhq&G-pF6AurhV_>^iXy?ky_q7v0YV&h?R^;iId>lKv@nmbeKX@0r4-Ax~SIAS(smKwXF~9xOfe5l=GDZal)n>uJ%4`da;cN
z#-IfLT(LnAyv0ZhL>B#Y&8Wa|P^Fa}vd=9H`}*!!QZ84-QbOGC$|$~>*klVkXdnp|Yfgfmx0#qriVaY%FuWp?`o
z&mVmqAm_}8s>Rm;k{IM!O@8k|_>I?|o|~%AJ+5+&PaVS3%6q=B$d-i>x)Kk)hS{XL+E)olQVreZ#6}4@A$L_T
zQx3d_S_x!a#qLN`IJ%ivhNs?VYr=8T-D-r5wjmG)3rF
zwMv(ephVMKiH<$ysxU$QKcHI=6sMBw+7`h6=Ef9?|43YY6$<{CLBKP9lyD0L;IYPy
zk?7$9<{JP4s8e_|Z9sDBUM6^UM>)aI`u?6vWzBF$Tac(8{H@G2zjh)J&(oQ!k(U+X
z!|Ht6TAv{l?>nH#*IbUXea-A<9t`j+2nA6-Y6_XWr4R01jbRD`Z00Mm5!dh2MLs!Z
zOyDQ-o?df?M26EUmO;~3&%?b0+8pi{pLV^U+TnKYbB*>t>(7CG~h^cbnueZF!O
zhl_Q!3-bCei3Ru=W-2+D>SqycE5VTjs*+RHDD-4flJa9H4uab#cF^&wDTpMrBr78z
zlveH*iZmC%SB&a4ikYA74YEfFJsq;AK+{oJu&OcDPf>G>QVUc`c1Van-1Xui?ss0a
ze&=OUyM;&V_%o4(KB;Rfd)~P6-TX?MF4fWYXtPHK&jKV;Wie8tsZEo)yHG*yXnuxa)_~+Q`^q)=D4eLQbBBQ8D19_UmprXl!_%qw#?n%
zp}9M6;B`pGB+ADnUQUe>gzo%T+vE)sqLdQ1IZ3eO)6A!~pC8AUZ)y9(vGvoP8=r^>
zb_6!=8=TrsKrFBAt!}W6{y_}-w*Kc!D=Vj_d}~M0MeL6B`q}7@EnA85qz0vON^y|o
zBV)D^)?@`rMLtFnW8U`)Jc6LYcmsd8G$tH`f?yHo*ZJ955xyVIyFUskdyKE@tMhV@
z?vAYQZ*FY1$W8P;QaBqlguQr5FzrnJe|Ii!{WA<-rdOw1d_Jp@k-LF`;ZTb)ogkde
z^hleG=IjzcddkEJd?~A^m(@%U#f8f9Ax}-xfkyGYE1O%EfvpnK(*rO&&6ngzK)+P1
zpy4g2mCEy({#eMWE7VuiD@jcuA0Ah!fKG~)D;W?~h&S#Xo{>5-IniB@nA%DoqcWvq
zu?jMplI%E8aj?5(wts+{R@>$zS3fI&gc&Q~dBp)eiP{3UGCF<9
zPhJwps;{dB_HG9d2XiNeZ}ihN$AKHo;GZ5AV{tQNWMlYkb(_lbXFh=~+uv{ZX11~M
zV%hm-GOe#x%u6UuaG?G6cw|@aw&7bV&0Id)+a`W_cSX*%;j>?ZP)#e?Q5PHc9!-;3
zZ%A%XiFN*0D;Yr1s25FJTp~$O&Oui48UhYT8c(1HvzzEglY?+78lGbWO-)Qj>@jK>
zPK&ov=}+|m!jx~XC!={Sn#I4NXmN2qi^Bh_((^m&@>EmNk@A22l6N`oUZbOkc}Hc4
z*(+ih#9n+GxQb-cY1v}L5D2!;moMLVBL23%bIGNM}`@w=>wr*F!B}
zuozJ5FF6=PtJfsDOR%F~4IRC-EcCltEmcm{1pJbZR(vbeo_P{WFn^p%;9J|DlV$`#
z4jCPZju&SJlc8^+U!m@nSyA)Y@Ilt4Z29fWCEfVT%)&m3IE!-&zYE-k
zSxF%USEZX7{GI0Ne$iFvH@LjRV10eFA|3m8pJ)74jfB6qJ=ECPi4==y^m_V~dJ!9e
z>*kFI?`|Zv$iC{WPA2e)Xob@kD}E`3Ac%TIHr{m4NTA3nCSI=!A_r8VV9_OBM9D4Z
z;PC3LcbPDT!$m9`nESXMDlg_O%OT0aNg{xSDE3Xt5n#-0m%A@bn&|p9I5HCn
z(8TSW{9yd^{(B&g$jv9o(7EU*<5bYxVes6^705Q8c~&?tkWA8n{sOlKDwM9o+%51*
zz4!ag4X97^w&%LDDGnh_X&VSxIQWwKH~WjoW({+54I+rg(O{=urbP5GvEr3>H~
z^lDA~nn*7M>qG%y3bdbDNnQwBQLR-cSL&ImPqK^(2KDb^(o{~oi*J6l(IBvLy|^C`
z?}wf#6n1lT2D(5gi{!B6gE^TMKH5U_lzE&qpmW
z3X9TECGsUP>ZElEYLw8L5#)j69~U=Z+ktWblPCPG%faScg1^}eS=X?wFR+VV
zRtMyoKUN&QAKpH1rgmV;{3@62pow0FT=OriRicq}x=yE$`!b^ni{5*9=Q~LR)r6VF
znTn+W58Vhx(K4|KfsxfGY34efN&K7OKBX1
z-flR|_TFfMNA9&|!8{r{jIj%BAr%+cLt33+3IKZ+2z#gV$m?DyF-%T;9W
z)z2n|=Jy!UzHKi2@yq;PU?>`zqJNwv-BLTHHThVOR>sCVIVA|
zLk4G28LfvAKOr0V#f7Vk<}~koVimifcd5D5q*%pHCVnGH$09&^a{H-^!wid4aQrhf
z0=a{$IE~Odxozpwm}+R7?GR3D+1NAeOmEwR;~C(nkZ+Rl7?t*fN=N)CE|^4&^yeOdcOg>0)!q{sU`M^b_|njqre&MT^+
z5i>S=lw`xDwA;L~h7%t;F#vA;D$_P9oK6rnP;8d#+#G10ZleHSuD9H(
z?sS$Wn+v!0t?YeW8B(#PNhko^Lo5QN0c&B#^yvFO$UNHK1(Ln$NCW>VfsHWnfKSq3
zAx~YI9L{r?>M010JEyvm@)-bMvwOfM=b3;)
z|L<)9%erhQMuXrw33O*p+I+MiLlEi^KNw%C0d2p-(((R-fHp+>A>L7=O{2>sY|fk7
z`1`@~gz0-pkylYPp0O!>@7lqM($Dm5@*o)qSl^r^EHHV`IX(Kj+0OW!=!aQ|4zC$1
z>?!mYznz=KI^I>Z{!=j+2cs5|vgBzNv_|+rXKK#8J%pqy8J8*i`5psrxawTnT$+?6
zeUeLbV6qku`0g8D#F|;FG8^clAb62iLN)W
zm?ry3#*S9N@W<_R91wJ0Xgkk90NpLrE%K+NRW(r?VW?fVQ4)?ugtXWA_Sf>$`Pnjz
zn%_mN?Cf%*8Xm!e-u(rZfb#8z5M}Oz>Ct|dkg~Ou;}=N76ehl&WZ`)rpS2EUSU37M
zg2M4qP>9yO4Xssq4{s{XtB-S%Gc&%aORDP>!nRf
zOH@7B=ct9HBwM&0cG3ZXATFxN3cuCynL&Gow?9|ZzM0QMIZ$ZvTD0se?(PwKcJ{3j
z&6u6%y>zW_qo-I)4Zpl<%Fy29(+6s}SY1elcb<$Yd+=qch(8(4Zf_V?i6L{NCm)A5
zxQpitWC81Hq^BrH%TO{yij-DPX#7WbcAt-dqufK2f$`8{!&!=H8lpv%1fJfZSTE?i
zI7qmp{X#ZD@@iz{)Xrmyj%~|*FN<@QS
zFAAC7{w>%xBBoYU8(xUnjSqr~Dg;0y8e>F@H6M7JBUI|cCN%t({p;im;
z<%+p!HN5*;P~{3~NatTo!6g)oAY5VhF0G-9C??vKUn#WJ@!J%S0L
z@;~n{z=F;$atP&O%-n^WC;xE%+D<9TJQPVhi&%-zK?q&i7OTLPqe4VPmJHOQ*urJV
zaH3_-2qNL;;rRkm4C{(JNQ0|(`4z>3;rM5r7Iqd>elfkSkhiyI?W)c>HRqI4pd`lH
zr^$;N4)*fbQB8~P;$qGV*+J0_HBNej)jm+xN)JlndI~GMfZMo>yFX5D9zIeiho9zY
z7Gf^I)M}SLYMaW@;9Bp^9yDt<8TfmcHO%BriMJd;_t7(~BBKXhi^hi+HvA_d5@jCAn}g9w?NPlUmSmVP{xKYQ(i--qG3BPP
zFV4B204^+-{+^Xgs)N~e`RXRl{F?`hcY$Fa7`V3qKeIue0^T&>JL_AJ8OAIh1(Pv?
zC|C#DPQwO5JLd+9(TZsWh}{|7{yR`$1Mm?*g|Y?zP?@hwW_oWc$TQt_=(&u38jF6~fGQ;S$(8AZ
z6)IvPiIlxDM8&tTM5B3dMJquCu#0ig=8NpfE=(SWmMuV$iDaGz2J_OGi{3qgh6osR
zTiSq(`<%XB2J-9S9N+W14cQ|qUMczjeX!>=~AYT`E5AN>n1b5iDyF<|6?(Ptr1a}Ya?h@SH-62STAg8}?&di;=?wWP(`KQ-Q
zceD2^RrS=bx_9^VB95xt@7$wiL$VrW^>Xj;ovoccYKaXKbuSRp=?KVyNfAD!&&Lj5
z9Ak5Ix@;`^cMt5`dN6T=75}VfDPV|$WlAa*oCPNtALpu-bS834
zTvoFWB4(?L0Yabn9jq4uzoe26G5DL$+Xf>wI*s>x^P3P?Q8`sRi?yeTxid~k2_0vG
zb*~)UhwCT&)69yivG0aohOlkS>@LpuJ%gNIhly%o?3Ik<$*#{Py{N&8OmTN;NWRj!
zJ515web+g#f?Db8sQYtQAsqU;)znG|)q|bCP_pbtAEn*0=tg4CT?w*Kejb<9)bW?F3iNkv@3d
z`FV{QgCEvQ+01r1j(3Alk+KYR#HpIYJX~(IRc9
zD_UPcl8^fH6t|{p`GLD-x-skshh&Dq=!iBIlH1O>VwqN%fRD`1WR!adp=E>NO8*VNIBeOpb9;NUI5t6??l&F%(i0o)W_7Wk_CAUEUQk98
zuMIKW`sBlf4M}nUF*8Ii=nC^DG%53vVLS{!EZ&<>b2#{Egj%2gf#O_4H&uoq9G|93
z<~;Y;3A9+XCaK0IS(6B5Vl26T0Dva^(+lI+l0q=%ExBAk)
zTGp0M>W@iIO&xq*>Rr8z;@W@}RUiDk@pm?#jQb1L6YRxd>h+jE*0JqmWaa5cY5eqemHkmM{3tC4Bm`?WOm$U>uJ
z*o$wv%hTv3PWObZFibk^#AIOQ562W3*jY}SiuHNu2q
z85@o%JzB2ZOXZ=Jeuq~2Mu%qc?x-j{;`j@NmLtoK7$Pe<#IvVzT+VOe{_3D~ub)aF
zx<6h$@s(sAYSv&oQqTZDBJJdb!zEyCCgUv4ibHb<^@~7QcR9N9-KFJirYg0cjP5E!
zflOu7wP2EKVk4!aK--ci#`E+BX75S@55kP&PdZJviq$~+?&*eCw$Pub8-kPvckhR*
zm)mHAr~8|}&uzG7oU~L8UOsjP{-61H|I!6);kWjvr%%;VkJ9&IZp%z%aGr+=eI_^UM@KX7r{Xw%D!=62zg7@Ln^rC+;eO28fxc-6AH-w;fgGDF@{dE126d*>4
zVE-e-@sh_=U%ar
z%t{wGq#Wd93ZA(CrA2=K1w=IEaP6*MEjrts&i$E7E891hzW#w+76)ZBK1J|5AQt0}UNfU<8`+Ax3-QnUVx^KbUA+d;KNg}%KHIBx+~VTTx!K0;L3kX^?{
zBB3lPlbMU;2wDH?XU+O?_BihRd?n+}{#^QA(jo&38nGc`K~(>>O3!6=3g%#EQJ*Q;
zq`{0SP3(5I%~4dgNd>Cbih^__N=yFtmu?2
zYYFMnLF!e$C*n4c+w}b&G&WqCMeXByn9@YaLZS=a5<^5T&^xF=pt718&+*;l)9hRBJqPG9#BEd>}YA&
zS+hp<@b0%iI>kG#T$93xPTK6myd&5xS510yb$-3F@)jDq^}6JaMy=UN+e9k4U`pO?
z=Fu}W*dZ;s{6QEJigA@KDB`b@A}$OyElhqupm`fDj*7D8SX=j8u$2!B-L8=>AaS**
z2hq12=1`2K#{7*T`*kw4rnhd!xS**ZKlqnkLTBg6NyAc1j({($z5_=R};bCs*k71I)7voS9mpi=3j(7BuvhUV9<
zYjR*oJ>E8wC0E5^h|iovYWl4f9n%N~HdTT}Hhw==rIf$HO$Yu9`e`voetn<|gsIls%o^*sO1
zgDiDM6WTuW`*mnB3bS0*u*3*|aqRtTf}%t^i8z`sg`-|97zlBFG_F@XYx;=poe$L|
z2fvcLSWcS~fudajXTV#a5!N%&!+6yV-Ppx%@8(}lR5^R)3b$%e;`b7~W981VJbil0
zBU2s`;S(UdtwfxB@{HUqq(ww%T23s1P(LA2!lC>$1G`iR5-QoKAXW=jYv3Xj*hcW-
znv}mVKF5lA0x#ahtrQAwbc@<
zWu5}ckYaWD>PV^N%BVT%Qzm7SQc9}eI#33ALzzmWypFE>Fj_1>HxF*iIZete^T!DU
zQ2VrG!mc-uz`G4}5x>CR*SUAh+zq>h3G>bBITpius(M#dpGH&=&w&`zW+i7sKj4nc
zQa*Klb5^H$TP>r(W>VYQU92C?DKjgZB*z@0=!XlDK3M|607_n#|MaCvtda|nfRAtL
z5lC;Tk!o8;I1iIE_B*uiSELvu2Ir}I%lQonelQa>GI3=ryoAF~*$NcDPb?$rwfz{R
zwwZTM`(`0jFPTHLg!Xt}yaawhzi<$GNE6a04kxGlkd^n4W-UqS8&|I9`wdePTvz!+
zw1a-Ij%a$RE2GXV-*5=iJ<_N>$1g+#-*fNr3;6KXtJ-xASI*Mv{R0Qu{RiG#r%_;h
z+OihTUG(T@lKk)1
zx&+nm@CbG4Jn*^9SI#c|GR{cc8cxe(3FHge&5Ri{hhz&fL6Q~5qQuYJj6#!|XNuZg
z%I~rkVfrjWeFp1`lNioM2-*=weTUiJ#s*KGzh8WvokJ1ZPg+ILda6aES8je(BNF;i}f=+pUY#T4jhLW9d1P4c3!t1!n+MSL%M8afc9>@@u`6LoA
zT%OuZzKpzJBsHxCPIl-O6$m0|#M-ik5vf(E%du^E8W^6_Icc5~O=ogV}W`qKGid0X|}%JF-A)cnm;gu*$MQ(>5*LXj1xx45S_Ctm
z#_lZe-153luj9Cl*VX8F(Gl>KY}MxmKV)cWv@t8Ik-XWt9G5A>3?Rl1(l@_P(*2a{
zyZ%xP=hvdfD{oA#kq{W}8QGg%+AD&Do;oZ~q4MIUs*zt;l5@(N4_7YO9eEy=!oI)<
zZ($cOluqYi;@jq213LT#x4j_OOvsS5ughg3*N1dbXFIf0oP+w+E~Bx7KiHAl&;IAM
zST#<}Iw}XRz^rU%V2P8PwNT8};L^R-^iw@vOfef)s%9#Veajo+ugoi^?g1I02UM3Z{;zez|GRb~S
zeID&_MXGOlyC%>h8@trxkMSAglc9XXk^ft9XY3Is34VtsCaw(X^kq&jFHcLK6j+dCn0&XCaekbPRfT@>>K*;>Q4;sDXav9
zQfKv1%{{yVi6f@90Vnq!V+Z=@5cP{N2|>bU+u-1%wvHbLg}u2)JU}I0qEwuuawUxa
zEumLcm~zJ}thgIYxAojV)r*h1B7cJweQDT1Y)^gW;EROmwD@p-u+*HNQbnuW!jMig
zbH8{$NqXFxa@^?raEZIzFEeH3AsTJwvxqR&J(C<}+HT~Lyr8%F^o~H4Z-p8}?O9JO
z>8rOQogC_5W3^>Lp9oRuKPavJ=CNiIubSe{;-Ti=L
zgHl2~c~KWLt*O*u<*0sj6CUrr2y|tQR!9-@cS31q?owBvr}kF}_+xmgh)yw1HgIJi
zOB^CyIM2$BJR0Eb-ad!NjfsAzPYw30YtJ#%ucRpX=?wwQWX%d)5W>_d{iEFQGpw2f7>vJ>@;
zyLKU|eZAi8^8kzgOH?3>xDPWaq;Fs(npbz?OMX0mYmc~OZrJ6TV{t2d*C9Fi2v#6+COg(C@Q=qoFs9;R3IC
z!(>j>y4#Kh{Xk@zKerc^itCFP)g}iuNU=_uA@Lpov*L8e!aK)Sk)J@6{(0C$N4-wQ
zenJKJ;(`uvL)Tp}N`ii-x8BYyC~+Mw-nH0$zl4{>f&RfRJUbrRayBc0_m4vppE
z@cuR!MIThM!At5nu@HM7{8A^M_a*mLQXzB(2RE@#DI!QSe!HBxz_iI<2hTFbR*H4q
z(3ew9lacLAsesvsM4L;iT)iaAHrk>wjmk7CNV8L1HwD6H?zI-a?@~~2Du;Eq_
z-;e;e*!t$w`ln|yrf~MDjQ9CT<#4-R>odN))4-|F_fUbOij>tQUZ%4zWse&bEljtP
zYr;ZC2ENP=v@w-bjDrY9UjB3_Ij$_zsO%T4XB7?Wdug0|{8@@RaBiS}Ib|MM+vL
zwpaE>q2>$9Q(e_Xtuv#X-8T#A^z@%QGj&aJ_DP1u2TIQHaxbz;{)JL6aZPeHH_aHiB{E6=+7xe&
zmvatE4Y@AS_|GBur?6j(BVrtUZKWpr3K?3%TX^PK$g?Ys7tLe{79PcUb(L!*w_bKT
z;EU;qU#u<*aze=}Ho+&7XQcJQh{yhEBQ*nUXru@v+g6dEu#_R>^^^sh2jmwpei^ozB=TLV(A>6Qebs+J7z%=&z#6Uy>e8@oFJlkH{(Ydm|<3n+V)QWam>PY
zOR{d}iC6oB^lisNFLPBF=rFFkP0_YBgJ0Z8?Wa?=PBhbP3PBj|aL4%zljHf%g~z-<
zblbc0zb&0Dcp`nt;nY;wXZzl_q%ApPri>*LpaMNcEH0@tk+A5E1oCv_#!$L0=j_fi
zjB~~<_Ci{~xkYZkDE35JFpE`)AE~{|_D1UI4*I_FK?~DE7z@iEg2TUh6G-XGh3x()U_S9G8{6N+0|J1sVF=F1_{Gqr%P|zrv=$T)q#~|;gpw$VIf=y
zyvF(H2d?uz?$MFZnsMUnaaeR`#M9@r+t8wPE35vS)q5A?7Y*HV
zla6alXWPebv%Ju_?WJ{uK7l?RZTc0RDX7#;I|D7DOHGK}3pOF5!Vov9s0kjGFuBpw
ziR$?0p0gDdv4`UN2!SK~Ks9e^Xs6pVZT}exlP465x;ggX}cNT0;
zH#FCx-y3>sZ7%muH%HeEyOI^?A|g_KJM3lHBnEyLY%y*P)n0`sj?qL4kHQe8U4|dI
zD3e?UO?H2Vqfj+WQOP?gz8nn80%i?pBcB0
zK^gfEeS$p_7G>p6q`yY(2iC36xgC$q_&$o*9b-_p?Jea<4EvCRjiw)sF5libr|CFC
zL?U2~rZv%GerA1rAU{2`cS836?v17P29v`%r2X|F)9Bk{jNVh+@A=)_()OpJ*B9L(
z`}130NQGeshe`rAF1ixs5zf0G_#MK0mYJcehXI=`S|B|v9?+fITRs2#bPL*J_WQt5
zG^b^zXQo%iNX~7w;=I%pFPEOv(vRFJKSHCo>Ln^q(F+^0%9rK&u`vd14EJw~b}|c(
zJC%y>OSjLb@)~u%CG0(WV@!-oRol;qUDVcI&99G#-$c;qWLxoV?ORam|fvnpT%(saP=V33LL4)MNF{oXS5pZVT3v?m_?LzW5hUp
z7vW}7XuO!v6@KZGbH7uZZebYA5ySG&@hNVwg%zh&OFpS7atdi*b2v2TqYIcEq)G^GuwFH0BbN@JgC`YfP#Rs9(
zm&1Ie)$*ruFS^Qp5mgoW87n^0qjcCRt22|5=%7#MRNsiZQ9Zc5S#E+Me_-r0m6Zpr
zEOP5XNu`OIjP&=UQsZ^roS$D#-}~kIjBu||VS5{wjLPCU*rg^c&_+Z8r*b+@-x1J$
zfFE+ox>{o^Tlu;zLNGlc<}fNX(XJ?$m(iFuWvRAXdf>@Xb1`IeDp%l(m&!ID|Lss_
zuL7Q(b>1+Ij}1z5{^7Ds(4t%)f@vK`*v_T;jC~p-9>bM1_VL};yb5MUNq$*mc#k)<
zI+6I}ku-6XxN0ZS
zp6#4Rlt9`pU88!KPwGy^+p6OCh7cZEp#*3Wy6LLjUsPW-k~%JTJaMx+9ENqW?4M0Qd8wH02#4@M8QSEnV9&eWLCNr0H-5Q^7&-Cisn
z-1vHbvGgy0HWQf3`PlP2>d@)&sj6wba_{C3D@k^eGD9$Q(`q)b9Pw{IPeTjK~P+)oQIALBO
z7;^s|i@@=kd8NBW*K#tUQZSeRw?cb9b;Gds*VarH2aS0$UF5w)%{wt+RY^7x;Wt6j
z8FK-lmkwLAxosFD56Y)yYDcCsA&;`(>;%TAldIGY(KKX}
zLNC12*ji~6_1N<>pX9)5X4(CjG1l>R>pBjP{+EaOVr+8$cCnM!qb|VYvOD;JKTSHS
zdJrwb`e#&dj;~wN%SOhomAtxb7fNaQpH9xdyE!lEL~w)N#krXsnt0?^Ol~l-(3~+y
z{Sc)E7@|~
zpGkOpBNOd)dKp+ebyRn!3b{9b?_SJzHX5uIy36=TSQPOnL;K|UY~mlc(3{2z^db8^
z-H~{6szC}m;J=QfFJ5F#+;`*{&9i^BC8&!ieS5-a)@#O)m~DWfP8^gX?rR_H))v9u
zY?f2t8m76dNN^=tf$3Q69$DXEO6TnnY+T>za%ilZl|_!A85v4$IdiKRntb3%U0~h%
z>|eRnejn1NLZx>_uC+--BgAjgiLx19c!U!eb@+ti>s5cyC-Gj`&rZJEG01bbX|$is
zukyyDVY~73XL%a$UEOwIN0?G{sM!}8EB+wvxi{^?i{EPP{kGL$S)@Hjptzae>n$V{
z9c%5GFZ%t~-5Z3rOzQ~SoM{6NqQzvE-=m^F7-
z<_bLi29LY12zQC8@4N>`6=;N;fl`vc?u}W$8z+fI{X-%=b$y>di?k%v!2ZIrp7KKZ
z3BvS7qv!6<-r4u}i_=;$z2XO32)A=cBQ*bPWG_7{Pb%`9u~C;~C!ft4=`&3DhDEy&
zgIjpQrQr*+fVBP#bEmZY_A0yfI#h=Ym+B(MO8J%y7I`f)_Drq}ZC4cnE!g2TYf_}_
zZ|dSXzX|A&x-b4vJu54n%ETQ9piFWnRGf4Pq%M8NwiNk-I8USWwJ+!-7!P^jSRO_{
zuPAwbyoP=LvIRM8;THOx>x2TzT*IHSco2l#EuleJaXb3!!1K3WUxHN!%dURR?|s!1Z7ZM3T!nQ^CFa~hAD^=D^Dk1L3_)7dPRuaL{uB{S
z$2v=LJ+riadoiSWm3_+*iT+Ol;$5*^1@OkN1rq-^?HUtb2wU0XKwF);O3%i*hpr6KSYRi$jb0
z3Eh7}U<=Q^yi~ubFZ*t7uj4Y&sU!EHdXx0@w0a;lo0cTcy$}5|x!XjRX0rp`MS2q~
zI^>d95kh%%%T7P^LLZ@V{;B_1w5MM&kN7XvMRCog3F|WbRDJi3KeT{Qa&s?!k5~lk
zfTDrJo}i`JBb8ww3!8u835R}^`%;SR281txh(vVYVEsogrJ@H3vAk(&S&F9+?(B&8
ztQC9Iya7ytr+5VHaoc!R^4)aNS$NY04Qt{j%cKksO6Q_nwC8vnM)XBBBJCsYM{XO4
z0;l3HHc-OgIVBjA9Lb+|U~0W3%D(P>!3hhj={=jJXsZ(hcL-YiB;anMs?(M{t$|CS
zo@aaolQh!XI$mPLz86bS!55;}Io{i9VhOil9I4R-L#@|2-`fg3#ggIK^oVb`;DyYa
z{c^@t##2p0a3NqybHXD5#b)}IYTAUt+RVl-T5nyt!3S&p&djNe)*icZ4>b@vr&45Q
z(emx$v6O-6$KP8Ue?PjcyT8c6pL$F%ls$_@lb_Gtuc*awSh42pwV2LVsXQ?)hZw+E
zA??hGLiL*}rBvN|a-h~t-afM*Q#YPjftSl;YvW!e>)bRT*QydLOvJlN*K)eL63PQr
z)$MB`H%X?i(0-pcCxel1PStZm#~PVWUDgn;Ir_s9&+{S#$VOx9&9N5uic=(_bfOL#
zbSOMYr~0>W?(g2j55H!)Smjxozd5X{UCnK-0L!YRJ06iu_4cnnXg=b
z=IY$mH9+9p{xg%#r`3JpaF#4e<2S_O9)MESYz%U3Zb!pQ)w-~jrm?!L8;FiecO
z0hMO_lx?PLMJYz$t<0%7DW0Fd;(Q#wUj2DK%r&91w}9({`6};m(NFRx9TdV|+V{vg
zMrJ&K4#T5r}4f8}$?cxar4wKUqPzOFtvHR}Jx}rR8@)l+122JKOcs-4k
znsc51?NM7{x(jX5=R1AALoSkQmft#*53|e^C
zbNPi9$S)*16(KEuJTB^oje*?3;-y{`YK3rV-dSR-b4BuA%&EWG!PtAqRd?+l;}Ur#
z548d3dUA8L*MIKVa8*V1$)iZ9DnsGb9n#nPocz{-aIx1rj+dMR>EeTtTyuXj!Me
z;BdvSzTi|YBQ{D;zSysHQ7b`h{d?7kx!1#++$x&rimDQTXvAqGbX?+0}VUm}4*ya)wht6!7$beO(
z54dnR7UCcc13nCA@5(z_>sx(r2tQ5pn3Coo#O+vgcuqUayj8MpczpBrK
z=j8wyQ`7jjT6gHZB&@_O6yGRGWh5?~Bm@cIbLh(S_8uR#;f~6to>K9tzZn~lGwaOS
zYK@yqRx#BgyI1;sYw2UuaXJ=F!b$~cpLBm-k?l~V;2DATJu55PX=vOxO0f7d79Hy_
z0&HBC$D$2Cs%dl*$50t2X3hURR7$kWKh4=ENK!F)`>HidgfHEE&8!;5H|6*~r<gIGR#8qSzTDB=&k%j&DShzut?0G4R$5lmJmXZOp4>s}TM|~^hB~(l+gS7#=?sjN
zd%2EHW~)J-e%;x87gZ)XHG}uh!0{Me?8g5FpdA+)iBF1}_fi-d39h&MbSNE4&JUEO
zsSjo963)dsG;)%Z5p$SP3Yzzn(VZiv?TyroYdAFdV$UINs;l|5Wrayqqq^lVMq-e1
z6bi;%H_2Fdl`H0whD8?jA?V7l*5S7A`8-aaQ``JK9i8`;+vEI*&iXx4eN&9
zL)KuE>D0|d4AQKsn6ifyQtGG(KlC0GrTgrRK>;MeO845i4K_sc)BwJ(&HSs35XJni
zJ9ed}HSEe&f{_W0^0zmHw5ry5Y8@5p;KRUP&nrqD^wqV_B3GZSsdQtE%9#cUJ$r%j
zb^-3y0Asw*QH+b|3Jf1XvQ@!57}sqSl*F3kkzGQH9(W>q8|IP@+Q+%Fi*C+bIIwTGBA!+4hpvTNy*^7VKL8wr#XzgnAOL$WnsKg%K>Gd3MHo0>{%M*6ay^c
zKeXuHHXkCR#%VJj%H|%6E@^fSR#deQuA@UurB<^>%X)H4snRwqdIgto`mIr@#mo=
zV+k%9P%@B@zf&??nFBUnp(Z8K+39ZW-cM&ux2!NN$ZkEsdPc~`2e@k}@pwLdRX%Yv
z;C>pw{GIcgCVla8NybWKDe+~8gu6>1Ol5D4ra`3Fq(1??UW%SgoxH|=8$=X&Hcf{M
zxFI}tW>w_S8a0C{Q$B}w=JxtL$4Z=Y{oZ(yxuiksyt(8-YrMH6MP-zt*75gp;bEcR
z0sQBB@_MM3fK+oyOe-cJ_;5+ao{PLUqPTA2WL8=It?4kA9Ivl5mn>W!QPOmcZI{=S
zs7`rL;5JTJL(W_?mt1$sree^I-=ty4=q?)j-a4f2?WP+C(sZrwf61PYu?TNsVPH3m
zQrTaq?Nt+=4CKf${F_t-rzm;II9Xg1TF9@QrCd+$k4(vsQII01xoWoK!TIx`v7-z6
z-+kXWJt0{bbYZAJ7&iWmxSwP+U5&!hv2H1tbjfZ-JlS++oAnhnIkRMaOW$<|)hg$9%g!+G}$&E(!vI=zEm#`m1%ilvMB_sE^P!RC
z#=7W(?QgUaNapmZ|260O?Jlh=i}PdcjkOaQ^!Mzpvo*_Ty1P7`@*2$h;fU_-&K||X
zH@#u8O1t_Bo8)My2bwd#&w!l`E{-N;E5lfibSHD8YEW1~&q_c(<<*Sp1MgRWn_BJi
z5d<>tnEavo*9ZJO7&A;I(v4{^3B?_FTj0%2Z@kUNs5JD31y&ZBeb`h_yc|9nXuiJs
z8xYgH%_FO4kAHD<&|0-OHYd|tVlw5z_}~&o?pBA6_XZY!aZ$4Z7lGFr_Y3`3S=oJU
z;S?f8z``w>>d}>@7uR87Vcp;&w~|1_CaWeS?LKn6PS|gkyO=nIH(IG-n6woo_9vM+
zrupA&$V0o!$?#uc_GzDxU(&j%_=hJxN9BYaP^2~yoPW~}E5(Gf2$n^ecC6^2>h``U
z_w?TMx;+cKKewK9-q_pXz>>B_$Smod`)Q;XOFe-uWUp2C?`Ilf%#LIW4)mvJ_
zmRWN-A77B`bdIc<0F6dwBhl@D`7h<}z^M{iHscOquZ0ovpyuUkz^FVsyrF2pk4nxu
z)-1oAqt^LBis$I923g!d79fJGpQr9Vjl&9pmJsNuBThG&Rhy7C)SIB(D|l4H;GQ<%
zXG6iMzDv9`?QVpam+)du-zRk#*NSA2^qH9n{_5n`8-z_UzSPizDUUpWBw()CE+$Xn
znWhZRM>7JQuf@g329q~@E*~`nK{Etm$cM}ZVrZ9e&QZ2ee%r7T!d4D$s=hp5*47wJ
zZW&koCg=r2ds~m37di(e*KYuu2gTh-6+tsR8JwP&jd3d5gCYWN^l~3N6OrUk6o~N;
z=JM}f8+nXWhD`b53WhNW&ETJ5DQb4foD_*@Tt|1z3SCp-~a
z`tD^Th~A<*8sI56htcE651vEdprkd*f<2t?qE;nPYH;{#{{F-F~)
z0x@z1>49gkrDe_+e69+j&kLn-BA0WMnEw@E>{o?>g<*yc;4OOD1<8_h(*i8Y1)Qo=
zaY{J3;`{(OcX{m8J{XJdw-h^uGDI5OtdbQ(%FRNV7A$+_p&H)OEI3bKoQU8t{yF>;
zLKU%K62UpVCt?*bx^n-u++OkpGpkgYNMF4sU_n>)r|DAyxIF4EFfE?xK~4ixXssH+
z{?)x~m|-St<^KJ}HQOhDa4K$Jk*M^qU{vy7nQ=vl@TiAO@G|!vLoSKmsyN{kUq3^n
zl+}ip-$Vvt45EnH{e`6k52>)RJ~?THQ4S8RhfVPon9Ufsi~F{n*TEO8_#pdT{ya&j
z^yiI#NbPR_XKnD5vj4YKp^dpFR5mR{`j2(5uI$AA;=N)G%w3B#Fn8oBut_IS1Puu=
zv?lkp!161Z9zs(Q#|k%+F&?j0`UW)l$Ul{H(mp=eD&ZJ_0p9cu2I^%eU+o!Qt`S_M
zqaZ&bTm%DoYMiu5Q^(=W;ETZ50NO#EOIw@?64)ITh#^xL1poW0O701dny
zt~B0frr~+LAeA~*Q4(bc=ve=^wRyY>qdm3FKdGGgK9q&}jCoM!Ji}D00W*+nt}yE!
zB2fywJQj}X9kPKK?T)2D|D6Ccl+sKV{caq_Sk5NBQ!51lB9+Vg&;m~p30i`nHPIGl
zojBNh_gsU|3k7ro7!~7qH5gT_Aqk0cKie6w;BBhW71_Vw1DqPVfdz8cw+zHcGy4;W
zQNm))PHoSY`a4^*5R59Ts@9*zHHU(UtqMBDxYM~_w#jioxQ{7?UnO?4#nbx|F%OCt
zE43?BjtxcHBafF%1pXBtEQM7vuBrOv{fS7y_QV!U86rlP$pI*F^B@2$!7ro{aDWI6Nt_a{r9lGH`e$jS393!hQ=3!VlO~ixB2P&8-KqoUUv;
z>#~`GQ`rSsiNI4pyUFQ;wU|MQ%SW5w|I0E$z!|F3fY165mgR(#moIUML~UXN(_O&@
z4kC51%uHftZ)z}m&2oi<1$v`5k17IhgLpv0TgrUuK%65^4}_CEJrVeWRlYo^dIOp~
zsOCHu5%>Z3OQ1JIU63h(|MH<*^;2GGVg#$Vd3pnq7ioJo_BQF0#zdm{BRen|h+v={
zX*}irQOc5!9}eVsq0ecEv?kGd8pAI#7MGx6%78(7f#Sfk5YHE2ASnXG$`Gf8;8d}u
z;?{ok?!$G!S3UkSjQ_@h6+bi}XkernmNRe9iRGNo{wi)izrR)s%oMvQ2MMs%Ul1z?
z-(KP>2Rns7Cmy)r?b!iV9Iy;Y+jkIQVC)fyLA;GLH1D2Al?P=TImxbMtH7KWI>HxM
zUNQxnBC_SqlSb0{K?_7*jxLCloy#-yJgD!P71uT#E&sxRg1;8YU*ukC(gQswmX7H}
zrCw8pjjsx!LuQd%UFAQEZU1T=m=t3S3rLVLQ8Uq+Fj|+|sd3^%*}=?9AVyUeFtjR}
z(Yq9aFI2(#q)iIUso=DIx@EAjgYwStaaS9-7zjWh!fgPih0*K*U1k&)FpXFZz>!!W
z7zmbqY-Z3kv3?(1{;PSwK^M*7DaskNRO~dFp8NZ}uRU0^5^U
zCmn`LPG;^JuLfIntQ_4zMKo`p!KiBCQ4}czDem)&j9~LZS^T`+t%LyMc|HeAxdHS~
z(lVfbz^IJ>)juTNTY3yXsq2?jGA_w5Y*k5TG+j?TnZ%OHmb=iT*0ui|7oI2&QN4V7
zRWOj;sRS1Q@k4TU3-NYz6FrXd;3>)i*GUghN57t%k|rjun-^e*M&*KX72|={3jBgu
zPw;;Z$k?l$HHRMv0nN4mNhmc>!K0ctJXPJaAvJ*DwkMJHYu)xxxK>Cr3L&a45*-6o
zG9Ymmsi*^q)CpMB<*{c=Rkv(?=#-n!|0*A0VEP!*3vy?mXm`t1YEaC%4dRn%+9ZFiXyZ2Kapns|It
zJy3g2h7tnQ+Fkhj-*S_R#YA3TCpm#SOo~Xi_hO17U!{Bd1RNFv+i!3xB#L6&sLpmj
z1~=0GtT_GSA=|j=<{zTATo;1h>E_k0O%SIPe*CFThoa3#^gy5uB3uTiH8JPH3q2#`
zco4%^glDi<}6n0
z-hOEr2;lMONXq@rKs@Qcr&1UmWcs30sS=2xsHxrK;+^P5!TK*j+F?>|?$>Zc;2r7d
zec;ng3FEIsoWue#p11%$M5}fOSbPiGo^4E;ziOuWcc0MQ4l)=>8wMbY92!6tJBUDx
zt4c81AQJ0Ygechlm_UqX6ZX8&UHLsktDtI#R74WZHwJj+{z@SnWr#{yu#{eiTYxO!
z$gIr)aQ4f!k$5hu-~f341&a4shNlSpdOef~ydE{s^F|h6gB1yxBI3<|Lq+u0M}t9%
zF)x$}4Vl)YD9=6$amU?mfij8mwy;(w3UI_4114~)+U8#Fm7kA-TQC4Lx&UZ^&@Ygm
zkQ@eDW3Qyp!HaMBj=VNAEk-kme5qV`I!U1ZiyxGIl;=>0jZi7QFs_KSK?3|hNNqj`
z{={}gp*2~lCIWg?2*lvpDot*PGpi0@SfgetXcD>gNM2~9eM2(tAgq_5?-UUi765p$
zfw6uArXo>R{)1y%LInPf2}ijfv!xX`yaAyzmqLOfw+0Z{k}0ECnV
zz&aE@_hNo20SWrPrUwBsW&$UfR2U@wYlWn2dMye@l>*W(`PuF(hv-$147^}^35qs|
zu>(lWeffc)on_*G@MN?ah++6q65b%97bo5Mk!p$OpRql0{e>abyfq-t_gBa2WT{tO
zmeGJgyl0~L>5hoNs^1&^tB+LjmSu2a;3^9N&DIZbzQy^z?m_
zYWi=LS`hn{4*d$D%u{zOk?mSsT@#hC=Z6Xym3Hnuf^u+6C6Lb<+gEf~PHt2S4}J*|
zA;4YzFb6cq9}vUn`}x{$(Qipj5D=WUIx~b{iz=v;KPlF@#i^4)_#}~i;l4?n%S!>c
zcVMy}v`OPtnlwM*txmrO31amEvIgzMgkw6M2@sUHs7xZ7RK
zWUMTpm4n&l_4xATspt{Lwf&$l*nxQcAM}|6Qmsk^uix%EXLU5wU{sH5U?5tBTFQ;d
z`}@vlhg85V6&w=~qMRDmMtpx!aLRZ
zs~Z^TX^#eG>^%Pi7qE;X^)9YVRHN&kY^lL*IB%3F&}2nX-uoC3UkPl{lO(!yNn@Mq
z(u`exc-dA_vWPF(GFd6Ice8A#iGP2){q%ninx=oq`F{k>nMi5sNAHU^6+PuJxs;3m
z=5&#^qHp^+7{)OK$TK@DfLddD41iKi^86+g!|wqIP%j4A3%ml5mE%90k!D){Px2#Y
zrw%che)~TwYe4o*A>{pE0^4~NcnWF$1qwS(S
zd|eHeS1}!C;37+bLcJ`oEB)h+qXCh!Vhc%Ir=iHFDNZ^+pa_JTZb3kJVde`YNYJb>
zhFJrdJ?cOC1f`~-@?Kx7!7B-ja=!zbdHRU1h`5%u@`YRv@i{Xww&EKpRM?N{$G%JnBDg3?M-Q5iV*l
zv}_=Vl$kJo=oFE7prfqy8A$ySaz$ftd=L>_fW7NLy!8O(0fa_uAOX&(e{rq1(4}d=
z3TYhQbG;pTt;S_}Z>6KYi+NtWzU%naSNA{Z6PvX_Q5zmR8z6BXaRW3OpF1k8$x9No
z*&epq>7q3kf^z>D!nubcOB&u11c>!N>TDwSzIWg`rOVx5pg=X1Rk>EoeMeW==uZ$S
zy*1z>@MG~DG~c;
zf+z4WE?N@;Y9LBZQFf#KxS&^VyD?b=xMTRx227g*AY-s2VN+OAqC8N$mQg*M1;8Tgawgb+|+2K;%U*3#F273uu6gIb7k`B$8z
zsjrqYiW5iLmk#m3`D@TA1p!cj;%54Xxd3J;lE1%Oc1HozrUxXAboLr_Uf4l
zR5vsKF>OGJ0vBX}4adYcD5aGonE1hrnEv=qEW;2_p#6Py(wI~iHF
z;dp0hB(j31?E@~%gzgjM(@ugpHZWoUwTG->bv4xPBS0WKbP$ZAZUtb9z?b|m1P9%?
zKfozNOeidRH2qkAh*;?kN;Hs%5hiWVa|85@_5Xtm@1;G)YG*m%
z1UdkD+7VwP9#IGPdB?232-5TQ3IQs~0Z5w}Fn$XhhU-Kb)5?5Jma_l@)ne1H)37IJ
z?K6tN4>RH`L;N2&AqAwvDb(5+SO1ERf71E?R2))P?qX&CiV@$_`37-VBcQ4yaQhE6
zVsddQYl!}ifTaXd6`%cF^?mYo_}Q2-YA6i}WcO@nRt(;Ho!Dfu3zg9QRsbDT0Xj5i
zGK`I*Jv;>#Qnq0My-zchEB#-ry>(nwUArz!cXv0^4bq(wf{1{0iF8Rz3eq4AQqrAD
z2}pNIcO%^mQr}oU&l`K6z0bGL`JI1suEmNu?z-;#y2hGQThU2Qo5SDdoqN}tU{9xi
zn?Fc?g~7%jzphb4@9LNG`Is&tddWhR*;)99R2vxoc(Q;DnSN0L5mlv#sZhOvm%u+O
z8g$huIP&)7g>l8Oolgm<|2Pa^HRO5A?hvPXm|swH5pYSZWf2h$a-Tv3d;!q2?ESjq
zDdPQa;XzmPzk>&g8e)QUj3=*}8(WF8VBiOIfZ^m~ZGO{t^w(#l@YHuTqD7Fp2DO&K
zoUZf{9Px76`JaV9F(~^HbVR7O_8pUv%L@uHc5dFp_~8rgx&9z}l(FHB`MV^lWv
zl^B|pB`S}_9j2O@+{skB<;(sC58
zBp|O3ut9nMOD31Y{&#d3@r0(oLvTT2T&+5U0cH0R5%74}eGh!V#D8fm5{<{y;(^>)i=xY>jyT
zg$So$;0Xelpk2zA2{(mvNii6|Q*?CE8Lc7oUE)c}Yq5&LVw$!w3`0NxO&jhO5bXa8*Y!`u1{6~GH8A!8#YQAE(DpS97)fve7|s!5GOnU@0*2}@#fGf_
zpBAur1R)6VoDjtZ-a+_Zip_swxqxB=99Ity>Tjn5XuNvo$t}yk$n+0ti`VSN_i3K(
zqxq$zZ5G2jmmWdgp|Ee0i)$Tv2Ze7dF`v#GIUWh8xq`Vx%I$xED?Qm%A!2WcPpKq6
zgvacI3)aFWoZ>Mu1Hxw-3fKg0d(@cncOMUY<^F@cO29p}(
zjrEfX6wi`RU{Hc^U^z2tI$uiD!O_e2N`NV(U&;9%I%7&12{H-HSyDxTZ{~_``>UfF
zgovGr4k61_XLyme+0J4S0o!wWjDT@wZ$3@b5y>95?O&h!i;M%wX>U@xKdR!(A+!42X?G~%_zy{p74xq^OLj^$ejGImM6{arYTKs!8QOc;yb_X4-GYqwO%7RW@XVP
zPRUCLG_M8}{sS=zu)xWJ
zjRs$2>%>%M%`e1_5;jP;HM2b&N$o#tuEKJm`JC}3GTo)8Ky>sA=y;=)Pw??8vN~Ya
zdqu6f#I7WI`3n*af2kwv1`u_`|BWoed*WH9n2d8sJDR8Z6Um$LAL9vm3Wz+H2grDG
zf*bJ5I6L|}CN%q}@#78L^bbnZjVJfoP4l9jjhIY=yIXxLNdYHDZ=sYFCw0Hw9A7Ny
zSn|dE!1!xaA&2#^&6e)@*RVoBEjv*n3l(2@PJQw$%;XY+O~i(PxBlPoVpkvkYhEk@
zFgak{64596nGOj2dBAA6=_R;Q>bBj83o}Aba^g>LrL(thD0)u9qkRr~gHX
z$^S;?Fu8}L9wJQq{seGpk)AG8-*%khMT-8LtpHX$tU}~A*PGCaAt-pP*6?cC*)NNt
z&9pyj7n&Dk{`$iCdi{Slvz)Xe#uL>+$8*+PAgX1LQ3;%oHmkYvT=o!scm5|Y2JYsX
z30D>Hk5T1Nfot(A5Wj$6QoDgT0rNFsIi;E=k>}E43ZtvR+*~55wg0XC=Y#-=&ItwssXGn}
zhs6&+9G?IoKy_)mK?8o^7M2luAjIsE1hgmrSu3%hYX2{==n1J>yQx33DFV7C&R5AU
z!v}Q@4JZONgog^d5=D3PLhaBPkXLLG0K4F%E|k1TNDBX>TJn@#xpLKdINId=@#~0p$-gl8;){mxFK02|8?-<$Czk&zi
zj1FjJjM3XT3{>%Gl=ag3h?QQ^Vnhv!bDKiNoF{K(^?=2Go&bpq8}b<#|2!
z=OOvXkLxTFuS|o{0
z{WGIj!vKZgP{A5R#!QM2l%ksM6vF>(6d84ej3WPn3>@%D7+^HJV}w;)se=MqNjx3aOnOjqz%
zKz;wsbWt1fZQ-#J0-fZL1T?727f}D2KKOG6h6JsF`U7BqI_>`y1}?9O01W(?0^>{`
z{NGafD`Uce=vT9izow-B7QCTQZC6d-8H{Ht&NO;JyV
z2yFa}JuG7uZ(FPb7$p2vv>_e*U)<9;kJL9@Dbat{eNe}Inupa}pins;7Fq{HzYT1B
z={gpEdj5|I1QX+FDCK8H5@bf`f7W}FmrTj;NAcIyu%uE7`Pr#QYODS=haf*q`drto
zc*-sFW9q{u-TEGb&F^*jprGh9>?x(pWikWD*{lq`5mcB8ARcfel|~|bUjwkCS*9*s
z_4OY+zz`U#mJ!sXzz(pTcK1WTu+EmltF^~z=ONO~IfeBr0fvR{xmi(^h0YCT>8DrO
zQYNe>ft}K$cHdYpoRgsGhX1G@kIKyGkm>Zuqk2argeko6cS~s+j@J9-fhA1Qf9_fwt&=}ZO
z{>-1=4*c2gsTccJHn>tl5eO$>191E9K>%N&7;>DY{@4~BM1c8+u8t@BM={BbZL}Yl
zt?tC5H>X#}l`6^}VefbKw0C~ShYcs~J}MfXT-2#1*S|mCp{qQ#Y~!E?W%q2d>mP&
z-4E}+DzWd{p6|M7B4Rr{+$2P)&G{-RmB{(y-xU(H@&BDdvKBb~>)#a;8)!yqG15X<
z>J{`Y2fBX@9*Skp|0S1H4OW7aJ=q17X588kioUg|aG##D%iXl(kQKcP8CvlVDljSD
zJS33A0Gv>K-Z-!O{~ReQ8yS7w0{%~gc7Yitpwo!Y%=VN2C&2`nf1eIRt=(D+Qg{B^
zmaB?6`f3j}osy^$$oi8hfc2>p9@F6f%6UGeAI?N#4YZ;WYy%(}Gt$9Mrg<08tD*`4
zp3P<&Xd`o@C~79H_EUyK_M2|IcHWL>CtxqF|K}RF-Hv);7wuOpw@@xCP3WY7;7)EU
zEZSIbqj{{f6mSYs?l^^&P#FL~PUwzxp;TeS``vM_Rl4Iimt{mCiizqU#e@vCPxg;u
z@}2gXJI+kCy9jdbr|vk3(|;aVh#*UsH)yNpFTk%Sy5scnu4F?-55maRXJjHs8GzMN
zs(v+{V2Q2j%!&7j0l-L491u*pgI}m=+R2&gaEeZMXi27u!)>8LnX~jsJ?xKYbUXb%?o1@fwRDKY8&qBd|bV
zzghcJB-l*c2~O)EvMbI=)&zX%UyK!*8i}7-yAw*-o7}Ph?!_le0mWGSixav^JYAtK_1Hf1AAfBfCfn_U{0OCZ<=M4U
z-<(A>3x;a@+eu~~JQma&d{>x@nF=F!97Nk=IzY9hut#h?Kc(KFVb{n0ZLf*4j^oElP%WTVb;X-?>jLb2`x
zpMZCR5h0q5WpCS$v{f!M<6YzhoEN<2CyG9B&;$-b7*?<7PoDLA;NUZAPoZQ4_UQl7
zGfe&iUG?GQZ@LN?o#Kz45zbJxzW$7?x-AYe8>s%74fc>!v)f7XrRENbt12Ab!6qsi
zn{Ov{iZ3`YLmB>TrQ)3bDt6h`JkKb!Tn
zY>hh;{R?pAgPTv`<$HmL|bcT<7z8F3bOMKM4a^vr7*oIMs$veQz_)Appj63#J
zA;#v~=pA!q(ve{aJ=
zXO?EBHvD0wSdjKgSl>J_EP?389VZBzRY}lG?H=dLZga&PE%64(2<;XwcJM2XDXW?H
z+kzRLv!hUYg`+nyF4RG~9ixUBiw|t$Q8Os-t~6X{GxQ1Oyp#3Vwp6vk3wD35xjQml
zV@B+lIeBqEAO6J$ZB6VNSCt_-bkp5E
zb{Gpo!H;?M=Qb)au6LVL=u;<0tpP-C6QlUtuOwbSIK521n{h&0*77DTo*BA^wT)9p
zVDiz~Yr2J7qi!RQ@pX7G<7&8w2a|HtK9#?~f-6_rH$zEpU(cm&X~i*c36{Z
zE?b^A%3{g(@%0Uf#e~i)C6md_>3ALWZ%-!1R`km09myusO6XsW=Vw6myvIeaq>JU9
z*4Ia8owEgj}Eh)BzXBP
zFhOx?yZ&jQtFY_G!@but)%y8vB|0g5i
zS^Ku9<4Na2?#Xx!mUNm?r-$ku?kfU&@fu?GWMGlT`v4G97S|k?ZgM!
zeOOGA$qzPo-ct>=>%SEVtBM)7Jze_gle)Z2u=NF8z42%G-hj{|MSAn{y~pFh&iP$I
z-)j+>^po60w8ch4f?)oZpGOl*-(A<=$c?%maT*S}r)MSwX>=dya*2621`mw2t+qX@
zx;k*J)tf51a(1e`x*9i=R7ocH^lTMzHMzLj##YD^I2uZRC30+iW~KS=Y{#%kM`WTCM)of4vhIJvwbw>t%`p&p%&p+VIVCyd#>=@tN_u?
zgm_v;bSZCaEebVZM+Lg5y8biYj|v2D6JpU9I0MPwunp_s8!xI#1Rk`FT>SP0j5wC!%I4!WmodCxiostdIsSp+sb^i#~D$tq&?viY*%`Zky3Ef*Q_XOV)=QAV3^RGUSWgo%%VTWAlD>80B`s635Vh<
z^%#=pitj^ZKRRO=#}k-tE-3WNqw!4rB{jb=7Ij%-T_NSS;a&ZA
zUX_5mW!9$IiyruzuP?zcO5Ir#zKyk($B~#VR3&5PIYGY8Cm)Q}bC@kn)-#+V9a7^G
zNXa1-sO^GHF4Z)JMJ`pEE=S2A6nHJ->Kw9hRyax>fy!9U`_c5_Bzlzk=f`#N_gC7m
zgpRH8oNvIlC5^~*(i0bvyO8Jn|DmwpNPHNC{KxhE@d*
znwA5(U`R8uO5`*reotP^S~*WVgWvG8k=)y2AZo^-dhsCnrBTYjZw#t#11pks(s|S9
zneAw5x$nx2Q5e+C0-`ek@QHl!%cCs1X
z&?#$?zfGqgm-3p#x8miOw@3_)*v2whPyuh+dny!IzowrwuJda-!s#Wjw{_Aeb>iDA
z;F!7c0P6@04{96CHp8e8j3Nbpt;^F4#H0dXt5=%1Nmi-GbOVC8sAGgIe>?pZLJv
ztqVqbz-z@mk&~O;h*&uzt;2+ci|DwRVG@&{stY`PbNf^?N=+Ad;MsJT)Wof%1FUPQ
z7~Z&z1PSx$Dm3|EH8y8TL#=^P5X*tZRaQtKUYNk8f*eajF|w@4dW=BSBjiZ4N`hF(
zfli#DEds_1x8=hi?0b#>fx%{{dK*g@;4RMQF@d-+%`?ZS)?ph1K
zF;gi!G~FB$&hCj7UL;S7Zqp(`Gz){b
zbT0xs)!9MfwhmHD27rmb0Xv)6zTG3qk#_xfko9BHdWJ%AGsP7%&%zf+fQ(!U4}@YO
z9XO!Vtn%N+%0`t77We?=ii9oj91_70gz-cH@vIMdR0uo}3yK0w5m*u3DmbVT>W{)G
znurH+kr!7fU8n}B2MLfzrP==sTwF>JpL)0#?r&46NWaj6=&-a$QON5WDt&E%193Z~
z5P%Dwrd6*!ngiebF>9!#hVniVV^&S8m{rKELf<*0Jj!rfP@I3$
z-h3}5g8YNcEdjYyndcxVo};gvkxusLgaVT{$=e>ATs=XX`yEK4ljo5bSx&ixq3NKkc7d}hQ~=N7TT+sL;Dc8lzQQ8^
z`Z^SYxK5aZ58vtA+4T%{q9rH{i7q?k4BgFEB&KGwN?tEicd(|}!HTp%Aa_|Xp4lxr*Cg)FO55=iAyoZfXI11~Hj>ER+G
zm&yg+QUaBx-NKLlLIGsUq={~1hpdz4M@A%FAz)wv7R+LqeBR+)lXge^e-C8f25R$K
zj#%(fyy&JyMSNC&o+&S40#}Pdtv-K@
zip?DlzffoIs0Xm>fq+ow*8?$tS&c;xGZ3T10i%>cjB>zxdkvoW=Cv^{pb|<2Lj2kl
zM0Z3Z2r|1xfH~8DLOJQ5C3tv>PcC>Lbzb^?qZTQ-dJIg({)Q-~&gFk9!K5J=)D1??
zA+$)q!v5=cpty~l3O#EqRmVezBzOoFFc93|75Gmn{yYBVXGf_MQXC4o2p77agxunY
z{l-DflMPmrR*eJJh<~Nw1p-1P6vOciB(fu{O(0==nJ;0Ywf#Cq`w6{Jpw4Fyhk0Y*
z)u0mpod-6{H6XH3q#@nWZ&LEFJF>xK)!`VUlPA_fr%vk+gOM1Lwca53HAT&V!M2%!
z9b7;`AN0f}cZwz_|ByYCfVf|~P1!9I9IeTSl3kt+LU$4yB*+n4wsbL$(i0`H;w4D6
ziaMvM!Uf;14GG<6z&$hvIntH+etkC-pr+q#M{jkwZsp}m*|}1P3w3e>zjS_OU%cpi
zt)1Bq%=CX>hz(jpj-hj;TjB1JP}lu$Jaq4nO3d_}k&ulWDJpL1D+XhyWP-I*#@5(9
z!(|lfE?rnV!0Dnc_DoL#7?hgS<_iRli7%hr696w%s+FrEGBom|G0;DT-RJu&CfO$Hk*(jLp0cAI1gN4$`nDlWF(uqKxU$+Apu3HD*QUjoF
zZSD=|&1Suwk*aFHxpje{F(0V-cRnbAFOPyG_!BmvKt)K*7eT;|nF&0aZMG&Q
zm%gd|1zcytGhzfE0l7gL?H{*}L4Z#f#3-ZVr9QWCUIvw{#K!KX?x;X*n
zd_@S>V2uuOxaGMcctUk=JKC3JW#h7B!^%;MpVa8#2SUu+TMG3QT3bf)0r~)BxOX=9
z$Ry%RqK|J1h(s2d@LERK%w6j05t_e9G<=UeM4syh8wMEv-Z1b8`}F+p{Q^h?g=;h4
zOL}yAqC7h|;5k+#_R9%W0you3!NixDbls
zYopePTqi<<1cgHgeIYW2F>hfW7k&?Xn{QzXfDdx>xw^eO{b`g7A+r8#H9mV&RnK&|36al4!_h8|%T$WFrp~)*
z#qOMhThbQw2E#}9fA4lIg6ov%T{SNbCo1{xRpcz@{Al@N?x^t*ZTe)gpk#8tf#_$&
z+vTvFl2nfq$hEz)CPKz%@15AIjnQlcMCa}2gESSFXFl7Zjq9q-S+sE@9ns-$xqT~1
zElE|4%~gmQ?uqBzf3n`OzP@(6Y2^a%eJ9=!4sVyTe|)j(@kG31=vsHWvX4a7mG(Mn
z_)|CAOnWj(@v~eEkKOp9mbYQ~VZrOV>u;N8-?vYga8gr)kO7$m}UvJPJzFq8ZYuvv`19wKamBi9G$w=E^PtzP3
z|MC!33QurchK{I1Z^~NHsz1B%)Z22(!ev*^)q;RmMq)Cb_Su9cf)9_X4v&d^ql*%s
zm+ggVa!7gVh+F?#>yDr2gDERck%X)5de6;enO`6e8+=)t_s%uWZw|poJxztX$
z%TVs8U*gY}drsqPV#Vo8jyd@f0y(LMRy*(-h)6by~V$V13W6pJTPNkQP
z+Tz7l)tS9tEHd0Ll`4!e%$KE(O^=qJgFWH7%O#(sTT}()PJ>zJO*+(#eU=D(Z|VeYQLs1sS%dbIg2kJj>{f3
zHP|L#!o#*6;+Wq(n$kxqk9H;)HS+w#-HC6Hes?#M6IGI|%7AoD!SZ`_VTtL`^F)=Z
z*-4nnLIpmpjqyEYvLXXdBFnkiv=r_vT0v{aTSvO90+`{6bL#oy$Ge@!+wuFM)7|l*
zyRY>Itr!Qc9^&^-HOU5Tulvq%To+Y+7#|FeaWh0&9)1Xji7-89V5n%F4vy?*x!8MD
zp+NRQ*jl}C_B*m8M{}F#SCaSg#6?mRZGO~A8>-kMEHOErhVd1iXc7HxxVTgiwrUvu
zXs~2(uf5XZJMoyp&Qb203a&A!8qQ!p{2ViU6x>gRe=d|PqbWUuJo3p)3+kuFo^bvV
zw}J*=#1vPDPDvYA`7SR^UNz|tb40E))x1fbCHO(vQA?%O!j|e^i%06qrg^r3GV!$W
z2D?c?ZU56D|HzL=qB~p-4-DQe;t>hP*2P^!2iVt4dA?Z18d#nZ?B8#uX{4}85AgkI
zgk`-Ne&|RbrC`6fw-!oXGFa3mHcW4?yytAZDI>be3`%2?$O%uVY)=Slb%%rZr&$OI
z^u;Ww`_iJKWhfa+tG0Z@@i9g2+a6{7ZpBmfpxS4ryk^!c0GRu*Ul
z@DJj6nZM>Ab%w-d8!lS%OTw4^&d$$L}5u6=nT{o10$cfweBf@LS?SKdXxhrWh>kbegVD$@oavi7F)q4q}mHZ?3?AK4_kQGhAd30l|)gylNPoHFs*53Y|x%_
zZA^zfC8}3$4yakvKT1foo9wcx>b`8bjjWWATHMP|CUbn#C9?nWpqC~|OKLYYlwDZ+
zW;>B$pLQSS!8)gbEp7_;M{Ud(R_tx~f+z{qP9c~wVVXjhuF+k^vQ~5MR7EMwkzA!W
zl^d3C)RL>Y87WzC-yVH@BK(bVd(KTaA#-
zgG0+5wb=~eI7c`R*B}j5@MH12gs}EtQSO70M6r}h<628XCAnl*HJP4#{km$i0#cRt
zHAp-M=65;+KJtm)V`j4)Z->8ra!X|uRwM1OvNX;`WV_wKSEezwyCrxvsCjU7L5zA%D|-
zlt$c=YB*Toa5ICK38~W
zv(fgg5s_7Eh6MQiBW6q6G0?%aV7vd`8xd=J_QVLzmCTSR^m;qX6zB>9Y;*yeM`LS>
zrz>`bXsNb8I9w5$zVacOaDPrDVJ+kSmPjBc#Iqt}ce$B_nn{o9GiK3N6Ngi~Lh5z&
z!}xM3tmWylJ7Z9zJ;TPmO|*Rt$K!n3mB2R@4DTU0UkmFWCsb3O1w*x|iDj8(c{RCF
zQ0Qr)hvhTx3$to!YKP2p=ksmrY&~>7n_1g#n0j&7Es`#OuUYyvH7Au*v*>Csr@M#p
z#)8}avR6l1_qRnE|F^n%lRhMC^swz2oxQ~T*Lzmj=4E{f?LMSKF4uI6#N52CHMa+0
z-^&l{jB|rk$68p^YsAD%r{?Or>>6!V$L`B&MZFk^^@$zG9=M<$`rjkjjkR^Yd^VG7
zuk09Ct{=5RkRDoA>V5D+_&C^gg1k0hs3#!PJr$GoG|Tp3GhoImy^~<(C*R?Svv;e~i{ZX6dbR>8
z7q{kb@`RE&M%#7N-c2-5(#~Vr?&KUS_t)NomCa*9wzkl^@vTMtv=~^Sr(A$69R`g>SD!IcN``~x!W7+gEO3IA%nQ`A)WHsbBV)Pk<
zjop4jlnu2a$LS3zNB!s0tRY_yjJ8i&8J9*nj^A5Iw_IQa`5>`l%{HA2yXfrnqG;7_
zR^LrvPmp@5lTAjOZrk#F=AzG%cH6B5Ss07{BjM9YAMd&D^7ky?VRY|sVV60CZ6%k6
zb=sG{uIO$qn;$sbUq3X-6Ohe~$)i4q%zp@{r)3pj%r-?W*ZuwY?dovIaiRa_c=@Ct
zxwvjuOI@+{sy#LBow~Teo9+fqz5dHkmYNzGt+B*DeRDUt2$_9Q_gT*escn{
z3^J`<8M;vkSlILNZA6P>tOWuttftOpdAb25s2==mEH7k43S(r2RM}pss^ENH2BI1hpIK-c4m3~3_L|B
z6(T`E-dO8oP5Vl`yyS}|uTyfi-{twjE17_@fPdL187`{s$OUOiGKszYw*hylFgY=MqY552%Er4A=@a*19z)cZng$#j)CrwGk!@(|`$RR5399!@b=jRJt`0Xa!
z-w0}-xG)Gr_Ane!1oS1FWNiC=7NSFOcKn5{M|_A4wIpeT!aAz0NxQCeB~RpJgmeS~
zwNbl9_XAM^UyvbUSSv_6mgW1$bKy;=oSDrqmfyaujtg14RVC}fM8l)xr5YQkq*!_#
zM^*N`v7hbcJ@gj0md?s=lH(&O41y*toQKV(KGzZI8ASaCq+7(k%AZS
zQ=?@9$Bu`WdDB0VDFw+fS%yR?zwFov1unfBR4~)*8Q7_kKIQy5*L@T4)WHXe0!xbG
zi@bbX5S7iU$lPaOzu`aj6R4Qvt;7>PSRbv~6d`^(y!SwSK(}_+hTC(K^kkTSWi(xY
zL**IH@GYIUz#}*9@K1)bRI7QOM|aWYjN*;RsAU##FeWg{-K?DQ+;A
zrR_-3G$jU&6okACnJgTxN5tqFRu`iY<)vgxwpU@2b8H*2IdmOqNgS^&xUkpR_+e}{
z3MFPDTm3so)EAJ-@}VcW_@%6eU4c7b9Y3lL0U6ZXEoM
zMjp(Mq34nqV29T4cQyRZxW$fr%hFMzn~|#R)26i?*%|_<@(r?sSCj$}FL~n;G0*dU
z4HNSU5oFp@uhlKz!6^l%!-=|U%ZDYY65IiqeN{f!D|C=UkS!kFx=Zdho<_)Qu>~9AOpZ{-4SUdJhJk
zcb*=%@)t5pCzOA98NbHds%GYjpIfY~)t1Pm2frX`ZAd-6;d6~g18cv*lKI4zOyqbG
zv#|DY&GUBFh+ZXepyP-t|AXM6taB3LWsnmvw#ilwY$Z%
zi2FcK^8kxMF%|PmT!MaIxgp!v>k&FoBUm6K>@bHqepg)Ng3imE2X(o!Z4{1I@6-k+
zL%E!iQ=gP!ZB;a`$%9aAUGnc<
zdm4COgy_2!vf=G-BZ
z-nUE;%lA{%i%z?;vpElSWtYk6*`q+}MmMPlPko7Q_XF}EbDY7W=>c&3N-N(RGL%9Nb@c7
z(V`ys^!igkunXMDa*`1x^Xhub)RM#o<3j)z<)aH_WTN_sc;XeNm~8>i+0{^|Z%6JK
z;tSJHpR*_sAMFe3--#P6EVf~HuGI`?xsr%k&h#v3L{{g2y!W>ALo+*DfTE{SHXCxI
zs)rs<^PNfsx5D<5#+qaJ4$ay9c@awZ#_-OPLKk7tumAnH^M_^hLX;A{wl=LRGthrRC7C*)O
z^?q*H(ds}zk`6obx_VL0hX;3sb4NfD?}jS|&sUNp#^D0W{-Ut>X0w#rbL~Rx{g!x9
z^yBd+!cxB;b`0gq*L-6Q#HUK*J<>k(Fy;}Fcf)%Ac)#3`q;Bbc1#=BY+_{dm3Y^Y!
zBb?H%SZ!b7!s2@|b7IOtv2HJWJ%Q>LkU_J#{|sdz?)0*4`@=cm+>jmAf&B6>{6T*d
z8?HOVLAD;lYlFwEgxmn>Wk;BlM?X!Xn8j|{YIm@pM`%dgo>Ep9lW9p<|HNCn#ccQ_
zr&JUZpm5oCc#CQNyDdF;9qz>=G>_H^p;`8$ksfpX4F`E>(tF(>j36Fw>aKAI$cj{9y9K@#7;kY!yeFwe
z^CXc&GI)pXqnd;AgXNNn$c(diD$iOHfh)L#C;ZjoT5t9V78Lc3@dk7sVX)T~DO!(Y
ze88nv#x1%7@mIal6=NHg&mWRaw>OPqd6o2X0OagJ7(&CH?fG+5SJZ5a7`dax{7E_O?k5qq0*zRV&2MQ%MlhNST+
z69bV^1WzNrt5{dPuJHhoUDx^-qiCN%$6VP4{3g5zQVQ6eJhczg;eLrWsAKR5j>c6GKVkWnTw@}TWa?laC9&;3*
z8l`4Gz~_@%1K&J+1ipEc3Y7r2Bl^f=NZZu{@lAV6y@BX9I_uqgk^2UU3I;c3`Kyy{
zZ^z#*`g(na*B$c5}j0=CuT&rUmn-MABCmBWTL&BbSN3>^)N4_jsG&I6!usf;N5oi?gvzf^rUoJ%D`vZW
z)Oq2D${0+W(9u-$s;gA0$zmK-uGlVgoL!W@`tQj@HJ!leN2!mHA@lYioz&9$Bd}@H
ztSPLl7?VGX3e=pG*e#^Zs(FiYLXNyBpOdE{PZJCG^(?BhRT<`cV?qudtU?R@(XV4d
zGu^1bh$9}d&|;Cc7_9sE`?{&zGsExb;uSv7a#6hrb6%KpMy}mf2sw(Lj!`3DTikc<
z&7?J6Il>jQGd|BglvSV^-I4XfMLAn(5c&np{?W19^eiKI^h5ox?+>1^Ns>#b!>}O{
zH@kMV1|6_`B|A<}i^!)UJTOdP=na<7Jur+6bbFD%?+LR>o|0AH%PQB2AlkNlpl{Cz
zpb#mg?Rr|=qH>|S3`#fIs(6pKJJ96T
zNq%QgXDW(WU~n%n;=B-k*GK
z!YC_--g{9Y4Jl&p$^R5F19`eQv#TE%JaNAcHHX#EID?6NC7*P&jQE8j(l;yjP;y##
zatzFR>d1VRMRNHTM5(5m0I#^vqh;5&ZRYIsP+s4xAF|*L=L^-|ZzT35&mE4N<_FWv
z*en89=I49pS@L{wqk&9uwHIh9pWIL1lA4uk9iSENmv>qnw0sO@jL>q*QY19?`#o6j*JX^Wcu*rn%Ef<)@
zj9J3%YM_38gq;qnkjUR`=mqU-4)@9Cc_Keex*2rKXQ_DVU22I(gj0o{CnLBRZ1wOS
z6fo78k6TZFCEu5gHmx@4=@Tut^pNb%qF(ckV
zP`0_}PbWn}?!L=Jk7%yg_v0YVyj8?B6gBpX`rIiI-MgR1M4-fZWK+QA%YYJx_gv~%
zd~-8#_@K`=+k*1+_@2v&6sgJF08siY=&nUFfvXePURTAdm|VC}Sds7UHh&
zOrX|T2t9I6-gsbqmFDB1@?3ZkX`q52ifGz+uc69BwVjBmJaQ)3dL_G@xfqAY$%L~G
zb1F(g*k2bb=7cFixah+G-X-H(@(l
zhoSl8emaWb{+$K#14E^w+>_eyB91@q}9eKveen?ckhNqc4naaNw#x5Oe?Qh
zWVK4yKF1Y;iEm7N*S(V@f?Z{i^?iK+l$}Q)4Saq2hZieBm(R2)5IK84`|G+EBD6cM
z)V@Jm@%h~YXR|FQ5j6DMVSm1~Lte9bV#yFy!p{5g)!Fs#osmH8qZr<7&z;vD{kH6}
zCXT@2jkXubha7Sln;L8~Th&S#xHd-!@W4$MJ7MWTvW&JKf;zimqOq-2w@7wR92S&J
zPQ+D?A_`NlEt~F~`BNp2RiZtio@uoZBvmY>eMySoO@?w~B;;{E(XvBz7H`6)$8>#G
zTF`{e*ScU7Igw|4f3Kgw1oa^L;4J>~lc;`^hanU@yz5$PTjH%lpH{pB#O-)
zFNE|dq{3FxQW1V^G_79T!HyGH2;!IBS6?3CqDY?Hb484ARCHNgTC$HZNaf1t@l1T2
zOz$u6rYON(BhVz9Y=(N6%vEvYAF6@I{qkldVD<-*fCOD-v{z
za_sp^7~hXN&{)kkL(df(g@)MsfsUH)1_6YOS5D*mvL8ylbuSR9TkKa%@BcK_-T?{(
z-4tGPc1MRptP$^@mHM{w*S~oB>K1_?3-ikSJF$^dnVj}OC=5~6!$z><4M|QE?A?uM
zuJZ#=p&k3z6J~N)8kjB?L+rOKAm-J&`Hk^!#jd2PTwf4
zeu&RoZaZ+|+}R^M4p)>gj$(p-v%pR_7$;-c?m#Wr+}ZsGDvZN8oTxdF2>Jvn*7b=~
zI()LKk=mE{>7lM);+^xE{4Vp{*1gro92Ag#`6Lv!u8S8kzS5%diqN8%DnWmT{-tl^8|
zd=}=f7gU8{vCb)T$?1P%CcoGly+bTwo%LjJs^8*8+1f6$D@UdANjyU
za!x76F|~d>AFOKXLXdSz?W0#3j(Q!iY}4Ved4ck@98RqXMz`|-Ujh$S3eBe?6U9?v
zL?WX#Sej@>eWD$K=o2RlMT7JAjvlOzAT7U#K23whXbV4)5Jn3zAH!U;`22w$&(2dHo(w>8ANEMG
z6Q@2Tw}fH-AeeukLR9CWFpPOr=Y6gzjHJ9o%JXbmKjJDJLiVkZmHP`c^~NNBxRVZ|
zr7vma8=)V<*U!e+)bB#DO)B3Vva#i_Tje@7a8Rk1zw?6Tc}6`>$SE7pERm=UgXU#W
zVZ0s-)n#2Ni&l}9=82`K_B`NAQlX#Lcj&e{Cbk0OGh0O}k(G}3(#X2LsW>#@+4pao
z@#I%@iIkI$dA$no6~zL5H36X^h$H$Cgp$H_hdvmeWC5r5AjeXKcjX;SV)1~WV|os^
z-wLbK0%E$w|4&Slf|wo|9se*4B*5@><~&IEeZ~K$`@WA0MSHrR!|_@2Z=|vx{`+{;&6rt#hze;L
zZW`C+U``$y3SNODwQk$U5_K6vu|5dSijAm&
zaoG8cewH4(IeAKiCRDih5uHkeu_jyk4VAJBKHa9|p;$h0U1_~vir-_lC{Im)36JY4
zShI3Ptf11a05F2Fahb39)U?-sY#j%*BDuWnr2q8}M?%4+mmUwa7rKO*
zF3Ek{O>su%1|on-Z9Aar?NV~a;f&K-YuJFJ)^Wn&jMS!$Bo#pB)@gObp?g=sZs*j2
z8e}o_OyNg8@#R5m;!x#N8-wY
zejJ~A(%N!*V{fx6)~xzN{VtQNJrV?*-%2Z2)taK0<+_R-Q-n}`$F_Kby<*D`Q>FvL
zGV-s990_!L3pJPQ)L%%UrM&p1u0}1G_@=O)9n9SP!j$HzS(gle#kS*@VmHht_222d
z9x+I#Y>bLjPx+w2K9H>kD%iEJ=i%`a8$LD8cxW
z@28l&hS2snp*&niTYf
zU2mi)8}>^SNN6?v``~Y0P9_dEQYamfoIsS?_ztC#;gzTnos$
z&3dn)d-^zI6+XO}Vjy9Zr$!sCjFW64LOI|Md1YiS_|VJHKpUpDbwi6myc#X>bE{j9
zQjX_n2l-@!n*0fwDbq8obH@LVv9}JWviaM6>25)~Q@WAvl9p1sySuv^kq#;8?rsU`
zZV?a=0VPC0>dfMK-o4-7K6~$T{<^9{bX00{!HioX0-mg_4ZVKfQcFmCG
zD|5@PmaO}G*g}E`)@+bZ^mc@+Uh8kPJYW1cF&q886y-V`AzhWkHyY;dI1i9zCkE!~
zU2E^>*Px;r^GHL=@X(dnGrf@0)v
z)O<4!jg=^#i>qTZing~j5=^VqhCV7(Nw2x`#|D76CkETMcDV-%mmpD=Os-Dru*AzRWuIdH`Mt>q|#9Xc>B+7i&0_S
zI8-ay)Bg(n{!y~_wXb&^pQ4ZRfi5%;5$pk$7wLw-?1X0%mxJzR2_1e#C{8FS%`k&u
zno77v>pT(Wp*tMpL4vd5av&@LwN(+fB3R$O8A*wDfZ;JC-2Yedc29bQ8B@}z<~jQQ
zjK~HB){Ra~vd;u+!0w+=4rIffcW(L`Re0Shv^xL^hB4&f(jzG_XL
zATE?y9p4fx^5rK^cD^sSwBF!o_Encg&Qn4kt#-{s@Wq-^W>
zqwcfI&G^q7PF-!Cp-mWdAG$L2RhD8uN>~gEr0Y6jK^a9@mA!)+xBA?Nu@V1xv1L~L
zF7iPc8|H5;_GH|{oSJcAFH7im#|dXrrz>)bsymkZ;z8znXr${x_usOjW=xo3E19VI
z{@z1%nmAux>M$6QF?c!bz;Kl6fNv8Mw%g9xqO4Mb>k@!f3HGr^!Varu>Ec!C$1yHj
z2GCS2=KrxG_~VKzIjo`eG_HxH|C3u&7TGc2iL*WL@t1atl&f>cm=V@7qhIIi-9Dc?
zA(A?Ecmdfn8`{6$?T05l*;TZu^QgMeNP~dfZ*=+C(on6NaNPF5{^NUcnq8g&`wv5Q
z6YdG)>He|)kX3|(cM>wi&g$#~axWbQF-kt!z)hY={S9YL#KTU?7tMa8L;rx{sF$HGj6HOp(K6c4Hue5t-~a?C8hmE{GY=
zBuu)coGy^MKS$fO!LdI;{b8DZ>l@@lLKuDdzVS~4j(}(%m!k(1^u?)@$9Hjf2OlV7
z(X|A`rgxuDXFMhHRbmkH-%4q;)RV_+f;r*#X=Q)BTtW1eC>{|qp}}75Chq87)EhoM
zgvqev%^83@VGYZbx~&%a3}!E{&j`H@lkwQ-2ct+5LFAxr45E=tl}raWY=HH(S6{7E
zS6^bboII>wJ0Hd4xJygk^Q-YsM4aQe7$&dNVCz%HTe-D8
zJ0xRBKxr9DG>tl)-hZccxX$?%xnSkFvqUtd02Yr~z;S>9I#hog15%T*5h=k$vh?iz@;T5Ee
zNFhdah&$K-$X;>%Weo*cT_YY*3`M#>8M<#0i=Q8hRAqzqL^%jf{Q^gXp`;UdpAaMd
zsFA9x^2~iCtPq@Dj^*+j9+oG)n_u^)m5{u&o%;xll5e`t^6=&(Oh@h)HjM8ranRrQ
zzAbt^cshp~l%l1nk$Jj^W-#rz`0XJ^e~>%8XUwP9PsPWilu=nX5#W7LJl7A}vZgiM
zN>0o#rQ{>x9nv6fpWT2{kV+zk+_HoN@Hpeuz`>!;FuzfB3BPYkkmZN;Pr06+pVY0H
zwZF=s#ec~-j1e3u3c#4$1$#~OzHf8TMISQNDFxa{IvlKCv%4@QzjWEn?QVap$~T_i
zOE?>IUCefdK^ZVzVtUA+qq-BT_>8(CXoj_2`LZQp{T922v8v(PU~7N}4M{kbV)V>5
z*9<}VO-!%$Xt_eV;BEu6-#l1MX|~4gG+ujObjHB(6Mflx9-y>ZN*azrv>rzk0*efnB`1og0*W<>D(?1)=V
zHa618R#ITCz$hB2co*WoC)H^3uydgt>iDK7Va|z1VIDp~QWBYb!m_^{U&<~i&)4P6
zB-SfvDY+3vx#*)7O}P;`g?Kk>gu|(4r^a&HR3vg&c}HAIf%j%T>R~X48G$jPCFM!1
zn&uK6ET&=tG9P(LZfmzSM@v*Y-jW4gm&mN?l@ar(4!U$JD?lXKpNS-j_04nTyD)<-%je7WacZ
zeUZsJn*@znTrZCGZUi%?q7zY0E-o@?
zE0S5!7M2BtyaPnMa73IgzqtNTZbONf+>BZiRJl@9B^j2h5q%)|SlFhK8okpJ7raCJ
zV2yPpd%~2jSx2(5O&nUSkWOLHvw#StC4CaVgYs!r&`;Q3XUwj5FZRmh7URAY>raM6
zyy&Mc;%hCJV^Tiq?U=AQ6;N;k9qIbm&v_oz@)D>%Iu>I-Ab7WnP
z-N~jrCrNxq%ERuxx_xGdpTCr13rKrg8*8aubYrC)SH`a8d)nve*CJ;op{zt`aEg}E
zNZ)rL<2=6-EN59zI-bV48yM#uPvbnFSe|X!e}-p%Jh!-EH3A;WmP5|3#~xoDi$_9e
z&Hp@dG4iukEcq~I>s4b6zTczHRvA3gH=5b7j%Z@b-LcmqVzzZ9eQf(WHr&NEdTfis
zuMAenMw!-=a2^PyWBe%aIv#hgJFoLJt8Xq4fkfP35C;J_p3lF^n>Os&i!~f{ra?XF7X$r=jCe^
z{b`~x?_F98)3r6pT2F}`Or)F8yQ|Hd1%qd0peklRcjsPB$HEBs{JYQdMaRctkZz3@
zPTCUL8U-w(W?~`EnRu<%Vju6Z_w)r)1+Q5Svx7twW_L$ogirYl@%RqHhnD$FJ&#Fd
z2m11+25T*)@8;dxEwRW!MEz3K-?}qd`WK?~qZBO>L?u{LR!vyvvZ6dox>~=4{mhLt
zR`gx4^5bXkayH3^8ElDy9!wmDQgP@Phz;Xa#&x(V;Gr(F+vtt>^XVfOHrs>w`N;2G
z6Yofl{qEl9PMiv+A~y&v&m4g1MQl`QA<{(dZK}i^+~VAtie^JE@{k_UX_bnFZNKrU
znH-?H{?laP2_}m=X=iQQUpPP7xyqs)Cr9+3p1vFLW~$FVw5+$;TBr)j?*-nsF`Y1+
z#5e0t%*-R<6K%87_&-bkyy(i|vdk2qfteU`uYLQ?^PF=G^(JMFp|&^XBv=;fVdo2n
zsRLzz=fz0|M=G|V?5-CnVg=unihBOqb7u+necbQas_~5$OtpoYg7&+dJc>f_3$%#L
zXYGvgbRPQGIj0m^Z@$>?x-h+%QTDrILrwp^Ictx5_w
zNMiiX;Wm$pdwWb4<3w_l>ci=d#5Ie*jq@$YW=pqbof#&j
z*zdU|>^GDYo^zY?onZa`S;E1O)!TV9L+Xls=B_Ap6(2f{>((m0@x6wOY;sz3d|X*z
zbfULU&pwED{BhBb^oK
zJ>B?cYU}9^%sq=W$c!f2euXx}wmAGs{MPh~^uAJlPpl|00{y(v&P^WrxKncbO5~s1
zkqM|JbFaM^=%b88MrX1Pqwdr&^U}#{hbAwiHr}eDWN@c_0#A2(1n!itsICTLR@Nv-$zkT3k?vf^tJbhRogKm<^j+<25ho@~*+b#uBW_KNi`c&wb-Ie&+d{Hw
zj}DdU4RGgglPPx))@Rq;0Yzt>
zO1UY(jIJ~1hBo;`V
zQ$e_XulDH=#sj2aXcqA9Uu_>{M6D5H+N-OsKj%;--Y&NFYrCy#bKck8X$hE;9L~C5
zXmOsB+G$YSMt`O<&~{bTR_{(P)I$2P#k^{;&)P~<#=(@XZ0K-L;)mAj@LXQ%*4ZS=
zh&8!*TT#&I7oJAyYcNt7;;5RRu*3#nN%PZ4eJ%Ss+?}laYC^-<5`EO3@Add8`w3-|
zupC7iCFBY{EC%6-Mg5L~uU`|=|
z)HNcwH52E2d{lw6RP>rhLe}B;qVt4%@%0$%cL-O>k8MxBbzUD#E?6*1H)I@z?3AD_
zb%&r1T(o|4(Ld1S;`JOduW|XkXq+fwnTsk<=R}X1|2V$V$cjq-#dmkjzoP4P!J5?3
zS3a60EKK$Il2)gWf#Kz^(WDs(XW-`gqyE5_enyu^{{DWskr5s_y{W+erlJIK$^3UH
z>`{gjqcf|(pAFw?Ga5l#DeYL==TmZYufpaFznjP8+jk-WNvM#Qz%1k-W2_Gu%>4pL
zXU6(ZgL#RXaI6FK$U>%}G40T1=~l-#Ly_KjvxR^(T`(H=jVF?iF=@y8jWC}Dsm*Ws
zm%cv(BqX>Z~pY2U($cp*}XbR9tsVh!A?PZzXUep5ZVdL8Y&`vtieot&-&eQS_J^e)vl
ztY~cZ>N6UQ%9n#ubo?K5A&uCXB_GiZHwip6yDZE9XknS-S;ni#?6emjfv>In#VIf$
z&&=vWnT{1W6K_!WRTqa-@w&wvt0#W49HaiAV@*HumyHBZ&zjN%AM00Lk^M{G8{Dj~
zQ{&V>_#M0?Z+j|@7~KZ??G+1BUt;UGZOSC@)W!5LeSwvja<*TV40{8ywGYM&9PzZ69*nen
znJtz03t8Q3n(32Tj>}}i=4&Rq4>qa>eL42v+Y=LL!W6VOeH-&(_`Sd9o*$OiS#u&@
zj
zc*3IN1aqAuArIorrN7-8CL8QH&B9lcj+_hfGxRhH~mT4BJTydv{_VM^XF9}a4yyNZ+U&yv1^$+;A=dRf2SMtHuc(2V3DP6zW&oD
z4DirkR>CzM`qgPSCK)h_T?lPIQ23pbiU{keGj(FJil?pb`nOYk#D_XDWKKJx^7%>H
z=tQf`nNB_PJkG(_nb5z8S2)jYnZ-DS$52x
zdv^8x*TQ`}a9%HP&+T4UQb?#)?(03S?Sa35r%(yJt~xGH`Nz;A;~w@TaMWu
zE%z+82JfWq!okO+g0Nv_V=iI9HWw13?vEIPmvEmjEPn^sv1w0K4gIQtu0VTd_zX_?
zCMWxp;oFy_12u-^VKR7&D4PZErBx`wc)g9HI`f$#_Wk~?=~bw$7x(ciFn)Kb2k!$u
z;fXO9{F;`sL?eHE-hIk2ldBv1zAofV(l%*AcF^H4j%EJ1k`*;MDZ#dk0}PQGoKx>6
zIE~cy&yHa>@Ex39{-6s=+K6-}qrx8@@O$5bb>j7Ud7?};SzM%ORj
z4D#q+kM%#eG$bWXs2Jk4r9qjw*PHf}>Pgt-d8PSMdU*psN(PXf4GKgbsBnHJC@)xt
zKb@@GV8fr1L_MA28)lV&rCatbf;RQW_vq+s^8|-uzeslGIu(0$npb@J$W(3fb9Bj5JD;#FBe
z+;5JC&7Y)}XxxLc>U_qG?E&>0tc_n_h=IL;Iu6AAIWRkTKvjTAn^piyRr{r};Q=WW
zwXtFE*4M8g9S8XLtlPS&;f@{Mckq9misRJyRm8+@!=3OMdsGB4
z-v@wI(wFl&IR>-+uu735PHM`48yY(bbd41-bZ?7$}V;;k_jrF?&Cqp?F
zygqPJxWv7n%Q$;cNk0A@xMZ)&im-?Sf?p;cdeY`l;cCM)#)H?Ez{DXZXY)NtTzi1v
z9lf8y!1wTp(BgZf8~xk>xH?Vt(xp$nQP{Y?P7zin8Uq5iSninY?Rq;T&Z_9Q_GaX8
zyX&LEVn@+^_MM1UPGGhE6Z&b(lMHNm-ol;*p-iEq>JfnSdZUW$pEyJL@UYFnn
z8sn;rO{kV@-5@6468c*il3P|4i^;nCjvQ!0U8r8X_)JN8U=`KzEMtPzS-E{9nzw;8
zq~771a(=UPe(NSOw<;KEp8uTRrUxUe%(B
z5~?^wYz;%?S8M5)?ycT#1$kS@0`9QiOB#9jkr62iJ=zm;RBrf*E><4#^v9l5H3bRIr5B+1T;A=YPSh#G@;p
zxxKV^rZT0in?aa1qOF5Mh(pD2uhr+~;36bem
zt^37*^ouYmM5cq9;bk3)#4QZ3^z7t>mB+4Acv1rv_!3j!tsqX;_ja@&x3Pww*Y6zv
z_CJFOeEAbQk9I{?H}u-Ph~~Yj=k*pzLIC4KsS`LTOS2%p#qLXXQ?9{dge16*id4^q
z6_s|!(0gVNEIsC3^7{zzQGvg2L;SfuZnH<%CbG&+=q|#)A98yW?^Y1r
z?5sC*@$0g?v@I)8$>&uNOu)>?iLdmDwCw%UU^lZihEa5>`VQyzmGrCc*(^|RupgAA
z1eBeR>X|#BQ&hG3D~4WawuOAIFbICH*&W39%k15kgPmZ*GkjugeID%Fe`E3>6-)q_#Z5H&>nukL|HZsH$dS7;rZoZ1?FGwT;J34Ek
zqAo?6;M5KUAJ7(iW9zTj8}LygQ`~mQA!iYnCjh7Nr1@l2ntVI?-Nw(|+d=P$Ttfw=
zJF{x()aQE9<Y?tTA8#&e^CH#)yt3*qgQ-{_#V6v7|-f-6W9@TWZ&)SWd+FaPvYt7*m5
zroI)AWWK4_9
z2mEO@6_x%$zqGNE0DZ#6VihR(ylI-d0F=&%%twGyNog&tr41uuHE$z|A8s7gpoW&l
zhTcxxu#upaTVGQlYzrQ(|9j~97>pKEX+%XPft3V2ypfr=uBQK^{Np5g2_9)(HG>l5
zYBv%SLmgSw-rrJKTzwQ|EseNdUl^hS{-P6TG1>&aQVUO$93Cc%%BP-i=}k97#67tW
z*05KJ3wJjI-2G+YHTWf<+xY`VhqJ1yqt&;M`G{&b{r$PAk1sGB9P8#oAE`)ksOdtI
zTZpE$*ywLxG0-as6y!9uhq=r#;Cz;^lxCoxL@CJ8y9#r0F~<2kmimmXwB>D>%h0a^
zUdFJ$QCmeScVwUO>6;Y5C7X6Z7F@{VmP<)^CHQx)R9P_#M0TzSuzDjU+$B0eBd26l
z@-trsv*_hgMbQGi6JIC7u#UqND@lLleAbF4c9T0wltR`DH0yU|S%UI~HUhNKjHo#@
z6?FRV${OZDh7Dabqir6Q4$(Eu?C({L0kPMWhmGZMvBg^RmMJm4G}X&E=6WbsC)6*S
zFV|E)DA7J|*Kx1QZq`!pa)}>$JQGo?KGz{H%7g`qk|Zjm|1OwZch$DVy&|NS36_T@@Sh$+pLi
zB_!04tT|lrc6Zhae~!nnnAD?iYm>BV`H^UDsi_u$KR~O3@#AiDfxkQ6
zQb^O|kZvvQ*=j27nW^RG3A)z*K6#a)<>m-V6RoAMKo5o_6YZttJxn1PD_Y#ccE8XA
z2{6hQc$v$TY&ty`h~Jf;xHQs^a7y8&?wMI4@8R<8bi9jEBgacs>mT;w$9o%>u8u3)
zl@miaJpSUGN=NwwXLq-uNFwkI^esvIFr*Wl-pI9ASU;!(F!$n~Jzb`TkJKON3P?ad
zN{m+}clKxa5czbe4Su?8fNrQqj?%t!`NE3wJ#`JHc}{(gluf4vl{fTb)}kVgCMuu2
z#$+yyT60&5)FPS!j;0I+$QZ<(opYm)W;{v;{mlvVHx5=cQSnl`LX<&|RRLgdu_CTGk)gP!chw#T8{J`$R~P
z#9MbcyF!mR^PcFmn2W0t`o&JS3PygaO&zQiH_s?^6Xd~yQwk^jSv1m7
z^ZH@TDXOZ_z>@>u^^gVSO_KpJ>DAZgh^v~
zREshi|LpdgKP7_;o-Wxp#+;Ach>7aVj`3ke_XQ$i{sQd}dVU$zv19l5Cw3i-OR*-e
zt1K>5lJJi2Ha$OK-&NCJgm&`>B2Mr6w`SrVe?L7@={`GKq!kKwckzC>uy*uw3*h<5
zp~rK`?x2(sV98DBCX-@p$-R0QN7tDx$bHAU1T_H76Yo9^E6;V@*wZ#6+g((T?s@<^z=xYc?zIDSOv6#e~>@*F>0sl;zy
z>iE689&TXJhJxz&-tT91IlcISEP01srH+Eu@KZwYw+kV#HvN>%Uoo1$vNnGuYyK+I
z{1v+StAdTVTyH%g^`$@2d28@Dq6L95L&VpXsz)?|N$cdF57ypOGD5#7N~DTD}wu|!Q9W)b2`g$OLm76d7noZCgO%H}0YwR+Yf
zMcpo}TVpUd&kuh`{+%(-rcpGU6~7-T4YkQ)_n4JFDhSV_i_`xN-uvT1AdM-0HxQ)r
zJCGqt1E?fZ>;kl*N(G8wmv1!CCB8yjWY+xv)Uh?a{lBXBKV`0YYGrp^G$-z^1SBL+
z#i&S>x3se(B3)Q+Qn7VQ5}-@G-TiBkDTcTh!G}9tgNGL0XbUend#uy1%HFBPjyqn1
zw@_e*h^)m#U_xvIFKH%OZ4_l&hKHtx-W(z>P-gJ%&OXFVwOjdo8F^0pQebS0UJh{)
zs8v8gs!^MA7Y_=nr$EdmZy*M#Pw$P)^D)$BlGC(;=dFcYGu?Px*^*f%^kNn>SDsEv
zb-4N^9yXi1R*L!Xk!{0-lfP0LVRh{oXXqu*TUJsHd@3l7s>{!xp$
zFe5WAYYFy-Om0eo)u(EpRg)?mM4K0_VVvWK8}dU&D
zSO#*b7{m1mF47sUa?Rfh>a^sU=%#mDdYzItu%`
z1U8b*3`iY5hiD_lHSWH{t;OIA?yoF*Zob4!2;$uS%E3vS(;rSL#Gon(Vl4({_Hb2k
zeC7}1<&3N*4sBsOV)YbWi^@oUQ=7SAzsovjMWwZjdNPlM(&)&Krdo3m&hTNj4*J5!
zq>X~jgxM22=p#J}`ZlmIf=LMn*XtZ_yK?R8yaab+uWAhw1BC)Fcdsuy4Zm|69F4ea
zW?>bQgZEr21HAiD0cLYySjJPu$drGR<)2A}@u$#*A-Mv*u=jx^R1=`$j8{8%H1Vol
z)=<11tJ01PZ#tbbb+$rETk_;b`Hj*2IT{BuS8E);hNo(vl~tEs7MLb+z}0k)kXRxA
z%q1RqcKG4kTY&ASMQr_ND3?bkU%|X7dUA^KTRY9Fk|X?2e;e=8O>U)vceV{?{LVk{
z#j;&Ie=FkUZke(t`8n|&(MRVLRcGlt5g)C)BhSA|5wq^e}kmci>T9HpQQ7P
zrh&(w;&apUD39Za)}ks*caG#V4?@+ay#YyoU0ZR!JqS_VNt2sBf~<7m3lpz4Xeb)r>Acrz3<5DXMI#Ph?LgI#5*#O!^9AF?DFZ>+l1U_0Dll;^OCr0tTbuv%krOXrCDTgMRbWC`9z+Fs
zpT5CJ5RsU3a<%Q6BV5*e+@1JZGlu4{cUi0d2`#TjSjfl!RnG>Z<6%>edJ9i9qWZUN
z5kl^0#47NnW0riIqamxC`Y11y@lGMdt4|=E?kvb1$OL@^1cO~_=ccR+kw`^Li_f^=
zh@|7D&X#E6g
zms?*yl#|FmTnwIpeRcKk2&<69q)}>k+XfV}koyOse2U`b^S&X7cniL`#
zs5;%E$m}|0KogL0RsVa45}(B9AZl
z=Ttkmm6
zr<~U@8Og+*pxE^9ycD<8?xQ(4M#=ac0ZQIO>JfRs>v2x0N$$3f(r%LoaOcJAolh1>
z?%s^jZbFjDdJT{y{}}D69cdd}c2UGI!aId3em5&SDqX4tj}Jm%iweg^*IN|5Pimu1
zP>@8wzgPLt^F&95Vt1Bis$vhQ5H|``_zDJw7dsVD!AJ_C!WKk@9xyTx{UCB(gV8co
zVLne|W7cSm!_%3sJu_kZd*o))k!LmnJm}lVJkuhqQt{qW5^*uIG`N9R
zQDGT)iE<1Wzp#-xn8}i{ocBS%0)lWzz)F@(k-48DfBhh?Gr6ohfQE!)*W-b+FP3C;
z(VW7L8d98Hn;YhhRlFs10>}UIgJK9JQiC(7p$MIveqlj>QMN;O(AM1c7Tba4Cj)ou
zb3Va=>QAKc`%60(@@>t1rMtx_mwwiKx&w=!ly;nLog3*kbcEc->P?AJ2;$r=)?l>}W^Bya1Rtu3GXB8k=Tl08q-R}z$28ANPowjM!i9YXu*ohjZu
ze|W6f`Ec#i-E~4Z@zucwXR7~8U;rZKseas-MBBvYzeh&2(`$WqQ^qeosQBjCdW`YC
zCa92teeoLkQuGC)3t@#+(c+Cpbj0iPa-4YW19e&=#j(;?+$OmysaB%`9~fsd+(k4C
z#gF{JPHg|Hbe8OwJMn_$(=D3D8SD0y1MIEqTH(eHt<@-l8xFd75$&5TjA*W%_L>Cy
z9_tnC6DMh!(J5i8RV-&e^)YOTOOY?)UwKy9=P*q0G3wd+HssuMobV$L2Aowt+-F~S
z_MZF+46?^MM*mR0%xHk?h#@Q5%@82scmII<&NAjPZ(IFm=U6naKC#jPmrp{7gU6`a
zj1v4yln!qSS#i&qEw!1+YmjOekrn4_-DUW`e@Ozr$(&G>A35lnN)t$oX?RePa_26z
zkyELBesy;0R0BA2bg;es2TdR~X77I4{9r}ak4@&*!8EfdMt5leMtr{HiV(E@75I~>|f_*5f2C|13h7B_d?>0u0ai#sV
z$aJcf4Kok#mkf|(dZZ&H8R6YVt20g}6V0$OhTO-qor2e0&WuTnS}OUfKM
zrOV|B2Xo{MIi&9~*rjYoLs1n8s
zw4iot2MQF7+gF~qDXL8l3A3teXakwnFi$i*h5P#93i}z%M?=uO!q@7gtuxdWQ#3AVg
zl!$?i<`7D{LXg5;M2YZ<(&@)i*8tc^X#*dssMbw$vksS8=#%@c_L*7C5BGPyDoHOY
zmgOHL#7h7b-VnoQ7V6|e;&)v^A)vnUIgZU|+{G+&PH6y&LcMh3Xe|H~XYT+gF6aO}
zJhyF7EGYy0_-)xNQ&A0Y;z;e7OJ-q*Q%dG1^Ozqje3`m>C1qb+Qda*>8vc_c95#=!
zVR41je75^f5r-iQhqV8%+``fUTy&)p2A*}Jj3_8Bm%H8Ui^|Hgvuw|zGhI&8_wNFz
z#qm%~-^=5DE)hs!e2-;8r^%50L$N}YcQI3=AdH=>TmsqH;&nLAz(g?$ZCIu}q_zTH
zNc-eRl>UwV*WpGEuH_Q!t?e3=8S8o#SQGZFnn?S+>5Oo$*-zDqQNlSse*_A!>^Z2_
zr~y?zZm@jjVbrh{WHkJdHMR7iblk-4{sw#}34W|OC9l^fyMV_!R*`{37Hqk(F=RZp
zZ(jltYDoCuC5pqr+q{_h*9D8X-
zfkzZ-dk&%Z&7ni7o#=nAFmT@fhWUMC~Mh5aG
zY!%?PW)x0^Q;UNI5&Bz~Z^y5$9{-{jd%eun3uG0USo-ws;lYDfAJ1vS@o7=rI=}Pp
zqB=6WZEK)vZR&dG{%CoZeA@8-<#Wu~WWt_5DyAKplyKrM~nDNoNd8as?7m9sscxOb1zSdQZ=a-3HjgV@f6}#W624sYRtIS8irL?|Nb7H*0=KH-1H-nAI=ew9rx0Rwj
zfoM4W9y@XkYPG`|RE0KB5mX;8EY8dmd`F%;B%NFu;C9yv
z3%%CuVh;%F3aiWQ&I$10dV6nh*X*?~XY=a|ZbZ$yc3O$1BwZ>g?6&_U7=rEiCua!m
z-(VEpN9x*8coe}$XFKqUg8aL6_~Tw^Tz)CuLo23BNS@ZUq39?|hc5D52pRT6Atp{J
z$QsX+L-)CGYsWJ-$a2-*DbdTwYJ*(?xcDBm5yulM`)zc#i?P;@1rk8Y7x)&m4hc#B
zW*H;5H#c!w3JXzcr)ybMN4|hSWY?urI0Pcw$yy)~>AF0K&*^@K6|teC!_h|e8IniW
zN;~H?qCm9seBXP-kZ7Gpe(H&dr2>z^ulB@~jYlGxP?PwnFLqsTaALub&?7!q(Qx9$-lH9`ca22fdeO*dM)_rimDD8hc#iT%
zA1moj90&$LU=jm@08q3O2?7I1o$%v1agiCdoGYGCp?rXhS7_&f02vLrM{gm>I8U(!
z;YrO`BOK~}3`wu?^-jH1YNP0(2E3Lg95XAgKq-l3WxLd6y)BNqyg
z`Z5K|{6N`_Kqm~{ma%r<-XRGOcV4Vsz!U())zQ5@2rnk;i9nKsV|!0DnWFbFxfDF!
z&2M96N70^>Eg3mX*Falie>LW6?@PDblH0llr8Lyt)i^kdcX#wYK(h9Jf{P63@D-v1
z4n&6_hz{})9a2Vt4lp?o9bQ6oZ~}wrsUmW#Uxn19J>Zgk-VcmwuGuQ7W$lxtuNF4;
z)oE=UF3NFuS^?8!tv^)*t-^FgG&@Y~clmywKjFt+gh7v5!Q1uOliv#UIaQ@6qRTA@
zUNuSw9h7=47j~x-RhhChQY~Im5(VCga#3z)QDG9l0V&?>U?V%*fB<`$cZH;deqa5kzsdZ%c2C0r&Q$p&)W2#puY*ntTSLxW&}Ga#G&K7!5%Ph1!8F
zeLpVN3qi*z?nFk1FA2J_+3ed(I~c02w$9J!H*_|FZ5&t}V8V4#{REVMs!gYRJbR(1
zzi~$fu(AMP<>2r7N^8qMJ}*UEcuyt_F>gnfN^%L0x1m?pnz$l`<0y2qJuK=YiND$G
zQX;J`HkpPAYfyr`2`7c(?YwmE1;N}YgBfD*Z3*M+dE!JrOD!%pNbe3jlZ5t6eh27{
zXK@mc8|wG`j8|cu4iq_Y{<%-PWnf%}6JH`nyYN^{vTP1weF!WnL157X0*lZb`THMO`2WF==9)Vi#=N!)UD@=PtACyb(64=S$NP)=(UEfJ&w4~(q|XjM^~ju
zF6wtz|86!dZ>cCxAFf#mZ0)(?x;07yh-B;o*a*vy(h>RqQo|!4bqP}KqyQpo4;a2%
zIFrB&ljKzbQt`SL&<3QkyS=XmNF^~c5>VoU1liQ2CLk5>YaZELGObBXKq^9LS%5Hc
zs2a=@+>8?}Hc1GTmL^$d%r*<&WL0HL=Z|%S)^NY&GZag4zt95#7YJN+K!7Nga(SvP
zwN1x0KB$SU>%iG6)P-BWN7pz$C=N;X3i&+)Nv?@OmRX%Y?5{x0;qgH-P-N0W#3hYH
z{u#PvFQ@i?W>X^}=EaX}MKv475qA1HZAGL1(e2d08Rcc$oQXR30kqs
zv_oJczLb(VMz3g&)RtI9GQ&}$Y{^5TXNM=ZT2v+d)Azp@n|9r-&&MU~PGeT@9*p(<
z!pL>0lHR2}V>B4;enivbcR>l0Lj~l>3dm8709c6cfrUr~3`5Et;2ak6fq?2W$Pok<
zqRHnc3$gGY3o)AM$wH)Q_{TzA`Nu*mgjk5D|5%7nu1^-C#6L9%)Dh?rGu%kF%p-G%3Du6wmfKz2rW5jVZ;R#uHsfEA6=?-r!C}QqEJuh_
zSV=~eP%cm0xF|Wn!DDUO;}azSAwnLU;z|F(jsF0q%hX4d;O+7MghcR6{6DiKSU3P;RR1q>gv^gH
zgX#7fQA>Z)r{}$$`E=t%7595Fhp#YOTXzrr&Y}NAG-}po)fnO)O`jXK&L3S?V8O>k
z`u0P84*bI0GvWMeWf;9-7hn39EoS1v5?4K(A-y_>-c<>^Tj~T0c47Di4rNT={~D0Z
z{F_7fZy?S(Lp|{LL!5U8c#WNiH)6nRWFt3&69!(Rf6}wxz=-@St~ImyD(U&}s8f9Z
zBm$6S_(#fSCcAXJ8tGy#rxS;7Z(w1Fw9i5d0*|Tx6CU{_M}gPa&d%iQ8ul+wVk(SQ
ze@x{++D2~gXyUXLR)nDAesv@h1RWz>fDldLDHJT{X3+tOT2|D|dKz)6mFmgERQ
zgE_2LcKvDccH5)~#C30LJMH9%Qb){0gAea&;UrN0{^1*MVLZ!-nTYrx`7aY@yn?XE
z{{oLjmj4YN@nDP@+{TP|qNd}`{}T=WPXxKI8ZJh#-_SBd^X~1_THwFf5rbe!>s^-MI8P7^FngGOTO|GX-aU-_D&ONjX+bNHXW!xnm24-p@%jNmJOdy$yhs
zyvZ!i_MIwuw(DH&Ehk-z2v$@-_i{-SYQ7ql{wDT0IoLfb!=c{*Yps7s5gJ15bjg4e
z6{-G%6si0E3n}S0fWh_OvGD&&kD%2vhnuI#a%*Osk8!iU<&4-}+CJqEO
zATR^LXyc6;PETNxGsIkk4cUO0i~Lw-+Yp2dp&$o_4jEAdh1Zj1gahIn`fo4|~~xe;+XjN}jIH(@-x%XdH)%UQOnm{8Go`T+D>n<=9X6kz<#?KAoBL7_d6@hIZuz;)zaB
zdMZ%98bu`5`tZy!75Yzrf2QdFO7uDy=PpN46)xej8
z`aKNFHA9aiA4U&dybUJsk9LgVUHZ$<9_mQ?t|GskF_jK~-x1;rDunaDlR8{GjW%46
zRk@czBXxUK4MQ7l>Urs{!@O|uf&vZIQO7S+{5kC#m-(@VHxrbDb4^~tj54h$q9x%z
zF0?`tGh+Nwr)=j0W1oubhejfAE`1QH1A|-jEnJNe@?odHj>9i6$@^p|lOrL`=dU76rTN8y>*OuB}u+YS2*$mvy>lxg9K==d$hBz?ah
zgxcXvua6186%BmB3%o%sR!qp|in$>FL2dj?^;xZZHd7Y|PDC3){LUjT`*TOS%B}wg
zen5f0pZ|*hDrM8f&*NW~GYCsQa}S7`N5;&uVxc)xlW-%ppbdwBb3a=RMO=Ck$qX0o0DVLKCZt^zyN^-7Y@QL^i(z|Q@9B;1hucA^_Uq@nj2=|AYuk0U16-h
zSWWEt>#We4zMCEF#`G=c;J?Ef4$QZKIp6fl&qucla20Q-e@t&X+4GlnDqYOL&UxqpZRB3wUuKrm9B*MM+ax
zy*sANJme#JVc2{?Kd7a&fdUX5^TiyWW>dLVQyWuxU~Yii9qiOpetY=#L`-F|8G1iD
z^3Ce2cNgZQ)~_9a2%uJF(@I09r<^cuVpFpD5uv^@$o7=Il_s5HRb?4zT2;fV+v)Va
zxSlPqAK+DmkS*5@{&;?LddairMuVg#j^ACL@>)sRrUi{tZC;TCoY%b#2O}
z8e)$8a&i^@%p)k2(u{2674*RFV_;;3Kyqsrv#;RAT`U*Z)71)`s%NW*4|j{32T0=#
z4$`ZO_s@B{T)ZD&T=dxLsHwIMUHWOdK+oA7=dCU^wbUoS;?`A2l!7Wwkox1&`zw+7o?j
zAsRF~Ie*7TWa_4}OVJ?q9u<@aI=&homPxe2z4fXRX0oHk+Ej*pxYfnZOl5NdA1erd
z1!G(B-^0F+p2M%f@14GRb6n;d64Vy_pZpX>?+5rtp%N9{6#XAm!Sd(QDTgnocxt05
zXstg!g-XYx)7N?z5&wtu2StlDed6Ac;Mbs27+61m&lB;EqFOU1V7xB&40KjmpMj1}
zc5()ePR7UY-kzO{ZT~AYqT+iEs!8~H@o;-1!p}hB6dxu)btAv~aW)4&@qP)LGB}Iz
zu$sU|yw@wf1$OOj@rQhHXLLMS-T(^>Bzdn7e>uJTFul2fD&((3to+@4TAWP(m|af`
zxMTQjG5QQ-&P{Rju!1r$yVeCH*c4T+rprI3H=7f?-UB(e;kNkI)!!~o<5Sw$==8rk
z__-K8+~13RJS-;p^Gf{;>cC=?zY%PI_1p4a1fBX9P(9;6x!8u^^=dlFpR3kEC;6LH
zorV`sJ>$Ppr{RW9@biXF@SAjiv~oyG>~>_I1~$3+okdc
zizU$uKQQUgG=<8F$v`P5J`k(c$Q{I2LR@%=#KZUmL8x>11ej=?E-(aV&Y$
zv*q-^9;Wl_KP49;R+Zu}uf%I<@PC5V{HV*6EalhPe0+WTyLGsy-n2B#LeJyZKarPr
z@9XuxIJn|i-+kix?n`cFA9gq5Kk0Yu;bJGQZ#b3>4pXT+F2~R^JKld^J5=KziMA$f
z-ylRieeKkwh2u|~Gu1c`f_{iRkda31i(`uH=qiRGHv)kWQ|~Ud4{T4wncn2T!0f@h
zf_i)?6I!(4;Py6aVq0LRYL)qwOV;jSr)Dx7^xf`EmS>9j;d|+;nc?jasV+aHII{e|
zV#(~KEt%>=;F57p-)b1KSO_XYE6ZrmSXmn$RZIs%lI9gTE8JL<_6T-rO^N{Yb{Az8
z;wJktqM(YPJRx{-gfU1b$ExvZx(JM#wlS3*9qiUrR%alEqkna^Wu$=y`0RK&saZ$^
z4J9KDx1m8Qq;VT+?fi0=-OYViFDdS3HMP(lIANxm7_nmIXN?srKMEF0MPfsJ!w6B3
z*ys^o5%q)*BzePYkcV_jOlz&o^mF>bo$BpY6(GHNN`L2xW#Oq>D)?k$zdr7;qotd;IRbNfdPt*D4)a+M5
zN-;I%G*A(BF&V_!Rk(L4C+H6_JywDkT>+B{6Mi+hyNC0vz&EP$VnU1ZAO5_btX9P{
zv(R6~Apj9-e_jk=X7BCp4q5hpn1
zLXw!_eSIP64E{6h{lQs$h8vxr%x$PrL@YNaqFGDhS*Z;
zC9V1F?%__H-Ch9Ye+@MMJ@c@ke
z=;{Ira90PE2jG_s)mq%!L-m7$B?~TeSr{2}oCL+Dhh|k=KP;Ei`TF)xIAs9`Am(eh
z(I9EKv-7ieYREoMVXUy_V)c3UQC!k08H>;2_Wg(H6omALgbWAez%Axbae1&~CPqmP
z!ZY`We=Zn6LFm^+IY{DCOd0q!7|)Nz^(~|)5L0O}hw~<4u*=fL=LwAV0)`Uov5>79)7o4C
zrt0clLjQ2CT$Nv%$YpUpYC|uji&V>@fY8g<_JueG
zB>c7;IjTyRkFzP99Fk)Xi(^sr0;78M>*?DRZ0>%Ag{nQ^AzQbwbkgO0(t3=W1iW08^2<>bJc!%*2c
z7>u^Y;j-a42!O?WP1;Qa{V4k&BN0o#<|X#`eO_YCIx7%EAJGZ*0-pi}qVb2KOpa~S_lh;lebNcaKf*_4g&hEqn4s^L_}Wz;~k
zMAX>3MARuUhh_p;czsb{h}DQNqs~SGYKiZ}Y-B@(7CLf_NqxuCvlm(?cPw!Eb82l@
zbX4g0^8|9j-4>!0Y_q3uI2m@?!o?H6k=qW~I80=EsPgEV7#YYXCpR?9J2=YR11O$6
ztQU7s?7Em0OzunzWTa9f}R54BrZ6cE1_Hz6+48fiaM)_`
z03)rxyWGwx2lu92-(NmYVTp_Q0&I}K1>f*iq@Vi;`hhb9+30R(>O%=TAVOs-Zd`tT
z2x7^EcCam!d3xZ}%6~z(%9f#$2iQx3)%hqQZ({EwOBC+Ee}CW`k=H*ZIhN{^$`FHC
zTg4k;$}sQ-ZIL`G^(2A}GS@t+LC@z=RV!FoF!U$f>)ZENn8&_9i5cSk8;lkHjqJc!
z8oQ8H9b@!#!X>a{L=meNM8906-POykGK!1d8^t*oU#YkO@I&jncM{-_L`Ym;P#ERUA;buA~|1t#V^}K6wrZzFqe?AanFJSMit}kQ^nP
z;SQR_#d3N&L7CeI2jr`z@vPS4TA$I5&UMn@x;P;CO8-kZpuV{K`VS7M4Gzc}%D*=b
zXrqIj;ea;udSV=qrF}Cp0y!23u?8Er^0yogXhXlh7Y@kkRl~S1KJpj|Fs;@
z#yC702PFLu^b#GRX}6c?KyvgE#eRRIbLu=upn$~zZB$@!K-S;uB+ka4Ee^=~dr;is
zfGlx72eeT|NuwDKvV+gDWC$G4h75%R+7O{|K$eJyo~c4M8xj-_$P)21QgJ{V66!m;
z#@H(&mt|UfXruA^j>WOiI=N%9I3QszI>!OQ+n@idIUuwD|KNbA9FRF`Pm%*NJMa$<
zNckOxA$TkfNSa9PQQ2I8+oLiRmn?SOTdMx5*0=Ak8ywK)4DpFUmKZJvRIgg<=R#H!
z@vTm{1S$^5Y$478nWYIFP_1|}2V~Z=0r2*B?+n0;>&>q&Tc8))pmT0X4S{~?Z+AK${=iP^{5wL0t}lFW%3OKMiUS0tbA
zgIq-KFHhCK#oxzQ|50P22|tL}!vx)adGWre+J}RXYdB*}d2>j0L9fj^5dx&0b@L~r
zJuapYX)1_7xEK+v##jY3_R(M4#vHW!*Qq&pJc7@7_~zpD^8D>9G5f^CtbPdx2kS$iT||
zkJR|Ecm`+o1tN=+db9aTKZN4dgm0wkn$)NGE0Gf*+;zUKk_}!-^ACrzR`-iJq*5G7
z9DvqhXR{PWAojx@Qf~2{^1>M|T3^
z<+Y1a=bPE4Mu+(*7@tMpe
zvSFd?g=I_Z^;D~)wv=3>(5a<#`u6bXHC(H_ygDvMznotk|5(8F>7&CdSU`U(e)$p3
z9>D%%d@%xlynrjVZ{J-Nhd&>lzZPO*U736BlIAUU*@uvba!0S9)458lA&&Y(W8W1=
ze->Zh@`zYU6ZoibU1Kd0S;KXP7g8Jf8ZTUbzh8WrihMDPk00?$J=`9FV^KghiPz@V
zpC^!X0IvJY*E6`E`e$*ooP5!D^C2Vl;!fmekv9xPq6BDm2G>}j=A)y_!#CoJ=2R_X
zhyqN+1?lDD0dgClHpR^XZYqhZ^>etyyjsCU7H9;n9EjU41>SHF;|JQ8cYnphARr;H
z@{8X>`{g|tsqIE#xYGh!iHr1wx(xqeDn{j6Ce4R!uSf~-QH}}JB@}@dis9n6N;LqF
z7eYpz7sc7==(Xw@-U^4hK9pk&?OUUa*N#CMebTP{?vQe4B)%`#d_ZtT-u9L^L3EY_
z=!ZyUv4TN{%n%TS`S>uu78kuHxA6I4Y`@H4tW|G78PGN6o2!{642{STDgKlBO7stw
zZyx9)$*w5EH&hGTW|);#CPQ~YJX5QGc-{?@5r4UUv09JSw6z|szjz0)(Sw12*G#^N
zR|Gjk?&0Fl;LA<+)?8%rCx%s2^h`ux93;qhp*57)i6?)`q*^CCwUfS3pa)R=5iFrdjWLo}
z?O+MP)xfVJuh#CHAOBmd2k{om%kTEepF|>}ey{vtD1I1}KZxX8{bBjTuK3~QclftG
z_;G+z`|tyFY^N-GApVBczZ5_0mw!2gABG3tVZkH#aR)0oh97pZ`V;s8`c{ga%AXF(
zpU%Wj1Kk?*EpB2Lja516gBc0e`g>XMe*6T!WMI#ll4VbIG%8)6uZ1t`ihHS%a
zG3H452!~pIn!JJn{eP@J`Os7H>g!jlj~P4ceSKN3KIcbZufFQS<;LoJNm+enKS-#MJPT12frowW~E-{2psui5GwRI85}NC!8xTz$@uz+Qbi
z&EO{X9Z*)E*$>j{JMgT&T173azJc+^k8AZo@4CMFhGpDKx+wYqDp-BPf2_V{t8ZAX
zJ|-RB`zlYc_&x%A^~v|PT=Ua$n8kMR%zltopE}MGsi=k3H;k-4=v`-4pFB=wZxPSr
z9`^0=-wN+8@pW$u|0ni|Z~#v}4=azeob2=l2WFu9R;1XtoxoYEo`_SGIWbh4oV$mw
z-@*1#Cj9G*-IGc^g2h+2@X{xw=y+J)KS21ZEGVOMMnSV$s1S>bEfSDq<>$7vHI;vT
z{F?N>ZJE05HFQSqf6GL?djHE>0CJeBt=EBy8mZL)KUh&CMn_1iK}C@`wWcl&d+axN
zW>)7rvp&qYi0Fq%vG1JmdV2=5LC^R;Z^lDXCDM#Hs}0Whnzp9$^cgRSpCgFg4xPP{
z&BNOMEZ(}E-s(kat>$69Zz>XA*@O9X{bjNI-CnfbE`VVgQ}D}Jv~tJRc+na=wgYhJ
zAT+8LZO`vBS~JJ-EpX8qD>B@76d-U=lsd~P;UuRlTM^N$iKVDlZCQ%V5$~*}5HGSg
zErs4nnwDa)9ZO+W8?+QPZO5;xAL*7tk}U!o<<_k6GBdVj7Cda;LNMlcrMWN=c1K97
z#+vWZTAR%Hdga!P-*gN*JLAPmLe3elw{PZ*AM$4W27YLu+4Kg@YJ)SrrtSE3^&@@8
zYi#UmY_yuEVB-evld-YVS3%E0Y-1V_5APA^7d
z*dUIMswq3%t9(63ISR*lM&jVj5?(fW3rYLo6^-@uepURo|3mLTt?4P&K)qt|W}JWtCA6O@u
z)8U=4;*cI`#*%HU=utIg>qaHu#?t%Je98s}%8YmlH@Wyfg2#C?S^fU}Uy6VJzI4pQ
z&*NX$T8{63_D-QtqZ0ueG8|$k0v2CpAPc>mJqv8uM(z}u{VHuSt+gN8C
zPt?Y4^rdcN;RC1JSXa%~j8*MPj?7-%fwT7dcZb7Xt
zbk5x!b4PBhd
zAWhpobh8+QOS{@v)1uDI@*>lgt&E(o@
zoj26u#gV*PZ-TKkS-NTJYMh+m{py(gVWWMHulky4DR)-xMO}b_Ig^iHhW%CQMo09=
zgUDw)M3TuECr3vpD+`)3gZ7MJGS>oc>Uta5oVqoX7K8F+rf#*-fzRAzqvIH>O=sRW
zUG?vKUxyMI!}FH5(-GbA%-Ug}HETD!L7A=4L}a#FwI&-_=g0?Vs2G4JGefJL4t&x^
zI~~VBZF=*1D*FD>`#O;HQqYB^?Q}$UJTtTxI8jLG1!aap6OkFZIX11@(b!H02H?re
zP_^qo1{6MPqn(c9`zpWJc7=VD6iHCh4#T(8@#Y79qV^Zzi<(1-(u|#sS2stu45ahyO}w=^dfG;9wayzAHg*@)
z%H0HGYqE6H)YXnK7#_Ud>6|v&>G-O5Y!KXQ8h%R(JW@A0qC3@!uKD!j!%4<4Ir@>X
zuo$D14$$64HfOFiC{JeQRvR7o%uO~rjciNeuo4sgfhFZ0@IYVRnoX#GZ
zb4;T8J_kN)qkWFAfjVreHht5yoTZKSIbJ<%U(=^XON>rj6Vp$1D^uU+)VVEjTP(!x
zTo@Teyt=?uGBq&bjn9!=iSoB~T{OGafL#)Et}-P@CcAVLV3)j|acoXD*d?#1Jv-1E
z;dU)9YJN_#bo~RM7-OsE)ypv&hAD)#<|3uMwK)c;joNBs)}X?TVKi#uZTh_Z-}FqZ
z+1gFlS>9a~*HicOHt%JxI&XUP=RLeBSDZ{&*UQP>hgIUW#L
ziA3NxQ*jk{Df6R4(qb_RBtKmYVr9C-oheO>!w=!xu<~Us^Vw1Ee
zhk9?bX=AZ?tU}~Nr0-OXiZ>USHKv_iV86;445PbO?Me@NXL?s!&Un4V;2_E;Na1cz
zcB3NvM!dCFTWQ~8I{T{O4{Etn+ON$zsupGYZ{Rtw0`4Rhuci~Vw6I~r%EZr(i7`xD
zW4?jJWn-)|v#8x?6yU8hv(D0F$q_WyiGQV;(hiM`)yji5SZik0PjtO0fId4qIsbWl
zc6oR_-rUAi`TW#AqB8i^iKvguN%@X~%7vhO*o_70Zb>9xP+tW+W}!eG>o$HW7sOfB
z-pA?m=ELOr_u^*u$7}_O=*4Rl;*|#pL55=TeH?k7-WHKJ;Rkzgu#N;)aOcg4gzlKB
z8{h{oSP=&xVU190PM+(Y1~%usH5A>%n4y?-btmq`cH#~`^m`xBp|R#N)_}lra(evk
z1YUul|5pPSc!WlJj?#@AhTXVI{c`1KH!i$*Ox4Q9%U1pVs?nBig^FI-p1-3Jf7NKb
zX1F;nbJ=*?{;HTS2A0;|PVi^2h3rP2d4r1{k<=)-(e>j%(fTI}6x^s&p=r6dXJE6T
zrEXd-0|GJ|vK!hQ^Q3jlRG+}#^8er7w|}RRWNH4~{ws23&UQ)FmXrxdmR(hS76Fpk
z(t`zLyNG;7CmytiaJ}tchE3v~TTAG|Dhuff0kxXryVXcoeGPn0S@OaEKiLjWVoI
z1y9wz(+6CQZ$-G)in@Pn{0M&MorNC%nRI`ipu?|@T>JWHk;>xYgL85zyv0Er(@@b<
z!etLU@7rK+*oDnL*uNBvQ-`X
zqLg1b^6h0;8nXh?POCjpIBF>s4aaaE|RJ9P}h?-d9#vrP$fPY#(=aXpdcK!UMg)@v)
zC9GG@I+f!Si@QLoz~XMjyeN1{EM@^*kof&{@-XSa0#y&t&8Je55YL1G7aM#-vO4*U
zcM^%HM09T#=)eckTJWjjPd<+ZjK^Pm8?D;d4PJVD7)`Jo-||(o%Q0SF#7tj$d=^bU
z^`j_mrp;RS`frQ5x&ILSPFZ8H>KeHQvqb!vSR$5Xmx$l(61k`xOAOXuqTB?*2JxBM
z>*0+)EL+Xr%T*mua3ZAXS8k=TQg%9h${87I)^x|}UTW53%brhaL9m^O%VMXc)SO;6LAUECHhEk9(
zWr@X=mk0r#WB?#_&Es4KfTk-k04%Y%{u1TF0yZd%0R&({OMUBt5*ZAjkR87=nB|<2
zA@3*yaF=LWEMx$YqJwF}IJ9gTK;+It*vW3L%QZN9?rK>U)|eru^X{)aX#FYwy)bO_Z|
zx$CWsiyPHz%;4f(vzmJvxn}@PBljMp%mBA*Gd3dKyvMrlx(H+EA2i(fvvU1Bb2xPb
zxt6`+1Y)aRJPSR62C$1SgX0D}|05&v$QjSaOD?EWj6g~rzULE*L%vsZ6(4-aG-g)7
zV#Dr?XEdX0Y#Tx0>~}7
z1}Ru;w7^4BOtaRy#JJ~e9CGudevYv_$K^`D{j;=si
zGU;5X8n6EnD#pv8KM7;QeUIa7Vkb5RU$Z%_gM@y`GTQs${Xi@MVWIFgzVUVr`bS`?
zJBFvi=ZG(hyZiC43ov%@Dn+E}#l!7jI(vhcnr4IPr$NlU80B7vokqP;lhG9m&cT7f
zpaq>R@1;~A7{!6@r1POSHX=mt#5KIE+r~t1%gxdju_jV4hWR8^c0k8*IkD``z~vVn
zaOhz^9ecqKFMfY9A2Vb-=;LJ`FwFbeyh99oz(cPc@X&`&A71dSZSNoC!{piRvY6mX
z{r4I$xf^e5O_<#mmu>Ij*aI7_@ey16uj$gb6j#1@(Y^Y4_@hfxO$4M)8?eeR8cK0F
z-mm$EqP?^O7d%9x%uTY!dOEGl=rX3@SOtmJ<;GFRf!Cq?UVSN(TcV4EKl>k4b@s{i
z!{;t+v-p@Y5zwWFiF;RgNB6hg<>aB)Wyzz2+q#a1lEVF$FKGq3$N_9+f=GiIqlV-v
zH-j29Rue-Mw`*LyN7@)vl2+|pFxW-X>-&D^o*|>o{d6{d(1`lF>idUQ`)J=PZP~+r
z5Ebh4E#=NJ`y
zXeJkpg^yr`nCt%Ke~`FQZ0Y}2<-xl!8*=R7h_jXEwE~H!W%O{lH31cXKQop#=Ne4=TTZWI`h@dZ`
zEq3jo8Q+W~%UR`L2HKAxSVCopItbuX2U-#v({p#2dgK-79NI^0F;76@IHV_Ipa6`a
zAVjk(wXndAL_y|IWuhQn((HEbhO=G=FBXopU$0n2;)_K>CaZXjGp|Q2)GDefc%Yea
z3){n|G|Qc{daI(YB+ADIGHOnL?%++-+=z+Vhh$f0m=goFaI%bMq74(^uBbppF-JJ#
z3odexzCiuqb(G=t5V+f)PwAk!noJ(%_ukg$+u>*+iDXKTrt+jyTKn6}vAU`@!@=sM
zHx`#~MlQ_Of!!R?R>tnM^GYChe4QJE+;Lrns;sr`szEt{ykb9jqrs=aD8@{WtwE=O
zC@fx`ml_=cV7wzC6gAu|X5d-ongjFHN*v6Ky!@NWPZzBx7t$GxU?HHD@vYKK!b{*=
ze03XxZ}d$Vd5$!`S|&54;=BkMr86vjWS=d?L$+l$;;M383w1M;+>cuY|JAs>Q@$Dz
zxZ_?S*Wd;=sY3@!q1Y;asN?SV!(a;c`GDM)7HJxG$TW_c_3BA&rHSZid^IwxvGhYs
z>c@SKnd`B~X-F}+(Ml{t8+MShe;$XhK$~kr8xb$oaGrv
zX`2~gGHGYGkxT{&8jF0Hi&zX^OTQmMD{4%p4`~EA9QQ_ZlxslVPxY+4hyoE-UyTE3
z4ex7HAT-mpDA26ui8NxtJU@P>t!!iP(^a~#2fRk1&_kE|E&Bz>WEecqH~C%g9shGX
z8NpRaJF?BfAtDNPy~>Cs4)F67X-M7Kfc|Yt0|0m7cTU>t;UUpc<6@Ix2bsacv^$>N
z4IdzZJS-uHPrX`_m93zKWi4O@#LEP+GSbB%MHnI}X=Amn7{ckRJIZBUy?B4FZB-sm
z(S}CbpC>AvaZy7m8bmwr{tmGA
z^KdkxjS1{!`GZdbJd4wP0B}iN`53(Mf5qhtATUPsy`$m7%==h;Q{b1Jgcn3`JFyh)
zh_7N%`TuF$risiN2)vadS57=G1>-I8)(Bn~olt7@-fD_!YZA{Fk}3Vy|5y7ZA3c73mn0BmP8Q21k5G|iH~Qtix-auJ$h4AV{q*I$rw>4Y0Bt*
z*E>V~j_Ke(=d1|@D#By|wSn>+;Izl};|uZK05MS*%iC%kSGL*edhpP@^%(c{uBVeb
znMqYzZ?zgIjkUe&wE^ZD-6o&u#9?TZ)8$CRDV#f!Z=?J{{QeGs<=Y-uH^^uf;%Z|7EZxmbN61b7pB%*UFIM@MO
z@h;nE^}p<@_OBPUKV)-^FCF$SPaE}JuYT>dCTc^J+YWFsaUN%PtheQ*EF)uU#*+uT
zIWN)6EWqobKRBUgs9o^4=?#t;<9A1MaK!V;1MYWM>Cbzh4ntHJ
zUr1HZmlI1_LpV@@mvOxDi-ke~P^vvxP72Sj3k5qzg9daV0xHlLFY1
z_Z6|f_|sAYcWO2PqY3vF{05vx;mZy&_RC~$UR)#4+u_v!OiB*rde8;O8Yp_?j~a=3
z6Um*p15F~WgnKUH9OF-}uU`tpyE!=2bg;velOc`*Pwm>x{ybz^JAjkTy$8kP;dfy%
zK#pD)F?O{)j?$lC5R%2L3&JM{09%B2+5x9}!vBo%u`|vBNXN1_`iR%2hz}K9zBv6Q
zznTzg!3zDo`NQ3?Bf;Aav>7Zzz8D3a*?e}7GsU-Cwei)cHM&3B7Iuuy85z!qEg=)Z
z(Q+j~29vn51T1!h!&xfRh(?(MmcS!84UAH?!*m5CwJib3nT7xj>SIDU63mZBCF=e)
z?!FKs4RQ}2q5Y$ZoEQK&7v@Ghb+B+CNy^}QqQej)Eo0=?30i7KdON(i6`G>e?t8;)
zk;Pa8lRONG)W_gsmUCj>M*|QQmpYq^s2qPWRDn~xpMWi3FYfMm#GiS$2&@fSG3W`X
zi9M&PfCC@&XD>}WBs^GlQg?+s%(Z(>dx?uO0P)}Z(EtS@!M;F4q&*c=Q5->`$4jmR
zGM1CT_F(r2Tj%lLKo`+7<@m>^P|(&DI#4f{L@-Er6@P_ElzR=$`htV)CSYzFTrl$
z9nVK2{Y#6g#VCy@w-qbOrZyFI!=@5tcI5cH2G%A+L8;;(>RZ7`CI85L6h)b7I=w|}
zkcmQZP$c0ps_y7>_sh(K86>>&J@lo4cfpWbx7UM0LD(2yNXRVJnFWL@ml~N&3V4`h
zS>PcTt|s8pp^EhI<(?`SP+#qa&^EA#gb!;<6KJlLA?%v+s=l
z$lk<|zYnI9ZG}Axxt!j2VwpAo!}$!ce*LXpMsv{Z@2IUJshgcT7Y-2JrNsUi)-{{o
z--8>F{_Te8!{B42*Z^pXV3W&`8fdsm^i@z_BXvs&1fsCuc5CmrwRhSQ%-+I}0KIL^
z>zAe(@g8Ys*lo`Mkg6G=XY&~{qYq(>vyx*JVYurZgIcQ1>fS~B1ZRm&4KL~A5V4P7
z5>phNy}JW{1A)o;T2X`_wcg|#B`byy7&U|_DzbtZs#`c-C5wOy7~jY|Vbwk5t}>EO
zu|!cecAzwBpH|tClw-11${fPSNcby=a8mMaqmyW}Bjl>b7$0U9+zvo~FyF}Ju^o2Z
zQGGmc*BV>}Vf<$mQ{W@iFDWfS!`K=v8MCAp#?O*c1*NEb1t|q;$GA?GX2K$B
zUA7vv^D0Sl>CGo2#&niuQUcXYBo2N7UIq2Gj$8QdI)~b41<`yw?87oQML|KsSCKC?
zyTh^;iiMEBhtld`=N@c5Hb4@J<-`uBbh&{@7K{(B8JAp2^()Fa(P^(a3^{*v5Y6;4
zzS0900Df-PkHb7~9~&&l_g|yWP#K{1LMMd94*C{4{Hgg60091HS&XM;)Fj#8KFN$dls(sY^l3SFCu~VW5G1WYGT@%g}OC^IvFYu7+HRo_=s_Vn8pgj@%kTWjJPR}DFpMR=~{8qMe73_R8HMofXy8X|%k6DCFtLYs*L
zT3fJNmB<;|C6e`$8b!pxj|bZzYvg6z!a1kCRf(P&IFLm$*a8Y$sLSSl^
zIn*b!k&Zb{!KhRmaAO6NLkh9dTJR2ch=AG|W_Kq_Zd`0YP6EO5IPf~Z7JhSxzoZQtZDMm{}o6;GhaD5
zumDm1aOipwl(#cF(5QLB^wTN)uu>@DiJ-_}gS9#sbNy;^P+{$?#48i3wNwuHo3jc4
z1s?A6Y`3<9A_C8ef>UZq!K5(NhVP4d*Yi0xi8K
zW5Eg-=z5YA15_fTlMM}0Oh7wpG4>(>NJLzbrxPV
zf4~=tr;X=#@H}zx#7N~5#}?5UK2}(?FQ_D)`Kr0=(B?t_L2f_gA
zU@(4PDc!Kg#Qz!b9O?yO!CHzkwG!xL9C$C`z#N1B65*8h6caIS$FMWe?`AMIZU(j<
z4ae}4k)$~>t@umk=BMryO!1DF!!RyP$u>y`h=S(hes>CPsTZg?CMhJ`6r(7De`4oe
z6%V-LL$HA@$#Iy$Te-~*7a%io${gUGjkcIf@BmBw{V)T#%-lr=F&W^my@BPa4jJP!
z0N`CA)Jut_CRZR2YS*&K71w0+aD!rqM}nt0PTOWEYwHIX
zjpzapom^GCA#@|q00t%uV1ocE#s~hJunlmX)Pt$OR5h+YrAHWPDn=u0K~XLyIBYvA
zFqY;god@XqHZ=Bt9y`LTO;cro59!Ur__W)_1X&V1){#e(6j3~OE~FMp`zhsMu#UwM
z9uqvyYN#FG%bFP<-m-QeA-F}BwQ{YkWo?zVy{uJ4BU{!OldK;vYoyWLG+UVZ_gbDh
z&)Q;qucB=WGXJvrn&WZ8_OYzLte*D7R`040F|A|dw%F&chp{c>LUl^wMg6DfB;c=$<-
z&6J)@EZJ52fV8?}Ud}mX070(kM8N1tsvy3JR%w;y4ojwf2_O1+hdy*|(~2a5qc=Xl
zSrR;rJFa6Flg0RICDDZ_RY>W6m>M1%gHG3{BCZldP_jZ2Ww;QzW+b0}+S&>V`^aqD
z)4Sb)&>K$rs5$U3K&ry_PU3fr&lcO;-uIB9azwfl_ZzzOjvPevCj*ajrli*3%}%H+
z0^P+^Q}AwR_)!6vkC|x#eSke#aHEI7{s;*L_PLvF4M;~ZScQ|yBzGP-_;VY}52v7JuAg};X>oBQ?JXt{J+x0r
zIOO+YXkHEAJQ<>;_-+sfz_RE}Mq4tXtrm4(TGKKcl`KQfv{j!?dbiWbc!IPoTIEoZ
z@9uRD8B$U34Pr=in&E)KgXIf^ILF%8Jbd^9_4a|3p=QnK1SgL1Ik*$40FI2nyE{ey
z?)LAfLUIFZwm-NcY?YTIdNQnUiAqVZN%@IF4$h@ujhwhU9nI_E*3q#W`1vrtNp91$
zW_W40HypudiMY9U3;R|oe=y(-inb9MwT;|eXGlBD)qq?B{KMw@7%Dd_!RR@(cZfcv
zy;F8C&8Ls30ht(@O9f3)aIyhDOX{Z2XNm&NnP*yF^Gs7<
zex)EGr&$
z*{Yw`D;MVsE<`wax!rDdim%KSr93{E6SG5XePfE~0+a(Q8rvJ*}Vr+^Lis9Zo{m3@e}3+Y1tsbv#*v!2nCN
z(`re!%U~#~yM@|;d`OfUUwyW@G*#t7Tm$&ZT5H-Ein2`Au#{cc7`4^Cs3)h4SdG3E
zijzFBh!5vMyLnktXg;8UX=AatwJeDoFh=8fk7A$d%Re9p_}l~tEz_DwbEX}qgD7x=
zsW=O75W!c%c1=`*0p3aIdDpAbi-h~nDwo=l2d-3jA4|WkMizyAMHZFDX$QAdYKT1H
zwb@qr=(N^pT{apQ&33Jtt}VM{QP|H(76&2Y#>KBtY37IJWRYvOPa%zb13aBPFiw;_
zc=tHA8yiC&Qayx%2j#g^pB)pLab-ndE0ebDH9VR^dm6db^|vDglD%@j4~GlQI~|(b
zIx07}JsRfYtJZcD@Wx4n;rHvyZqk+`iKl-^dLE)gA+
zm?Q&UuRazF{D>Y!w8!`j_)mCcP?*D(F9|{XHF#5!aj_{v;WiTtz2Uu*rT@U&2MQpk
zsuqllqrvo!@le3PMK(6aCNTe89KD7AHU8;NEmATTrgH0O#!Ex+(Oi9z8xPo8HSaXI
z2So!H)A-wWudXn5@Dl&yqOfdUfXeP9u6>Z>;JW4}Q
zF-ik`TJc-H@ggk=nd?k87Y_u(LBwq#n5T2PS20GHvapR|bO}AcRxgJdP_U7~CQ&RN_^rx7FfE5U#Ub3zR*cymthf7ogJiR^?_XKCD
za$9xq4U<(tZ%z;6+X;3Z%_yo(A`5hhF1bZTHM(AI4fw=jB@^T0PCA;cr)GLjRWdRD
zQ`AhVTD;mGRkWzThld$gUL#5-##d@)fof*3s+wsO^|cu?#&?wNmDSAT+O?8NhL?jO
zzqSlH$W|xQe{q$}*H}g#C9_~n@O2onGufvwWEafS8S?8tGDC(T89JK^wh+`ej;t-=
zZyZ@X9eFHYWB7mL$Z=`38b=QBA`Sx}lt$@{H}hMUBM0;={k}n91wbK_)u;d9KMG(#77-Ez_$!wTNca5`SdPe;JK^OrK!Bz?e{ExyTsZ!#c9^zWMtQ1RKd-7;TG27v8^e)0t}pztIaV1s`F
zQ!4XF0F%(3@RaA10M2xmO8}0M9{vklIL{yf3X3FwOk;B%ok|1%gQ6<|thfBxBtTJH
z0k8&EvjQB&Oj!W};j3B!g|B4=u+RpUAGHE-GYp0Fnz%hp2kLhnx{mlg$=U
zxgkzgi0XChAIEzQoIbdsXo`pQQI4%Y(7l4=AU0OK7v1C-AGIQNzqmR09M(x;v2`Nj
zr`jj1&hYiE6O0d(`_}~wFuu)8DbYSD8v7(~Udq#~6O3<7+^BuB#5h}Soe<@71Pp?r
zl}yESBP8?NhrVr9|L7gJ3Ey7EDY?++fqBCYaz)G~PTqg1!l+WEy4|$^QRCFi}QfrRi?7(h~%e00v~`HY??oP3fT%0?Xqz
zb0)l8HVM#l+2q1`2H8|vB%9RQHdr>fww
zru5JWP{U{F1c~rbRRGlVJfV}~Vi}-ZKHowo<>o$3laet_u>b#Wg-$Y4<^z4Bh^x;u
zL(+ec&`FpzALPAMRLl&W57iPCfkW3_J|U8^Kap?J2kC
zOe$F3E5PwYFsxr+0nT%Q_i2F=DFPB+W|paAd`xMH7+xt*Li_^MbU74WiQP{(IWoT$
zTOQiCI+Yj(EiTYGTOCN=;k(i->>Qi*8##LG!Z
zwKZLo$Ejlu23OiC_^3v$VejKTc>lE?ST1JJh_F)+>#gLe(pJ!VOSSe+inN`TKXe-9
zUrsMj9d=1MD$&(!K`lJQTgLOQ_v(4IQxq&7_fTxPiL|XLAGPFl8TBRp)=yNKOFi;J
zJWD~NoHOcjA)`RvJJIib$}`ROonLI;DPA6j8F@-A6g}{|tX(|bqDnouTjweJV9vw4
z#nYOARp5uhEh>58Lx~@Xw_b@K4*8*Ui#KiXAvoZteRPsneTveJo)Q>o{QW?>zPiN&
znYfpY1&-w_6%;ai#Ftw}*po9pFOI5YzIwq~z1FE7z??Zn_Fm;kOo|^L-g#_X;FY<~
zY0x<>w`=E>%rbj!Vp1WmvVCA3|Ng7uVOT#a$X87)53(8Vm+;T$SgYx~@I{jh4L%M&
zl@i=A12$0qOHZGQ157y^7u=dr3ycztTBIDz=2{B-?p5rHwG`@oR2&=P9SOxa_Zn1WL5pr@LFWqG7Dyr{z>A;6LL#R(QljD)!e~o!0w$
zyYg0Q?O!%pZIlx~>)>Te)=f1+)8S>thmEN+&m`4%u&?g`bHyTyAd~8qT8AYOJMCW@
zwM^H6SEAbh{RW<0%9rnE-ud8>kM`+mreC~^>udT%+5X?MAzqy;A#2
z7`5Hcd+E92YN$@}L%)%8
z)Cpi_f)0!|*)u>#*)w$J_||VOdk%ajvnVLrh{Cyj?y@%>-~|kl19ZCC?PSjP3h~HM
zA8&p?;9*-;PE~PBxysz{K6LT^L~kGu^FY;mH$*WTkWmFn(|9mqA<8yrOO#y~j=8Nc
z0;!>VrRZ27%fWxLvnFLc&Ut5ge(DZKECPwg$Wfo@UB&M-KXjVlQm6H^dfRBp!K;F$
z(@HgqHDMoAe2rk*7wz(Cr_!ud>+M#jl2NSH5UT$Ouz;(Q?EIV=7T9YD0Ht8O;>98R
zRzanj$E&$$zIn(Fqok+ZEd=~@a^Xft>BUbjf0OCO$-)TAR-btSz1-q0Xg+F_gJfo~
zWT7QdGTr0aHY>K`u`NbG^d}luQXX8DQdXcnL&Ao@e#ASTkk`7_cj?g5MD(Ii8QY|=_^Ty(X0pD`iR?egVpuAyQkq7?#
zgF-16+ggA|hHWL(i^YpH-4-bsm|O<8TQnbs+gSypvN9l?!!uZc+=D3JOxgcU=9`YE
zE+|`1-4mEXUOgj~ilsA%N-H|$0Tytzrj^sB
z1#B}cE2e4$hq+kRqWR`wJ{Ts0`7DI&aGy0zlfX~9jv}fiH(--_h7)BDj%>#3syst0
z5qbGVwp~J60s7JR`*gbm)vvAIbwr~fgIaXBCrK?!hy}(4z=qV4Gs=a1&Y+f~{anYGsJviitePPG?994p?0W;O65o$
z!0KDsEm)D|S`)hn-=+s=^}NS=!{H$oEpPI9r9Fc;=_9m@Pg`f|cm89Mi^sbbgGXAl
zqb>qwctGSgIB&1!*Lbo@J$en4Y=7|Dr)P)>|#t#)9(2dKQ(s
zrn*@MFeO7LaiK(<#?NH)FRa3?PEs
zc_{N1xjY`=y>g-u4ECY>cm8+KZTiDrSKfJ>;W_NlV8^@)u0zDq8~g*WB80(bZLuTP
zEDur1Yf|zTUw=ZrN*r|8v{M}&bs-%}@CsnOfkDd2H9;u!_-8{$*
z@TsC81LD*18-N$$H`lwl_+4^KeuvTJvsT?}45mBp2E7M(Qus(6Shm7>#&a1SR`1d?
z4|!>11SU(0x4ob=P};I~X%N1sZH0If?T69d+3T5)nB<_49HCaOp
z4&g_nr7)R0Oh^&im6rmrMzagHhjV4Bi!4o;<$dqduxp+`W&07I{>64<1MumtJMP{L
z`0yj5WYY&nk~xNN?k%`DPb@X-3!!#7L6e2^PtN2SVgn+XJO}F>`U*Vm+o5|Qi!V_-
z%5&|@NsvIO%Sn*Pm5G|4Mh)9fSaWd@7w5T~n)IS9Yc3n~I`&u`S~fpQvu?7iyf{=W
z-w|iVHp<)E?8p;9L?^JOzKB)D`W(f@$Dg6gA|+@Oc#WO8sa>pZG*5T
z(*1AI>gHD3x0~l)^8>ts4}&SN8%AYW0$<9k1e8Dr$&h#%f+i>f9(Z=zpcFFjaj#2_
ztde+i_)V297rEv3R$ot*%hE@fs@80Jl?yyMe}rIVpuaf3I6p2U*;svB(BG=BFg}|W
z@g?qim8D-veK=C>_tht)x3J-X`cze)UU~4vG|p=3(;H
zZ~?eFoH3^B@#6CJaD<}+SK7se8W_sVYw98O0te51z8c(iKMi5c;wa@ag1@)e1)Sym
z{9zU{C&#u6md?FeZ^`5_fzEOLv|VfRy33+}u3r{gfDv*rCo9#Dk81@>r}ANYd1YvqmD5UwdLb`{9MnFV54DMZna7Z=c61qxBwY
zusXQUgo{q+_YYu>q`~3rZWox|MAqWagv)tpF4U$&mH~Sri|mSVi$Sb~qw;xGEQZec
zMZ11nuaw($n11l6IdtffT`{LFjh(Y9L4kIw35W2*a;jT(wmGN@dy`HOE06Vb62XvB
z3PFNee2+GlLS8$8l;BlNfq<3(TyGBUM_uHTAcYsmKcUJX-&1wi=?`$#57y`DX{T9h
zoR)v-wCiUzh%fDj-U7iOf&WSxNnlWf&KyE&2U%63RlG!?@m@QcL4l`0`xvm!@#T31
z=_+vQhR$3hytq)94U8$JXH@x_4%yc_0+U!kr?$*Bt7)k<;46@#N!jgSzB44M##Om9;NA+Yd;}VulaSz|IzXr8k`OCC{-x
znUj#sQ(l3AcRTrv!^2kDFoEouL=NU-=mCnup+WZnd0kg?)DXZ29M$a0-4((HlF5x2
z@9hw8XAb!SPHD`>-bw8|U=7s);s=~Z!G2vxXK$+?iNnV-{=|{M)ndb9uXBdQfcb{Q
zMUq`!16U3Yw+M#}H%q7%*`2iWbAeWo$^Wu})>6EX+^cjxnhoda3=^=U3^QfRHUG9gxN0yyecd*D^_hrmP7Y4pG4`MY`9koyze^hb2eQ
zYW08qW8W``v+N!CDOj&FsgwyhjTTSn9V#@eH6zmFV8C6f^9pGW6(1W*QY23BpC}uF
zU#nHIu*IYp*}OEe(+%`uOp9zXlOf}JcXSko8kDZisU}D&Hn7uab+sI@Lh4a_l-Q+>
zq@LF0QR|l$vFN{h{)gjg=@5#NRXAGntJxRa%)E0^HiM3$Z8I>}4kr|4Kjo$=*w#eb
za4d&dv=NX(QK`*Wnc)hQ7SfhoU0xCsX_r7ANP}04Nz4uu-Bd$Lu8d1;l&Lm%BPp|~#EnCiHs`Pj*(MsPBS_Mz5~vqA;{lXZ^RdwgSTT@_vol*760PT_^6FBG4B$5G(KMuVlRIfHeAd3EY%jnmp$?Yv!E
zW<7;IfxmsuL-2N$<2-
zJp)%rl($K4^5${{SH=Za#)a_%Ti6qq2UpBijr4eGwyL_JMvy|4AV4W#hdMfn0vRmC
zmn;>?1XnsVK=h3^l=pGg~fXy&23i3C!V`Hp;tB=he+swcCyti9A1LFE^Ll9=dn-Lmlj0t5$jb
zOFs*XTdF`YjS8?koMTWjMg{-O(pwJA^+!xtxLE$2_)u>-%zKeH)LS4?;hbEJV6x_F
z=w=;i$b{(-#hQ2x&{5+eWzCz5*sol~4xg*7G+SQlJ?cTuhF6Ky1eBuaL9il%hy)~$
zO`%D*-s3V*(jry`dd>BbNLlsN#GgzIeq}BZUtF{WgE1}&-*(>BTlJ&*X}z6UT-ytC
zd0*wl;P6pRA3kFTgL7R)Uq07dxSWx3kOTVDu^NL!u{vcRHW#Z)PL6>emM}}v#BjUm
z!;0#0v`cRN7_3>67#zKJo!eYGd4Q8xQ5_8#c`0X*8e10{ptRCfW8|geTyx=lmQs=e
z?&*k*NyZQzib-sxn}O&rJi~H>A71?aVvaK4H%x>XO_&cpn|EkJA@jB~L{>$IHMF+2
zy?+4h_V&CtUgNUeW`<;|)~wcA9xfi$8*gjP@+neQy=JXdYsXt&wvPPBkKZ@-ix>dc
zY~fvlMiptQ4drY--mm$EP=KH_T
zty2rVkz2ory4baYW<_N2t;90GTr#K&S#S>fVgwTK$+dFPmGv0F&~=_>;fJMk6`
z@IMae$rvaAVMS2s^Z>g@Ck+SqsVw{MVJQC
z;b?2%qCrN0@s6a>wHj^~WBnF6m*b;eiRJUq<6Z5hkcN+o*0T~iE(Ej&HYVXEkTJfx
zjYLMe{?RyLl{K`%xrG{6R_Acu4wFb|Tp7J1OL6+=Rl1U3BTOdk>^73gR2!KrrrPKrcHMaU
z3m$ZOkGNL#;{CbFnJL4Jv)Nc}R8mLD)|rQQt5N!Mj99xV+(V~dfa(NylTQe`iGtMT
zclVReXv>?(_^BW3z*O6lwhaX$$-mos!0R(`!Js7Qt{UrO@CMQP9ag`=h(51O&hUcx
zn*zV&B;e6g)+5%DwiL4}EGqv$|3jJC1{H0nVsr3-m{|&bSfck;OR{l}oQ)JhDJSLZ
z(#hwd!?MKAm&00_5VAlKO5tMsJRRUKlxL2hp@rW$X|E)0A~>o=Pm{hJnSs8h^ML#p4@2ZI?FAK8
zQajHF|Kdtf{NAcM>*NA*VW2XAGeNA0c;RFc2p39VOkxt)0fHC)$B`*?@!ie_qyF;v#mrD!%SC
z-Zw8<628srfWlditA}`A)9Mf+MR(@+xYqff^8u=dhq-*ZY6O#h8oY!l8H8t-os-jx
zBfRSt2j9VzR{AG?)8*qEzc!ScDIPk8JH4x3B$j)Nu*20wZAoC7kMEF;B%Imawa&ql
z^`0p8fa$-MH1vlAX*3q@!wST)1klRlu?U_^CaJ633^IXxG98WaB*2M-#0BdCN+3~t
zI=s1oNM4S+gt;>2dMaw2Ic$isW$!bPR^H^DKsAPTl7hA7=?Eb9J(XIL<5ZKQ^uYDO
zv&+1AT+r^#)Dw>D7OCi>_vEQqY`{DZ4hytD4hBn9@8a~-Lq?+I)vb29ec1vl%|LMV
zyMy9k?q~wnTB@wXatv2MSH|&RxmBguW*WK)3zaC<_j`atrrf!oj7AsZciqu^u$78-
zdZOx#C77*II1i5f~hY*B`vS87BK;?8jy
zo|20G@v_C>aP6#q5yu_g4ewOx&)!F+p!XVe{4%Tx`!?JK+yhERBF~m))2w^P7iYY%
zv)?&wz5ghm<Q3#@BK#}C#`sv6PCL>7gA)%tI~nL#j!k8
zVfk(Ur7ZO&-U_E#xDNHiw5i?saO`pGXdBMe_apFz>v&|5zjQ&)2~P+_+D-_ldG*f
z8vc`bg&8G-(5Qp
zt?Z4^U9(k8jic?0lao_XMO{N&|ERo3)V2O;nE!zyn*SX3`RtglM#xkXHR9?24Kh{D%4a+G<*r(}(T9@q8MfntJ{qJU`|cNJ$0n_otov+b>9=8Q;wB
zL$?6An@t>t{~Auf8@T_ypFAH#{b4xjKy@q@wxBRoeb%D$FHJZY_R=~jH`
z9y%6lgQT>oSXjLMm(dD8m=SF&xGNA2^x&>IKS3}8j*J(7LODQ`=GfZeIQ6laGBkoB
zt?)nFg5sQx_itF=qvl^~daUVz;Kz-pmP$>+EJE4^&Mcfwz;CDtM*g=)XOr^&Vrope
zA9hE>zbh{YT&gHRc|XF9V`MR`JJmoubW;t}@a6LE#85vV?{tPS2|>$=QS9;XOXhc*r1BtM%EN
z^nao6#G;f8ZfL#O`~LeE-uJj6D|ejWc}78+GDI_LRnW!%AF7tIY0x<;xA5F(6?~8X
zP_mF0Avm=}OLJX{3HfZhh5s|xMJ$wU?=JvC07&VBsj$5WOpp&uX$hD@J}|fwkv$vU
zDa*AcJQjL2=Ftm>XT2YI@SRL{h|YY+>18{KMFJg_8lAby}@_bBUZ5olX+QX(09}6`zp?
z%2mU3enFKo5sI4^3w-3!d+G5n{;d8|1)=4R;wQ;RfkMX?-=pyqD(RN{?f2V+0Yc^w
zL#?nHWk&V*v%ubl&=<(+@*|4CY@zv2UUJ^5!JjnEQUU(c@A&`WU;ctW@mEO9)EoBp
z9-(U9L!*AU-um}5tfD~;@C}5>e|z+HcK)jV_}kd~+w|YDR?POLS_;??m_cM~wvv1D
z4EykJTak^}unqV$8A3f`oK`ujxCQbT=Sf7It2>)p>Py))gD_ClyZw|+^Gsj%chO}r
z60tS^5xg>gqC5A4%!e(Kr{1KNxA@cn5@*it{HM_fU&@kR?Cl)`aVDQB{`GBKx5D6z
zX&Ga@3yMH0ikz!5@7@?y&Y9bBEnWE+-beinwT>opR6b|Om8ILqcqZa*NRhq~+-ADOVI
z(}cHN@Yuvm1+wG?Sb&YJ;9+ntC4Vp|lT4)88nXy`^XZgDo@OX1fq=F5X)u*ipB#@D
zTSvp+2BR-r92Pa0-e9@&Db|Lb@|+ASyW#Z=)M-?!NI;tHf(Hqu;iUk~yK_B!>><0Y
zhiIF+3{5H|?dsfypFG^9=1D=a?W#jiR_#aUi!H4usfKKp3KF0t)mk=Fr~=!
zg`U_+>{!h2I1rC}LCuWwAqRB(z!u)-_loH7hvzajjgfJK7OxBR`C`xC#^7!W_U|t|
zf{C~j9`5cteuwH0e$gMmt7Vo#!gMU4_~Vf;l?95&;WSg=6wuWG`7k2!>-4lf6IKL7mURRC4_)XXhPBw;mI8?7(BErw=@(Q7JrP-6&(C
zg$`oBnCzBXSpl&NSRenz<rQ8b&J6Fe%DGzA;;lF>s~(tjOWg&v_>kGq
zzyrG!M)N2A;m<#LSp^%gjZUjHE(YBs1haUn)j5lei7A*-bsw2+U#dhzK!!5|xx2L_
zI5oXyH322g$Zbv8B!H}9C7MM!(!du^5v0;7Y*j;j@T
z-HbL7^sMkCtxXeC>Wy_5?E54(f!0)aGQ2L7GRcXOH$*5I37?Qt;JS8{YYYPDlIDDu
z^-kY^?i21kA;IF(>v0EWi7hb6=&tH7uwcQu%Wrpo8+a@Lfm7pa
zF0uu9o4hx`TTsn?fot|3*vP#Qx2drj%}&7h;%aPDU=8^0;_X16m&oo`hilG5CUiGJ
zzBgvWo0O4>CC($XO!TdZv<*A!%IouTC4#C6ln}CY085cWQ}G)Lb0GUtAKj%>79GIJ
zUE=vEaitq!(f`LD7c_)8S5&?5z`KQOR;_1H$R=1wqdoHmK#T9YUuH8O;YN&HUj
z=LM_5kQ~8=NQ6{+96khNCgdP&dN-VegzjwtjMG4|s{0Xc4Vbzz=}iQIV~rw!I1~dD
z*>FsYSm+`#9@~YSW)_1O8B_){Oc@K4&tYEy9qABAeS{{>J>0|XQR1^@^E4sU@-X+Qbs6XXH_VuTm~3IG5AaC3EEX>MtB
zE@*mPJH6b{Ux@#!<$S*UOcT6Z
zE+#XY_4>6C-w>nYkIP@DVoFj47RwDd7Ar4gAvlpDRzvISG4$c%RIMCH&lcc>{-|e#
zY2JNYZ=eUW@w~WQt_0EQY^4retc8*|f`SeRAprM!IiJqI(p<*3w^&Red*Z)%G=5yH
z?iNCYpblfDw8dolD`xPdSgr`@<6|tscmp0c)72QOLQ<{*17x+l`$T{Lcn7JhBskV<
zfrXTO4&QZ)!P(L9eXHLsdV}J;fA&+a)9n=h(Hh|2|M8@F-y6O=yBHRL=(kRXKNn|5
zMeFqE;_toF&Xc11;k@4+42rWp*y^2}ANRWWYwxsue9`HhzAfJ1$KEr1{qwUy
z7c6vu__TL=)CZmJN%wTP2fFxM(ftYkC4&0yb~-o%ri+u}O&2V+
z-W+!&1?-0Gb?DLSo_)>~q$U!39Lz5p|9y?@sge*~cx{;xgkot@GQfO*)*Kc8TN
z{h@jIeQ(fxQndQL0jYJJhakcb&Nm&LaTLw`5JyY-4-VE
z7ScIYv(w;GqTMf-)7uRk3>gMFBcaOB1*o6YbvP54$YOkBR8%^~LfQa;$PVBXCg2j@
zW<2?I3SD25u|bKJczX4D1_g)u-maE6%ME@7#`Sm(1;uj)3R*jc%l)*L#w2*~{MPMi
z2CSb~v(07-Vt4RntJy!5Hw1cR0b+Ld8YZ57_v}9L33S2({lDbIi`(_x2%%uJcdgtK
z1Rw_RU(9lOgDGCZzaX|u7qDWA1q6AYKhM7V?z{iITTG@`MZ14IYMs9s_0NxwNA07x
zqqC!R^IZw3Cn
z7axXw9L@zS6<`1})kd4MWF9$^8ksULVID3QlJ
zfCrIJUz6W&m${f+e-F90_8!C^H!{$|h0nAtjy$FZA23BpGXQ2v}K_8%+
z1$##>jo_y`4^RcjBP^f|b#DPA@|XwkAoA%O@?HYuA@|nagZP7d-U|GCFFs?~yb3UY
z8S9`I;kg$Ag??3Sn`fa4l|dh%nuWv0cR2Ti(HHaO@|I2{Q9_{N5h^@5howW~)pGvl
zXJxRgoEzf2f7Iz7{nR?f*zl_Whw~&@7;89`L(zl-;OV5X;yT6^zNuuUIM5_VgjZ{
zW;U_BMM#mE#bqAyq8YKIa$cE8wb0rPDYWC|
z@mc%tqxR{rUPv0SPEZ=IPFNaFIob5-Ckabq&vt#ygRq5}#me@5#PiD|)QVVPEv{yt
z?ob+|&Ilzk6wwf-<|I^<|0m1O>)Ai2b#m++|C}aA0!)!3!KKL2BK!byEV)fbUhGFa
zrI4eUTLw}Xoe-jyo7#t#9z
zwy|e>i~W#mx3O;LEktG~;_(n&2h;-d2_9Yb=fKaH8IkH6*A7EBu6baI!?N8Fi~5PhNbIJt#l5&&q`CN%4R0*60|6
zmY_lI7Cmw%SBvQYG+@781q4)`1_+=!1+eL5EvJb0bqZkdnT5P)zKCc*Ik7yXQUl<~
zl?J@|dW%*_$dQCZn^F-M_6oA>yY=`Z`e}qGgT!-ZgCRLzY-XqP
z$zJhDsKw%&%MVn&3p6nd23L!
zyC(ZnaCO?J!0PnRrJ5nnB>i)E%|Kp+(oJgtvg3!|8#EfPL;z_)_g0&A(MJQYX)P5V
z=KVD_qlsbad!r8FjclAFEfq2y&sWp&L?{-z_)yD7=?f!={0(c3dPUBpIV&^f`rleQze*s@oMEU@uJ>`W-*M~bhG8}Oo(e4hx1
z%1HE=ND#%#LRTfi$#^qXD4I431A_ery>KP*;Jt}8-aZ+&gxEc8;pLZ3RQEjKh~9ay5uNj3ll9Fw4%$Bkbk4(`tZ#(T;={&5-
z3MYAfB{)`_UQ6k0=P@mg^r4mbbFC0bThb&bAXCIA08?aV)21mV{h0KiPIeZ*Nr(kd
z64ETW0j*^D2tRBEu)c1tddcy^4R%W*X}LhWpj;SUMlMX2UFmg>$jHT>Wmg8fmlnE6
zbHyVCudDr~jFL*{CF!!LUF}zJVCn>;3(b*9mX!38B>p!^F2KH(SeWX$Gx4p&qBrFC
zS3NIzvMbtQky(}L8lXCJvgsuXOoAne&Ehi)IaffhtkE`-Q#@~1K)2}YQnT_y5fNy}
zIss)fVn;}Oww~!3|ZLmA7|okM%JpjrR|7fIVa8a
zaJ4Gv5>D3>k+al>5{KJ#L>-Ywek_dar{t$15(irQN;uTAuSXq~1N-V8gzG3ILS)-{FI$%Im;Y1%Vdew-b@SqAH{Xl&ZsSP=f*rKeQ{Ti
z8_y#i#tF^!aJ+s838x!&TBLEfO-KGONhC7s>vGN5igPr4uut$VDncSAN0vgWvr;wo6$KxXs#HM)8t*=+<>msz5UxWZ_Ov}{F>x5MyoFXO(lO!yS
zJzHQ-aXqvK*#aY;@3*+lv1Zk`!-k{_;VE(?geh{g2tR-vw<)Zx!$RbX>O8VK
z0XihporFs1>jY?XnuFYVK|M0DESxHz`ZueoS7&F}x5Fx6)v0TM>J-4Hm$jTp7HsjE
zh1@Nuvul)XzF09;)NQRwRQ&!w87BuVl`|7%L=
z{8B{sisj_$4A)wM+J(x_`?L@KP0JPqS-y-e*c;2pVUeebEW~J?6A!)!mL20-;VQIK*GfNVd#-43vOx@gH
ztZac1&ks>IcUiN_*Ks+PmFRl76ggUiOSP~2Em@8ww{gGPyEwt=G>gFY9P7ymSM7tVY2URCP
zhoohvwZBR?Q6oT`(^`x+fPZRHU8QX4>0QXbW!=1-on6Nc3)iYg*8tTifKAVqK<)2I
z3SjYBi_igZE_S!$1bH2SbqfWM8TB6*yQ2Qy`
z`seT($LEgP7rO@*DqjIjYW1(Ho0sx%ir8VNA;IeMgIH}fK+;{`_`i~5YjYY$R~ZfM
zCdsu}6RSK`^G_q&f5j{4RgIKfNB4^5v`^8^y!X#fitY
zV7zh*onu~juUc*7-%?X*HZKmZ5oF%bzan?YtecB9iJTq%^jqdIW88i_^f<}RMCq-M0z
zcSa5Y}fyqBIWuq0t=F0uv2)Xn|H
z$`%;${1A0>mo=+=9hYNSiLQrBk)uV}gpb-^lI2)(TZ^*d`eobqZk9vjkB8
zYmx$3eAZ*MA(*;(WsSB_0GUz$Q8%~i=H;r!&%Qmlx)7q!)#;y0)mDL;-;?z39?!nL
z1;|%G!ScWMee;s*Xl=C$RwrDmyc{@=pzOdQStCwoI7zk=dvwT;3B6Hn*>jg!Hx~@BHQ!j!U?1R}QFmDtDA?pNp@3#
z9Vp9kvNR>jzr(t@5Qr(H*3`{;;E3LNh$A}Z!6xgQV}*en(!-vtZ-kwxoAYattZIJm2st8p2qzJO{;ppgjx6ycx8G0-~3qfrZ+V
z1cX1{Ha5;?VIPrt0j%}n-bQBrQ
zsyUz>@_^MGw7g|FZ@13lls7)D-I}&eyIs>JWV)lop$PD6bqHdgBHXaPa9gDlU6+oEYy}Pc)DfOAN%`PFH_)vw&j44g1>!bIPihC<-oJY)=9$7
zk^|a~gJ#29gAU?C?PiVx+Li-P4~D&y?qJwDIj`p<44TZ1atmnkDpOZkO&hd^QMV9*
zN~SIV!GgHs*$$Jcpx5qoW2+E>+KvU=IZEW6^U+VePWP;yjUZ$?D|#i$ZDo1$#i(^b
zJIjb}8iskuE!ePh(;y!V+eu7taOo_FkSVmn-c3j*T9ly%a)tmz4q*waMPZ*ksWm{(
zFzmP5-8c`FHTYmzj2Iq#IRN<)@~7x35C>JDEc&Go?DHPA3Y~rp^$I{HWdhgpw|8@r
z`diw^gpb_9K$%<^4m=6Gtx1{`3mjA)51NHHo`de3bJ(qbtt7>QWierRumZM3K0G@g
zyvKL(dZ%%12*BlVp_#CAH=Bv*ULp>d!G__&*NEX;sAM#cm0Y|H0B*yDuN35V218^I
zwZ6dz%iy52&LhKvIozaQhKLj5H~~kY)tyxxUkKmaAfOJuUhllzn56Wlghg+tzgVv~AnAr)}GIPusR_Oxw0O
zZQJ&=?w3hYNR_j22XxMCg@i3
zKJ@V7LjGby9?Y*SKH+c{BlfR4zv3q^Pm66EtTSUlx#*D?&QOelm@#k4&xMr_IA1Lt
za_?4yX{{;R>;Y?R|fK_&dW6Lfo2m?fo2iWfMywZR+JL;
zJ;6P}EjaZgjzUl9PciWJF}p-luCI%!N7ERviedFzy5sZ5$ZXui7nP5t6sM@%X9sP(
zR#+q*YHP4!my94XQGcpFOe-kASozBUeVtTpXTD@#5xrX7N;Doy(Q9r*^j8!&95ZD{5Z`1YI{bSDi*E8jUzZLR{g?i$gQg{9xo{ic6BN
zQYb?Kki{cHkl>?2X6|>bcKUT@?v8xnhIOV;$UOWqC?&y7itIfT_iVvFpPsA;C$Pyp@irO>IVZu_E`R3~Ki53&wRN+byU
zP@Xs>kbOFpTi@kG=FAm&jZ7(2=b9#nUgHa|kGQ3jM1#e9*r#z;_(|g&LLU1Df#DTG
zew;{wVHJYZcRxU)h+)(unS_{0G}jJDF`Ypuou*RHam^Th=P?~ue85Q`UJsS=K$Ioo
zFiTm$RQAJq2Ix49T0zZ|~iNzHx+;h9sx(S=S&8p^|zwTe2;82yp3G4~b@^1iV
z3$5wZz7Von^#Mn5j01N%#~}I^OsGF-Y=n3T!RksUQdU_Z>&Ucd!r6?LFHozvnk~(v
zc;czpgo#w_kNlPAOrWRr<;?q=tIc
z54&5};-&^5b)XROl4uZf&iI_!Fkn`Bo|JoL@SGvl7^E9L2s@bIQG0(gF+QPt5~)~+
zh*a!Mf|eIVW*TRGc@`cByFyu2oYV`m$unTo3(FhB(4o`|qv0vpbBA0Y{l)Vn>}ry{
zL7;I>oK>3&mve@%ZF>f<-t5mS?|gx94L$lAH$|^sk-)1zTC>%!`Mm)Y5iDB*h>v0e
z$h!iz9N8Ag%W>t1eGRy3Y%lnJCUQ+BU=e9-Mg1n;cnphZte#n(M2a4-)yh=CD${!h
z!B93y*L4R0DN6Kehq$dia`1{EIy6bg@y4`eT`+}NB=uXzv#-^4fuXdb4k^1fnL7+Q
zNXY=X7j$aACiC>e4Z`!|=<5xx`hW*|J{W>yfC4Cj1^9=E+*9z%cY}85!^q+Fb$%5H`H8gRJu>sZv
z=bj;mvp!(*CV$J*2I
zW9dNII|w>dE|TG|%qw`Dnth2Wa~lZ-31;VW!ht#$P$3_VC;tJ2flzqZ-=S0X7=|u}
zyDK9(yBn)w0`*|{Ry87*V!au%4#9chO7ZsAw`RSGMJ9QP2PS#UB&tR~4W^^xhkT)f
zj1a6s2JZ&ypzIDcsO1ln6yCwzx)Lplc~KTXB`wQ?B~
z%P!pF*!lbsY?ONlw|UopD|ubjiYp)S=*%}n`+Fj|HQ19koi?*@F?H_nJ#}vmuvPTR
zG0eNThcLBg+0===Y@5@<6&pEx9$^1IbAQAiQS#^GFw!qc?KnfalM*RO&qvu{cL0i-
z+3;#g#%FRd@OSCPOWYsj0Nc1<$^2s5N_7+IgZ;vD-s#b-f}CJ8Z-b9rY)>6}D^X_V
z$=B9Y`fAO8_PuzjsOLDW0|4)6kA}s*-G5vF^qpV~scVUKpOI{wQMk&THHl_oz6zA;
zLO}&Tf(PeWp|ZsC_3hL>Y+!z9sE&Q=Bwqs0@nYlyIjN
z3_l1SYhN7agig3CxbVdwqnK2%6Y(*{1`?%G4`C+o5(
zYqkYBnpMmBaNc?)|EPSA@#(~B|9iQ>>IPbwx?0)#di^_&^7|d^dTe|k=<%X8)OE9H
zD6ZEvW@!x0bV07}b!eVw3>>?_XqIR!EOQz#7z@
z(4<3m!1(hp$DGz&riXH}5Bc_b622qxPnN_vawTPJo+OBbT%}F(&&YZI)>i65m{CTy<
zoHlG=Z?N$ImCyt`Y-Kanp^uT0N(MXb<$}R7B70&#oPw!-;W2M4#1P4%X^guE8lUZi
z%6m4C#b*|WUGZCh&jlx6HZ4p8bv*5KCz7@702q0bOcd>ZIXpooKb;2A*}E9FUBt*o
zUXdmZrjXTKp`M_Jg%}{S39BTaj{YjmD?%`*f7}Mdz9p(QV1_H$Ec+C&j6Fzggn2j>
zl|7;IR{kEI(y0)Ae2W-EUS%lT7P&;XJ{p>9Ds=_j3>x#8%&-uB46huPbe(_MLI@Z<
z@IES9Fao7v<9Tw(DZtanY9wIduW}960H*wv5ItA}SRf$>5CDb(6oS65gux|t0O(&B
z-x2!&UdCS-1%zp$ng7CI#R$+4yUS|E56~#$jClM>xH1mE*P$=d9}3?NgU>=Ciw_Xb
z?_hm=0E$=ecCn4#E~#VD66>kDj{G>!S>-ehtv`g
zrv2;rApxcob)_9Ym{#QhL~kp78EhZl+CMIoX&EcwiW$j_MFZiAct)YRE)?EYwP~ch
zJF#~&U5c98(DACbZq=`AwjtwJ55g@peydy_%B6`+$}Lts8z`CgHkTOw*l&q@uB;y}
z?JH=Ri|%!Jk_rkya1m?X3cG^HJNAbP}<|@%;
zxa^pmylV{N-7~E{Di4>FD07nURM%awvO!fQWW}Ma0%xs#6k^JIG-S&22#`Wc?8_mi
z__9%Tox3{_QQV9~^KqE?Rs%!xcTw}3KjUS@?#@QlD_NT!x8cJ*sg^|nc!@e$nwwFG
zWW9R;u+er@jb++)r#v2s{QQ7Y*($Z~W4Gd)x;Fwk+nEUkbk772bleJK;UfFw64ekn
z*PCk+Q>o8p1)Spq2AjjoW~CA^d<@=ii^M0Z58;zB3g_NF%Oql2TM9e%eAx#snYw!2
z+oGm6_E@L#h4)kLM_pMiqQ0CO{UuAHcRxn=);27dI^gdV(_N^S4{ITBD<{E2_=}cpUV!a
zLyhz4zmjRYwMo_NS9uyC*2v|fwR5>RmXmoYUw&F%_;9<)rkr+39?=TaFj=JJi#})g
z?t5o*|AcA{0b-$_0%D+F0J4wCRQQbJHig!oaR8*!L)4!_w#h;Kg~IYlr>G6_R|Gt=
z#t=L@=2%3`D+|F#UXMEEqDd$VeE$;72@
zp|#w-wr3y#lK2(+a6b~r{w*-+Avl7FDMna?1@e~d?k;U{hTDmlRixK+
zwKV0iHqz6O-m0DzYIcx8yb#r3PBUa
z=>pi+QTRa4E{OzFl+kgmsXKH(RrdFA=0mhiLiNYu#i|HMfcyos2q-}_NvS!{JteU&
zH0tjXUH{7ek=y=snraA_3o;{5qq!w=y-YfXhV+nJ#3ihr54ii+qIGoVBmFfZy4$BMDnkG}68&@W
zASPH=vBn(AwC;!^CBlr-SHBYTB2+)+5NF7<3~A#mt5Hdq0d_(<5&W==3${I&<-0YY
z?(vJWtMrf|Kxc|=mrE;vm*%M<{)gsHh3W%X*%hb3!|Mu=$arGfF~{QG51VA64V4Ih
zT?E7;3UsrF019zUl+XzZ0gqO{CY`74Xn-jO$F@A-E^OT32yc
zanc5BKAEhE7|0+WpZviTns?{YCyS1lML-_NA*ckwCaoGzs}gmd6o}Hxphbmel~Q%r
ztc=sAe{tx)K#IO5f9sB~q~x(qSt2sjkVRW&=gogurNndNm${c(&VL^N8*F?sIW(gwH}Eh0k;_=`;FPs$%y=r#+!9d
zWrp5;2aFSI5ITXWR--;5M8`@N{)tAT&LDLlgS2v^_8c`TNC$yKM`^cqV%JAPa#MKa
zP<>0*!$zFCUu--}nu2WW?ym~&P>Z`+_Uo_@cDBH?Y0TgO|u
zc-rv@pSeU5pYdq=Tii3H6uwsp#cJ)j(bOH1P>P1ZGLgAqf+iXNg<~(YBU2bEiHUxL
zF`#<}HK?*dfL<=qXdH&<>67>8v~oqOwfH
z$jHFmJD6Ii$O5`*_Q#U$;?KWKxf1jQ)DSLsAQYb72_7BE4`_Z!k{&?&=c|4=65`rowUM>_nt2_k!xcnOF_@
zb2L!XB;{hT3@JNXl~H@XKRI6kxERemENZVj#+zCse{;2}iLlOw8@JbdOi)pq0=+lf
zGw@KG8ZZrqu|))q@KFgK$swgO4IMO^N>ItEJc5GIVMWZME03!@y5%b>a&=wg0W@@{
z{m8x)ZuI8gTIq_R>`!K{`dh_`qoGmirHce{$382q0=T24d|!Qfo@z#AdtosL!RXeL
z05XF>Dww4&z2o4A8uwy4^@T=Fmd(KK5}{to69RPU)RGGee0!AuSCqJL`=%G~TO;O7
zWajO%VOyFXEuWmj`BSO<{b>=Vo=r*RUTy0;;IMH9Yrc})ymN$%l^
zuHcD7GP^lVO6H!e4|@*im%HNR(s{>e;vVrP86WANg~j&PHZ8lbmlwcU?oF?Y?Z?f&
zP5+Opc<+10t8W|%y6GGefZwQhkAT_N%dJe>Ku)=gg~Yv!q$3S11}o)8t=l{Cy@duNn0^Ikr#q8Z
z6#XlxDzOvf{Sv4u@(pm{9m_)G18LuvD%S^ZK*#!{O)(AL5lJ>Scmg>C;qSAEHw8i%
zv2&tt6cJxAcI7k?zv6*gQ_d|MzOD|;e{=aUV>gB@oeL7mqxe^!X@E6icM|1|t&!eo
zCl9vgVukC=yW*mBBu|ROkx{3brh{B{y&}fc#hr)smPjz~Fc7KZOJuZl3(<7$GZ68Z
zMJ~8v_OT=oV@?wk{u}O-`6t}B`T+NYv)^z(d}4SYQJKKr58;xa?r@bvt?Ac(oTO+?
zv%4`7eJuR?a_{;}%T|4lFDLj=B^vw?JsNyUkvZF5<%%dxoQ
z-L2UHf2JRR<7{7}3Xx>$?e3OlW_54!=9W%y|Km4PvIkG84aDDQDaX(QoPA7d(SQsC
zZy@i;i#I;LdOMDVinq5c&sA2e@0m-xS#hE=vw`k%;#~w!-vrGa5Pi!iXnB2Nod>?&
z&OOr#)RXcmXK?$PiX=K7G~FRx5_Z6(gZ3qAdcgg;Yt!E#(diKP_D;ZB-Vp`L@ynMo
zoE(`7fB7aOsrntNcXSC~j#{|NZDVV?Pdf(rzMIt_*P{nmzOwLzJ9
zS2ZNB3P0qDAZ;>67UN_6Nj&aRrxbJMJ9;E*9cNDuM&1Vz1?zms05U930u|?e5=5Z@
zScBB}o)xV@Ob2n-=aaa&4(^$Jub@YIvty0#%etP
z@tukFd?zrYx~$L{6b+J?`xSg8<5R^>`>U03DHVs^w7g-VKN+mX9ik_mgjdhPB0Z8ZHR@V=G}26Rgu#%-nE`m
zT7g_z^C$6S1Knn!p7GC?oXUi#A|>p_>j
zW`l-z@q|{J3yn{sueNXX(jM#T4M7Mwr%XEUP}kjyT8zb=zpjp)XzjoP5S8}EalLcq
zc35@8)pd0w9|bnW{TI$LZt&b0g`;G?Wv*IENhRjdiGMqpFOO!j3Xop%6aj8p}
zXxPJXscV%JzS{Ep&XDcs8!mCUs#s3vqT=E`X0>A1)M0@I>@yJxdR&YiaCC?sFwI~;
z3d{d?^~`=a9#U(D*_!)3D9&`H#keiudzhVyx{l2vj^Gi(a}IHDJAQ3sTfMsNXpJcl
zAfA&!IVdT0#1wC8cq-K_yR}ma_pW4Iw(?N~*PZ%{p`_ETcjCTR5=12|5$ue~VH-qc
zh1px|@KI{%+v>gaK8M?ccx3E1qIsWAM4Xf)#P5J#=I-WWRp93)z^YMh^}I>6Fm!E4
z`mskIa;Z*ts0pH?RV_8BIhazawR_s^FZ*w<<8YW-$kQ#tLZyh-xas|BO-2~6Dn3^#
zEO34|f-w##wI3_3feT=HoDO2@J3FX<7nvTaKIYHB(zH8PMx`MsHMpKuB-nyoPcU+p7dk1G(8uLU&~x6Fp??jc)GSv92QTgkAV
zTCXMAsH;i$Lgmi5Y7Wce>a=*Gm%+Pp@S*kL+!^RXOFS{~y0A8Nr@9&B6in<>tImT>Pc}4i
zc+}33>ythmdB1q)*se>jc0S_uNw<}rlxeNP%z?ln2#+=oM!%mhGx}JY_h^|{YxauC
zw!9Cp?}!&URAPuQC}yHRy@qz~tpVwT;JO9BnA59A@Q+(*ppRXNgyWXU!-+k$O_e-4
z#a@n&qvNUl%Rtn3pr!N$$teQBvv*OI2BL#`g|X7kVhW)!mf%c)W>^=qzxdJe(@UWs
zcqEYl>lY%-6G%m{KwfcVU3Wr>FHl!SC*~^O#t_pPu4%kvqmK1|@B|BG63M0lGDpa#
zl=SE9lfJOTYK2=ntXb&lFn(_2s~<0N1KaDW6PoMl5}v?~;Ki#!d4-I=Px(Pvgba53
z^yq4kELW>`0lcpwT^NT1$2OTFk3i?cwc(aGEk9pMCgt;dZLeU)<%T7w-wsI@wUQt%
z>8*DDT-v3C$C}kI!4t{mA#V6N*@#=Qa++NWjqS2XIqbaz9Q5@B?(Ly!Y@;rQkaeYA
z?%REk@g=aA>uxuTqK?^Ci=&{k7T6e%x4@I9Yos`2>1q+aHoFHt`1tyqIvsf9BWhSq
zA6D5ixPIwSSx3y;duf1y~Fs$oS_=sEDaE|Xh&jOQhoG)p=IbMv7
zl$E@OI-Q7@QwMS`&V+MvgfnPbH0AX!>prHIZh4@KTD`4oaJR?aAn~~r7qwNDqBz7C
zai)L7F`KdFFG{O6hPwP&8t>R@R#k|3lL?kXtDKM;A3qLT+~ooHSh;?iNF`r}>-lnh
z!Jz#f9n~GZ1KPQbh`LjZ5i)c8<~%#~`oZvo`|gWrQNN
zOpEmu$-SVS@*uq8s6N4PK*`pk!WG|_zY%9F;z_}G+i23IxyjI_(~QcwKwU@mN~;Rt
zm~xb}2Vb+Br_J=m=hkpSKWqlRDb%O)VCAixo#Q<8S}vdc1k-*CPI%PABRDVdqigOI
zBk?q}mi*1DnVG#7$74?@sshc3GuCd~_RqRcV9jsbx>^U)V$CJ4Qs>U!`7+_=bnTEqnZ8QqvcBz?xNee8U7fv^EF*B~Tut-un!e>n
zQ_mmXc!kiu_3z5ortB{qwUez&6CLPERZSA(rV~Tw1-I=dif5v^7$rP1{j7T5HtElP
z#ZJdA>iK0yM_vK;T99;}BT27%<9Aqo_GoQ`lq~az-aT|P7x7u-qmQPyUm85dWMY<8
zVlYam5gNvgNhWA}i4hvEkd9CqqB58SMG>MWN)KD070jXa(P$Bh(8<9N7N3`acUuxB
zi^k|wr?7*giBt}w&col1tfwm=6-g;^Vm>SW`aUd$si4Mg7*}IENZ_^{jrmmVLLBn2
zt;Sv@kD1!fzZ8?t+seV;hRGP9A~gH`CWu^HMZ&#zF)RpD2|e%@1A65Ldf@{Gw8Rhe
zfm%4b+g!IuXxEj?Ztsz1{+}(wkzIj(Cl@E?v$z;!+%SPfZ
z8Y?$o+8mT>wyXXvJ&o{{)_~MbBeD^bcIND{m|w&VA+ga$=eAW8E0XeIvh`!rYf+jnOuman)a7MFHVLvRjadIaT~!4r1uz(+J4z28z+kdfW68`pI8Tf+
z!m05!l1v&4X3O1)7nQ`Cq5`S^UD}T2W_DN`%=n=uoQdvA0k2xAgiwmwNC0o6wq}-1
zsD!o^+F^uIQ>DkcE6nZ<#91I7SIe3rIt9WOq$7#AcHNGfQ^Ra*F#e{pP_3*y-SJVl
zfA33Rt|ERfVQDV=Cz#tr=#x)u75jG?)0Y)R$Jyd5asbQLYLl58O=1r4a*&^WX%ySz
zPs(*-2sPDE4x>DgvuSlO1n`k8XWVXZ{w
zMrs`ghu~z8`QZwFn6Or+R#F?*{eh55ji7g*sCw2`Y7=(3tjN@Y0H+f6lF6NzBUhPkA8sr
z>D4z;AD(4NCI=*C_ia+}{~`ewiwzh|#>=?1IjIEq^F5*GNb1DOX(OgqTdOA?tdtW=&~0b4V=F}tvTFDXZTJlUWI;#T;D10l`K
zG-B}C`9{p#3a;WQGSe|HPkN+7^i0`959wB{oy?vdpRSr*&)oX`Fm=&~)tDBIR-%)u
z8{VgBhd%dBPWD72%e_H6Jv&ToSvyl9sGUU!v=-ch`7tgU>p-R4ikRhZGc4g!-(j<8
zlp$L3q+(AzdLBeSebMr*;jg6HsO*>u2~5oF*~j-13dU`lvBYF1BI`06Mn0X*B#^b>mJF}45kwom8`cP1FT!u?;#9%PuM*ai3}*0DXBTJK
zc6Slk_c9_U0{n+hZlN`-&G<%Y2Uhxq0b?^8F*lOS2(76#f@g_^s;Lv(BI^2-Y^2tj
zJ)KIYryTy-eFMkUIFxO>6mgkdwV+9mAVJ45*y#H$BJAv*HxK8}=ID-)G{#MH90vghufZ`1F}{y`?Y
zx)RTSY@k8Cnq1F*JPo9Yq0D6F%)O>LCiOON`8yn$ZlsyGQu~$qk5tqmJB?}wGfylO
zpa(In8BPoAG(vbOjm+)D7JBmpxXl&-Z42nlDhr|6^QIV%sk8XJD-iRjZ1;6K2BRqe
zz$ID%oW*{n`uyJ_fPx^0l3t6tl2}W0$<=iU6Qe^U$_2O4?Ynsl9wtyEN^3NW;T$Y
zk|#o#!d_3WJ)V`53LTns7dKNCljYaWeTeQbgvzYbF}qOKN_NCD8$x0;;zl(!)@I{m
zOq%GUm9+A*WE7&~{@@(v7PH(J%1Sh}86(4RN}Ae4_=iNU5bT6CJMNA@Kle+^oE*ej3bYfRz~n{;riTDyjD`4$
zJ$t`<3HLXDilrxV!#Q2|Ay^M%1;?M!7HaSHSY)pFSfJ
zFZ=KH?qb!iuzuIK+x%>XBb-+^s=wiF=o5fBHvtQgLYGjtg3Hn&5RaA7jonRiFV9av
zwS6mF#A}gt3!?b&iBPcz_x$}BJ7FDYoK$NM@lcR9XpEd_$vso=Z+pHB@uO36)PI{5
z+4$ii$#bDb4N!H@5AdV0>o-+o{JTe2LI=!w#h($xUu-G$^BdK--t)sfUCvvU%73=1
z=G@G@A@^+4H;HT?(luO({_p7VA5s+20m0*SoExHa2v^ydje6K6zm*h@
z$2X!}U=wTF=@kTPqrI^8{nw)Cx+VbWDn_=yWbIl<#YUqU8JXSwFQOikD_OVMVUVV_
zQIxe8rT|S9RfpSNG8q348-|}kn45*y(>V5?-1#hwtnE0AymXDMr(X~T*R$%7@6zfx
z0m3j-j)@zIn!?%+<}kAk;xPr3|78IC@E`>aGW*{OQI~E11Jh=DC1-tj5V>XKUh=z<
zmDBJO2<&%h;_O@8FgFeW3mJ`^{$DV|6*>N84(2-SauUZKod_T3_zG86T~}>%II(T)
zaU$FB(r(lxDF)kLBnX2Y|9?n}{|Bkg^os7O-e~0oCtR=68Yik9;Pf}8wH^+6ba6W5_0^
z(_af7bs06KnTE~kGh~003R%~bg7?8)@nPJ7HXX7HrML8->MZ+y)61*!<>i1m_x;8K
zbLNZ80+aEFRsoPs^gcseY`b9PM-Mnv9exp^><5N<@S)n?TVL0Zu`B16%(9Sq>cr6E
z#log#XWw&S6AAf(p4m&y!=@*fe-!wJrgw9#
zKaoJ3D}X?szJJGWgtCA?9Ok8OKYnfEHqFSzdfHV+AcHu$5P=<52t!fHqYmx~;Ue7Z
zanZptB)}TXEP(lEZy@mPaA`s98>Ujqqod7GOoid+BVL{#I`Y!;>CMpnGFZ+vec5`k
z)QM740uCA_+-U&7jOr%R3E-iXs0uv4HGXY-XC_}O^nD(Qys~&Zo*UCB{hne2PDio<
zqb|{oUh91;R;<;RL%;Qbk9n$EdlcDn3vS1nJkP5&*@Mw?Q1dNw4@M90zFelAsl3|$
z5Ph)G+j&<3cL>DamkXpH2iw(!o}t`-ar6&l&PZP=dXr_1?#w-YUGV#L`Mn_K^R*aX
ziljM*DIdCec(I3`r|-DkA-hH1(F2Z249WZ{dcC`MhNlY~8QPp0Ih9h{{^qA?gzfZm
z5+j!(Ff&#`>P|<==y*YX|J6!J{y{*mF4m9blzw1FIv5N)IuBgbPxGPg;B5I+M2T}U
zA7lVBpdkU~Q(+$XLoZAKmH%aC?#`Ap-idAA648s_Mf|~_U2sJRr!3BgLxAwy{^y+y
z=$PWq?OM1mT%t?2y;3)uzHlQcUfuRRC_dNkFDwvjBOn609i~_
zI=5*eZx0WhX=N2@W_1biI@<=QHlx_>QIf7WD_t8z@XCmV{Wt7|kIEe(gAb5B;@B?-
z%zo|A<=EB;ex0Ikgt%ig3^^kVTHj3Uq6&d<>AzUAWy{0dfCmo<@jj)v<>HJOwoyvu
zd*=uyRU`7YW-XdV@385hk#8nGolJrIfPb`l{c)8zkA>8`yoI7R#J~iHahzjVFu1M)
zq+L3Y(LgzM+j<@dvF;0+TmgZ`sspc&hF-?33-P)LZ9
z2244Q0xTwxu6!TU&CyQp5)Sw731_2=fnPdwiF>ITF@1ZxaJZPP%*&)dn7C)j`mx<{
zx_4()*O@&Yb4L=5x!U>M6i*5E
z&x1SIbVqn}ibDZQf>ISSfcm=M-^6sV8TuJdS;8(Q(MQ
zD1i|e@ehmOqz%pe!g?DZl}mRV%zIBnadli|)4hTby_A08(QAoBuC-LV^LM8N*gG6;TXs*?AlmbTT3
zkU4hL)-%_D+iu>R!)}1;aRB(`H26eIXX|F$%02C`wwcxJNY?GUqRrh%hWV=uD9ArN
zLGRp@K@u>?q^F7e~%f9rS5|V=L6o0+FMA<
zYT4jSA6-ltTg4fNQ~^aiKYc%=bcU1MXo6yZ+4p=3XWNevhdj43ubKRS8RXe$C4O?M
z4(tlJcyPI0N=G?SLoH3`nQ&?j5gj5rdE@xlJ@x(Nw4s907aZTRsfypCoU=5D{Een)
zo=#b!P^Zj0IOf_y`{ETQ+J~TUj&8|2m@MZMGG8R;+F<)82;e~`qG#<_M}8R8rEm7)
zUyemzAFq1;2{IgOH%}4n5`~7^j&u*8eS-IpDz`rmz*&EA1x3%}f4(Fy!L3*ZI($qr*r2^o{O&O(bb8b
z33>4&H=gBj7@54RWe+otA6I^-DSp&1y@t*}zi4@7SBP=@F~rrlf
zgjjnIFr2YPAi#-#QV$2JCH+=G$rUFLH1M-y+KLj##2S0Jv6BEnwmVo2G&tpT#bj^@
zDXrYY3EzSf6zLm{20!^e{ZHOD7aq^;FRg`}pf2eA%*my9)1eFbu*~;OgcI>6?z>q*
zsRBczCNEq%vG6YQx6M@#j$_oAO
zD45bY%T&31p={-J9cUY=ph`YvKP44X3O=F48eSTE-J-m#+r6ymX8YReYHOxq2GZ%)
zpyEED__SZwdCHBIN=52D)VHCF0@0z)0`Q?|y+bvr6#G4jEoV0={=a`Zasxui5DdrP
zih-hi#DPUHe`hM8^gKd}w>IB^M=@v6csj^PdjNA})vgSgOPm-okT`y~o36)N
zDI2Bjo&?qCu^%}<^sZM(?$tby6+aM4MDWgB_HzWYiqzpfi6V#Hs(S@heL(S3f3f5t
z@nywP0{Z6FCNb6{ir%|Ri&YG+{)8=XQPFHYGYTU6r9v$r{DciR_$ko7>7xhykc$KC
z1ylR$4a!(yMGp9B0H#*25a{h?L+ILET|E_Vb)tzsg6d~qPInkYy)H0|-BEm$Uh6)3
zK9HptR+*GSAyBC6@6ZqnqY>Z&=RbcCV{RBl%;L~)s?D_Hm^+H#vu6eMvSKSx;wZ@a
zK*4Z61=SBk*eL87F;QADH<)@*VKLELhSb{DIC~tpOC9+*(`eL*uS!r_Xx_sk0y!TF
z=0WFcP3r^^$H?cjiQEn#41=S8_y-2gG-}mN&>K>Vg#wX(+|4w8^wxnPgtK$>=P4>C
z`?p5kZkmRpkYZ;Yt+?$X8OWG5D2sxjIy*yLxC5EEFP;!pMsk$rb@BI3ZaN_ZptR!<#beR*j@OtA2rndaC8c8X;YL7rp$U-=PuB_lx8-hoeJp*L(lS
zv^|Z0nU{B<4YvM=&atw%r{nsv)@1G1g-mG+g@JEQO-@9h1kK#o>y8LLI6~@ak;CO{
zv+wuZbjv8YKP&CG6;}fGpHsj)%3HuIs+Ucl?%8q(u4B2yuHij+$}{UYRfbC8Y1XyF
z-zwH-V`pENj01GS=JPB>>s+QF9Ea;SIhN`)t6d<1!0Va
z)eZ`eLvnoKaz+mmH_QCubnp6#C0LWMJlw1{H$$NV9l4%JzGKO|=Z7@66M8j^2*jEt
z{{nHndHz_A_G=}-J1PFT-dbF+Whv$>+-Op!%e^}!0(l9uwL|=#&|CC)YTT?ztJbKj
z{~5rCU*}8qO(F{c8K4^LL>CKMUeIk-(BT)URE71*-)Lz>v(=Co9C`=@_Hz14j58Jb
zuc34L_85WlLH8C@s45$>?c#WTm<8Ox*=$-AdQwXo5jwBx3KM-*$kYguJ!9$EmKHeZ
zf2vUM3Q#r?9{!Z8EWzPQC>?HP#WubX=lYJ8;n&qUaOja?HMoSof>K&V@?|CkC9Ng
z)AX&UPiTFTWp2kA<#4Ya`iVqeY*1hyOnXi?QL#C}(iYEKte68$|_5`jHe;~$O>t)KYNuEw|O
zu`|JCIYddO%G2XMM7w&V6a7)+AudUhyHBb^`W{WMGPl;v0_mS>6tr!8OthA8!CmiM
z->nurOA4?}%y0HgLdu#8nMpJ`z;Zu+xb_a*6Y~)2SDkS9%A+?rUjRX;eHV%-+l%;g
zPxBWPj7BO@d8<8X;T|eX{G1rEa5gzFhngaiz!EYZX5f~Ei9bMXM;#UGds0gJc?kvo
znNSi=vY=jH1CL1gwP^86BD*djFLt=Y&|CBaiR!c@%~(YLQ7Sw{Q$sBY(%aNvqv?Yu
zaJ^uD)AEmVmmso`-7EaOQcWH`iS&+UyCduv5VsUk?RuXVnzpC#d+hTabWv1vmy*GE
zI>R0|^}!IE+IQ_XmN2PD>QSqJWURO|L8L$yejLk`MZq|`0b|Mn+5U^xD6)9c+y}_U
zL$2#alB7m)4$E{V#GA}XJ5tP~AI>&q2Nv%RY^Bp&L`bus`gr;FWkI_+mu2V*1jwh<
zVPQKuOr}$)esh(WYj~VEWP3Dy6_5f~jrS&W3|1-M?|{sy`-A}-;u5Z+TaJ!fW*vEB
z=yrUr=N}~!gweR`<@v0@>aMzbL`&|mju6aAksUC
zCg4BF(pzj??Kl3b347-zEnqIB91l{JtUDXV9Dt0YR@mmZ=Yll3wK*o3PKXI$|g@C)4@ohv(C#h=038H+No&!q4$AHM{RBzz$
zr=0@I@GU+~13j^i-5m{+094CwqE5*hzr%fI;U4(WA-(8x3-JKStQ?{kad)8(9Z7sU
zvc8n^7QCCYMz_EZa#n=rq&6Z%92q}^HqSCCr)4U|y|d}I1Wt&45}L&K#QIv|>fLDK
zf|>s2hMG9>Kw_gFVwC!!I7Z+))>J(izwMA1waI`cl2LpUVd5MQBTuf3XeOYSf1y>T
zeFy|!%Gpk=Vmk${%Yz2ZD#>8{h-Q;Y=*=?hhw(iuIZ&
zkf1#{(eBzZc_k4a`A%z6nbC)Ol}^5s1>2@+P&aukyO;&edl|R2uFskAa?Aa26rDma^)X*pyRf0N;Zni
zYf622*uNdMOG;ny
z`^jm(W5;D2-H0JEJw05(Zsy^yn=mQAx02g81rNoo^
z%$2Hai)H!2j+>%V*>;8RC(4b-WFVwQAwHnuvi_m`{PtH8Uc?$0Ow1iT
zTjg@4x?Nce)Z{|uI=s|o&9^T9fGSaz5;xSK?p5g%oCG|&b
zA)~=&dHa}{lKT*w5zrSe@nVLt85a&Y06YIqA40QfYMFI{MNbRWR5U
z6##3aFGm$;kmVf=sLtR7@&;}~_m%TqL$H!6F3?B1nH$E*;3?NthphTH6uFM@JDnW~
zmtY+tnP1_u>_i;&i%`JNh@YKq7dM~0@5-ATNa?yqI5coyhEdw%!G^8L0}Y#z2byR<
zD*73n9}FES&qIO
z?0Ywx&ZoP#t^+Z>iv=SD!|IL~dTL#j=17wsF6X_gW=11y>tpLu;
zuC(%fU)^;*i1z98rMTC#pu(DG0fqI>0?OCATD`Nd=W89XM-KzAMEP20u`Ey7TcXQU
zL^0esL+@|NTV$^AuGBe&MbsMQo{+qWa)Tx`qd1AHZkhePt)fbCba6(PgpiCv?|@X=
zlhL>7Vz0PBhw$s-gxcptKRdSVxIIkrmb@2*5}WhN;o0cJfq5^qdKSb$@_NMp^18(U
z=IR&uv_rhfU%h`tnrC%px%ySTCX&aRt6;?QQF%?|3A&M~DWaOFp-w|b3eYY}t)8f}
zO>^-5f4ZG+o2uQHvn#qcU3HqHB^u4rl&#Sz1~!p&P+mnXve+4&aYDIp&JX>R@mXmZ
z!Iyy*(H$Go$@Hn-K}xP5dUsRkP
z$gh@ZXV|NXYksv?wRPQ6PR6gM9`TW?l(|p6WA$Ley5)g}70d(8)3O@p>S52*GCy#$
zi&7u2?ZNo_YcCU)i)`Qk5u=h+GL2`0KEx{7qv|-6fXF7{0SQ!
zcx0+(-l72$POMd2Rw3ah=|G)M;l<@X^yV8j>a<6qA;S&+ffkR;Yr5OL=e>X}-Z2$V
zs3UQ8En`{rMEPTkxG!gg6R$fImlhkiaZDBmX$S#$DGk1rkc*UJJpVlYN-yD94Ns!1
zi#K(2H}ht+y1E=KmN&GIvQFP|oURVn^kJVW`O^Suz#$Z%uQpydLC11pW%@^hcaZX)
zL+Zc&3m0WyA;75KRVigmA|l?&pV=;SM@-4eR17-OVSCLvSSnGBf(9#0*7d
z&6zR>b$Um}-(ull0b}!!fhIo3f|9&ZTw*0F|EyoKMTHyp^2sSE&x4r|x{vGS{7z(g
zx|p$7sB=*J%42|vqZc?W(2`BybUs7#gN54N!@c#>ZfI}(}AgLvpimg}$3AdQimt^P`Mf{1b3ILFJ(Q}RY-{CZgs(@zim$v)T
z`eZyvBuxmxrg#vAHpPRu9MB0&!VksVBoCsn=XsFo8}Xr)$oC+Prg(bgECq8
z3%W?4VkFiwX|UB9wQ?GU9+QQsSA3xecqRT0pR=I`Djoh;<16ga2u^&h3<{%f`4$xc
z@>@!yV0o8PpKw{{B}^6v|MR6Na#Io_5)9=MEGIz>z}w+oDg|GR%PzmM3KU_=PU!wd?|kz*ycoia$>7@XEbd9>AKrpfzoB
z8kiH-l~O01O3)OLHNBgCqF1Hmii)>ZU_nZ##)ru3G}m*$QdR@k0OOHg8)?c_@C!U_7BD6y1m3vCqno)C<~GP>2lIdz{aRo>Kp!je1RtDHiv&3T1Z6)0Kh{~n~LTF^aUT}FP2#Ql_+;3lV6eU
zD-TlU19H(nBai}_SZooA(HMCrbWVg!y+BGtIsu+c=i{$5YaRTE572kkgZKd7`X;N|
z#8=$NnwIxU(3GGhAyZZz?dcZkbwp!Kou;(OPmBMj&>2mTdeJZ2gz4wAZ
zUxiiCUW7<2zZx_90#DWaQanX$IPJRM`C#Y3n{#~Urhetkp9pVU%ykWUkJez
ztLTeffPMtkv6~19VN*Qsg9Fzi^4>;u3Al@h_!S-(dC_!^^yVpCt^AIex^I67V(5ne
zP4g8o(eJ4+5q;g1Bpf&J=^L_$Pgy-;?>?bsGbC+z`4Tw_!CD<5uu2#Uu>#Y<79|Kn
zrsIFRqfHf;lr&DQa1u|^16~M5$RseHMm7KfLef}h*f<4Dn345i5l3#=zQ?*%sDI?8L
zbhk>)P(81YrbwU>P(*b}e1i;EUa5bI)_Z&n4*_MSUKqx+*d&q0sxW1Ahdomd8_R_k)nFe11T!#Jdmo2$tvhzPgTWA<41f^
zQdQBgEE_+>N!9nw@6l!}Kkpz^!t6OeO&8)u2XS?s?L@_MRERgA@RMcJH-Qe8ZSmr-
z%=|Sbt*Er+gbGS8N9wCTLyX_#jR|zgTmzrL6I-Y!1X2FI8Tk9Y{=3++IFB6YA$2?l
zW+E8X$IBXid;3SBfFZ_(N0g46)4C}R5-`&JtWLZRXl9fR|Xx8Yy
z9kniS29=Qf;U4BHbj+MR;Fu|Uz^P_zyXL@YeUNW@w*Ds+qCA#U&6r3UQb8LR%uS1pS_
zQ@52qF8YM?N%1-?-6TOFu&i?82vs^c{2BDi0aa<`aWuZ*1t`-d!*n8WevS(0!x4_2
zMyF>d!Co%KUIjAX-+Yt--{u46_%-b)Uf{Dlui9=)UyR>+pQa(Iy<9xj9LJ`3#w*lR
zJr##C7v|GipQ$NYIFN(lW_q)vi)p{!s)Mx!?zj|r?m)izreEjLb$;=%Y9oZP=#8DM
zaKQ&6ssjXCEl!YO9zw&RTrkHs@5@)-ibuNGN3njrL=8`|q|a#NMLy!F@2fl&$IbNf
z84#=OnYlk)J;)qPKc>_lK^^qrwCEU}%-!LGLO$4>V2rNN^2TY5+4+%9NxGwt
zP7Bimj%c+98&PZzHcPiD0>%{E!=9RY3*By3-dqi?MV4;MsQpSSHWky0M{s4h4EaPg
zEQ(T-@VMH8A|&Wvp%U~7f?wekWiYLLqWo`7D$H6z2N6s3pMZw;^>k`TF_9FjPr>El
zR#f!?@@&)oyNc3P#Aty{MT~|Ng;xKU=Bd#mu8BBy4EmzXBITsc7)33jCL54P@d{_z
zf<)nH{E^;1r-l@&{fGl1)15*O*a-m5-%kN{K#r*26Ymu28Vzw2W)t)sMiYZ~@#sn(
z;eB|r|KZ8u2l=HwBBj2YGC{=zHK5uc5Blys^^q|Dy;4B&0{-`Eb5W%TcPWdu*t1-X#vY5$W?l+7^*?Hx
zaBw6$_d06xNFS(PU#{*xqBQW6xHe7%OA#S4);@aM*qdHn%FoRItvLApBYK&H*o9xf
zd)}k|$$ODdQ4W0fxmN!qz=OA`*{{!;O|0e`~TT(v&w-
zo}cvwXQ!h#xU^jf&uRKpC_UJq!uV)|dgFuUsgH8DFh@?rKK48>QaKS0EkvIB7?$OU
zu&UMpcSZQ{12|4vEoFBSjpODWGy|a~ryKW>rs{8r&^ZBZsLWv~9*}aSkGM3RHO+y*
zIzbfzFXV9x0MJB5(66x7OR6NFYUpNB6ZF7voQk~qYF=O&^3{sh>AodZwk*5o<@-$PLJ*Oc;!=>+M0~#*yLan;7fRUeTRTJx-I6XXqsN4M
z5nq9#IsyEX*)-FoAPOOlH_?A5aZ<)h=hyz%qlj_rs|XK$(d~vhZi~(B^;e*okMY`m
zU-ymC^g!P}6ctCC%Gb%=h9V?OY4DpOccP?MfKop%_GqGdhVR^o>w9TaM|S{;1dEPR
zVF0+JiV`RtesPqbY5<^*&vISj-e@q3Oddy_fHh6}R3MfY{+1PB!3u4gny;J15gkv6
z-aL^Cye=?(q|uE%S~qM5jVS)2DGotT4$_){KCMde{}kU(noYX6yZL&*inVpx!T&j^
z6=E#JXgygKfBPGP&1;^7SauM2!C?n|d~z=Ze*^e4C#NaPsmY^2QV+RLsd%HZC?l>M
z8IGVHqkiYO#mA-yIOCNf&`gAiKxYIgoPScbh~q%l??td@1gZT>iW|Y2;hq{_4&+-2
z@-R@o-G){_+3ASn6J%sGB6GT$kMYq-v{<6Y3Fr_BwKNzt-OqqPBS)EH7_G
zqo_D$fx(jR5r(5nW8$cg{@Uq7HBXQiBjuHcgV*ELM0}d);}m@!vTavdHV(w;(^cy|IVvFbfnV$ELk
z+dFFI5f@hw6uC|Fc>ro30>g$VewV(y+=zNEQr=I|##akN-m!qs!L3EqBwazSN}uvW
zU?>3*uV&?_vw^;vST2sJow>_G@A6{)XslRF=H%W9h4j$Rj0y@3ldVxkbYk7DiDD
z6JLu-(YH=974>08)$Jr_N;CBOo``4FjW2u0DMCtuC_+y!sSC>18607PJ{Db>zQ{n)
zu1;+#N_Fv>6pW%XUc6%<6iQC4c4n6DV_t*q@UbQgIC|g0
zE(_NKjRJR7MjwcWG@n2`sQK{8VJ#u3`Ph@g+7H1<=_5^!YHEjoIIO#lUl(fcrSwYr
z_~K?t)vMY1hRRji4YZ%Nv~oJ(PdIIT#23ONQcxQMbXtT^^$vwR-BDSoU9Xjve1$Ut
z3YW;c@ty&c)#*E-;=1glzr0@F(y&f%ADs+_{XH=zhJ>SrTX?o4`l@-z?LV@grt%Bk
z3q9Ba@&Eo~1y7T5XEQ*q4?J(ZyU37Q|m
zo}mAgy9$5_D+wVqMpXz^fBtDchTb#*QMSmKEQLro=jENM?uzWi~_7z5|?)Rc|m>7
zPx5s5O-5e447x`PX@Xuj6!ihht5Qj%A1V4e(hI#%E>pD^sv`$d2*(rp!<2_=O%rd_
z!PS@?LWNblYK9m3LFH~Qwn6n98n;ISCxiR-m1=X;GCc;giwvi#4Ms|
za4#jaz@(~gag4|l@j2P=@w&9!;YvEzGq^XF^sR&_$I6h2oox}<0cL}i*T7{Ju%6WyZxj7PC+#6iaN
z(|GQj!?Hbt#$oQ`auhmImFGdXpGR1|pcU++iO*gEbQFAuhkW*lm_4u$#EgP{Ak{KR
z!|?UG=Z#7aV7WZpj8iS6+5;HJnra&0xoPzPK8#g>RdsY2HVGW7Ln}7`y+4zvB8!;>
zJ_iZ1zHMUYTum`w=bbGKlPO}H^i8_1m9;mYi?}2-@2M>FyJ%sj6WWpZO40E71
z51fRHeN*|-NJ>9-D8QMUydVK-sa3Y42!g93E`QNAJ37CTJ*xD1K5=Sibq8KgakH07
zY};zIFUnO%y`wW6S3w=cH!;Kw9k_&*vcNQ7
z;#-C^PlO-BLvxb|ByqtDov7pHFZ$HL*Wyrqbo}xw=)tzMea%
zUiy!qkNy~1k6otpo@V*{(VOFD<1r>^Jj0%xTVyhz|CfTF&MAG|1t%t?SR!N;kEVM#
zMR(Tkv1RNeYkbUDWLZ)O!cov7m;_BA-G5!YQ7Z`gBSW?;wbYGegA2?Qu-qf)oIdFb|_yw)AUFM1e(LwqJ#wcUg9e9LZy*v
z<}hs8>nvNP#ReW*rSa_lWA9zN+DMjd(a-B&)E)Oj(}2oBOjHOm06W3z`gg{_?*2OP$)91az=OpYdE@kM+LzyoX5JiVj+C>}~crI~bvd$De49
z1bOVIvslI99`2=EY!Vos(^w1g$e6_I;^#XkZyqOQy$p=+zK*vsHW^dt@~-jvdi`IB
zF4xx!<7ciIk}?8oo-w}__g!QBMPO6mVS$%1iBQIScyo{xBGOkyV*b9*+V0fU)S0^J#~%{`EIj~+xXRHYq#;M&312s_t(h1+3t;H
zlC-?!X1mvfL{?SWIznQqD;cv?OPfMWCv&r#^dA`gOWD8Jx?o32UD)jR5e-yj2i@UE
zb$E@wX4s)<7$Vb2-KnVzF=ja;yntK{8kVY1oz}3#QPi=y=zZRE$jU3pqgIpHf$@rS
zvHBdQcQ8K1)>2KB5%jqP13H_&VmqU;uy5x
zVv$S%IHrT?;rVI)?lwLDGzH7N5y?dp>FvGT(yUMOC0ncIf(;jT!P(3)~f
z@NrU`6J90R=^y>HbEs~M;_pG}4iW}LIY<|f+aO)Dkd`q<`;!O(j)>Q`s!_)v_huor
zJj)+eJ;4ofZI;rKnf`qm_?1Gq5zVsHl|C
z{MK3-sk?mwY=p@+cvoxlR0h}{#^2lMqmA;<{oeZV&OxZwyevG`Z{r+mL%$g5s3=V@
z-2kkf7pjHnuD;{PQ5BL74~`J-_-U*ED;KLl>^#D#*m-nOvGeF2SnNFR*<$AhOM@?K
z0kP|##H(5C)ZV4T1rI8NI;^B65wLU9ry>2mXhO~*eMU@T=>FgDt8!xG4#{SGX((jD
zg~Up{rG!>*5$`a*5Ui2_y#!{e!uCE#7+F$+@he9fZF17vN)wX`U0g~kWN{&>kY&q=
zsuzgvO@|fk*)rmnIA|HEFwGVbQ{sTe0FKM#+mVSJ2sv
zY;%R!fTY(;8x7zX|6fd(TYdp4lhpO5y`r{axZ_}#LPJ@}{hu(PuMHa8p^<8wVNU51
zf{S-I^`*NaD`l#m4&Dt46YHQ9c#e*UhcbD3N5}gu8W?p+2oU!j$_TjXgb{ev33CBv
z?0-K`J^W<301N5h`kZqShB>>ez&tR7($g&tiLgdSZk293hNu3ERh
zYmb$SLH{P8;48?5pq}y@b4nz22k>}D6GkPWn2;c#jc+=;2OFC_{vjfH1fh;bpaun&
zVPH+tVFe6|)BR|`;x2jh-1`|A_W~JtG&ju5@hd}Bw%?6V@
zWgUm%{h?GU+LI%Q)HbQngF`RAb#w}A%e{n)0i>DCOXXM@$oc9iu)VGHcQ$vo`s>@r
zh}q$yn62YR7(~b;c!*F(fDxh2K!^s$X22ioMbxcfP
zJsmHf*ti(sx`4v?`5GL!1Zfd)=qvFIM$qWSoM=PQz!q!u&0iH?amx0S^1?$~)ks@?8BG%bRET>9o;zDZ
z>AX`Be!&&0o&;cfJt!P?|p32FhIINeTt9W!8}>Z9w5f?kkZR_X-jvq_SGUVHIIzCj}g7
zqrwnSenWvlJs%EDaGbt8WRz2#ipU8#ZYF>i3x^al(zzK>%vU3Vo?pkGY0_7wQSE7K
z?)X+fzlKY}a>y5QKWa!0s;@652pAv7d7iNI+7Tt~K|uiL21($jQBmNBQCV>K<^f7m
zH_JjfuZ5V0^zUllKF?x2wf?0zH0oarQ?5xXI!n^(_N?_^2rPT(Hw!43G7qI&KaUX^
z@q0{(p~>eC->vL?909?a`f>yX`qP|k*L(FE1wsE&b5}F-zL)lENF%yWl*YxUO4o?1
zRy12-P?Cy{P^({tbJgma@NKyzavQYUez#;2PzCbfXw$s4{R@)ED&-0m2dgn^;ni4iv1;72bx=t2)VRvCC1Fhy
zan6n{hFmyxf4fO(Mx2`l7HfYE7`y4tU+@vCz(SY^yb42oyl0ITzNB)JOjSn9g6M&GNu<^b`%XEAIyKwh8K383V
zKYT=aCJuU}AJ7-X4xmpF7r<4Y7Xi*X@<2CFVsiN1TxzB*HX>C9{2WCZUy+M#
z&&!c=h>XLA37FeweUh1;pF})N$I2V~*m`oT@9>O5&IC#MXllHN4iLD>=EFxsjC;L<
z-p>BVATFD~5x{Em7XtWg{zB@;AJaX}+*3Dx?^L6isXSwe*XU1X$}8#sLU)2tm__Si
z1hQZ-?)8q$xhA5;z^MK^4M_=x8C7IEmlEB!c_}K)dfT6irJlKpknFeBJ$o=2ROfZn
z9RtX$G^wT#c1)NIlaNMU(!B>+#1IoETrl-`gbowusD4KK61lF;h|yp^XCWDKauHTM
zWqlH7ykT1pm}uj{-TW3kvoQYHB*an*-LT%wUWCG^9wUQtotwQn4*r~NzJfPaj$yl&
z>BcJN{go-Zcvr0B8?%GY5Esv!u@j~;(zP-HL*AaHx<~8#I&g6@^bBtX#>)hOX~MS5
zlWAxSZ(TICgfnBpit!ONMb
zO%#eGs~fsScT)1>P6oeNS7?B4?DC8NS%bhk%o?QJp-L5PM}UmT`1uUcnL6KX|Iu?b
z158sz+ZoGD*|aww%e7<_!}abPBh7d#rIb5=|F0_LoFc`vBITT{7U!L?Faza0tulQM
z?kmpvMFqsU2n#dDe?W0wP~b4@6oJ!ZEdr;hS_G~-qyx^@9}Rk&1glU%G}!z0WRD1jRg4Wx69K5ivzfwHuX$NL=$0qTr!x0P4E?98a21
zM>#;F#ODB<+9Gd;1L>`boP2)w0`)nQFEmm0hVWcn%5Am>*)*Zni%XON-HHLrJ>bJK
zYf|;zOZgj7&TwHAs%2M~*MEEtodT0~y^AzWyujz&R@XbrAJ&zfy9`~=3-Hv*vOPFf
z*VFT%2J`1)Glw^@!rXx=sr7seeG`?=EahJq+d|tZT=px`R*YXOCgQWn_Rh!0LrG&7
zeB3}`x#(-7*~Q4xk{Q-
zc0ptuj7??1SsCDWX_hs7v&pkK_7Pgr<0OY2mLYq*bc
zY5f&`dM!UeL$1H&PaoFdQ$S5Be`s($!xffBmCENI`T0kDu7n;s7?GkTU5fErv}s&x
z)(S9dI?4n97*hzVD2!iKQnETPm8z1jL;Z?Vhc&^u7~LM#MZ{C#fyrP*)5ld%;josO
zqM5ebq+@0od{Uac%8}y0vLOs#nkK4E+k&HBjrSH%u6%x#Oa4&m^_ZqB{y$yavb2+U
z;0eFJEEWZ4awfBi@$rfLyr!~|5rSd|hIin4(BxtLzE^f?XWbSjF+8nOP#T*z7X-3U=>%OR9h7uN=B6`
zRqL$xf}ww#QUzN_$Lk+IB3pjrC`m4>IB0Em?YuKe&}UF4*A9gdCs^l#)aUxh%9q*cAlft?-cv?}2h
zi#NET+Q9d85N-u^1)>j3VmEUKpmuz2eE)TR6IA$l47)F0k)^hPBHYTkq48SvwW*F8
z>IFE*5`6#4>$WBgbt`V1(8`rKBP+e|lMB2&b#IotPSOfRkuVIQ)SR|c6}nW%Ej4|y
zYSo(Z`K6E$uMWfPlE2J-7Zx-Q^LEh(lj}+QsVWTW08knTNsy6L=rX0FYLF)Ucu5VSI{>Nb~S3BLwpyX6hd_
z_SW}*QU{IO+i2ae|5N{@*Z;VVE+&Dzg(z`AWk+cP3Oh=hp{{Ms+w0fc)o5judxp9$
z{2IzA(+qWOr))}_{(6NCeS=GNfSdA$=1(0K_)1^%9YFXN*1V;z
zgdSJSQq(TS52*2yS*qfdZBwjHmHJX7s$Gnqs(1w@>AEaUbz=Oo`ui_Xofw}jHd$`2
zy3gdR&faE*>eR$Zs#DV@sm|&o+K*vKp$*3b)mfQ!8uP+CuC1$1_wf>Wnkjd-RZ>Qd
z>ijS``<>@CV;slyjKbq;&ls+uzJrl6mNW}x*wT=~cb4aqW&Rh2*
z-M~&2FAk<~mFZNf+D8tn!+{)A+B#tT<t*=adts+T?Ve%DFe`N9l|=N?{Zb=J294Y4Y!n|RiJ=@{W~VL*J_}s!j&^Qz%=D~<{jZ=ZNk$_9+OHJGxbUa>NTKW_hdT1
zLp_H~uljC3p&uJeXEigrd&&vo0qeQCXaa7eIhA~_yE4|O`MNPa@_h8$HLjL^Ur3%~
zk@Y4g4i`%IL#gbKQo<-%hh?GzmtzCcr5iL#h7x=yBp4~L)V^hk8`mEzkDqLKh_D*`
ziT=Mfi)1uMhhIcl(Z<@C_BZmOf;DE;L4<5L!0q-72G97}xz792xG?UO_qDGWAG`4Z
zy7+AM@SnZ){f({SV1M_YF>9Z>^%NppFxzP8yL1g3l}pyJN4aEKmc8r=ZF`i~zYGyOQI0-+H>d)rVYrhNDZv*c0h^7wICz6C2yk0u
zrQg}RLOOeEXLf$l!=8HppZ+Djqg>s<
z5UuKedcmCxClmT|&nXT>mO0#eJ>_c*fOhKQOXH8~D!%LC_;P-wB~gwnOx%X!*MbCM
ztKvvx*W_1;7G$StyFY5Jru)QvI65wt)KF@7z$BpR{lgw)Z)nBJppLv3jDI2}et64h
zr;1MbTn0T;h%L69^ASFqLzCKVLRD~>{zP($3ayG%KHkg;uX?KXKb2x2AqZ1yXreQG
zpQ3;mNTLN-D62pe2&?%TcYd}h&y3(S8tQe6M0~zTz_srcd#AmQ4NeQiOqgo
z14FE+A)L55GcX!Q^nwj?u@2YHUak}EM8|wo-VlyB!wOr*gyIZ7O+fYdBmuSKljN%$
z3Nh5qcDK|0(D9-QKKFc;L+<`H);`yKoulT=woLpd`33Xs^%Iu5!h{rCNMdSlx!gBw
z(?l&ZTf%Sh13H)Rzbc_=hW!T=R+e_g#ao!b_*iwFgAsw|T<~sjVTJm(Ii?(-r~RK0
zPM$A9%3=K>lZxm>G8OK*V8BeKr5fUe02>a&1>#~$Wb|@HZIvnj=ClvR_$uCG`eX*3JuYL_7qxrC`>JJ#)hs9Lp#29PtAM!Cvxp#f&5^D@cQ
zhz=1mG^!^ZMDCI^q^sDY!8xPdU1PZg&pZ2VDp*hgvIIPXDgn>skU7dN70-62In4bQ
zFFu~lgJtow(K&so!u;1m56SKg0P5bWuUK1PO|onyivg)_N+BYD0ZD;kMVF_X#ur9-
zhzR}lkWIOefiz6kR+u86M);-8!j-aX5e{@&=Q%+i)YgTEjGg*S0>SQdAYkvbx=v?H+R
zJDM1|ZqjFNE;o*8j~&JdG~Mwbd@yFj@nRr?9cc$bg^#HT`8m>m@EM@QE^)ACXpNS|
z2|WH~7?0_pKuPG^lj-xK$7{f3XgI~aL;A){iNtMNJPlvg%~9SJxR?qyFYE&;svXU7
z{jYLvG5*nt^%GZ?k1!ea$?_2|?NW#8oH4k;zA>MH%zt9_z?^~*;hB93dE_-iAS^IG
zPwnk%d&{@-HsI|>w;;RAE#yvP{7c;=MAr#>-T?1Ci0yI>Bc{637#|@EcaQTUd=~S)
z%{KSCi|C)wH0c9P(xefpBV~$ht465IF_XD}Xz#zA#Z-b!xx5~8-rMl@HWS)2{)L>!
zII1ASD63jVNOs3)?#=-~#P7;T1Ilq9x6L+0VW{#!(F779Xo844M(!G>Y#Mfc*~}y6
zkACRI0AkNmJ8x8*m?LFHAb5JrQ#jc#RNPme7jWZHe~_ah=v@_gWYW&`VsK{SlqR~O
z&61N{Wr$FT;|@=xyI)Q2aG@$Xkm6z{1TuNx0*HtW19i-_cGyv@cTiys24wVs2GW=0
z8qm8L|0oH$!cw|NF+ybC_Q^+6Pgow4`Q&VJJ=1cpQa8i4;tImA
zJI7o7-Sy+G{f&P%$-hq;R|Gy~TqF3DnNB`5@G5Q?f8E&(8hk!?HREK}5Q)k9Tr+h;
z=c|fLX){u*1XyIHN)Qv$(FpQ;mO|)3AtVSnAXyi4baZ9>J}%~BJx0acISgqPa*RJ2
zUyRyKsSGi<_HTlaQzbmKn19R=a*Y4I#Jsn)zL_TF70M4#inP#gZd(CTEev+Qeq-@gSm&sUSpXz}s@z2uJcGP6W
zl42#p+4bGIm>ptl@n8!%OGv9257g-pcWf5IAj%}iKuER5PfT1^pqR(b)w$)A5uu~<
zm7_nUS~tWqIkZu)zatgoxYyq;4j^Sy1j-bF30vVao(}W7&+VOOa_$oL*edoKW5?RZ
z2lVv$Ikk~$Nrjr>8}}rqouk!c&|P6g#!E(>Tow$WG#kc$2;Ih)qm+s3p)lbGZ}fd}
zI6ykhH|x%^q(-L!ar{SCdwLz;BOnhCd5ru;HAiT#DOLZu$;5-kKrxxrXxRvi%5BhE
z3mZv#>JM{?0Fv;qi2tfxiO(;?E;2+`b`j2+sXxs@33e=6)fiv?7!OfCl3m@T_mJ)r
zNj9{qQIRz1Jw?%^_bS6YxZZPTn9Dp8X`)-nH*+t&N6jaCPn<~zfpa+$u5YX))G0xM
zwi5NVwAVXfK!2~-Lwk@z6n09g3sa_HjF`J6HL!564ef&&t~N(nuQp6gBZYz$JnC=Q
z_0^6aYHV%8MrfifRI80tU0g4s?2vbI?T8!$ViL5I%Hq2@9|PmVvg41q21=wNHaB4iGDx+%d5C~djVYf$iLDtU61-nU
z#1*q>G7=0)Tv!Z6Tv!Z6u4m@#xUV|MAKeHBVGQ>Ljf54yKw9Na8LkUUi@v&8C&umd
zHem#WZqIC#8gv_z6EY`!3JF2%gvZMgxdk@B8zKffn-T?E17^jF_60>sffiOHu%4e#
zL!S-f(|~gIB|JkR6GK50Iko>LZq1=0(@AYfIDT0A~2Q05qn
zE%DVJWB^VxwLH8gI%_nQ)C@pHnQ%1C=_(TNHaUY(31dcW7}zU7VZ-v(nr?0Y_!Oav
zB?%7j{GfIsfbm0Lmt-h?qQcKBG1bTci@nRXDbgzQWh4i)qa<*A{EDnTstUZt+969g
z`sy^N4cGv*SP?kc2opbv!^exB(s@
zUf{FDlV&{`;4Ui%&xGuhr3WKw^2OR(;O<&sUDHW!bc6BHNf}LNwVUitK%X^YUWoIo
z&@wd^X``d#h3&#y$eNsQH-g)c#KCPS;@~zEi(6aVLDu|xTlFSqxG!pLh4Zlt*M-ro
z@}?>=nfV5;Q3k#%dDU)Y#B3YPX(G&#h6EjrUj*x_2-Tw8xbh~TL+(M|K$jT#E!?xE
z2K!+tGwRu(r8#5F#E~0}pI|4cD6=}ajp$;o314A@E;c01a3zywxH`k+s!QnNHn@`e
zf^dx_`kCim7_LyoWuhN#4W!cbV37Li*nr4rWL;P+g)u)2exUwTKcD^(jyzeog1e{c
z6>q==HN>ifrh&T{@@Yq@bu(U`OoJ6aJ7674)lRGrf-&kVMOY=3&|
z9JT2DqaJ%Gd!P%uDCDIr%bPQk-usUxE`BaF9L5_XnVbpn^utQ@;%j
zlx{UNCR@u2AGYE8unpFBjBMZ~=-{52UpDiIJ**#kK~$?$KWO2uj%Mmkt~Nw>sya#>
z4X-bX-Vhbav#VlD3I~wXhRfgS8{Q0XCV>Bg$%$+$NmE1NqwJ}$9ue_lH?`RvV>d^=
zU(p&^-@yX27rv09!@=e$V5I|tW>ix5aN=@@y8*^l!`4vJv7e<3Z1
z%&Uy%p==_m{UmG$eSehN3`~i7RrM1TRpmeLZErXt00?g#^~@iXdUyVSoj}T1cvN+`
z2{YxWrx5_ZKtR8bJ%QgD?=l_3S$U_t+ZPNfP5nJXE#Fc+~c-
zfkbUv18Lf%z!@wLQ%O=#&N7dA#Pl!U&!Rhngba05#Rx&!GfLr=W%1)A>j@e?Q5;yB*FoD{4dZi432sne;8rwfxaunX6`n@pZgXBt|Tp`-O0{ku;p0O-H9RA=zq$fp@+vl|JayYElT@
zeIdg&)+k7jk#-4bmk%>cCV;7NUr8jV$#hz9k3gAB@UYFinT4dIti6f(5Xy4e91d@b
zLjR5!h+c~ufpiLM#f1C_hbq2XI7IR7!XaA3m4G;`;Q!$?H;7z^`y#GH#FKEi
zE+P_`bE7Arz1x~VEbdlgIU{~G@Bq)6*B~&X(TptQRqHCisNlD~g2tojETk8*a$I
z=4ESyZm{b@aWtRY-Y44Raq+!xU_*vs?8%c5F)?iN1U&L-QDc@aKWIJycf!{D)5G9j
zFuwg8!&I6oOTMaYWAda6wCF31clH9Kg9svB(pTdR9_dc9XXG
zX!{J~Gw`hI$S#BHNI`8tk;7jaG7B#6*j@^d-|pb|Eum
zm}x4BJ96yd%E#i?S=2aF8xP>&8fOW%S&G1{Bp+g6{0EO!<=AN$KjO^fiAv*6V(`+m
zlaw^=qGAWjQ_R>&_^(Y=%q;VmM|KkLu`+oYQ86u*=f57Im*&y&J7t(v&O;Eh|Ly0E
z-RJz@BZ=QI2YN}ACI5Vao*C>^#K_La;b1B;G3H645F$yj11bk>_~S=bd5-9|=yi_V
z+&EHQqgTU6l|GHDIO3MxU*>X3*s2(x2cDAUd8UlUiE>2v+%M&^wbh8i1$C$8)_BJL
z;&ZKHq~|kEi%_LDEgQkl`(J1Mud6E&$K)+`1O49nzpk#B*iy)I_etYBgHIU;y-%6B
zO91q%oz=BiCY{ecbC-zt@IKefZKCtF+RztofBnNjF9v(F=u#Y@I+id*Gr%dy+3yHy
zN~=8dm~oHM*H2N>lLCC8ZvA-YuLC~De>e=wTTBFTN!yCzlC%}ZC21ax(_mb3&%<%V
z-PSNJx#r=R`;7v!%3AvM2uO^mZj0eCep8T&D)Kl^0VAi2`lG1m&nz*M?dAg7l}7jT
zvQz@&vzS4ug<=sP{krjz5+Q0RTLEeaTj6O4^S~)l_yjF$xaWbhb{U&Ke)nEi9yZOv
zLD_@%*P}LQ^5WvhfhW-M=oUm1Jc-U!c&3>Eq-upFiCQ7)jF)9SrfJM_o>|Nz)~<%6
zeXcy7*4ov5{OQoG?hRiC5k95)
zvColtGo^0w6_sXMZ1?NAD3Vmq3#(9bc|IubKr
zT#Jr{I&HN1y4B?0XlqvAjarg&ilZ_w9pl4QbB^DG_l;y0u@l)Q<5zoFF(FWe7e~$5
zH$+X4H#AL1H#9i_x7wu@>4tj_z%BQParh&Hge>Y%D%_GM{vdOHL#XSNcBb41iz9G>
zM|)|6I;Xa`PWwo2#w3syvmKF=&WV+%Y`inlc=Q$3iv%-sfNrJ%LlNN$(^x_Ec{Zq&
zqn?)CUzI`%Xy%rVBt-Uh!kymKi@2-|K_#IkpIw8w4W5keopj#y^kj>{)xB9FU+
zIaU?p*cktox4I%JwTxtkQQ7TEv&lZ+hFquY_uhvZ
zy5S}{LGI}Yjs%;7T+<=!2b=c}f9>yn3gdR;sEGaBvJ9nFuvXc#MDU~
z-Puqw_u@!vwA}40Y;-6cssx;A*DIL#;BZ<1We7#3!R%@vLr0`5^_2?mSa?mNa2&P{8OsS4p4rllCM{Y4dzz
zZxh=j?^=@nq-+JJ0f~ZLrX=WnbTq!bn-?hHLB1%j5i#{HP*zU+!!7gx*L66;w|U0}
z7Dq!Ys
zwt?nqIz-k48sTQ!djy>Td25=k4K|vr4L8+MlZ0FmCE=zr*9_*7I9Jzw0r|Mm+R0=f
zsy2+9>s6zFk9}l&!^;uwKxB>W+<2<$j(KIMAwYAuxi0m83xWu+Q7y>KEFJ_z(pYkH
zy;b!Xx)u-_vK9~-vV8560wTjbU;8v@G{baZ5Sc9wCy=aR9?c{*?QU=5cz30^9FBF%
zYQ_SXqV{s{aAWDWpK*us_2^V}vwmiP#g+paZkr!ILXW-p*B^Z$?Bl8{v>?_OFG~Yd
zeK#jJ&Jl0D!es_kwxachxRXHwwCjf-h|;@j_@_8O#sBT-UgGF|tfxs1%`-$3#equm
zAnEaL_r<)AIdXi=uP^P%v9I^P@}lLujBT7ut-h2aU%#xbB@=pbB66<8cV3r=5V
zR|7VoHx2lBXAe@F_lAS<4Eh&sBdu$hz@vxWzJmcRfg#%^C
zNP^5p9Q2oUFpNQ-a;
zxaWw-%8$XFCBQXDL^@w(Gfdi948(}vy}{Sf&E1XeZg4dCllTXMcxj5-$oqFUr{Dm{
zl|60t4-QTA0^M1p7J5L_d$(|%2;c?x+Fnn_m(R>La5NuG=hm~}Wc=|{9V2L2M><%htpWsnD8+}<#hzPVh3{Thnf=MF#a9<8uKEnhicfB@WQZ#rEI#U9K#*33HWut}NGD
zt!ZJda?O=x&iT!D*=kKJA6Jyuln-jkh(&y94lOFaD9rPmb#d@TdI2VUwmX=gT|JQe
z25R>3+K|*2Z1Y4g2TumGM8c%}RrjzIfx!5+^gnl%k3OLkEJ-Fx$`+w030tJ1B+M0y
zmMu>3TXN48i*N+NW11@!m@@z24k4AI`rFSv-0m~a+Nk6kHL%NHv%n2dz#s}|@dx28
zLqrfBIr(nFH^)ab;&!TT45Qo!5MJ5TQo>eDzfgAbRtuzSlrc!x2xE}05iSU6m_Y%5
zpvFBH(*BiLq5^7M^D$ky5^McWgl8|&BAKyJ1TGm(mCNLeb33@3Pi}DQ2BNUMBTjn-
z)Sfj^mm1vD?H1?~=eNe;OJIt37Mo4Q$BX#+aAsJvEVsuhCHMjzYx|rQ0j3v3($k#Ny5C=-HkvGa!9L#3J
zDeu}O9?pl$&hHlp^9&35>I5BSC)WjS-@&zxVevzxev}^oX9z&?Fn?Gae){J!>lc;8
zT@20;iW**A<1RV**cqids$7s|hn3Dzk~IL9mF~5Sb1`^ydxdj~Wt_2Gj@i2v2AgCO
zsOZ(Lz1IsedxuOuT(cv&=5UXilcV+#ssk%LjDGE8Um@n
z@5QJ;JwG4J2e{MwW%--)V_zk~06FFe4hWP?(odVxIuEY8${3jOxCCNSvd33(=Et)T
zJ`6zCdBHJocZC^KynY8qWCm#_Ysm`Ljx8JdcgV;B&ZhuDw?aTpE{mdv@h^tB2WUbO
zFJ|hNfit~T-pD-`lp{Pwi*_mP2TZW-!uPqvI>Dac`>7S*n!m@jZ-AQ!Tk>>BJ5Ml*{YC0ZRo
zsC|!rD8&Fmp*Iemdso2&G>tA`bjb!pW4j6;)v8tgHoKjSacPzw4x&($T6S(FLG^>d
zj0W@P*v)XE;5m&RJ#!#d46O1-LyV8V#BVR;lPLLHLMV=x6^eM^uP_wP?yl9u5y^9>
zU<@+M6|b)GQbUYyuNt3UVQ;#;lGiDlhOzlnwxwr|Rkg9k*w%i+j!@FJ2oXx~l#GIH
ziv+o(8R7$&r$~^?JwtrJy_V<3?_?tY+tll?${a5I?w
zPPKjC?cgI2q_%_Gt8e`;IBFC7#8vW<-JoTk`KWgp#g-2f-eoX;U>CXfHsk4uv#6H9
z_`@c1>7&}2#H6XAtxz9;&IQAldj+P*%1cNt)T|0=hM-j*m*?tQ_Ys_>~18AI@{7MF}+QaD4X7J;jp_b}IdjkW@G{
zRuilM2bjaLqzx{WXoPu$&U~#qT;+m?~-Jk=>p2
zqe7e$%%h9aIKue8dDLVPsWr#ZO}jxgvKi
zTry8BB|JZ9RP;32F>&QiBENK~I=WazPKh`}E`)@bD(apAAWMc#!03A;VZf47_R$=kSI-G+j2#z7GN(D{Mha%t*+xf-2aL0RKqPV%*e_S^7>
zblxt$D>->Iv>@^fbun~BMUP+QInjM`aE^i({BCqcbtV$33QgyQE^Fuw#+So)Mdx|3
z`n*`f1!B*O*U#lF?`;tKT@xVM!{x4x(Dx~$$oC1O!1oFBHV30?*~h4Q$e=X2&ppGs
z5g_}iAz`k0y94JePJrR_
z{j9X|++_=;2jk<5$x1ElAjF}jD0Vo*Q$P?jAC>XMUshgpD@-wdX~iR)v!rf=MEr)-
z?yH(uwGQL#7m2`PtHAkz&N;f_h{&~af~jPoR`9tTO_U;!onc&Tqc#!a+v-GJ4ht$A
z4k#lErv+}RM!l1=oQ|mI6-Hx}UwnW4s<7GhXXn%RUA!)AJY5qk6XxP$VElLLj*VHP
zhOjP1^BIE?jS6|Io~Tf_s)`DAhPFsk6&3Co+9DiR3cimFZNWJ^{R3K6g~=b3!XMfh
zmFO-1z>VS@R|ECWu7B^FD^RrpF=7wc-i_xYoQdNL${h#P0TuizM|k?+O=qP7T;37i
zDeuc3Oux~=g+Su};H%5kl^S_F&Pih8ksimFL%s6{I?`*zJ0G*ZvHKH?i`GBvMyka{
z;>;S?zS4^O+BaIUU;9QP{?o8up(H^O{DCA2>d9KnAfqS^sJ4
zGX(Q6TqRe9dX>IaLaXGhVp=6nm(?^et#VJahagpc4r|jJNtadbVM~LYznk(uzO-)fV)&Qr%4q5_bsvLsV2iS+#t5JbFhLI~?nQxg
z=q7x%XnnkKCM~2QOVg&HN|UA_syYLsC0qWRjHt?-TbSC90}f_YCf&!g-)j4Ti0Vi=
zTejk_+^TbLtq)BNL>V3b{k1-zj`9CGt=~o0hQIwSTkF@I*eWQrqCSeI)5XYB1gd17
zB2y)Gx{{^|oM23qS{e_UuB2f!)Q%Qn?;~AFYqOntdQmN15v^1e-3A5dhg29S(i8|N
z%9Q1=4Bw`f%;(9=@6OnKx%I#GxJ7mKori1XWeG&1icZbesHKl4p4PprXt8{uQIyU6
zm*`X2K!5vN#peBvRy6c!ho-#i0VG(_Z9=4#SgLhWlBWn$Nu454CG{ifQ#@#fKCPeB
zRt2h@a<)39;k&3hb>!*+m1!ylphfIk^mDVSuSZd)ti7VlSa+(Y9A#=}Z1q~(4_+}-
z&Eat#u8mdsxmKo7r`gK19>RkABi%t33{F6q(6@IL%6C<(RAy*d4ny^?2~J>qh9^X^
zK5B3R1&M1q77_IoRcN)e`=p7!mWQB_1;5asl!NpQq8X%57Ep`xh!h36CoATNS`IQz
zR?KF~i>u|hgr;g~6Y~NzQ=(p3z=FO?2bCdC0hFOl0h6Ik1`<`LS(#V>+OE6do(v@6
z9(I{(Op}3BnX=OJCX~rDHFNRW;0A}vb2)ZneUix*)a^Fe5l!WMW8*<7Cvv`7U;4)#
z+F;I#C6&NO#s779b|NDCc6!lNq(JvNyN49$EG{0mOaU!qRq3`G!vSDgMejct
z3}e$xN}&42@ayde-;$G{v-$KIU%=VpA9PZsy`U6jPX`w$-s9g+^%dM@A_%ohh|
zzkekajtYk;%D^d+DRG!wgI#$xTS-ZQEs#d8`zsAGr
zXTx|XRiCI7U=d_ymT}pCgryEqO&{%=M&Z$dEyI38fOyMGWzDG{rv~zQFj*
z%$I)VDE4)d%=Gau@utgu&0CfE9x42Si^JJymN{q|_w
z|BCUYk+0umB3H$%|9TGS=4xt82v0X)Q1rw=0eo>EQ0)%CPC9Unq~v)FgVk?#LMNs!Abk=l-vD7Xp1&$x@$
zLo9ncM;nr;E@e!(YU%J`7a7UN(QXFuFNA>-rw@Z8PTvR!S~BLJ-G97h%#gh}_eMY%
z&irpZZXIXZ2nd&{o${Ij$A=v%rfa!8L8sGh_BL1<0i9`&3;8EYhO*8*VdrK#1
z41#=g64Fnmo^7Uc?;nEtK_;y^Sv2>_U>4BZ_V!Tvi3F(X{uem3mY0Ho`HOp}3QnA$0?2!Jp{q(jp#zaITd)y10>
zb7Y4|)tgErc~P9u)+nnvVRTUG@XLMs6`geAcESf3=F`#TB{nwHG)r$8HQbE*HxSsM
zYj*Z`U=knf9qw)&Z^@DK);3xf6@K)<3Rdk44G@8p!_4*uXn;zPJ{dChy+>9x$UPY{
z^^GY0N|GT{PFbMxznu=Ks&>-&came|wVf~~r<1R2+76Y;4^#}H8nOCr2B^R*!(Jzi
zk7$gFu*)KSQ__7*=_{Etw2B)Cd#{R9G|yS@
zuIN4etBvG~v&`ySUA_?-a8h*0%ye_!>#hFB>;LqXk9JLDnm7ARxJN3C|Ax`nG`vN}GEW{b6cFM{ZI6-A8!YXahE6D=bt9+OP
zJ|GVfkPPslH>Mbr_Xgja2>4ErP6dym8GI#C9DF5B9DF6sV}P&Zz7Y6)i&KHGWO_gF
zDL-O!uUX;Y^8nn`U(<1RJ-KABS6x40(FX8El$|{xpi64iByn1*L8!BPA`#;wl41@c
zFw|&_cp^_QRG|k#lzYAI>VLfYPkr8iS24N0oy;h(Hm;-V0r8nqyJ4NWxz_?|MG%Lx
z`aBNh$^b^yr2p3{r7-H;*`+hJl>QE`pzJ)7rOf!DoU-^irjsML)=xXztja}99no@Z
zn$np9=;3ual@9G6SFn$g9g;)NtXCz=!4g)C3
zKok~JlYtJXxM}NLdg5_X;y)p9Be%VA9RATFO%BAQm4+0riIFhDePgKksZE+PsR=rM
zXl5Pe!ruB}r>}qLBj)#E=NRow13q|^IDo?_Z2*%|+AK9&-O-~wvy`ic#3<7&8vZm~_kA21A{7l||bbOd&Fj%LLLiZV_|pq)h8hL?#zGwU?w
ze$1!&@e+Az&x{ak+nyT$7~G%h09^TR1;EC=*jFZ<3;=dQt{5scPi=B`-lV&h=9|KU}WYOm48ZHpRdT(Q?kvn-1;eib%MYuvLei^8vH*Me2!
znk849vs=;ru!6Pr@PZ|>`oMw(VHL{=z)q5@xWRruzY*hq2e}I0HxowFTEm9r0dK8g
zzp9Zwrd*jhCvI1@PUo>Vku6uc23;(shn1_4@Ack?_g!(!_qO&n`X4^`j*k1gTl*i6KfUjw
zXQ*<&-Q-38?o2cpMOKDf)1zCQo==ef$woxDUl(bG9A9sX2s}k%Jf4WGW^8_|=|Z}i
zE~It_iE`9pRMws^Z}am`vcoc}pDuC2_Poh>H4iJJhygvcQ7K~oz%mNCPm<9Vuk0_A
z(YMUAOBB>J(Q6E9c`#l{7rm8q(X%s1L~@?!nK>sikN9)77qP(hC>geous#0x@S@l4
z7E4{Zo1=1rrTCqwg1MKkhwUNYFLhTjqTDGJ9I+nCi@Je7wzz@Zo*wj|Bh?L*9r+zg
zDBvXje_NYd8_bVbdAa&h`r=gDraebWSj}}
zeWYhsgXtx9erCF1_pBbotl>(j^9&{#^H4%Re?53^m%gw_GEQ
zd&@P_2es;J-17{Eh__thnyt1T&s)ZACJ${fh$ehsi@~Tus*Q>i7-g8Dn%=gkrlx}g
zjE~@2<{50JYC3FCOc-BXzxIf#$((tI6cfhx;+S1T*wHV$vMBdcO-5mc6cffzQ%!F(
zRMXoAgUXZLw+#kWjr1{9lbLg>K@~Y8tj#%FH9cOy;myOVCed~eteT+ig3gTE`|APn
zH}_CKY}*-AK2%NiHWfDoBvt){4?jJGyvdNOH|cWqCS9)V3=*N=;;7V~FK^2a#|Uan
z7Z58EtVeKEYF&Je5D>0KK3g
z7unE~34rm-?9%URL&u!^wW@R9wHZdC)TKIc+`X^U#{K&`ZI%_?vf0;WT4}+gmR2PgGZH@U<7W9yHr9ygK~wy+xX$Xd>nw~93!DA$
zA0qcUUuR+bzb+&RzaQf>4jA(M{rsgz(ODRuhngYJKUHhlw6qkhWwOlDXw$WpokW^#
zlBu=KtkalBY$;!B>D0eOp1v)WqA#ZCJ>u3>bc4ykUEYU=pn2VK?#4W4peEJq$Sa
bvP>EF
z7I=nB{ZLv%^;S2C$XQCYMf%4~7LEWEnLk-4%MNyH`DV{yapHTpJ
z;l3p`xPIkQhI~G}F#E45VxAQ`_u|Lr=BF+)VDulMN5Y{i4@@iluGPySg&!hMmPBEm
zEQ{_`QZ#PM1`(fm3iDVpT8L|gG|HSs8q?GFJyaHv9m3D$ifs(~g!N(qEPe;{C!w&>
ztMXpCslrG=YqufNQ{$So50qPdIK#NcJ!>C`l#bMxW&jVE_k5~F_5pS~2yFm9_FCeO
z|D~{(qyCJMnSi~fsu6D??F^C>lU+z8?F4H%Yuxj&m&kM>>>+%w^`7ok%l(^)pk>yE
zcFI?Ef2`LZPbIHx1^-pIeKBhT+b4s4?9wJ@tPb_dZh&+P73fkm%t{mJJ+!xFUJ5kp
ze{|R0byxrM{ri<4PMPGxOQpxN(K&B|V`V&w*QJsfy#q1Wcrsqr17c#qq1I6iqYZlG
zp0dlJVo>&q!}w^R+14vg4HMbKU-#9={nsBq^zpzSnj+RhvM-1+*JsdD(&wtbhy@xFs+aP+gi>AKQRBFzwO-NCE6(#$%IdBg{bJYFKt3?C@2
zDuX>m;v0B3mRk9JLAkO3C~f&e3MfrALmF*5DD5QD);JTCX4YxUBgY0lD0PKNB2NR#
z(m86cov+1&kZlyul!yn0j}2C0m44qBly4G1`Np#wJBc*K)1oPT
z{Fqs%F^_11lqb%u)bUB^e-I}`)?0(s^(8>*9^Cq8N#S81
z>PTtlLW;EzMN{4E!lN;^*4pgjt<|p|KH^liDU#%q#&xSt83(aXnWa}-W1&9xEWKK5
z+pX5(=$>Iu-&o2kZdVcS$e#
z3qjo&OZAr01SLZny+)c0YCD5OWtsRDWJPU*pb0=VApE?gP2B?PI`=G_I$~1Sxyth;3(EtT)TVB^4c9IG
zJpV`Fy0J-zzm}%sMMzuMY146SCy|DdOkA5;r!kLN)sg2*Wcnahb@{~aSB{_@yEw-gm@&d}0m(_w8Vk%p2?Sesd=F^^c+_4k%*g{Z_^lRzHLk%+@O
zR=!rlbxZjIVEugx$0CtEjE`=F4;-#WIcCMY#(HVfHVD=_b%TLjCvJdtojAwD4xW?*
zo-N0)4j;b+nC2kb%Af-D#<#O;)C=G^_iBPeiG$5!)v&Ut+}g{Fo`(fW@kcjzH|AP-
zKtUZv;3NYvk=_s&klzf)=zgiI3*SjI&v&R__^|u-9d?LU#S+_lF0XYuFJG;$z679N
zzd_w)=PPO{Pp*Uy9jE=}!xMMu;MgV*}&Yu?w*K5LgeySjBb5K(
z`gQydnQZ=i#N)&B>FCelnAaGR>P}kVH;e7Y$u3a1z6$~LCC`YiLsAt&=Yy&=B86nh
z`Ea%Pe+tUHnonUn=g;nNH|KP2HImXtliT4Gy?rOrGS|p8uw+Ggb9)EZNq1lH^7?uI
z?B=|W%jSzEyz;^M|G|3`?Y4nOV#B9rj?m#z_07+9p=*}9&8^+_eIWTT^#vbGf$AfG^k_q_eTaev>>aqnWZrG2jQYM>>{cJ69kC9hox0n}{OfeiW
z%5uRy%ZRG_1IFhESWzpkz9E^p9l2I$ySa(+)vjnQ(aK!f8Tf{5pX)T*@<(cv|&q~mw
zt}xBlJluo%@6Cq9_jc4R3veC3T#e4Iklc2I%av%Y%?jHc?rzH7Z4;E7-%XVvEO-#(
zSnk0_GW6Df-{$?vS15ZQIE;!VShqA)k2ZVjd(ZShY=;Km!L+s9VbL1XnB=&-VLG{;
z(v+5rYhKI%JC{R98XXMg`E+u9jj3r{c=zbTKhzvdCB8$zJk{~=tE4=WJ%}+r8v?y3
zwoN>S5Aa;BH)Q)Begzh1m;W;y58xxBljw{u=S5N0<6lcPK4x<}V4(
zgii_PHxpR$WIn5-ANPXyd$@(U+qX-*{R=ExAJ#Rx@UB}U3!}eAmcQ>RD6On?y;^y^
zpBndk^mpsIQwdJc_l^R*Jw-x>wGdD&A&b4>^LA=CJpYc=lCH0AOkd_C9M`gj30PZ
zclHQ(t9S51wZc@)_4g-e%>`!z0Ygkd8Vs>U2mgOM#3#IUjoTjoFet8vm*`ci4!c-y
zDObDD3R2g-YWBip!f(lyOMzFXUNSwQFC(<;y5cQ!<6?wUvvYbYa0sLdh|f@x!a+D6
zaXsNz@Q96TatDV7;~(^j!>!)-L2qw;e`BjS*x&u9C!a?fpSCu!xj;yEHg~uBAK^2E
z45biVKt4lcfjuTfw(uU)>Ab2+e~5ej9^)Sog}5#vpl{qGBGpMfxF#PDRyKM&$2&NS
z=zsd>(eYMq>uBewVR0f~h^|tEKDt~H`s8)f>NK)k5$?(B=JyIx%N608yl$NHc6qR{
ze|K{Vt$?PuI76F`5Zura2v=tXNr1^
zqkA>O!8Hymp>Uwvpoa83Fg^&IpR~@nLl&A@S6JbAv5k%F1JrV8izty2ZVni~>529c
zUV4X&nPO{WgJ+&j&_thVvDzWHUsN7Pv^`olL!DC7&+f2aV(BL1Av8QIeDMAe
zUD9jL%}vJQmEFYwi1?zusn)f!Pv}cWHGO4J+&ZduIJL!Wtnc9(a_k)3lBxgs@V&hg
zeEP>7-T@mnVti>WJ-M3`f&3Y9BZiW&v*W906KwEmW9K)^Fm+J9>>l>|`=9p&dplcA
zdc~)VDiohEs!4ppWEGu7sk=qfa5bP&6lfQF@_k(fxkAZ@U{7uA*Or+BNQuu0eZ9q@&3#w0EGPg
z(_v4&Wg#G?`i_3TI$+B+v~Q1sjF*et1&A>PomymeHoZG_#T~<5&k!DV-#JCU`jm2Y
z-~}jwC9)Dcsl*Q`F5>A9*&f&Kb22r8j=+Q#K8$_5Or}2wG43WFUBFX-CX?lV&PS$R
z5-e~zMf=b&zJP9qKcN1^6fBwU@8ijrG5gaBJNee_1S|GUy(IZ7#wVQB-_7+UG`FXt
z^K;DD3)dr~V_Cn=Wj;JsUbG$@7(Vf*oo#>^?#RUemys-8jV>gsLsR1B?PCyGNER1E
zuKyinYC8FIbS^7DI{zYAQHy@S*T$9HkoQwQ1U7tx^aDnH8baZN>Qupthi9*x5*axfb*
z8JFl4uMsj&aRxSxYp0iUbL+$BkK!Fg7P7asz12flV&}MVEnTwsa=KLU6?Lf=Sk#sk
zb-6FFsNT7ZUQw6n0*k7q%+R;2=sHXp_~$gxW}{2oqpH1Vq`?iR+=P~X==^}ZFj}a%
zcw>U(Q;b$M^tgb|P6F%typ
z;-dKQ?G{S|O^a9#cMLH&%&W;!n^3SDTm4;J#dFx(>F+lvPoFX>b3S2I?0mvp$!iun
zpL?$4d8x2U?0lxVl4r%PD`Ho=xD{DaA_9S;Pcx!OO?dYgH(**qa8l56=5hjII)h-~
z(nbg+1q)vQ2(QIyW{%m?fS2FkBkjfFFQ?B6Gbmu^iLkM7UlgCmqxrkyxD@a-Ofmk2
z8FtZ_zSsYCedD;_`@G-Z-P-?n{3!^n#xDdA)<_=!S|fcj-mq#CmUy#WjeRw8PsW=c
z`)cHx47ko$6-v>kgl5q%RHRv};VPo^-FC=dp8g5UoerT{#A2;LP1$&+`T!w}(Rp!k
zHx^&G9+#CiOH{B^LbUT0!I;D8?gt(ahC_4s$i&*#MVF!0bQ6jS#W{ViOskiRr0C
z09L6@Bws)V_SS#xA04mvehHg0m8EuQ+mP>&wt?OuO~$(zeMz8qxF_RXac__$hiNk0
z&6Hu$Y~$a8+V$kYlq-vQD>~hV5ALO0PoP^*k~M3XIs&dRaRgpr;v9fA!7I!?2Vfzc
z8s?gVuwWDZ83p#<%%1f`7NS^lNl7Cyj@1
z_&f4MI?HQtPILeg&KVi-{xC61?FTA41bY^|W?u%k*KB)f$NL%-I2I{ZeC0^JK$w;B?Lh
z%uf7&9XLm%1knVPq_S6rPLgyV(^MS-b5#92nr2>+8{s`66d>(zQ|f
zohMT!|D!%I{8r4~O9UXvTyInAz8N=gN9}Kies*=u;&v!S2P}=b#{PN=UUq!BmG&Jfr#T=Zzzy
zuOw0lw;HJ#mzOxif})vDZeSZsalQjB_2+0HYHsI%l0WbNFF8HaIt9Vd1iQh&ld^ndluT%;spJh5hiy5NMPVh2Ug!q$@Lim22L?gL|d|B+SpMCg(6KI%_8n_SHKq|fc6N-OEahr#&faoiW9v(@ZdgaxBtpR&60
zAG&I3ahsYWs&a<$<^A&9RxA)aAkKKlmw0*5<0?W9lVbw_;G(Hxf#+EL>97yQeb%4O
z=3^AwV^6Y&1f6F!14S0L|LLTU1B?D|KO+SqCeZ*ul`bsVHL|dT*T~X!uaPG!E_Gq7
zanF}@|87bJ^y(W(SH9(((X>PUNeIM6JQh;h;a0>)wr&gvr#NbP!Ech01A~O6`)Bj%
z_1*0`@cIW;0|^g5{Zk(iNzhGa&WIJnJXfUhNMV>|sSnJdTL>5!M>hl^R18yJhmay<
zcnVT&I8PO>8E7KN2fGQWnF^en+dH2RH(`T}W_@xqQ+!{$@La#vjpN=fzR`p|LlTFb
zp@<{SP~?M67O(|zhI>BPgu9oy>AjhJtW~DGqIUiJ15WmsrQd#r0gRnMg?1Usoz9=V
z+&kRxKC!2A1SWJE04D{Ct>7%tz5q0JSf>P~$|J(~P@H&x<6Q@u|M~-{EOrF>a0qN$
zp8bPkaq#3M9a2#dPo(caf_88W!{iRW1-RGjlHt3~lx2Kb_C1WRF3<0T3h-zlrbr)kj+NzT(wOEl8W&$o-eC3aeCWFpCGHNEYv4tHX_!M4xOz;)ticdLZl^*l(@`Dg)qWpAnosAG96sObX
z3Y4_ie>$|9bR&lK-J=ui4G5?AHxKs1
z$M;o=08Xj|0f1BqvXP;^zN%WS^32AA=IOzr$}}4fhN*5_(owMZaEBNIsy)V+IFdoK
zIkMmw`BrA`hi|qHacT4dcJJwRA2fY_`u=_AS@G-Pj`|YfN30V3R;>TJQ=AG<UzoJ=7Ea>Z;*?CKKq8#PtVcF#889gt7PZ9Rk((%C)4ikP-i!0Wd_Xg(
z|7CPOzrrIUHiX%T&E>ocnH{ErEH8)!^2yIIaT!i~DVV8PNIXz5nfQlN;W9$L4tF8^
z88V9%h
zL8E^mF4#XiL%%;5UPvcJ_9m$5W5~nuGdzF)2F0i4$I1zLQLwlOZyRM5@Pal!>_7}(
zz&TP;r*oESy~nFCc|PzG$(@gnD3$6{s2-Ruo;uKwGX*|Av*PsQVf^v|JLTWq$9`VO
zN|b|Fm!yN2AeChwKKG7}b)MV%x5`7}651~c!1{=cPTzN72NiI*Fg{-gJx3<=2VQJ_
z1CV9SmUWkH+qTi=F59+k+qP|W*H_DI-M31KpgI<-@dC?cAuV6KdSERpimc16KnUn3sS@Q|TI1J|
z@z9~zbC0wL%?iK3=k>&!UahSH9(4#J3#sM>WmvD!QQ8j*%BM_SWR~;_QA_vEy{ocJM;AO)xQgHpd#|Yu$nA`U&mJxVrr{li#zZ}v^#}8q$
zn6tJ(Zim^TbR}Y#A&p`fB8_5cFvs&c&sEEzYnD;0NBmUMPJP<48X5iYnF?-H9={}e
zmX~sS#X#`Mf~sKki}*Q+DhP=o>gUDMTayAIOd|Hc6uf}#Ae&-fa+PnxMR>M6AF0#*36s=G;wO7yf0$K;USxL4ASTTDq
zWv|idMu$*Z|GsMSE#^m1|AAa6UqBV(ySN=Y+(2o5kHulFIk+R*;JwCG%Nn`5t9S{0Wh((iNG6a11dMnNumZ+i$0LUR!sR+1Tqj4GS8MyoK9O
zDZD9M$+UUFY-W7y8F(nOL<}xPB~_XFX&uN8avC|rh=3EGv9mWyBA02V6GX*K^8=9I
zhsV;M%}R`~c)*nJL0G$ZMwSd-Q90GoSSc94gqwns
z&QM;v=+h*Qb#R1M%2=1cp_u2KD7Q6njH8do03NPQ-2-h{S8?|GyiF;QTh#Koo@Y*z
zkm}2C4VL3hJtHiJ^>_g)X>6~+oMEViJ8H!Qu|pYOu_c#bnYYV1Q&yTpVYu-wS3k9h
z(WbthvQ_0ClhS1$cGLTFsPC}NOf}}z*y!-5#Y&i`c1}`=Bf?*!Y(0@E(bzICA)1UX
zfef~t7MyVOLzY+DPk|g=#Qj~HXjhy#%$;#q;OPCWq&`~9+wt%bt_<=Tjl9%uyTUQj
zbo1gneG-v37{c&L?x%&drK1b908PRi%ktNm#6{@OdJQ!_T4}JGG+fw>hB3VXjYeO7
zsdf#V{$Y1~W8^+_^5WE<-PbjjL)@(DzY7#y&p-TD*Cqo8XtB6VIFg6MN_N7`=u*>n
zWVU;22A^6FW@gcag%^BEv{z-K8Ms{IUEc3fRmby83XuK?)0@7EC4`!wgYZAM%bm#;
zN8%SalP6a$v(yz_#&L!O+^weJ%VH8N=yS7cT39&@kl-kl#%GI~yu{^87QaHMW-py4
z86Jf#$o8gHX(Ce6@(Zwp-IUOF3pEcyWkr?9tZLI<69x&KyvXjV6%rV=>tTHgfz~U$L0T3)jE&OyG_`wRALT}G#_M4nWx{SbPCwt!
zxPZcIg=ZILz=>(oe6Eqar9duO5FlhSjRiP^B*(r(rd(zRWV99bG
z3ADRY>d?ULS`L*`1d_P~a;6MIH7Fxfz$Cg1V_uu5mLz&L5Q^ZA-gHQzlm0vj!4>BU
zX<;{yf;gLAsJMxnNwraa%Ynx(m9<_OgMz*8QLP4tF*FeMyc
zTE!v|Mu`lnMl6NY3QM1`+^<_u=_upz4o>PjH)J4&dZ8*!kGa|uPSO^~Fo>FYFS$
>{{Uea9&1DZ7xW0aN4$(WqD-CeRw9Ar1%p413M;CtdNf)3$HWl^FF3JRAR3n9j2
z`FV!g3njr$$8_dzga$}s0z^Ur%y(cxI;>M&9-@qd2G2>bqvj3f`rZpx`I81RsBmo>
zhY4gLbkx9ZeJr48!-5oxYxxm8Qp}guRjD!G@eEj|e;smL{_qO{gu-EtR<7|yD{KcXd?&RI6|CT1R(!n{jm-=t`CT~WD|?C+soss~)0
zR(Gw59UJmvnGmx_s8V_B`(8K|aETxBAV|{j^3=SfJ`~({?SEikkB;RB$L}3WqvNK@LRS7
z$mXdCSK;^Mrla{AkpY4OL0yE(Yer6kWv09HPo4p!D!wT86EkR%L0z(xG@qX2dI3Tv
zof6BJMa6cJH5Z-6J$Ey^i`{#NT8W>bJ&1aDj6U9T0}o@RK|Voyk5Eo>?0Cd)Op|PD
z&b`??oNiZ}MoS=1wr>r7qdKn3ao5%aYPCyCTB4^Z-jHlREQ|dnO*k4EN*LahxKkfU
zM7g*K%!>_=vg9;!;USjx^lKSbxXK9NMSBnhZIby4s|p_w0@o>@olVfBxdHYM*8~jX
zgz5~nyB`MA>AOavj7)lbp(%alP^h_BHohT|Q*cmn-}p7K#ijuw^Z1JLJd|KSqO8Cz
zjaCm(k0S?5ay%i)R!k}0_t)sE8^KO)SxMFZvXgSE`Pwh`^A>IWsaDg#49>=sQtvku
zp>h&sfT5yHG;~LG_5h7U@m;k`b;e3@*0h-L)X8AtRR6!o68VN^OJF9t-0c-R&6F*bCtq6_`H?TBIX}
zeM)w=Oj7Cb10&h~R+>NSaRbO;M!k$sWJYrzl-J4v<)Ny?2bI^V&FpN=pXI1RW5OAT
z%_`@2a`A$#(7c5NiZ&*>Wh!akV|k)6T~M>QcTnj#%f*paZnH``^OWZ+*@72EPEC3A
zn>g`Vd8%l;qC~1w5>>vn$B`Yc(oAs_vy(De?J$cNhHR{s0mM?6EUrj#X(ng;d@|JR
z9#@qdL2&(aDNH;B5gvtH7)O;$W|vk0GLys=j5ImkX>%5>OuxRr756-o8DL{Lw>)hk
z=UcMkROelo-0zxdD=B(ye?BSZb~r3%pti=w`b_4pU){#eE`aiyX0H;gCEPcn4WtKD
zC2y*Cd>QjyH#N7AR7=e+%@UK%r?TqTnN5ercU8Ot)1|@Y4`tqCj81V4&V1p;u;9gQ
zMZr6-wjW}X8frM8N)>9@N);udSA2*q>y@JNVGwXL%Fr2CW4y%NoZ~fmAm*`Fy=%`wgy=#J0z&~Fk&q+R^N9H
zmWL!Uhk%)5as)z06_3`u;2j6JqisPFSx7IO!DHo7|LTXsBW9_btK=0<)sU#MPygo9
zB@GSI7nz}6a2t8ncKZD@gG70)p_GKsDU8R&wss=o{&)Js*AFtN0;-cL?n%iS?|ZBd
zC5b>P3H7n7AiP&0(B>}R;QxVlS_yN{;kxm@@DDSOsv!Y33gz|
ztjmB>4>du8ce-Q+YWQWQ9bvM0xs#sg~L67Ka!*hkj(O^NLFl5P1v=(hAboYYb#Ii(CRE-X}tO@4_9dQiZW^M-8O7A&y_^hltNZ@ltKoq&=Nj@
z`kK@o69HJwhuKkzU}}cj5ZlF=eQXpija0am{MVmsCnwIs-=upzVg#4S2y7$O$J(vw
zw7*dX0ho_3N#xXsuVO)`xrX93X&{{Ig48ZX^~D(rG(PE!2g%S#l;`Vl2{z2?d{D(U!N>-;uTca?#*E5C&Znn}uN95#~uEuMV~DUncV%DiK_k@vWAgX?@HW
z_f#Ob{x+*tivPbnl->--r7Dwl|IFrTWl4#CNg)ZLe_&sFoAz(mgTR75&bYx>@HFan
z8)(Qy{TuiI;chv+D@YG@G531E5TQiy
z(muTlXBO!jQ`(H>E>Wcu@yMJ=khRmewM0Wx{G(G}#Bl!?uiAJ2ziJ2kM&su@ZnP5i
zsT-=WtmVTs9ck+fgDFPoeBGx8Z^jE7-F-K2!EF>jOOW1)C)qT98BXu?kQQ`b(gC2t
za7gFnBq0?3ZAAYLl1v(0n%#H~kjX$+-^XRejLvN-nM?7C-V~igxHmwZPJbYopq2O`
zE{e95(NyY72p#4a_dfyjXs463AXtJfsmOG-O`h(b=#o?xu^ymD-TLNiYalZBu^Z-p
zDGH(!8CQ&78=Q10iw5O}ZO)K<0^+yF4vC{22JB(q(aNIX`qwP6!a4!4#2
zxdz;~8%Kjb6q|rsFd{}5ueJQz$@Y++E#b?C3IR`zZCWFw0;EM`0da>-|FNM30RUo~
zjqGUx(fwP=bPHfl=vgB7%89f4YPr3&u&S_wv)KO`c&Lcl(T=d+wf+aB?g10nQf%lK
z_^|f6q^}G6u!Yb%{OTA@ll$$JOq%?Uab-K{7x9+JA(SO^2&7FJ1RyG>-c^ITjRFRF
zD+(aa(=D=pn^sc^Augp0$dYmysqDJpRQCV2t5$YZJ`r@!*=X>d@$|cNE7@qeqe0%(
z67JLz@fWByqG@WsSY4~Qlc=T*oAZCE)jD+u#f^4kv=`@e5f7~`UV2Qtr&aE?nzxzQ
zs?x%Be=ue6COu^h-0nVL!&Zm=6mq(GJ$-BMwYga-V)3o`)bg}H@VnMRmgKd{2?QAB
zh<~iJ%xq)olfpyQQErJD2q4ff1qf@g%B56M5?K{R5?L~Hx1TYlhx9+9h=Rmm$JMGd
zJM~a0WXVzuh8|h)7`j>*Qc{`3fd0US=t`x0<+mV5Y7A#tc5!Ehp
z+!#H3#FG@7nK^Ro=3g`+`Dv6+y1Fp~-ni%FI)RsSk=w=!GARwZyyXTKkKg4LY&!aC
z&NSy9%y$Pc;1=@{i3Z4dNn?$q0P78^^dHunRK+FzT49L}A-yTa_lA>^3q*S)%@75l
zfTOw;brt-56h@wqdG7dDr(XBx{FzU)dVBBd1Xp}StBl>}i5Zx$N?!Hv8Pjpcl$p%T
ziL^aJM;>jzSOa~UpM`~&*ZMu~*rPjTMj!nWWz(7$O=Iak7nS?L#S7f`|G4Etebx^n
z|G4Em<8z;c`Uj%AVxa{lWgmD+vN>q=T*YuO+b%8vpF*4VkP9OiywZ8r+^Zazx_N*T
zjqlur1OwVhD|k*{UlL`HCUz3sa6UwKYgtLMzdi_@)(8mCSXqy
z91C5@zoW7&;NQEd<9`n(CDT+<5
z04p+m3|PKt*kkG`uG7`Xu595%a87o#S+t*@!zPrj5rL)ZgRKcmw9Qmd;dO3b^gZp^
z8$qvcn+~j*GbG46D!2wKC1Y?fNKKSUJ@@#>p*Cj7t%)`lX}T)$>rP_R@AT$5FLtY_
zl2IkL--WVZb|%zlxFWt|z_mZ`A$!jAK#mO#T}Vk*#_VNTc9w_;pQdiD?aBKxR}1HR
z4*@sGLQCN0DeMw_n{c+cZtVqg$8d~{1%srM(v*#E&T0}5`}3PO
z`}0RJh}EwiNgj}@M9-4y*Na07HukK0O$h@zSO0S#=7m8_D0A;M=nGVFnsCNGT0xLF%|e3ki#rAZVHPyQp&%a`IPbrPOu{c_okfk0%D>c9k5w+viVsy}
zvH)gd7o5>t7n^HL^-9f!<5a52Y?j85Z(Pohq=MCyqJ*UeWJm@o@)Ai~@l_J5O#B1#
zzh1>kRB|;KcIsd;z&&ORBb5B=1V6s>y8hVMUWng$>&^H^qA)SkbZ#^N$ul3tu6luh
zQf62w77I$+b`%8x0m`7;ATR#NCwna0ne?3GE~BQo_rJ_tv$~RnVg4Eg#7g6y+>bXS
z!};IVf4F*Sy9A4&%xkyh$snLyPH?X}ghu-EF|&gy-0lSLWnv`%7lQlpV>mzi
zb7b)A2TqV9y;b>lJ<}-ta3~d8xdtju5Hmj|>d-z2G@HD_H=#(qxsEo-(J;M8Wkth_
zxKY}-Ax;oC8IAMw&uTNG4Ie+PniaI6UHPuAee8kAXP1MuKB2ja3QFdn5P*2wib|cf
zo@M`L;Zt@5ftCf_n3di&J6gzCF3tC6wGvb6)H7sffKZbvYe)4P9{vR+u#~kO$DqwL
zo^=|T!sQcfV8=iFfueX<D`
z-vkM1udnqI=Qqj1yE?WZ;q*?0^V^2vO~CKWq6T
z3JT%^yLZh*r>PU761#W$glKXuU8QaTY_ej9Ud_IVe!3R$(T#!2(EX;?L;Rv|>T&C2N$Gyo^!DBG6Aiwsv*XRn>GAR0
zG++c|U>v8(6dpcwL3B}nN}1hMhIkm|Ksz&=#&Uw#tkFJ>^uZ=VK-}A+CJH}
zs{YfQj}BiQQxXR@vFu-3qePt4pg6Q
z1+C6^fLa#=d~s1ZNW@Z`Zz03HnrjJew)V4z1=KY3%-#8;L|xs}%gNL+S0-;5^(OS2
z?tF-B#nn@aW=rE5tkJB^!DP3bgRW
zjF^=picK{Zz>Xl|*iv&9obiD(UEuNKF@gz>n2-{L5cU2Jv(Nx#3$4S6SwaHnTK^gn
zsR(YBCFC=<;6HjC7b9r8nL!}^t@P02P4GEyB9S4!Wcm;A9m2q$dhOu9C(v99@bVhk@#VtZhYG^
z6@1dRAs4dBJ4(Sk0t<&N0-PY%4a`L5t7)p)aS|r=SpuD(dkXY-h7z)iyXFK#z6}^Q9
zB(t|6>mh5m!P;am$QqXT!x%td0OBKz{
zdAVPFp?VX2O@O0OTA_-HhIeuOgkOD(U``?$_eoBH(En#Y#4FB2ey13Nq4&63=+f4-(@_wHem#&Lqgk=S`>$A|M{wKbD85B{OS#N?uWe&vuA
zO^lVo$>Dri*KjF%jXm0nZYy?hq(2|scq_yv7g(1GhP32ruuS@mp5QjB47S7@jay&C
z`Gqqf#6sUrr9E+2@h-~Iiz$LVOsBn75-uy&2fI52UAy#0x@=i;Q8enTQ5W8OvmG-p
zpL$z5cLx)<&fM=uXE!r?U#7NOp&@-GwO0*W3~*H|T~9EH4rI`@xPu{)b$lKkUVa;$
zEHpkG6Mm~E!+$7kHV>vp8k34vPQ-ffzS=zQj{LSaeK2_=-t4+9RtWO>G4lxE>2LjF
zD%U(oNG4D#qp6kBnW-I+B2O3klk0z%qjfH+8jNG2VG!9dFTxL`wYa+b_`Sp1_i-Z*T8t5%F7+-TbyzrO)^-!pclJ
zM&yfPxYxS5k(;{Xt!j6X0R5G>>{dtq`GjuWr)aBQaJ5fUGl0J?J%MUSdmA*d0x?pS
zls7FU!ijbSV_z|bv7@|Dbi*!F_EO63g}Nh0keA~15PO;bykD#qCM>a?G4c)!vofyy-w#GV
z?|<3E5BZ~vAzFl>fRWpwn`e`3w87!yA?#)(7&mMEl{ugrKV@1!EG6Usv--GC_4&=-PCr{uVL8tHeo@TS^@ypb~
z#7`_Ykq@n9C4MARm+Y?+lh4%9mCmYiC?3cr)6*HrLvUXI&@O>0j60ugL7*wlvUNta
zQo%{xtGk;Y$c9cY%qniMPSCsDYGKh9n)M!&t*^gq{F%^frF+3I`yN4~#Pjacw+f*kjB4~pG}-;m6w
z%MUTYC9ZbB-K_xE{GRLJ?2IApW@aL40;;Ak10O%mZ_1V4vS(~i?TRA9zVcHT-A5kk
z8o}P;j?#w1a@oXz)3daZ8fLIBZBHtj9btoQC#x%yQ9n=!EadI;&e6w*cW0Ubqw;#c
zXLLl0(t5&*R+a$0atIq56je%T**ANd5qD;f!OPXqsk?V|ZI@lr2oMpf#f%YCdIZ_s
zVr{%gH%Y-@V1s0tXI@SO^BT+HwBBSV_qPCpx*M9(mYPRonw#EyJi~Cx-_-=PKL47j
zZ2PTh?`-+RDs;MWYKaG%9>9|&JA!dA!NK?y6ebbncA?e)y#1C?75>MUlaeKG63I>@1=aBqrz>3K!_cF{e7pAAR;F2^;^w)oXx6sY#S5x{tuGU8RH*Ovv8U2D
zX{UgC7+g5g%COtUG^$Bh5Q)XhAI4-nR`x*D#2m!>Dwc2X%^gQ5aq-qK(Dizu|8I*+
z?k^^GqdxV=fqR)Fzn|ZcQ{wYKHV42Bq$A+QDUuGrLsNIs(*wRe*?QXA!_K#x>StS#
zFec-%H!6Q_hC=aK=OZ%?*s-QHVcvYqnp*P<(SX1IR4~p=v&-VBzn>;q9j1
zokc}42&*mW6Y(RCqJ4wWP@mHiH-vtBj;t$OCSw9y-e5pyRzYi~j-a|=p~W}Vik-1q
zcU<+$NFDHT___1(NrWA%CSPSeaC>&JGBIOCS=#SfG*8^+c$L5w6*0CEa$>fgm4j2P
zdKAD?@OliH+k^Pf;+yek5wF>k7$S2a)-Y=EDUQq&IclMi20C-&(JW}GkphaqF5V)+
z{4OX}lvC_f8zRa9T&?0
z8>%Y4{;c6xsKcbHEk
zsQH~fL?hL4%?s(ZlcNg3Yebc`UcBBYH2Y^ru`*2-=zd(Wa?m5jlB0}HDyroQac`!L
zIf``K*U%;99myakuiZGC^vpYbI$ieH4~SFY`1yAAshz%h8aYFxknJUoorX_RCBAy?
zBzPrrjASs>nFN3Maop)tq=%Zz-t~v-o7bNYHQ_yx+bXzmc6+Z^+bQ|KOkn13UxYUE
zB75YA;Q55m04K31Ej|cDvUVl8G%-YFy$USbM4>DWyV!Qt$$^4Kax+1Vl-?cZa1($B
zkUL}b+tz7o_qG{0nn5$~-`%EO)mmG3+52-Qb#-HB;OWgy1du{=PHvXLzcTT130&(M
z)=?>GWE2_{4IWSKCQl}IP0H)kFBHRV?DL_?PJHjXgBk5;?3b2ok7u!)F}U~?MP
zlGc7~!^=%GBdw?w3ow%_!eRx`-|GbKGN32~?d=hIcqBYCd`Z4p*kSIPdM_XOdLQpb
z;XQOLn}ZWIec{O+Wzw}gUo4frju`rc**U41F7C9i1{K4Rm_0q&d$w`3;$GcnYih=-
zOO4lCNw}a^UTQA85V5W^)LCgP0jf5wx!p*^3Kp|6#OdY&bC*L%DS%d_mCpb4es%SR
zWe9YL{P0Oar()P2b%zTZv~s4^KC2?WU3Q_(ew=#-Bi*iu6?wplOYr9hA3HmShCj@*
zGthhhMW+w?s4&1
zPPXt~{C2DQuGn}HPuC1l4l3rAHbCI6N%T;i8nm3~c&Vv~*Kax4Ty=p6??)-DJy8Kq
z^uptAQ6acNq3x@_e_jm3Y16>fwc{JOKz{X}tY|L7AUlIVlW@d}OG2@?S}Yf7Q+KMA
zBC}sKN{Un>=9$o1I7aNbCT7gCn)kAP1GI11N&!oa=-4Eb0D>15eePTj%B3tKT76*%
zRaHhIhGe{0L7!SR<4==~yJXv2IaCT8a$Dm$>}fE+9RMylZfTS1*M
zIC8_X7pBN7rbNbyW+WA+^UZu&Kjt?6OS>qsCRRjpDXiD}
zU^4Ys%yHi~%%(qG6qJFCVO3sc!wjGg{Ybr|ANkxfc|$#=(>Ap#alIXkw6&f!_{^N#
z6K=IUt2~GU)J_${|r;W;gVG7Gi5@fzcK0%lc|TNaUV=k?)(bJTBNWfT&&*+
z^^;C=HfBIl{~D+f4WNQpefV*0F|F^ha%lVL`?{BlP*^m!7JM-lLmv}(U<`^&`UY!4
z4t>tPpSSMLGX9LCUEzfUOrcL!U}8)p<4`Yb9x%O)yXsLmz)<&qnx>ET%fi#a^)4+c
zNs<-}4T371Q(o|aGDf~`yDU|TqbwRO&W!m6@Rz9!4Kf4o=S=U28seGniK0yLMDojK+a9vqq|&
zeRm{?AuCQ&-35^F{H@z%uOC1cYZ~)&B^>KPVJ=t*OfDOzx|#3p_EP{p7YcmizY5QCf8Ic@{ru%4J;pw384y?NF&*#<8#Ph6YHG#8(?v-8f`7<>k
z^*#ZRCbU8Q2!b(A21BB@l6^GP^7}?jIh5u3mGXgMng`Wj9aN}w>p0M`>0^O9>WX|i
zw))p7RZ0y$%q{p{zFfTAd7Yv4eREV=X(dARj^%>zXiL9~$|EB+)x;FKQzRM%rY2aw
zLsP6wYS8Npowho)`l%r6sGWc=Sod-&H(FBdTyyohLrhN`U3b~l(ROM|h2SyRM)wNa
z!$w4^D;0Q7}N$s;|~rO8Y~|?O!z1&HG)@knzHz(htm$GO*DBfwX75y4rx{
z{##X(47uo1oizr0mQn}b1*F?kuj?%MM9NM-cqR5O;6Qzo#*Bd!x%Nod`?6#J`zK6z
zoB%IQkFU#Uqm>1hFCEoL9odpY6|=R*ii7l%P-1D7iSo#tYJBfa#&5#1g@a@3FQ68r
zJ()zM-hQLUAN`sMqm>wK_#Q5W;T2~5MA
zZWjyzmQ_-1UGzh3Pz5vu^9twv0q0LPteoAFX?KH3)TC_)*(%_$Q26NZtj3O+sK*7W
zO&?3s6K0hyFk0oVA7>hE_hO`Aq{0e6giw79!5T2gZ^e@4Ze9^GZprJnDO7vkC{Y*&
zEgA4#dqFF$_T&ifp!N20{It9O_&9}*R&KWOv{XFi1{4c{qM{MsGL19S5+n00V%srK
z;7K%ifndSzvZkb=K!B>|8}`)n?~mxUft4@QR2o>QLq(BzBr;E&0}1&kW6vz9v+jMm
zzku&t#r0xeVA`1sb3m<)VrI5OBUDqf6Jf9rQ{NG05+fF#shGiaOGC``5X6$NVMnQ7
ztC*E+`1y1RR6Pj=D)AVz7x11U(bb9p7clU9`;JuwOo(F{(-pzCrYc6%g4dYnL@@k;
zr%ytV^kz@4tA~=2DKTvn38`Hx4DActf?yrExj_ch!;@HYcfXKC+y=C`TVEj}QdwW0
ze;lg&&BVFxK$^~zo;yHZh$#l>{xTP(SdzAM9AQ%8;i&ODmN0pI&iw|K9ECe0ySauW
z-QysqxdMi)99Sl8N@Sj)mCcKtmoqR3$6@8X`RDLi4zKl@uhFyFM!;{hek`0rZ8#^@
zFf@c6xNqSe%SnY8{r(SI$B(jO_!jqCeullCUB9l-&)n-1dm*w<1y5rC-!D29ePd%x
zjqIItMpEL8!|1X3^C>VWa*zE;RTtwS^|@>Pi?Tg6+U|KiYJzqP|b*nr0JBHJTz`Q2=h4L}=`tQYq{`V|X@hOJjKQd+zs{kGW=$_gTqY9}Im%b1hW
zLi6?|;VO{PA^JZ}+WJ6T*}Vp-_kDqpAsWLgc#azoAcIK@79o)s4%(feBnNEg=6%kp
zW9}E{=7JX)Dh3wdkA^|Up$v6s%*L*@2ch#0z>r*;1+GB<`R67bnJ}cfWA80~bQpg$tlkc^WV
zfOJ7`VGaoO;8;y}3u579!cHSj;r?-R+IXq(=eJk+Z+}4vFjxTkGLRYP#7b_-8;^K`
zCB##g%d;p4@f*t@8IU5YjU5I&I`(L6IIqt+^)nzQ?(?CeHPynDObff>+1p0=68l4)
zAY+c5AD!E^)5*pr&}w9-tvL`xj+`~Ma}&*}1A31crD%N@
zIBhDgK<832P?F1ww~e!AM%N1|Y}|@dQnv`qIMO*K@lOqyaaEcoshu*+Xooe^+EG<=
zM2=!5s^oY)0TvRTSmY?Dx^U@WN$3C5$fdD=OO8kaMoDQ}j|l`a>^+lT
zfG|tZ92)9g#*zDTX)r&+;@kjrmb5Ih7ro5XIes%~QT$niK7hYPoZ5ZaG`pv!bXkod`)B-EI6Ykyc>4fo0ySxF4Pl;c~mg6z1as
zfyL3p;!TLwp{nwr7n+dEZ*?8}1X`*3Dlh?n(wdCkdaZ3QZ&Zy6zzs{f_sCpvU7cpG}0vKn|B8)Kn1_u0P~Z{mfE<
z1;$7v6jz}YPnet7!ROXIJ)-{XNt$Qh(%xJ!Lw&SN2BgF1Qu8Tu3eTXj7d3eW0;>`e
z2`ZGo9&%ldKwk_g;Zh!x01+Pz^;xxC-6S%D)KWU#M2b~5NE3UiYGj-lYAN9qb*N~3
zS%Z%H&ojfmS0&wP)e-7L`2(?kAAqn9jakw-{D=U#;B_JZUtWvAv}!W@8-@kWskyx<
z)*P{`J@UK{`(zOYPizZLy}kUS4AQk3Oq;$%N}GH5iguZrH4YCCCK>{K
zGhPnp*lZ;G&Qq3REG%ag-NBw4lH0J&(AabaZpqt%-NucsM}Y$Hw47GO?X~p;QBX)O
zWg=I>5u_q+9d|);nISrM|z}3h^t1J7CQaww7juwvf!@nBvNMWfs-Yg*I%KGa|`9vebeux1<92>e0
z1NU7o5qghT3e2`+2mjGMPY)*bC^)v805LiZ$SnSpvVbf|{DmgT04*XYoJ%(yMBO+D
zN7p%-Sgaw8lzzHqyq_qMc%$V+W(g^sLw$~WcW+j
zs3^r0Y=!m!XvB7jL4VtT!8ZzeFO;Jq6l_I0U?DSAqNJUZliL)6mJw4~E13ASdy7+umuctBYcDGaj~9I!miF%&{#X
zzT>?vcV~P30DU(-`1sQiZo;vYKhF>1`}ukboBj=$m;RnEI)9HfNiSCJML})WK0F62
z*7l9mWK#Kz`@*trIIe$`rdS(pSv_Pzhd}>OBodSVPBH|yYPP+Oq;_$eWY`Fkf_hxo
z;4tN_YIqsjgV!ta9?d~B=z?5G!-I<+|G@kLx@fl-6A0(mAy(vO!@MVK!J{t{s8&G7
z$U=g0r9$f>QNk94R0={2?TBikgu#BCHr<-b64Ddv8i-TU7AdE@hsZzF2tK{P!~xcg7#SR#_%q<
zLqpOu@G9Fq>mHdWa4X@Hu%3(`jUzudj_I^DJ+{(=#@MI4bF@rAhY0Lm+w|W9Wc!F%
z$T{U7up$#JOG-N(^P^qxa!-YAA1x;_@N&)3%8V}abTX+FH37S0NL=UZijMq4*!we&
zW}A!S(2SOm@CFrpkL!|9xWnZ)H*t)@re!hvb*(w(3^0P3c==J7jIUj5^pIF_$thPS
z=^gYW$C3f9@L8)2%$BCEP4=KL>87w(Lka2qh`MX94`
z&jaMlj;^WOQ%SgkGhpcJ`IpC_@Pr=LrWvuElk(tkR+S7&5&5@vdiN)0CN8cckW7uT0!t}CUqox_d`?frd@T^fOfa9FdZo_xDJJ)gh2
zE;wkrtuZQPzO1n*;l0u@${5Q0ZZlFZSluNuqSTVd+(qQrqUc_U-4#6==}C
zYL5u=Bx6dmhD-;{Wajepnw3x6V|GZXc`?YM8nCGGb+7qLX5Q{YO>rTX^tm2iue#x=*ZK10eK<4MG^+^?kK}R;3j#{7PxwE%sf5q9$L4v+f2lxBmEaSZ
zV-XKRK==3@YnL^R79@h8OY%T-nMTNCxE^-_?W~AbS=F1cpF6V%Molr{bT*xE^E!8`
zaEFnvs@u0DH;!ft!%To@GfsLw{k+3-BQRxGx$3R`+927mv72dJ9q(gq;&p}GoJ;*x
zO+p8uC00QKx%MNcc23ZsZoR$+=FcV(HKGjwR_-|74qGBxzlNDs&O4kho0&S?#WpYA
z%+fFp7FLu#cG9e8_|P0r%LQX`md^48_i7xAmR)9hJ@>A}GaKZN4t&8xs11
z>=3$7s7GQ`570BwtWtliB%YuCOPZ%>q2@W+vvVMMXNWeY6xq49*SYO+uRtuQ>1z{E
za-)=-^rF3U`7`Cq?>2%d;J3A(8*e=@B&=x++~BtsyZ0c`v*HQ8Nb4;4N|ea})wYuO
zmtun^h((#e=A3LrU8X?7KQhWW3Z4(zrAk%Hb+Dc6{LL(-n?Hi|Ou+mrr
zOU(b7&{|-U=4Y_us4+3kjMJ;-g(C5!8f?|c)b)f73O%8>YQwAAs~`ws{bLAXP?7vo
z8G*2_#sm>Rmq2C>aGFfGs8n;q#bNE7yV*M5un{
zhC&zI?1yV2FGMoJv|r(T*L*Z`4052Iu|j
z-&`k+m_aO&w5!k@9dcsv+j8e;O+a8mIpXbBYodT7r(zm`qv`tkS9ijM?&k!p^K<|7
z-y8Iu!Q@>szT_M|`rYiIfi%035t;74EYR>tNcPQmKA~}_w>v64gZ%Y#gp+PRbXv^o
z-7E3qHkN#zj(h3k_(PS_RMqq*%5DbI-`=HWza1yD2lB$l^$QD_v&!d0V?*I*T
zr(x!d2`8qMJOsC9kd+sAD2SoORB5w~jaec{u$J+DKD{tP^_l0>&IxYdzH%3j6(}A>
z{3nJr3@JJ?2pUvvR;oyXyUY0A^{{`rMC~69J*wp9b6jZ#%$tw>1|u@Oo~9#9r$A5;
zppp!foXD!T;d3ZFRR&kydDop8r?(O3AEj>uJP}>nVt11_e`C~=mS0QgAvSz2J2~TM
zYo`V#tW+?GD0Fw>=rVE`JuWK5#~=RQsj3t#o^MT+Qn)8g&O9T^CfytM{N#H%8S`j6
z*-Bla)G%V>8zZS4N`e&ju5v-cdJmUIsLk<3!?JRD#@BTwUfiF>!|9@23KsE+(Vg&y
zGm@f@V?`QHb>W(sJWnx<9rX~hn~_cGIEJ?3aZ~y%rP_&?&5iCM{FBDARH&xv;bD-H
zj4_V&+E4QvvCD;v#ERERPlmkbFuHICU1jHtcYkp2b?@?O4;2GDMNb^JqE^AxXZ!|weIMvrY8_nQ%!Wa+>2dgldVO5-CEt90xXki05EwxJP
zB+UDp0Jo;vUZ4`L-zjb2gh>W;nvStP4l~H)f06Z0@sTy(8*gk+%*likt7A-T+s4GU
zZQGjIwmGqFI~{X!`u+dT&H0?WzSvz|yLPSWT~B@2vj{cVwRLv%+cz}ZErF}Nz5L&u
zI`B!UD)%JwXsQtesUk~<)I)%jPDO@8!bv5}mg|gd4%5%DGb4=?MJt7RFcNWkNoqZW
z!h)KRn85%M!7`-pc!dVKc)zCVyaKdEFso=F$9}M^oMytE16gRf(Jk-yp3^cjP{?Zc
zq+?caODv%!6x07KV}0+mQ<7>g-3_nC&YtQSRI=C~y2z6=bC3AA{IGFASC-ThO~75%K?x98!<);cywH)i%Pjj9`Lg4IsA(f7$(4qjFP
zMwPCINKV3LRa-?Z3YXSKh^D%^B*U+&)-R7i-JyLsi=-SCr^G`@Pa
zhlI#oJQDE)@(b_<#oBdOo;m|0O0neH-iI5pOyz2&(OsZGJ)61blqNj{|$V
zu>Z1~>R*_`s5#@(>aSwVRa}ut%X;n1nk=82O90w`?Ut?QkmzyiBIhJ6#s86470HFu
z+^-yPAMCP1;rcFql-KpnHIJ@-dfZnJQoFH#kPZ2r$#toQ%wDuAqqIS|=LPk
zxE8!EEJo}$py14nZCq5lXEknxtL?}o_uu;HfobMSh2=Cv&fKs17WT-M&F0*b)2qEr
z_hqO?h&inqD<3l89VZN)4=)7~b7a8ON$EHhw?mzV8cul!yZO8u{9IoS#s7Rbl-<$(ClR=;Z>e^uw>&
zwhriC>l+GQnY0O^;BDy~U`ZVd9k~x|;GR(+L_bNsm-Dknz3uc#udzlRV+-y!0rW55
z#1YECoGc(ll1!|gdm@XU=|fkX)PbyFyJ8|u_0%k$pXNDUw?!^t^=@SRjog(iDVlvV
z3P#L0j4x^}c3NA$k1wPhCa@(T=p9-2^coRzaRih`!+CEdU{lgn274dn=|Y%WJgKAk
z`<9<3CQa|^J@^^nNC6+F+wCK->FF(O(rTv4HRQFWv2r5JPQCOR!^>c%vofw@c`0bY
z_Gkl8Q4(6}yif8a=RkOXK(mHN2fRe#1lA`xyjC^d`rw7XdSpO0*U+!z*V;2JFRhV$
zoYvT*!mFA4F`euB&gnIK03E>9L9f#rQ(xTK#Bv66CAu?fUD~#LKWy9VPje=#+dze4iX_UpzQQk
zODUWzEh5>w23koDyrVxc_}PI96foMg$fwa-wAyY9bZc0*OnGrOJ3Vd8ycz^C#!4xd
zjPQKq3I^)4a)v)D5Fe3vuS;g8N~l9L0(QPNU&>xz|N5fJ{p@|ya1ov!C6a6O458-e3z%B`Ag(!i
zh59-J33>OHwriR-NBDX@|NgX*g1_#qm~y_@;2|?#`K)|gEo8KNa6ZZyvsv8t<6vMq
zSDtSrH+o`;u$@9#sgFv*}@;vb?eBoIM
zVKUrLDz3vS?l;{Cse8T(H~3%~>~i*4vUv_mQ&R{v>}4F3AVwp^_JjL5k!E5I-a~)F@2xrgX2DUS0W42^>}Ld3yqI!nkumZ*
z;lV{^xOvoFbYdZp%>B)7fsRuB5HgF|V{ynW|Y@Yrt9o?mrJB
zPnMkE1JP9^WZG71C&+I{k3OhMBqg!@styIT)K5IU-D~_zlPaelEfzav-qruPYh{lz
zeCOn6_Hw{(|{i1C-xaZXfFsq8{ghzOJzxs^)Z#0pB;M>ZtJN&XC_Wo=z
zH-}-O6yrK=(xB*+cfAVGrX1lYW|^!UgHK
zLlPRM@c-f^BkRi^Z$3*D_qpBmBky4!szSv(r$0F5wP$k9TlZL^dK3xMufm?ZCqfp(
z(Dr=DbnKdNYcV2g6ho%xW{($(UB7ZBsXsi1Phw0YK90)Lo9YqOWVKjwx&e+Pod*!EEJ~Yj}4)(hxp1q$KfoS>?so
zMXYr~t8R{XoxC-wb~kVLw09C!M;5YY#X(XE`)Gsuw{vRgGVTG4##n_7I~2V5iS1Yy
zkhm;1DC7J4Y|WSTI)DW-$4_YkDkH$=+hsn!kUEtgVzH!-3bT7rxFCV3RuyhCplPlH
zn^ueDxPwTN_;Y0DLRHY>1<70;hPI&6
z_g^P@8#n%*h}pr-9Tg1Q*S7)Qb#4q1{Wo5nAum3B-j!?a7${j&BVT)>he2~ssQP)V
zQ%Y9c`@)d-UF&|$R7Q~`tEc2%oI|~>uO$;TyhvEuq^uCI=1*PU-y&Kl#TW9JsTeSNm&jC>{?Kw8O0f^KW)}W
zqCwt5e4Xjc9;wqEkMeoz0i
z9I_a#z~1gPGs4^)DHloW-@0yj&lQXmF#m;d@pif!#0abo1AefTHC7Dc$hv*msE
z#v}d3^1b)rdY@W3x-4Cm9QZ>*yC(0Qq*dH;iFtZIkxov7?dQt>{&V)so5xP>IO|f(
zWp!%Od2h1ys46Tkm6d-Ti$^XbB^vf(nemO__2g2eRMO^4i3BFkx8fU$q9g2b&K~KP
zed~y&cE=wWg7@*4%jmV2eP~nS!cJg5vDy2ayqA6f&h_JMXx}BWkk?WR-$jlF99BOECuj9Vb2So>w>_`+
zki9T0>Kz-=Yw&aKY}?%>Ko;EQdHC1H9r~#ojcDD#7mdrAypcZ#
zqpxGMjjisd%UUnY$=G7wPXf$Kz%yh~sB|6y%n&d^uetrdNWRbb)>avQ-+s-b{x@A+
z3WmfiiJ&cruhX)@Ovy}RSvw^IZ}6_BaOurRxpD*0XQjJc;j5&Q(38;cb(ix-^eA}g
z!@VLxpF1LYGWTZ8RXU@VHe5hYO?L^_@}z5wb+PeD%~3kjSlWMIktz4z;5<{*v`Q_*
z?V7_3VvlUnV6L&WC~~1!Ys%HNN-frl0=yAYYEmBDPo!vS81T0lGhQA^9qU9-eYnnb
z4N5x*RNWXXT_;_cK%~)_%8~MB_@LeZC^r)!8L5pMVg3#!!Wwuw`_T+lJ@VH@6Rd$(
z$UBi}j8r`0z3p9JoeG?svZ>Gd?#9CZ$YfFcwqQ|$1dw=xDxgD}3-Hx($^yw2?}jc%
z_A|^roqAn){|MDPQl1Tb{NSnhzr4X)gFCyB{SNXxkzdF8A4G4hoC$xpM5dN+OlnNaEu%;r|L
zLgc0=)xe&Nqkb>O5+0_g=b^jl8-dC7QgzbA)I-1WOi2==8HK$96DY3_M(i$nxBekW
zUh`*7)ngBvW0s6?;rl!s!-lBFtluEyrg>B)wDqPQM`>m0!V$!Dzb+_|@OV2LBKvHH
zsc~{7LY2wB%0D29SNJdasgRVD4Z5z!o)d*c*zkiNa6T_siefhd
zc84U6VNoySR`8*vo@t*N2+IqDS&qCOB-3gkTOv`FHXu&W{dNP7I^%qnHXW^z5|?}bmEVDac)5eU_+!DzxICWTCjcsKE9$40_)f{1Z!m2!*mP3mE5{UaZdxmIqc7u1
z)K{B+RZS0n$lyk9=GLnp(LaydRu(qMw!kS%4SThLLh0N?C)pRbu`r?PaF2lDT9Phn
z>CmH;VyRP$WREmAe8*;a8=6)V(7metzxO(Rr#slvJz06*L+^HswT?ij16pZ!F
zemSJK9+5$xmVPM=`I&KMMlQo=M6mx?10^o!IIB_pH{ZKIjZmXnD?&ijnHE`o?Iwk;
z|6Z=L9PKS(6W5|o_i}+a%4sL*4X0TIH#NV5*))lRz7?U{i?VDe5j^v96?{@;)(bkxc#nhZRNw(t*KpV#j@txk%r4(
z*yodLKNrA3Un0CcL4q~nGpl`3j)By=nIZKmYm>dbCfqdo(MaXu*c*Dk+cH%-j9>>b
zbt4yoaqG%%xGnAu4mpTxU@;3DP6}lh6I#DbAntlTbtGv=*l)`7XlAk6`Gqid+k%1o
z!iVS|17pN@Sn(k&A=5G%sd?m+v=ROH(mD&U&htLF@!hRBYmE@Yma>c(9fHEwbwsvd
z?FNtd#fg$Q{4pJUUmieg(e1`*(#qF?lmh6Hsr>Je5s@618m})m8zvKx
zw8U5rmI3%b%)1jITgOFA%t{vEIZG`3g(Zo9A(Y=1F;0jkqY5mXC00@3VjSvHvgX`U
zhRZqI-X)pM*q1oHu`U=tA;5$I`fnw2(X&&1ZzE`db<549M|rtKLT@6^&=@)`tT{mJ
zp*16~UOmA7iGo=$$GW@T-BzKvz@lQ~`HN8TjA+3iB#Z@{N6=vkx{*k6V!;O33jl@fFWJH^hRY*CX&
z&=oCuDbOmF8DXLV=ovqAAhIGobQ_$Vws&~{1_@hD$P
z-cBbuqVTBjSiIzS>G2qQu;9g~1+!+!F&&>Unb-f~VQ^p8&=5>E3)BVjoZKU$kPEZ^
z<@kCHNnrta_n4WjO!7qByTVwKL;&YKTNlNVV<9BAD4h%dM!8`!rysdmZ@jAPaAg#}7111nj_R?LGUkiOdiAxRzl_N>
z%=SX5Jk<88dEmHoRQ_X@w%XtvE2Kd1|AfuJjRMru*3v9JL|vdwi7Cl`=uY@|uCW<)!>t&*N}S{h#Yim4cdi=xUrs
z%hhxtt@YwrQ+!C#o8)tQmYx41&F5d3Z6mO!v4_P3P$zzKs>ux$NaY3pR{SV0l=4==
zWmmFo7<zII3ggZ=Y*?)lbRI7
zQWDAQX8!x^443@vZy$Gf@;{q0%MJ}Fgkm*+EVf93jz?WCYI(DybGnDhB(pZn3|i6<
zi`VuSKpA{`J3BqvCMeerqA=LU*z!hFY=i}8ARZ5-(}j9<`sgNmJwNzNslbi7R|%4
zq>bw}tNiqJ{1B-U;Ba_5>TYkkZ$D&PfZ$=u^igyv{}-l)ME?b89n;qAfBXuMJMseZ
znHQgTQQFOLe*i6x#)bn?aQ@yZCo5sngJg>%_Lp5sL}QKd9*I6~QE2johI?fye9x>`
znLR|<-E&FnL5;JUx%w!2R6QQ?<$~H*=YMm^cw#eKNkV&Tp{#D`_9~YQCaH4NJsBD$
zbc%A50xrr*)fM{jksjCX!ePr=>Au}8Wk<(wQ$FZ
zVs>Fl+sDtaV_pO0)^8()@SZq6O7xuh)ABq4lUQwrxdKfr@j3CI$}N{bxDAE00aZeq
z1pejwU%M3vBYlndhMDeK2@^VceY!#Aq#@u}*+S&<WM(aPjoflcCOIZ(
zH)if{q9R9!S7FX}v$+Ivq&QiY;YKMukhp7Jm5+?7p9>*0({maL^b$pWXE(3+{dpF9
z7=M9S@ei}~a_2%YPJhZ)RLg=*O*tMn{nPOmrP1)kn$vyT=B9Dk1&%eUt3k~rA%xX4
zjC0G<3!Q2rrCr{;Gq_VAmu}A&ZIuYd%WQ{(mX#znuV&?bSP$g
z8C2MwVge@Ct?SEYu5X*A0T!~Sy*sD224os2+i!w|6V=u=y}*tTTaRvUa>lwy(Iu7o
zQp%pI9VT)oI?Bqw^+LEp`smKQM5A|k#j8mVOE=U3m?*H4B%!6QChN$bq_Y`64n`@g
zmS?7$>I&tip4ld3%ZhV*=2)3J;i?MoXm$64wY%CABH_UcH1`tLrp
zHzztLGVDNvH}AoNlr#|)f`jWwVF+uha?g?dcDpsMV~CJy+GNGx9Kt9J4%Zg%d0vYzZ`?gWN;jZ
zo3ti?$C6CZfuFUhm+|p%lgf~aV+koQECn$+s*pA<^BjE0!IYtuFl;n)9b8zQ3fcDD
zQ-S5~^a)uxXuGtW@_@EOwXqej~r+)Mw@BX9
zhr$)82ZNWr49`(oL0q%I%JOx
zqJBk?%a~*8AFb-{q$;)W%#bYOX2U_FsWFE3Th}j1En(T0w?QyrS^bg%D_I64q_$^u
z#JgomK>B;l7KPb{!Z(h~*M(WVH)nWvcLa2^d
zJW_~Qc@bDvDECc>@(My_u7ff-`tf>pwJ1_-sg00^Q+y;CJ^ycXlvQy)d}6}g0RGR~
z%7nX)QPQL8N=X--5D}$q3p=Ht2+~J1dNl`{?M?zSd}+jBR-s(H`mzwpa0Vk?#Oh9i
z;^Y>EsU?AzQ~Z}o1Oq?d7BXRvJ?j@jXY9@L)HzB?!KT0zkB#>*G?it~KNN(&UmUMz
zbpi34n{>6I8Avd%#akJ*~?a4j5#h4TrI*A
zQ6dIh1}4EXh*|LWsdm;~6X?0HliV_mWp$#~@mjR6_kmX+*Lk?SbOeaPwKK}=>rcwX
z(Vxu6gH7wOvETZQ;)Hq6{GmVQY;7hyZBfG-B*mAKSzlHyewIStY^kX5xI!6W%Djk|
zD~&E?P|4~=`KNZwnVU__9hm|gfHR|xNG(m5@Cc7k8D^>ppcR&>s>Dq-C)4ICFoNUn
ztj{H&Z5jlu@T3$5>s4e^V67M^*~CyTRoEj4%{wy)W2kaQ-KR+;y;TjYW%gbMllv4I
z<4mwCrQ<}lk+0)R{iseLSHhCe)WNu*i3d$9jg7oti9;0#J>?OdSOE6jtl~@kW=6Zcc*2ERN^Vz_85+f9Vj{;Z*)_zM4S(6-MjUTj92&|j8;fn
z1Cr_lI~iats8NI+EM>uB+24VomBhukJh}n({<;cDxcW@7FIRciGJkKx1B4Ndk+5kR
z9ocZl*enYsP`q0Wj~^8aj`NSvSTQI9&O-
z^;xQmM%JuD5D)wal!=iaVAN1QpyhD!O6#w{CwW1-Up+>J7Z{wW7Fdhe)sUFI
zpn>YH5}KVL4$E)d4l?+Cj0xvi=>vyCC?sV6v9kAX$5oJn_*$SDOZ{LXoBh)2$U-#+)u*L9HF^8l&#K4D45Z5~*<$vlDLo9}i`G^uK6H#0oK{!<
zG?TN9#Oz+u!@Pu>wSw6s@=xgCMV=G&|5=pgEv*iHYbEOaAvHD&Wa^NCbbx=S}E}Ig;G1LM{n9S(~MUc
ze{Tabae_JA+(2cQ_F@XTs!429we>n{rHfw8(?(%!eFJL6%j1P5T?nNsln0R>&3~^4
zYpD;?^`I83EwR1#pb}!2*5u8(d8c6E(bLPvcZCu(NLOmBxe!95eG_*kjOzTR#eczh
z{lp(Hj;C)0uc73COu2MND!Ee)O=Yq$^doce8`kvx`>$fj>I(bo2mbglylv|c>q(CI
zQ-Qf<1&rS@lw}2ZzMx0DyfB71{3pZ|1-Hd{;tLbD1mgCV8>`
znkh1u=?hsgQ?(TtcOnzYB|ztg;4spis3sg3vOu+N%UJ70yJUuRa(-Lh^thxl*!>Jt=0c3TKO7tq{f|}!0kkB9NNImsjb
zBqL`~>ndw_L0BW+rchSsN=FRY)Wx!_LYXXX(WEL~>p{i13(rNLM9GrWl%{Ak$dO=S
zDk_8y;8RRAo?cKjjil;gc9@V!h{h6?YZ-mw8K0~vk@1(B#c8R?Fmy$8H1c-PsM+62
z^akIe*uYq-F}Ie#@27nf!D{AO&Uo?muiiskcJnTpYsayu3$UU+?vXN8fQwM{T*sqU
z`b`GU-+PaO3if{U*5BQPo)cf`E%o^Agt(3MKl2$h7^R0@j4YqP(iAUO*Yn_6CyDo
zAh$LJB}Vk3GIdq52jF&z7ZA2L=ohC|&>|^2P(UfyQ^HV?D_>;dUJ`F&NR)^HcBbv?$$NXBccRblx0@>5>Jwx0rlzZ$trifeIkl&Z|EcCY5n4r9Bx)uCdbBu*_q(
z%ro?WoKMwaw^Ox2%L)v?t-P8#T0-vm^%eJigs&xh8obT0ds|QSWyk8xuhHMXXFtGs
zz3dXH&8g$QptDm8?9Dg;FBRCJbneU@%s8w>)m^olis`^fr=pltNraWbdNn9U0H|p5
zq4f0mh$=;974tW!tI1w(W9iiv$U&fI*5gU8p-BjjtDpHrn8B-14a
z|7Dw=YCwlkc|;>gsi*=KP!B*76iZm#T-Dh)tfh$Oi^ls>-~Ty&jOJOHcEcg!hz~=C
zb_$_j1I9>;xIuP4AnS@sNLp6SwJAsdhyj=XF?d}3dSvT^9Hy~V%W_ZtlwjwVfho^G
zfe;(c++UDCgO++uU0Dc%V30N;#kOL8kS|%nOw;7&6No1I_L+6QELx|2X|O#LoGQ%L
z1PZEMP|57%hIQ_(^Lbo!DBAZ$`$LL>{N3RMR0Ghzf+-{D8Y}&aJz))E)6W|6CVSI2
zjFI9APIqkxH2C1f>mNj2S^gpJG-vgIlqX~?Uceo0qG@3qgyo!Yf+)>j9p{Vk5EaGl
z%f_>on>~X;B`3FkyoAj~`=8GJUhyhr0fj>J{9>usWr+%i#3Om|0xqpSvnJ2c07zu)
zyiV57Sha~OjBR&HmqXir*N3+<_w90d|GC@U=wK@GJn~6p#&7Xt{BQb_U)Kyck{H{l
zIb^V-rkVEdK-$T{<{!7A(u%U?9H;NXl5PRm3
z4GhE5YOR$>iOvsuz>hA2jBdVcz0|mf7Tof9V^J4EmWqqHquTF9%hj#SHx+pZMNMpt
zi-z#S(XsQMuG%acp5EyRD55pB5flth2%OMiQ|k(ljUEi)O{a!f%G&X35i*Tp$aIhG
zbsjb1#mG@n*IEfMLW;!!vBKC!r2K6;E=PXq3817p3ED~7M2Y*~v|g*9Fy5|qEpBI)
zjtSU20mGaKe4rwvhCvchac7i?UyQ2O%N_XXK9+{T29~(D?S92;ZkDe$6+SI>&RRb+-kS>?-=;`~3A)j(
zOo1JoTFyGTZ+z5KB30JmGoK(i)b*C(IkEamjR(Kr8+Yb7P)>6rgJe{Z85`5nAHb0G
z_W3RL`y}e>31&xwg^^Vjia19~&kTieYGSfTnIEn@Jm?Cb^W9Unme>TVwRIcO-7O?;
z_$uZJ;@WbozhKzs#bu6AzGQUj?ETrDF*S#`-xOvXu1iImIJd_{p9hsOCNKzOKtlQ!
zt@Yv3Q;YHApNp@~C#qM@BUGw_jPjC*`Yt@OeiOvJy^ulPwE^6|^UYb$+PXlhG)grT;Y^zAqn@Wt
zm>Hy268Ra%Oe*oxogru*Ns0QKlKK;T?EX6e3U+;$Xc0!Trf6n=P0=*lY6llcr0qX1{Z;zF^gva&W`i)Onx_^28-P
z_S)ubpEVH;_b`FTW`oiKr;XtSKHOZFkZAu5mCn}>M&
zQeWx^V&3Q{E+z-i^xd`jF9vLOT`}?f8|(>yd+dq91d;C62jG_OT53fBm@L|uwsRA=
zJZoW-s#m$#l4+A_Dg`s_yTo*xyTJo{tPX9OfEoH^G1_DBmLdE^2!HyE%t)tnp0k>z
zjsz$%u}i88R$}TxxK>gUTVctzg78sx;{4E3QvkjMDF;+jl?!sQK{rnnRuMfpZCMCO
z)da2`Dz?pg+OTNp_MU>7;slv=F>kv_1tj(NG>sMTONO&?vtY@bcx}Sub_%`*HJiS$
zwO<%!)cYARuw{FOnlZ7769nLNR=VQj+BcK39vbADMpE0$Uwwpj8v{D(c3W6O$8
ztK3Gh`r=jKnnx@3HQ<_r4K7ud`_(J)Hob(PA3x~#rC;v~A2mY;HYJ9gA=LhFe08W%
z*1XpN@qtTW_zej^$Z#867I|A|^EDR!H>g+OVb(dDv++Yh=5fW!52U>(gI8Yv-+L}T
zT~GbtM4f6A#>7;Zw&&J>I!v0?S^;`?5lzHKV`7of2B7ZUZwf&rpvxAN-)JnyV=kuA
ztFvL5JB%#@HHGKjst6nSKn=H(Zz>EK6QC+6BXZo;DbR?LfJPG*Ut(|k4=I6|wuG7j
zqJT!48%aX~hB8q@a}#faLf0IfJVSzIAziFrdL&DI4WtHsLoBuLd{`h&Nxe+yVD$uU+M0q)^!bekhWwb1-<@_hKRum8z
zFh{NVukfY%&xK>wBr?#WL9OL#TPU6zx5OTeMz+EdHoAB(g9fscxDh!6Pm)e<2~U!7
zzg<(f*_{j(aaid=5Yx_KTg8MmGBSug&lUNP0k)4Xh|v1U8YrkOKIMc6R3m9}p%YN+
z(o|;ym^;k=-`HVuALU<#Ioe@JE$oJA+093}TQ4h6Y@QAZm1FwE2WQoTf+$x9zv;Eu
z3KzO)`DhE)rg%sN)`p%wj!s0&W_G!uBBFs4BJqK24xOlPKEL{?0VSW&8f2e^$Umtk
zF@Pk>+Xw^$G&B9zN5zN!((C|JzF9@b83yEarb(d&5nqf1xAw36tJb_di(E7$_huoW
zjjLQHY^w5c{ZVoU8f&GCezZ7at{ZJbHc0uIWR~Kp?7)QtU5#)*I{Ex{9D5UFV@|@t
zGd&6E_pa$UX(soV$r8^Lw>cSgvdmO>qO22=G7Z&IY#jc^{Gt=};`Qq4V{5AL)fA=l
zarZhc&7J(f$mOw_>y!bWLoU1f%@j#Iq$~T=TR|&vX^wfQj0*-Q<)^0LW8e}3j?!XB
zB9_LCb?)_{e`3m`$IBh`NHTmmevJdxiblAVjzzQ9Z+sm5n%GNb2M>M8Z%Ut>m)Cmd
zFPn%s)|n#{riu9Ronj-rON*G36fEW8@Wlq<5rz44to0O$F`!%#5+MV=#xy?J&fJK5
z4+C4tTa9_vLTPQggQ9UCjH@fL^0E<1ox52NtBiFIUUojlS}^u48_Dt+p1S@)4Wz8`
zQ6AoL%vk2Y!Ps4QgVg~P0&3fv8fm`pg|p$K@v|m(*$@Zja9m!&!C<*rUW8nOZuL`V
zx0+JPosig__J4P_$o9Tj(Q#R=I8&dcR;y;37LIzk)0AOp)ZN}*4zDmMmfgE}rha|5
zf6wt;HM`S|tMB8R8ICnTG;mBLSBGKp&PFW3EMw-G=d14q;X!{iw7odU-Y9ARr+tYG
z7d+(XPh7$?&%BUa4q25g3GF@mm+q5;ojs#mRCmX|kK@5D&-PDu
z#FbD3fsg+TN3F>>{*8ZnElhT`JnmJ_DU-aj>ocBweeZi0jl;`p
zRU7Maa@>wWpJLw)7u+Fuj!xOXFq+^~-6b{k*&LG?$?J*lLUr#mGuL*uxq6WP$DZ9E
zMAxHhH8_>18*#I1o$39QW)=atHEAn|E0jk}$kS#)(nD-sUauR;R-xQ~G1_A5MC!;e
z-7a-pH}H-8zIMN}GF@o2{&ST~`8T1*5X-IBOb4q!IT@d4!vuFDaD{LigZo|a4lE)b
zRw6hK3}ko(IXRpUEm3t2-eCp1d8rpJ$o;eg`#qM-6dX61xA)8x?d~J|7X1bNLd!P;
z(b4yP4b~vDO$o{T-}`P<{6%r5>4yP$0
zGHUdL8&JkgX{3ux;{+8oC{k4+7%(H;z>fKz)s7wnmO(%fUiL=|TZhJU?T->s4|gX>
z{L_CDZTQ(+u1duJ;4!08LOB$#>sI!i)V#Bk#W5n4Dow(}G2)?roMJiUutR!9XEBFD
z?eP%C-lMpZaLR^JyfqJd)1w>4azm-kOhPkGL+rhh0_K
zh9wT&!UR>sSBLze$?ah@l_dZBz)iFyX{+1$erjc7W7rj0ysoumF`Uy$KJG?7qmYCD
z3oEuF1RhZJjta6}!>P4iRqD=%QfSXdQ)urZln6@GN=pmcBp|`)TrBG%)JWT_px+=p
zLJ+hNg;(_h>_OsyTZpKL?#em{@n#9yMcyAkzZzqM-|(P7TKPpfIkgani}wAgGn?_g
ziR$aqTT9`)G!F{%s=>LxkUdtB4?j>&M@y>_nvRG<&t}#^+KE;}L23A5BEp`-g~f^F
zI2OHrbeOX;d`QM0kDYOJ95I(Alhm`sS|2sECUHou$B*LTLu6$m?&qCoq)j8M9yVHY
zgP&J=Pj93Ve`C5L`>EWL>6Vd-=Sn%8*}}#`k9fnpF)D{~)J#1~-yBC&>F7v_TYned
z8W(BbR6BLFC-IPIPwtp%VPP)xz%Rs!VScC(<>Ifj%5*|CYR5;CA==N26d
zSD=ebtfwOL|3p4eBLC80)Xzi18CmZln4m82#>L^)pzGu6~M{
zGV1KEQ}3hd@wkTJ^0HS`2pzdm{IH0#rGkshPzSyWs39KI#r(dLtrc}V#`zQ>Z-f6|
zsDrMdTycJxJt10A*Cer~(!#VmtN4+tWAtB~lVs}{>4G}iLz86X>G-*#o-x{rO#%ci
zV>GU6X{BmQS3;=AwWYdXwSh)JXQaGOGw;2o_D3A*MKJkhphh3P1@va%lVTh61&!^n
zVgNl-KS&7untxOc_R%4LU|f=lvO@3_gwH>Q4)Oncbo2|qYq6t?@Niiji$z2arE219
z;8ArA^VdQ#4TNuu(r=x0t$uYq{b8>lvgW@eKIpeS>PT6&QU4c&N0woas?N_#f`%(g
z4~#+T-!wuYvt}}M)#+9FrL+sZty@Iy!lN^|U+$1*HVBYA3>O<1;>IlaSg*DkXi
znwzU%OnL&+WMjHBZ{6Fq*!~<>95q$UytVuwfAie)wID3!hcCjCVAU
z+Gq&5ATyr)^gp9cUz=&WVDzh`s6o5T#<=^bLar}3s!wPAB`*@neEu(>sl$wl_-GNr
zvAdRF2`VLcwSg|G_2Si~v*RyRq#EJAm5$rds<@1Q-rF)at@>HxE3}+;AkbcqvE~*o
zk%jVQ+?nMkKxSLCbRV4y9hKTAmpn3142&Ac`l0YZ>ZC79`{>DQw!Bqbz$g7G-z3myofb-`+|6Z){zO1?V{xys3M7qDI4K~UXQwCy)
zKs+t}-;PtU6?T6u$$8vb6w5V}?&EI18Mj$6sQR_;+Ug+GS0L@Tn=Wb8iWViE
zp*?q3Q7kPmL8t{&ZK^3SsWL|yc`PebMW#4mWeUXfi@75US{vWl-F
z&m_I9Ry9c^K0}!-U1EOB?wsU`6GMMvod&pH$fXN7xVZT9yDPS!J4m^IVvnt}jWYyN
zKsUiQE~-07ZWz+>2eJHHm*-o!kUteL=|km~*-6co_VFAouvCk8uS(~(maExI-M6c=
z{kZ;vy5P>(a1{6Pb98{cUZtpJiAgy`rYj8sMP;7vJBLdtq7t9%@#}g$mjm
z@aZlefAGfq7-kSb?sH>zlbZp0Qcd^w@~t>tUj+ieq-cqIjZS9KVC)5%~m
z?t1iw0
zmR%f%Cy!q(@mYmN8RIut4^evFeycfM?#!J@-XBhxIUrN9Z+Z_Kf0fM0ZL^7&W=+D=
zVNWzZoQ9ITtk)GCGr0~Cj>T#OVK_qDk>Ov;BKVxgx*-3ZtoRbz{;h%1gPZnA9!%;H
z{p~oE+$}B9@8yBfzLL->M@f8i5EQ>Mf+gT4m0aK@2D*@AT8up#fwAc`Kas!RI5l($
z7$t61Co^$Ybu+r=7RvP@m_n!>ma|J1ex)=-_C!u{E1FfhQI)>cIi`7T$a$N%py0%B
z(&ZA@)Yv!!yHUmWbR-a6Ahf8z&Hj*AH7QG0djMsmkJGKlTZ9zdVz%i5b)m{j-5&x_ITMcBIinDhkg$=O^4oZGU0
z6Prp`75x0Q)=*QxMT0!c-Cj@t&ws$?)ry)Z#FsW-DXKpPCK(bjNt1wc^;;rCODbr>
zqq1y^MO>d8U?!6_P=?oXHCj|)T?wO}q9Yu(^MLOb(Q}XXBZX$s#8U;akTDW^4rds@
zL@67D6@bc!af##j%vG?zS$_=IXXAl4b
z*nc~QeS&!W-5?i@C&nm_miM1uj^Z*TSb^=f2=I5?#%I^5G|Br)+Z
zDGRW0oVhyxKdilVR2|#4?n^=fA-KCsaCi5KySuwP1oz;sAy^17ad(2dySrs^+l%>tFwB6z_~d3^a}jcUrg@PQ+9B44te&vjQB)TWQ$v
z$$;U#@h@$MXQwASKdVT9;Xs$GpT2_vX3EU%P@pc_42Xka`RZ$N*CL`;DQIf
zCD#e*;KwPy?*~(h@8Wbxn@{gqNp{kab5XF({2OBrpOQf!OFrua-Jy&rrtUpCbSFs3
z0ac9BiR!)zb;)Gjb}Y2biz!-+jr_S}Vs)HFQEZp@vA7_lst0JvAv7Lt>RH*W8%Cust|UO{nC^I|7~ytPRm+H9dE7^ZD0SJ
zz_z?qezWMH2q}f9foM@ch^Y=l6i|B;KJI1GO@PJGnA_)To^5bnPe{VSDvB2V-iqU>
zHrfqqn}&V`p=|^&`l=(v6~1TW!o$t3A<-Qte4|FY*GP+(ek%f!TPYB{Aq=w@=KM*L
z0IRAfz*O44AS|IVHy~s#GQX(@43%<)T@KZGXaRXbOo9+fA(E!Jn^GOeY&P2!USmW6
zC^J2XGS=6z6kA2>s@>uWD+a5B@bIEhoVd=j;WP-l5-{MX9Tajzx;F{9M`&iDsFAVQ
zj=mdIK_TENPI^bp?)TAJdRR_~7!I>Hm0$gP-7{wE8C#2K6JT@2c{^C&KU)aX-P1DK
zkQLlimPJie)$DYA)F`*5iP?~tEJlD7hPc>n=poZ*Ljl^gT+^qbdlzAZOiF)jaVOE8
zSy3Htre>iwj==RrCe}RP1cD<_$h69F_&AcyR8Q|~TI#UoJ;~>$*Rb4vp2wHIQoaSY
zYhb*+jbZ7A`J50(=I{N^>CZDd>ue=0wpX5Q!PoE(C*!}iognw`yfrdJCf67+Ip*)s
z5pCxUs!ou)B;n?ddL7Di;5aVCk)*jBXWRoWgl|}~gK!#y3{Tr7T%&~Nqn2T2ek~64
zB1LPB#5I!)n&OLWHT8HT^63(1;yVSFiv%$pZ8`g{c9i$-p?|KayEhmo8ts85
zI{t>~jFd
zqSAErUiLEaPJ`2dF%fs^7ALLkysUgsL_M>6au?Q2BXzDyoHisPv_R$)s*GA`_7@|#{m4GRfXb}hF$z`+pL&4zfFI}gOncu(
z##sz}R6y2^B-l)W@aKjzGxC%k85xcx&xfu}$45FiO*X<>M-OWmbqKR3B-8pFH`}H>
zn5`3%TpK$Ji41y^b#1JZ>0Dv(YS#qDWosUAeArBJ3;m1FFEoLQa#1qgjlhBuyQIEh
z{Tw6ohr`DP!GiCvB^#QlKhTsINqwP?Ag4(%%xkBP;#kzi(&8%kW&-XB;F1~|(;c)o
ztc;bj7o)5f`&AA_5XaKHEty?7D4-ZA_N0PsU){h+=J_>jTkmJO&o^X5KUfiOGG|yw
z^x51bd&3;JnL3=k3L=xZTgbI8LESTv9x*sQC;K?EZ6;3qb~o4{AKylu9HoZ0`0`W(
zw;M3bd^E3$3|8;KFxe~Rb!y_k`SEuYy>xKD;wQdT0(YYR63No5{BnPG$y?52FN!;D
ztc0H9^kAH_aXPro#h+5aN{Nt%6z;e)DyqUi<8ed-8zuQ>vFx2#4lL=f1$Va03bnCH
zQ4JqEN~;ek@4`taJk3Ol%1+;mguB|B?AjR~m;_>Ent%HqLX3gwME)9+o^l)8FhCp~
zaiFBug-Gy?f2%7Ue&rV)INhgZ%h!#4Z5yWuH(^0x>vj6
z$l9SX*Rycp+!{kVxsi|F{K5#0N-;T@^w#9$@}^0~c0eZH+>yru$=ff=NUQYV#`IZv)+|#Wfo_H`c(Y@j;jr
z{vl7NOhs6zz}rVe
z)8Xb&GoUMgnQIX^-U7_n%Nz_JV#tNgTKl&b8lJ@TzYRRgzI7I8XGZdyV2(DhNCPif
z!a2rI;}ULQKy9HAd}D}hFTxPjM}u_`zc3cnuPy)7ev%ur*gDN9_L=>8L^|0cyy_7n
zGzF0#PO2>XlfcMp$w%xgq%^-D-Tj0YYIeLW{OwulKyLGB1F>|I0Q+5eq&yZApUOPz
zoh>)l$NV1J$;-}^KgkNJ#hz)XN97Y^p`Qt}EcCdz7U$D;m7O6Gc~o0SZozhLMjE_3
zx=DR|ed(crQD+K!2%#R#DgvbFfmJmc)f#P;(68xP^SQvJ8ut
zwH3$W?<5K~-Rw~v(cHen?rB-8`c%pY8a1aini13H&%^l=1v+oONg-&1RRV)}DYN4u
z3z+K458EIXw=g1RzzI6muwo}2KMIx1V~=YkYj+7g=8edWl_%|kqW>`3o#L^SZ*M#=
zAE~=MPaD^5^#dJTSsu*t_X0;~r7zkC`Thy};>n2P(OUCPG;QkSj{C|VO8gZ=u6JRl
zpX;CyyjM&SPi>%4ovqB(hpr-b+q_{#=J&d<@_i}q(EBfdLurp(9tSv|iI;d5a_OUa
z;x1Q&J)sL2&$hM;nsO}91N)W!OdQqZ7nuBL8xvm`(Q-1GbsDIDTG69)g4j)aZBvx6
z4@!>3c3(4gRNI$3KiNx@{Jik3yI~o4R_30St_j8WL3a8$&YO!{coRJ<-N64Dd_&IM
z50}ZKI$%2f!v>RRkMT=+QXwX!r9$URQ%*In
z(FN=ss<5PE8GEln(6_Q!M-QKrK=
z4&mtjG|a8lXIhHm-W+1Mz@LxTfbCF|?CBG)ucsH)+^RD+g}He`2NzO1q-kbvNU4$B
z?cJ)4#a&K*LtsKdxx6TE&x|zO>ws$iW)_S$J73^*bCMpH&+D8z8Tp|f^~5o+i)M^_(kq8G9ws8K>6IGj#@Is9q2Ec+NGDdu+k
zn^Mrrc+G)HT8Y}-T0=U$;&h_oEK6nP{sie*O3$>SG^lv03SN>U)7z{Q5yK@E*wQ*M
zF)9HJ@a1A)4on3lhMzPNf8s5{5dVUHrO`dXctL6cc_ZXsXR3?txd>({qmy{e1sZfe
zsL6_9SEf1A#?sl?1H
zEiC;xRzyZo!7b1TXfKhX9WZhXbp-@T+KQkI+)93D<`)>EgR@oGc^$0e-P;;_gFR5I
z^sNUb19o?u`rG7jb>~jzBXu$w6%N~=wC~_!H_7TLMkofa6SQzLsC8113_XFAfKjqg
z-*P}KyZG&y^D|s=FdmL-fOB`FFR<+!{j>{K`jv=_paCNv%KvG&XvFf>
z#&nxP0wO%P0m7M)BVr)p+
zflX4B0kN@;z<{X}QY3t@`7m2sdK7R9@R|?jNLEye;91aK@Lu=S^My%
z+8Iys=-Ojs23t4d`oA&EZaolCLV;JY_&qg%ljn#Geor(oPSoBA+24nnkbG^Um3M&+
zawhrsAcU+AE_aabMfWe(n5O*m28YmRU9zN69(c*=kdu$Vy}4B+>a?+zguke>4&+C0
z!;_;%{)J#wU$W3F_X9$wes7+wW}I-^@vZMKX6KRY^)78nb4W`56uk{FQfBT?l4L8U
zyE|Fvw1}5hiY>O2b)T-@o6c?}iPwbLA=Io3R>dm1
z022hF>7Gq_ng-=AASusMvto%8!=X0J=CtaE_7~Tv$?B2~@9-J-@
zw+#E?)h@MG9X3-3?mUncKr5k4UCf+nK8Ddg)9}a+J*Z+)6E1E})CkZomu*azFeXtX
zQ^V<4z=@T2bzG-`*v|EdOn4LVOBfvz&BMQjrv&M#5h7Xc}ayf
z0A`CaC3CY-Sm2*Rn8~!TRRecaldBZR$SNy5ftkNsmsfx1)Wq->Y`%~1z~!s#x3{p+?JTU=y6y3@J-^A+rX12*0lEP
zoW_KYPOcZLE#3a`s$vQ-dq+@^#1L?G<~TeGjEi!Km%DoVhh9(=s;QNSUnlLP(L*V`
zXQ|=vHTg0uiY}~Nosx^_$|0PR-L!SC&px=}8Ag`y?iFCB^fET)~>b|XDZeD5>#(_}3(
z)(J*xrU&j)u?n9VqSK!p)O@EMLyt|x7c`972?ZA-lG%Z)z0ay9U9poXY+Ss*d}siU
zHZkX~)a&bLZq=esIrnYjp*^QB?-AQMJl-#b_!LY%aDa><>Y~s}zO4$GlNK$$d-=-i
zGR9FsW)zfp2*DS0NrRLWo#?9S2<3bKl976I
z2f?@P*wQG_>h&7c>#eAK+~nOGWPC*XL60&B0<(O@J16S0O?my);cDtpkCmTjDZ$wC
zGK%lEb+iO?s$BY{ZX~vK;wB~EB4?oif3pff1^kUC2M_aD%`UiKsD)u$!sX!QVtfwRS(kRLHJ$YpJUhSkcCU|~
z*WFI;ZNTU~HhQ~zs;3RYw$@ZY=;)dG4@bf|RHa0z$8J!w<0La&7GZuyEgu52Y;)i7
z^26ZkEuN;@OBa3m@$)Wq*uK5}x&>U~{=K<()#=y9a7Ak2xV=Dvf}|_%1L=m8R(Au+
zoM3q{U8XU#620Z7h)Dt8QgqXIZGq~N*)A99r-20z5A*^pf$I2a!+36d)K8iaVj##g
ziI%qtGxYq)nO3;oIrs5VoeorKv~+CP1(a}hmqrjYbJTO|L1;tZ1uKPimtzq7m+Cjl
zHp`1A>#tJ~X{Gpr>WP$fXop0M9L^oM(kzlQqNwQ@peBsUaPT6gsOxc(ZjM3BS}v9t
z1-{gWWG-P1rh2Q6#X=#wy-{IjQfV^gyS
zW@_@qj4z{(m)E_d%9qtvq5(K;CeQ9$2$Rm_(%$4@_s&K{+ONXP1ehf}RU%Ikb3u;*
zS2?~W>NrH2Dv*=v!Li6bVlCwNJs*udVFcT27_T{vA4AF-T6F@p#`Uq${DhFchV~HJ
zV<955KBv_+I$ab6UsTI|yu0hRz5ZbIZu0Zk8V)rb0gWcUHaR#=?Ok0u4^oQ_ZJNrIgpd`*hWg>R+7Y61L*EqfaOw+V%n3SSfBYIrl|#n`M5pc2AC
zI+bHkec(Hp3I)XRcUf#vu|ABWt4E-EddBT2)ZBh-imt;fBATH+y{6RHxdP>Lc{sIN
zO5JMGINK9_CEIQ-;*;eL0t
zVSvC9uwo2zCST(?v0V<#Gq(3}+DP2PWg1U4pt3rjTucfzl}CaCUb
zv(6SPT#AfmpTCYpljO6;{xTZ&24Un6JzSH{)5EGm)5vn@`|PA|m210vg^%C#D)_mj
z(`SsA>$HkoR?j#rdF5tj1|`^hW+
z#UVY7rnFDmO~Y7@pBDMANtgL6TE#u+z=-JuCC8uGTYoEE6-B=CUP0Ja`M_7MlxefG
zFN5G$KNI_tR$~^Yp=SCB~
zW0nss9l3Ri9iWwz`*>vN>)}qhm}@p4QgxW4jyc<)RJ+JV8-`MymHx5{`1$l-Z*FwC
zf7CC(EuDrt?`E$ysPwGk=6Vlh_UhohbkV6hVZCFpZDmxv_>Ey*QyDPipIDcKt~q8)
z6SImyddWFsktESeP?n1%bjz?bm^JWo^P$Hw@%3fCJ8ks~pDRKOvebU<_J$uvMxs4z
z-Exz=Z`wUcY-(Ll0nU6(cI$gnG?*QDxLt0Ypzgo~JA#8A78B6jb$OmVw&@MFh)Lro$pb%=}{
z(y&)v&*%v-JO8jRRXPIA8Ij5;F20kWC38zweBXsyhg)d^+Z>h#gV<6@8}r1G-dYSi
zZZnE@={qXKL_SMo9eItNdDK4h?=$KmYvS&|^^-R~satj~lo2joh%I+!tcpPOA>T7n{M;D|
z(NeOQCF5mYWlY_qcj>^kTVm`i;!U%NIiFS~tcq(ggO9q2DeA~Isq#kgHEDVj0ySFL
z%mrSF@6J%)7RgDXg9~=vS@&G5&DL<4PwjoYt|dNhh>S`Zq)l)vy8a~E@CZfgad8I2
z;#;FO65ENV?b}hsh3&|j=en}*x@&qZ^Chcv-&b^+G5MNOIai)MJdfAnZvfIC{-M?W
zowxNPO)G5$dvvlLUQ9+|0SYNaB(tfw0mAEVT~o#pvuRG7F3zV74xTwCcHW?qM_ikt;!596wp06D-2gw+sd8K;m2&g;XS2<=`wN5*Ly&@{Q1zWm|P*d_SJb@ZtVU=KuE8$fa
zm1Q>eakDwz?CkPIaDGiAX3XYK1{DEjJuTHK#rKMO>58e7i|WzHY6p-VU$kKkX@ysV
zkj`?je;V2jAP6s^fr@-hnDfd@Ik6On&-P-U<4O1|a5rCdl;iit4t;oIP_~NFvl@P9v^!uSt!kUHL$RH>$dQ0dX;fcJf#AM?4Vnru$L>_lSjs
zS=x@tu_q3fvX;NSiacr$E)K3qr4yxIh9cH(jnwH$qP(9M?CBmT<5o&IDEoytfyAuY
z*Tg2__&?=lhG(xDwDv&J!vhCire3^HpUHt<=ZNbX4`!{
z%?FJtQ?tU_CGlfWO3r06GIW}E#idcVB7;P9Py}1k(ejW0guj(Ey6$m>mpyE8n@Pd;
z(ty9rHK}Halx>UDd!oc6+K6~m9nfjnQ~o3Dd$aHN@w2`14pasNtQ_a#i0g#u3O1*F#d&^>#ZD
zhnc?cV#|qLgZ0Zh(|60m)qmv@by~KyfulS?pQ$Ca7m-z!in-e86eGk)<4pGIl>}}t
zMISVu59mI0hSM*dAP{dI8CBfJPnI`-G4{)qLq~JTHLt!F%Zb&>!hZX?v<
zVIs$lTg8;=UQU=kSZvR;CroOm7f;|+g|Q7+$J$#$j9E9Xa6BKoGtVzVwf!&qc?1$?SCs?}UbQmk)8}s&QUm57_cn0nZ1aH>>ExUou)0ap2)0Ee`$K<0W}`x{n{>QFggJ
zvyKI>!2qu5>abz~lWma#H$@3wR
zxqHR)FVD7*Mz}H$PSgdMHG9C^5wuda;;JV8k##0NDFaIuEL7HfP%?m)%6)(_u-2fW
z%04SLiFPljo4u2&gK{Fb(X8N!bCQJZwS%*40HSkA$l=RYbn&BF0vKJ=!fp~*ZVHqd
zh=>>{#(1}fP$_R}4)o|d!D~`%NVUN#femtLY1zJ9td5Afi0d1okm|o#`h~wyuPe%c
zPyk<=kROpdV}cj)s#c=}DlD%yq73S#6QT>hS%i??Jo+m+*IX87gLQ~
zKk-HZ;1t%sIAy|x-M)lyQG+pp-^t%=n|VAiKT((7oESZnAGX}2%y0nhJkT+d?rZfZ
z&wQ-OqjxSp?|lR-l8+cxcsq%WVZ;{g65Zs7HC$=VNHthxLLXcpr+Cb{z3L;mz}yiu
zXfos#rR_MmxKU^f>-W$sYqU>NK06!{`{1ePkdM
zz-nTHs4nyTq{RBFJ`;Qq%f|j7Q=fIOs*Q!;f2u~oh!bGY>$09S}FR@BguFs
zb!EX&KjLn}1a8$Aa5`na^4>Qd0|BSxzlv@F;I)1mah|3CbDx=DYA96t=&^B!X`5af
z?ke%uIqwO-#M8hxL`8Ver?;u6gtFCuP$Eh#mc>jB>6@dGLr$E{-1A1Gg_w?Q5)Ry)q^T
z3_|kUMwyEBW&=t+5#FV?WdqU4T?ImOPdCNIK{*=j&@xshK|dn-qn@+tya$4{>9cN
zV1TSwLV?t4F&T=K9z6F-Nk+v@@C@P)s`v78uxnMp2GfplpgtxV8)_G-)}b~yl|sY2
zIVFEZh;H^;I(lb*o-95b*z*7l(Kk{Fv|iw&V_I$MB16HW=9_W6w>mE4*!@sh8Werj
z&7Nma#02}u_Sz4^3C*h4OwbYOPV~ekSqYa%K;>Q_wm+WYY(rxn+h&7Wl5y(isdm9d
zT71g-iT{+7Bkg7054Q8Q#|@HomIR{SU0(X(D^G`Dy9GFcI!x
zED*qI#)L3_vP6#A*j9aYqbui}j~I%+HM*)p6jG5JUSKg_K11(c(wPNu4U@VK;cg;d
z^nm=drJW@>HL@c5nl%5ds$~Dz3Wm-w4a*TTcOIBZ>{r#e1z1M_dV#|j6V!%k2c
z2J;N?eHjU0F05@MBG3AW%m(GNVtFcR^h;$H4k0)N{d(20WYGYZBfJy&Qmp0Q$eOO`Z?bkhD#D4X7>d~f?V`S9Sb<8E
z$qK!gErPvr&#IMNJMA2}KS!@gwG~QT@>$E!&y%F0(rAa0ushp`{Mec3)P~=e*xwgs
zvME)}FdKav?Wn(xhv!vma~#N@F$xwHavBL73cA#%-H8~jZokib{ueio0uj8&Llrdm
zRLY)DotL;tH(QSV3{TW;g9o;L)6COYS&blND_VWVDT8wi;&&L&iaG|VDNTv0!AKfV
z=ccoT-;=CKwU}-V@t^!J;W%d|c4x_afp#^_uW=5Wy>rh4lBks442aISMH|LWt6m#c
zJ1#0;?U1C-RDJq^+_sJ_4CZqEEYk|7%*{ai2-MfN3X=}VObJuS&1H)>UHGQZ9
zNebN5sNCSLNl9@zvWtM5Qe{ai6(|=k<07!?K;$IUE~o!of35Pj7Jp4zY^yh-m?693
zS_6(EEhZ*jBm2O3ABAj`5`(6;ej_(w%^*u8<>*{p0H9~!FTNpVb{a{(yfmpSY}9`e
z@Gsy;wNx6#Xf=8;WyK@%F%&=!DXDSOLqG^>wj{?)uYJ^(I3=gaGH~MUW}A&QDO2JD
zq05#Jb0WR&Q203O!Ez7#o?@A6O5M*-9{66(QZc>RQ|9Kn)6QobU_u2~0JDd*1cVCD
zrdK9cj#Af){zAWzC2LPTF{Cz*Vmo`s0QYj6;{At?u2UF;$uJ{o%`gl#Y9
zoF5!8Yo;Ow2;2n+#J9f#0NU-cO3eBHMZ3?gj+^W%F{BNAy};Uod|CQ;f0q9CCLK2Z
zyA4A?Fn-Zi&t)bD!wx?J+e7^ia108RTBaiUq~t|P)YuydCLn|EZ6UDxzDa{<`+Aq+
zD|O7qef%eck|WCI_8H*GUKDI`XcCtQfSy-V9U1p+@@n*-227BFE2=30QjdQ{KbJ6>
z|E}B!5X5hy5dbE3I8_#y((XQDzGYP+FJz|R{u}6%N#0O%1y-ii-vOTmkh0RSvm
z{q99wrjt?p{I|ReV?JqRc$8nE9kaE&JBxUZ@cpCH^&FDl8WiPoAdv+8CxJCa0ul^^
zU$@7mzc_qWxlfaE_j%|w7PLhQdPzrr@8ajg6%kk^t4Zg)<><&fHDXy}@j9oA-l0yU
zb4(eW{3so(Dv)r^_>yiw_vHOy;h@8+oZLoWg!@czM@*bND9@g^9lkvh?w8wbUhdr=
z0R^Ge%ctv6r(d&|KkqIxITPsZ$oN{HEbh*pZq^Cy>{5@J!VM}JlMC=THg2$Gtsjp*F!HU$;qV~a~Gt(MYO8fof
zfST;&=d05apWT>Pp=-9cA8Gg?V2GB*A7Gd@(1w8+&GP{`M-XQHKXmFJOQvRaUG-0w
zR&BP3)0=m_v+Jn<1+%9W?ScH_2OlzZ98Aho_SH#(GC*PM1}i&D(T_bo-lt(OzD$>H
zkvum?T&!oGDY4w;l=j8r6*Jc3|DbvSM^)pndYIPdd8(g`G~Da1kukNz%sLfGdY?;}
zVn|iWc}Un}y}Hrd7mZY!Zi^rhTM(55nD3*#z9|Vfk;6dgf~zQP;5B|1)Eid39$84n
z76If>r`zpM0LCp>I<-gjS|iwdg8a=lG65>`XiQu5!nh&v`-DRh01JI%spRrjk?^H!ECk
zp&=G58U$Zx{eJBABx3pnRZ1n-1bFciF85qe=msVK&r_WOCFnj@tx%9WDnwtcwt?sA
zmYtoCqaNPlcEFvHo3^~723%9wCtxxj8Y|*NHBy#BeoZSn@n3lbVN{Lnkk2%P;=}r7sj&Uc~AFXrI$twD~eZDvMr2f(k%}
zWxe4%ERIAeX3QW0MCv2M#$-0ZoTUx%Q_hv=%bHW>6O>nxB2mplZd;em^x~^s^22Ye
zY!S8?dx+p!cD@lIR56*PkPbayC+NCwY^Gzd0@0N#yZ}oux8L?ScH+|GjF5=*h>@_JNr7P~ol2mX~bT$(qCC4du7l}YG!U{IAeg4O=
zJmZMB#(@4X?;iTY>7uU6*Q7Rw`jAp+I~m&*8((o2OEfh2FOB-peF1uNVJawAi_WA-
z()=nOm#W9z$r>um(&YP*Qmvk59aqJU|E+wy@S
zinL?Uw+>|>CSl_zX$d4)RtZw2#)@WrM}SSrYy0j7=P_i8?)XEw((`z!>WtJ*s9-kM
zCXY$#c%eucWXRYKpe)1RLyDsN3e$Saef-WK%-gZ#AB0}CKs2%
zFdd5Oz%wz@D(y>x{R^jAfwPL`>wy+Gs*a*X2nsMr$=)XzWB9k%#nG?_4W&MB8=`Yn
z%)Ftu-IiM^q1^HbuF#{`*I8-ODc{|#XmAIMz6)th7hpk?0&0PET2qk=#J?4irg`*@vkI9v`+%4^c5U)bz`TBCFPqC*R4$dp8a
z^*()sU$fWayR%TKAzKoBOPF{(2dPe4m`~ywq~OF(kPnRH93I7hUyD81vUVxJ77(g&
z-9Nk#v6K`jN#)T0=oiv>JRFjoa>o_O4q+uH-@)}T}kAwVj@8d6~zzH!*;g>^E
z%~50RR#BD0gb=@0q$JFdkLCcCEklTKF7$-xt8881*%TS+(NIJXa@~o>ERaXfLi+3S
zL=Yy+zw6LyArEgsgc-yvS{VHP{yzoiZXq`So@UMUnjwmYOf@OruDcn|%11Q@M
zDj1GPoc}38pKeYAssQKE7cQ9P5*By?;6&1k$-7C&1;*yI$5u5D&kL8#dr$#BQn
zu@f{Dc^Fllgg_~+dDsX6@h`_qU23UI;NbI{`6th`1`++8WSvq=l8W7~0tG&hE!oE}
z$IJ-95R5Z=Y->@^fq{c=F+XS5Z;n9BjD+Ptg|;1-OfjVdvaB-aXV1g@%A
z^&EI%bg;g0$XL(IP?H|s*Oi(L$pV
zK3*zo9`NzfQ*oD7_nq=515r#{-vhG>M$c1K0p=w(@Jq1;0ve!lS#cXfiq{LLx&qbJ
zi{a6W0B;T0B;VH?)3a{vp&$OCb8DKQY4bcX3hNNLAehrA;ew;>UrejS1&6irqF6+PuSpgTWu+682X^FB7Y9v
zQ55=sD`tfP1Gp6C0@y9C{_Gb0-P+9DfNpKWN)2$S$y$0|BH}bq0>-ul)NgXQzmoSY
zI_xZ%I3s}I-D^nGo!JANP?a=Z?{NkmgD4<1R6wfL|oYSoZw3Vy;(iVUD*yoy0
zW4_m}I}jNn0fPa%6F03=p)m;)Y|eoN1gd3hy^()j(yfXe
zb^nh5U}8X(CK&s5NT;N{tXF?@>)8#t|DbcD<*~i8|E(fzb5KifLs%U0GSd%crrS)3
zqoq*Z(}NMibd>h{$fJWuI-;#P5F)mWf7n#J(zE3KZ2-wv+Hr(nl0gyE+FyA0|AyyR
zfQl0RHvfPWx+wP5j;4c4_3$q3*RBckPE)^Ng;v-;+xoa6_H!M9go`Uvh;hQF>&VWs
z5tmnDIDjM#C#sKJ&nV`Iahh^~dLCWYY6w8NJ+Qfl5~BI7y_I-;%Y~$2ho!Ho;lH?D
zp)OE;o%|L(WL@%IheKRle_%)(n@gh+)j33nsH;;g*Z{--$BQ*gI%iNmrkXsGV-bo$
z9H*_}rv^|1LIh$XyHm$IFc76`HN{6I@E~v~&YplkOR;R=mCrJfKO4J)ai0-BSfaEe
z_B$ye%9x9fHK#u^!PO**ic0bQ|S
z33>F!XT%*X^yA1HcyQz&rY3FL+eNhCD+9>I<5Si8LvoRlr3oGQYWu~W@!vqbKkK8E
zEXJE5|J>B}N22EW`Ts3ZXN6=|+GYcpI#i;P{YzUkPfu(9gn*7sIB&P};cVM;rJ$td
zVi`!|KmAS6MPt$TEs1Zo%UNT+I+@qwdy6i`Rw`=%hz9%~C30SA=vn8@VxT1hoN{$3
zhA~s#`$(BJmfdDjqpKng2w&?+#oeuZgsjLQR|;?bAN8l}nuK{cF(|MR1@ek2idi^QM
zqFV%Tk*s~tiG}^+{P>?Dwep(OLZAbdFHlvUm3qM_+!U-8Edgd6L05067D%;h&^n$<
zAa|wfvct_=f2PyFd>;+%oC`*N%ox^-wplwG`YyO=fInlpKaUm5QBeb0LRrZadItr<
zAb<6B)k}s6uiaw{1QyX11A+egj6bsbKLu)?-M9ZTd}yP-7(M`eF4BUQU{d@yI7icm
z?-!?W3lOo+_pe!ex{!|v@d;3ym0KCAB4Aw@R88P!JvzGQFQ2l|jJq9%_Ge65IdAJ5u^TFL{q?nI%Y)cMzI1!
zEtb(3WUOmm8BjvjDKXt(pWJ6Gp5b{zVTP+hv20PbT#9=H@?B9=zp{i{vNYA#+nLA2
z%r9q%sTt921hnWzHSZZ9nLw-EVvJQ6a5ByK_*tcdkZPdYA>Rwj&J>>Ua`C?*I_@us
zwks!W>e|9k)S^(Zc18mH9+qju9B&=Nqls(q6xYV%PMRSR$6W?2D+tr8?&f)^u1T${
zkiQk#1Q%MN0H4SS{2_YkVG{ppRb(VMOc!fVgfL++6L>})^~Fm-lr|CnrzkBQ2#C@?
zC=#`}mp`Xo{2p1vtvcSerG(gYMN-_q>S3O@JWa)Q#X%};p;M=|b2>oHGXTE?4Pl+X%IyE%6qS3e^2arM
zO*IT)>Y@5Eb004w4z2p0Ey%yUOipZ5vYFKE5#u-
zt#u(++!H>SCzFnhG}Tx=SJ?ICkDsGP{9Xvyl79TBlVe>guL{Vh&Vl5Qa}*_Fx7Owx
zK((LMU6WSE|I}Eq*HDgX$)Mw2bSc<f1D(27*Q$E`0Q2
z+~6r7lX0^hH4J=gc=(nfUV^`n0u*8$-G#sXfj3dfWP~C+#0$JZh|Q$h@gC)ysQhLx
zo-dXB;U71#p%&P0SS-%`6>R&=2_)dStP3NHZ&j%6DT
zariT_HrMH?^blYtO$@2dhE;CJB7Mj1dCW|kjw
zML5Un2~;Z;Yy(2EuI@FT{|8HsusG{NKz;BrOcvYz{*|w0*e%k$``>lzmp(Tpn0=fL
z`pc@pj%YQxQ;D4klrS^~vwQ1gS`g9IL@Yt!-9*$hNv^es?O4_HU
ziw0b$tI%0mW$ap=d-wnd(Maj5BxuY5R_<~Y=zj9(1EUJn&Ohv{epdR2eci&497o&L
zp9U=Efr1Hn0VLi`Y$+>tRnuAK4Lx;B8&Ku>Z!<>OB?A*dRC-nDR(PiR*D#$K77;qx
z3rL$?pOH@6+uxu1_kWWB6$2W;8IiH3@siv^_iA^w4cvp@M=S!C20+AaWkJ>Tl*xho
zsiQHP%&S9Rk@7FOFUTdIG!=x`gIqB}IceyM5i;vDoi-ZMG1CjUG*S^KYDSg4r%0Fx
zbIf@ifEtXzzcgzQV8uQVgg~sBECLkW1W)q_xiz0tfWnu$0N)qZpGW!73y?D^QSS@w
znt_=2ZC>x5?T7wfb!q5AWq$+z)1~nw@eh~Al+-_68ow-PpeUt2$?tw!f+8&PB{S}z
z=K2NQYGPSD$cYB2QKbfdCaQ_94gca~#g*3#q^du)Sp#&CMc_Ixmeh-zLol+=%7Id<
z1Ta$roxSK`6`?k8GK@%xZ->b7o3r()?PL4-+0!UG;1&B{8>H*UOvPQs_VABE)pjb>
z!eD3|&$yqe;=*k_S;lFK5mxx7q&B%QIe?~S@q+t4=DCM9Yk=xjB`7dyy3vzb-0)sV
zr^(P;1rV+0wuW|F3|62qlyYrjBWJTbJORUcOSe;_*GG?*;0y}^ymAD3hRb_1F2BpB
z$k^Szt)sARr;jf$7ktPfp-A*@>HrLOP=yjN0{5%WVz*e6>b2T=@~s^8msugj{Y`-C
zBtjMz(2hiPL(}I(RJj7^+7^$VFUodXL+xKYJqK*u?=q$rwMED=l1m9}l8as{KX0@e
zZC}~f-+0WZMsQf4Y=
zUzBP7H~=CU=(XTn-!YK2KjzjizIdl0wN`+gl3CB_NXrmEMJ5jCr?H0-p5-5W|Z=)G{;oBP+hvyb1lV$%*q3<
zC9$=Wxqn-!$>VljlUZkp`$F*Bg*g_JkT3m+d$Faot!u~<{7(<{yRb*KCAxQid_?as
z-}P<03_1i@kZl3K(um`JF9&5Npllh6fe$b0aNG2s(sWy&twQaK!&kCPN)*~7J
zSu4zs78$cno9Jblw;2W;*vQFO0dIGdRFT^qyy(aKFZ%J@g!asm|B|Kum@;}-bxdpC
zs#SXeqQSTM#y^rYO<8w7Q3SX%yyWD^Joh6cgpEv<;0sZk$^Avtv5kP{PKt1p8kB{1
zZ0)H%v(Eb${cjX3lhD5yo(VPe^>NEtPGP*$cNm4`2(v5YSXvR62Le0yW{-9#vC`h=
z(9q`Aulp?YA=h^@i{q?@&F--~Liab189=H_9`#WA|K;*cb&Ucb=JblED!^&FoRs!b`J^L@Sk>f6ui%dmtzPo){46!$@i#m}#S`aF=(~!p
zNZsTA65_1?>BDGM7ne(sH3|X){&@nwk-{@vutCJsR-7iZGTL0#ly60K&`OREL?!!@
zZ2UYvcQ5P=oawq}rsm=sU`)|Gtezw&@`I>DFj^`&VffPOdgvkV-fb+l_>#3;7Ux95
z#bOn42zGfCecdxtEmIAERre^`6#xT?B#YZy>U6c7-kQM$XNRk}gCl#WeHNsH1g
zA(Da!(%s#i(%s$N-`sFNcRc5L&pF@kegEL+7S>*C%~<0abIfsF%Wj?OVT+0ZVguug
zSHv7ZjNT&$_UQ#4l#af&VDM!Bi#r2+DM)(?WN44j@vqpK%u5YxhC#n+i_wE9DkU5m
z)|RED3V;r6|CbI8@2$9Q*=#811lEy*%+(5*Wv_dpZG#-PYd(~_%=u$!U*%O@9vyG*
z4(@NxZ(AKLk6i10t(gFuy8o>ZO+XO@CWqZW{T|OQ1zB`b1dtUZu)q_CsWLnx{Vctx
zC(lFyi4Lfn6J9`e7E4P3#>x+dqa;?z@T`z?AV_z!LOyn14;z2;|4)7o=s^6h%pQSu
ze^;L=kE|I9MiBo8A`NzT3E8~(vmT8JiCuKT6=leZ{EmErNJ^6(Cj0+NekP;5lb=sP
zz7HwqBG%B_<0S&M;*QFhSypdqQ%=S8+Utrvj~Iog7*kPndNxaN(JLyQDW#T-JDPT~
z=7j|R&Y)p_)gtVY0pa=ORol_$A&N&gQO8{j6Z8p>LV!V-A`;rmA$U7s0s$et)_lwI
z-8#H&`mN_-llsnOAR$qEQy;nt_)msspfz`@n-LfoMe4Q!2Ls2NAq*fSR&r2HLWn
z3>Hfu!IJ+F0B|t_Eg=pJOcKQF53h%L0hC7vekeH)%TfZn9pvz#VStx@qbRF;dz?wE
z7QP&iN#jkw%=(Or8*5
zCF3?B5{4^h$~WgCc(Rx{a5cGm8~u60%gz5FA1~hjclp?z-pb|&o8dZm8lLkl27?`R
zjkga=W@m(X`EPK*B8o8-EP3Vf#{)BbQTMV5ehJNYN#^yQbzPmte0W@MZkp
zyP6#YO8x(zdYb=W%UVNsp5`$F?*HGO=Cl8Yo@Pk*rN@92SPB7qM@1=Jy7N1Zb}B}F
zRobC)yKkb^C|1DMF=-y!0LJ&!c>jY|3|){L0@3kAL?-dORz$yh*;|L1yvce-sIju%%5smpBLJW
zp3I3DcpALZHYnGmiO?ck=n}HMKj_S5PA@Z&!WP5J^}b8@|vfYFD}Uq2F)agai$Q2!II_hPdA25QNcYMWSG2u3(wmO
zG;jKOXp5d(bgBYujO~fxSt01uonVPxrBm`h}PAcDIXO)
zdK8QuVwk6_jc}c2(Z|-2?NR;AF`KGqCJejddj9y+J_dwYzjZe)>+t27et(6(#`6?_
z;eJr8%bLXH>+&2T=&a(iei%=G>BJk%_9y@S81~b0h9;;rknLbwx{6sPh8G9w$O!YU
zJ}S!2Ssr{?G}uv7)t1Z1Afly1U=&knRqD2w1`HYLWB)K@sAek*D1`dVi5x*w2H!>$
z)CY}Qmt8FxO&E-l!(sa%y8w##1iRFCfW=ci){E;QvsmN9a%$gKkcTl#zWX3?aD>p&
z@ux}ut-JZ(k_P|fZf<*i?=ETZPj~ZWQBKqHir`6G;H6<@29kUPcKy+tfXfdJr<>6n
zk_wU8+e+$8x7%-c4V}#+EdcXBX8h2z+}ioRce~G+Zu)TjCmGgxX0We@cx@v;Qft)G
z_&@y^85iC(`(P{K*4WHb@TakvQ&`(!HA@u5-t*h{O&&{D+Ss=sJqIoXWVh&bbgm}-
zJ`dZ78Z{sxhUIkz8R6Gqm|^b%2tE9fnw^sUu+4cVJ_STLw{FXY@4UP4&ndfi$gC7fw*netrO=X3-0p$3n2O6%g6x-$x
zrrc^$BG3MH^QHCwPHv{K#p`7T_g8tj-4c0RRin;-akLUJF)@vF+Q%o(k^?r6#WB^$
z$vl63qSGj_iIf1w38*Q094ty{vsoeEu;8GX^2bR~$L`uHU;zoZ92R!We`O5XR=vYi
z#$g4lCLdaHXg2(1DkUuz~p{3{t;zuH|6=CD)UJW
zaeJ;Sg6pVefmi5p4E(B$>7R*#A^=j9_+Unh^*B9>?IqD2h%v$$foEo`$Y?{fWq8Vi
z4G{JR>(vq=~60)iFt$yCcUO2bbehIE02Dp-z{h)Dki0OW{p9}<^I=FV7Vy$uGo?<8+7Z%
zXbI>Xds`mr2dvT|kUy-_cU1a+ZI%8bMNl5#e#f-MW@>Y+r2kIW12{_bANd@sQLR1Zz{_2b~+pII5k29x|#kjC$~Zsc?v760@Mn&m*X>GdD`(RRwEyqc}2MeJXI$b3~VeDITM_scz%LlA_rCW0ca(7%I@(3Uw)$Cae
zUb2cx1uc~W<2k0O>i5bqN;V4!#LAzB>T-G)f&JpYs(G0Fr)nOqugL!@<^h|zI7+-5
zo_cGUe%q|xeC{0j^6wh8-}wj-;kpo%+vS_(Zr#`FSxR27az
zP0$43FWW~MzG4TKEa9WMP(Zn@#TSy0{zbWYV
zQXL7w~|#R{&}CN{R@pt
zUne?R(#_EU1G?*>U8j6iRn__2)SQEC&NSY9?*vS<4*LCH&-PmJTV6H6brHE&pG0x|
z(_VcRuza(RDkt^^tym(Hyze9aY`1+r?iMaMQp5%@9gu1mto=WGtAT&2{4;Py2
ztY_s!q$Ef!1jUb>VcwP$;3(IK#gsuZB#W7?u^G3V1-v(U0OJK}ex`FUWzH{xr)t{w_0|wqUfjxW@
zY4J$HP)QgMP>iMt_-k@FA&*O;M9SLh3h2Y<_BlY%mY0&7K&NB8e@E}_tvP`^gc0@H
zn!_^Zwl2ur-|B*3VS@AV+@A0C-jEffNEZi5Ep7+38)P^DdjCbwReGjP>EjC~e`Hhq
zs`naA2F~x6=J_pL&C7aY*$c)AMPs;vo=vGkz%m6!*_pI*HG2FIZ3N5S~Z5?{J9iuNZ`b}C_m&c
z@ma>w)tY(ze4a~EV4_uk&*!9gfex@Ic(nh6jiYbJ+$zN$ltMZiv&Xgf^Jso1!U@)v
z@2mr;=rPlaxqTbaz1X@!V?S~=wS=k#Q|%au*-v@;7=6RuIwED|xM`sQiV{6X16E|v
z?i=Zs36d|-6VeGo=vb1RePed>P)MCtU$HnTUbXqyMbZl(R;0Q7fbJ21q8-I;xs-vu
zZYJXB`y3w*bYv^w?dCHd$%I#5bO$WxH
zrNN#e
z;1j_1U;8chmI^T7q8oW|t3MYy(X7rlknXM}{P5T@%l<=u?$=*W0|a~+2}-}^si+gd
zJfMy`#gHI>?_wl`3qdX4c~sZ^x7aAhw)
z`zl_-mjznaa95xBxp(R@QoP=pog5M9!z%vhsDk)yd&rxSVcSi!htU$PwzBd%{$^)?
z>1g8G?2+2R%8CxZz~FRfb(HWZc`;Ja_{T{-#GB9G$+t+df1A1olpfy~qcu6=X#H|v
zn5|2VS{K;%q~$W_Qv%!SL%(@h^iVreq~3F!)&~ua{UpQJUNp%%f>~~ILAe^pybIG7
zG!JTj=?NNqHGp+g!%B)07ShZTC4FTyj5^;T@0fwsrbg?VIqHI;Q;CsYj%$84-%x#T
zxOQ)DeOT$ucFpql!zb?k=h-$kV-j$2$r2t4L-rL3d+vStET*N*HoaJOw8F*OdCdN4
zSvlvS7noFhmDl7-6;6AbxS39@Z;v)VW4eEz!lkk|RP#{5hW9n-UuaSqw$QU5pDM}b
zd#AT7`bs6nSbB4fI6=dg&lU9^N-}yb3G&>0cgQPRi6q$LP58p6N;Prz2M@S%Z0zy|
z%2ZGmW@`c-I~+{J^QLa+$mkdO`3k^tan!;%f}a%hr7>f~l)M{;$cDoH2O{r~YMFEq
z5-gORU9PS>s++_z!xZuCE-GqkY%I%!>kQO9RI%aZ4CF)Q*Vm{rvIzAficW}2HJu;n
zzk$fSG7vmE8oHS9a%R0!2_UBSZh|pS2E)rB_`W`9>
z+nkH4{H>?(lBE3LsngEUFME`nQLUDbyOIng;$x#1=)Ih>qHxbOiFfvWv^U^vysUnMYAR&4&0!*rU&
zPx*fxS(G;w57w=UOX#7WRgN?JPDa6y
z`ayuQCE#M&f%3%Y1n0EK&gQ%>_e*MFYK}eA_M+`V
zjxy8k*$MHpzz7-8nu>b_)lVopba1$5%nl<*7XA<<%Ec&9bQ9%eH+9
zw0YgnF56eD@-g7QlBdEHRX9~N)FWc451@*uSR781*q;q8%>>?Tm&7w2I_7*KmGdTgmgatK2N&gg8m9=rTLM!1ZCL)8X`v$LN$`@g9a7CX!N7GRh$0#DVJBcm(`f6Wqg}I-+
z#Ke-3+CKU_`Q`nj(M!15u}e4tVtFvXtXwt)=4j6018dN2DHHV*mSk2raoh!}Zh*OA
zp?mJQ732dTqO=<^);JwTQ|i<@Uaj}8Fy1_be|LZhqkn(`egfi!IL3uS=LxsC+}R|g
z31p{Y8x=K|gC>l2EThv@Zn!2-eb7W4%m&z;kH-{!XUlQ!m%(#;D2Lv|jTAybt<*I?
z+uQx($QgU~K>y9Szx+z#$b+K!LcX~=N4ODAsvHue*#|Z-4AWNSCH<6GIED5mbytjps0Hc7@ep4{s16X(dsovEovK(cp?Y(dY*Xq+mtHUK*_U516ADn6mikl*
z1;+EaI$iHS!O|1QB8eh{)wMfFSCrQUPyT-D#fMD{z03Kx@mPA4Xk!Yb0xPQyBTj=H
z^Gif_bQ2UuR80arV$LM5G3J!mL$vw30yF|?becpJ^gfYuN{NiNQ(jn%iS$1GA^$89
zxT%q7_`*v>Is!gc40wBD2)99)A4Yf$>izuf!HgD8nKpsW?|OY&Rk08?IgIuzvWP=F
z=TkAdCNlnRHU8w~uQ-xrD^y0W{$b3V?RGp#p
zmYrrVfEmuhPWmP+E%z=%tr9syj-XVoTU}bNy8C;Zx_@h%*u)dE+7y>6g1VLfSWVT;
zU4`e>5-o(AerTk5W(CZ9BEI6XQkg-1BkN_Sh^v!{O#Q+Pxs$7o7lTXj?vqd79Qq?;*Je(Iq-|4PNMKc;m-R$%7XWBAvE`P0Ju&xuqIKkHC&eb(_%
zj3U-4ig+o+!^JBxHu_PS>5#)nPw_yI$e1=DPtx?UaWVYcQt!LaU2*tEYXdn{d0^cf
z^+1(?%t*&iP-Ic-kPBbq6dA6-;{Kf4&Ah5mnIuQaEDm~RBI0O+{&Reu(!>M*FNGBv
zJIdG|(L->*3#fbpj*RtJyT*g$spyo{Wj)ILyA{Vq%az<`e+m$)N&eTk9A21j#yI-a
zyt}2xd<9}amQz4iM;idwRIqA2Ph(cf{3Rg}Qf&x=Z{rzcbAUtEM;Wn!rW7~qlhxjG
z>-Q(*eK48eaS9k44eEpx%?H1A=CJ4Z*aKcoG1>sGZiWZ@w@@qB(Sm&mXY**zsJEpj
zXc=Ol|D&q_CZFy>Qb#gL3Kst#QB`tmG+N(@boydtmF}S4l
z<^FdM;g!?^X>bbj@uSDMQWd{+kByG`vS>bp_CL(y5jMD8h#PDRaYtc4YD;275dA6q
zB3_G_9*4a}7^QHgXVZRcs|^g%G!p^ZTpz($46~W_k^+bQ5^bos3Htyyvw@ysfE`28
z_9;yvE`~7E5OzeTg1~qA#S+5{1HDq2!Z3-i564Ec_&D*>(e&7p>l{~j7b0~(sUFZ^
zAE$bTj-Uoxmc!0r%Pt_`C%KH)vg2PAC8}rVqQ@e-==MK)qIZHr)3eREYa%JV{e%Ip
zi6#->!5pD{J2WVsF|)%L+q=e?rq=@DJ~ZHQ!+75uH3mf$DeK_2`Kd=1qQ$P%ATlvtgB#N6nYgX(da+%E!RpU!mrP`@0y1Ae(PMi
zX6(<@D~9`us&1RS6sU#ytd%T9fd%=Wbzpd7IqLQvL+M(pC^f!DWk=NX`A*o13mDMq
z_Gcm`*4?rmR$$0IAa41rZ6Z8K3T-XeyvV`HVGAXYO$e;4zj9ihJcoTMdQvmKwu91|
z&TQTUE55U&(y~t+NLY
zeF
zu~A(7E$u_dW-wP?gHZ?UCn-G5F=vMqq!@cE1LC5MK|Dp%x>adVywgB0(VLE#rGAQE
z@x%md!_7*lE|g+$%+hj_q)x=rZXvknavYC4Ah`7`JGL6W;;?7)Ab%1v#yt1z1qBaT
zt3Lg#pp8@|{N!^3y<7q#fcgCP9QGxQD^Ex@3+X)AK{@ckbYvPSb~8?)Cx!VMxiLu}
zVx<8Lu}9%d>3Dz2U)h`x;^0t0w0f64ya9h?$!3ziKvt@xG~z-H&d88`7Jsc`bnqSw
zZ_JW#W}t-kf!xElP3l98`RCXMZy?!j{HFmCLEU@?0r)dXrB2`>;OyK_R_cv@xbpoe
zjBoJ^EBqTg_&1QHS|V4X*FRNWw6@Y?mm2EL*j7H$<0#q1GziCV`#y{11}mfH=F(53
z`J~88F$w^MF?_#8Ps`8c4b4>xx#9w(N^1`L%qKr08xXxq%sA}LSj7Uy2udNb+h4*T
zpQ(jfL(g?zf6A8}iMG%?C4n8up&bfwx^(YTVon_O(FlNH1gZ0eocf+W`
zF~15YF@tNM;4Fb9W1zR9eB~LN5Tx}la6YE`vFiLjD{$OAa1pXOj=~|bCdd#M@+rTd
z>M>CUm{&bx9b%ebIr8^K5(OXb*oW?xt`P5ovC&lX1k`K>(OXDpXpT)o!gCS4msQ}H
zROmv_2Rl~QB|@9f2LTu?(g(YL8)DEMq)B0VmvP==CG+BMy~UD1n?rVkE%)9nG}2oU
zu`OX?Q2?v5f31J~(Xf<;QCTF$Qz4tfW+W-PwsWs}Xlz5b{^P=z-=P=26bF$~M=)q3*#asQgKNGy#Y&I!8bZT3{h%w>)TpKvj1mRO^vfIW>ijMHUQAJm|O-b8;H-kv3`uSZ2v-Jvd?;l8p)shwA|k1cSP^=
z5u*Bq-U(iSMN^&sfa!*UYX<<+_Svs5aj5YtZLnpiiZKOmL0VGbut?kHD^82jbSyq6%$llQv^ZXpAj!X8t?7>`7;#=;1CQ3D>Y!x*EFd;C=p78^Ry(od|9P1LyONvK1n|v@>
z&jwL*HocDBIP6;q5dxh;Cspw;rfFo=rqZ&1uzS$H3!0G_^~jy{h_JBCDZ=0N8yhv7
z!9C@UT_B8oG&b4~6P3Yh*!sz5_3LIR!Ixr>d+i{{&I&+ewM`s+T;bU$;72ua*@0Hw
zfM3%+kn2vSNM{<#n!2yl)nZX?_;KBw1K`lGs`h(#T#Oc?ggIWUdu4gbqO?fIeA0O9
zT
z4b`-Z*3ZJB=Yz>tZcQLX#*)jAbbH|P^bVD$_9njtxz22H1VZ^@gt)}%=Z}h~@LUFG
zd%~S9*#Cygo{&vt?01|!Ef&QeixlqH_t|&1SePT2Fvn`4R|v!w!EtZn@10&&V`Z125z({b)BZLrfP>=@?VR+
z$`p*k3i37nLT0@lmX|b8HH$>>m#H(B!XY1?#-#T7-frVBtDTDD=%D^#&=dAO$|A=9
z1mpnPwf44QGY&&Hwz%FF2J-`ei!8Ueh=gP5HhS^}2JbCY3d)B*^7z?~FAMqbdGLi0
z7ZxCpIZDAv_8>rdbUfsJp^ue372hXHD2HtTpcIeaJ=W1C7GnUbtA-^QDJ&$?($_gI
zBqClJ5j6GTPK-*0Ht@fY=Ad64pv;OYe&zoi4ma+hqjrbAqBjIeLk5%?=_{xQy@!mA
z{??60$>yo)fOx-tEL9A@RPbBY7^^&c%&jxuJ#)eSf@ukDil+;F!}Q4_0C@N<$amLXBl_3$|ObE`;TY_t@x5{L>;5h8GE_Qf
zwmhf&id(9x(q0qUORzAzD+CxSC#UDDu~9y!PJ)&2QrJL3v#+mGL!gQeF*}Hj38K5F
z2OPa1E|x$enfPra^O%1msXBZU{84u}C(`!@P$-q22IN$GxbzsXz=DYT6P+eN*C*&H
z19_`OLpWTd1@@`0t`W~jxPtwlu#ZW*&;*U0ekS^KP8|b;7pt)~Y6ZCqoK(FcJY4+H
zwWdzpDhhMyGcXCJ$tcq7%J4M1Wnn_Q89nL%Nwz?f3k|YI|KTXgb6hR*%MVJCyTSpu
z-WMGkjeO~WZRv;wS#plRE-blpJQa6jUpyc1{`OTcup$V+$o&MY?D;#sk7M~&YjT#<
zKR}JAudNolAfHyp^O@3b3QbHv^`>4Bsvo)CF4=ypFL!=kOO#WHY_5^5q3=*PYw0gys7{h0a-9l23K9+l;D5vF3+anMfYrmG9vd=P-?UQr
zbsOp_ZYaGdlJQ*OAPq;#%{c2Y@6dUxJ*g|Ka}{}eqFd;N-2ZRbu@_G#res18C->!;
zGXBN&|A4(}4OTvoO=B2IC89#ThF9;U?8SoH)$2SLK?Tk-;f@w`AUPs;MKHxwzAU9-#|d^E~qjd
zIv{U!qC$Yt%`S0MxDJM+DWU05)_L@NkT!l{0XsmWFrT>0Xy!ivud|g>AF7Pn?L+pu
zk{dtv8zKNjwNF!A_?1Hs1|;_2UQMv$R~F;`Xodu9lmKF{|Ju#|hlKMsYCyy79zzsK
zR+suC+irn6UNh%D5-dQM{wLs_3H?61l}S*|g}+S$N-ixZHfEk^v5Y%s^RKuGKB
zD1gbOdw|}V-0GK^HHED*@FgsJ1k!bB%#|3VHNL#ox2~_e1m*=g!?er9P-<-otg;#%
zwZ>KD;eGx8Yv`qxl6#}Z(?(?y4embIGtj@=B)teq>HoolFHOrZu3>>@LAR=YQ+P-M
zy>8lj|7vak`SRWYw`7WB{+kF)LN{aG=_@CW@%qy*w|%DB_|&AUrH6k1hcSET9rtMj
z3s{#m9XZ}Eb#bMYna_wM;IWhPKNf3^3X-NDF7K;Y$m}u{!>WIyA;%zjbzd(7qO4TF
z_}QmW{Xc;4&)G*p
zT(IMo1dC;sp1tE*O9YQSlma(Eo)Bt62j(w9-e6DA=uEw%#X{5Y$FlkK*C1(xH*0+_
zkQ0FL^Smo#Ibh~cmWkCOKPTLkHj(>h4Sul&Lpe37XrAy$WLo84`ta_&ydM-lB2(f_T3vS^nj6J^_qBXII7LEa?OPTM&x^
zAZ9f8DSREqlmfq!O(Q%Ru_g_ATvIw**VPaA7C?q88rC%c7$XcK0?n+cgNwNf1SwrS
zT!5Z0@n=s##Ad)FAYOXaW^YBOqGsp2t@EDQS@sz+Ou-pE`qyqodjue8
z2t5FJO<6C`W-}QT6i+`Z-oL)vcB@a(Pg|9i+TT1zt>iP)Q>lT&eX>EC{VxdCeS0gp
z;8>PvPOM@=Ay}ck1_uhk-Shudr0AVYb$czYgq?|Z7X1=14rbC!EY)rCusj1EXP}7s
zbe_$1&+QZYEFGjJ3OKlzJ65_lT^;Z4xXZw$0w1%R
z^|!Dihg*hx3($T_e~{^#8nH7=s{9UJHLZi7TkvIRF)Ymgbp-UMw7OgUNoB}ofom_9
ziP0iIJ^SiqTZ;uRN2i$vR5|>E9OIH4JX4lX-cI9ic<)8)ykmv+tWpjtVl-0VGc60*
z=$UUKX7U=?C6j0A52>~;lZ3qh=@QHTD^LenJs7X2mb`rkjX7_X
zWe$6wEaMyLm8uJ=Q|rDpt^`qr!>h=@drs!KWgMXNG>(c%@6X45I9P!oZMQ_1F3j^;hH>RQ(nCeu$nhixX;=H};>HGqu=1;hQG*N)A_~BR6+?
zhG?3>Nau5yg44ri|Hhm@E}A7m7${vLLF#)kytloslEUCSOIr$o%@eg&$*ec!U5
zkN>`h`vU^0XCxUhE)evMMh@VJig^rQvTce`&Uvcnb9{>d@**;PR7=P@2EB_Or#YXyw$9EE&U
zz)xZ`D<5ip&vG1)wvrp4tGoVHG6cIJEdEBXRinE)!ItqL_j8|&(dA#3WjZl+}x;Mx2v=HV|%{)=f^jRtsx1n$E7%U$#l;b
z+A&zZ(J_0HYyT9$*>zWzeYqF#wQjz6W~5l=tsjR^<3l4`O*+kMD<_9N3vQmO%2PWh
zdnY?pH(UGT%@qIN0Vt&rJ6UriT{>X!D>x)p)du@?EZLC80t5x%02g-Y)2Zd=m
zZsoky6;+k*S^IC0G366QLtV~C(sJ3zgvF3?X7uIAyr@5931M6^!6+8V=C4g6BZn#I
z;5;DfgpY0fk__7g_Q@+_Hym~*>(9r|NFRnd>n}iF`|9fpl083o7Dml$ur{99FMffQ
zkZL>AcxKTV1UDkwctzV=
zRF1)qjGp*o_mXx?Cl9A)wV#^Sx#s@W*OM{0}#Y+kWn=r5P>2B%{XL>5}
zco8a|e__Eu<%o7*|G_;)T)=mB#N_K|*^_uFtwkUT8zXY5y)4fzNYO})z*}aQ*YkX|
zoP5zK&y1$vG|jj$@x^?^b|FD86TynnJpy^bmdCZx)^8roMn{k%a+TSgQF`ClTUtb
z*1*`&Ll*0T=Lx9}anwPr06r_TWCmRME*`@nGG(|#(k$?f4-X*w$g{evqywQgsdduJPriTv(Y^J_XfiB)db
zXDf_}RqDpio&|gj;yOD%=zTTsQ(1MQVu?1xNV}A_a4fE06wT^vL$^OOuG(
zu%z$8V%TT(%F)V#dZyNn~Q^NfW96>!tp!=k8iiv1vfBRI35ZC_apKlvdj_D@#e`=I07`lJ&!Eu;>TnQ6;r9uQ3h7(U&kFdNpDSXh<
z|MKa!{}*LWk=v#4W{DE8cW_-_{&y$-vy0gUo!-x4-i;k}Xj~oye!3f^fB!TLv$W?a
z>v?+%|GFIY--rIM8!tql>P2&r_~QopcJAp^G)1Yb$Rd&o(HgKm=M%QsdCmTg37ZU4
z%yi(Bo2XO=Vu}zgyGcU@t=sWxt~sMS4C>Ttybf5)4Q|;G61@#
zZ1&U0uQyCiM^<)r+}zwtHYZ_H08HYPZCuCLF}ucmgQW`MP@d2ng3
za)Z;|sC+;3efXCV3*^)NcA6AP?5qPn{qh(2Vo|JVFYGY_^tbxe?}ddgkkdYjHtbWw
z2+$42X&rl6Ga`7saWu7mv^8fg-m)=f=g$)OQO{f6qASnzsRMFbs73&-5$>0Q+-2OB
z!1gw#0aM&*oTm&Y*F}?r7CV|>wKcDXmwYP)ug%Y*N1|13oc47X-s^D3ETw+2ZZ5Id
z=2y?qIdi-zy*ZxAAg=J;x!J!?#Ll`m^@>Lhi@+g?igQ~~sgX-B@18XfFzGZM?38tv#tJUhDPuHArHkJ#PS^+a~$jHuG$WPM`kc;6>8z=8OT!P#l2n>uFk
zW_c~Ca^8;Pbx|{X!Ips~QVkk~Rd16A6b1JoY
zVob5bu`?hokF4^8tMkUt^$H&`vm5-$QggPBKyzeXEUAfglsk^HQLX0X!tVKa@s7$D
zx6j8x7d|_=mTsoertLg#srHJ>rkp;UKAr9n2I{Jf9hpU(4m&QakRWVYj(XM&WyRK#&9t0N21Ia=u!sO@+M8n?R)n`hD`;ua>*idtkAT6hRwe9
zrz{szAt_Ih+WRrZ`;xYkP2t7V6Pe%wDO>w@oopBcte>Jxe(b0|Jkj|X)_(9Xq(Tbi
zOV96T(B5K!_7=V00gZEM9pOp(7Orsg~-TUklyZD*n>FQMA%%r>^SX
zu~FoFiN2-%;`PCnkFa_b%9D`(4yBq}t{9!z>Z_Txx=Om9{XKvF$10Mf^ay7(Ms%FP
z^%?JYrRtt8LT`gTCZIn3{R;#K^)FLCBl@)BskD=#Bl=`qPlLrR`kshwQyp-d%-Bkc
zNTgLZSP$#>FhHb50CMzw3p^wYn7cM(VR1^BlONGPNek(zsBHpAP!A1=5v+(?O?oD=
z7=tIE#%PHE)ey390?5xD!}$98Wl2Eniv?;4}9#GJYd|2u?CUzeX9aGbrsK`-6i5o!N3kjjIPe^egk<%T2gfDs+o8FrrP!xKJn3t#}<&9_>`dnE@xe8KT{f
z_b(tPYCTKN=T1T=`|*{Wi59D7X!)*zIfG(Wb>9{dvc$KkUa^^k4CATNZh(iN`t^I25^F=UvUL+f~Gs(Hhu4|>CJag8Bi+w6UP!XJ%AH5eebsE^wW1u
z58%9QI^#5G`n>tom+kp2FyhN9W=p8%ryATNrqLGhtR)4;Hl^aP)XgNWHJ2h@v{#WG
zB)jb?YZur3Sb)nJT^zQgZ2obap52B^>}|VcWV=tT!Ar(TKd!0Mgl!Jmt6|&^ZExuX
z<9OTRTG^CQf0XQ)cJ0mCN~5%P$zEXzxl2lXnX5m;I2hOX#gDd&!uaikpLxK@Zrjd-
z`CLwH)W5vh06m!@68$*1^{3ml#-v|XaEZVxa@P)%vo9ne{mXG5!QY_IxG+BS86S7=
z7om^^_%EzM0?{bSb_XYL8ry|Ubd}63frx9Cj0I1ATN>TqrOi0|VbQ;+tY`2HXV|c9
z4DX_Q7nXBrh&bo!y(k+|MC`C>4vMZBI|hLdZILpmYwLrNs}WQE{r6=uxkCf6mTniK
zs{YMVkycg5#X3dw+={}EkK1HN-dV3y1e{8e=g&Q>C?l;G5`9)aEA3=0Y9qQv^@C5n
zvUffhgr|rFy6rfv(fQ!}tq;F96Rz=KH(ud5=GqKKh~Km);TuYtr_L#_nx}45h@CN2?7beo;ndhC_bPGPE1|}2*z8l*qFK;w4OKTEL!=T~U4FyQ5U1g|fGLT>52j@OEeO${
z-c3mq{<|r83Z~>oOYk(#UfeVv*mi4;T19b+S=k9#qvS*wp>IzOAis6=Dv6t2*FK3w
zBbqv!aiyv+e%h9hZM#+Ja5FwlwGtJu*EIe9aOK>r*bo!P6HLXebgL?abi8SY{83d9
zXTzU~t-XirRD$=eFe(NJuSIw0?qTID%aI{!r6Qr8OFS-;x!=~3Y#eetA1|!Nh@Cpz
z^O9mhhaG1mz-02cvpIH0J8k6J2YvyXsGaM6x_PygJN}_RHkkft0GS}3ItzAC>vO(R
z!zxN*X`C-<;>33Cjt?STkywdxajdtdSNm?LONXn0pF;<29D)Nnal^MTjaM4%_
zQd9IEC$HJ*{eWn2*}E;M1n1yrMXvO$a_rs|pA3{AYpEfR2syYp%1VTqqhV=XJQMIr
z8)!*8u3*f!l~vt3{;jR*RB^0k0pVTXq(^k+%!)FY|BxpJCy$bi6wsn4Y|hsBqLa4O
zr+INKeab=jX}H->kq}Z5KXXLoB?I6d-V}XY1C$u-$Yp_3e>a#v0Y+Jxd=DUW5V)YHy
z!FNq&dLk&ebMRMCaT#RQRXAi7VLb~JX_esm=$L_|m^GS$)NH5lIGIf7o8qTDu7E>F
zVWjBBA1gEsO|=dp`7V;joWA73s@W1WFW0c4$1(eJ2_pp*iu6MdOi7{2LBcdhd(NAy
zNcHkjfDnfE`Ws%{=1yt7Sh6>=BAXA3!mUfcPTS~qgkQcRTj=3`yc3#JxEkjht%Bgf
zBHuzmjVT}gwIfdIQ?r_)QVd6l?{zRTOoMU68B)2!flldJOZ|`Igeh0YlU9|r;If0%rPOqn`6W&h
zd1Y;#Y#o>Z5d|D@`(#{N;P$6ccL(%Zzv&lWs5ZcZhfY
zh75DM+aAB?9B0-=Cv-eV*#Hrnlj(U$IM$qIQd$J*W&lwdRJyxiknRR)
zP>}8%8i4_%y9W^ImJ(@c>Fzpv@b&%PI_KB9F8}zjXFYqbxc9x*+It4lT^4#`To`)Z
zon4eZz1yNL+0g7#nlim0;YG!
z9Z`iK9%m{$q|1)sH}l--hdb=rdy0vM%tRnfLQ#HIsM(%Mxd7h^S4vc
z`1=`h!Fu}B=tXR3M+;Ml?2-3ukLi+EFAdly=4lw8j}VJvedVkGfQ8J0iPdcj_JJ{+*P^jPk$0JDzZU1oJbTbNYB6mhr+S
z@@v$SRI!i1r-NzY62_g<(tlwG7pGh-dh%7hpKUV6p2zrjr2E7vb!O7d$-%W7g~#M3
z?Y3;>jlPFGs!4a<5MRB!b$-p?fx1YY-GLTjVLFXGeS!Z`CFeJW)8GvJtALoUlkF{Z
zTqD%}om=QkB7R1izmjKC2JoDg9Ugtmu6^{VAKE*mIOtzzW#Cj;cb>b0SaF=`+T+e?
z@-dVywO$|iuzOBI=y!XSrO)j1H1!jM50R{xlmRC_oq`}VQro))tBI2Pqx930SfsiH
zqt|r=n}&ydB?X&k@pX95xP_^{8Ds0IQsH(IvS0bU{9692j_A@pd|%7%zV<0*10x2c
zsI@}a3@^1j20NNY>@lje?6;CYpY${og2Edt7uhK@LNyHm<)SsY^HdB|IlK
zC!ZJI9Q#yAL}@3(lmL7EYxCCBs!|;*uVsj&E~mcXg`j_Uk^}ZEE3ZyjrY`&
zoc5NV+G{Ml8{PZWMoUEK-0*F?J^#1PmwNGI5=k}_bTX=}mN^j+LR`4~6UqS69x*APoKNi%QUGPY+2lBT
z42Wr)ri{wv)c711Z@ZrqgalPi5{Y@*wbBORFWYLB;AAs+m97|@$G;U$vYiX?lT?lm
zW|C(Cvm@Ya1-MQ%@6-ymr6`+7-RKupVy*uF2rt=S8jic<`9_}YG{X2HxNm^fltb2NY()+V;DOXmeT7`)7?V
z3SF!|`im}?1AZ&_U@~Y}0s8yt!Hn_{FnJu#dNBE{Ij4Fsc?FwLC?eg8c1-*|v*ld{
z1&jJ>oTQI7WhocW((%{<5YF%Gs;k-mZY|)+#)DPby4cWz@DYbtf>;lkb+NHSPJgAf
zyk~hRs7CxX1e$qKRzFli-~MZuE_5Ua<%u-J5-4ACrL}i1pOi-vVhPZ}S{1TXQY`Ul
zbG23c*+`I2&*{_YM{4D|o(0fxJ4KwJ-4{|>-z9QtHk^4ZZF+|$6auLks#c~h?8)mG
z8?|wB4GvB=HWEi29gFygEVbR8E_7iKfd?%H%r>{c^m=&3pM&Z3*3aGo)8jg#dML;l
zn216HP18pwf0UK=>JHf>>81y3V>2wbFoiSl+aI=+8~(=d*Kn49F0LW=5$OE;uRCNw
z=Y;cj$u!Z>L&EUmI6Dm3*ljfIjgYdBR_
z^l&2lMgn)wbx^){KMjiZ18DP3ni!zXO&%!mx5eK#Lc5#UaFceo5z?gSS4@XomaJAo
ze)Zi6u!q49mP&0yF!ZU(>%IqKh4KhP%wm_RKbmO&=<$~z2!vOI&|0#cLx$Gm&Kxqd
zHYsdqjohQ={ux?Ke?tos20{xT7k1jF+BbZ;mbb>gY7*3VwSBrdlIGbp7gH^5Dilp2
zYNw8gYZO6TgfnX!XD>@n_uEbM(B&%PyT@T`86?HS&grDNZjtcb+rv(;Sj4I)CZ>l8
z<9hjAwYy)pDun@wIF?>SlsoWbhESM0fGynlQb@?1>~-#<&CfFCLPxFNAp3hqa>C7IvU?Q_pG$1
z*rZ2P4Jm0?WFzBZlHlI0YGt+vxOew}8mHJ`XU#Mm{+G>&a{Xm96wi=s2K?YRij$oE
z$z)QwUJoV&Aj<-kymBGD0Dcds(Ab&~1L?gxgcwYIer*`2H0^WHM$e;B_)T<(wp+Ct
zlM-h~BO)?RN994+_iAx&C7A=FlC)yz0QH^4lY+3&eHPlga*_CvN!Wl$3fLmB0g)sn
zfO(lmgVDqaJWB7T~H?GId5O8Pl+gXDxh2QK?P7^MZc
z?5!O{=%W@gr^BjRZ`q0w7ZX-bv~)?-m=Dd4ce`$owi1bB?FBrs1Kz+Ff@cT3A(bkC
zld~cb+wSis#^U#P6N~c(n^KHx4p1fxbK3>*hzz%;2B8&k@k?Q-P4O%rK4~2^ft-S_B3MQOBBx-`p9^pgH4OfCXH~{D?@G_nM*gu
z(Y8xci~h^QwJr2rREw4o{iuFIC5g4YJkuzdwu$DdExt)c6JiX`U64VpN>~H)$SL|Row;lSgg>^YJpj|
z*{N<43Ppx)-)=}EwRSR|^5Un#x$eSz9#2k0sSEh)qTb2ImGk9E5qf{>`5E=vz1m(M
z`$&7eJgpsq>A*s?-@t-ZRx&?UBX7MeC_nYp=
z^9QGq!irm-mr9n1vs7Xe`J3Y85<&;)S2JM%&M#KB_Y=2@Qr!<0>eh-3E5(|KYMS1P{auUL{{AWcPJVNo-J_EHfm3(7dEe+@8ZksN
zM<>95wsogYfB{z7#riyAbp{mk&M|LUnY@=p2)Mon!^X3Z4t;{hWF&i?$|fbNOxqv}
zcxngGTE@CpnVG6amH6#voqJLKTDHs{S96Wp7b{bK>J>iTSCEJyz$qX1?ka)i~+nI=J+@cSN-(r6o>xti9(dQ|LNoGrs-GZo
zE+L~P);ogdIgh1wn%C+Q7je;*JZJ1jv|WzISFQGVpA|$#S}mUJ`VZ|-e6tyy<`LLg
ze0`O597|%!TTh)qkAlBcCcB!wbd>R3aHId*=2*GgH<=yRV27d`#w)z`D)y|QKU__|
z?YPKD7g8O7Y;n4tCaxBK^UmFDgsaX}&{;<{QR}nsu3Op-u|edc#lLp(##SBAR+%;q
z&kj3>Am}rUo+B@#l%s`eKSjIIh<#n60O`3GFLW1#`8rD^gp$jJLfcu%PhmGkDKT^6Q=SxU}i~NBpRL=3dlwFj>l~<00c}OLo
zhpuIttyAGKi6FpI6_lB#?MiLw#lB|gFB;n5uFsa*+HpR14bGQbi9l0x=HIw@#K^Ig
z`^sQZLgw=}MUu+pXeFfyu{NQBYyxld2(~?!6)Y$@5W?U9XQ41WexH3cea*
zx_$Cp)@2-KeP}AaiQNO7+{y&dM#P!ULw$0b#i@xp^eqqLf}=^;UT#g?ymF}s5tTv_
zTMOwUX;QScF>NjncjExC+hSd*wWc}AAg%DuZVvE;CSs%!@DK5A;$ERRx9Ch8kp)os
z89^4KeyJKZXe%?e&UQ~Q$_QV&U94u;t<~XKO*fuCw@RY6=j+B?tUp}A2kedy
zLREag?s%s;cbkGVPR?gp>5!
zp%(xw0yX|vXZB77o?OaR20WwFp_#knSSCEsIjxBr$3Q<)9^`-lJz_!tDFySkeRKd}oCEzBBc5?5aL?Wmzonec$_tii&>2pM^~4ZtyA5NL=8?y%guYE
zRtttR`#3)&+^x+zDy8e81YQoNXC4s@)G!QP4;{R!hy}RO~Xz$F?73j+vxErT>mYGy1eYP#r
z|5>y=;&=WtS-L`HunQ{|a&DOq?dV^AL7aH_W2bC2qJ4Tp)Gw>^t}6lA$umKf5F
zdHGrayXP>nTNPO?I2%vURFVmJXNn1BqnEE{U{?6Xya?y9?3>3uIk#Rmhvx?jHHoNQ5z76*?YIiu}B2D&u2YldM7&BBwLvW9c-$i3C
ztBATVS191=l9E?GD5H^V4wfhG)PA
z@bH#9TUs-($o*S4d80jGGT(nZNH_j$PdJCg$`F{{2(2UcUnF}G_1OKK+PR_9142A>
z%SwP}(<@YEse;bndxsW7Efl>Fq@)0G+va!3(?Zg;<swUsPIlc
zrLiC$vTHLo7&l7crYkQ@PD=&67LgQ(^jb$m9MWsK6(tMBhB2Zbc31~#@j{G#8Bty!
z`E3DATU{*mpcYF
zFS>UvhWBv{Y3sg><3^LDQRmjkP)tIVztk`_;Il*A{
zvW({nubI;0M-rwhzMipQY5F&W?1~
zEuNm97pbgh?`X^&wCO?Dg
z*TwhqiZ>%}Isa4_`J`F@DCZY^rj$ZWZeq&~q}ys~wuH71Ko(WD^9T)OQEHk^na}v7
z?>a)WWv#gqC_cO&+i+*?88!Hk`{}9cn9a_f$ehkm>@(-x^Ov_z$Y9Ub(ptWo@19ey
zC5)GidV0{i4@6qAE|e1M7#h?1B`DN{b8HaQy1pv#jicYj&6Ef25B~Cnr@_KTzl~2~
zb$@b1)H?F@+&(RgEYM%}LEuPg>CR6->T@Es`fA%Xmt7nNJ&DQai#z_3EiaQ;yg}3
z>EM0cNoxgbEf*8{@N#+O|d{}LJ2yqXbNWAKs4myi+=yI#h-7d
zuQf33VrOWCo7t{O4rUVWKGVqS5YZ>`H#4q{ek129x`P9?*TbyNQzm_xybs9%B`5sQ
zq%4qyG}|DuKo&BKKWZ;l!~Jp!pumuYL=hg}Pnj%%>0{-PiQdK_)s(B$?n)o4RN@8?
zo4SRTr5N0R@cCaxG4WXIPd%1Wc^chAL_-gre{Uz6D|OoveF;j8f=k0-OHJsQA9)U1
zQ40g6%+wk~rm~?$R3p#D53Muatw#D1g8oMJb$Ic!Qy*K+r(KP)c%Ak9tCOT@xn4%k+rXqM(
zn)|Cv3dG1Pt3~bMou$v=GN+x)6q%p^SQZ=Q0nqYCD9i((rCGZ;zt*VAO4U+lCGH+c
z$Hx))DX7xfU`y5y%6ft?PvbzA#lP?af}IM#Y=OvMq)~i~Q1ApaYToJKK5*3boW}i>
z!iQzMdy%j9NO9xx;#OtI(KxHA&khP_8qdtS3Onj%X52f
zm(+1i1o)^fU;|^
zSeV&-D`;7UR#gAwZe$iakWB1t|O3x3}V-2($wJMu0W`Rjtp>iumlSx(nygP#J
z$L+-Sj&+k=6OG>-FC>rGqjb$z*Yn{y~0+v+cynnV4|rgrWDHWk&9cq|mijtsXsP+QU=f=naB
zjbq1S?I_N)6mH%7fhDsW?`1@Q?*?n7EKp3*az4bF~}ikwFcX
zpsV}4Qi<_R<%L!f4~(fzmCfvtN0sY*x_?v==;rn0%ArTt_F_f5>Z7a=6`(5@QWatjzUovzH6_6q7
zhip4RND1#2?hrEceY+OG+-7sDAi+mnD%9t7x6frs#Gc)+z)2`IIysE`-&nXEkaZ&lXlu<+T7G3Z_RIXC)9yvU~TWrT88
z^ZQTRhTJn&zW9WW11;<;Z;L&-)**BfsXuB1xhJPO_o}i3{pnw=CsXxUF8baS%K}@HcTm<6#Mi6qwi7#k$Y2V5
z62w={b$nS~$JgRLWPH(9nHHL8)GX2wFB)bk|LiJI_ffPQYy@(|bUAFhkTt^goi1dJ
zP*1alvP*jLJ=okV>0F*qt=mbxy6HV(sNEP-05u`K+H1Dp^RnO_6?~Lu5)IANXh>Af
z60i|bmE$pEKiWXA-L2KU{5mN`-#?={DbYX?Ce?XVy8V)tkIGzSSnUYZ_|XrUYBwy^
zg>QF#pm_Nll#gLUAAoCIhK_y!uHktfP;D#U(GRx8tT{LTa$2_Mf6YjUfi$DZ>zyDZ
zO@Ft*2JjS^5wLV%M#AC*o$((ZY63-WCp^Thyq6D<{WC!Jn;;tOKgj8Mc0px_=ZLqAlCVi8-N6DI|?@diD&^It%b|c`?l+>w41;IiS8n64A1`5
z7-m@J(1bHur~|lx13DsS-U6z=VCIvc9Mtx?dI(==`tfKFrv;Ik5d|MZVDT|u5<`XZ
z69&-|stcjOmjKc6sDHe(`LRt1`SHuv-l?@!J$)V947A!y4jpTZHbWvtYdd=uxy
zC)9-sR}^F8Cbw^|#ePzD=BtU9_I;W&4q7V7Nv6Po%j^)Qz=6jI6f8y^tN7BpLod_zZ~qTtu#oU;AHi+p$f=B>
zV3wD+C<8cdol{u@$XK*#?boP2Y#Vr(vi*dFGpuUs3rCbicP6g$MXqh$-R$w$!g<9B
zPzy4NHU;}Vp-HpS1laH4tx6LoN*Gg;etCObx#RjfRtgrLQGVU^YPOZ^0WoOcH+T2s
zl|34vOnlP@Nt@^)QSrVOPT3`81=_-!{u*tl)Qy#qEo>PJqlPv=*q$;qzJg^8ts6yZ
z+kRldqjd$TZVv$Kbkaru)`r(jXl(%2JYpUItk2&9u%>Rj2J2lE0M@6AFv~YhK6$4K
z+#=<%N3OBLfKXSup+PUVH#0Riq;knjFmnO{8r(>t13dKhI|Q9q_rOgI6`^Gq?Y`0g
zU<)`a9H6`DR!NtkG*j?RG?Yoq$dSTkzcn(%(P`Vt@2y|}T_m|x)u8h!cI)2kvmt4-
zsO6c4)9uq%^!v`GDL=A?5IB3`10sMkQ&7=o7XZ8KKPxH#b}wx!S7Nc$57yH1Jl;zj
zEh^gb7~IB{9+!fw;#zUi#bK+_jLm~2ScZ@c~%`vveOD+q&sF0Ps!(Tm2eqx?U
zXhX1PYGWD}UmQ=<)(TG@%t!;UhLEXQZ<7by%
zC^XiresOj2D(3e<)z$LJaw8v)=kAu+
zbH*y%=Zdj~%*I6CRFq15mO^Er>Xn-i2x9+Sg2?;O>g3R?H^V-@$+qMhx&(cymB^I*
zmX5qmCq5&N#2#-CEdvNiISJ1dnA=*y>Ea?36t|tf%e1TdRHVcRYb#vIqODTi#RUc3
zZknHG>mYrcEZ)3Wf5r52s+Rr~N=#jB3H1!GsXwpfW}qJG)?VBm9Nn5G_CKSKeZP(!
z#_J4HFepu=ul>hXwV!2Aq3etlcVW#xA$gT8+VU0vd0`3~0C~5Zz~c<3X45qa_DDGm
zQ17d#DA?0F79YUl_a9gFc&ym^qjycp+j-jr
zHj+B+?v#Pz9d^0#JaL|M<9AedWH6VK5@gGRV?c3h8vM1Y{7Oywjm1SzOj_*0H!ki3
z$h3SR#@&Fe4N%cmmn*Q{f}T}CkteFU=s{82Ff>-hYK=%9&X;vHpq4&_t
z+zuwh-l}56N*&$9a!|TA=sqL7I-N@_q>z}YUy8@h+h;%{)xg#n)Z<*W7iBdMDjrBI
zG-Z{vT$OCs$1W*Y%--I0*+dvPVs$7hvEGv46u_ovXsGW>|Myn7Wt6g+mH
z@j7}sI~*UfUwPVnlZX;k^NDPE@Jk;Dpw-QJ0~}4Xun*l`bUUzUB^t3`i^%8SxS`5T
zi!{^4`COf}`uZcFi=&*AP;>mFps#c;aY9Pj{USeHDUV0o%%|t%UG`eggU~7PYh3-t
zrYsxDVH_lq#5$8DwEdn{8{@1kYN1i)C}F`IQ3EwkL@Srxis`Z%MYW8&9GR>0%gwE~
zXpcK7BsCe^vxeasnS9%wlMMYv*-CJoJfO2bl6H0kbpu%YRA2}=;B~}dlT}i(kHUcU
zG*8j|!Za!?iVSR95#IthK#a(@1#y5QL$oj)n>h&WoNVORZscBK*a{!{`E_IkT^y2^tO%rvhI=fjh<
zBm!SWuVacd4bz8g3N+ES=uAlA1%wqhX%m&~ug3wTi8;
zmkPXw&u&!09LW+aVaev&o_p&nHRcMQ;Ng2GhW?_>eY}HMJqX_cm0qNx6=0k?()ECf
z(egm+0TshW%d2we!l{YI`WR8}ND#%zXMcjk5=9xK87!rU7f7)LF@b
zL|UkfZA`i9T$~h8NX^vOa!%HBBV1hVoQ`IA
zyTCqkJBbEt+IsI0G~V5_EY@mrRF{$Ik0~D_uAe)#2eE=y)Kgr874br?E`9dyU4*z&
z^hHly&kvcA+RpqG{hEyySezPH%hlD=9vz#FJepO+9$oBJwMD~BVAos*;<4O&Od*a!
zU3Y|NaUSDs_pdeDZFI|6Q_;)(M=MMO@8O%k4P$LC64G{n
z-77xnInd_|JH&H9g5o(%f>93
zdswJJfr=CRHpb@>`Kv2PM$phZ(Bfj1Co~5wE>^VBcc8`9$)W0D
zoF-)WBcFrtzjqz}sE6^|-pMMoY(EJt+DnQ_Jg~HO7g{I0-2^T7IMut|(Ys&Ha8%RJ
zoVf4l*6p1I_4lLXWxZW-Xu>cMx*bm)GqT6djyK3k5!I+Bnp+U+MAoj%&~LS1h5Itf
zQsQIzWcm7JnPmQ?*$3(pO)*KJqRiHcL7M3!*0Tbl!8xtErr|wDP=aoR_y>p&MGQ0
za*)!U+Vj|vk)v$Y9&NLMlBTrEa4I$2JYk{1^MlReq7nyJ=>3*@-|)=-L{yRVzD5bL
z|6rbnMt9eqr)c{rdKOR}EeabmYJX2P9>
zm|C@t5=H5hR7(_onW@Pn%>Qdy8!2l`%m?AF29bb%~Mhquj4(`&O{cSRad(fTTQs
zu?1wO2^I6Lgdiy&Pt&!K8vmrK5%mhafY&%|0bfhL7z7)~qb#V&gI6Hfh>)GCJD_41
z5Qb;IBBCZ(tVCCNCy^}~+nh!$7+bm+Kvx7Sw76+;TeK$s-4jo-CUDvYihRz1n7<1$
z|G5y9%JNEZV*}(9O^3ZM)3>n`-G8=G$(G(T6P|<@CkU@7l`Q%vK8VHRZp~^f)8C`C
zOvz=Tx3NR(yY`^zxCy$w=Qw;(41*WyamUJKdZVgO}tn#%RbKr;UhMH7w
z)RQ~kY5%Sihhie{od)g_486O)OMnU}2mFF?{V?nJ9>Zw(a_ZUX6nzmXOo(CGAin#?
zbL5fs+aDB60LuTC^dhm@4#=8T(x7
zcA6GNgRdq|>`^(*pJy9m*}RM=&;U10&+_;CY|$9$EEo}|K4#vd`+YUk8J&9tcL#_b
zICQ-rh=%ik%?ZtJ_c1`q*`3|TOd`wMs?JOGB6|@;Z4$XJ{+?KI08#qq#0nRP(oLJy
zb-m32&EhC|;GFA8ioiL4woAMOg+AhF)6+Ly;u}k+1?I0@4t+G`FJ_ml_g1AXrF&Jx
zMcFP2&KIZrWMX?opi@-6*R__6kJq&pw&3ep3*lTXqlJ^rYULi6kLB4|Wm$mbn3tJP
zS9fhMo+kZ4+@z03FWjRG*i-ovXKbU^3%PPBJuKHBoB7YocHPwOfiI}YR!HwWCZ`0N
z9EyoD2AZr5g&6})YKcgc_nh;i&0L(WWy_$~dvg$XuGGN=ffcW7wc*D9sMWTMvf+o!
z5mOKBKM&pSuBm;XjySHY*4St2Gk}NZUNe#$u4_oj<3d6bN!}{O>ERO9eVP=6>)w(N
zQRvbBM(-L75*Znl0jHbg$_c-XTGO_B*7)U#tmhyqC^w4f4qLB+v*;lSJFDOqK
zMY6W|cV71mWX*F1ckA2W>ddquhr(%QSbn@7U72v-g=%XNO=D0}?R&|Yj}(UsCo>Ia
z){gI3B@Mnt*n$$^NoOZ7m=u3|H!twl)Qm-FmUK5SXCW-w^=~WP7X5E4y$0MLn4Djj
z{#?gTA{He|0E&2kG$N~$fHV>zNn;qyraO#dz~;nqS?1~_tY|OqqIh!6?aOMlqQIv~
zbs@e7XW}QX7SpZ4jWQ)(_iO^klQqXe1u$?*AGLM|V&e3Pc
z*FlWZE-;$qYByHLyl6)6hh9AYXc@1>N$_^5w^G3*&nLiu?kjA>Ze|xk|3a%mHgWA9
zm-A(N(%E~-CN-mTnR`sM4?w$ZIq5m5jqJH0o`c$mGoLz!A!z+Z+kFyy12X69GAHQ+
z&?L4*X3m(OkY!G34Ab)>TZ`Xspwkj9R<6z?bDlAQ1r!fVxM+z$v4u9t8VCfqYyAn}
zE~_+0mbH%z#}Xa+rwsc$*CW`kN6Z@{M-13J!3#y^&OYR9%HH@o-
zsJjp~FL!mS?m`0|7cTcR((SX6RQ~3>TCoeVRvhuDnrtr4znA^4Kmiqbq#l%$z>#`y
z;G*D2y*F@C=l0yDuUc7Q3q*SI7@)iV2Q%OP6End@C4iZqR)(IbVH7HwKYR-o05k#?
zfYb0T@|Iw^N_@D4BX~9~z!zF{+WYuQf8^m90pBYxHn(KU&?sY_41N{dP9t
z`>juvTnKJ&N88oYT?NB?MolJX{X>=hVsS?NXaX__nr*$!^{JbgSFJ(|Czi7ml_Mff8Ox1~MTJEuJ+v$z%isij9YkFtuDsmk
z;`6IraV#kgt?GRhTrPTDg-y^EnpHBU*3h>Ab;F|BT5E9P8ZlS9eZCpcz{FFOQENRU
z=Gi=f5|k>HLa%M$QgGC~ba&AJ=Txlrw_ESSX)Y1?>`(He*ae95G8b
zQ{3X>%Rpvt*DRM6kV)^i%Cn_a7`8ZR$fR2xvp(S4IZPhn$o!`msD0_UA7R5O&dso=
ztkjspqxDugbwjkJSia-{8h%O93Y-BDOr$daf(e{~N4_nfsoZJdiFZvP?Y+?fnt|rE
z&3o-+;}I3}o%h(O}X*`W6L@hqtx8yC)f`nGag
z{~;I*X1BJm*lz2@mV+->dNc=8SPPKC&Vdv*5FBGKZ>MkDw+N$Y6L0+4y!iVY)pN*fI+HV^DR-eT^R?UDQO!Y=Jqa^qGiH
zDi@sE1WfgM8LU1B>kyeb9Cpy<-q@jIb}u5Q1Ln)TmAL|c1P*P(t?9raERf~VfkWFO
zT^u-ZySLrwkR7krcHDY9C0qedmGi>sWKUs=AHjJA5$U_2!9L3Yy$c%b*1>sSDa_rd
z38BfOw2Hq7%Y7e|_m@YcRpIuDNU#^7(6-TvZ+-K%GT?g5Jz#BT5%n=y@^=OgNknf!
z>~UNeesN0%1Kt*Vew=cD%s1FHdZ$9cveFbxipw?^9G{nJUl%@vjbax3Bn6$k_NH8x
z0@B@FxxN-EC35jYW6;Tq5dMjSY@9eiHeyY$7nsZ9K0}^c0v1RJ7KoGuw?@hW3(Up5
zUf@U^)-AVO7O=oJgxUZOHz;5$Wq<-U;dKGq^iKiX^tynp60%bDQQ;-1V2@N6km!|+
zDTipxBHYf8oEeLAYl-A0$0cXZ^X_pKdCKE<$|*?lCF?PRNqjGWQ{xD
z;)nEArIj+%O(u}z_r@sRzDec_+trq4aK?rU?9y^)D@y%hHsOJ21VHX_|
zGXafE(OEbt*xP95GfBbT7X6uRxL#3Wdvn_1g^pk-+axtv_ZVT_e31}g%CiqzEn2p2
z);W>4Au;4-VrkU%LXUW(DemD>?}Hug7a?RH>~PktKG4WL=``d9=fVX|+rMP0#8L0;
z5+ahLf;l7?o4)kt-GI*~J}{uzP=qmpUQC?R7{$)T46kec9QO|F)wCv`@4)XC6dLf|
zY6W3sNhMNU9M?C-z}3g3-OEqF(ZWh7=ijjfvOJ#`4TiTx;zlR5rc~01zMJGt+%#D|
z!kgUIMVPk4>aYc~d@1=s8P8BcL|yge*Wl=h?rXl=qum8x)ZX%*r6YD>iZX-fa2Jph
zAKI-x1aNh^v-%LUPNXz>GYb&X2ljw*D3G?6)SBjHOSvo@3>qfoGlvYWJ>achI_ljO
z(CZEfzsA#{!N%LJB(-~RrfQvm*E#b!%Pbdz}1;uXZy%IyNJ%u?Mp9^Tv!#IExA60KZ
zh}1oY$#HU%T&z3dJtSw%Ml6K9m;5D~I2It58~_#N!$vs(DiY2SQd=lGm?i;Y*>-Zm
z9$tWDF?6@9c4w&sC-ki68e5^`S&QP?5!1Q4cb)*97cvBgZ@)5Y-843
zN3xs~F`B#Ra^c4m0B9O3#$?{EKr9fn-@j`Oz`oLb|B(ny@pQWAuX2Pe=nq0>8jk1D
zi_kn>K#}G0V8Z*$6&_>@dUcf7tPQ<7fe0t9t{L?grFtIiPajmtc)Gf8P46zR9k{D!
zD$vh3WsC;0hyMuNvpRC+zc9Vf=H-$r>yvmz{<79E`hJj{)A^s%DlL)`25>&UyMFS-mY;@1hC3h9ks&8FfH_
z51zU8$wne*D*~5M-`rBP40nq(ro#_!#r`Tiy)860%{c07A??<13X$Im;1^SqB%1o#L2q~SF@A#8Zr5t|57myYY%
zS<+5lFfd+^qDNaH=N}aLAA>xcT6zZ4eS)Q)yMHBhUl%$38Nde1j#!#w8%$;wL_Z0S
zZFtg#9!3BcLLo?eeM;-MufRVjlPqfIOlZO+O+Mu;upf?Yvcj!%zD?_0ZcM7D5J9|U
zBg(%=e$n&4B&D*52H~>4!dbxy*#C`A@+^5aqk^Z~p0SU0%2mKVB50)#xx9{+ur4ZA
zVVu?5xViiv>?eK9Pg$BOcu*@I6k%j|Y@rSa@qO96f%W8#y1Vpz?Dp|zS$>1GQvuO-
zt?#}c)O~e+&+SWsso6)MnB74@&4Nwbh;xU-cxTd^r!D<#e2HH=h%k9
zN*m8UU$0bzDzNM4ABY<;`!Y!jAQe*g_pP?vM@2K{BPdFIITVVXG%M98(-_fR){nK4e38a<
zBpJRoW=Bip4`TbbTGykP!KfK9>cfAH5{&x4Q5;~@FEA?nzectE%c$32)GQeF`M*X9
zM*l+=(J;NI;7S*PoO*XzlV1e~iUZK@7Sk8*nTPX!^i=7JuOe6yywF#o#NQr>L>DGu
zW&$&e;K_|6t%aV;o^IbN7_FS@{^F%OQe*yuBTT+So~eb4CSS&QcoiI{AN#F_&}gxM
z&xyFn4pGN^S`DMo+R){=Gt5dSfR~-Ni6B6$K*mzFE}6I)`swE^8M=ofByzRmt=2%P
zivLvV)`12xLNt-0?rX{J{fnr~zoJM_r|$oYu-eZ{|1ZM+VIeSgpocfT*LF;|uLweF
z>&t&?D=>ftSlcUsA8AFw6;r%s;1hBL|KSrjPvq2Hzu$JafJe$+U}olNJ@)&oC~WW_
z{-q)*XtMDJefS`%>rMSu7|oQUaP*Je^{wImQ2m*tV2(MNo+6p}+Mk8~8OWxnEokz`
z|EK*2-Ko;cPuJsfu7?EBJX2s@z0i7`eZV&rvn4Qvv(-PWwKLoKg?nwxQMZL?{E36n
zaI<~DV)s?G{_t7Khr!iBrcVOQjNYvFHVG?zPtzwl18U9a`^$M{9EER77JY$#IZJUu
zj`9+CO{e!~RN}0p1n`Yy`(ds7_u?W~zNA&LLmwZ~iWs*nJ7*m_Nwd%{B-Q@xeb!av(
zVyYnr8cQFk!^>+0??=90G|4i5Zervv-!uD>J$yLycvJKJis)a)@Xei?4H9Qxt(fKTnB@1lz#_eV%XU5Zhr_8Y^^oC!@|$spmvK4NPzv4HzC
zYXrPPWb%d5w+13bPl}Z$ruPD`88g7_30M0PXJwH}ug@QL$TG}>e(4sc1G2<{tbYfT
z8A(QW>fobNd6h3?xp=FkkzH>N+9QeA)7kH2vJ(FZx4$tm-7T(__J6`8fw2F9J5CUK
z2cLujmoz5&95637FfR`QSvqoHYA~;-=`-$sXNF^1x%w&L6}64*#Vq`O-3_!iIgdNP
zx0-z6w(|Eldh;(6dty4CB>2YtcNjIVeOnapewl=S_kOU>#}&Z)*+|Nxt_9xA^y~XD
zsGj1xibAtdPg>h?f8?p`s(xmnY!DR|aZ!_BIcI=302bcKR_oKPq3fNZiY=@~o!c0=
z2iPpexJcZ7>t}Ad9oBp7d1#~M@~7`xgE;;ii;Uxo(<$c{MAuuz_s(mr@O^P^M4C&^
zrTRZG;g5<*xR8c5AG!Z>>uB-wDY-bhBMXt2JV8ua(2y)32p5~)$o+iF08Ft=iDVct
z1N%F_e*?8^974ciYTx!MUt<~yAJ4u>H1Q??$p1pMe^`v^%gG-!{{LxI*Bkc*pgP9x&s2Qxsd%IH(pMx^#EH-ivOTem$-X*&}=!)M%R(i
zYM~R!YGJjJ-jdEd81
z{Mg;+VXWL>-n+)&hAr^M{vm1Q)khV^WV0pQ;GO*8`%ZYZq=ry}V4(XaND2jl@tQ)F
zBwsuI6cX?zB@aX*iMMo-C`I`HiBjS&i2s1RYYz3VDD`j^27z8KZnuv*`r&QOfE)57
z8?&2Jv#qm-2NV2P+pFMis3+&S{N+S_GdP36;dZf~$Uk}3?|IVh$-8!}?QuEb+30w&
zaN?*vRd+d8m)&@_JADAY3A!=1(d{H}#{F{SW6?V|)!zH~#=X1ySiL8sxs`*i2re)p(~mjvF+T3z`qu>
z)b^sNwP)evYxmyAsO8)LCdBWL5U=H0v=>p!0+4<`=@j&2o>|$(4C9nlyBU28)V5zW
zuY!vormPWy*MuQ>NI0GOZ2$E&3U5$T%$gr0{;DZ#1h4toy;l;otoN_4;l>>PD`dP|
zG9}f;*<*F#BqxfRXw?zBSHXQVkw@`|*5hj_T?(UGhP&rI-Fq*n`}>prbt=8B*HUtL
z9C{6?`ZKs+Q@l*V^l_DjC(2CqrAK^QE9?}o=xlvQr#$w2fKVYk`EW?jL!?Fj=jYU6
zYgPxpfL{uDH~JOpHxu#;t5qdWUJrCBs%U2QDYO_EXAwHsC|dho{@)NL}@kwUg<
zShV=E@!kchqK1f)vxGj9&f3mF`Cya_b(B(;xls|fdlTMbf06|KKs)!6jVz>%gN`Hq
zTQ<{;lpL3-mukE>hIPB{M_>&_-{-rU3W`GtVf{BD#HP!h>Odv(y0vc7%l$+2jznUn
z$GT|pP3`u3;7x{)it4D)E9Uu8v&PFC2C$z>rVgPn3-$OWzgHoQ0IFm4k(p|k`?KyL
ze#Wc@4*65$baY>V>2&UnW*N-?
zHDCY?P$8oAl!ko8W_d~&A*@e?lO#F&PYb7vM(i%zKT?o;-hFvWUf*~Lf2(qk
z61{bcmzH1O^CF;k-7a-Gt)}s^#n=>IM`5)2U^1i0jFr1+0W#$l5cP;JrRCd7z{L)a
zbN$4$w&&cJ)aB@l1MZ^dj8Cn;U;p{?^vT)0^R9Xo5Z)rk-%oqC<_LYGT*{;LVt3Jf
zOM_$BGopg;Gj#}jrt0XK@C8rydeO{FoXE(<43`MV*8D@id%KFMXH*ksYcei@+<
zr^zbeQ4Ay_fo{$u$Z&Uaq00fNuyJuf&AYtBY2Ska6=kuq@GJF3eK{ZtW
z{A8#ZAQjL)%*hRMl+(yMmxnf=Gj;q;w-4f^3YQ9R$
zY7?J~zA`3f(GU_1#}!a7<)gp^-n3E1}bN8_o^>$-K+wY`RcCy0Ft8FZoWc?+)BEnwS+
zNwVH^be%6-*L`m4ap|5(Bn&F+!EI&XbV81R&CL?tEpCEg6^M^Se-@r$6et=HipP`-
zZMO0KmJ0_u9Y|HR{;`cAu^OH=>w8?zJ!>^J62b|&Edz}^T=Iu?rsWmQSCz-=2e#m?
z%#BL^lVAOriI;Nc_25(M?tl>O#`VBj8t>G`Nlj}tADB${^b>!PvJ-(N814fBBv3Z|
z@)3EsfynCYSi!!BbLnO8)tOsMqje@kCWVqfq%J=xxN+-#A#2fwA><8W!A50&e1LOU
zmlguDn}}i5V!(zmGvi>1wI#J+Cuuj-be^xo__SWUK)4OdP=FA30Cyn%YnP;(8GHAe
zlyZXRb@ZpkOMRva!PaCLS|Mv8YZ69lt5XFF6a!A(JeQE)@zw0t*r(?caoqSw*D`
zyg52lYV=Av>^B@OymBr(MHJZzSWFq1x;L%o(%d|l!Mw(Cep#TYoj1}WJ}!89sFSpi
zi`3Sq0e*%9yjH6+V(4U`u1fK1}%Y&nIg)HfqT~t-lIAEadX7Q}XAo<*mojhF3srYFQ|NYadWm(@xl2W>aqLE=!62
zCUXqGN6y9=!U#)sPo?F*Ub+A;b&~C4)VEziu%d9|g%hCB-xdC*KoC4ha6mi+emmFm
zz^3q#pAE^dk$jp?IEyRG=Mxpvn@j{e-?(yv2{^3e3ILA0sC{qTN-4w8iPMzu`l7H3
zJ-bWl%6qh6gws{^N@%oz#_)3xVmzE@Aj4Q<2^kifX(c3G1;7#QWHv9&%_mJOj5YtL
za2A+BoFqmXySmiViPq+(`}Tnc`cV+@!T&!#+@_+d1@e7vI^>LPbRAg>JsmnUw#a7~
zUcZN82y#)H5}PV}Oohi5`7?-c!)Qh#Wnx-w)v&0@sPt%uW_Sc``g^$_y+<(}CUVX`
z+j@o&iPSdcmxQ15Ym7t|WLpCyW9>GF^ox`XB?oKH@EiBXzqwzJDvdWgoo#$m_c-j^
zc>?!Dv2VMfn#%s$f?``({CG?s{)T~=pMDe{jkx-L^AaMq<}v(GH3Mf+0{=+se$`>?
zUhZLsH+NAY)r?J)FgIxd2qCHnw`zTyuWi22w}dQqtbWYI!%~qAvxFvtd7U!giCqby
z*=(yq(>{$P#NFK)l@3%*ai&H>&ATvCd&NtSKejQoSTBhlsfPGSXB75V2
z0&;=8=m;uf{mhODHAKMcF9EZ#=j#Kxqcm`7FIzWlazCQMvoY$437On8w%k@VyQmy|
z*rP|jkP)g@XrFyF5cVM6xUwsZ6QB8AJx1ak3v)mH^2h^idul%yxqiO|bOBj+
zqlKFIRUw$KpEQCbI}ONf#-z^aIb*&w7TRj;>W5lI5quO*CT7W?dsD-S^0B&wakA@z
z-m0YFXZGNsUX*^>hF8s_h<(A~PWem&G`5+lItKdsswXjBQu}_ME*iOPA>jYKq#jtB
zMAR#O*@HPR`zS1GOzm{<+^V_;rkvvky07UQ1dO_oB}ru7C&(-WBT0qn8c)InG|1-OYAA!7AG22`<5VF8Z-B+=oS{Z(dFGva@s$}BJrBDL$$^Fy
zYGw+Ojz_JV$_Dn*;xG&i0&&1XhU}jfZ1^D-qMGxEktltIu;q$>7Hc*QMbr=AL7HKIeNQ1J4mWyM^QkSetEhk~-5WXh*m_4VNKD@T^7hE-MqSNod`!RM!Rj
zF?{|gi_5Fn=g(j@`*-Q=Y7aeJ=?o9&%44oCo5phycB0I}-ZaSM(aPluCPza%E@(yi
zgn2uEW1j5a&9%$CzmtR*_NJtCY=bzfZdir#E#?)A%E@m2v1H^{VW_Hz^KO6FIxu2d
zPb*jFyithu3E?_{+SPIN9Mm?MND&FQmLl8aB3Iwqw?k)0y^ypM+@22aDf+pr#|
zOUBrH{DwE>Y#_*~qM)eae&FWrmu4~q0?orFP@HA58!zu`2I%!Edp-w7s(=xkzl_8P
z7m+-1B-b}ia;eJVs*xco_^kGf&+$!JTZ;(R)kg_?MyC8^QTmj`c-cKFth%A^VaV3h
zjqLWMW(&;WOua}D)X6&eI`AzJwV(xRlm87bVbc~J8;2xoy9c=G^w
zgVNH5flRJ**bI&eSy}#z+*t5;Hf>|>@LVYHrW2w^;4eM05N{~nvTv=`py+sqxRx?A
zE*GKmBmOt^RUugG>nlVj&4jjLMsnb=EpT{{=ud~sN%NEAr^cBR9_7%)#>Tg)t$QM1
zlp{1$LHn~|s%fkVB7zKYVxzA4w^0SKTUImxW1+y<^S_KK3c>E-G@9Z_RaNA^br*EEsIn|>yS5p?T6DVx6TEN&&h
zf%H6tq(|D{Vu2@&b#YZ63%zxgNhqcx;6s1vqBxQ8cSvpof8~ZF2(svc=MTYxvIJ!q
z+kzLuw8^80OBmLkEh?q*y3l%@4ZVT$RjI1iohqDcGauXBOtx5HHMeIZNDxKN9_)AF
zyc9}_`T5!r_HZgL#bA`eTnBs7b=7f7qinXRweS=r{;jm&OP9AphwAHw?
z!GTd&A=?^fgj
z?w!3-Y=Kx}B(Juk52*$(Q`tnl#>k&~Yy%;B;-=pWQ6iR<)@|ez1=WBvc*<&gz5R|k
zc(XN45b$7(;}op1S0T{fxL9{#-e!>cc1cnB@~anC
zzb_G!RIH;Fz0id=!3lszx%Lmo0Ww1Vrs9Z^$-Rg{j+Rg^q&$>NE&K4Y`FB`DgnjaT
z*Vz9nB7{_L8PCyF_)fznltd2wQ}&}gnNfOcN3;0=l<^oWGEOI4j6KbL;gqGG@(I!a
z5>+4~`(6Bi31tWvk+kBQ2{U`0n7xn=-!p~uBmRNpX^#MJ&$oJ80cOvZ4elt
zdMjymFT<>Z1&&zYK0dCa4(qh(w+<180+_wZ(AZL~)_G#$%S9cPH^8{YCv@Vo+k~88~L2?4`|DqxGeuTfYI8<4K0L-(u
zk|eLv^R*XuCq6wUDyCror<%ZK6Y1RgFrxrsNp%teFYB_RcfN3dCGY~ebr7{hkDR}C
zdzxpj;n|^=<>8iGAc#c)5{tBdttee(wAwiaQV{#&H$908bfS2V3V&U0(bW|YUcHG`
zl%UN2*yd%-&Pl`1M?KGkN}(s16C{E}iwZFCvSQ|Kb5kTSva{fMFW^@q}s$^soE5&SX!3*
zxM<3(r>t-J^GotP9P@$cp
zl~I_A&t<=^G+~h(VNj;sADLo=3gKlI#s5l12ms0T+EVzm^h^{28Gl)fa4N~B24o66
zs^_gIBuENwtea8SW;4OEP*ZB*w1v<{6gw^V(NrU0N1|Gz?b+ow)uuq3(HHC^R>uYV)X?Wdz^9NoKsCh7BgcgL>85&XZ1A{>&)G`_>D?R516nN!z
zuICQUKuYb^fppjt;aNUi4lJHDWi@@MA73bMVvKhSz2-Y^JPS@ZBH*#ZI)sk4lGF42
zbRSJThni3W6X<#Sg{Xe`u=%T736E)8`}K9N_6UN)hZhH)7C#O-gWzhGLGm&twPJpre|cdYa8Xx&A;dJyfp6ycHnYdf4<~8bd%2rKJA$IhZ)#^r6JMCd&}(RsP`^PQ^F=Nwun
z{Ct2QjOQ3+k4ISKhkgAJ_+E_ora0n60&n|&3kdNY&WNVw=c7ty`Qa2_Ahislwg%7x
zL|u6putyFQnPX91opy>uhBl6P_L+I%ND*7P%Rg#N$2K+tOcM^B$J|ZlBETGe`?;eflJJz>LE_5lQat+bPbJb5+roZ@vW$9=e8YQ)Pg)?eY>TB
z9*I7e2XuGP2XPbLw;KS+DYFnc$Un_{ATzpARD4Ko`q5)0kt+T!ey&sEJZu`Vvmn#Z
z1R!0Hsa(s?o?Q2Xl*x`>v_$I?M9_Ue`}TF`JX@3KHz7t&&Fj0!uNub^j;@;*kBLQh
zoD59PGBxKNObiR$x1ux3uyMcyN9C#B@x__e%_1#-o{G`hLAXD1A=(I|AY=*FIq|Q|
zB_Ffo7W>OxW%hegG3re^d1N}wr7C=HkCf_m2uO)CTx#;e7<`}B3bP*fD+lL}17Dd!7qr}HXY4VQkKpB8jwhrmGnNI9
zo^~-r`BrMmsrfFvERbmXOQI1DJ*}Y=_N(ZP4xujSp+k|I!({!K2OK5aiIv5|xpy?=
z;U6U4d2YOR`H&)pT!pXh=pQvHA8rk8-3Nwj{xKAoC5jPV%n4XBALz*(8>fMuOs3su
zeprfTg?v6z9cEJH=DUIV5Fw7gg!~{v53cnnr9yuEMiGFSmbT8PXa$u9P
z-)_=hMY|deg`WPi8SDc0LLyagUHQ-JH*UlxjIq_hXX#6~z#32yvx3s^0HvS)CC9>W
z57a|(SAYLGw*pUalxDLrkVzvp0gB@ON0CdeD+MLLqzex19rX8*y3)U?EBV+vpb)kb
zn8S8T+~iNK)2u
z;Bt!%d>7@s0(wTAJ@af1$Adh5Gg#5tjLhGemnXx${z-x4EJwySN<*FO?D^v?w^CQL^Yx)g*b&Z?#Ar_$hiCZs!xIs>_UwH3
zfQ0+R6#TFrIn(F$SExsYz20?d{#>>3Kj6*NbgT?olp=!(s&6Q-GQf`S8mZMawq4wW
zes=XqBwz^`DI13xDI_5;2^iE`qA@maow`6QyIL8rbF9w%6aHeg
z@y43~6+ggjO3=Gtx=okSh@m~NysjrVgJ8xs#s@hI0|0aRhl5}*Ue6bZlIc`@%qw*>
z^cpSbHRWGSl$%&L
zKE>Z=gL}O+?}6%--hk)j{MqzQ^V#|tXlYy~Zj>~gHj<3CM}Cx^~taVKfrj0E#s~sw;pNt76gfW)yJuD|+KJ8)JmMOziA;6ia=iy+
zpyqDaCT{C|WAz|&eshKX;6_Blqo{p(upu)IY~5Ql3JC5t+;CU{|IhXHDamWc<=a5d
z1Buf-;|oeTrfxt2te|g2q<}~wT7(mwxK`|P$b3|4LVFrOz6}e-u;ia0|Fz!C^ucPV
zFPMryuB=39p@GT07-4=0KH3qU(tsQjt)D0FAq4))oPzw!sG)*_K|0e+?;Hul)>4969BZ3`)
z{~&RQ_^DHgC^{7D<3-aU*kpCD0zV?@^M->pmxnuk9G1&H-`uZyN}4iD?&poJucC}l
z*^%28$ysbFfoD(DyUJVm&cOI5q>VDlJt=~2BpUS%Py3box!
zj(lvhjZs;E5S=e?m~}_%WZZjUsbG#xvig9}Fi{29Z?xks={x<93w}hsKRDzV{!!5z
zz+fnAMhFb%JjFt9pH&YI*(=YqrEGtIb!ucR0Vw4cKq-Hj!V899vbbt%cT{~S+(rWv
z;#$c}3vj45V6S{h!8h1>?nM=o{CR?~;hKiRjKF-Sh`25UQnp)_jXFrRuX}(l$@qt<
zcVs6a%gXs@~G
zay~3#c)bKclY^k?eS>HS|1lH>3~kmsYvQ-ns;S9&1!3$z1b8dkfZ-|&Fv(&OKUf>(^|HkYZU{VqueBj$7&LE7^B_h5gG^hIB>9>eOg?t#E
ztR=*e$XX-tKP8|Ec?`fU7U0?_EphcF^6rahpcia2;d2f;tG
z?CcxparxxhlXb9rgwmn+WbPAE6%De#4`X`cZN>6IjPxT~i#jWiqHdFhxN|lP1hPLU-$*usSY{58T&dzcDc9kC}zG}(^
z<`Oa$CTMI#ANveLJ7%M2`Zga7%VHcSZ9ZtB=~UshcvbX1VQ>=3p=jLlwfzl|MPTlA
z*S8)JjiI0MDnAsIhr<1%*Tv}o5GhbF1J^?1ug=RnTK-3?t6HA2*PYZ_S}cox=1W~M
zK|=S`AHB5ccyxp2h#GQzMJx;LfN^9=>Z4*Z76P2#x@nw)A7+Jyvn}pK)f?r&2qS$g
zo!aOq3aY!cv)*yrU`%$7S)+`jak-fbEwK>`V)GowWO_3V1
zjlI46YMaL<#}o)|NM_JAkb9QBqOWItVnUg(%F}Xt(HXV5cd0o0xB{;-TG_&oc%T-I
zAaFBNn-H^Li?WG0H9Awf_K+c+B}5c9+(XC;2_M&$xbp^X_WRC$MB7*4z>QJ!SAwkp
zcL@a+uAYUm&*Wa}YC3V7nN|~SJ%n0{ZM0`PBE3|fBz5Hh`&{0gn19TF%RZk|FE>_(
zUg&6HbkPRlSr^=43y}tF^L>l%J876&2&Wa@Ee$^|=VIJ9hQkMDG=Q04U?v#vziu@7
z&3^0+a+@5q8B_^9dG$7tnFY&|vv^!aX!jG)(`(>Db8$jp5Y3muTBDA}p`#47j8g#r
z3TeQ`kqhO!p6!>8KS^jm{A(aw{^@`j0nu~Fa$HSj}M@z#&Hi1#WtNkbI}
zN!yHoJ#B48?V)Kchn`_J05De=z+9e3%QvnLKwxeVw_7*eS^WikSs_TP%3o>aEDL`;
z`0;|WncC)GRDh-{f}fA8WK~%(ZDQ(v4wv`E!l=hp5AT&})lNxqD%bUPfy=m->+w$q
ztvM3f`CLV#*2(-8T%m#$&L8*GK8^+`npcxf8tlJbj#mh&{x+H=dn%W6?NdCv3+0ok
zFYodD323hkVWweyD=S4tKXxUKimbRuCh#UgHCP`5?#b^Nx=VXcM1aS1XW
z1gxIo-=JJV2+AdpVXxd+Ti5#Dq?B5qcyw*Ftg570%WbSSF{)%iodGCqPbD?s`|TqW
zo2=PB(q)s=Jt`$P+OvtXj505EyAf_dT@GBpX}$G5*WsUO&9MnCgpaOFHxDx@xXtA!
zcsOs;uiwMz>E4BELw$zua$Fh=-lbV}Zoav=U$--AI8u4No7a+yncEsk90UXO@B!Yt
ze#^8clZ&r?fafaDSg)=PA7*H#q0%HE+xAGkh9f%uBzrT#Ie2i&J2;CBp|mpr-3|(c
zo^7d4KD5|t`Pu55X_@4u=i)c5AZ0#Ap{*Xvi
z)sxP5q+c+%ab#Y8aP*LOA5fsWHhgB7=~rbxCZbm3*ct#zq!f$W1@#}qL(apK^+?6=6{jwUvA1i
zw-5XNb{2-koFR!<{^OHlYLd+y2Zde!SyzErWskJ|RvS0rT#3DvJyuPgcb
z692}$lP}H)Afb;{UN=`QH4{fYb@_Cc#qx0j@bMRP1#sPdpyb-;hQuYfoSDkFJ<2*s
zasS442>+XZ|3O<0TQ{iaN2Igox4h)WvnpRBGhg32Uk%4QkBP;Gr0k`4&&
zuQD~EsXnlQ&C&M{Uzd93o|X#$`)dFB)E$QxQTya}4;9`M_4J>UG#-HITDBBhxhCFcrFCO(jc8iy9~W?PkRH9Q8IIba*3!_`0{aXN-6i-IrA;-HHN_6x_=m~5Gle-bTBCkx=4pEsi22+EUD^1
zsql867?Y2DtKl0cM<6jy@RtsnbZA>iN`d81XcbNgecOaPm1{!=%oI5~H~)GgdAjMudE
z@{iI%i{b)|v~$QW{MsFxn+@Lt4~rsKxsfp622vpPz0{=#W8%4gq2Bb2%43QrZnmI<
zGXiMj!(TM=h9qV>x$wQ9xZIg^Y9=uC9|PAh{<_Y~2M!K_ZYI0QVJpx0K!0Fn2{O|D
zUo-eqoIA(zUdSY*xd&jSX9Y$er^{{M`83$QJcYL&?c#rvc0qBaZ|C?=Ak*V|kMe2JvrOPLrS!
zGUbAw3jwvW0zV-wv_FHoU7@>ni~Z+~YX5?1Go6Utx8z$bU!tZnzkv|j|CA?S;C~ni
zjeq`Tt+ByBfMWbH1bwwrm}iX3Y6MCoXbuW8K1cz8ga7V(3xeiIiB!y*k&(!FdieeRAe6
z5WD5H_Q-XHx43uD@+Sp%2Km+r&?CD6o81lOVDI6CPASZ!-ORy~y#=$l-$mo^y!u#b
zyAGSZk#XhB@YQN0d-2{431)%`#?RuH?ncS2^I1`#qt{^iiv)ArlHgSc2`&R9_<8=H
zBsds4Lqz3k1tUBl!IKaYtoRoR#=+w5_DYF1ma#LPp4}n!<-Yi5bQJra(NVrq=PD7G
zkkGzvzTA3rfHWnAr3Y3hSFDFVb9jO^2Y0=^gSQ3b(pF
z9uP$)+@^=#w?q*S@YRi>)5ONjC$)rTLg_QT%wxYm@6|ulkpRMAQLv9Hd;I`Y76JgY
z;XeSh^k!C87&0qs%JqN2adWsSfG7XXaRGB?qD1}wAh~(tCk?%U`QUHmcd^(u7|`gt
zr8jtd;s%dfYadeG<+Ma@oH2Fnv9bCG1|NApNT_T+=B!T+ko9Z42eGl
z`7wn`i?};IV8^Y=@LTn0g-t}S*QAd~wMnP||1Qe`^Rd0YC9BLokqK{>`G>5ZY4<8KXn$F};_?W-iB!#Mct;XsCT@=5mjZI2c?cKKG@upY{AY0GrxKzbH
zLQ@@%Y3D`9F*k;}-s94L1-hs0hXXf2)y?=F7`@%#pd_&SNN73Rxhy{#xj07h+Z?r-
zp&PTB(R5Psp{xVK`dD9r%sL)E5kV@d97=5pMTs
zAcPXIO+h%S*N9Wl=)>KHVJnrrx~Dr~4^oV0x&}D$dBA+`Epsf7MAF&arZp&O_+O}t
zAoUMMeE=}(cm>mr{w#$1#sTho0=RD!n7^HeafGmf8V*yx@fq{Lw8)cD+q2G}?KPwcDb8}}q}$_Ph8H>W2hTD;#9CJz8xj9Xw^W;&djq~Tz#w^X6JfapbuiFXcb=O6BEi1uzvM5^K0Y(AL
zPQ%7e5O*nvyXLRB)i@!@md28+5fJD?5D@KO1X`mN!hFfHgRm@!UIU74op(#IKf~Py
zj7Ta_XzgmX|pOuHy
z-l}g+SzVlngZd1LU-lUpQqi%N9oxzkch;(Xtqy@xDL|hWr?whTVNS7Bav?|Sy9iIn
zply1yFW5ip6=S#es%pIuEv|W&?hrDNd!W?#v2ex1QuD6d#!Jj^92`V|$kqcQ`}{8&
zikvz29%!++W_LhP9rY0#&8?7oOLt-VWq0q@P9oWKEkRZ2&)wvxb8CQv^8gZ-{tF3n
z10=k_N%?JQhNkeaPUeS6@t+Df@NX3?0R?0B8o9QIV=9!Nz|gPu$;r*oZv$lL_e83D
z19)IsORG?)3g&U=!O$vqvD0C944!Zf5Y{~+U&xSWQplTjo#?koN5Pr$-L!4&Sgk|s;bGR)!C-9n7e7rA
z_OW(Aa&nsKc2rD(K-NG2NHG8)jqk83gKdS-!1&E&129XQ($TX&l(ov>1>wEOf1yu;
zj4w5bL1kRD155g%5aLS@h;Q6q#Fqm?d@q7R_A2p$1Jxej0OG6u7x8TfGBF(5SvPjV
zME{7w4s=ZXrK1*Ov|kT9XBI!!S&76EaN0e{ob7L%cK;dRw6*9xOGC%(Te~%Ax-j7&
zBH_P~uM`CNra}j=ttbF&{EM?fuBoHrS*l#TM
zeJ=g>st9$M8uNH7UI56-FR9--c!NKf);(Z%1H^XiL-Am4rSOsvPkSpY&Zyxd7t>@w
z!daK@TNL0eU2rsE>B77R0ZaX72}K2OmXKFLSeNZs+bOA`;9$-1p>Du7^|=1U`hnrV
zinNw9Z9jd1y+d~*OMOFMLbB8BqWRS3vJmqykwiwaadIrVo}EtrDE9yFWS4sNEIls<
z4B{?=Hq}3mbR>%b;u_#0N9D7C@$>(R>~0G({tMY%t+O_QOOk{O#<9?@8V^&$w7Uhj
zqhYsCQ*iD8!fazN-CYk5@|O~VgyJ1x6JhHX@aV|x107N=^ykqnGz*pD{T78#=jlJ>
zEN>qRnSimnLD+?ecaIGlHO@`rUJ#qcwl=PCpX3oW6DhEWxgG%ON*D^6pB2TqXHzzn
zviQtK<+zSwKMbx2+%4W-ka(H?m(1F*0?61Jf?iAgP6Lf&@fDN>PV6l*{SWP=#KYL1
zJF^#VDhvc7I*LFf5r~lZb=*sRU~@ANItXxPmYv>m5Ao!S_aqhoneIUbb$>&qaQGPe
znlU26JT#wMY!J#I09f`?B1+riAWGaxzD!&YrvpeJ<#0bz(
z-@PM~=gPstP6!wH9R`YrTGgcg;<$EI%~1&QAoeSjk}UaX80ghi4EK`6#2x(3be4y;
z>IG-WJ~P4kTW=HbE2b!a^oQdHai45L*SbFr>+Y07C0I@xWUIA3B!I8Q?wNvO<2I<0
zA4(=-!*JQ1gtfUO!;gL+Ldw(0kzx7GS~p;TnklC0u7z{2NlqrGpau2Od(qJFC5t@N7OX={;po<1%C0Ftc%MRG;m|
zNG
z9_J{bo4p@D`MLPPW5(p#4l#sfFN7za@EK)@Av0Z6NQattgitkWZa%HZCkCAL2_MuU
ze6p}3l0GUw0kM{uL9vi78y4GoJNyL{(OnLqp(?YV(Q*8#89yMfzB`@|xTY|FdF;jMCatBt&EGle!R1|nenMG`k8Itg$?gx)}480vc
z@A;Fz7$70=WQg&QgVUFCnVi>M8~v_JUav_rz7abIG8HXBAYN?P+Lo;^Cb9kpRmPf;Th3(c
zq-#q0Y_gQ%q|N(G(m7HJa7;@ZcKEaUk3tvV?2hxr(OQmESH(%zkO2kGzYb4L^VXK)~`TVlc4QBLr$|=4}d8`h67Y
z6|!&>;3_=C?;~m~KR?^trJ|;9GgX<#9LkUPkbH!N_=$6qz!JHA>k$^m_a+{64L
zekS&rRHwkeZR~Vy%e(h_^TRMwqw9);q6H~Yq!W~vGd#A=mn=LtEgw=N>L9(+=vW5U
zhhE*!o__Bc+EZ7PeJYrokWY_2LmZ0tCCv8f1>@_7bT999>@1kgG$-^TVN)og?|mtq
zZo;!&SyNmqd}U0P5wT6JA>9>xxuja8-D`wQ*O4)%Lcn9pZW2Q47rohtT8#K*fa2VK
zgD-eev}9ymD^zW(7%`z+wtl0->fW5z`!{Q88U;@h`1I*baMz=m>@QYF@lHK8Ywcbp
z8hD)j0KZjZH&AX+olu;U=<3}vC^z07ZuaFxIwq51Bga;!?qVCQfkfRzeX!`k^Oz4W
zC6tN`lSCyrOLQqK*On?6vKm752lY63T)4D!tUP!wxssU(O@ptWTvk8)&nw?7WJ=}Sm+(`hP3hME
zjueR6d+7Syt+Uv$U}MYdae*J%!7+KqEL4wMT?D;$C8PGDQPykdc(07CWVok``&hv-
za%7?K!Z1lXlaa5;v8zhl7`|sO#N@pG5<~v_1NeB69hq2}Y85BLCD_%8)b26q^+z-E
zKTF*nv`n?_a+~YtdG$=gjxemXV+%iookK9jD3H;95JrFV1DsrG!QtFbXN>|Ip{h4!
z1K`IBapqK^dBi_w%^3ZucL-
z>`1F9Hm+&ZKiCywtnjGC*4eV)LtLHu)%#
z2w23QhbEBXiS(gfJ}FL>>2Xur-PEFwO2<8k
zTX-AX78MScJ!@UzIxywmN=VaGUw*n%O*rrge0*b7NMwb^Hp&;;9Iex^sj2i^o;`co
zPO0Z}p*b-oUp5L?GhyOHTdjI^{<@&5q6~>sEucs-A-L!{E}E)+Ufd>ObYavNuCJNY
z$faJ7vVS1EzswD;9_3Fy4Lh25U?J-Z@Df0zUu(f?=WIN|QTx?GIa=Yh7|JvO%_*Zn=!$H$BX*TPI{_ON
zbU$LGIU)fY=beza-VVu(Y$I9jnTlO<(_n2^9H6&g
z!qqdb_<{X!CuaIo(w+sj6)QacwV;J|M!T5-g
zQ0~LEk~nfCSFb*ur%Iy>tC|(w^i8oS?U5oxGZI2r`;-p^xnLJ&68I>8q((eqtu{qU
zZw_e)!WCBj$7Ilgmd`E&&QT$afrv}N4-bo+pbbl%Q4|68Jx4m+*}gICE0Ov(ix5O%
zoFAXZCv{x8uV<^w3+FArvSzsPSZJrO{m^ofs*m%2=fnVe|40X3b2>QGu%b*W<60#D
zwQRlX-Mij9f@nt{6!&6yG)@nu#>cq>x0pB6Ppw2gLg6~d*J;E!KKi(?iiA?nP@NeR
z*OnRYC`*a5#gRGfI9R!1>*D%qY2{-(*C!-5e9q)
zq8|4AI
z<3<5Y^c9)daVkUKpqRv6;0=yCOYSm>n=%@pxoj`vzR$DAPI5K~IG`Wyc8UWA-vNVO
z@!V~T?GmPv?ZM98^*UoO3k+40{NiI)wX?IDkquOV7N`3I*b$yBsz493RK+uc3vQ(l
z2D6bxuHH&!WG0$RH~L}VQIDU7Yn*XWSKOdZXEJ>xuJb8U0?hzlABN#4gP;TJCHt>t
zTdp(2Gzmpf$hh&;S6i&HqVXoFh24}`&!_e!Mk<}jOjIw<)3U1$WP>V=?L9Z&CaAMo
zaZS$Y6?7RS%=YpOSXikJt#!F_x&_hL(p9WZn;jW@Mn+ncySbX<;WhM0c)3Oh40XKu
z^qC=)lLFbX?J*h@C}vR56-2C02adnCRaFr6i+o)an?x~gZX^V27GS2U}P@qs+
z>w@iljIn7!y0jdaE$TJ_7mSDnYL7>+#>JLnxm7om5;{v}^w7T`u|1Y>G5z`u?Xj0Q
z2?EdLCUGfJ`q<>5eN_T2>w%@Rhv#E74BSl@RPXP}KWU#1Zf94z3cTl3`_^Y++*3Mp
zo;*7!>!CDEiHd!;Gq3$x)?>ZO;`zE&)@%SOG8nUpeb#bx)8)#aZV`}
z)apJ)vlZ2{AM`QJ=UhYp<0mn!t$SV^)YD_{4x=55iVY5_@TVWE)IoPzRzdWg*8F!=
z7@@~v#ywkFpSkC2z6`>?Lzkl!gQvt;5h5D*MqRZACnJAtRqEttxQ#wJTO6reI~S5I
zGz+~?Bsg5P^aD2cpXvBUloH%eZ>{}EE_g3Wjut)(El5D6lO3J&au+TY^JAyytx%XfzcRhKcpaEd{GaH^@*pd2Cfu6hccIow@!T&#X>)$S0s
zYQKrz`c91(I+mYO1yyNO5HVHThj0uVNeW{8%<3Yz?h04+F{r#l1Ip(}nI@J2z9X_8
z2hY!YoEkl6}GC>274?y|XqsMAl0fv(+f>!IiC51VtYCJFrQ{`pm@?HR+Ai$dP>-
zRpJSLTi-QJpgUV_`P*UcyYfn4?tegfyik%UECXxa%Hj&c#q0Il+xWvcHsZ$XXvB3R
zg{L?}Av`)*37_#PF|)$Zz?7gsF`VP>iSBel+RSsuxz7ZURavzVdiWf<-~t=wR9E2Y
zfm3kO{D;1z2HrbYTts&FB-UTnQrKlGM?LpZe;ht9+W}V8Nf95D#y(MqKY&eqFkW6H
zP}e6kE5TZyyzXbo=}9W9SrK+Pk%{XVrTf7FL7KJCP#@l1nj7vq)Zk$cO7Wk=gA4e;F7{yz=D3Y_o
zNiy~OQ2YLI{>BPM^jHlFLmjn9>auUP-O-9gAisWsY72FT_)q0kTkS!b*Fp^e=RvDX
zDr?5e@nmW%FirbUzY7FB3#S(gsR$Z8X^2kEt$oiS*o7fDy)^nWX4S$tT%yxp`(cRNzW;QOOGZ|YXw}(3b^Q&yeboW=R6cGP=zTz5$S9J4%&k(L{bk~;6Nx9@f#m^$+Yx39CQ*zjfRdQO}Zf9{u7RaOc@(G_q`2t~}LpK9Tmt3OFC5
z(?|T5bDnXmhbbgTz&+k@_j`pyN`bIJ3XL`SjNpTgECoVs!iQjwd4A(*obh;ZG$mtp
z1QQ2}YvTfDs-1=|z96Dm#t|8Mxl34O&LWCU5Lm#R1REWi$B1p1nR}#CSS9m}8or>A-Y8R1
z@lsdOSV5D%#DL#h^8exM9fK@sg0Rt<-LY-kwv98kZDYr_ZQHhO+ve`r=AHM`y+6LV
z5na_?QJJT*vNN(zXJyyp9WKde9%nY*HyUPdp-;m~$@w3vc5%|oFQvxs%BlqlR4IdQ
z5kK^&iO@3jB>rG+&N(VfJYQ=qRz(=drLd4Iul+
zC7s-r{pXUpSne)q%EaaW!M6eid%#wD0fU6c5j52rzuNZ(|Ca~YV{xwMiPD+R;SmA4
ze4UqT_`w>_m;o}n>%F6b%>)}(K^C=(OI0&?6c(Y7PBHYMWX%vx3CNb5kg8aEGUn=mfBly77Mj7U
zJ(AV!Kk*xj*)@-l&pu8TH!i&9nKvCj=Kmr&Z(7wb(gF<-QUY}l009PAq{;GQQp~v=
zFt{e{so#LbzIy4Dwj&JSQ`^qr91KtmYkq{o7JG4jQqVP&2S~mjLHiGo7
zUTBF8-IhBV{PxFyqMhhkX1j!=uZ}MZwhLX;#bwKJ2L~B89vQm-4l=u^&5|WT8+xtw
z<>H%x!vCm4#b;`pWeSRGY8k6gKNu6?^-vB`<2m>TD`@^FaVw5
z!QLbLJ3})$Y
zUd5)<{!cNbegDzUR#CHheTqEVdSzqLc^8LZ*L>X^{le}?>osdudsKr3vvvN`2NOx>
zWt4DypCt3NRVWfLqxnlUdSxYsuh)&MRX!rCSB*GWlg>NXPr_m<;TdKY`S=Ge&h$hu
zcEiJ4G@JjbAOD46{ZAw*q=XHl8fQx%lb^EPsA`4(k}Ep~L1h0?Cn7jKGZf;e6g;Ip
zNjvJS@vQedNmtXb_A$qEvcK9LMOf4N)+WOcCSSD+``~SCZiScDxQ0#`
zz;ND9Oc`!aD*kX}BfWhQ9o*8oVUpV)_I|`!4luL&^!>aVyY*?yyWyk!8oo#G+=_^=YKgw8i)?XdH|--9rpG;{cs2C)Ln(
zWjVA#4`*|n?W1Uv0|vATyn&4b2H7J&6{jR?ve>}x48?M7di2&tIgHN2!XP`*
zbOChChGNgcWyE3jMON8G-}uLn(bBu=hw$V%=i&*BS2e&oS1sIA)Zs&Z!fcyeuI#m=z93qik_Co
z5t7X~0j+u?6N&)VpdW#}KC0t$AA^*c2TolGZkl$AMOI;hZJ;QS&FKU
zMQMVBB+FQGRe_B3ICzz&l{n7{I6J_;f;5?_96dSI9SKRc;b`uE_EsfHN^mSE*r!K@
zl7G)fFXaZX#(=;?8h>(H_tbE>g*q-~g-(iU8U|si#)Z`v9Vp?Xq`71pg(J!~|Br^g
zBj28yAtVM`x?}lG@!mepjoJiRil2?lWIuYSqcCs`saTo;Xt??8cgFyFC~3$q9I2=u
zNl<$@Xdv%NQ~V6#DN~{Jpy09xQ`LX9uIiMv;iK
zEG2{K;iLw|S%%hp@IxJs9nQ_drkx^C
znF@m@@$=i2cCNbs(McK50c~63w>4HmbtWNpzNVTZT8PJKv2tRN&MY)*z^Cu
z1-)$OCp0xf{G_ol=f1`8zA*ZHvkzJuWBwH|)=Y&m-AIu~!%^Z;C^Y(9#|Gy&xgfI{(N!uNw7sNn7+kqV_^qA)|i^n*IK<(s@1^8XJ23cS!XYw
zM%S{Q`Qq%yjJJg%df3OGk0q+vms5Yg-I>aLyM)!kW}mV4=+AlRh2zcJX?|kA-D!R<
z45a>@&q3oES@o_iilztG^aj_HA60Isd2uP~c|6e??1Jgm=$0feuWT(`t;Anq3R}!P
z)Rg4Hdbi46*srTUJ-dG(%e||F(^)Bdjs*VMv%6BPNlGRAZHJ|ZM1*+HF`
zD2u7V_OBzC$xQHNOBm`4LhS||(~>Vk`bc-rSe6G#!OEPGTm1+J`w=q#*FPapUIr>`{Qzf4_;52tB~f*p7WO4tgm!
zd=#)C&VcF9xLw4MtDou;y%JJZ34fF<^SoK>8J0a99Ow*%dn}5h>BXC?v*;|iIX#Fb
zC6<(@j%WnAVVN%L{aS%64)OdLL-$mD-y`Pu`cK=ZY3X8b}SznOnOx+hO1&EZV&ctw^u
zJ(goRE_^{=?t%6#04%=ziE7rBIrOKJAEe$kSjXrJcc4e*U!u8_sL7nvu+Kx45=eEz5`i#4Pn#RPJz5
zTXZ)S%vy3abz|QioEp`q@Ka%}1-^s{{#vscGxzZ`BIS-B|beTH}xpS7#3?DU$z
zgmL178`Hq5=f_2lU0gnGDXF$ZB+)$#{_UuZ9cpt0cmMc!sN!T_Va
zYu(#nn)5;`p8zoSCrGHRHFAnI;CGNquM6a)kvd?^;NMI;%$Klb*
zc`-^tDDbkZNQ5H%@22sNr%*_FetWSGIBxru$gM02sRiz_LCFcRt^`W#Qvd*dfD2)D
zctp6PU^}pGUiWnQPsDg&okE2viJJs_hTVB+%uMzm0uHi~@TJyrpayxRE0u+U2acv&iogOyjl_;?Gm^h_B&76aZS{(tvkfsT2Ga_{AWvjrM}93;ozo?tL3Zw
zUz4?-$sT3;(zcqVeQ5^Uu(p;Zf3!uoV?qB;in8IDS~-4MHGM4u^NMdLqdn4rahR0%
zg(=fYXgOhz3wD=^i9KNr|Kt&V+WE($Nt;41Gg!lkHazfjA`B
z!_=5eh;<}S1>0~W?&E6Ap9!p+{>0T#JQ7$Z@kw4>_f;aL-{sekm>VmFl`cwEUu1Se~a!HJIOH8et+EX
zyGths0^I0OA88uW@%uq|H$Q=i6ig=42zjH%V@w}v{z>F@aa;4^o
zlWm;_YD^%3G9wj5nFBzP6_q$?C(kE&i+bk$+9=M|L&{JS>s2Hx8aeXjc7$>bU
zfn=-t0#UdCV2Z?3k25=5|Zfhp_>8-un7Ue@lM7L6=w#CUTv11dc*U6m9XuUb9`F$)J$LuDyGCb)rE
zr)eUCC{k4=^vOJVThs!@%BaDq^Ygja)a<6ouJJRs)}D^AM((6lu7v(bjVtrZ(QRu<
z@6-%ub}3=k!S%Pdud9n=0ls{Ite#ilq}A;u3}>51)5<49Sq=hLZhkFtSj@eYnYBAV
z=@c$&OIt3a>@5YbH0X5X@-jK(x~(z@U)x_GUQi5Dzj3k5t;E!(*3`&pOHMtr)S+-C
zciX!`%XST2`hS1_S~-lM+in3hcz1wyHGTwS)S8dXP({$KgPyBKROZ74k8adbHXxSEVw)!v))gy1sn&P$kyXVX=v*5WUA-nDouIg`*?SCj}VH5ZCqLUDB&@xsMfyp(g;tx@AYYSB2CmAh~w
z*?id+lAoPDe4rGiHe!(ia^IA8FRz98I4gEYABnsrvElzjVSjD|HA`M3d&^0NK(Ozx-vFT>P4YQ
zextIeOm@SKC%6~rv#4xbGSd>F|dmW6ug}9(@DM6$&I#3mI`LjM1
zAs)SIXN%ec+Ge#-0^YLDB-LBGbed3t!5V^WVA5Y#fZw$lBy?`gB!~l*!~GHBo&H^Y
zI92+MQ&tUus3XRlnw$lL;i`*r%vpSm1%VI_0*JKMD7U}S$SNUzN$oexi&r(J?eK5O
ztTZ~iux?h>e;|q{e9O5?Sk&ANCyzK*r36gaq7SAXzFBQKRZleXn9CH!mOS1QWh}{s
zm@9(+ez6f!?hFKOdAbWrvgcGNh67szJPvavz?da2m#zn-6z&>gqN?AxGwpK0mrV?Q
z5}(n*bPP@|Dx7<<@L9p`WM}1O^PZnZIWjxOihd>5{veivEod4QP-@heG-I+Wbs6KBl~Ms$Uo4%D;@chtGS
zQ`1};#3>(Yo>^F+z+DG0}X({pOmMgI9j4?fW)&!Ho84)dc759gWy{ZYCi5H!<}rjXgi4bGCp;L4SYi{cijLr-wxm<#Mev92S;EFTDB(W8P+ILsb$b
z=~-4Q`x|wpm*8N6=tcV2ca4P=@z3J6gB1%_7EUDp;otKJVBmCp+ZcRMDDmbE?5I>p
z6sieqaEITHnBsW-;v0U#y}(hw7>N42wE53I&P!x|wxn11_>2ytj@)C;_8pw{W54}~
zmSCV?jV1H-eO;}rHYkpA#8e~8HyZ&u1h1GlzeOs;PM0^W*^L7B0b9cUiCjfdC(be3
z2=qZNW&X6JDVSI7M*M)lpD@8N{wL#414FmW)>tUL-G>BmZ2m#|#7a
zGMK11;?y}}n|_Br^d;#?{DwY=;D$dRrZhMAc@|mSyMEdu@!~h}OnELxrTzXES07+U
zO#NFp{FcADzL3_~5kvns1sj1p>Mlma`;UA9?VLVKI2?DWKwtL;U#HuR>`@+ZlN`ECFA}MJR%Vb{P603f_`&aQKFjV}xc<4cF?R9beR1LZ
zbLXHI6rD&-e{W~(e|-zQ3RV9SMRXJO$Foqy;E5cw}5&O)Fl2?FwGIj--HUZ5Ch=5zX=sbxohmow$zVG$T$+-!`!G&+74
zz>b;0URY8f>c8Z96Cciud@BpjS$_W)Au{lT^W-u|vnD26sy#MEU|zM|eo(|~ELE@}
zsU6R^Wt`B=pf)R_kPT);LiyK+0a=i!S5amzRPN)nbp8Nyjj>Ufs0ZLi)ZLz#nLA5I
zuJ)@S>wmIxWc)gjt#KQ>0r#}B{mD-6?9rlIUA(aDcxB3_W6BsAV$!nS>*uo0>sd2S
z9F|f2eyzxEKNp`RLIypM%>LMVb(H>%_(F$UtnG{t)NvC|Plch@$GK(=&r$h&o
zH?_?HXDD#4-c#D{x93#Xv@&ag1Xg4SACoS=Cmvo2%y`>d6(<)#V3Q{jxn-e9Lnxh@
z9K%wvmV5xk3sh-p0@C#>EW`bDad-#~j()B7U^p$>Pbx7OOd>NV{1icCGbe{`i<)e$
z-}jB4T_Te|`KZjJ5#^1ZKY6@$3bX+kXo_+D3CtW)1}=zpZ3O1oBUXelAd}8Rgd?4FpFVbgHHEp5=?Z!F0Jsa1!qse;IZcKE$4(K7dlGG$dlYSkdlYGw#J;I!=J~3BW~`l-hV2yprP4AcnFYEB<2vWg
zEmC{VUuc{kO0sF`AM>n8$>nZlhgO^;gW1Dsj0SZ8<4SftbxnLUv8BkN0G0xpPr+^eH-kUR#!nXQrE{m2
z0_cLd$-Y?=ROYEP&N?QJVIJ%t6aT7j3BT(krlJ2vov{h~j=Tf}(@5PEg%Ti<|f-o{L*58R6M9X`qQZ
zvj-E(R#aYn1e=&c$EOCpD~2X9;j+G}m_o>_AKW5T)EYN3@GV<=;~0+X*0j73WEi0D
zpAQLQ47dt_ap6APBRW^fu_@5C(tIj=t3P2!kM;ymj?^b(Ec6!brdwe>B*ctYUb4NO
z&)$@pQBbKBP;GzEpLqNu+45nuKOn~&!$~TT{o`Gw+E$QL;(aLr>mp2KMwJ0rj&>Kz
z4f8I|X;mreb2me)96o
z)4y+Yo%ynlmzM7IXj#Q-8JvlXO
zZu?daILU52I@4t9=oNmOtm#a82mGtZ+Uov66q{NV0N2e*X(yWa-llCEO0bz9JTYu*
zk^w<;S8zL%B?o)?pia
z7wn8i1UqRv5P8$K_M?*@*tZv^Z|)&BDbE}vGnRh(;Fk{NG}PpGa9o9n6U+FwAfmfS
zsq}9tZ68KnQrg^|@eL(@2b##)QjOIEk@J=f>Uwhhuc$S)f&cOxA+=0wp8g(Gq
z{f#x=ZCgC#W%3AUmWk@*T66b08y+yDGI;i?>T4T4S%ULSjIM!}KRCk+>1tBgH?26Z
zFAL*(Z@dPu;|yY4$CxeW+C$fwJrLV?kkG?LxlDM2>{KZxK_!=h*awr=VY{Kibrv(b
zKBzfS5{d>dnMuaayZ<=*NM*v}_-X0YwkCF07)11On~ZvU_l)
z3*Gav6|%bYw>MZGtLu)P`Aq1DV0U^uJ3RiO
z@Q?I+SszBFF6vF@N7hnVIOP19U*K6SC|-{l#xk5GhRHdO_Y?ifg2xz6YWR#`#4Lm%
zvW~YU*|fbfGh!s=6w8C+3Io4?bL-aO&$Hb-ZM-_LBc#B6I`xfKyR)-F?!|A#Ul>ka)0R^FrfAVqM#?YJfoy~!y+FPu={4fxU6@k8k
zw1wY?bC=%am`5aj;U^SPO;P-cA}I6p@#5kcwpJ|nJ+4d^%lTIv#W5>`>CltQq?6p1
z$+WQ!ET00OBnlmLU79rhWX$bw&r3BdGLpaW
z4&;WHXPzutR~QZKKA8gIcxZuE`_2qIa$CIF$&`H1^RH31eJa7F_vJUUZQ-IN<@K+h
z{KnkLh%rjniaN_Ql2)^jXEnKHE0~hR%+!XmF{`r#F7%lubwKjne0874`wh@2pk@gr
z?N?w;p9pXseHdEkK7OCbC=T<5y-Rr#%Pc#EL5>;4Mn4oI5|41dZHnW$(4>UH&1V3l
zzCA|(gnkHT^NBY{dxbf6IiwydZB9>g8tvji^Y@;xv_i;WStz;nxKweaZhM^QmSwZ!TEyn
zFL@c)96&Qv`(LbKiGZba*Ft%5W9uNO;16dQGNDi_&Y>z|#&wZM*&!(>u;Gf-?kW>e
zTWHHON-(0&G05Dr;FN4b$n916LS}dBUEwc`=m7|F9*6+{fLjW<`<-Ef$d1peVG*tx
zL3B%h11BdJh!k`u;p)1b1xb_ekK$yHgf+nrsg!FTQ
z0EkTaFDi4PFF7o>eoUp__yTqgA(ZHdC9ipuyJt}uSWFJz&@xCm=G^uhm5cr3x?SFD
z`RXd1mSMo)eQdC`n{Go~5V|m_+jxMBE==;QTs>6CKkDXj%XKYQF0OgzQH?r7SDfoS?S}6D%K9o%V;{G_&Sl&B{vzz1JLNSV9Dzs#PI!%Yo
z@rW|;*FsTxag~P9Rg_nh=^aMw2tY)7nIFjOBnE5V3wID{-@Vt;p^Ih`OYH`wfo?GM
zMt=kji)ZyIf!;R7+O%TMu^FLw(p^Qyl=9CafKW*|5aQz^Pe8fhgOfCG03($SK!*B>
zNP2tvJQ78oA7OtQBcyJqXe>}iIg$RvW-cir1E(#y5wBnzp}dT&yqp4Nw7?^^Lr?6S
z8LR6DK4VPp2@wid@TuxvD)T9YW%N1}qHiS6%yrJHxpQ5wfs8D7=+s8f)T-&ZWIF^B
zC5G55pAHd>pe!;kgshZ>DY#w{6K*<6xUkMoI|HJZ0X5VCMQ$=oefZG@P!vsN7OJoJtmwX`EU
z+#|)bB`+8#!<=?>#dZkd*Q3m;BhO7t$jRw5tH(ME20==|F?01v*#w~w=W5!wKG>K~
zcgb8j*CmFZ@_Q76s+a?>%4g;}?TBq>1
z72{|^EQEZjpHJh?FTg&b@d#CknhrRlsI%P&AE60mum!Qx%`i@kTQKs3Z-9afZ)35T
zwy`YQ!;&vLsBCW-yFBB&BcZy#fuRXWm?oVgMkajZ01#^;F1%-Ww<6>&ekDl+b;VU!4j@QSkJ
zaeXPz{CRqxW~qXCrqC$K*bM~)WC4GPgKDeFOy9Aa)&yvz6{2~X+
z&{fkVEQ!CdIo1991sL(Q(*n|Ol$v0Vp&zCZhbgH9z8sh~2uaoG%D4PI
zGP)C*Uxv5g23$Gc$BB`}>`CN?lg3+3?eLZULIP?;Y>OYkl&w2j7#x7Tfv
z1!7qCe>{@Icmm?$`K#&2YwD_EQ#8X8k`9Lmu%Ju{xg{G=9HBDU<&W~3%|cRGE*?}v
zv;oOk!Gl%0n@ht}<10%3Mmd=IsR*AT%yoJ_9}j$NS!TRp7!rLq9m!
ziZa16T*DMQw|P%zrn5rJzF_}{xwZ|uq0`-pr>c@xmf}*J6iyO6>B3~$B!OWHDsqKm
ziQ=358%m}^*UR}+yD`{a7++qy?`WiodS#lG&p#o#BCP}Q2{X-Gp5(JNI8L5T$rnj~
z1I&dr6r!0FQ^IowRp1WrYNdCu76~I$S#S$H=pA`iY*c6Vsw#2l
z^Govh=6pg%$vT9>E_m#>l%u2Phfq_Ysdi}+Ju8O{ZyfL1hf
zIyvvLroc|uYg>pii%Lzc^Q%QH1)=DOiq)h8beq$!>B?V#3f!K3T>b1@x{7OSrN?m(PX5x_WS^v)rJd}gm{Wa0cF2fQSH4=Ev0&o4fAT5LA`6tZee&S#rvDYWT~DJ96FtEZ`|Emf@dAb0
zYR+M-Vi6JJL2upkGI15MNsE^Ru@@v+GEnfCu^x;eAd((tZ+6ehLUM7cymtm>v
zeR%fPG`Y)N_RG*p&H#DK!uHFNVlQ$ooa-SnU4d7U@Ba^tX6J4Bs{~*DV(06S?A2dn
z?pIkaLo2y`WUW(MFURuTa50;K5^G&8h^BGr8A(c8MI!bwFd)7)=Z;yWYgc~`@LNmHrKNnt>5VL
zbF1H3un(g=KFFJsr%BxBLSS!Pe7v0B=WW|(vEwnf!5o%V&K^t^G%ve?!tsmT6ch~}
z;GlfEm2nWIeraLm;Fo;5tM?4H;MIJFQkfQ39qOu~SLf#T>&YycNS9MtjL3nF=SL{_`t3!RPKJDD^yhON
zU@g6qtXCm9YfMR>E#Ixing?Mrf|EbMa8WWgI#DDs+~k8Rw-&BET^G;vV1;zHI9E@6
zO|lL@@23s$At?~N?j<4=6G{gKqd8xA7y!<{e5%&SHmbEZUsi{Z3(9
z58KusUgDk!r@J{@Su)fxjQy}7bbv!Ev&DDP5}uH>o^;b9yv7=gtv;j23lX@Kfi5$E
z@1^^b)}c-IkeIqtHJD27@^Mbnpm#>Gcf0{NcDGWapk90dr2EnC=pKsA399q0hRl@2
zV(nw=JCPnrgoGKII{_=2)K-FxZ%J^CBB6IOeN+dJ&h}!4)JY$k5|a4(+=c^V!|IDK
zns0k5Jtdi!sv+`b##5d_+T~g1+6!m%x2O>dvCkt2GooMca)f!jsl+_yGn^Lz>_LAn+
zHG-8a7!944%ehmel6X_oEHmuE+$t)h%VwK30#jDhDd3ZQk#%Mlffw)-HMHwD&Rm-i
zVh-KlIkJPvQm^)8BpMKkJMc0h#q$vBSH1NvHjoQfCn7wLYvL3i{C$nEwELEbOv&ZUo*SpB
zrMU+C(@#w~+pT4&CzZQ3YqKmZi~CE^x<4PmMj`ekh~m|1cPdlws7ebM0Y|aS&&nN+
zYJVw-&c!$y&|bNXtTu3;KZ&i5;3q!s#jN6c)7N%N*E-6LtgeQh4vDOe>^jVb*SHqy
z!^Bragm=tsx-D>gnej9>2N*}~CP#33Y2TG&c2{1FV|G>F25-s5R`_xFU4XysKYYLT
zU%nAzayR_u;wF3|4qJnbVs=xaIeoOA%5i#s%;=|jfZu<4RvC&NT%p`=W`AZGr#n*F$
zKCjUVi+1&B)g@`YJ%eR=4dzHoXo|(Wtp$RX*Z@Y1>es}I*n74)c2aR=QirSq3#@77
zaqZad&NzzX_e0>um~UOL)(tIKGxTQTm-M7PTvZ^;XQWFU>E%(u@%Ga@`SsC4rFffG
z>%=t3otjoF2X-wUJ0I;6)xXTSpwlsYGSQ8;qFajtwXyMknc;8;3Qa$zb@yXhiW^&
z-GBOX|4)DJTBk-?UESSitDOh7C!yo5uSn=d>f)kaefv{x1n|BHk>0zetT-t4SoDp7TrmmByBTp+`!u4>`&(QSAn_nu%%GRY_e4VuWM>#aTvbZA
z$>By=&w6Z@95?c(e0`sD&FoZ0^-$>pdPW{SgPHCy0Abdg>??2wsEMCNgSOqb$A@3!
zo1|In{R>F@w6jSN`R)L1>D2QJ>_=0dGkudp_MhkAeXQ!)K^K?ZL32B$%64uzG^JKs
z=Cz=1wnGH*pu_Gf-pb9Mv2BNRWXjoO=t~vc_$oHk(513dydMXsRu+nk_-&cz$dGgK
z-ySLZR}^;4LVgcT@aFhmYQM4Q4p_X*csm+xv1;wg>9+R)^e2{csUx_uvi+&vZwp2oiN{6%))5+t(2wh_jmWBA>?Z=doc-rk{+?RDjd^kLA`w-PgvC&IcX
ziZPrMM^QD@Ba{rR?uq4Hq|&-w%`I@K9@ARtihsecQqT1Ekm7GGyuCKCoM$(0je~JdPHwDn!$r<$aqRJCZsqcK!oe}gGJ8gHZ^=SK!VG|J9>~0=A?tIb)lW1
zclGwa>G@4ZE7zyVw*mv-<&HNi|0#|Y#T%N>NBnbNFE*KxroufnIU|!T)tgt={cz(#r>SeBOQSp3Sqmtf+cj|;+iedAxn8zqk;IVKW
zbvjvad$8)ozKk4Y6|uC{7A)EsL2a|Dt^u*zXb$nU($?Rv*py?ht_H&_p-JzVn+}@se?7=$BO9sOKtCY0{p;U_1
z-n9>w?qO@sl)+sr%W2NA_F&qWxj+5S0ggZ#l*(M_$$mM
zJ$4xS&1^sRs@0_n77Hw$DEnMd&$-L2sE|XK50DP~GYH|qaAFo%ayW*oP3VHj9j
zNH|pcuzap7HLU=A!5Qu?ZE-ai=9hLcHB1GB_HJjI8FCA<*|
z6|;^WbGC2zt&4ys_3V{)U*oYg2-fMxjEwO=akt(}N+C+(;}{cMfD!ov1WeSC=ubb-
z!>-g@^I&*E%@AqRxrQgrD`mOjW6m1}PxxOp4d5W`D(NU0j+)
zXlWHaJPq7C_CJ)ZHU8-J{5G8{|3JXc(%cP7Wt~5@8cS>ZeMOx2LJ(xXB8Kve06H%L
zeHgB};{>ba&Fa(?bUD^3&yD9Fnkp=G4nEt#@w4^_!5>aY$RnW0Vpo>+&&+jTOW>Mx@;Ru=m=PpEv8(bH1R@{DH~_4w
zTN|hFH{t2}6w%6je0{a7cl$AifduT!S%BnB8p{wx@pMc84yh@HgI_8Kz1H@}`OO_+
zHn6U#pkYW7m|M9WoOktauP9JmJGHh=m%zn)ha|?QJwut-fQ~GUR$lXSDf;<$5kKNU
zY=_8g(`F32lGVy{#+qTALotnxTumOWYTMqeIpnB#xfLt(jGd!E^yVyK0#kcILmAu?
zHX`AXZ9cl`ufDJ`o$`Vz2hxa!;be*-r0oo;>zfWO=qR1#Y&-me$Q5099ILApETX6t
zDjPl_5K6J34rnX{fktrMJ*tKCS0|xT@ok9(YgJ~aQ#AK~c1|0kc^b9OTtmVCe8+85
zB6A&HI3&Y`?{33-)M*T4nKGU+A!3?#zn!Ci&ZA}%6uIc+0OM`al%$b=NW&>fFCA)v
zY?W@3t+S{XO#fsCm`2=?t-3Cr@8VAN)dOXqDuP6kdaTiV8#Ny;6G4+XvT
z*mICd)q7E4gaZewx&omGGAeI%c5dh{N*0;A<*l#`{%$s{qf|=fq1O)1aD7-(a6D}S
zm?>vT7f@Y~m2sp8J$dMd?JCeYFln%{H(&QFye!tT7_#K*N2usvdN&tyZyXPo5e%Og
zv2pPZ!rb9)GJWuEWZR?@Pc8HhJ)A>cPAApe~BcJs>uA3@Y?4e_5fgI*HI7GmvV@
zOql4hlBW7ECn1uNG1gV^4h*g4%TH+yAQAx*tvX%W7Dsb_4GIttfJwMwA~lEjV^#G@
zq4*eh<*-5-r#f;vBjHbmCsJt0;uxB6kxp(1SHXbYNPA
z8NlwRPjDSbd^VKV)om-NO-2(>H><72B+nQNx|waxohNQfFQ*P$Z3}hd^LDR{kyN8b
z5V3?hYSidy5ro~>rwnY{5Z#(3;+yxTQU_92<(+qA%0~tJn;ooauHmV4N$wkKrPTR*
zC#r*5CMdgx1W~plAtskj73;@ilW0Vgz5A#1Fx;kyV-R5
zthwc44s&ZsAe?Z|wE(VUAok|T85^$(j+H;}IFZ*~QH17w`zlj)Aw>;L!K)}>SC@{h
z@^}k}=V^0(_h*Iw#MF_4uc?Y%eT?Etx`3@Eb~!Rh_}^s06$nXh*pxOd)TBxnNB$loMnHk%;sh3ZYp*36cTo!cRt7EK*Y{1a@08
zt)NAC-Gs3>b!JC_l(cPGbL|lO;_DF1uo}&4zsG!{SA8r7a=uOEUao1Gq=8LIrv5rD
z*rIL2Y@;MwvMWTwN7hx1hzbzr?WIpcnirBljQ4*I|O9r5;$IFfi<
ziFk?1t*Wj^2j7ig)xWS?RMn;aluqLHNhe09lwM0@mHBM@jSn65zBe0L
znTKpe$BK)mNSMWmqzeFY>h_XfTz8Qp6vJ8;m!zvde@bF!yg*U@r7&rToAGxgoBPV>
zJjeV?mih>7rD9NB1-YyybG%M$Q+iEZpZ+`3sPVhdy=mZs`Yq^yc*VolCT#ZPZttGY
zJH@K67f%B=o$nAYTtD-4>a>7Ka!pg=V{bIq=w-sF&t$I&q12u_$S;%A7YwT
zgvB#=nSeE#(wVFL1|zFU>uo{-4$OW|OvoTJRGS6Q0ZqJWuXpt~E%}O_9`;>k-p}cI
zm|e1Fw}MZ(ft^3PL4|Dg;cA(@mUn`BFjUDh2Df?S?Ww5cG^jdR-IjyfD6L-I
zB324@FX_!#1?Z-uNzCJ>A$&ZQ9g79~x4uU_BE`Ol3K5(imXa2d6o@#dsHT*nj+k9Z
zrlQHqGi#B%mAw*68^mPRz9SdG*-f!?{J8gV
z(6u_?;rZH>pEDsomMfC!7UmsH8*lrg>6AP0J1s3A?xbC=yUlYLV$;vYnh%$t-5b!z
z_tCWegxQ_Fbr-=(qhr^t2U?L9b(Vl_W~ZoX&5mq(#D1pay{#%NsneXu+l0pb&Rd|>
zjZs%61G~(s=;Wk%&0{HyYSo^gdXM5t6>}VpC%z%)=iWU{#N6?E4^o+{$BqU~XHzQ&
z1@0K|fu0ghONful|A(!2jIOK++J@syYOS`^8qba6byksT)v<#44jT`hpFkueQd
z^X42_bC*c{nCYM?tn*WyPI
zCpX=0(YR1G#4?N3!BaDM>2Fk_;?YOfc_dvmjs8s~D$~VZW(l(prhL;}WV6x1Yj5le
z7n*Uudw5Zi{|9q&fc0s7Qp+OzIVSUGW#>Q}9uX}fc`PG)I(z@Lf!2VCI-aGDGI14x
z6^D$AB@*2dycL^@i)9LX)==gE)g}#9klMiSwLgJsi=30pw!0Fwr4B8b-Ie89t4(@I
zSYmITx-vEX`m{Zhr7Jc5r2YE>#zPd<{X*#0E1+J~vB5gmg9Z_;(MJ9eS#oaQbJz|WwN
zM)%EoZe1(xAqXO_uTakohqtFqE5XTxH^a@0FPbWPt?*)$eyy*f6jk7+CNNedq>U
z&T%)e>{lVBRUc)v79)l@VYHSvb*$?XcGSFT
z4V35NE*_q|@2(OCN{5p@kZ0!fDl&T`D{1{mEew!ot}yK5Q(Z-ir8yDp>rb!A%z|lC
zf65!V{M3e22w250T_Y*})@WwJcFCoM_sFG6faTCmhv-V=H;-iOl;3_sN2(pEldawj
zUOmZ;#3tN3XgWKl2u6of&&pr1L0YLV#G9zk!|JK=My9RivJp&F&GDI}OFN*{Q-(ns
zQ!vvUT23+Lnj4<*rV@2zmsTRHu|Ruz+a?y-S`0@6yzXuoM;H;#8Cw_eKMY@
z_NDvCVw0Hpb7c0~sP?~iugi^{el=2oXW}1tcOVKUE0!J}7t(N9v#@G4j)|rJIdcFJ*Wa
zA7i-1a6>8S6S(SH^!_@Q!7@^Nanj!Ll7Y>MeNKqXk{Qud2EdL{3W&+u#udoSHi*{v
zy?SYfLp3@js&rVTNMQ;`_SB6;VKf5|i4pHPrexMO$h-ZXC8aHdR6uQ``8gd_Q(gH{
z6sIPZd06B+Su$%$Bv8+vL
zDMlztDGHxgui!CI*qK;GJced>4AUWCVzl!`%`Bc6X=m|_C?6SRvNmqmM^{?!nV9Zq
z$qmDD9aM}W0x_7c+TNsPFOvu^BxVxGg_?cE6MwYoNb;IcH;2MfhR6k~%^Jps$^5zu
zl#7`#LCTPla!z7!4cPo&s%C?58X|}AwUfUB-6xNsn~Hw_G=7&P3qDw18rQndR#i5GSOG(H-QO1Gs
zAXKG?D<>j&^7`$OqGP7gT`mj-s2}l?M$|mc^9lFfQ
z9fZun_c1&8mzLfN;6`q-B!m!KMkq!BQBI3!WPadM#6L=l_G4Z1Bk*z?jn#O$*SRW&s2TO_QjJqdDFDbgcIn
z-zTWN){{aRsZJ)2)ujT(5>VXTTS;khzO6i7htb(d`5(;lJQy@iRy-z}F8LC#W#5m@
zq5n7Lndbccf7yfUSq7o*r8X?pAOEg4E{!Dl1Wr2hgx)Ry_WLA{bvaNrg?^HE|6!F0
zfwR=WE+y8Po$hb58_CZGGc}~ODFKf)btTwUg2NB$nkKA!H00MbxUc1xi-w9n=iJ@%
zd%r-MrI7jucLOmt0YD64EhVV%q4P)C7#0f6ihULRPPi2MZ+#M+!A-iV^@DmA^$yLLxy3T}SK
zQj`S5bmNSY_4myN968e=R%npL3#W;vrF;u|G-~*H!*?{)w=VH*_O?@4HJ5#
z9OsNxYn0DJ4w~h3L+9@!Blpls1ZDYx?9H9jvt#bdN>Dv;baKq1#p1%+ptQrmhWQ-)vIBH6zEvXpefL~j8LjwL!0=5
z60ka!VIgy3zta6W5W>&pzM73+?|X(n7aOluk)TZ1e-v-XU#eKdH8awnyv~N7jt8*p
z@7b%SbW%|7AMv}@Y1R4#imfKu?^5WIBT^;RTBaVtP0YFVIP7wS$t{uU&Or}hsWEqZ_>60-EVL0J+b$SI^&a7MY#Tgr8x~L
z4Wlx64W>Iur87)~OHw?Ggh@wR%HKq&g%HeBZ^ermKg__r`G4;Kq<2(6r1-On$OP?!NCjMMoDIL9SbHTkK_pmv~T
z-D3!o$SqI}mU7o6)*GXuIu5F$IvS{~Y5|=trP@-#Qb2!-+C1Hc%&D4k1(H;u%q6$y
z(o_{3(VhscQvK&sxl>#URh(T-s$cPwyBe0EqNbX%P8y(Wm~s|AK&@PKfpo~Nq|p9-
zW%`i&uJ9tqqS^&?U?E9#=B^~?L;*XM)1
z3-9WsJZpUlUsdZqPR{zn#Y^6
znsWck)a9QYV`qnDRCz13K)tBGw{O9l$=iuOlGGQA{CKP35C}*Yy|?&Bg?p7x_$lvV
zFYfFpkhL}W>JH}Ll`EQ%E?R=eW$nm{I%WIX-&`&Bz>@u|=}$|as=g2WE`01-GK%(qy%h|Jjph}dDxw;x5okTCnd8CLEkIvQNv~9+_RxI}O
z@NwGsfOJL{AK7eFDd@He+1&hif4QHYG6AsUY+eLGTYMaM_=|$S`&)0KckE@^f6iDiV>5)E
zd>OJ{#gy>0`p5XcwZ6SHaAZbfc4fWYPG9!;-cR{}BI1S1&wr1t3%z&g$4hM&QX@*6
zuQgXjoE>>S!W4EgAXhv+>+PIi{H@3LEKc9&etY|UjBYj7&Tm-mSy6?MTEOR?;$Hq@
zW$V_Ymb}FTiD579>$C9rtECM3y!Gov(WU_W_FBk4A8I-+s_jpj5PPiF*V`1w6=gWc
zlQD8=c);f3wigNGg23ffWb0pFN2i~$GqD{H1MU_O+COg7MS^@c+Xmd4lO@K~VB_p-6kV@FhH=~lEnb&u;>qvI
zo@J-G(5)YEgE%3e+FU0?=u@t#3yyZKR>+B@08%PD}?EFBBq5@@C
zJ6FHhIppi}(x-h@-~U0w-i0Qsf}FEXsg<8leP388SNW!ty~HEXg)XoxPp{2zkl$hy
z>kq@vY1PGL#ilKuwr6^{D{K8#H|L?-A)?t7L?HYe$k&ar_m7Z`{!^T+n~h#c0Hw6Z
zUj;5x7vx|OQbZI4{XpUuwyiB_>_OgI@$-a!V(-t3M3dJK)qAyh
z{W){}97Z0L!I-VD$9le*%E^7f7Uy3=loY>Zo41m#2Tb>C_v!T`6c2{HHv54Rf8k)Z
zga7WsgS!z4`VG0E#GU@8fKb`)+r3fTm^tp!blJp<_WuP)JZR?tr4k!#fR$>74`4!GBcCLxOc3btUBeO*98TWsVftF#osbip@=r(D0$#p2g
zhER)K(UWt5L2QGBUzM^X@->r*lC__K!-tV(@*Esc%|kp$5zGKdFslYFPO{g`)6Gu(
z>a%5uW2A9Z+>i|M`Wut2ju$D>9Z=+Q>n;_;L)2MYRCgJf&N>_
z+7uMPdh7q-j^G~|04Ll3vT$ZNp7_MR6rLcOI-WTBRoNsgajoEG=Iki0ji2*0_OtH(
zr>im1XFnNjed}^VwI*&Ke{Vq*SyC|Xx>hXr^03T0b43K3eddl2yVbnGK+~EoXkT5*
zUn;O4K}Mnk+GgJaaTQcyloP_UH$Z3etEtezLui!P8pFkQi!8v`Z0OSi^D(TGhCyxKJV#_S)oV6>gzZl@o-XAlz14^oWMEa
z_X~hoHuNQ?4YhHVvc{&Rn%)bYy#>iSWW3WT)lRON#ZL13|4zC`*vT!@ftuY*M77{x+~X1KiOMwYwei0-gS%
z1-@$nUDgaV8yTM2)MD~UVrT5|-2sh$)To|%xQOPod{%Qd3Ad{KY0nNNkmKYooecOk
z;kNb_uOTz!>b%XmQYX+~(l1|f^qESeK{GS&;pGYUO0D_u+D@1bLL!YozW3zWEfXa7
ziLf6vt=Yuh#Fywd)f#TF@8^;{qThvXLq-D-I98Ud_KG%(YzcqJxfD*@^9RJOJ%$Dh
zPF-g{5G;%@;l?qB{J_6V1K^(Z0jp9jrA
zuLf5?k+z=K8SULzS!=zq8|xp7l6Dcr^}m)Pbm^CbOio%mWh{?v_lxm;O&9}0ut0WL
z%-9*riBSB*_o0DcElqiVr46LI=b>S~?XkS~_&y?DvF_pdZSn{y)ipK46;-Pj-6gen
zt@k$Cn7j^>ucSPHqe!X73I4S8F?snPc<$Y@y;aO|j0>p-uQE0qYnkOrlmNN!;caVt
z|9^I4FfomEEzPQxJkC-hXQSjoLDvY$5L&mtMQjf_#7pi@#9p+Xq60Pb3mbmrE
z`ft7;>(~`an;DnPN=blNKxX~&J4)vf6U=zWR7#zAH#6OB>c33weX2`#ahLgcVsGQl
zqopFLjwy@;NhPX%wpz%pqZBO`X}sp)Y9nf;fb0tq!5+Y(kmLwpF^EtYB-VNgS!Z|v
zR;6GCbVAVnu`%;{!-_IgYTL8sM~|XH#x8H%u?bF~QU3dYwzTnUGDlj?LFvLe&xx%Z
zoS96t*7cRl=Dcej#d=+fR((ENC6)I+L}`;E9>s(zjy!dnbM9s^;gh_Ud8JIC{G-=
zAIiu&F#4NCMZ-Pki84C;nM|QuqXwhyg>fcKI8nDR`PBD&l<`3**Ck*t?MO1NRRme$
z^A~=ir>Cg?>uUggEe)TZ>aV$)P?t*X`RZLVL_>cmJm(+lTP|Fn6Yf^FslNM4lzVdW
zO&a}qHPL7KK|DDzvqkXe4yC0@lvo^LHl0hbxL)f}d(7N%nEm4_T70KH6
z<;bfEX8QpAGx^@cGC+50rv4_LXf&dJka3rvd-r
z4d)U{ed0M{`?8_u2sgLRC1N{A;$5sOAL`5iL3i-glh#_j9EAQ1!NY946xUJ&a!-c2
zuA@(HW3C_cW)>Bo1mVGR+oq@eY0S0qjR;NeQ6aEX&ea!s(>fT6uwRkR-g79=q1?Mz
znfL6Lz@?`%*U>=a2+^xdPSU@9Sta@;mq)j;Pi)LPm6xNwpBf4Bev&>
zz{Q`pIOh~($d@07qc`hHzM_eRAc^|iPFd%>YkF|r^B<1Z;%>;D#-*-j$Ne=AO`s6O
z_5vZRx9MPPli#hSHTb#of&e#>3ff^O4D_GFKy>pLU`kpx|ovR}I
zcusZ|trKX|(D;gBtkVvgDPHJSv&cE~V%AtS=^rk1@1qG_@`^61X?#!usjK2>lK9Cz
zDzZgX`xI*jlZ(5OKNV2_&s4y??)!=1V5(V~ND9W(!g-GUko#6e?D<{1EkmI^=Xe)0
z7o6&2)dpQ1(>3SbXb6$qXg%Oq2Q^K`>F$$z((2h8W`ryMN^%B(o7hbVgXly#?I;+*
za}t3f#TZdr;~$uNZv+35#yd)GG{-kS5qv(tDNZ=~$8r3)3wAWcJ?qUOgVX!t#Rh(S
zRnK{g#363)UyCcWE?D?2$&quWHbgxxEB^+VldfecS4|ehb-uCHj3cxzP$Jl-Hz6Ay
z&M)YH{j-SO`lq(gP<@sQ7Y`#aX4mE}{T?*?h|%0_Iam0U;n?*Z{AGfUa3O^9m_95f
zuCJ%AhnF=->FTccht$gi2HdQg-0iEGooQaQ7aqr&CClQk$nnF7T-sCKU0V6ejS3Yo
zoJnjW4GEGpu|A>3RXNub4oyTSokQ>8>LB}MjJH#l%fzkr>g`EYJ8qlg?qI}j{jkc7
z=mQSdl#wpG=*kU(IjlYE?R~gtD*idvcNUgkagE1vOxuYyPWMy?)NukBrD%dteMN;@Z`5Chm`sXx=8qF=?$RCB)QJK*eV17YmOZ(3I|QZ{bq*b8m_*2R4`ps+f=1!h0U1ij
z#9uchio&@VGKG~~zZP4}p5lz9CLL1V3YR*#m1jci1Lj$uwarxLEqJlL=OK<86|=}E
zRPBz?H`r#bs5v&%daS$uR&E@P7b#O+P(O)vp(@v$P{)NO?nwHx;|(RP);O_LGNjR{
zJChbWnbM<_RaI`p>u##FlBFBDHMbSm)C}6NN7AUfq|7(nw~c4;_GDD@inqIYDkTCH
zxb6=dhHCB@7Yn5cMr(keHG|Buam&t9Pn4|I>mzq$PR@q(RNDzm8!
zUqq{88tiGMMRgASg7pEF8;lOU!P%DjEf#hX$1|I|
zUnD8o8(&h(PphPjvKm5Mghb?4$=YS}YCewZ(I7F&!oyLCtW#<{zqGA#%e$t2O(w>l
z({hXufl7gz1MJQ@oKv$9{oTz0IAiu_v~k|LW14=m`r^ZG0Obu5U#e**Ofz1F)5&%t{0wG8(@dohb1vS(@x5~X^k7na?Ytl3k2Y<|5;YR
zMQ-Cpbz@@V1}lcK7c8C)dWkvr#9?;+#+p%X#ODVo=L7;I`=BOaoOz1(;hkYjjAQCZ
z((7jS;ax#N$hq6~8?Ct~uia%OqLEESBX5oVoF*YhJ~VO=???V0-<3gQ*oB*`?>|D-
z5pCRh1PSw>Jv_(+oM|VPV&dPQyD^2KyfoP2>Q1TWwgfKprBp?qWzLqFHI2N$kmiX<
zK)_z=g)Cb3jF@dEtvMh=*DL%?QT6WAKcZ9qcJ=-00)n2E0FvX|HM8JsX*tdu}MT@U}@(n)6I}zNeZm
ztWnlZF1G)icIpw_hnYSH5e6_E>%GuCX6j6vT%?ZM12^I+)6Dj{CzQu*^;4+}_ErX*
zxxD9d4lgjIA5&Snnr47T|9l57{E_Ve!r^mUPAyOx=o3$EfM$dTrR0C#I--6@ZDI?*
zLv((LjM;xH_Ro*o0q-gBJb5@FnJ;8n)yd+^XUY_FkxvbwCphBOd8-NNSgPcj+-xzj
z_;y!jl-b)qn4&NzRz+0&pO5@|H06#8vm{wV;C!4&uZ}0S0tgk(V#o_c?N{_4TJ^%e
z#G>En1%QJ>Ui-+*JIZ0yLP1@J7Jez7+kt<=R9ZQywk;@4w1&1f9l}Zuvb5M_@
zufann%49XAEcLzG^_OvA_UZEEKx_oP?*z)Lt3_#--kWi)9U<%Fg0xy4g0-
zb@=o#(8z%XQyCxmdB%bDT0e%A5DksYne*3hzc`QZu(czbR{nr|p&{$U1r+<$f9rd#
z-#!`zSyDhd#L+&)aAbjTir;?7Dbyc@2*Auwy`gO?jU(v#p-%!yFUMtn^!c%8MV-Kn
z`K&Ca^m_lUa5E!)ctYrX3;L4fPUQJpg&U*rPm}cL?-;Jo|FfI44V)K>J%fJGsrw=h
z=;se+>e3x;(w<{D7%h+$)p6(}nDZp?WDcB;n*4RrgqO1<$uu61jHM5nBg#?8H6Xpl>
zm&dmnv-@;iv#@EgXtXSi@v)G%a+DFy?B
zV4X5QjH|@U0~do3P9cX^X_hcQT=CtdGX}>sGMXb^+p0)wPTQ)b?v?oxOkP`=cg@{-
zayxrcIXr958P7G1O$#}{*m?5RsUA5z-!+Y<)u#DSB5;`mA(rna#Fz*vfZNomUTYer
zto~4PStjN2cE%}MhfVdF5$0GzU*94u(mJhaEW#rQef;{qKa^b>qw0uI8nd|eT}Jr=
zQXbDaxcJ5rt+f@UG=?qv_`5%LtP}zxmPr>SHSQN5ML4Ze5Wk
zOXMx*ch82DzK16IXr|XPi57#~wo0ion_Z3N_Cn|+?^~cu(Qjch3k1u0LhU7`)h54R
zz*u%z)2KGhVV_jZvXVS^-F262x2wR|$MWlM-)A-8eTA%Rxx0C_e*D$eLKx(
z>Yz`tp^oWox}9d7&WpY+Xm$pw?wo
z$A@VOl($U__KBFSlrU?dMcR9aXQtw;_Y+-Dj}){{_wF)_c@SIJ!ly=upy5=$4d_oIaw`F#}Hu%{+N_ea0}VO0*=z(@Bo$ev%)
zDP;|(38~_{eNNOqazGE_$X#-BcaC19F-M_2B8Ynj@I3{uL;Z|gz^&4*TaKc%1L9A;
zHt;B;2Cg%egbiljtR!hZM-jVYlR5L&X9Y1;inv9)f>onq%4Da>+Q6|gBO`=(?NJbl
z=19=Ib+4lLqQ%V6$pgrNn#41;f4_5Bzq}itmY9Fxri_^49MJGRz~w?^I_+6TWjdZ7
zNx~H+)^Ykv1oZYWQUwin9W|Tanx1sUXM>+UNr!)`ATymmjqt>~nT9rQd^vhks(q{0^l&+zj~tje`^bJ7909fex-}~s6D%;?
z@2gI1TnhnbT(exOvWhO#Xc+gVe;Y-!ri6|;O!tI?I`M*Zt=BT|?=ay0HZHD7o!B%h
z|H!HKGGixkanp?=tXG-pJh6EMAiA_Wc)2kp+dt;Dt=Mm;by?rW7
z7CMF;z|F%@=%*uz&s*953wS{4iLCxkhw42hr?dvGJ-=0+
z35ckEd`zADmwDfh9H;S(!vhOl*+_T&1KYlnwZ(c{G!Io!?j;Do=x=@>q0BkF`7tB*
z;&){E&G@wYRCxq-tMJm{b)4H^bI>f)>H2fJ%+uDiYnKCC;2QZ0?=BUBwv0B6oF{3<
zzlN0@HRyq0Y*{Q3wXWpGlGn(FCsrCJH;Z`njKfmUZnC`oEQ7Y*-BAdY4Tn$Q>dI
z`;nUnZ~OSFqgr&6**MG9`HB}cU9V$8<754pfLy(2my3~8ZO5u!t-X71R`{gRXVi)vH_?f7FQ_P7(DBojwTl{Cyjo%i{*fDi5Y}%TcF*aX^UzHA>vKd(!)UdvW6*YDXK!uz9
zZeR*0Uu9#W(WqfD#;okP_rQeXtKVdLe!u3S#Lx-HIh3bRMMlm^ge_ofOo>FMMXEYz
zOpQg9akZkPRe^E7)Oyrmtcdz((4=yN&7fg%EiGa!{2qR6EQMp3sUcRvw>0f|z@!y#
zO2K;Mz<}cq6PLUUFf9#htyor5rbe-I@zpqTD>;&?!99FWm&kTg(|UM9l{#?DPP>?C
z)s~!tykl`vM#!lFOZFh13N5M2;AiPxMfydo09+CWXY$D&C%?K87tZO#az+bCa-_GX
znoLVO5dINAJ^SKFKYh}vp<@m&bPSrRCF+862ILxQmVFEbhHJGrCXjAM>@rmgGO3yb
zqtB!=b4y5&iz{$!EYk45liJY#FHFpER3G>ZKUV!Wt9Timai`)p2;&
z*WH0h8oMdei|55yN-+AmC?5^_K#t;y+iof_`k2(cPDM!0O*&=Rq%~tB{X&g}1!io_
zmEw$FgDHB<4n9=dQB}rGd!pY&?;$3-w-AEVUjl*yR$I8fJr*(uNwY)=-ho8b^_{7i+Ly}5V>dR=|{~J-fB$Rr+J*&zk2oq
zAC6<@(~S7LqLAYRwA0P6&aj>{^x8V|MDzZR3DKH;jAau_Wy>AynMqA$hQAj^k$0&}
z*i+>0)T-Dr>h_m~V-b*wyzH;Pqg+pI!thpl6dFCac3P0;3QKm*V3gaq7kbvD!`p2M
zrY4NPiV7Z=_c7di3TCk%2Bcfu%a|Qpr;G*Vxv0&+{WPYxOEMuFX*N#=8^m0<^pohV
zQ!U}`)QT|)sPq%l3I$o;=O~1W=&1SCSJT4GueIL-WNJgii-`5%I~;Iqz2y&#w|;E(
z{74q6$9JcDw`0{u7i6MPzfcb`;I|#mU%4kqcM5sop?!78PuK~?=`kgf&
za}@ovZFuv-H>X9~I_GrHYRkKl{UsM+?W{P2#aql!2aY)e$x5zZF8rt|5!5_4z-&g)
z*+wDkk&LxttK#<&JRjVUhT4_{&gEal9*N&8T3x&)VGYkINd0?utQ;$NjN97;rx(vU
ze41Z}0{TSrC1ifLsJuyjn(9|+LUWqDg^Yef+iV=qI~Zw{F*=TDICY0ohK?94HKm8O
zZF3a?7_G^F)Us%t``Q=JA=t)WwYrG)1d8Kn!d4EyRq~TaYfLExTKeKOl2s~?-8BCE
zWsv?b_lAjPp8RNrGFr!vY6^|t@8wXcFnwDADi!cET^|_zU@3B6SrcjP=dF3t0%*XV
z+A9*S{#8=``BHKU-WvI9ir6Rv(;XFc2bS#dB&Na
zy(@EKZI_zZq(kzjs9R7QG%rm+vd)PgkBmYykd~_mmqD%7oHfgaqZ$)%&F*h><0#Jz
z*LJloP24CBk?GQMCQrrgMM*>o?W*8o^-)T=ni8`0POi}&C
z=^tS!Rj_1r)*9<&R^N58$^hk$F_G(1b)2-Mg&Sg5zvr#YV-uDa!LM0VJ9Ho*+cEYDhiEIOkr3Nb2
zWuR)>kJihq$^o?D7yB!OTp=#YTEhp6ZeJ<
z>oNT0QIZP!m2|V;-m%Vy{ACDNk%9)(4Pl0=vLk5pmBycASfdqc7E#N^MA
z@|sO%6^1yI(*~S@%OWAv;YKq*B&?jt+J_nNJ%#4XZ=XrnAp9hVSk$sFlhJ{rdX8zPe#WA3{I5+l
z4li+Zh#>qHU32!#M_BiPfUm`_AA7SUtf&G>1O*9Bhn@lxmsgXN2oc~uX%MR>1pzWP
z7+Rp;b>W%gSJEP?wY;7nP!`2+OuFi1F4idU`)gtcmx$*Q+O&3?w-m^>;C|j}ktWg0
z?aAe0M10Tk3>cxK6x(J_X3Dq`)hE-n#fsN_(vo>=mrT!*wvF<1^j%G9#t{F)WIc=xK68DJ`o
zB)g&&$&sRc;!>et(m;otsyUP>?e<>XJ6sR`vKUNof*nm7z+^{8F9vFFm12p$&dFZCi&FfsBJ}hV
zb7uO#@%&G*`xj;}sv1g2MUfBjMnIePG}eOWm$N_SW#@Wq0J)_J78q+Nk#$&aoDD|@)Ai@0=8-iGu^
z=;^s>@pMU^L5SyXsx+r0dx2>3dqc3(v6_J2VB+@we7cvN(flI*E&cwWeWGB%W54ai
zgVy1I@W%YRrhhKv?xsdK_6K}v9qX-)lL*}}35xkCl=K9kHm~JR1y)*m2v|&HTpb4C
zd^#3>xX4MvD=>|GH#LAMfK}Jl}
z$M$1BlWTBpRhXPJ>cd`^l6r7X64{+h&{GMstyXhAB_$0w;y?LfS`
zbl69H_ZRee$&ayZ{^q&>^vr}f;{s;-5Vo}f=1k^4Ce;eUTnf}GbTA4~*v)-ZDpT<5
zLJOV!x@BFo3j3<75~o*x9XIYEc#dkHU!}Rr5{8X;H=GUde$%NX=0dLHgS~&Q93dXB
z)=gcC+5bW4WA~LVMs5MHz#3<1lSkXy;mBs7t{kx^y-9@9b=xXlGX~$0#v*LJJG}f@93)`Df3#EA}lPIpRRe`M^
zYH7pU+-UH$;3}<}2ZAdp4wyXL1XEfLfoWmY8&_A*l~yNgSc~?`pxCq7a@leY3BGeR
znes1g7loK#tNs%*Yi`1!@~GD<@cLV1>Mu`&BX)5x?V!jrUsGzkVX2#GsX=KeB7V8=
z^VeyG{7dCa%ZlvrrGm<#?UmTFBj=Gb`k(FaFxUQr#
zH9_~e&p$Zk@c>SqlQ3YV6o
zwOO{W@x5AebqRsl2esTP~bPN^)}6wKgbTbGyLaXpA|2hTfR%8>RAO
zAFM3h;UJkC`PF|c_`a#-|79VG{)hoB!;M%jV)C!L^%@SX2-2Tg0v8Na{cnKUg3
zGj6TL?5lOqO%ir85(J84s^>TRC3D6Lf^ahKjaq+0d_W~;MlU3ZNL)a%2qH&W+9Bsf
zV{L2C$y$8`HAOf~Y&RJHuqzFDiQ7x@U@fg+JH$)(HPEDO_QoQ_Uhion6qrQK$Hp9o
zqpD(^<|_6%NvJp}*Z%y|iJoUK9;{7rsUCIO)lTPu07o!P-g2_Gv*_YTLobE|)XcQQYBYQ9u)Ay7{
z)yHhxI#Hj&{TdQ2jz(`0+^?-+{50ppD{_hs4}7-i6=(}yD!FY`nT(w?f(x!0^l
zh2Bv_#gc_Mp>mhmmIDhcZ!naQ+qgc;XB*~Qu6&IOHVV~OypQ|cJo
z-wcjyC5L}L7O8hPCgho(EKB!}9ty_E@MnAf9p-KfFCwb{6+EHIcS{-m5#I
zY-2O+iV!od#h^D65FHQ^WXqU|r%PpJr}h!XX1mN0wX{#Ej_rDTMXuW(s5d2h*BF17txrFNoZSObEtwF)#EY8jHkZGnv2t
z*4IX*(ubXE)Q`+Nr%0nakS-O_{tx?#>a(|TCN9DIJ{R;LV)sbV+7??rMm@TbS4zwx
zmK!9)qRV(6kTjyQbb?*ZOtx3m?qqg4Vyvdiwd&-0_+H)q61%*x+XhYB!1(4PdM-$o=dKUKmgxVpwi{P4YHw3v=DAV%mmhU1gO
zTmeWAKi@N$O;%xj|3=p05mx`;_797(s6(5d72m+-o^4u+cau4V=+e;;Zvp*(p#z%s
ztT=RD1D}6;9);dHIIZ2)J2BeM$p3>Zk31&re^t51&CFad#N0R9y}ch4En;4(l`aI$<1iK8jtfc7--{-cGp6sP
zBu>ScI%9p}){pHx;2}-m>9t-)VaCexxLz})si>J~AKpXS1!M6)=I}1qpPdb&@S#r)
zQ41^&jJ|7n^R37jx*^T7_Z@x?vMU{MUb?JDUQ)YM4g}oansDMiU`aH~!?UN$)rfOU
zX!?T!(rINM_8DJUgE~92NnvI!`UND1R|Lr|JA0ex2>-c~yekwFA?^{~z{2{Kb+`EK
z{`6*pWjk)cpa{Oi<-@hCU44B?PYlh@BOvIZ86QkcI=ufAvwrGASWctD(u{KqX8-rr
z#{&v`>&3=}s!+qr#Ob>lEY*ZjR%<)lJN*k!g}R7a_<
zfaZ;AMaQ8B(^~E$MNj(#^EOH~e~pT63?_D3Md0xPc|v|aHNo7mWf^r5pI@?FQ~Foe
zzcX9gFCv*pZ>=9^=_i8o-FaIKBRi2KpK=qe*@Hd3k20Dy;Vi@RGbp(k`%H4F?&?69
ze|r0QN9n`ZqLc&A243!vU})NsXK{sDpU-q`@*f5MY(C$Rn(wb}QUg0o~z
zTPGIAVYkf7S1Q8GtiXVM3#VW>pQeFyGN-z*e;gM>nJasXSq#_Lr7T+b%*fk@%bmUH
zrzM!5BehNPdBm}RJVv^;P3Y&8y`_z~)(4n3w(8b2Fs0v(y512Z&|!DiZww*?fK~@M
z6!Fc{PY)R00zR<|TCC_U>VUK%8}8hBuVCMUgX2PfYKK0$-p>Gf24-ibK$Saszp0zp
zWY5n7g-g3gaHVT)i^nKPrfe|k#nB}cO4pT@ZN6Tp6}^qWUzgSw95qp^M%>=Kc<+#k
z3@&%{C;WSlltNnG?VZoRMSK#7?PV!^qOc$_-?bILJfdY;wI@OOfFju~a(G<>(%i{%
zTISah?D>(54n!~AxE)U)s}{FE{4^#BBL;yXS6PUs
z<)g!*T``g>?of?_@~H#LL6pl$f5M9x^dd=KiJll!2<0JdXT7t`e19#oxFds|yR&DQ
zmh7#Mx4tgfcG5nelMRN>QG__kN|^)kM+TGArE`E&J%$v4Krvy)t-Y4G!}N*y*E6Oq
z$q?`+U>v1nuC^&P88#K8pFG!B;;-MBRXm_jpZBe%L_b*J&`FOJun7kqS6u|%{g_zg
zD6x^$lU9yB)>sGKaDOrJJ;XwGMJ)&OEv=k^zR}f0dLH|9bR^NP=_zh+g%zW*n#%8UKP0I=mf)tap<}gJq*Un
zA>mbj@+ex3hFnE+bKBw}dWelW`EcCqzAv-Am7Gzt
zt=icOo_{5yirSaFj$75U7YeWq9uM$9EkI&$+n?M-w6&xJVsND)kAyJ@39?}fFw0(V
zgI+i~Zh8Bw7WKor>RnsjZy5RijF1cFqShrNHdtjx
z%0r(=b3FRXpQ`bv<4If)+X7o1lGhzEv83Nz5YI*TFk0V^?upp&K4X<}R^QT5hiL)2
zYtoQNLZ!P4cSIwu##?cY1D-??RdODIka*CTo;cR}gC2og5Hk;|?jS3zK9LnnU)yC7
zV^99izB~q=u3v5`6{qmP&_7ELfuUho`|b`&B7N(uSL^oh?&a~>yK;=6nBW5~KY0A5
zI>4l?v^}^*{s)i=W7*rK0cimOdd@wIgYBq4#6H5o_Ylnn;1OCHNIIzW{`kn#B*fMw
zAM3s2v&KoU-aeEI0wNGkU>&hJP?7Vhda$}hdfE+BKwYb1BGQzp8%E*Hl{hN{D%qDwF??d~?su>f`a%xT`lSm%!<~*m-6qgRre};S@
zg-^K>9-BNV8=z$uHCSS6yg$DvgXmmGF^m)qlr(P6b5dq_C+(}BlrE1&1#)QZcLJGM
zm2$o#mxxqHH3!M(#pi~Lz+5=e=1WYAPX|s?~X8-{G1RIl10qHko+Xk
zH2FKovY-4_?%R~#Ysue<`}D7w;Wg6U9m1wh61V-HRW9Brlt2ezyBNyT#FRE-m-ql}(x
zl`^U~DZ*^TTfn<+etoibkOdWkAO#++qXLZT+8@f6RVbLGvZ0vyUE9-WNDJsd
zIOh6Lgh(OB5Gk?+PnAyQ{Q+6OUc$6+jsBs%LRVtDFSm9#>wTWdu8-LoHiKGvcNa~D
zkXX;op)Nye)iz#bSdgmDG5o$SMKg--VZQww&9>Pb0ur5GbWSxXV6GuL&Ry|Au21i@
z4PB-DL94`vI-JmC2xt04-m+;MA7%m5il)?J%2E>c4CIK@HvJcWC+YaKP5)I6g41?Q
z{zHD*qkl;Mz$t`k{s*ln)q2JMWP9If`?dUsto24Tr;~3NqCtiOGWN>t>uK#<^N2Wz
z__n%(H6d+L`YaqS?8~_-t36sm|Gov_1$YQ-qSp$nJf2Ubk(0V78c=;uMEMxR=jjZJ
zFzDBA9-p4VX?9Gu3|JrseKMS2Zw#h0(D)wq3bxD6=Q*o$unZngJ^?h8ky%j@LyHyInB(i9Ls_0z9N*BsA(`%yeTtZjbO_N@9u+H9
zh?PFW(|E=%f$<|RCW?|cOq0f1DK`??zo?-(Tsrs>|042>`R#NGTNm~Yg8=*-n3i~t
z{f-I0lpGp6UtKE6(TxZNfhP;0m=`Z9E5h<+b`=cKfq`uoA6QBOrFb9Mp+^6dkq_9a
zz!U878Ck@3lvz}7c60$g0tT>Yo4mHPzNQJ8-INN8cB3h_PTOx@vY
zvjmoVkG=KMIxW37hA=K|IiW2XfM?P6d;vS4R`N}w@w%daURf%xS6AxOfx-?Gpk@NF
zkV1&UxbUCiq1fPJ1z1UjB%pQHK?@9WM5pZzi8B|?x-2D`3)@K^*d6>$p02VOD9wHu
z1>OCt(U?4&)In%cXtvinE4#^7niMATp^amN@#*xU9gG~H{lIYwm?lv|PS&XxniiV-
zJ*MSI#_+h1<%M@2L2yXeQPz05m>*c4mNRVAYLVkB!G@3&yT4qNiW#D1R&01mvXnN)
z;4l5*uIyeNsPVUo-r~(E+xeB1{EqMtk`dy)2=Sy3C63%tg8F>4w
zpL-)r3vrUzr}+2%un$K%{&IIe!(Z?zk6ozBDd`U&sU9KmuoWY?mueS^kChK?ZK?1N
z91=*u;p3{y-K&tl7^1?jOb07M4=|u~c1WnwGlz
zL}8wJsJMIv(AVXF$Xj$)JCfXw4vcHGq}Y%9(E}g
zqB9(@HWz=c(&2OgQLxk65a_
zjy8*6zKh%zN9er(ZdalCX}c|0`G!C#Pccv_CZ{C*UH<_Xe@EKn2(mK;@qys?Fq&{2
z0EfAdK!OxGT{vW$WccJ@lrW7HfewG^mO0_n;ihOL2P4l`kKZ!*c2%N+M({G~U^U`D
z(jevGuig!X6b`ME6nDd#a;zXcw$#C!R|0GZszbFSm7WxLG7yB>5z!S=rGOSUW2MyW
zS{(_2@HAc$VpmA-#rx1I4JKy<62sRkFm)`Dv^e6$Y{mF8q=LwF{jfyV=u7|Bx66dCZsF{i0@-0GA?s(8-lDPpl5E0)>-`!
zaYRM`s4dZr?l_ck38_tO4@q$&=wS?bB(Iuz3(c}D;L8JjIJfm18gUX
zwu+?`;FasHAge@dO#EjwqgYW7T`@Jd2KMn(Q@u%shgKUrQUn4j4&jj?^E80fH@N8P*{-g7pEROwFEo0WJw4b(F2T`
z*`?UYCPg2F9P;sKwt#ZDK)fNx9NQ!1g>o{7In8p9TF<~cRktHDqx#j7RiI^noAKW|
z8Fq72u(zM2Xs^?)|AKu-SAY?AQ1pFzV{NG`!5H#gm594=oR@<>D^u#)BtG9wKLL)^
z8noTDgFlj&j2svcAo=EefRVN)3SV!d_6%e2161;%(eSt
z9$RKxxN`Hj+oCo02BKHOm{7T>UkYR=`y>@Y|9wau+!m({;H6U23ejBBy4U$o1nA+)qMIxBqA52GWdQ+8q;_5O@BunvpB-W4(Z37{(+&Z%@01tI
zJ$#@Jote89?6bzqsEE10BCqsF;khrG9~uP3;^O@;a9l~-AO0Sno9G{9di6%H(dk`w
zIQ(5p>&&;b%efI5bDu6`fs)IKd1Gx
zMoXNZo&4em&}s`)FKe&`D`}a=4PP6g*OiBJcs=S3;Z^CuKG4(e)Dg>&SCG^;zMQSd
zY3vmC6&sE62ns>r(2HX!je_dZ&5V2*
zPoiL`SC}^9i$2g_Vc56>OY5+quoo6?GrukLkCUt@oDy@=F{*4g`fspd62y`&&+Ka{
z_2#eGUiKM}{&o030(kS{ShLl_J+Tihd0nWu&rb2dG0=Jj8y$d5o@$B_Zl-kEVgi7@
zk0Y3*=eAEb2g!4M$B%F(Y^>kv18g+J^&JL0<4WenSaSSUY>_C^?w-Ee;a^Fd>@B9f
zhrL?j{ufDjDjEWQUfn(LNo^v6;Q_8&%WxWXn=JMwqaS}8twK7IEuJ7>Xdl@?s+{1f
zkg`MD2!TmT9^3*x5G`>)Lb$)yl>FA0Mb=MBB@CB7R23;tAe2jh^nH$)XC713UTli0
zys@2tsivr~RIl|#aCdx4?NgxT`J4mQSI;e6=lr-hB9o>V^Lx
zSpu8mP7&cmo-8xV=ai;G*vTMcp~4Mx|LgGWWLAzI)OJ#$g>8`rJIQt|6(xTMQaHnlX1{7FRVA
zqqRCJb~4eR?UN};`Hei8+DD!DFo@gNUgE@(-CG#tZl?(4mQHt^7?w)IrT`T@qQYTW
z*`TWexTj)F>44|^{tfgfP7xeE+#~)309O|Sza%h}41Z)TIX2lt>R{)X0I&g8(n_Uljlj$9)X_l1`WY@*DA*3~d{*_(_
zOCQJy%Ftqg)pne&{`yzsNV>-1qe6E;9DTxXX{Y6mblj;tJh#
z_D3Rn9N8f1*c&y|!C41iLFYYSqW$i;aBQu5Cyw-Voc7S{h+7q#Z7teI4J-yssC1F#
z*NIx#1-d+b!P%80Ck_R!tl&NsjL_4`0QW_%U}}a=P5GCIe{`uWJ?I_P5z;aswHT;`
zv?vO4B&|+>^90%T|d?
zKkM5TaE>6Agq(ufIhYAGcQv1mmn_9-!|IMuW`8>e5Q?&80-Fwfp=-o&al|U-2M)7?
z!FYqUkI+BkhoOozQ<%#xdhT-b6Hzrm9kS!%5s1(0IHsjg)iTM6!QQi?4^tNrvy&t_
z7KOZLqY33pn=d){8CHb0EPlnFqH98&oMnP+c#?rol47#RsR1g;a+8Qs6jI_3{6u%5
zP>4J=qdDfkgt3LJ?M6J$As}mJGCN>3iJ^p#PT1{%@0V$`(JG9u}|(KILrs~MkN(0phLIJVx8Zs=}|q$o#Cf(6uanoS^6
zn9Rp0OUDX$8{9)-pt$v-@4)=P*&XAShLJ8rD~8*3^Tjsbf}@3?3~$garUUXp4}r)?
z)TO6|{>jrwPDC0b42yb^Wv~|y2C3t=ku_3bp0EPqVlAk8ZR6KY^Ue3$wWFQ;;k8tesPrz|fa75^
zH}ZkY3&U3ikt>JLn0}x;guK-9M%E1dOXSyH7sI~5E^;j$e8;G-16`$Sj))wbnsVeI
z?2U9loF4qe>
zqiPYUALEkvP?I0z9Wb*<;1+z_m*3d)B?k`g;kLZ-L!7X@Cj}LFL{1p2i{34Z{;#Bz
zO2ai=W*pUv)zQG?vMO+v0vhJDvQm7)=?PmkZFnO4r_q$Skc`SG0E8farXB_Q=W!5T
zOhNk@`;H(=&4~9Eg2V@!B>HEZ1Za$j%|{6W8s
zcj!Umz_|5I>TJn_@9-DaXO&%6?yn257~gAEi~57wj0mQ1euq=VD=9%27^L78l)dHv
zjH$ZKP0a#x67^_VXxS~VGyJ50aP5JSc};-U5N4Dg8v>NtE#b@JK&`j5Z7rJ*yw?mZRSB&tA>TLyLzAao-
z&}SZN_$y@%hjLs!f+ER*nKjDOnx-F{3Ah5QR&QBDPLz>HdUhF^Jwv_R>o()lN;j0H
zOXJ~SqvR&WBZcgzbmK%dH4RHQ)=D_YmEN12S>9TS$yyZ)sN!bujxruv=1o?{_bfy4
zYZIQ9IC}Ix;0OVn|1$gN=mGdxeGps9c~6I!N?#0II^xf@2ZAWhJ0O49ryuaX5B{s7
zH*oON2}wD8QF;qI%Z_oO2CG~@SsZO`(V1buh6=ZE4nG3tA&o_22vyqvc$v9aB?s)H
zGq{P-r^y@4;Yg|_>R-nd@Nt3m^v!u1r?iXf`*&S37wD6a;ze-r1oz4z8BtlwQI29b
zB55c9J4p7aWzau)4~>*aRHa;vNV-XL;vp%AtM6jfXQ&decf@J`S5v1ihL4l}9Ykvr
zcBIcbLq8fK`d_l#6`nUf`(V4LF}7TqMD4}xatx82po%QoiXeUBBxAcdCmF`gclA$>
z*+Uv-3JL5<&D%zPg_;QQnZQYWlE2$Tt
znB*;@wtN|bgQ?~1EJ}?~K}u#8mtRte`1fkc?=}59i>FSNJ^e}95-?cwPgBqztWZ+r
zXOa8@sT!^>t!AqMVf?I9$8notPBy;fI7uwnd~jMOGg8z1E&EsgoYbMELQ4*i(Wt>u
z1TGvZU}wsenW@>KhR>SzD!(~?kv2$XhZtJJT!^rxUi}isZb>1Dv)}8(At5AD28ldE
z(rY_pz`DJHEH^1m1aOYz))DLCc5B7roO@1Ek=l+Uk3WI5!hMn@O!_>rgQz@IEd>i3M&{&xpW!pGqVQ`0K
zeYb}0$d(#k`StB7Tn?@m^bcbKrav5ABeI_K&G_o2!br9DY&VgD!4guV)@b7)z=oSh
z*JQ!~C;$M8xXjdy@v4j4=-)D#Docsop+RxWnG<%wi0=f#8??ZA16v>Mf`;L+hYhE9c79qm_Tqpaw7)bNt|?So?~l6(SuJ3o
zeY{t;mI?CQu=LiExu0~nwD!GmWfi@GHP=$NwAy1UWxXQ{p>)Lv=?ir)80y_PX3&@xVa!xD9!?#1_~IX{t_DbPSu$
znd>zdV_WLKVm_48?-Mvv0-C?2tK=!MHa<{;9h&Gv?>Dj_5iSu`+O)wh@7c|UBD;&m
zPYNmhh7mTDw_$iVRkQkkX`Z@yU<+f(3Hm3TS8+AU-ozO31R_h*qG~htX%jE>ujnQb
zc{s_I&8nwycTxo#glYas7+#@qAn!3>IM6m{8d3T%(Z4g$oB%4euBCC{lR%69-OP9yQ2VW7K)y`%trDR99bFgXrOIyEw}C)S4WD`Zau1sua*+!>A5>ZqU?Ozl{f
zy)fxFQVPb)GmWEnc9hKi1Nv)>hDB@fqXUTN3r+q
z6{Qs=m6RbDcgK3|(+@0BMc0(G1^d(-KdJ$`6VvN7+LwoVGZgz@b^Op!$pog2JUCsn
z0g^sxs|B5nY?Y)Rbx;bfI<^|S%~n%7=c=&JVDoRY_d@2dRqiTj4ls5?67R3c2uAP=
zpa{(l{ggC!F&UHvheiv%IX(=9hKAfOhBub>TzwPgen`*8j!ua~;sw&Xnt?%o)f3bo
zv$j0F)vYgr>-uK-?OkZLyQMel3Z}zyyH+=2?OIY@D+!ux@UE>|y6YRGyCT3E60ak*
z-cLt!C@yRbt;tNNthhmb{Hv&Klg(&rIe|AB*^(Dz3VI=v2FZG`+wl!iNRxjRRarW%
zEO=j)mISWKhhk(yi1PZen%o^#nNjHC{J3*|);q+#=YoIq?%?z@{FWA{JTjxl9)|Kh
zo65Kf3{2p@G{P7th(N{6Kp@rmTvb?hY}!KwIW|hLR@to@^^1&(9*((lDSpFCTeoSD
zDLb7gn8!}`Mg`k4TRRq+G-sk(GJiSrmbUi0KTTaEbJr&}vD*q3KHuJVtKpu>DhN=u
z&uu1E#i!LqB0y|Fwm_g^K%fiZSzqakW2|rqmEsa)puUbeQSP5O2vuGcP11|p
z8aT8_Y9~%3wYa~1L^I<)ZiTk#nLYBU(Dcy1ZH8lGngT4TTd9tuF9+bq;tYxST$I8I
zp^>ut23hhMOGt&KtNtwWU?WiKDes+0X#HwY(0}?{lRv^_qVH43o-`f`DT&p$RdGa?
z1dgm?Q3lVCA00!&tn3iop!}Mp__OYj-nNt$KGrZ3+|I^q#}h*cbvvqdmh5uAMY&jiO(hZOjW#2J4t}JlWTu4LJk$
zRRlk;3>K6e3DY4zq)Uq~KJ>xeB%hkDRcE_=?uEKkop>Ffe;NpPf#_hq8fMxgQz>PT
zWs59ta~L6{xdMU%HVuVob3$qEkVzxW>9gfMh15!aAp5Q$t-lrT_3UJ{8fIwsFYu_v
zEkceFh^MYT(a>z7;|Xin>G(P{m7?u#l44T$00wM2#or|c#X3!5Ys*{D4ZLQM`GPDx
zIG1Rg4O8@>F6l!smeW`b<;W#WuPMaDVK0MA7P{Vr`D4u|!!f}UH31leMP%2oAaj@u
zjWA2cbSHBlGYMC7d4z_<<9WoxPIq#hC~`mrzX8HwoTku8y7e9C4?%h47^R$C2q>H*
zsSgrWD~qWL@Y5`>XDUM)@WRC3@d7!R5vhr{#nuQ(8?ME-7Zf{zp}^uU=l8AN5a^#i
z@Y5c&+vq6|Q1&ekpI-RDRMdkFD%wHLlxCQSd!R9^7+@K(O2{rdggZ1EP!xpCGcYuw
ze-K@5eU=^(BuoB%#k!RH`hr|V9NEkaB`5ae%q-r=ygIG!TiuNw3e6Y&(+;DpTyVBn
zOQfe!_a%+sOVN-TPt;X7u1GND*@Af@0ltf|-@MG1*Y;w~bS{%C$jHhj&vjorE?rvumwGupn9)(#)`
zb_-Yq27MK4EbRcwd|>-xB=22Ar6PcbgoAiokk|3q6BfvbQ~jW%wnNAVHu)QWqQ|KT
zJ$5OwQJXM0`ozR;pm9@MyLoqD?C3c$57ZEv2py1Eq~1lnecZ(f+3L1`f&IUpH&vxl
zzX*yN{jt1Uf>Tf#OX5AkOGl*;b&j`>;aF*&YH5$O@)5n4ch>a?NBBpuqY%RMG^9_m!f98Epm~P)Wfo;j)sm!77+B
zZ8P;v0#63Pu-I{FZb=y`vs(lX;#H1saf?PuaIzn(4pJKt+2RuMw|IjA9MOMZdEkVq
zrcqpNtx`nS6vv9I^9P0jSTn|k_3~N-8f+2RJA#_K_dRTI2ruT?;#z8Wv9)WONMK}%
z&|2eXqkvT`0r6=CQ742rS;gh1%_^Z1sh-w5KZ*aLXbU7Si#NWr3c8srlZAaX*J{Tn
zg=K%hV#z<2iPNf?q)w==Whk-g;;%u16>CA!uvjHU*8G)RN?Y{`_*JZ_$41%|=G|-)
zP0cpZ9Q7OcNwAOpDei$tz&<6q
z28pS`IUyA#RE3ZZy)nA!j~#POFqp;gN)1<#2T1oX)$jYyJy0(U$~8hWYx=;0kIqS#
z`461{CZ5Kkna|5a8n&W!IYA2>MY^4Y^Jx_qx_
z3&t-ekjSJr8Wc!*#}J~FWjm$)iQATgU$x$W$S#gL#=LiL>sN~f(Mu_CH;jdsO&mG
zEV9plkY*6d7@^jlSDV0$l)@23ktj4q{~#TON>K`-7n1nM@VPDDoU-&z^ry5tR910F
zTV&|gJaK~HDO|+eV#*@H1IFp`Y_Sv_0Hw-fO%3!=}@&_6g{|9W}$)7kllGyIbp
zu9NjrgqppY!Zrud9oHRSh+Tn)z5dLP#2msyZj+hBa_mo9G&S~JH81@m`iG~H=&{O_
zKF};*Z5^IeD=#oX0|`5FZW)t7|9{3anW5>NQ6gQKPl>S@;lx(71Cx+LzZceKr?tj=
zG<=51MPQ&HBADZk8?C(+hpJ2T-+$avOSsDv?@jDR5uK)9^HjEly|?00#UJu5Y_@W2
zQTpg;ruc^~L^Nr+cCf|m>i)1|GDGnGTegRy|Abh;r>^2iHFIoi8D1x&^H}MGUeq5U
zodd-$e{1XfIKr9Vo6-H^_FL$rYye@0hiXpUKgRAs{|p+uo0Js{e@6-w`K(Wb3#YUj
zIEF-C+B<2Tz3aYb$HZ%Kw8ZLMA-wvO;yt#o@;^dOd_m3?)z^>W@)R0>O_?+rr_COX
z4lnpzbl=nI8EoS$e-nGKR3kNexj~?R8peLGjRJ#sE&jFyIs<}=jRXDL6XDhHacS4C56T#GWEF`Y*U*4*Tw}x?br2
z{q}1L=*kwpQ7&mQ)O(8e6C~%}`}31#uX}uod(C}v&}+^EyaHWn|M~SytuD30cjQQSEDX
z^hJ0LH&V5y*BR`X$)<^!gpm>F7J)GwpRw@6@~M8RfUkP`4-TX3{MQj_0aDmp;;*t5
z7CUJwWLkoe8^O7%z5OQ}
zlF8Bo&2S?}XdB{r9Ehv0qoM!PMlbt9T70cXQG=haL|2F)!u_>aX~61vW-|!-vW{cZ
zlKgXV-s$$RzP*pUQc3=J>KB!@t`XuNi6%-*UMn*xYl>ni(9aIt0vr2028IP2>Ge)q
zroaB^F1ThO1PlrG-<*=w2{THe5&6H4%^L(6N3EPtIMiiLnr%SbGNg*ZD@z@~)$
zo+V`231WhSu;dyo9@!~ug5yfop_vy9KFOA1r$`FPH&$}0TK_jA>m_!q?cY%#n65@v&(aSB-50Im@x+#i7U-mFQFj*Hcy*ekJNoFA!1n
z2MQKcxkwdR$p)M_>#DF@oZ%tj4-`mLDu26<K2z(WI_N$gOI0G&L)v>@G7abqQTh4!7vF?-KpvsC-hd
zdLmUgPAv@e>ZVr!)-rd*y+hu-O2U*ACc}c0k|>iJux^
zDz&}Js|QY%?Qo~&$ZBio+P3h0t>_*zOEP1kKfZjH&6qFww%UhUg
z8;cTl8p38n$J1c7;9X;LHg7G&tMeW^Z38T%e`!Y?Lc%y8iG+m0=E(_b+qCr{Z?ODC
zd79}v(u%?%tZi}ZMxrw0Eyq_f?pcXl#^lUqfs)>3gnvzr!gh|Iwky^!D7B9+MKBN?
ztFuFOGKuZr4Cxrwlf+*g*>exCPrDnh@V_b#-|w+)DUHT0pU89Z{o6O}O(a5-97Sdg
zo6zhY2PyTipCI~_?^W|9GKcVNH`sH??h-V6aFuRHWRsE+
zAMD*k(p$*R&=4>><+}zH-;QXFsXBfp>C_np*=}fdDv^xRPUO0dAsy4bjU9g5C$#J?
z`O?-M{lit`@it{;mdu@8cWQQ}Kb42Q3MXyL#^}76+nSB!i{oId3OdQaXyRXuwctOB
z-9GN_^)Na8YX$AimuuE+`A7*?G!AE@t3Jx_^nJ^RnKJK<-RZCF
zoo*~~|M@pKuhN^I}l#w
z#SWFR0vcSLxQf%??`Oyd{@Q7{Fevg0za*xqOJ#zJCle%kvOvS=ZPxp5MAUHSR>gvH
z#VZSKSl3NbYGcvnwT(8$x`TDvx3n4r8`^r4Je5v4;ewQNvFi~9$+6W`)tL6l=AYQu
zuOU1>8IF{FXev8szG1#HqCw$dzRDiPQ(r3&uLn8K@z;6xBHL5E^9*)^*NrTLEt6Ys
zEwcgXSK0@BDJyHk`De3i&e|+$m(d`cLtOS?6)d=`UR%2=WzHMBtKQhV%C?5&*j4o2
zPl;Xi1`GQ7DTd7cj#P)$@1H(8-sELhqgsMT!5s8*3Oe9_gu?&{oOvEO7!xhI{3a`w
z=eIW=zXb-pk^I&?J|$C_#c@Zme#n<_$!<~~4q={0VD^a8Y|$@d1Uh_2))T9gY&2jKX{^J)^*a?xER>Nz
zd{ofzRiw@XB9e`(7tv=33CkFOe#Xo%GFRhc+mKEmc4wxo21mCXFhFCKQ&dDoz0*@p
zt9SSg*7SD!ynTH3E_>V9U)90Xl4;K*iIKDr7AlCGr|pjRSix!*%%O&
zh*c#&IE6A&D&!$91me0szqFxOy}wxS`>AX%yrN4bG~$N29InlX=gS3N7bm;GLHl&@}{Un1e$(v2q0)BpW!6FLz3_T<&ctMzT$l}
zNH0mqypbv?H6CokwxAc$Kui?SX<)V~pb8A`t&1wncFHu~LjT|{HcxWk1GWn?O0$!T
zD2h&a>(KielyYduOpaftL)=V}Z+J=Omt4eAqSy*5GlpYd(Oio~?V;`B8KNccsyrSR
z*Ve0VGO*T|k_
z7zjfy&p<5ZCMc{pYKxGH(Y{R_D@GK)L188;e>SNJNY@=ILC&4P(&?8aVd7WsGrt4@
zC4}8Yea^mx&{e8?J*CG=>BLhT7Ej({m+5~=P@^B@E1`5A(jGnBri)$*8;PGr#5c%V
zk1J?<+x72Xih30%WW9=jB~b1q!Ct+xeOQ;r<~Ft?JtiSNSjIsmpG~Am^%pPs2o3{`
z(C_tlFaKy1r-_mEf?nRlORHoVLjQ^2aY7e{Uz$E9#dpzBgC3-m$Q+L?VhA<_^uDB#Nvmgo!x3Smxk8s%gprUF>}_?iy@93iAQMXi&sJOhm;%
zdJkLs3;nADAZ3Tq{MQBla(^9bKBh~;=pTn4&xjuz7g*LF<;@I6CdVYbMk*8j>
ziD~W2+pst%4JnhyDpArLjxUva>;j@g~Vu{T2T9n*WBKT|c0|
z9o8YMV0%kBiysQ#(h$Jk-_iGX_%4|h*a1^W76zdICs07iY=PaLxG0j?TUrjLSjq6#
zLjUgO;?>!eTa2p%Hdt81ngC%)oRU|{J?IGx20iM0U(6L&(>zk738Vl|P5m&gk?0`>
zH0qdvEZSB1!ZYE_f(0!V20(%4FXJfJ1q)pj>q;VYdAZUt%xJtoJ}b7A
zp3lcGX{@A_LORCZ%Zw|Df*|xot52FT%>HD
z(5q8Y6E#)Q2h0_C4I2q8DbSFf4#$iEgm>~EoXr#=homnNn_H0|nmy@iDRLonsG`F-
zbX3cS;bnD*KK#leE=@_s#*?IzZL2orkuXyrBqEZ~3dB3kX+yG?%q=L_S;1ID%6XWh
zI^FuacL-u^bc(W+I?DNg_S2A|yF4D^BlZxJ#S4)iaiktn@26RosW(`i!uAqvz5@x7
z(odDd5-1%t^|RDKf}g3Co+Iw07qd5KdMStCx>#OIxSkXbi{44F%|!thH$8-CtmC?}
zMG?zviRDy(!Zj3;a@GjYtw>FWltn7K)U|3B@B(N$#kXoCVGl?LB+4or#0+N)3MJ;WJq
zjDqHitl;;lJS
zpHML(#MN~AD<7${Z&1mUNB{kMPHv1F^+H<`aN@{=7?!*ECK0TSNPR>S1}qH_d=Q=}
z0|>Er{X06E)M*Gh)DW4?XO4~wWwS=IHS`~7Z;H!5UW3)0SJb2u5K~%<$A%{lfM&-hP(-w16;%IB0#Ye1XXuo&8K
zdGs&QhG;;b?{D+GxDoGkppa}V4``r&$k*wRmKQb{^jR*K-f58&G|+!u*kCTnzZ3Iq
zeDoh*Yy2HHKKiF*YNRj8%mD;W1vY-W`P*##!~Wn`GJ#KE;cn~gN@JaqC4qJ;4u}bR
z7Nt-@hZyQ?HE5^k*0u?@)vJ^*DSjiY635;^iU(dP7EyRf12W*8u`irPGXjSDBl)PoZc%S!b44iXETEShW|yC8#wj&
zJcuUKC8gX@m%e-%N9Jqc_h`-G#ur2NZG!#`sxaBh<+T;+R#~d3PrfdV{aY<;d`FBjh-^{%Ym(<;nkfNiB7B;m
ze?>Jz*B2zZNiPYB6Wlo_Fq=ZFc2=4?#|4QSt$kCvIXytN20${X!El!Fu9b~Q*Q#7{
zdU6Qu!jnuCyzY-+(P8%~tpoL@*Gsnt_ro2{4h<^NSc<&J8pzR`vFIy%WT&ytU8e^}
zi!a68Pv{?0RGk?n)-R>7IYTwcsKzdCr23FTF2C+NrrJJPH7iO>8eW*T_*c`2pFN`f
z;d$aLl#(QUNe1Km$vVb2?jKfBO_5;3ZUe(8p?FT5aG3>=cP()lqgN)
zM*nbaE9z=7SJ4Y9E8P-o^1H~klgjKs%pBKoI4&gih0?M$WTtb(S|Af441h?tsl}>0{wUcRD^r05439o8QB|3K
zhbq)T@r4#`y=o8WA7{xqQUtWx_@C4IS)(P+&rW^`N?H_;%7RwAnM1Hj6sbIL_Ov#^
zq@ob;(A)ybWrR_owoq~r?`Ez`R$jkOOPi)xGa)5vYX;k2l7-}n5-em32tA&HK@
zfT_0@pL18y;&TL}fYe|~DFM#njDwy;K*yVxT;n?azd^T?@&1jI{RaRUr7b?R
zk;IRUuK;Nrhd|r|oh$?!P*h)0-YF!T)Oo7Je;^mt>HB}OQpD+|aU3cb!wbutHAFpE
zG=n2#o4Wf^4S9?XkW-hHMEoe9Y8gk9o5ihyId)ZOg9P=T(0*Brg)8Jl$F~rsxgKtH
zWN?@>0<}6_u_e2bM=u6}bJTx22GIuU)FNvI(*^y1;44F*GSa;vT{10$8YwUl=lO7i
zZwnC3oWU}
zL0)2XpC|@`C?uaem(--3SmdaZIxU^L|3G)bAb7F_#a565n#UbUb+movTlg3M
z1-JF-e`RFJ9H$ma7$!NMhyw`D_$(9QK=eSS6=-xw$1Q7Xzgr&}dq08e$YBQdh0KVM
z79u;MT9Cz?OdLEcnWHDP5@Ewhz>={=4ei$C0c+AEV?!{N(LW^XIR6#7Df?pIodrt^
zReG-Rxu#~H4<$AuyE9Xn1G`Zc--1waZ&KD4AH`^cTeWU)zy
zzr*VIpUAi)#Z43&;R1YeuN7EfJ>Bij%xlKE>m+*8DZr${aCURyUFsU7p`B|-
zq@~!hy0kZ8s_{S}o{(!MPwcD(IzF?=p8v0azgm1VpewDxTE5Nu&^hE1x@`UiNrCDA
zS;DPWD~;NIwU%<3%tLQ2lS;>;g92%v6kBF~K0ec*vxMEM?ZVT2%TpyN<2GVh)l7o{
zD^$8>-BGhj>(N_+t(JvBGb0Q8H83HoMgdXSG!)CiDa*CVvaprRu39lpx5dW`4_54)
zwemTP2W&KKe2x?3pa29tNw@{eAv}!bs@RsQRZm!B2rfQeQ2G+YqRdI}=VZOQS=!tH
z^Ep2RkK#DTk$&Xw)!IMUsboF1MgVU>kiX&^I@_n>}J2%
zF^~i|YR*0BbAb$A!$?J$Dh}k2MST<&2&tQ^i+0yvDHe~(>_c>p&tROF7U(0Uhx5%W
z_?Zo*q2OQ#sCF+Pb5i6FWy7bXg#VCB;WL3QeMhVazJXAbE#?%zqxCp=nEW`&*QkX~ootlx0Yugkf2H*``DofRFY@9UfS?Cnza6sB`j2u=ea~j`(V~bd9bi#uuyUP=A#)j
z4{W7F-$_y!rsyUg`c|I8YQ@}S@5r+gMkKHpOwQ!$koGTSl%@kk{=ohS;IXv8;Q1`L
zx%vZbuhGi5I*dP@NU=c1_2T4ILVVt{-
zeiLgsryn`0liz4pX;&u^T~X_k`DjWK0klb@En;32DuEA}j(b@G)*|ZP*o$zQY5UpY
z7OFjYzo0b9AkqS`VxhVmhQ6~0sYcF#nq_+t`qxKhzC`NEHfAgb*CT$hP1@R&57FEm
zMRIzWFzGPIQ&0~BQmP?(@oCX**KwEl4E;-?YXJ{9IRG)R=Fu^GthlmVcu5vAI_igx
zAf2HcTUEIa{=2*aJ6~R3j|L+$VvwY^xJ4E;NF>w6bTA#y6>Q4bEOhUiENU=A9d}#3
zlX|yx*7&6`dO~|*HB53fgpHW1Svsol{vbO663`
zuK6UNqW@5u|76zp0-S0@yBvIq{t>MsBiq)+sqYH#Df<6SIJMoXH%l`r^!x+jRBX@M
z?%uAHfn(uVK2Qhr!gq+B_J=AE4W1*|YU`);+&Oyyq?9Wy+>m4K^6ks5Me}c+#!nDg
zcM&f~uiw$taWszpFQ|j9=HCRxdqJbpw`gHuda4n75cFzak6v@|$7HuHuTH@`soO^X
z9Lp9OqSqb=!cq7emBl}%6Mp1CPROx^#j23C*_|VeVn+Ejcl5vDQ;!VNh){qNb<&qs
zU4k_VYlo7{=34}{{r~KJd2`!HmgnE|EfBF0TXK(O^U!5?xnn6(vbCjyCh3x^CMFmZ
zNlDzINEMHg-O(R@fA8gimp}ppK*^?iYyQzk%x%MondhAkU8ECs5ZKB7|Fvl
z?j-1u9E+uKne^?+2o5M>r*v%?5K1#5CCWK5Jt2ZmRM@6(j8n`{<0whNxx(64!)$**
z$p^&wu>c){if6HoT3``J=dbwdu&X}2qf`m?7ihxf)*IOa6qpPKp?MhduhylWh)PBy
z8nvK`N6H!%I1P*b(-Dn|Y}8r&Xl5QfY%IS|G8Z8PO-n5zfwwE5R$6bBUTu8q0IH0-NAY3&E7bIEc^HMLb4k$_4L
zddmg7*$aXllAIQ%SuAK9m><$3{fKAJw2eebKH7O=VL;**g|sUz8bX(~&mcpzb&1^2
z771b`q^ht|E$*7Ml13Ane{4|Nf2Lv096sxA6@CobOwoV(6$L<{0U5;ic3bL&KqVCR
z4hRzw4j;-jMVhj83fsomxIGYI>9Ro70llhdHH$AG06{_xCB70AkxOmV1+=WbhSJ5&
zSWeN6=zmNjb!Kllhn3-}u8FrFWy{LG$GFR!0=G*hQU&Ku`9@*!dl
zH0(d_LL;bko3+-~;_RZ~_|nikYO7JVpinfZW^2mEkE!00G^L}P8JZkB1mvc(V5ts2
zKu^$j#W(?|=%%6^=2%Do41H1r_*fgqpNMTK;fTg31%qa{9z}wJ9~=tJf#GOjt!i%0
z6%LucLc!f)m6FVV9F!#kvM|4|JBL$fgD8D>>`4jsQTq&4nw5#yOZq=nM~6)F<5vW5
zB-u#)mM2lO%R{;G*aVERAb!et+P@v$Cz27sujoG=pQP;3z*e>n>zLwzsz+q*Zf>cgz=BATqLA;0}k%5oFBb{%>k-tCnexh5ie!lw2Z^kgj
zEE+w6plWPD0;yFhMmS}37R$1EPU7dlJJaWYpT#*$I4n6SxzUJdj_o)JBi6DZ@Hrsl
zCITX+VPV7&plv`!@jdq1t7{q!HNgvQ4!|IHcW3v)-m1O9ElQjGgl&O(G}&hF9}kZt
zWFN0FeVA;ik?-xe1b7HE-r+HSbONGTN^?tJ`n_+WjC5?RfUlGokc`ipfRT~qr;I1&
zN{9kcmY)MWU{o!whyl@5*vKkU!qH?Q=@VgtmT;oIS~jR8)zTBU*_hP``NUdy#FKSe
zQZft7-kR3zYc0xXi?Oi{(Kx@LBwt`jIGRlsl*A(}<+6<+l^j;{K3FgCxbJX$jch-p
zFU@a*BaR`ZsQ>yeq;cK#V8h0LAd4Ubfnzt2Ji;6aVg>gf&F4!J?%S=;s28XUK0_XY
zhN0TQ$#ezm)|jRA%SF(N+_i~%O-ko=%Vlef`_@SobBS$y~frkW3E
ziK~nVL+XQ{&{+p|I}9Z+Oy}AG}%G4t(O8Iq9N#T>7Mqs(_16sfX~R
z3{Z&(xTsJWDf*1c(cd|u8&&Uc1z>bj0a-&vccq+z+3K?53T;h7mV2bMQx{Dat>d~l
zSDedHyJh~M5K;UAhsDvkWMFMJz}MR?eT=|f>Z=Z3_tVi3z-Wc*M|9Fa@^5&wB;tyL
z#r(-fOZzPLPX~{iqYbMCs8b+mk6`oRxvCO(DlugTiSKUTvZ?Nd8yRhVBZ
z(tHn?!mg))X(BzG_h+LkVqsUvWF>PN0ZWCFh_nH^TH>Te>AbY%Kd4QXD#c@4<+2S?P7pg9!{L3GuP9tb9ruXaUh>=mE
z>IHVo(~!m(Idf*r){zL6V-~~)%YGw}JqXd#Dv~5^(qAyY{Tm6Kx>c?l<0fI}yDyku
zDvgD1jE78^+8QfwPrY66^5FJ}XFH?bzKl-BNQ%RA!$glEMPX
zDjp?Iy|^%vD2phrgiT9XB!eiD#p+ebY|_B|@fyD0@B(1|1ZgzK1t`vDSV-}!${C;b
z1odDx1Nui~(4^hca{=XaHe;`^VHLRjHmt;aEXqer|Ez4pw0F2jey$)N4kd_qK(fhP
z;Xo9QtAsHjpWCRd)b6}hvZ`YPhdJ-}kM+}+^xthZ1X1+g7VBX2=gSuAAfP@0nTXyG
zdown!Q5Y4XTQd=9Ajk!!`A6N*#G+&>}Rr2B|o8cI{A3Wh3**J;F-W(>qYsFh6;2
zI0&q-Su*f-t#{ftsV2?cmKm4;m8rfmVa0VF2Osm6}o&-xiQRp^f{538($uKX&
zU{=ge;ik-EyqdPY>wr)Z5R<)kK$`aAb9)tp>4B%GfimWQa$1xIWdd?0D1QctEA&r0
z%lx9k0p`yVe_GKszxGj|!&K-%eU4J2w3jX_MChSUV9-r0uBNonS1qLlz+}Frn%d*q
zWpt%N$Fv6V#9razecc+dyc-vFq&eNr6*undPP9caOMX%3K)jKz4m5V8n=IR>FoL1|$&k*r$BQZ;|mVn4$-IXDoJ-@#Qph<^{?c-i7$Ivcr&ZH2Lm
zNK7X2%$b~2Ym$eQZQq8ixiN5wNsLkHZ;Jz6+hOP-=7)qS+>hR3usIW|=vYkP8+-A+
z4D1c5;RO0zhZZ(Q!Am|q4$6u|EanXuO+LPKKm&Y9LIlDMDOxN9b?O5aM!I$|0kIIq
z2V<52i2$!DG?w9QJN3=Opj=L9VMV
z;L=C)xdCeSl_zC%=c~hz6VABMm_Mm{L*Xp&JY^j)KM*x{VF%6vZ?8(n9;jq&<@U3W
znMqRC!TcaYIKk|x;F%OvC4#Tcw#NKcbp7L#N*6!h^7J>B|)nAHQ7p246DC
zbsQ~$G@^ZqmoO%vN~uyhOqc88oX?0|AidTWWC?82MJljEQK`Jj
zHxxpC>QaLRd$2l~2
zo!g){6&wR_*`A<;@oTjZ5L&OZiU62j1u)Cv?#Z-X3WG68wvdkXDG`&I}{-HBA=4GfUAT
zC*D;G?rWuic;Obga9@vjRDWVv_mS#GpQAWOeiLl;*4
ztO2$|wYIrL6qUo!0pJ?1hAEmQsET`~gLGxF
z9A0We!W{z7pVfIMe%HG<-_uw?DX!JY6$mP8$#UG-u6pQ2`MSh&Ke>xpr|43Emdlb_
z2>{$7Hk>-Ud%WobOR
zQk4c?7!;+nI{j>MT%1S0uR-i#L^Zro5!4-)J&HpV
zHf3{Rt$9fJz8piVfy)5@InhN6QNT+tlSW8iA!^F>luwnKc23K$7G127=EwTFTn7={
ztNVqXV#*h728^k`#((X^qTkcvjnskQZAruveCk|u0fHj`v>flAp-FgECwH25a`Y-1
z1tVB5eRD~smAxVY;0u~lk`;*GjGKZ+D
z`Qiqs+}w4RO7m0BV5Y^=axyQ~_ilhLd)45Ws_g9ImAY
zOs3}(=}BCa2jvIZSm$PU-9itF|HY{E-);Wy8vlYy?ZnwRfdnkytjb!E=2Qj`BicV;
zuFyT8-u)dQ{}FKrQ+kqkHl|ms6`hD|oZ6_(e?$EK9YX3+`=s5upiHh>3vUAF`Ugfx
z#^hA|HozgspXtZ(RHSKJy$;QyRVMWC;wa{KvGfThOv5zHe}l^@a*Y^)eaQm2U0`!e
zRmoUU6rD8GaapNEEW17|azme>o6LW7a-Gx%JbOegEdGKFjq~N*6-EGg3-e^pFPb`N
z26(6}D?Q>$r-9_J*fk!o7~_rS7X}U6i{5NunJytSkx%9KV-YfkOw1(>72kRrj|9ZV
zG5>Iul!@v$bUEPgjtUAOLkZKI%b0%&mTv&*S}8#l05Fh{tfP%-EKwy#A4du$p#9HB
z@rzfS*LOhNyQdfD@4IvZ^8W*`FR8Eu?7b~-<&KgxOrSg8M53%kZz94?BO)1#aeNU0
z7koSIE&8{QbQL|3sI+FxU%qHNpeRPC`Iff+DCFFT_xz$bsP1Ng6Tq)CecO
z?{O~YYekcURN2?U!H~oT7RaVWs?I4afnqmW=JuKbh0{{>u=^JZq*YVnT|6Mk)-eL5
zcqbfaXi3!zbO9IdLl?kWUuB;VmZDP*y;zSG8aNX!-{vaC(&2evqt?J)TB!ZI$i>0A
zM~rmxUvrU4U_0a;f3TaESn?DJ^fJLIl}0UTeyDu+GgT^^xQK^dI^2Gxs!NVOg%d}G
z31o!{WDRe<({s;8XD34f7XvrSLvOj5;*t6h3=mY~Tg$GvscCF2!tm^Qv9Zt!f3E==
zdh^C`+UT}fkAgBo`3d~`h{BIoC`i<$Wx?j~4z5%M{P5N1)zXN8Kjv4Z$w_0f%d$Fl
z(zG}_b+v4|YSPj%;bcl{z
z%%={$Wkb7IuJbVtBV;rIFrAHf_o2L+C
zmA|2FL1lF6dygjl*$^In%&(>o=S2-}uD^|^bBF#a-V|{-oZWF?j6Eec_e#C;*Tq-z
zo^@KM-Nw;rE$_p8I_ak|yhfcrFvi;%i66VlBZ+MrOR;%H
z@q;Qu0JT}g*UrfdiZc#}M^~7p$;L^$0E9}fXbzMpHFL5CE`UIT;VRP59P*;cIu#5o
z(Lfej(H3Y>b{fz~a)_XX`LBnl(mSR58O&7`!#)>EW;L%rogv3|p@W6d+R}So{(Bfj
za0snNqt>Z)Keds>i7E2@)0XBA2j7yjmoBzIhHE6bIgz~j`AtkKFbV6A^`k$8r-!rD
z$Vy%XchA_?2+u<%?OMg@GbHBs(+Mgu>*;6>;muyy1I+XwqbQ$``BR?`rJbm2vjuAo
zRmSI2#b3=Uo=mMkox~E1=?iOxl{5CrsKh
ztv)n-m`OBLzcCu>4|l!!AA~LIV&QviOJU*t?bq%Dti4RrByJ@j;R^JAuaR2~%kO$(
zx$$u^zXy5O#_q^H?hSN32MKGD>m_jqlU`
zs7EiXsPKOS;lXV57Z9Fl1@^{tKn-V!0OLmjQft?N!0qq=
zP6zqnD`81z5Q8Sxk`tI#2+8{%GtKWvC~z4w$H+!jEmhE4#eK{`R>jlJm>*)6e7rdk
z+dAr`$!Z%31$;R#V>_U6%Xs_|PT@>>L~(q$CI=2xCSYV$~^GSV(Lp
zI7(t0mogF_qiW=YAtmxon6%CizGAW*8ma+TXcH{sj(TqC2CJyjDEP)21(UcViI;$y
zlGqVxGE_;SmirME?!$q}DyYLFNkO#Dz&Q<*G@);xUy4I=Eho|s?VIf!OGBnPxWPCe
z4)0FgPM1guz-ub7ToU2?sq_;mB%xUPa69VXg2Tai!{Gr#+Z(dGj^IIG^d>p&W}zUY;?5viqIl;@Wk1|<4oQp-cLI@r-#AwZZpFsS&U1#
zprH`A>Yj$O7;!Ekbu2gnWKKF8c1p_3ct|3j(FDn;f`_s*h#@yp2+=FkZ^A}(LPw}0
zAiJ6{#}N~PR$rCq@`kUo$zgHzAa*>MP?S&tf{}TK;Ilq0g%
zZ)2i$$^=@$grmeK*mR`BJYLC%ZCL8LILy{L(`u0h6-Z8ZKA643`%Z-ZWusp6;4B_v
zemu#@f+~JYKx56)@>_yT9ct$ZhZIX8#}8`t!&nNHWsvZ5fU>FG{`ilsc`ZQSdvjX>
z?d4=K8Z-G+3J^{R+X5A2`=GY!={OX?Bw|0jqGxM*v#+F5;2z;W(2lquz6KZ`R;1P0
zbLEmw^p|9NAa5q=^{q;
zkur9Y#gFrb{W!-+Q<4SR=$W9z(x^;eBD~$m^gn$tpIP==x8epPxZY4tc
zxe~6{rYaGq&HC|s8F2r`R-{L63k%pJGUI-LJ1@rfT{zoSsw&c?@Rn_8c(Q{26&`99
zCF@^u;5OOF(e)Pf!6FsyNwv`G=L`QzPmYOfWISPvpmk~jk3_0aoc2mwYj
zZC0Y95TI?65QUW0A!44fVThwM*ju#j69Qik24)JS1m2o2lxI+;ve4S;NPnX=2}%H0
zFHX~6s22C$j{HlN`c)3(pLX!4%I=>0(=PtBTXu%pqmIZukjHV9^UZuR_
zjC+i~ewvJ7%p!rG&5QtidfYsGx42Z^cLU(gr8@GMKWcsxR|_}mvi8f-r)C%B`SWN?
zT2oRf2y;dQ%BWW{(;Qa9USE`#93Wu)4_f75IivrH-Y|Zu>NOQWFhS=!k7fXP(0x&J
zcp!qUO_1RN5@13*L?~h!Owy1I5IH)}3k`ythDaV{b4pmQjcK^{fCyDt_&%71X)*uz
z!?bd>jQMk88u~~j%ZnU2pL{Bg9L|l%iW#Xpz-7+4dUct(26LXvEDCc!##Qc*v90fT
zl@TcSAOGQy_;1KGaFr1jMuwP>QD$HosTV=h`Fvy^RE^b|0(4&7hsV0eIoB>OGKpy+
ze?oBh_2_1)GB6AHjr0>1s40Q}Q}K5D@LH625^IZl{+bM39-bSB&
z^c62>Rf_SgYGQ9u`h-|ixb9R%Pu8Vy*3;2aZw5^-5pY6r0!`Nc!YFQ6%(k4r=!^+3
zjk#_xcdbmFz4N)sq1!7w1m6Z%%!hLkz4GakdKsZxs&wo{f{oTF9mkX{&y|PO#Z^Mc
zwP$N+N+8^%Xh?GZO*JKAHBc5I!F?Z13GHx{}L#gwIh_`kzab
z$(RRQ%B@e9t}ny>lB4WyQNROX2Jus?*+~o%ujCy
z^zgo|T7MV-;jGi<>xOAERINj*y98hp8i3ex{MxmtEN5_{XGv#)ju3lR5D|duo{9Ex
z(^<~2QN&c}gsx!^KyzXFcQQTTycp)H$MDPj2))?W*LV+VJ?hy4%fj&W3I
zzjwc&w_b*`*>r|EKJjhGaQGWt832YyG)`4nkp@K|u!QEXotFqSpaL>{ffssFb2ws=
z5T-6D68m9&yX#H*98gOUi(HfoG5^8^uWj^n({%K|fhw>6FO-bIZBb=og1aR=k8t7N
z;CjQ*jPnF?0AW*mk0#wO*guz@iROjny70Bn887^h!%T^gDA0yVWL8#IV`m?pV!|7J
zI?ot6#z;&(sw5QH3TA7OCX2+&e8k>W9Yg4l_FGjE~!}74h%;VVgiE;Aj
zEWCZ8vG^grsSNP!q+J(pLLAy$FOx!WKOJ+B6yrW9mX0$)tQ-+IqG38u!bZ=59>741
z=h!)xP7wvL8;~^)tbiEq{YLC9!aQhkd>uL36lHar7pDll>f}jI(zepZAyQl@*okVT
zf;ds65Hc+(^bVBPdIsoEwi(HA{Zr-Xm^d)F;kd$>^4Pr!
zE{WxZ*#d~npaUmKr)#@t@186l241q5jc#s0Uy1_Za2x-X$iD{TdNM-c_jFG%5LG;A-B=L+dG-Ds{+C|@dM3$E!
zi7e|G(PPQmFwmp4>|YZW}*gq*bj8Ztwof{y{vhuNb8^s-e9pnC*Rpm8kTtb)I1BB5FYMbT56
z|3Y~CCi&qr4pWL>21E1=`E+lL-k@oeN*UicqMZ)xYW%9
zvCX7zhbJgMBqYeXl^|PWKp+Xq5h{%2WkfF93dpFVd_jqnlqJ8ZK@5@7LWj}jNN*)e
z&D=(1;fnSkzd`sw>=yfrP4WZ{j(dc{Z)dID;0hV{wQ@y^I$x~umQ`6&jCBmJZ^CI%
zqQOl0v$Iz9zxMtc6NmN>1`a41OKrKt8A<-MXmiOAw5IU_kmA)i5`@RoVCi;|Jwa;ZASzsruX;LIpW7)9MWo`
z4&cW(g(9B&-#9CNP>Q#+`LA*Inl3+_>s&3wq+?>jEX=5$D9Z84f
zzK^_b^C6Wh$-v_1tb(g}W%TGmeC?%SMYUIJ6K(Uz<7x<(VMVnhKy@P-Rt?8@R%?o|
z-%81{EK^^Ec*%#8V@jcci5JFOs)9*YQlKCev~@lJ6XD#&n=B?_j%=xweU&O#E!$ey
z!C`L>`{f?QY|8$lN+uXFoCX(}CnAbtf?$y;h`P>$0g2wUD3c
zaP}dmK`>XG236z&#TQM4O*bex#s&kRuKuA5yUXE8rzAO2hM(b{^AeIh>v|>qxQhM7uY@P9J_{Ps3_t(Ob|JI*lKH_vK?;XCP{uARiZroZZ8Fjb
zR~h{HKfk{J2fw1Hi}Iu)4ZlSwu?Z5F2Wj50Q8A7)J4rZ0)^|eAr@)!`npfdW+1{4J
z+W9Zt!@RFf8=OfYLloz)=um8VkhtO?t(Kznr$raqKJJPX(brX7OOiQo`=3<`yL
zte~vXBMQHA209~~l)m&gU?H`%Q&tKViw4PqSzd|XdcBx
z!db0UOE8-zoV|UDoW-q#MrA|R(;AgbqcjoBL;It*(Rn%Ca3yRj$}^(<%93Z~=vR{c
z^79%uD#Lpoo6Kv3!L(Acd0E@R@e%kACI)m{XkK6%#-M2xd!@Gb@&7)-O)Ghr5!VXZaZjMKu3$FUHQ}Uktu$k9;w3*_h*F|5Eoz
zycfx0)Ov~s=6~vYv6JO4$Tm-MFRG7!FZilG^1Z-a^WKXnome3X7NrxE!;ik#BixHI
zEVdN4!wbtRgGK>3XM`!i!;ip!+(>*;pf8Y7=u8cY}N~o8?MA7FZ
zpc}$H&81&;S)9QX@mQ48kB3wc=0o#qvINcBr{qS6PgP!^EI&WVC4*}8*j$P4?IT|@
zT-;2TY=yx5-7eVy#eQVGX<LUR{su8pOD~(so7<8w4Ykwz-}|$w=GELXs|RM=t)Z
z5s{@F9ciHxyj_PD*t-P+j=0tj@yv0k@2aD-ybRrZV
zje7EkkLIlW(PY4drePbWha0x>7)Bp2=iNZqpePt698BOsn=WS%6Uh9C`L#J;$E)4p
z(L@XfOS*SXuG-}s3Mo3MR6&dB0hGJ~3_wOm3Pg4nLe6f|N$WM%1$z`CqSvLTqkd{@
zWY_cYnX0QGy~!e%$Tm+RqoC66W6LOv$&W0f7*r;(JEv%nIR|PTtU#?an<(aoJs_vw
zCMRk&QxFUDtBUMTh+4)^=0hyZA2Gd@VQxi1Jm*l>LoI{wKE%TO8Bps$qD_{cp9Hn`
zA0M?CTOS#BWCU&xRhWRJo
zN$g~QALb8(xW28}>DA|UTzw7)obO-h3&&MGGES|sdANcHV7iv$btMWX2_>J-@h(<_
zWceg4HX-4~F|M>4<1oLjQu!DGdigO9^M5}Z3KTuePlgMhsu%UKKMBTRescWyRJ}|%
zmp?KlIhJt;i^(FmmBUy@@bxgEkbX&xWsDIFBTY%^F4`zl&>d{2f(MyH{UWQIuDp+~(GI$gF
z$QI!$KEb*h?a1GDUIfDhN`uhzo;|MJOpDs{H!hc6#JLjY7dM3#C&M>aY6;!Iwpbxu*rkcLAp2*J$Y{oZKM(5mQU)4
zG|MuS9VgWmbPy9vqElrROd|bwCnD_$COP$Q^^DT6lfB!Tg3zuMg#3rS$%4?H6ohOP
zuS`0G+ne8f(Joc(5~}LLA$#wyI83L4|5arb$)yU0LuMH&#KI0F(fW1S)AR^=jhseB
zVioWU#n33B3Pk&hMR+WQM)A-olURQnV?!7|
zkm(rLGl7Lp7;>`6R7o;k0S4bt7-by)3-e}czKGRi8UBnA9`TafPM1!>-B4h>ST5>Icd
zWTO2ln8R=2P7CIU-3K4-k2cB{h7l*K(Q*8d5v%*H85*%Kh#c$eKbBA6KoGf#4UI@4
za-sE+Gw^TlR_wjeE!l$XH9}T3t&0~?h?6?pQt4}mT9EzIK9(UFFY97{DnF!3l=x?Z
zk`JXkO?f-8r19`Q90@tKVQY+A=ODZW%{-+800V9uyf*ac;7vu3JY
zlirNaLJ}+1O-d>2p__E2UDI8>*A(eCDQbyyNAcSs;}W0SYfY=*L4*`~K()#8-Wy2@
zv$#h?QW&+LBv_=PzJyg_RPm}Ok%=A&>EOfzIWt}_q{t4({D%CJNZ~*|#>v%NwdZU1
z6%lA8sdTZP?iKsELV5_(BI>l2cYS8UHSp!E5;QQ9w6D#EjxSO_UuhBB#K5d%+@
z3L)4mH5C2dPliI!gO48H>?I-ju~?qin|VxF{7J$Dg#gx}QI5adkhxaej5bHI4Jwc2eS^J?)K_
zr(|v8N){hvGV4x?ERRv76%no=NZ%%=JHh^e`Ki`0Klb}LMyYaG8&!q<=d>}W#aooK
zmZ+_SPB-M0gcjz~D#b3odZXIqjAiugxo~6HfGI)iA)zRQwpMeoGH`R#`@2DTRflHN;zWc=iv)
zdUS@uTdqCy77?9?rw4CgE!gE$`O5ZAsq}icT78Y1zqgOvjnWt7V^E!33zA}WIEZx%c?J4V}=*#V%IBn$i%25YEpK^TY
zg!y$_6os4weR?NNKV<(Bug6aB;2@kYDW13I-VM4ta2zh^6I~y^6a3uSw67j&ei)&G
zFkXN~CL?YLB1B$sL(_>;NiqLyNYB`EVDO@c_n*m4O4%-WND}Yd>IZpgkjBS0IV%S<
zJasvtha0GsdN4Wt7S=CM0o2+l?o;$4VSc_!qKSK_#0U3s!N0mCK30RD1G>Wc0cTq(
z)4V@P5Tcza^qS)7U49x8^V6;5Yl@(EdqeRq7+$Ti5ANO#x_AaI*aFCVga1cw?9y0u
zY>D!OUx+(|t?I{};&&+J5;cxaYk8jiv=>g-+(;xRz?DIG{EtFSKr;xVm>@8s6A(*Z
z5=aM*(``*;$304O0H9U?9uXz{1$0N#FCr6oW6F{V`7_f7%01r^*U?1L0Uve1{Jx{bI=?Y}kca&!JYyx0BzlVc5e+60Q+qx
zBmOgpEc(B)$d6gJ1EMG9>Zw0qe)=GkhEq<9;Jqn!ffvw7p3fw@@M(KFJ
zuEgp+$fEd9LP8p*g!CuH1S3!5j@5}ah|jz~-*-VpQa(G~Q^j@h(xbZql4HC%VB+;I
zw}+Zki1s#ZEIx_chOb9_5_#})T{-jzyXT>l?OcJC6xyoN^+tqgF=6JxE=Lx
z5pZ#b8ssG0;W0>(POc!gEoT$fZiB&cro>0aR2C`uy)4An9rdU;z4&#DY%qF{*9;VF
zK_(;tk6*Zcp(mn>7{F0EI^;kjP*QW$8=Xz>XC#1f5FZs2g>*<$aD`L-qVE_>(-P!q
z`|$5-4JJX2-oMigC~Ryp{K8RmG&~w(e#$I=6&xGu0d3$V2hmX;ICX)XR;K^bPjk|r
z0i0Jsn5H)7BsHuiqzKT)NX$j{+z^Td2EUs^{-wdmDKF^~&ZXPJ6G&xx`w|0NX)MPN
zT5v0Pl!_@}hkSSiPx6XD8Qzm`ev-spHs&OiHkac7ZPWEmGJ=$dwfrB3lnJ<1+7R3-
zcpyJ8ZY3VbIw-z3yOT=_p0%vzryb2_)D*j2cX3_(vm@P`EqY_m3T^n=G
zYVBWwe~}Wv0-E`5E@M*vl9BRs|5ORg6?M!MhL=cD$I4SlUG%C~3shznyAfX(@r%2^6#I;f(U>7vRP7UVkx~PJ;P@
zWCvKwhIjXiug0b}hb^}^`5H0u&0(j57zSp}0@RpGX+wPSjCZZxjRDF~u0D^gOvKDZ
z;vKfGrZ55Cj&5!_L2QibOOVZ`cxn6V3tAmbh;lW(<#>_05!ep7trj~lzh|p*^)L}C
z80cr56_kwi4fP5jYQivuC2;NoMGfQsXG46UI`J?9v9#C=#={%bYf|=ZWtl`f%s*6b
z;^^Ud5WH9Z1xgw%BMu1#WRim)MyO$MOLg%l!3c))0m-Tm2iXNgox`RO4+kSUPe_$y
zWv79c5N9#}MJs3?wT>_F*zS4#D7ZL3{SAM$LLy%ra4;a~N#pdW`yP^ffq!^0lT5^_
zEMR>6_ZO9V>!fo6LuB{EZ|%-e>!^Lw&M}V`UCx(xS2z+phzXa^h25s?kN9Pwnc)W_;Y5fN4$reN7)%bqaohL!~T9AD5YdheSJ;=C+i6zuoxI#Da^jbUBKX+zb)9nkB*{AifI)A+z8
z8bS|N=AmE@Uo{LPAzd*P>R=^>Fcb5q?dTku-CMX;gQI$#jPycZQFmRzjmuIg^dw|;
zw!^4~GF-UJgl6+4h!u`*IvE1JNVfs}q1fp&C(6Qe(W6qq1sV~czN$J-jHLRF3fSx}{j9uo4==38f%`13)zW!0gv!t`8kS#CKe(CZ!|q~qH=MmA
z370%NXu)Vh^XnJKG+k8>nfbdDbPV}@i6z{RM|}VS1YbQ?5^T|0$pzrP9r6OW`IQV6
z=0bvL5{2#eXnwM65O5WUF-4C(Et)o?+u~t}C0~M*;RG;2i`WU^XTIPn@ZUc)TMEkD
zfLf|P8opZRr!%zB!~AmqcgEL|E-YcgygyrB$!m*g$8%U1B+TgwySwCy{nu!TyF^3r
zeNrAbARyhRCERRdxz7phUp?7EheRBo{7&2$PqK`zA#MO8`S@SbmI=T3F3@o@77=&7
z291GGq5ed!Twd-Ulj#E<3Dt9Rulp%Z?5hG2PlEaBI;+2%BB)bv=Gka4z=|Vw0=Uw)
zH8i(r^Ei3NUPwW-V|oCdpLM_Pp`_{7?dZDOhdWKT#DhZ}G_qGRxE|8^FA1k+)4xUo
zKKaq$f$xes^a}zTon)Qi6K(>G3sxZyXLb^Z6l-qQ-XGOZFWN^rxTVunvrbS7zWsQO
zCp_Re7ayWyVc`&$neHioZUi5_&c@NA22295|D#aYIwJdu3F8fXPkB^V5$EAIxx0g$$N~x5jw<`p7
zWM@b3R^R=yucu)|DDbqfw7~aGV4>%81k9#Is{Sw3Y~NOenhgxr|H68Ksk`^|tq9wJ
z>Kg@!r;~i2P<0Anl&!f0o3BR<2vJCiPC2X%YO$fQA>rO_q_KhYNt}(0)ZDW!pHM|}
zNVB52pwA?ekBCA~sd6|mUJMmL$VLY34ZR!N2c5-(1)%Xnr_lj4jnH~}O@RTPfgd-Tq_Eqp{GFrS1Iw8NvK%&e}QR=VN{amYex~)&=`gPn)#7Q;M
z;gV*R*UGM<*^mnYUCMpF=<)M;U&K1gq4rD6@t^8iNVYW
zrl6PPUz*;`dUwo1NgH63gyJcK(VSTx!=9F*ywKtBV1s`*zHGf?kSI;CEjqSs@3D3F6p6jCWVrT%pLS$aaaf@mEp7nVq|KP7GpW8OB7d3j0
z(WE7GUDSrc8yx2CVH_dHG1n&WGJ;}a5YNMX!n+7k>y*~T9VSY&c?5gbzAu;&}=G}xx9vu!VyKeG{o?c0b1%F@8NzYERyn?tuX^A
z*O~gwddodyh{a=Ae$RHm7a@)+5cn0o$btiNa|_`kyG!Ri(_ion1aYU0bo-nC(;MCs
zjykqo$~AhS;rI2sj}YZ^!+Td0{wkyVZY=n2oInGel$Fdc_Bg*8HKrj(6p+-0Tu9yq
z6GcXwK*D0y7bZ5u*7VXJ!i56L2@RDE3--P1)N3eV3$5N3~%7I=}nEG|JOKwHI3tnc_i(6+}KbHZF-U0pbcEas%
zdIEO)3{PhJ1J|2Y@H+BDj8t!KNhqLZ`Y9*!&}`Df?JKPMat%YEd9jscoeRBk86DLI
zCCDGQPAmZX$f6Mpk{=ti2Fo;4s?Ag;sM3yNFnN)8kXw0-L9=$qEA>iq_iZ#|wqxudrm}!PIKOr}K^Vv^wtO
zz)#+B`aSipJspTQ&0XG$9RelfrfyvI=d%I&WAU^c`T|UiLb|L6!SP#jr7{TEiA<5o
zr*waWnM#dml9RPw&6GB>gpD{5dIHw)`!qR8aHqw%m$-Z3?a`f|%gelFeCV3d2J9i@
zO04(v6ct)HR0PXYB6Fh0Ts4sRyWV%JEanZf`_SKb4h%c6!^Hu3ca0rGKtl^)Uu@i7
zXeM(ySX*w>+m%&UDz+BF#9<2)+7npk)2aZY_wW_2Wa-?Pw*}aioThU9g0mj+
zj-94mS$J2tf7edtWIV}B8
zx8n|oV(4s@t44{L4oLK-XhZOm-&mvGZ>~Zty>H#Pn7GQ=+WydQ`U3a;(EAF+X{!eS
zX$fj2h^JdTXm9lt7GbaQDcEsHd?2io4Cw058yNv!=4}~~Q=f@aj;@nhKRD9q2VpfH
z5vd)Qj26HImwfNml;gRi{0G80;^ZVWK2fbv?=Fnm?*^hxpFR3y3gr=QZ6~rm<(JW
zDV;_e2);8u{*?o!K+HtH1twfD4AG_bpF&U)$Xu&k6Mtw)rxR2b8bil+*B1+plUV9l
z)>wM4C0|i}LqUIK#mI6*wJnw_2hgLUQ(i61=rbet+)zoF8T&nY-s1=z4k$P?+!o&5
zab-cN73kmNu_>T`sPsK2jC{;5JD~05r$m3`>WhGOczkS;niXH+EYhB68v@R|IH3e4gR{Yn{*K#2;hu0!FD9M)$>e6MaR
zyGf9Q_M&n6PVtvg0EXsVAPDJ4-te2%K|;Z8E3>L1{+L`I+j4*AA!HWH@eIefqE{M1
zx*ilMH@K3N`=L+D#p;gBrHS>Sy_33r-n}SvWjhZcqMfW>E{fdcaqpCcJX+qsX$Bpj
zj%&I
zuVl8*X8)ponQ>c)<1V&`+|qT&B3zU}RBu3{^1f>*9~WDTDR)bJWb#5Din`CPDTXN$`SCnzTg?13`3
z5UdwP|5h#!D}+pKii-ScypcW^CC(Kf2-4LrT)cpo9a8>KACX#0bR>Ur%IdD@N|8BX
z8}AsNO$&9a
zO?CWZJZH!4qyR%~xT2ZBfpKE+043nn+Tc{54i$8Cc%RyGu!YF$J@c1SN5!R2C``fV
z9A&APLSq;yY}hD_C#nUUqJ5n2UX8UJ2PG#C&=
zwn8uuBtL-}`*lWs+&yAE38R&Ah@IpuzdE^&*oIx=SQ$D9doIl!VlpGDwgcXAi+9uB
z!=z;vQ?BL*S+8SFm@+x&;hQ4`VIyMbNc6W-dpg{Ya;-Z}>LoAY&4q?*yea=p3xhGC
zGbUL4*d@T66k6>K6XzG($!UYQ0*%UCTb{oUKfSJ(
zgygFPlF@E-zB^57p)u%ahCt!%#(_$0!KQnq$cf#c*@QRv`J~&mb|>Qe#BT$rxc$
zPs3sVg!t@_4bgjQ?(xI_=08^&d8&u%S@b$%$Ct)B(3t5+I4
zyBH{9ziVP1h-7bXGkP-oiL`m?S?v6fzuIT3N=z}1q2kLhukV~sHQG}?18_B72-*)l
zmDIP&TssvBG$kMoaSR9}eKM1(XN#CCOBU!cxX#Q9X0DP|1cqhIUN0Bp8@vZYX{#6M
z3|20IlZ71i<;WQ#0=qU7OVeRCi&WhaAvv+^&ohL7E_`wLQmEYF3mP>1dbxP`2YZCO
z5eYVjM!N~9808Y&#*|*QU10-$mDgAXp6|e^4~bU5{{r4y%AG|;d>Lf?RA!4>d~?;Z
zHfZjj)u#5cYuM~`-1=lG1-}INM(-z%7Jybu??!nb?*qSJiYS7_tLSjBwS<*BW*JCc
zkDWh-kS>&;;@N|q_OocJD*xZyq8EudRhH8Ck_JBljPx0
zC?iErM6gzXx;hLe$`v#*qvO^`0cM!TX}>xo9hPYi9V;N%8M`*vHlu3_LZu>rCa-5#
z;NQf5FH-fxq7bJ1RrYl-X8N+MkspJ&)1Vpa?P_swefL0xgz4uDX|l
ztYAn4I+j!BUD4|4S}n0oMw9p$Cj1jn1_HyPSq`8yoyROxmoS6T1MerbR{ehE1TK`%
z8TNf!nZrD!sZFE`K}3~?K83lQsg2i6pC?!`g)r(qI#R$|?ALm`W@rSEco5_ZX?Zw%0(QV0ZUml`efNvcJtO5Q|D+BJj0<)^4zsMM
zb~`$e+*Z&5)abefOIt%Ml6&Bm_H}VF;HJd`)L?CN+6e7ZnM|&Nd6Kd=$~DC*f|^An
zRFg?o^-cB~xPtIome@uF)NpC!dVGq2n61y*YCKI*^ex^~05Nku$EM^Xrr$)&-C0G5
zB)0Z8&1VS1cx=r;!gpND!5vJTCR5RbUW8o#hwProSWM1(F@659_W=TRVHe*+5<
zoWKcMvKG9ZaqxmqxBlnlT#XHGB()cBtc=D8FeEBoKwRw0-}MuVRdP^jU|#xJqCTtl
z*89U{}RTKb!N2u0qU}EYLeX_KqT)nTDUVZ3ks{M`E_U&lYYtEMm_HX
z+-5)~GyZ3rPRinbVQIRX_d9lLyfvGD(4|xl7W1=*ti^AL;F>mbs)iD<((6-lPRgFn$v6
z*xOL<6thjLO^KR53b{#qz|k{I3@PwtCy!*5V8Q4n5
zk%d^^n44p{RpF&f-ev&{3ERyZ7!$-;1SJKczWl1njdIQm%&P
zg+;s4Sq#O{M#ohQjq`)|Q1PHl^b1?{yxk&#bD`*3pdj
ze6w4VfjEI+B73+>!TM4vcwTkn(u1Z*gis9Y4dEIbj?imT6~1pIsWdC@GECVe^^)7S
z$1eB`!Fr%uS*z#O?Q6(>F(n(v*IZ%6v3+SvZdZq#HJm@8qvBC}rQ8R+1hT4olXu()
zG;KBCgm|&DMh)h6DL`>SUSvUV1`e-;j!`!)3_R0CToUz>cV5h5PN
zm9P$JSU?tp9V9dPtl!s4Q$#a+J9Kkx6th8TE3k=%W<>=$7?AyWBW<^ttnKx^
zA%m!@|C0YA61BgLeX7H&vYG7YT!~%6S12oNzY?fcDNl`5u|Ie%W=n%(`gpGP*KSlu
zOa3+~{6_+=n-Zr&F)!RC2FnAq0LnAFwTSe&yxu>9BWESF%RRcVz^-33x-cTkqlQps}uxtieu%_
zdWTjPV8)?9lL7(07A!NNIH`4yz3MeXjv;@RK+lBy%f`vgm}*sE>Bq^k{&T<}*8Lu1
z>HHc!jXHRp`ucF;vDk}McyyT$KE-A1f5
zh?5g?If*m=q(1ywcU?D*N($~TMxh?G+tcGvAlMXBEu^_O)z9jiYe$q*M-=k6GLEci
z5CUFNKktll9Jy?-Ck{KjIgrznbFZ|Dm!QPCRuWaY{?ij?I@S}bxTk1~*n?NbLsNbN
zrfe43zk2yb*(BM6B#vvd_2r8y!G?vbjJ-@z3R$a&Oukz2C{;$~$t;9InXC1-t+;t{
z8_^UA>$val!kMcM|HDQ~Kz)Oe&wt?2LC;H(R9<9J>~oOETitb!IG`Rmpiok6E!Z{2
zQH^QOdeCPv?}hw=FPK0Wy*TP>{v`(g4m18LlYI5pQl(14B;tS3KwGoqv$0|r=Hwz^
z^FOhqyy#&-TU%5Zpp-80c%WGSyVEaMxl)vNk}3
zH1`qw>0o9)GCZY;e>(-muX6tkz_?`E={1Yf?jU7=d$
z;O3-X{MO<*z|o1boQNmStMaMQTaZBv#jKUhuv()g^XP~dLR&L&XUfyFR~hjxgs&fg
zr~e7te8QF)2k`M3{P2K1Z96s?)2
z2a~y)D=AH^W2<0B#H@{ce>t26f&pL}q~%N5AtHFImRT#V?nt8e6`a=>k&G2b-hUKs
z0f=t^^6BTl52p10LV5Y%pXtrPpRwF1)Ibq$nFO>lH$4l1wO=b9^!^IdLhGca!~SSR
zm!`*+_xqL9-Ig!k;@O(R-rdsSg)`dDZ{~;3{pU3v^;+#Yy>+!dZQH@w`W0#2N2>m0
zxdUa(!zKzj)dx4`9%c7XI@(2>B(v6wNiJH4b19?RQ!R9y%24PfC+WTdlkk7(K
z0m1%9VsVga-&1~f1u>LUoi;s`(pB+v0GhUzq79MDrfbgs-?o70e`KVPI~p(Y=f8an
z$U6Q(=Ksc9PorXhl7O6OJW$M>k@NXpEI_au>6w>JmD84&YYebgGwbPnmi@AVnIFWE8;OWrUTLS}5)V{C4-nI^u@
zlUBtrCvD$?8`$+xVVg8uP-(IYf%bHyu>-Qu{U>&nDyR^`uL@PrBAX;bDUh!mKq7=m
zl;PZvh|`iFd9q1t-#gxkyFKkS4OF_k8O&w!6l;XX;kS|3S0(gT`Pwc<;g?-L9_=;%
z`%!JEx~G48a;_cR$b4*5&rXJfbXUl~=RZZ{OI
zZAilI%CRxM?zZC5nDVnO4yk)Ls!J5)3%a`gSu7mw_Z@$QXJm*qS%}V5u?#q_N)o!u`_abr
zR($Cav8p1Sd{L6lrp14@a$4!XIj?~@#0icf-q70mSqn3p>1VBO4QqDZyg|0X-H&+R
znMBK{p5gvbTC%b2Y?gFO;7p{jjlU{WE`&~#GY{@VN}h$_M>OV9TdHV+fe>x)qN<}x
z%X2XcE^;|C)mI6)eiU4&iM4?+K_$-?&ZrK%N%~08vO~{?fo*2h`~m~5nV6QN2#kLz
zQ-qb`#xbmKHH3)c0PB=Xy^Q0T4ZW7&Kn5l#%+mpVwB!?9cE{60mM7aJmX&1q>3zpK
zN4zK7QlMiC`4;HWXY;2ljOuA5baBM3|7aMaF2M<2kds8o_DK?6c8Up8?F857@+*bU
z*Tw*f=JWeOi%%q=$LFgUU~j51lrL=|5-DwA$>ap6%=@bVG(8>cOpuh5_H(e988>Hc
z5s(1eR@Mq}W|m4B#j{w?>BZxo{3@0JZhJo^RY|!19tpoHhy%y!GVpHWoypz=pC?Hl
zZ_aN>0Y8^)i4}gldOvf1ubjNTB)eyb>cCwHH9oQ|z=Im7=l3my&8&|fVX7Jz3kO9t
zHhyS7YgLOD38z67v-S2d(A}yxZmY{tDaQ0adll(rT39>-uZ?87Oz@3P#769NF*B)&+*
zH_bJESG)jiUW?}fK8ueM5+pIKaRF?za{6bb)ZB1RK$X$m@gnqaPsrgkqCf#q<7R!)
z2E&?KGvgvtQ=DJ6dE&$du~<`s3t`GH8F0wkbMeF_25P)Cb3MI4N6a<;Uv~gNdf=-R
zh*?-4TJ!U}+8GA7?w@OQBveA^LP&?Tz$X`)l|vJE-vMNMdBgi>%hr|7<94b1rpLir
z|M0urYS)Dp?#1xGPO(&9%dK;{)a8lXd)C)kD~f^@JxI)r!(f3|^>{OuHn6a6^=bD+
z2gr+*@PB*Yha6JALd6vf>72L)vTlS3F3hoYP(}C+$F$Uv!(8qRg^)Nv|xdU-Jo~Mhm~T_U~>C
zxWxU$!y^W1oAt++v2d(QdJWT$;*<*h2ghwdmqI(wZqg|zDb|&1bfwZ2PZxnD-uke)
zn#b-1*HF2uu3VI*;v+@&?L<(^Bs#Os#ab(InPud>9KKy;np2
z2!}9WoTN$Q=ar5m{;vc3`F(fu(J^$e!)?dLPA$LX%Ja2
z--pNixfc7Hxx1-d->u%oLmy-G0wVkn4fl!Zqm7ZWJiWc`E){GZ1^KI5398Q$PzwKvZrTnaahrgCD;Vmz3I6T&v26E_(-@EU)7|0y
z$%WmAwD*bgQ{C`v#rJbCQqMPsOGL<`GZhzrhCst~72}@B3vhBr<8RyzhH!&c@a?df
z(bw`-H^ZfAW44G3TN{!eO@pc#-M9NxlqWZ<9F_fl=~?kVIUHq9o+fVoYV2+q8MP4J$+eg$#Es6L`OQX6(U{tf6MX7911$0yq7e}byM
zhkvi$GzZam0(}m#yQ74>UpL7isGmV;m(ax^Al!pH70#238~c=PdFCOvWKn+b6hx3C
z_h!46dJ2bb8e?1Z7V7N17z1zk2$&c^Wk{Tglq9Hb2{~esfsmDd^Dlp$eJks!-1?+F
zj9=D&`^)-`S@P}1{{v5otyS@ZyPG}0;Eg+HskFu4h$$UX_W`wvsZ?d0jO0LDdEm(+
z+j5k{+Am4G5ETD)P!4uDzP(mN&?Y{*)0bD#%;$;zpy@l|
z6&ks?dDZ*P-aCxnWMg@)JYG>B^3NA}jfmd`&q$A^{gpllqzm(zAZ3Q41BB>ZP2|*x
z5I~}NCS5MHn&zVQX^iM64Z!e!7z0ZzSardv6+Pwc^i9pOG#1jXw|0li~MiCn3Ko;LAgNDaW
zRecVLCwqH)TRipu31_0x&7iTW+!@5w{})6!`JJU|31Dk4&I(r7j9(U#i(oo=HFhpbq~S^JBB4`WGbh>PyGC|AR^GK2fE=P2378{-?v*A{|i3<
zW>LwsrsS_U42`D)6z*PKfBm3Opj7s>8+O=fsA7*Ri;j)2D}L)(-FYSFY0E
zZ|?4#*l?%^KXEzK2mM1Fi3yTl
z(g@xek%iWD7>h9wCT83i@kv(wxem|gv%|E_|4EIIg~*)rlJ9ZyKXL`SLiweZPkII5
z$p*v0L$1kmLaEN=_}Rf;6&2<)!c*nU?D{)||HTjU)sWN@KjOLE-k``(dHT$6@~54R
zre*yqFC{431N$)z8Td6aPK;gQI1be8rnb)VXi<8|W6m=)^X}5@TfVmLpQ5VBCL36R
z$0L`wtCSxV;b)Vu9A&^JIwgO7dLgy_Ei*R9T
zncsWOt%eXX#~p_wK$IAxEI&$^_=x499@w0Un
zeax|y#@~8?9@d56?hP}a!iXbL;M6}*#Ic6&xEZMEd~I!h`d5pC!}K&g(KEuWg&Zg1
zchs`JcCvO7SB}|?m08TZf(uYHG16#j^w5~ZB}3^Z&9nb!J8mKy%QHOD$mE@3tQJ(CphJ*u{&y|{G
zL($<->SeX#wQ1vQnPR-m-brKPvrzPGf`_9Hd%)7HFq1t5805A_bZbrT_p(R(z}Uqt
z+nu4Ra@An-ox}6!bD
z46g-hHr})X@dXw6e;TnMvw-C|DQ=>ZuXpi|TUJ|ILAm+%iC7GTyih&UBhhRFIODQ8($|q}b(j}j0cwa%zf|89
z#03UI(u4$`unY3OeP6D>39Qu7p?3^5p`dSUdtC5Me9c5iwEVVjSR5+!&6&RckBVRk
zlDqfj@aKT?s@EE2wjOSqB#pVo5rf2UX;#Ze2ZEov%9^v!@RSgKH6*K*U6TZfW0Bqizgi>B
z)u*-P&fr7lsTjCfH5TUzRmxRdgxhtB$W%zuf>i%|#%z5i6
z$@Q?`G}6k*#%S>Wrj9HETL1fEvt;$bZd}izU3cEFt|CscEOHp*6flE0k~z2(9Nkb-
zGh$AQ0dwn8u*@-A(9r?Cs<}nnG~ZXY#dWou8n9vKksYucm1$O*m^Wqhnb$Z@HJyGK
zObJR;<=9$0u3V^6;#AuM659|VJydDoa>lT)YS@yRG20s=i6H+LW^1-bM^44;ikNzN
zN`4yg%L_b~KhUp|z3DlJ7D-92&EV=w(X>78QqlLgQnA=`nECG4)ZPt`II?1d|K`Y)
z9upUhnR)_qBm|FWJCkYg=C*LED6%o;#bMcyb+@tl!~QGK)VtVAe}gx7h;f=|y{bl4
zC9OO8A?9^WqsPJ?AV@zO>!rQI>14cNLA!J#%Q?ku$#qw#`+$!G6XO;r!!oNe|
zDtX5!gTbn(Zwq59a+G_c&(gYY$iZ)1)cnKRiFRF7xW#ht()mTRI(TFBGhy5IaTU9u
zN5pZJIbNp4{@(JKf(W*0Olz_TpvDk@=?uq>*hG@WibN5?IWAU>mZjF-)ove
zovDp@*s1b|Vz?2W(k*c}1C1nfG)G^QR^KTsp(l!z`d1u%=?nkrG&16w70UH<$Lhyn
zX$PR;fRfbPG0+nbo{Khm*-0j;uL^+@Og|UuI1+i~C$g6sYXdV4Qp|k8r6Iol)P(OQ
zV>nnT{P~#K^UBMkc0vI>u_=S6p>pbqnq5Q}|02u5Ren|9%csWa%5^_%O?%z}C-GlN0WalD@VGlQ8*>{gFmBb6q1Xd5FFmCqrsp5vh
zwsg^|$Y{tmwr}+rXCTX0h>Z7=`gXxW0RYrV1!;B-ob6rhe(^5#n5fJ*cy~zHdWZD}
zYi~{^h3z@?)_uKK%y-wFQ|1{S*J&slU8c{`Yxth+0kDgmvp4aRRxg)VO~N?so5p|c
zSbDJp#(2yWJksP^S~I~98@U`pJOjNQIWiZgt!oxWJX9@&AP*8vgU1{SKq?T(sFiw2
z$(jb9G0@0GhS_75#Sa7>`kC=K8kJI?VrGXwV(6PcLz}!mE65(&pF39!AG{X}4ET=W
zfP_~Go*=ID;wTV=B(Kxu&oGUZSD4Y=!}hG2XBxBboP(IwMO3+2O_FW^b9m?7XR|2w
zLz8Kt&u{9E!XW-_m1{bWQN~lOupp%xb$%}+pWf`koH$@K21K*6ro;K9b9OBro9}LF
zizo=b%}HZ*SktN#^t$rT@D3#>0W2(Lk;f2$ej~yRg+}e|8^71sFHZQP5+aBil^?>;
z@@04LGC);{2YCi6*aCClgW++b4hT;>wsiStJE{cl1M-z3NY9aNf3fit96_cxTb$g)5II(UF5$3V
z3ThoEM*L9X8?I+YEgXMnbnRv>W80#nHaNFAh<<~)Ps2!gun{j*+wp`-PK?tBBuBf>
zr!^OY2agPi37>{J@It~oyr8D;+9GVL{O&AD%KHs>k6ziAD(CLm^qotFNR
zG=tT9(-=uB63pxL+Q(TVq}}G}{s)riCHY`Y0_3L4wju?b$H4EcLR*1I
zqV+Rnbc8#iUuS42Db8gsgCE>*HT}VSraZ|RITa4f;nQ=N`JEVfJP9`vUv
z(rOV!0}C%ak1bg*UG}DoKVN~ge-QUgR&_vK6j!@A9vZ@Zw
z&#~A!^&g^cx>+`|uz3)qOD#faMtC0Ufxk^qQWK=H3`I@iB$2%l1(S_Jb$ZTQ&8Owr
z1mMnIDMssh*{XSxAVY2E2F>mZLq6nlYH+DVf+gX3HR-Pgm%J2>X`;K!Uj_IydKW*k
zZfZ5hx&dNFF){>3C;?k!q8^mo+&d0X(>lDBQ`r!qt+U|QTY9NB*c8h)cKq@Z^s80*
z#w6=)6
z>lQfKsVDYML_g?CaZa_fb+>1Dgk=N07cMFZ`Cm6VP+Zwf{vF4tl}d~^j8>&F
zpd2V-=n93}qI89qXp09#EoinUiyhVj>dYbzpd1)_8Cdm(g#B!&c6F@{5h8PtPjD+B
zHXLjYhCS}*8Ye`heeR51@_U37vBC=)b5ZMWyH+fOR2l`-ZQ`OyuKg`GEbY;2wh>V6=3TXE{pH+O
z_M@AEeP}5JXpcfOax^aR89-cdc{=-l!n95Ayvs>IMc?R@EsC-niZUw|%>E5x?TQOA
zm;238J7E+56nZ`TEX0TW6m&HvNeBS%AAZZGU%d0K`%OS{8HgO;NIFsJ%Xk8{h+Ts9
zU;m)dlA%5SF)!+2l4t%wFJ}FgbrFdL_JNLS{Elh%So_I}>-CgSBqp}Vdl`omhQ~O2
zU=p>>s|k^g3>{lnNN7ZEB{gF4Ypdwq(-vl_hu6~8#oxi9&T!ZKFriP`WNWYSaQtG4WbHidRnquw|JAmGd{U3EQG9xw(
zuJIkcPHZ_iLzPhXijVKoWecO3muN^D4WhT-DrXhr`nLC?w|HmqFY;&Lj$WLe_!l`R
z@OxUS6P8MVzNjJPYN;?`yH-MT0js69Ha2OdtSwd98H2eJqSy-D3%guA=szVT969-^
zut~WW(!q-1UnI55?@C1jOlNPx9ZB3p?A@)A3Y|CaYF1U3&Jkvh?mZ#8V_JUx0NGo(
z-^&~Z54N6rY2W#-qGT&??)c6m%yx8lWe=K;)>M6%Nidr>w5BhL^>A>`emzx8?yT*1
z46FTrl~3~zYUuuM2vIdse9H>fb6{`D6Q(3Ru&ks{{pxcr2UrVu%w*r*?cR2l`V5z+
zFoPEfyqU6V3VN`fGhtukO6tVeBvWp$W#f}h<<9s%4i|9fw}vD%WarPQ0a=kKS}BVM
zgloC~NF`3b0D4g^D-wYlyzgG@8PwDS@$>AkN%5N?ny#TgMznH=ZqyO1kNLwPk
zhqxxR3Niwqz6-y=+QihnhcvRRfE!w2B^uKMJ5w372a3lSV=tm3U82nHf)9hr
z&p?7y0~sm-Nc^YRL^2O#@XIQ6CD4=}k}Ed!p0(>n<4%o0N=JX=HvKn=2Ms}@k{N01
zvWrd}nD7?GVu>=*I$sr>A%=;0dGm_r{O9Dm#MLsuz3mv2)~mbWy0Xq|u)cO(R7Mo{
z$S;yoIh0!p7n(8H#LsiED6I=BvY}KX7UMQgW{#1x7>6O+=5Fn0=vjo-h$MJID_(=T
zor;mcfDNgAn9+`y+x}Hto2%It4>Qo!@}-b~s5K!;tEQThHZIe=)lZY=kqd?
zy(cp;Rh0w750>wT9)C?1AW{6uRyOEJqs-U5xZi080Oc@Vg=VwXOuYx~(qnBKtFp%D*`LPire}RNR0TAlr
zGnh8u+I23|O}nC<5UzWEnqt_qg#VT&m10>pzGf9COp`z+GOe?W-_6d9^S|Xb_DCSv
znT5wxU_CzhG)OJbL6Cc@%_Z4Z^uTJ9{-AT&`_t!6k33FMz_juqW=@C!C9!8T*xfU~
z)G9Cp>7tQ)lmIx#WiD2dc>#gy?X+7B{WYGdhsgAazP$J4!K};tyyr8(uyH$MQ^7+R
zA{p0b2qQwNxo3apEkPB4RY(hpZvUWsMK#87qEJQ&%^HgAXk|n#4a{mv)hTAj&9NdR
zkXyS^akvOfKf#2MQ&S(kj&H-car?q(WSPNnDv0mcj^DQbN+JHxn*VZu5gi>ct8INs
zWvf-S(0a`=ak9Kl5>uP&%IEys)md0B3sdF`o>S*jle1EL7)w!7*e|F`{)!nP>&r8U
z>N(Eb%X|ja%@-*Is=HUEABS*3jf~KRS@mh{`-F10E5C2-(_Z+^>QwWoOYL}K_|kIb
z*$ft(xv5=AtG*Otd4r|pZ(C%i%MjwPw`_w|s-B@K#=vk}f7ObUC%3+_+G5QW!Ws2C
zf66M-{i*3zMz$dD!7~aMYD*@yra-&z3FTHOs&Qb
zwX>)f$_D0X_!le+lksku9Y*#7qSkY3e=?qQj+}f={T%O72t;9rS%?0Px&EJbvbywr
zM97Pyq55&OUK%Pkp?YBaO<*DpkWN$SHiE;&m}QFP42M`{ycy`$nTrMb3GDmL0a2u4
zLp;lijQ@#_PP}=EiLMiH9b&_l-x+JMvE~PN~unKR@-r2Op?)KQIBNd)1
zn~m&|U6P-sZ&a9{zM;a7^X<}3Z@kkmr4M#L*bn+fMooDS>=yNJi>q&WO4PW$xc-D)
zHPUZnq}p=}Bq-r8RS;cx84ALI;+~M9Cw2#M>oE35YGtK2CjIBrq!+K4U>+B(Z&;&NCvUC=)+WD$e+8lIKpikA^a!4Jvuo6(
zUj8J__oTzE%!`8#_YX;j>3)A4i&&FuF2#%HRE|p=t|V%Cg|(QH0H05`0xB<^=U(p{
z?T)*aQ_Mu3iA*wTo1O!O)lPIu(N(uAD;UqB+!qC4=jATO-W1O!YD=R@Tv~Ugsy>j?
zmaEOwCRMF!<%A7EA*Vo9(}-W{%SCj^^vj$AM=li$e6P0HlvEu6zr|h_f9B#HyT!j*
zBh|lUo4KOLc7U?(R$EONIo9}F8Tc_2#cW$wDzC2Im!7@0q74Q$=q4uq?o%dvq;zHN
zS89gXS{U)okIErpzxzDo~fSkts
z{D~DKfKDm}l2fSrn;zC&H7*1cmLdg^#=ALC&&Zh)6^H!d?v!mFEtdK6nH}SHAUe-J
z=c!iG_a0}K)e|LVQGpHr||q=bU(Ok>ao5`k5*b7o~+_M*k<&v^OF>0fNlR5
z=bd6)t5~xnOy5{E6a5->ov7N!?ZAitaEraEgf?*M;P%V4x9um(-%F
zQsf{FoP>%Qm(;{We>I9*n;Tz)DJo4CvD5{JR~jIGkHbqrf?8GfnBgV!Ffof~jpt4R
zwX-V%mY^eb&9POs)i`)?<|%MgkfI&JnqVS#1J8QO>c|;_EKU#4+G6`HNqGahUC(}=wfC>O_I!k;28adiu&J4TBq2AEa=K02DQD)eW@amj`RhZb
zWg-VzX}pk)=+R9va#qGQRbu{7v!Wc%E1#3}I##H%9HsT@`j}px@y%bu=WVeoPN+!^
zWp#c@3!+g$Ci_i{Z{S_!O&lMB{NHZgaQ1^0AZCw*TNj@(c|;;PjM@0`&xmmg-Zlr6
z+TS*;`d@r~Z_MpM)P#U1ouC$PYx=oownFi!nLO8%2crt(iqqbks5f>~iK=n4(|?N<
zyZa6hnnepqhr34SoMv`O9k5F7AaO;3!@eMQVK|UO#RJzO{3nzW>it2Lgsf)M76f`7
zzJ9j)X6XAb(m{B+oqT^Sj(6jv@BhjF6|=5yhtiujXR@LNx_V)P
z5+El-yJfZ&M(iHh*qpN;!C89H_g(vqsouj0Hl6L}5LV^<66_`#^!e)2qxx2F
zak8Z-Xy4nhuRD7(Oah}Mj)@+oy
z7E~eDm#6`wuW6xG7Fpr*4sFJ*nTG=zc>bwqo`c=6aBWi%9tP-t|
z<0s$S!35<+o#s7H1{Oe$tY&HQjBGfDJIp6Q%gr{(teXH0e;
zhXKet#gTiJz~TQhP3YS+HdFDHl>i8nheh-+NW+Cv@Ln=xc$n)=Du{cUgYWU4rNN!W
zdJEXSSzP2_#~Ip}MshM~7pqL3<-}S<8FQ!SElMM!+4{W57NiUtdm+^mJPJr3-HpT@d`whyv!G(TB@26AVLvCRwI2Z6
z^nTeB;*EL)WkMqF>qS?A?BgZ>%H{`P9OG45S!bTp$D1yLfO2E25`0+RD+ykV-1NpX
zm65X?f`!d+Q#%Jdo$Yp=@IuDupFUHE3Lzlh;dXZ>!~s4>smLoDLR*zv9IH?(v-XuAL5!3pdL_mPio
z($4!@xze}BORBA&Uk;GocX&I~jS?Z%5T4>wC<9~*J}DaqQPA%8Nnn>6vqX8Zb9zBL
zhCRa;vaLpiQE;{n-(pIW)6EQxe-8T^@Hg<5|JG_?+P7SDnPirMVHGPuVsI+f2mdS%
z94;X}osQ=~JRrVr>nT~us_{OBqgz?TZIxM`twbMHG%7lwC7>@0NFnDohtNa-zPK5V`~)1|mghp2zOzQ^H^si-c}X6W3g0W-s+rN|suiy=KL
zMySr$ZImt)VYG|*^O`jvxgTK@n4D@w5=BUt+t45W9*|wOolLoz^y1i+Pqv5lvkv=FJpzm|&9h;gu>0x-I^R0+R;AL~NaKe@CV
zy!gJO@6h|S7*krWRpH^&65xOPPX?u*y`j{P?baNr&C)sW~?oZD2xafJ>94)d^iOUSikpVmB*F|&X8Dg
z)%Wv1p`(`)LaP`pd+_oxAf7#^OTuh6Iu*WDjPT>wYm1`Y$hUnh56;Avg{z4xT7r!r
zS>lQ$5p5ZnDc*CsCXIUw(2P<;X0Qm5#P|@V)!}S55-pHVU#%hi;Y9jWBl<5!o|bwHW7CGbpd)Q
z{sKy)p2MS0LoEhc=dHz)cFiu6a1Xndh0-PIh7;@(C&xZUFZNzG%~IbToQqva$Thd3
zIz&V%0pDT8!K+7)CIr;|qg8b!sXgk|9M9SbiCyU*(-%~2js*(@*FPf`OR^lUQaz5%
z6`u$2)us9$r!~_$F)o9lW*JKX|9W|F_$8eA2f+1izB3%?%j+Qbw7awgo2t$9UDg!K
zjf}gaYBg-e%>$z77=~RjbbDWk+y3B{IAsy}grw-bu~z@xuQR+%_C-3+ez0!(C7G8@
zRwd$A?g*=_QmCFpapScofGMPC@F4lH9yq$S_==&2X39JRXBKwhm-;|3mfuMltMsTu
zT5{ITp|q6dn7r8IxVU=Y*ldM7ta#@5Qx@C3(N0WWr@~BtabJa=2R>3#xUx=M0vF|8
zGYX&pC9~p3k4yc|P)4xM9a>Z#nFoflyTaK^b&F{na|~z7x^=2futp!M(7L=_z=-Q2hl(VbpYZ|Twp-s$Mb5cxfsSJ>0hEn+CS
z-sSyk)g!7?P^s`t?{4qZuN>F>r{NQNEFA(1JhHc^`SqHGgz=SGGoVWWC&zF$^@R>K3`N$s)e%ago>*>)l7T!ys
zK8M$|#Sl1ta;KA<2HT~c(<72dEjyZERU%#d)zYmcH^NjE?1}Kp^3wv!BIT5}0#w^++1z|o+$7{CDzD~HmEi&^f58Enz*Xh*@ZHR6vVGAtPZx(N^P5*H
zns#|iLqnDQ9^{`}YxjQac3vN@knXA#j0})?DFcCA@8*)>p5Am51G9vppU6M1N4ICH
zzL5WTZR|TCe`p0O)#YN0fc@ixgNVC8vYuU7YCmER0=ZS{Xg^4jeXAVnc@UgY#5A5~
zXU0F2ue=u07nppYniy7JpQsj{9Zt)nV|;l|FhkodEw6AWA*`_2SzPD*C0nyZ`3nKO
z@M2>1b}~wiwczok)AQHUVz7|ivEQ#C{oJ^{nyx*;sP?o13|Ofu$&Wmnx8rjycgp3f7H0#MybL0NNPy{SW(n4>0^Et);iYT
zK0-EAUsw5~pW|sVu!a0AtJNW_r#ldNR?ttQ!_W6#B|bAeflMfsM`xDi((D9oQKL&m
zmmvp%3Ra9i0?708{iG|aII_#VTj6-4-^r?zV;5AuziPu5gaicP`^3>jmk|F#+k98d
z@#L%DPE{GNuYdSCfeY?Bf9N;gi+R4B#_L}#gs*lbDxtedbesln%+BIXtd&};ZHuCi
z@EWVtk^LWASON4}WDm5qy7%Y9YRNZRrj=B4Z)FTD(Ziw+7ab;A6vOuVvCBcq`t57J)Mk!JD4P)7d9?7EUDR0pn=b2-muB%#ZvXc=-*Te$QE@1DB`
zq%SFXBePsxnk?=U2G~_M^9H}5h(*p)R+EqBv{?Jd;?
zzYN7ME&b`<$1W`An}+hWRq(W->$Wbtm
zFG6`sZKZy9HG&iOP-R<6wg3PMv1q+T8zI$O>013bf8T*EBZIFT)J&rDCu6l~^tX1?
zTE6LAI)Eyt_{0liaabshwOG5CYU>a|d%0qP7YK0MIdT}Y6q5?cg@Dm%>gi7jC&rcv
zB)<-ked3Z(ap(V)X#5TBAcr{huB)qeW?b4<#*dapx2I@xA<=O7olYHo^`>@lI?vH8
zvXYnaz7V>s(k7DCK<&$LK=mLSdK42uYQkn4
zU;AF3VrItgPhK0;75!2Pb0JJ4EW=1!ViWn4XMucHdB}*z*BAaC)YMw{s+q<&#aa|o
z&P+0-Ux%I_b*$NBRvkb7C+NTkto98gt~BH!!DphM5GmUxEbHES-Aqv8z5KSwMETwQ
z;|Cp~qqlE@PqrqBB0TP30OaQepF{a(-|C;CI)~ZtG`@mS{8lUt?D{eq%scBkSTr*~
zR{c-5@4~_^dQMo!e0=H`ehi%j%ATX*X(@X2cbu??y+`cQwt2wo*$=bTEC#odudL=eS!L_bDsz?phOH_Pm-X_2;~una^f0Y;_0BXKGzs
zC-|>b<ERTm=R2+Q}oWkZqfvSjnC))4Jih^dxuU*}He_24NAH
zZ&1!+UnT$uW35t5{c=!=9V>T8Q-2Mc_*18U)I%cin^wYl_>d^tud`u`P`#?b*K&(i
z)e@#@ZIrQGz%p9-V|XOJ4niY@6{h>`q8a5V)9L_7k@9{5YaBRR>UQ*=hLb`i_VVqa
zRk8G<(#-l(Jw30=mL~Gqa{mZ-d06`#=Tn>|
z%Yuv3&Dn8wSnouvB?THCoKf+iw)Efp=J6{>db~`i`9CH4dr~!l7kDb57mDcB6Zz9B
zSR(c&M;wAQ4w!`r3x3rWt9sd(4hlWSAuH;9J5=Qg9^*Sma+@{x_&oA9?>FOtD8MJkSlUt?F-fyZn?RRy_L441(a)3
z(u{p*xzr`-d9r%Fycv2jPTqQ5G5bS+c2o8sDz8bCV!Ua!l{AiUOE2;^RB!?jTbgqw%&&Z@Y$8{uYn0K@26o-cM
z4vH!8AR$sm=vi^bGK=M0{arRCOBXFpo38f!5x!$`QJ)pf5>+AXG>LUcW>3Z~KFaF>
zQ-|u?`>j*n<`YG6BNNxDr-v4WG*ZJyqU6`5HO+^S#vV1fqqZ|}FL+LW&pGR(Sx&N!
zW&*Vdu0yXQ*OaCFQm8-sB)3?ntvJOSamObsS$%%Dm+fd{J4MtLD96);VT!{Cn&|s!}IYzqIj1sGGl);R(rM^
zFY!pIq+mkMloK!*##fK8ddGMq_n3~7otd*|;7)O|B*C0f&A`c4tUO-#yonvB9cP(g
z<^obg_yEIQ^<<3*pRLZ_BPEIMq#;&pK4oe)*ok6Vv_Bz$0Bs{2fsjJ1faE59%%DP2
zL=hoq7iea2`wtZs5qGP7U`g7Vos$nw7V~Uv+S%PL$zwY}H045<>7!n=bA%b1!M&~i
zWxAI7HeZZMBrqGlhX;?~NW=+i;`m@yt0LIcNTGkZjsY_T;RColNxtsG(R&}ZdsHXtYv}xe9r2ed
zqdqPHKqC8iCq=v>zYnORLgO1v{D-0}Ig^)1pj$rKFfW_2<}b+p;FQ9FSz#LZd!&o5
z_s8}xs5py960-U1o&J(`xj;{*ZC|}|LoZLS`=zjKMo~E=vEwygdCTcaR^yrx7#Lwv
zTPI&f?@X9@vuRg{5CKbgZhxmY-nK9pzDd`ci(A!9fUW34syE=%Uul-X2>qsoannR2
z!8w&T>mT_#D0C1sR-jc9s3zas8jCFcC%hv1dELm#IT;Txhn7I)R!RJVIEpxboOp+T
zpVqgMY60=8tnf_zwsxvOD=rbqvTs`de?Pq?~;qra$`D!4_>0
z6;H7+-z?0f();1hkpsA$;1zMBHz^4-Ayz_@E8q*8zXLHSIWK-DWaS$A!bDSkz%Z3h
zCu08LOG+_Vq9+J~YOj}e9zM~FH6M;mJDD8oU&LoeSMsp%kl+DDh~GXeJ2fqxCp2oD
z&z7~aGLS!84#xM&qJgt?H)x6%JM(UO;n1$)HhdI%6;DBPYI=cow_RxijQda-;Q4~4
zxt|5N?j4*~MNOQ-&;gGsfC+wdf;{d7MX4-ExsBGD{eI_QgDQC$+szA*^3UOAQk8Hq
zsD4(NOWCbOS5ysvBx#}}@?jVUI0LZNlcIj8|2aAKGcH8akU5{ST1{t$l0
zbg5CEl0%yrh(p~tP~+Ix);fg1kJ<9G7O7NFEyfEqLjiJ9V5A2NH@^lhPk&eIWXh^>
z#>GQg#Cti!a@7SIwIcz$&=8zjMyL`=v3;5-(j;$a1%a7+IW4|=3EgIU3)sw9k&>-;
z;FqIJ1xl95O@XW3eq;)~qvn!yp%83Bx>K|}$Irj9FZek2p}x)B_3_CbE=IY)zlMnH
z38?CX?yZdm!Q|eV*?K-&1wV4ACc`fJ6&ln2&Q8_ih
zAL{k}w{~>EfxZi$tVDn{_p9lpA>G2^e3Oq0lg}srESe6)rmF#a1eJlB+d%}4>wYuz
zaYjew5NWTQ`4^NQxVu9|IB}`7$egUX(?&h4F?(}wHfUZ&1M0^lX7hC|3RYwoOci78
zxo(C8C56VXs#v-yh!sAZ7gq`y%knNbg27er=8imyz#_TIfyG_cdE`1_jNYessqO&n)wrozs9yPM{j)j|hLaHaQ(B8|GC+cow?&)OV
zy%s$(pB^by^9QbN!x!;L_8D=bbO^(9kr5d-i=P;)P=@W*`
zd*!`>dx$9LJ(iHLij?QA`elsVjPD!wUsBhwnbH;;`AKCunW29|>Ej3s$Ot&HhA3wb
z$RX#Lg%W(=d!B~>Aph08{-o3AQ7x%=yezq443V;#mmEdp{*JdN7Sd6>Or$*h5T+6_
z`UAXs?SqAT-pjH$PJSnq#I&_K2Ay4wbq-!bg(~0fT(gjoEi^39g;L;EOcc^uVW(*=
zB|Fumcqn9X?!M`-NjcZ)5yte04UJw%k$Cwarw;MfUq6n(EaIA|QK@Wmbs_Wk$e#G}
zumd+$g;}1-jWqpN&=~;DBjoI$?sL@NNk&D4qsWMQ
zHeWQ9vOscn5)?0dCPXxr#49hQ5hg{93)RP0L~%MnvK{`BIe?Y;5j$p2DZ
zz~%0SP~6y~uKbxoT*>2$V)By&BlX`J_7qg16O>!WNr~}$YxGTfm#MK6a;a1apS0wDMlu#aR)meNTI&09(pg!8k$(aL0d*`+Rw^MUY-}ke#bsx7E8m;{I&Pf`pHsHAq$gf!n<}
zrW9b5f?Qk8EWv6Z;F{I7-{yLobp|w<$0w|k_sBSXyfcui4wt^1@4{u5R*vipcPmh%
z992T}NWOEzRLA_g#}?tJQl!55*m%eNjs~AovmCuWdiq1Y#f#42kJ%-~2kK)Pz!rnZ
zd(5p`oNOa3J7m?N0A4?~)otuWUdyN?L3)S7u6UC0yhSEbzq!fakBBLw41p=W*QiYB
z0(u7GpuAY{7Ti8nT@jlWUrj9YC~Gl>4LxrbWi=YcGx`Ce!_vkO{f3^9f|KeiY5r5))IibPo2dHsIw|{0#fw^}A6ChJ`66O-mwyrtSgM=a_TFDh!G1mA80vkNtG9l>9!ai{W
zF_sP4;n*7bvX92WiT0RaQCOf4?QPHVS^(w!`=d;fZy(P!fQIEHzDhe;(kqO|ZUdsd
z(`utw9o3`Vv1Z`LicL|=dF&rcl^H7Qu-|%Q|K8ABVNxQd{0p3vqqMikg4!4hTC3R%&}Ozm%+(oU
z?e59QJREs0BRoHOfvk>e-|9u{IO`crpaZ=P0<%tqnjtIpdFGOJb(~~spKjYQ^
zj2Uo+SdcaU!AdxINFb;|Z64UCfgBldW#lE22uFKH9E#NiY{LqrFj=qlhik=_wFN5N
z-bSxt+&-wqpXGY6T`-E}{iBWl0yj@;oq5Yd%KvwQ|BP{QYLYv$dH>HVaiDl1nZwVJ
zzTWCe775DBR()!@#?QuY&rusF2ww;FCZ^IijDBZ*1iB5z=G-5Tp0t_LR|g!@|uzki3-B#{h53^j!91
z2m$z}drz=oh#BgZQTbZqp7Hw&#rn(G3w{QS4ONTZV|m%E)$SAc`JJ_9$A04tJI;`Q
z-q?eBxL4d0-UfcJbZuz5%vEg0k*USSN0^{ysp1y%FOMZn;ixe~P)$R4{#ZV&|5qVc
zB5!D9V>(gQBc{s1(wYQMPuaYOSP%9QwA4LjIsHDsOgnj>Q6Y|zkrRLDi~Wr8;|<%$
z>AMK?}aq>r~d!d|I=O!WB6V!2P^V|p`b~yvPt0Dw+EFZ1%aj)>Ypmg|gVSf#h
z_Tjhgc9b89p`_EoD{8z3U@E!vsf2eca|4pMPlfG$U4i|m72mmea$@4jqU=6ij6UE4
z<&wKa^Lb-s0M(1#8X>!>FGlP#5aDN*R8%Af`!;nzO4{9aF=Y35
zrb3t7K&X~2!-+UZ?;ZY~-O{e|EoUP2qQLkyajOPbGpgd>^QO%%P22;|#fpfJS36(U
zpkqy{)p0$QfYtC-0tULJ)x3ePf#m@^1h)=7oNCh*w~%gt6Uy41A@g4z3gx8w7HyhA
zAAaOM>n3n%qnDz1{R*-LE)plH$v}zlB(0C)GS!nPgWsUyz|hMXe-quYI7oh_9{5`
ziS8p7uqo@&coEuWh_Dn9nqLURR>hKwLL?7o7_!x)Bmj;n;S~fVJ&<{@#Yz7HeSM_q
zmnt6l=gR|K^JjK;ejVE0&B3Plm7ALbD+GIUKOH|X@k1l90&asiKMm^UhmMC6CUhRi
zmRJh=vc6d7=tf5g7tyP0E!Bf5a8=>+ATQsDKMKmXg2@TGVeAXbuDjD?R$q#yyXe<_
z+f!cp#n$<$pQCgW
zy7k1Xex9!#K0wmI{Gea5kyw1%Mauc8Ik;a4p>FjqXzbpfz@u5N-g$-VA-DY9`u6sE
z@7)u;h-uGjKJ43zDQi$u8+6~-w>W8$*~kBKAY~7zai8h>VQnXlPz6h-&2Q4PQ~c0e
z!EPgC7g7_!x!ItdOpI~_313|=i3R`kG50JU97-p`*a}4`vL_?r
zKS*;@P-nIU@9j3JZUB)!n=OkeA@;b6$klN#wJ>Xd9FUfJU`*r)Buz^i~R5Ik*1W;{9!dYKKhyx6VKt^
zn!P4))kJnW(a_Yx+lH*Ex6lvBogIfW&oO
zV@&(=Ur+j;??-oJDP>i-0R;WIbXP0x&*%G@)pkorN@%ZWvEfLiqZZk{Iiz@p1DdBg
z`fSZAft{_=e*pzU6I^5#?v#=U?T4jRhSn0|>4{|q=N!2;=BHnS%mezE_y|7;o0s*=
zW0{%6{+c3>3HVRvcAb8~B4>aeu}HdDqAQepyDovzzQE;f=28Pz6(W|bjZ);Pwwk(R
zNUd3oW%VdkBMKHsH|{@mDY2GE7R(>l%n{(oq&xn0T*qirt_emqiy>}dS9nJ~j1-Ju
zPpp5ZTboov&C1KH2#oG?1lNXl-2NsfC9j|={O8UvtAS%!y3wD5q+wNXZ^;XwEv&A;
z*|&gm_ADM$!Vo7%0?ef199%?271e-wURMG-q%pQBC{twb*3D>Q_cnDl
z?s;`_!;Xrcz|Tcnd9BnTpLfggs`j4psmf?2tW#~ukXqSBwz=b(7M*%3irnT!&bdf&
zTdXs7wiUV6y1I(oXlL+Hi{lj6y~+ju#Oho=YD@*NBf`0$IwN&6cEg!$2rqa{d<+w}
z?3r1W;$c~rH~ai@5MQqTchOE>a+k$vg>jzau~^IcH7kDk
zV{rL5!)n;(>=4(rLR*-wPEy)G9ll}*AR-6k)Bv|aDo`2W0$46))b|T$rv7WR&Y*#J
zb7eF`*@%0dXq08AOJ4q~k+}MCk5+qu&GtR6)AYMY3B~;c@0fv)TY-%4yFBOiwgJ$v
z9PUzG6T9weDnudS26}NsZuv2}D|&ic)Dtj;x!ZeF@XO99y$soHm2DFumoKR1$8NRu
z>@UXpY|>ubyh8{M%MClBSWtuOp~tcJl4*4Rj>p6Oldk=X1shiSX?{VPR(B53L~#Mn
zuZ8YgUI2A?sS$RJs77Hf)ypOFV##8$s{wK1R6>BV3nycovK|B+T8<_To@t#!E20p)4#*VrQ~>H)|(H#cZo~1_7@yM7{u0=SXe6yQqjHx2s_Y`t9|e|umxGE&Fk1cy
z#+wVoF{qJS?(xZC*j0BM1QLrKM|C$?23-xmk7t@w+vpE!vnI8PADqToi(Kq@7|YxH
zVd~FB!C|~(EMLKC^ckBbpGbi@rY~nwo=jkrRm{|2MU0BHET21Mdd^5U5nNUHt%V6x
zW4v{A;G_@*E-RV$YX~%r6Vf2x(lheUDgrJ0$fkH>8gPTXkdMCGeiLocq^Hibym92KCPk6wWn5%
zA+Y_gKi{mP!iZ#8VA|MNIR4Hiv_c+zqA>1SB%Vy-kQKIp)8vjsb4D2UHFFbValn&#
zcF4)Odzy?gcMfC@2OY5Ij=)<+7;3BeH@^Pt@>NR5dr5@WG&iFoWjs0kIb+ymN>M=N
znc7d9I6O|G;fxyr@3dgsv#4V1G+zrV`5a(duYKv&jj-()aqlJEg~0bAg@co`=-~a<
z=y503BiGX2^IDmRJ<3hLQ{G1RX<(-^5!*Gc>OK}RBZpZhys}sP3Tc4C`30$;OY@r{
z;k!IMTH=LnV#@n@#pAdZcs8$+^=f%qrH$jhVaLBKL_RXu*sOfc4a~OWy+Lg4sLUl~
zMF*5a(03|@x?sb8$2a=I>fG+k8K&&j$#uBR2H>l6`^K<$
zF-(kEQAw6Z$X7PlnRL|Z9vXhj0zE$wjt2a>J1=^(yWOS#rMux%6j$M@>8;LxeYIP|XwqX{rdNAbLf#F)JRXTwHly
z3QQE+v=V%;yROZoHbcMPVs2^NHxo~T>2Swd$pmRaV?rC+pEm2Q9!?!mSCRc^4>ooTv%TY47K<-rxd)E&ckAA2+ULr-Jb=y{OC1V
z@W{pxeOy!j?yWhX9SZZmGT>DDPsKefyA{AHZf7E&JlNdWVEATsv$Eywa`Z=mRI>f%
z7BR}f0GYL+F$IViNe3{zjVb{T+Lm0fVkG)yYA@q5+b_@aqjr<>`L=c_HtQr#m^BLY
zaW=M!)Iw>_!UfV`s_^`%*1^q62UCkPiEC+%Z|5bU#yk7TR(_QBO`WP0D&*K9S%nbjYn&
zFQOvvYLKzPwOI)hKAMtQ@$&=1BU6fHrg{mK-9Lpy$To?kixR>cQY{vLBIXgs1FkxI
zw*k&N#n%0<0~R$H_SfGnfji7}m$e6Jv200UR&$9ccdT@l3wS|n_=d`r{&n*?58`^!&r7kVQP-ugPU
zksBkOFJSfk&S=n`U&VP_Umi6i&ipzv_O-#zzI{Rt`|L7cuyraHO!_SQ;yuJu1hW}y
zH)^=vD{(Z8M3cPQEVJ++n;Txky}f=F+_BMdG|z00k7~A)QF%ftn5L`@${@YF-pbK?
znKSomvnEWBtUYdhKyBOC&_QZlai2_P1N0x*A1CsyohDV=tD%nqNVx{gY=vmE|N5yT
zd~0O;g|vJ#Q;`;jCE2i2_GxqFL~DFZ(yHkx?4LI4eyHCcUEf#n4@qtQLH0yj&%D|Q
z;lH9!fi;y2>ak1|?hhq_w`dGdp78%BpPt%TX~?Ms!w2?#cs#S`EDqtHK$8Nj{>dewDejXeqRDD^$*74W7zlr<
zCZaV6;z+8o6iQQ(JL*9wV%dXrlCWvcJ?XnoM5>vnPeh8<#pP9>K)7a9hbvKi280Uz
z$+KHsBnPa=p3`W~NnP-1&OMOHjt6`h1v(l2@IZh|1UbNUA}U
z6*^fT%&SL&wGPztg7ydQME0S}Z_
znYFo2%BZnW1AE2p>-EPOiiWQfpy{8`PppNQ7u*&?GhJP)>E(6;{Uf%7*J?U{g7Q?VjA=4$yukrELIAZ
zPn!D+Qq(Q4di>BWyLz0|J*WEQ@!BjAP4nF_gfj!T+cV+B4I9{sr?DL9H@iQn0ct*-Z6?aYCZcud4!;!vf#?-tm0DojOE?um5Z+h8
z7K0O!+Y-R44V^E~h~cwjZSG-nBYuhosd}bs<1jI2awr)P7S@V~yyy!htcG*F9IVvI
z{2D9N+`k}QRe)=tUD}l{H?S;*DTMNEBt}Kcsvg(WA_o{Lg352xO7lJ)YBuhF)r&S3
z&O=D+tjQsL*1o7co_a1pfLDXn3R|_4kDBWd+_ey3=*2x>Rbg
z5RMQMo0&wUgdSUPMA$JU(5FB2sDv7gN{}Sw8jFV4;bRj`L_Zh7_1$!?0#?Xp?PIIk
z|ANb-KLiq1C03ubNiT;UGBe>_nMPQpxcNUKzM{E-J+9UnOhmrhCZeT~Yal{LAIl}8
zDOOKOOSK(edc!Omp?RiSOvX^Crj3!mBhd&`C>C=SS|0J&qgN5O4|`pOqay)+4(kz=
zb-~Z>Z<>hOYaHiEF1b3f0zK>0nPrf5F*Xgw;7O8%W*C9|8C(j4L5!y>VUwmC+UhJ~
zJE#rB8Rv?IT)(=((MiH4aG-5)6b|%_eqy$XdjO0OBy4I6&~(W(**+7E3>FpV&}NUc
z0Lh_g0WK(y?L?k7KGG7L0@NbD&DJ-24YdC5(
zqlYB47{U}x>IC&R`w~Qv$76<3a)2j7l&qRaYwJX$hSUlC^1tV&2Y9!t?CKX9DosUZ
z_sr^W6!wH_i*>8Qg(Xh2v$%%1-FmU!>Tu$KFMTr2pE%74Kvv2m9(5)3)B4eQ1^lw+
z&lTOqLbNs2#=^Pt0}23_pe{L}P({j50*683GE~;KvGB5eIuWgA_zK8U`tv3-n?}?<
zTs2~3fX>#zx15D2(|{Iw0F!2f;(b+WYDn(?kXOU+?(R}Z8w0x2Lfj>Q9<9-swE{teIx`VZ%#N~pQ$hoqt1lF(`u
z{1ZF?dQ01xQ*%zD^dDRnw>n69pIB#l^$A)XQ+f1R;**Mo%;03?IC5UK1;i{!)Y=wd
z6qYkeP+oO7{Ov?!Xl^GtkaL%5h&1Q!hJn2OHUeB^XgiSR+rahb8~W5+row@4fS;R)
zEJa(Sb)1Nli_R2LlK!By8U2}7eX>+#+DM#=z6#Z~)H}AZTfi;i$5u}?{c^G@#ZOk3
zoB!3_o|#oP_SNuw9ptArD4I+h>aUMDOfNsiN$2lqw;4k`V^HbSh;7vUnm6x9meF5w`*H_k5YON
z$ZwuJU0>>L{W@J!Fk{<~PFY^QlQaa9p|((k5NHSk4K)A`sH;lP^T+Ew7leqtBw1Yj
zMLp714_P)x)Yp?kWR&7d)gK|)`pOENx6(3=lOo_FL3^uksJ;OXSl^)D68ni*#wNK!
zbD~!X)63B}616=l_yQS*i9IYi*S2AdI9@dQI&S)0oo92fjx(bG+*0A!v(djGOXtx%
ztc#%1FfSH%#80c@#{MWX_z((06~)E^Fu&G#^C6P5EHj<;`^*xVWu0~tWo?dxIucyrn=Lso>OkI%9@Y+fEt(jTTAvYh(kDbLY=->;zF?1
znYRE;vaP%E>%e;)807%V0zd#puMQtn%DKbr$7E!&CLMo!~Y~uNvrq%
zL*y%8e8P%oRDUwuO1o32qp_wQw5OxRl;tra^L6NbpaGcD04C8KH(
zDFy^Fa4AB0%VNpPL>{N2R}BFewXW7WePcx;`E9!Y=p9!6a1)z9iWDjhj6147iUwpF
zZZ0M}oSvAQRPoB2EQr)gjrPx-Pvn8F}X>D(xJzi9}b>mo;N3#QlAm)xhir*|Oo
zgLgiL34ilG5P&Oyr6yOlnceT5_q5Dg5qsew_@n5J3FOzD%-$*mlPcCF&lZr=i%R@_
zl==xmM(rcfBFm>iV=dQM$d?~X&rQd_XpMTpF0Q8IR!#xuDHyK`ntZc?mWFdS5ec4r
zBibT`Ffu6Q8z10m~1uX^wo(YBL|I;)4O1payys%Rxi
zrrH)BGkU$a-0P*<0J1OpOuwF2Lc-$dyuninQB;ULz9+Gy!$skiJ
z)K{YcA=GK}R>F)#jBw_~L;|sfY}zc!&tVp!^_e{RB@2-nH7o;^LwMPAM4E
z_#@eqXD)NnCMIqtzl$?a?ol#b<~)(Ftmeiyq<(*pO9M2yycugFailUUZ7_n?40l2i
zeTM^Bi^fve*TfNk(N+6R`}d)K0q8utIN(}EDUnF$VA#xv5P;2M41ti)i%P*r_F(v$
z4Xw{MueoN9ym<~CPf$nMLyouM7Kwu|0i8A$WSIWjKK7y8B^XKCpt0((?aP=J%-|!L#ON4Rk$l~Z4N1AT
z4twq{bj&%Q*smo3Lk^(GQen4yp=b|rqKIsGM+YVopvfR*g^g(rRHJ(*h&FQ23SfOu
zAY|}W4a=%K1bzQ0s3Cwz5mr4Gg8QSW2|z0hqCkLvt^@cm6u_b+L6QYRJ%FqFZ{pA|MP$Dc|DSr=z>oi#
z7navWMWQscP6eSf{JjrKCi4k=!4<~Mhxkv%aJstVv~D&GCZ!Q-AprB=qyfZ^0xC59
z*AUB1Q9YJ8Zho+OT`G_gv6luYj6bqn
zpnrfWfLSjf3BXjs9a3i%Io}y*u-kz@N-2I1
z5Xq)3jXxE7l~D78Es+c##_7zl?gU)8X?q24s?tfq_Duy~KF~pu`{RIKuuMt^9(RfG
zNBO4>3|Ygr%IL?0KkF&&q<+KHJRyRQf;>Jf`4Fu<_zGaBMWAHSM#7dpjc%hr*pxo}
zXBkrc;?AfIV|>`)$s8WY0x%^gsd^Q3JM%)hCzO9mI?o@jnfiNrK~kuWYQ9E
zLp^YR4;$W~NloB^T18Hc
zt`OMN|7Y|u7uzLRG=%4O7tP~plDR+14_gqjWOAv9zZ2x!FC5bWeZ9IfX>Cn7!P89Q
z1q2`p?o3^uHLK`&p1I38K#4$`mWz1M>Vpx0sSXTUkoez3!UD+Uz#Ir9`39H+k=6lo
zAP}kk|K>n^-aTz7_@GXLXv1c8cnJk!Y&7s@}QObRngt^ziYz@JyUjo
zOB$$FHjt%VoxUN?0E2{)utQQW*Q&V+2E(s99qEoFwtp+X*8*G5)+?teGyL;I83D~0c|lO>5k&9l
zJ_oOGxB5o$t?)3w2as8+NmW3(9l(Zq7h+x;qdA95$|kc#0syKYp4o!+%>kIV@OnxJo4(f>KLU|L*Iy=wvuq1z3&)JB0FGV-~s)
zlpTcydz4xswwz7SDOgZ(9p#V$h}}|G_wjsip5kLtvdwepOH+U*t|a_80Ib9MLr~HS
zLdbUoAwozsltX2}c;<-Gjq{qeAW-Ymy?~a&9~gIsWcZGgVYl2};A$*^U7B7=uqGPyzWo&IBHqdmyFAT0svc
z;;yyGN{l|k|6LGV+{@Ao>)|093I
z@je*<_j^`diMfrY04PRyF4*D?u#%qtUnwLDQ0Ml;fa1I(H(nS-dawd$xg-MvqNE>F
z(QeBP;2j-^8WOjFiW7*Qhn9NTNDLkZUcR=wEq~+<#cuVCvMNSxfl`@2Gt~MUwZODh4Q_XI<1*
zJo2;bb&s*1z*GF0-$sYfSr<}t{iDSik17NbGP(AdX$1S*3Cse-{HZ3OLVWlJ&|f{h
zlrWQ*V$XmXtT^j9h;30EFf-<(t$a`)e1KHLDA!yEajF@7Gsz}oHU=T$^w|8d>|Pse&S=At3$@=b)BlnE)|N1l1EO6laXfweI(KgCG|exfsd8?W9x_BM)J9W*_?g^
zYRYBn{QOO2_hO|-PEnEwOPS!`sCLKm1Lm4HrswY1E1_yEq1LuX!Ev3s92kUjZ0i;4
zHNfrl@cs#w-`d%CFJzDzZ;KX^M*_<)CX=K(e};Nu2Ku7^5NWkV^r-_Dn`D*_4Z7GI
zfSab_7B<|NMDm>pTvjTAMH8Dr^5Of-;32d#BOgzDquzIcZdDn0FzTRgZ`ZD3r=SWA
zZv*+Qt5iHLPfx$5I*mAP*zOA{MN|hFC!eh6+VnD=2Qp5e5fss5Dd7X(U-=&zXLu_<1%+0+7SAkKmsb$Cosp}J;Ep7*%
z*!aX_@jB_34m#r{ktt>9sndC5E=a`u2YXF`q~#BL?e8?x3G+Tt$OD9+D{hihAXqBE
z!Ktk(rSkQc{;Q|sD_$Ezq8^;dku(s0bXOuE<1!M2f~QbICt?brh>wjy#Ws~KOR%HB6B=0enLyfvX!
zX$y1ON{I3+6(|`!vRvzGC_Zn{cu)YopM%0!(f?QgGfl4=I}czipCu5X7L~`om}p=2
zSAM?)F%KYX=ADEhY?2Bv(7iqrasC%U0!hg`v5n)uhw*K?2t*|0yFHVdKLYh~d`6#L
z0gOcfj)CO!Xz=@W#N`-$dBxTjurC=Oje5Bd7H5c_Y8dbK2$C}DNE<*M75oI#K;gm7
zpaeF^{dCYdM>JBjk0|Du@w&`|q;vvG1X3z227;2+J|D;kTab=+_Vo5KZ_`Nl!IQG+BGK$J!Y9BBaMjd@TELG42ddK+wLgiKIU(;)-im|`q!xKq&jl;QN|*@{lBA5sJ_a8VDi=E4D!GGr#g{xMRJb=oL~+J`j#46Dv3RK+iN2Q&~Dp0loY;G
zvD83ylzUE<6D8vSX(f`Jevk}Lcb*7vV_bQG022q)-23szwb4F!Dd~qMAU7IF(h->+
zk{eTGd4tox*kxWd?~z@k9c})dT`+m|r3pDPEo65tt~uCJMQ=O^6l^`6zkfDgp{
zL#^;e#HJbpwF15OzfdbP{0cy=m_SOs)E@;!iQyTBM1KKrt`tB5q~?Mc;o=;x?N^N(
z%B6!92FhV-nF@-Zz?jm*VTS_6=D#q*KU}Jn2&mPoABMyHCj9q1};#y29
z#-wz{B9Xf7Or}or-*|y=76+bsIn+F!FeD)0_K#-%OMzg8r$A*QCgeX^ZNvh;V>56d
z%6n<~$VL+sl@`{PC|jt$`tXOMA$@Rky3xb|$Yz@*;V3dT=%wdTf{BA^i1A#57kkxL
zUCgs-2!i43qdWEc4J|NccGny@I@z!EAu079S}-qw_yjGOC03
z?AKvhK<|DQIaC(jLbSH-t_f$x5M)mueXn
z%=CUhZQ{vPX?#FgWX$L(L!)Lkho;t-+C|F{$ra+}(bcsQx$nd0dQHOcjAR}j&bu(m
zso7k#4={l=c~9M+(gSXc0p7+Og0ev294zL)*g>r|mme|KO#8=XPR*p$A0AbwQ$d9R
zXsJ&`#nxF0W=u&sYTW`2Cf1YwY4>+#kbu_gI0cFb7n%9L6BD
zq=Rqxvmbv~A1Pp}=*GzbY&Si5Fnmb?kBU*;OaZ7blqJA8I&K1FM}uTHHnT8;z?KMbU5I+0R4
zMSjz-Az(|w04YwUsR>|@@=ukqOp}_zA`ongnc;7IfGrP2X$`2WX2J+Pk4sd-N;?}6
z2zD?*5Eqoy!ddanw_lL=dPkY~9<42q@|{%R;zf{5)*f&Ww`jfV*T!zHCv(odZVE{f
z1C96V6QpC2Cua_|>80gN`9pL|P0hNy-OFd-M!Kox2TOvC5Q@|bUagwnLQ`h;wQvgf
z)9+3%1|@0PO`ij(W_@?&2t}=bQx3{!x+-8*XHWIP$G!J$0z)p0%SwKQ_#ahEB4-g^
z>OXZ$Z`GsmRcrwQ@L$a?y7e1XM$to_>of3|MC2LsTGb%3)P@(nhw!vGWF5As0BfW)nC7Q}tEK>I2>y0U41K*Zo=rv@Pf&uuF;GvYKE6`klYDmLp3(iTn
zRG1EXjw;_(tO}eQdWH%Vr(%!D`c8nrKcVD>Xbc(v_r>i;)UZGKi#lNK2&-;ir~Gho
z;Q3Hq_dT|;X*IRfr1#3L(dD%&&kn(!-w3w9zJiv;pOaWX)=m11Zk2Mj{
zQrXVlm=z@|>`*&Bji9ir>B}MudSDhZ0pHN*y*S!a==fu7z4-rKZjl5ku}Gh^=LryF
z9V@GVVfg`TQnSZRQdv-eXK@Rd@=$;8gsj4YT9sD+Q{7G*3&UEl>_@Gl4_LsS8<)g3
zX*@(CTCSCYfPqn82
z*5E_^hbP9dSu*{t_x9Y}Gr*7@MZr(G$M{qJ#0xz6uGrKUN{X96$yqi(9YS01!WKZx
z`=kRYb?9~m?9pMF3Fq2Rb7z6mZ9dW3Z{S{&HDy@um#w3@#g*W`eSHvE-}qA|vUOlzp|UFpzl$NvY;x2uX=A-G34XPT_zN7A#5`&UM@u
z6Nk&De)Fe7@wb{9e`~W2lP*P8Io0jsABL0xGv-d80b^nYeB-}6W2@|s9g;>DP}Zrz
zCg7y)y)()eaVz~phn$9e4>Z36-t+BbzDeK)w3JKQgDcj46)brCQla1~IykGj;~_POuv>v`<}@
zaGx|r4B#WOf49a$49*|Oi9nZBzAKS9k#uJO>TaVyWC-=lNRSDkiWZc{%|=!d2Tz`Q
zfMw8Dpi-Errq*9xfmP7w2@9&F`u`?axJ1_}flct>i{ak=n_591Vmba7wPFU^1629V
zh;?8yS=X4_Ye9*VfOlno%9Vc0CL+r6hh1dh0(_f_AYYxPWb1-;E(DZ;>1U
z`2-(8$wP^r!vg~mW8j_*&`yz}n8+~KpW-C)4dG%*05BT=y-AP2J)@$yh{8bp?qZw89+h{d=%?uAV5eW6AqhQ_M^@dXo@n_6&)n
zh1F4N@r;q?1E3-PWD}U~Hwz@;`DqYR)AzdoM??0IK-cID$fnc`M$nO=%`Mn?Bh*aJ
z{U4mL|DSQnmvgkveZs0FW-4Z2aXgx1TZI-tz*vp|=AoAZ{8Fe39t?w^;{@Dz4k?Lm
zG-c<)z#I>uqfqN>2+m{Tb?o;PNK(}HM0ObyfmNr|`ru)i{jm|*EvU@=8w6#9287gB
z7CQ{+63jhobuq^xEJa(SubDK-=Ow7Z8fgwm=_6E`S8C(wIRg
z$leFV-WW-!FWGh6yM8|iNdTUdpm}tdjZE#c2w3$}0pKC%p${^$=wSwXV}4`;;9H@o
zER`Ox_B_6p&Q|hX0uv}7hCfZNsJ|K}QJ{<7;`ATQu7AjpzsxRSb>M#gX?8`GC)*<>
zJfZHSa0dAYwu(Ves@>@0O%sEh<;Wfy;j#dA5$KYTr~aRINzO0vLC3sx5@>^5Sg^t7
z3C)W@9DTgP*$~=)A%ZSoNr}z?X#Q9lc#hVy%K7M2UHOB$z1RlexnVG<2Q?l@KvTy4
z=T^TSc7UX2AiV%$87dq1DxK*E&ZsB_z++hkkd&O#50wDz+Q8hq!oGA~&?^FkZzgMJ
z%zF-CEhtX|?f%cU_=qgR*<%N!{cL+C)4yP8bGPL52{=pT8$-*_SIruC>d5Ve!vFB5
zIy>_=#9xGnLH(^4@amHcBg_T96gW
z>oT|oF0T<&?k}S=$tg_y&oKXNl20*i!3wItg64c;N%%*nUP!6SEREcc2KwafU9uS@
zH#o@hD+MSS{y$)b#sZFhB0e+#@#(+z#z70j%cquhQCrVf-pBV{DL}>N
zlI(Xe`tN?oj}ZJ=(T010!Xq4|0_l4AuX}}U@Z=59#->7lQzH}3KZq$s4bVEE#qq^z
zj{rZj^l5YE%Ls2m$}d{@nREpBXZQOIc-udDl+G&q2}6+Afs}X^e=WwoVPuO)b{B^L
zuePIMZEJ_}YeRN}v|JTpRo4m{239CZ
zfldqe{7Bc%z8_n`pUQ>e!6y5wZStsG98V~~KUlZazzhLB_Cmx=C3#c4cRa22%>|el
zJ>cMjTOWF+KS{tOhRBmhWMNq*bp7A5#H$*&!XIStT?zUAsgG9HhjCg^cEn>qQfe(m
zN3jmk(Kr1ld^d5Bh13D{MJFv`+&AQ10#*Y3gP~R7GYZ7ZU%hpuPT+XU>48P
zC=~s&_3v#G{5+sE{%f102eEwMUjzrJy4~63;e|S$eqEM8cyzUxY~wW2{s-;RfxTLq
z)>O^<&sO_``fx(HB$lD$+PAjx(FKk6jprx}pml%#`Tp;_n^mpPDm`#lg}Z&%k>1&
zMG~vRT+qo7mnAd0pj-fje2ML_f#e0o)~e(Z2Z3CdJJu1!aJ?2UVz;$24Hs@qsM2Iv
z4`t(XNf%7DS{Gi#oX9V+0>}S&V#S^Ab9HHjRQs8b|W=bBR(72uF?ss|1^qyQX(HBFojIArzb7*TayZ>%0p
zrR0WL?LcqrAw@po#P}8X&vVvajtwtJVdZ?y@>E?gTXgukVj=7m&$O*poH$9wA2%19
zWFdP9oa*czQY8Hl;YBRReJg=V*Twj@7DxGC{44(>3boLxBZ`Ne#l3EpCE}F0q;kF!
z9Jq46l|3txE`PK->;%jpVi1S)v0ZaY{V+DZM1kwUBx}%$DI^Um5}NrIAf-Quh;$$#
zf~o!{B3v-P%`Hg+@9O7@%#tMVu6(H;yepT7t_GG+^@(6B@UG+@c39a_L(=A~O1g|J
z!lXZJtHO7EUr~4!*FE4plrvlUM^xOsP2U2zt$YRLPXrTb#-5dOD0z-!Gx6fJSprQn_Xqf4d
zJo2tF;?={sC!Bb4z^b}^RmciH89O!)Gq)!3njBN^kN$aA>|_6Yrm8C9zwH_Z(*t%5
z=cH08JP^l{q|1+YV@!`4;qRMSkOpa|;p!dtx8AR3%xdlisYXzAkufYDTv;wr!nP`zfIA#-T{A
z%Sa>fl*=mM0#?5_z_B7`N{ZMF?Oi2#
zf28s;P+oDW>EaWbHZKqm`0c>*qOUl0sMQwC;u9si#;M6XFAa;DWG1iAx_1Nu0h1R)
zb4J<@K2$!X`)KJf^v`4NEP7%O-DC(bnAiKiIcI)oL!4pQ_BGjq4v04+GYk7&^T)m))OR
zvSuH8>n?w7$a?6lpAyNf+!{eJj&H5>G@*B=EpIWsUbtfzi*Xd%?y!jPvBcnIi
z-X!6b_qFDDWdBZTnXQd6PA4UAE#+u;bu6(^8-Z}5`6lpF%o0E9Dxb@9w}-1opQKzR
z8bB%LG+Eg4aon%F$NUs<#HlJBbJF=Nr|aX~1l2#(Tcv_()YCyNi33hU`_Ug9A43kK
zQJtMjq;*@Ri|mQtbtx}=?9{6DQ%yk5RQpwGK8v98g?+=BgUJUaG{L2&9@)I_h{(@-
zDdSo=HbPjEf2`<8o2#s85VpolzD50^fk~w>(x~y4
z&1whneGA8^x5P6^`__Pal+WOzS|kMZ1cJkn{%jOWb+77ZY(P`e!sjSav)PUnAyJCR=C#b
zV7)k%h-yw14@x7dMNiq5b|dC}gEY^|pb~N1Ddp<2#JNj6b#)8p4fDf661n*Y*jK4Qr>b$3ZEH*S&rE-hTNanJwX5aDZ!u5Jo3OJ#zBn1W0@tw@3LPgz`^75R$Yt`H
zRsYKrU9FW4&aRv>3VV#|$*dVSKmX^{{O<8jb;m=;jSF&PIi+Leb}K9!#qpoqDGeC%
zUpXAzn6aTsX%{;Owkxp*Mwjy;JJRig>Bi|y!8o%nV|6UHTLX$plA)nCXWg+X!2ycy4TFz{uQ}rTi2}+`VH4Qp
zl$}>V#2+TAX57jU`zh4Pe~Q
z2nTCrBG*K0-QH6jH_+}JG1`XmFe>G7z*1P-zOr!BMY$Fs;ZwkL9sVh~#xh0|Jv3aQ
z#F*+3tX21GwwJd_5O20c<7RYqWcO&>w5zUc&d&+Yv53>;n_?_;xaey|7x=NG&I0e(
zmpT$ojKM|*xLlFxCtqzoJEL|5$%gw>)h-4>1B@KFpu@7BWS>-Unax9S_BTt`I
zDzC^Fn0#rcR+gk^i-|kORF4xPkp3E6Xl>lF)-XD)8~e&X&6tbZsD9qHkR~dHI4DYG
zNOL?=-Q=u{i(jn^$qI))+Ohwg=on*0>=t^=tf&LRzz;lWg*3HiEPOi=N6Fd35(dtr
zFPr<{eY<46Tv5*}J4|mU?>-ZM>3s`K`jrC~T&^N;_E6dY&0U%Z80=Hw!(D=v6(bjI4b
zgL6FR`uBDr+F)fPk|~0hcWt#EMUBfM}j2jE@qOLn7%IT8OQ=o3n*Jl!i-e
zFf-^E!j+}RawLx6M`lfEf|;^JiS-nfFSt+)H~foHT^#tYnfp(Os)Jd~@TD!;%q2rn
z3su-Cx&0f?E)#cXQk6B*Yqrq8=n!9F9t05I0n_3np#O)*%RI&cgvA*s1u3p?F|ak8GB3YDL(b@rUh{
zM%(keuZKt3!Uc`%bf5jVi&jg1+OpZXPD4a26fhwYs220y
z0U=tgw~OtAwukR1xsv=#ZhwT-96j)A!qmX58!R}067UL;^WU5Im$TllG
zkpfj%g_R{-5Kc2n-V=*UETm-yp2UNIG{$5J2MwKT&uyX8zN~SrJEEdR%74ds--q6YcfvwAl
zPv=5f=M!aVFlr@hZm+fj%tMmzihKmqkKGhmPPe{Bk54SrtH$OJk~*$zVwYl4Bv77N
z)&Rsy0)#jr;{~@rVB4K&u$X9jCkX>X*GiB&u@ZO~xO=MN;gz%G9}_$>_B%*_gRD{N
zfuhk+f(%Sm85ApB3eiA$Wixy#B$-fDa{V%J<$UsS-lX%77
zkp!&$G-J}&-2O%h~LF#0HXG;E91_9Jr7Y4Gj%g$*~o}K{Q~F>?lP8(G!)G
z{z}{Q%PsU3TjlZ9G%H_A_Xu=ip`Q!bQ4PH#CF-V_AfyIT4hTm%;BQnl91v`CMFZ8!
zz{IXpc}%f$`y(M+>6G4W**NqkG`)Q{N*)N(*TMES`Ri39v)3!lDWkprp2UHVN!)zw
zJ&*gX#}IrI9X70jsysEf{~*G@r*I*Nlek-S4xAMFEh!xc$PY_QG?U?vtSBvhv(=#V^H_)FK3uGW9b<5S#!%i~;-rXiK)
z2;zb0G}^^ek|n{YnFgsn4|oHjO)m%#CL1z({5cqzQb;KqD&BxPP8J!xvxY;^J36!?
zkxbUF6zt0lA^tDG)MJH8Cv;b^c5rNZC&SkiVEo!GJ(f)SrM<{Rxg*au>us$LT4t(A(xP)Jm3S@WD~1
zI_sC*YZB8WvvaMpTTxPUhl4r`CmHY1!~^B^K}sf2034=Jsr1=G&w3&j$muHpkd{*t
z(AhJF^4OXoTG3H-vj;@}U*<7lAfbJym8EY3({eUbG)QKDTDJrMd0Hw8M<5@P!4h;?
z0kF}h%>2Mztu#^7IBqHw$2kB&7{&nP(t$r|0JBK1`WEE!Oq&H51?)%m@=4EA4sN5l
zP*m3iMs5+jzVhwrq$B7z{)G|CqRt*}@$#9%xVgyr+Q5
zK*JWgx&OXf%Ryobi?jwn3p1(E<}C(Hn)%tOU}O+88V6EcRVff{9K#88kQ#5BRLW!3
z0KW8c20sK1MJ!OwH+c(P4EkB2_}d5U*0dmEjH#v-5mY+>rNWR3iBhnTS*oOEm+f;z
znGjU+7lh$4C4{X2NTOcO;YosU$#km~nTKmUCUvnnKpES7z_@=E8j4b4;M;Mh_Zx7U
z+TksEJRSNEROaTtie>#DL2!S7)$J>Q&udNqn*Uiwj6dRVB3J;%j|<@I|iyU#^#T?!=;C76x8%{Bq1y>xBbsUZCd?^c(?Ds81|FUh*Hu+>*^D
zAe|nTbr2cgE|@l%|7sycgxqUq++jcW8We$^rth^j^=HNq$)D{KH5UzofDf`<(Tv9D-F
zuJ>nb4Gz(V8Un!70|1v40r0g1N!=6kfWrIP!WB8*1Gd?f?JqW4Nr|hbFnQL{pZv3g
z04dB$!ipgX4nlJO8DPcjP|70b+s}CcRH010Gb=;x>Zxg|N$ufyy4Jr>+wZ4lu2Rg*
z`Xn)%Ls4xpA82#b$=0(4K+nWO;XMmrBiM=1BNeQ~F>da)MI@KTJGWXL`dwq_;da&U
zIhUUT<2EFoHW=m_A^7M;q`ekg?}Nu{-^24GJ%2)JQ`4Z$gvUX4@w~>mOydH^Y8`A9
zi2HM^z%?q}^`AQh5O51trW=dK0_Axn=dB*u?kL76?GdQ5sJ}fEC>59q3Ria{r*>y#n9~=B+iQ7b%T-=Yf
z3o%WqZzi+~y7713J9&=Rp_azA)xMr5%$v%n8TEaKz931ua4Ryz8bcEs|_
zl^3h4iA>EowbwY=xee}4yGtZZdqR@ubC_m-)erQq_78qhcKHdnêUf(`rsbpBI
zhP4b_3a(Yck?54`3#x&ez&u0#>KuD?_3hWOvXr8rV~Vv-X$|;Dj{d6bM*BA#JzqR{
z)!&Zo8q(oB;ChQDo^z(A28*2uo4uCWJSs~OdrMipdd!3L9CDVbp<56Un)j-5Q^A2F@c7Kc|t(eH|z5-QFLW`sM$Tb|&`ZXTTWy>0W+&wy7YDyTx-K
zl>z)AItf+wdKukhHjT8VXyRm86b$*=Z3%O8I_UPaDUDYK;_!~rZ0=TPhW&J0(7Q>h!ec*Y&EnM{<{(Y`n>A(XWgwRuw%K7nazF_i=vOd|f`esBjH<;1&ps%?F9<-Tyl^Us7QpA%CeIUwXRO|r%E$NZ-7
zP?U{4{qSBcN7sT%=sKgc^%Qcy>J-+h;B-BW#rX$(jr5O1XR04IW&>y*ez1zy{?dh~
zqK=bz)Y`C
zK{IzrEz*#s`*p_t|*Y8
zRGrJ8`o#IR_4MVBnrbe#cS7QJlPl+|5(jdysfF9Zb<4l6#(rPq-^@*%_03%=+g5uM
z&(807USGK}w|=aS*~Zyx`s}WH+rC6~due#|t9NL1Y{k;<8p_>c+O$Q!{eE#RddcKH
ziH;2X<-z31a+`+hc95J6lwcv#uiw;PH#xw4!I&>CeAL~
zGaW82?t00nCUUgP;9cyJhESD%`xX&8I=dc%w1>`FFZcsj9;#@kP
z`K6X8j_I1$mCq*(v|H3i%EMM^Cf+5ftd+TrfTP!74NY-Ai?*h~vc6Y=LK4H?^q=d=_{v=Uc^}jVls11r+pH&RVVvznS
z!$bEqPA<4-BYyL%%*N`eZfa+R$7^tMBEEb6$5j1{(Oyo=RVn(HB!Yq&2prFr7rVFT
z^UKH1NHcmc3Vy953dw+dFV0eDQ<{mwnv`c~Z0?yt-=7G0@pBhqDmv1$DSaICz5RtG
ze?0G1YC>u?bFDjewr(TfcK#U;o+%`B^xGm1j~9a;99L<9*AjA5n{vSH)he}Q+jBOY
zmo*yqjA4;y>vcHg_sq&zig+JvnOVlFT&|~9JmF|F-Y%176w^iBZRpu4lq6QqO>FM6
zX^G*zKST?xf|Y>YcURr>30mK?J8(IBolo{#tQHeBbh$t$d~$;lVpwt#Gb5ikb;Yyc
z-lg4N6QT7$d$DW95k9{4hE-Q6pxh?&oK)!@|F;9Z7LQwdThw^V26c|mtl5N2&FfnP
zeY`_m%?YbdHR)Tm;kQP?0!*BaFmBH#F-+$%1WV~6R8)&#Rbpq9%ugX?ntJ@$aqADSZH<)Xm^8jqPIyX$aQPekMRDEuPQ}&T-A;3q
zzV4gXOj12BL%oUai@z$1kRpuW&c(hBEDt}ME
z`^d8RYYC4Ocj#LiF~_WevHSM$rJW~N
z`~CdP`~4+oDg=ijlljjF8M^nv2`K1Q3tO?h7p`DtRqg>%~tleBSA5@Vq`Vu@f
z?0wBd8<#oIGVvT5)e)SEJT>Gpxu69`z63^&(oklW3|U?k1V>c&yMhhv>HB)7k0W&p
zcs$TLGs)1*pWaBLB&d8+mwxg*jo|$=jt?iru-{`~Ut85I%}OF_9x}9DEU7c@iMh&JtLcRYagjgNhr-I&8^LefIvwNJ}8_1
zK%H4zTQ^~(IhSWuU+PLIS5;fLZ)nF-Kd-siP`j`(IV+T1JMUy8uDOf!&XmRGqF>`7
zbfxvx^>fcm{A=Mv9V|;7WyVSz;{((!SYj#`#q5dsC7nMaqkvloG#iu^-&o;qFUOvK
zqcbVhO@C!!_0yn!zK&}9US*D?P4Ou)8Yk*+d~f%4J{XQ|y_H}r_H9kYpE(wZ&l^Nd
zMpP!-&I^dwg!y(*=Q=l51?5{t0x_<>vwPhLTDHj=JlWeMbl$4Dgq7hgm2iYPWB-gT
zPPs-@J7><)JZp4fH8SQBW7TFw8XIeNQr~Wy(%x-(f0%jD`?`4bL~#1xWdBwwZ79)H
zpP_)ud~rK^Kd|X^^!%66oM-f_u5-U<+;w+Nd1iI(gU{yfW#+TW+q6pOQCja4oBKRD
zG<7{`zl28i_MVw=&QB^9G>k)19dxDgz#9mnaV4yp
z2;ZitdZPWwGYD3pju@Gb1i$yG8@?x+)s{0!*LSo|*k>t;p82wL#Olj~lc@=xxqaP)
zXorCZwly!DD+WBU)RQ6Tt
z5SD4k`GZksCZk8qQu7Qh$hC@xTw{31HQ4g1mrtxM7vY$O!Xfhsd~w|oAtNhl0|-`9
z-scogzaJ`FS>-SGyH3pC>{EXJ)sj!`dwkt_>i60AwDM1nlERy-Z=#)d$#jvUpcNzX
zC6DrmzAOu;9M8iuua{a+m<>GV(PUn)L7l)DPqBMT6dz?cXvOxa(UN7oZo`asAn#{g
zQ>yH~A^AIgO^w0S>N>R|uc>KCFw!AO*
z!DteUg>_f1dZekJKz~vYgE+-edyKVO=N-n#bza%`cw*UR~4)--ebyd!O(y_&NZPjuNvJuc*~dDRD<8`uvTQz%V&jidY|6FU+Jh^?xQ1FdCl}|Y
zU7g;e9t-zpoZPu)w!=7Yf8b-;luzVOK54bIXS5SbvX>X>+t8X~9Z6MHPvXiKZ0h83
zGW=Hf!u0!C-FA9r`VTHOs}i0h#fq`7Jr>2p)ubl8;dt9@Toz=DspYHW3N1K+`WN3-
z+(e;ik^8`2z$RwQar#y*aHiJ
z{RS)qW3UiX?rhH7_)JfpX07Vy9bH~V*o`f35q}HAuHvT5=YSpP=KNsF)BYRX$@2*>
z8H?-o#a2yDG)CF9tA@!A!p=S~O@vf`9p{W5j7__iw$XBU-sQY
zKRAqj-OZ&K`Wnb7>~yal=ydPo^kKb@ubz}KKhYj}!^82=TuaNdsf})k@zd2wQp`W}F!`jZXf!Ztd
z`N)R^zX)B2Lafs9snbd6u(g=1xf}ip!XY++94!JSU8R>4uLIx1lw)PauK}a<;Lxm>
z;;F9fbJOsm=LOEsC2W<1BA)6O54>@VeX4Jf{v~!#Z2Fv;>yvd)waw3Pd^>@rQe0r>
zk!C`hR^JApoAgKGqgD|I8_DyWK7ZpE5AK=znk~t8Hd};7?7^o8}$W~FY
z^=47d8jC(-qrl;@-}JnggHSQl$0)Zh5jA!F=CnWfLX`D81mS%6J!Ckn*1TOTCNCm0
zc5sYGKhY9TO*?_R_xbvOz==yc
zH_lQ^7}}+-MLtvx6S(K}=9#iq=m8nRsPrkiyV;?@=a0urknM3lx%|ZXplTRJZuV7Q
zcVg;O38IlqMz2sRl@R7}ZoEKvR>-SP;2=NpJ~+oaNhCNO>iu23N%yOC%Y2bzqO@U$@p?_BDk4ks`}c=rdyWq~h{j`grBpj5
zrEGEZs9BnkVwCfW^~Uhapbj!>%cFMfUcU+G@6fzL>X&>9kLG>>U9{icus|hC>~;We
zd1K&3{_0AU@w`|MzuT(=+ag$cELyC7QR<*oFdG_CLon-I{T=+cWG5!ZZ%BBwU5R7T
z3{0mN+M}=AenW^92@}bQUW}4SosqVkQ@DG)da_v2ISQksb!-Wh{-%udrBWYOm+Rq8
z5^6}hTgnY&{qM%N!JWBJU;1(sEXuvZ)q9$QF4}3?wJ<>aWET5=^W5g;JDhf1O-KB3
zs~w5A9$RtU`tM`j62akz45RuP#c#iyX5D&;e`AHBbV>YiaCYa-RrP7h^-G-G?n74B
zvrLbM4MpS4(xw;XXdC^-X#3Dx@?UE4Wg(62q_sR5^E2YHy}HHn@oMTs?5%iU3!Hr^
zpUFa^g21d{3sAb}3)tHv?U+(P1zpPe9AuBaEmAzJ-MrpS8Myx_xruKeSA5D0tF+>~
z*5YiaX~Sti=C||1NihN+!O30_x_FM(1?BU4w%Aevb%d__g-%N&oeo}t2`_m+eMt62
zZBsz~J8W1NDoVtyVQz)n(zLdwWa6VIN;B27%HT!NZe>ANw+;>3-QOy;u)qRl0-ZqmkiJ#7$;#a|V&M%N>5^;px6oJVb@r(mJhJGL
zFw}WMy>yPdFsOyW
z@H(%`yvOm?5R)?Lw_`d?c|*&gU&A;OmA9xurk{II*~p(tFPq5j0-UO!3fzoxxWd|HKxrcXhO{3#
z!fTuIGNs&J`tF?Sz41B&S8T|7PITPmZ%dN3m`GK?{u{;04O&yAm~>&ZpTv3R!3~=6
zb!S@6DvZK!$XBXIct%;j^|WXk?&OGr6Q_NUd%AO>e$hY@V3$|GW#*DQFi|gMf9UpA
zuOmDw|CCQ2Pw{O`p5i-AUH4tq~>I|K8EKvPhFios|TNjN)|(FWJ>f)GtrJWzHbG@ArfD?U0PZ
z386T=VOEri=qw+tN%Hvjie2!!OFM|1Z2hM$8gW8kuKS$mQq8bwtONYO%^U_1;qX_7
ztpn2Jm=9E@SwCtXol@cFkm?heMO(u%!LEMn6L6z}+`vy)IsfTz$}r^ny92tW9c_h1
zE2!vXwq0I%5kSrzDP;Ky2C$nXFYJ-JqX*?i*v;J#w=vw{sv3U%;W#o$Rf>^?U6O
za}qTJUm45u#REMB&LfJJI)gdxwvXzb>Ya5EoECE@sn@$-SF-XoF<0QQeOH1Ue4%hy
z2wmsm1>$k(F>EQ{A67(As0vk^Pwy1aWr9h+(hlbPhWN+Ct3Hc?di%zzUQRxVi_E#s
z-WO`j1tgqinSa>%E3M!n-ro3*IK%Mksp0sjOy_jEOo_Kzh$d~~A#}@RmSgeWuKjyb
z(*xwIW&SdT4Vd@^Q*HjFl!Zi*PTvgU+F(+7KkwRnOu3?o&O3V)XC4YBx!5|h9;%Iw*
zTP=;>KCie?GzBLn^xHg%zET-H{m=;iq`;O4{~h#S#`%75#E9MZp1pkxVLIcj2#6Hi
ztqAXh1W~Pvgh`g(;+ycY|8m7=2$D|UWvYKqu$I=r3(=oceqgf8#w%Z)%xDrjt3Q&o
z3C;yQy3YG%4{o8>hoseGb*&f$cXE*m--oOy$Zq`2V1B_+P
zzTg^U&=!|~c4unT`~}f)>ce0dm^-j_V-+;6%*4bE-flfA{GQZiYN>
z5fm1l-HW}hA%pj-5yE?-PsjtfH^>+2^4d)GIWd0BW&Fe{#2+7^%<$NDy&RJkX+?d5
z-LDFzQ=T3FCZ@UV6*g-*v?IqgblsHCER))^700C|ePT(SK;wy*y9(vP45INxYeGQ@iPX6<^x4cjU(F+uo+m?R#--qwL_fW@3E6l!=
z7LdV(i@TqhJT)p)-A69iE9*t&EYdqE_6sY9N2l&*wL(~5S64_-iBwebgEnsGI5&fY2-)(WE6rp48B2x~1F4L0{4-?(oCXD)Cba_swh0uxZ&V^t7
z4)uedNgbtlc(BT}y3o2d|7-j^rCaA^dW_05PM2w^n9`{d!Y{1myFL=O-zbjf+~n?Q
z8ORt~xFH>3pCcQX^LX^@>%9p2IX_4q2)XfO$auHZA|3O)i3ontaRsg6CZ*`_^zU5W
zMy{)Yy(WhyVu$@3My_-}BykTDX+#LJNT5z_$RZsq3EjFfVL8aZ345O}ds&M{%q$WP
zplq(wPLStCl8Kj#8D1i6^_fvE|62Jjw7N;%ak$zqf#!pW|I*aI9$k<^pkVTnNR*Y^
zn*bUMc4VEoCg!c(lykDr26M)OsHXJ|bU`BkITGkckYhGg;rgQc7*XWMh>rS{^X0B}
zyrF5VPa8u{GNHE>JXVy_B=HkDARrM|CSjEuH|&Tr4ZlwGl?+P#!BKA*J%iR7Ft_dI
zR?Wyyk9W~KV!$8B1oipQ4fT6FPSUGrK0~r^?{i#GWrdPAA@=*MWs&vV*Pq$2w$XnR
zbSl_@6^Z028Z92p*wnMEZ=X~|GIbb&f3bB%q~|%xVS2F!i6CmACD10mT6J8S6ZsSR
z8=P}rEiVc*xZ{u`<*e@9V0Im1LXes(5pT)!fk6uulvg2q7wcx|7N1D*AfC0y|7vD>
z9h5LDMT+PMy9#As-b{@5a!mZdYI6dR*V6qf`i*2yt-lvq+%@>U{CSKZ8nWz!DTcyPBiD4y=`Hxxvf*8zxfrK)gB4--
zd#}4b7|XG6I0E+F?n;|#)YuZe!q#?Ny~eXU)$rBg6Tju@`(}9~(vy>;#EdE5`j`&e
zZ-Fag^qf0_HKld1;`3M_)0Q5|6LzY^j{czl>ZxCPjLXfb1XSOF=KEJZt2&q=zir)Y
zMCNHGOUg!XdA@c-QC^YAp{Q=g1fsr1a~Jm1SbRw1b26LcXyWr
z$s&%uP^foDnK-3}8CsARD{tq_X({>5aoM*B;N_oLh(dj4!zx9C%d
zOk|UJDPp-`c=uS$K-o-jAnx{V%A}~mMV?=xY|kHrxmZn~w13`yS7l8ie~(u&ihgN=
z^^tIpS*_{m!j*Rak$(O>odnLrxbnqOWKD=EhoJgju*SCUrz9$L#lVMO$684trPLP}
z?WJECweTL>O8+4uoWw_ARyLdy=2ao2Mm)j1_qIcx7I%z;tH-Zq5A;7gCt`b#$iAij
zv1t)cv^KTjR{^73==2q3F)*2P
z3K0Do@NMEN%GA0&Phk|cq~+dX-iE=V%OBR7`4g
zGZRu(wP3gKNGFZ@76t3H)HzlNfJI;T%>BkigaOfHK+SOVgvucI*$Z__V4AS%tHB2-V*MCG^S=I0!KGo`AP-YMAP#s4yl>z@
z_0$E&-YnAvzn+kvLhr)zj6|GsQ^-ppihSOp%;&El#>^vzk>Wn)-6_ooqW-pi*Mjhl
zH)WpI{*vqa6T%&d5HJ_RU{LU5v|hrc^J6?F$H7ApgZ~tWi~}?8lhbX=mJCMa<&-(s
zhr#GeV{a4X*BixzPWxy<+n@3jg>F3Ma>2}8vTNPv)WS;ksmjF{oKu#37MD#nxI-*e
z69UN>*eBgh0_(S_mPPuNk0lI8P4}ZaUS2)yOEY+PBR%sEqgy*UFd@U8_WY2_PDS{{
z57Td)22qq(%t%G@o&+7U2-GA!qUB)cqePJ;UnQZ(@!nv}N95HZSiTmfs7F0_NFsB6
zg{)`yhH&2kuQ#Zc>f7uB*hkU}@_3oi)bwo71kTq#(Yp-AAY<~#3lPp!)z?@VhW?3X
zLP^e)9skvE0{gGYa%l$+NSr0Qwu75!M55I0F{Qb27ni(%xs{NEZ66
z#=A-2{n6F3+4_BIIrf%+1$qY(VRu@ScjqO%(GM*O5nX3SYf(Oj-WV5%NYvmLmyRT=
z;m#4kOn1CMwwYG$n7XEk!|9J|LLbfJIMZGDObRI5b6AE(4Xioi*Fhkr!nGoK11uIR
zE#G*)dYC;ee+Rg2cll8<^YoZ-NITM!TMo(iJ(%^i~A-U1&6JVe$+
zWk=O0Xw4OsBj@v%`z3DNO!P}U@T22M4c1yf51MkM!m>jNdDLGtVA1|t
zE#gTeRmfDz{*;S}g#J2mVop|jGSeUAcWhi*
zO@C}5_M@&Qcq1+HP&Ze9QEiXlc
z^gdB{2gp64gdJ?KJ@e@bPlh5@I%`(Ny!TBox_s}_JtDp&C-QDI%psjFinJH0q#$1R
zGoGYEe@b_!CHz8{kYOyJIZ@%#9g*o=0A{{2om$eNVM4&q<@Fqp|lx^7T&?VRvMvk#PIhWx3K#mp^@bLAt{0YBTwyV!OQhpIT
z)ROvk2k~+nHYqtk0BgMQoGNbum@4?--%Up{FjZ7kH#~mtMeUI;6{KXL$V~=0*;oq1
zqz`kTIB$2NVZuq*l!A2Iq-eo8y{M~nl+X&OX~AbBxObWYlgSF9iD<WOVEsq1$UF9YF{2m`foklW6s
z^E5y!bM*ITAk5d=$MYC(j~+Ud21DPBeP3n8a!aWSx{Lhjol-alv@#H`k&rx%bvm}o
z)!28|aP9cVzQ5&gY?rQiET8?B^w6v5V65_&?POzQ7^|gNOUE#b0ktagH%}S?SPZ&D
zepsH!ZKAC(LTMQ<*th4b`ACSAJ9
zqbKP8N0+qatXzhGQX_B}`cJ{hC>wNUQ>a=RYa1<%j1tU=A=kf#z*U9itRx
zK3}~vtr>c-@nO$}BOv0^^nDHx08V#JUiaV_J4^IoDPVFu&+ri4X6FOKab|ifs2RA(K
z-*JjEq>wAWws5zslln*qS}
z#D51j4RE`R@ja}05WALw=u8_D*^UqXf2*~D#qWd8mIpPy%QrQVH`d_~9QJebaXnuf
zAvx2jtJZ0+xY+!(DdPw|2{`(?uDN2ezx8ZvEz3szFiHp$j)mDq!u!-*@MkyUM05yF
zWcDlI0R5L=x3c0ll&TGJP;6u}e*+`&Q$iPU-+dO8IU`
z`7r=aqWX~-{#|8d0G0he9RtSj%z|I*dK4`GaNJvl=2LBjeH6W}i6K7_mDg=1;)Tfl
z3%BOfGBlOeMj%
zOljc#i6TLjGfz&!$5Ka69Sd-2lq0&8_WC2w$k?0@w?yYP^V%BCsY9Y~o}7RDykbw6g#HrY-Xp-(ugt6p&
zC@cZy@>%*Ur=fj4oE+&8#eGUR@UP_a{)a&(R7t}s9J?{VFE37ZQ;$V?pN{*|e-3Mc
z(a}eJ+)_FvmpYK9f0b*xsB-$JlINrVKt*p5L@?ZE0aP5N73ql$IKEL4jACD-u+>zU96I1^=9Wzf~Yw1m+Cc+epY3mV7#
z4Gzhj5#r$sieYR)cRA%1mfA0Dasne8#9#Aj)ly4yry$pjf?t1`k$lae2vi4%fAHLY
z251w8qVODcM>3q+>Tw#C$JkjE>`%D1d>EU++ttlEGctu(ES~#xWya}`4xIKK!Cox{
z*Ga!aFSq4m0i&$NnD6$I{lCp4B98B)Hy;*Zmo^z({OE0}Z_
z>A+Ph1B+UhJZFa571AZmIWnDF`#&ilW{xHgI%WG0e{cEoiYGd*L3uq)%tvf0IwmQv
zLE+7g*$3TOrrQT82HQi#`0UdNVJ{hM(D%V5H5m;F^cc87#2q{ibWpyO#6&uisePw>
zxvFv<9^=787kf@Pf=DJQ8;9+s?fT{(S=Jwj5wK%R={g1Xx=4UoS$~e1M*>)~C#ZKz
z_6aPd+J(fLd5oWf44_Vd7bb`z;!KA|hmx@76TQI=(_f*U*<6*sZ#$S_+A|Tv8A;k$%N;8E<@jA4%5%G7OUJ_3L5C
zW9nhy$VzbEd>|mXw?s;-gMXGkh4t|fZKw)?aT;^)6lZLwMa5e@VMi`r?b4|BfaQ`R
zCI9o{*ZCA3zHf}2VHSlt+V2PMze3az;R27v3RW9<4a+o-Sgi*A@TTqS3l>qxp|f*}
zNAXhI9P;@u53)Bn%rqtmnB||IH#yNPOCiHNQfaZ(4h(&ef~9?ValQJcy+p>uF^^
zpL2NHk1t}fTZHmVDkb>1oG4&+R=i57^Oqst(0~
zKyn-#`!CP$*5bVV_Ks))_VE~>E
zhon~jdXQ_n2bHS4t*bp4hS?W;aKXu^GxQfiIa3F(ha)ni#3Tir^PMzpMj&SD&f|#l
z$;|#l6BD9~_Wsb%lT;O791(|!a+!p}@mAfR_P6>K{fv^I%MI6KCBd@>pURyn$U0w~
z5%p5R|LotH3p_(&0Dk4s<-MweU2@55mE^eQ$)|!{?&C_TLBYH2Q?BGV0@T<_yBQT!
zz>FvefERs|kE!}SpUsap066;bkq@S;W8+uvbdTKN7VlQ;Ue^pZ^1VTRcvVDn9O
zu(Yn>_|3*M#Y|13MT_KXx*DY&%UowivJ6dup`%NH=9l$nFckWaU!EQ6IL#IxO>XNQ5s`0_%TQJ8P&WZA*
z0Sm(i`)*-eKxE!wj(=*cHNtlS9PK&>@_mo$kSyt{>UknC{J3p
zmmVm2u2zBF{0T?yhP@8zmGX-`FK&lNUy*E7zhLW9Q~2hZe0N@wtK_LD}wpD#(R6!%W3(fvKj
zr|-F_-$PJ!+aI%AFsp*{U3d!~CT9Jx7*R~97D>Oxs8%+ardag@KF+ALhfjn~U*|eF
z>PDDgJ)Q;(PiKnJSq)AgAvHdn$L@?o)p|T>`)Uu{cJ4<%8b71F{s4POmxyIG-az(c
z&itV#+#Ndn$aZMl#F6D92(N#azTQYRU!RraU^7P;E)
zTBqL(BdhfmfK`9d(mt^3bJc(5+z*TtlQd}bRhBQHU97rMLSzbe1X4i@?&j(i`D8;Lz4bQDS9SzOYu$Zw@+`liOrJZ(6bI*kmRUdotqp0jC{Y||Uj_FN9mz#a>)0YqOrv_2qZAAy&>^&hhi>%9G
zbo{aD_b;Saf0YZ_Z}YD8MOm)iH6-<)<4F@DDXQyK!Tjn!og_1LA*Ay@M&Z0C$I9GAoesW#62_In!7
z%QpOhx{t8~X(nO3O15fa)r!XH+q9Aav>tgmA0!BWVB0_Db5oYuu62ez^cQoYv%Z<#
z4Bqt`d&RRK0J{v19P+EaH^{a>n%lKD?eKJ{|4jMs#d6m`tu(Y&0`XiA+nrpk(c19L
z1$G`z=dkipXDsiA-2*V}M$s#JfMG8^oXDd&$aL^{H|^*4RKc0)EB32;oWUzj3~#56
zt*Y@e8=9;ANW!sa5|piovYUOy&iA@8YxhyVPPSF1{#obxlCvfYrEShhd%b?JMHLFU
ziuM_dX%2l_A8#}nP?z>4iQRQ0Qfqhe&onNx!}#%YA{)YQR=se}cK>so^$$DU5}0na
zu$I1nV!tZ6q(HqiKP68zMW)M!b7w~SsW`tU)^V1?1&L^@RWscqV1?Bh19G%2n*pxQ
zrvi5^fJNObo009Tn!TIxRwCKJ1;19?5-~xg{;#j@S`3N>dIK+lu`yzltwR4Oc!-@v
zU$*V9@f*9%HV{*;U0$uUbvxd&zS_j#2R^M2SvatRqvsAv`LsICWEeZxVf1bkWQ?Mq
zex#UN{hC<;`+yVTy84)%5C2KT*^*S^z;klhq&`JdzrVUaGbjtP`}1tWygl{nat*3j
ziI&}*mE|Y9^4Jp!O$y`sd=!3AjKusx1%Wxcbv^eZ;76K=q3D=j0NINAmBc%X^~M$R
zzqQE?;HC@DrmgA5KN9J!OzWL^nN_B~t=9!lwPp?MiM?DL)Lx`VM@*U&xNY)1Db!p5
ze!Z6R@Q=5bYQiMxa*Oc8X1y)}XI?r1KHSX(bhtpjDVh;eceYO_rNF2B03b
zaUk``a0AqXx6oVT+rSaoc2=8NmwceO_a+Bj9
z9^!jjw?3bGoJ&jMiY@bDZ*QFn+iP=L)7o5BB23cq
zU9~hc<^5XAY)Jwx#N8zGL!U?YMFhJxFb(f
z9pdFv8C_z0Y@1YgTw7jq0bfU6D~e
zaToJ-)Tk!^`
zT4)XrSmS!Cc38L-YT%i;cZP0r2j#RQd|HX7HEjN*YV?Kst7_Vo3d=94&t=)P6SCK_
zgVpq@D>P0zCqH@`Ms@U#IHBUBd=%?-Kl-cbosaETvSffGL7_IRX8BkaLTe1zO-gIS
z@FLw333|~`mF*{6VqNBeh$g9BBsb{WP+<6F{pnF6?3%aVWqSQu;4~1z8_Oil2s^nKN7m0L2-iM<
zuXcacnq^1W9-a{h=)8R)FG)iQo<&w4+eESYNgM4ORZfcEtX7@Hld5^fN1Y;cHC8hM
z8l^NAlgSn)g|^3m`e${oeu?_Xg>DC#3UZPX0>#TMxqk?1#dtC5TwU-*!RY6(N-2cj
zX7beZC(H1tbZ5dI_RBL#YFP?NiE88Ee_)tR*BoxxP*W~jQ8sBa)i_FXs8D3%d|*}M
zT4}He2o9%C8fyWj{VbK*D$uk)CV+N5-trEMR=g?IX@?dsXHrfB(wEwe#g$%D0e}$q
zA2qGX7Nxtv<}X%AdI)wN4pd0SmW0$EUeHo;xlF6{y(=H3>&Ch%|v_>N!9Ue*5R$1{a{Cs1(`?1pKppX{qow3VUSw7M-SfG7}A_m
z2v@>gOJ+)Y^EvVHw>6!{^it@&Sr|9uoNH&L@ftOpEe-4tW4y^VDSq?6`>87U)C-7E
zdKIKAo8GDM4nU1}-l?(1i_Itd1`8TqK|B0i^UjR=@MABGMf>PfU3(H$rsiNYtW3;9
zob~fI>OmoC;F-*Z&C;8^aiV`qUIObC>cLVs_aZ`?j^e(pkxY}1-}oPiXn89{>R98N
z#>qnb{n-Upn@C_Z2pGQ|Wd9cBwS?T2bHIOPLCGur;+#Ka8SS%8z?$hH2{7Uw0fP`-S>=>x#Umfv8pr+oUT8tAmU0bhhn
zN>hTo*-Iq)l4285I6VC*hYX>#argrn_l$xD$QuVx&Y=mKgfHc0(
zMV8kiI&0I+H9c8V_fCR^{4I~L-7v!eeu!32|E9au8X_CE`kV>B7K=Si;JMgca@WoG
zi8gzwL|;NzQoOegrP4&u*T-w7(ZQ3w=R0tS|}gyzZ)Bvdwvq{Gw_Et7W*h
z5SVAKo~`L$hsc6ihgb^zY~Q_z(3GV@B(u-4AR_*>C#WE-tH#)h$|9b+y6e|WQH%?A
zZorayO5uG$TY@
z`$$LhH8kWelJ0l!v})Q3IL?p2G%U0pR#~y(g~+XJUdE(&_|zwtbnESNEITJehgm!v
zlI??Egb}}VvAeeADM|UIP?HS;&#_ZdQT`S49lp9jBeC26l6>CSJA^VGV}uD-IVwvz#Gf1>6|_<3fQLe{BMW<2e7hNaGFz_TH}m-`X2Od!G55P
zzASis>K=MoxNMA_sdcWsH1el->#-YE>xu}Z?Dqz5km`eD&^w93fM42?OVS!_T{|GSp5!S*T1ED~vFPHeY&MQ48))(A@OVXg2So(NOp1l!7XLL`-xKR-qVfaqc_OBvE0jUSE?1LCj3Z~vm7$NY
za!rX@0diQ#O$L`x|C{p`EO9N|iG%_-HT04O*sMA$Zh^1ybjPZ4S1$OWun!Gk2
z*+enEo;RG+%ebTmG4sK-e}^!4-|=YV{v-jy1!pRGve04-A;uhic+9J`>!?i+*
z(N}+BVHOB-awO3X@aSN7M<-xw-XKKA8*QzgUGHy4%o@02VUXInJj#QhMiy3JAQHM;
zBV>DlIX1N2eu1d#{P*Q@SrXr5rwKouky!;x&t95v_)aX6*O^lpvJld+6~D9&@KM;q
zya$_^0}-`?ByODV5w%(WMbw)2B^|r1k1z2i9p67APq2PlndR%~8kg)u9ZtijJ*NJP
z*Hrv-2cdE=AD7t6dQXC6c-IRxs_#^I%aHyNeB*>jlu3k81nQ+Ypi^P{8)dfAvx-FI=4-d1Ug`;vo4-B>-h&zX@MTu#=@;i1tyKAbh+iIc
z7VR12{YoGB)Csy`?LL@gI}pF+4t57D66sOIfDHsA6CeS?XwJdZLDbk4EU(J3r(;48
zOuDDTzq7j=It{XG#HTa5wdn8NstG>MmO!TW3wR9}#
zJ|`K9g`O7fD$;myTW#G3KO~{Ui1XPJ<}ktogEp`v
z?E`Kcl}$&hklm~qc4p^Vl^NNVpjVh~G4TQAVhAox#jcYIL0HHbGC})`=eu9DvD4JUNZ}e$`)6xx+
z$_ue;@N*58M|K_%*y;d#$a#<
znx8PvBst34U~!dik95P~bY-$Kc9a0SaRFrxFR!k~;NVhggLOkjI+>$PMdZ=r6V}6}
z<+cSvgw{}@Siq92gvmp~TSUR5r$pQXf+xFJ*?O(#Qb|4Z9vt>u$@PdYEb&r2>6u9!Ye$cRAQU;WNz^2ONEySJ(!iy?
zHXMYCD>OgUC&r$it>cA=_b*CQKXt0@1$2@z9nq+)(@uxrKU{+uhH&_R&1e~UgYm>}
zgKy>8;BH;+90gq>gra+a!Cwov2T1Gsfb+?mlc;xP`$nFQVhdPOTkYm8i$l*PSr*xS
z0mGIDIvo4G!*#)d4!0?+3V82u==ToS17c~db~`faoYGyD!PDv&w~Q{T`k;rs)*^aF
zXV*TWIS{h35EM{LW7Eg*B2~A|RoU9SdO<~Lg?bIyYV3C-muS^n0o!+3io~UlS@R<_
zKc}9@_1q|?Rbs<=hG!GVhZU)zTM#MiW!w_NSbkkGl_24
zx!cpbCh8=*hnvJWE36WKHq()%%fGnFC5`cCcx!b8!fjQj~p)R>E|kLyivxYDXS1ZAAzf_
zNjUgH=%4y0|N
z)GXS?Y9tvgAT-AqVW?%WD`wEm7%9^?qA&OE-q0PQYTt~4_3vkG&~uyDU0x_NH_|T8
z>^5YiDJy^(G}GGlj1&xqnM|RtvL~U+c(qi1&W}n#V~q4
zo^^5~&PR9}%R+X<&^`un%7uyLug*3E4=oc543ItuGqHpL={KV2=$uN&n$bOD4@TWH
z_U5Hk1l(r@mWRe3=&d%UX3rXI7JZIp&t_~EDID<$!@I^Jp^TN**AE
z{%gktN~?*P8RCe3n+8{YkkwfPSBpkzDEt8Zy$?Tj+r926;pc~NTjnwvXoyS-?;89C
zO<~rsS5hCe0nZX=E@4)vm;1J-KU?Fi$qt{_cC;=RXJ_A{Nu*?
zqrl6iqzOuFAehi#rG1v8qx~$9pFP(c;;c%KF(O;}fsS?_AwOI9F~r%~2xDY81(Wqh
zgI0)h-ydZ{Yze=w4&Srm)$WvsdNGUZGX=d4?}em=?1cr#bV
zL~nQaLH%gZe?Fd3U!nL?j^bLoU~TnXw}?ILGZL9qx*X+!HTQ^P3s*|X#JqLgFMq43
zq>|H;8R-_hI21LYIF+k-ex`{gQM-j6e0-rmZ@={3)=|I*qw*{$vDkfTHm%)6e4L!$
ze<3a4!BOzK77#UllP|iSHns4TOGG1lvz6H__Tw44u1!MzX|rMxOeD&i5k7|^vfIZw+d{Qf0NOUp_xw&Cy1c?$1kmyN8abIvWNiA!+Sm*a5O
zfh=(Y4t4*!2cR3_l^?8Z0acm+Gyz2|`T|g~i~l9dQGav+)Up7z_CPI=WzmUF!Z`yK
z{H~{qMFxJ?%ti%6zj1V~pcT-;Rt4skR$}Is|M#p9P}>O94$c+$0F6P}!G!{<_8L%u
zEi-{+!(*5z3aq*%A<^Kz02eo)ki^Y7XaX9PkgJ=y-!_^6RmLzA}b
zD5il?`UpyWrGBK{eJoFO<{$2n*G|hS`JJ91O(GaCx0Y$yf|HiqH24}aZPQ|)qFqY
zYCnrMeBsDuQDgv1UI0`sC2WwJzow&XDC|K!S|uS`wlisaJcO?g*;FW(T=fo~b+cUcdh+84PN#w3NI~lfh2O@ibtHtx|%7A{1Lc
zu7_dZWE~ix}SY&6gN>j-buZg0mrT5Ej}D=LPJ|NKDDcR1&-(%D@oBE$%|`P1S@hyuIk;S)_Z*EVfx%WmYHT=y|-#Ce1s1qyc5d3sAnOR2f_`fovZ<8P7uA?Z^!ZJrGS&mer$7-bfMGnJR~
zkHHRR{PhlzkHLJT)|F^~RkGsy4AuFu-zw9-VyY*V>Ep8qY=8eCn~8zLAp3bUSz8ev
zF{Scvqy8Il83l9bQorN3IZ~XcB%nk^^`Eqe+(}vq2%nVE0q!1ld=2w%q?95DPTtK8
z*V4aA_MDra4muyVoTBz~645F|=U_`e(eUO*J=VIhdwDixDSiPywWts^Z~KP+J19rb
z*MO+UK{$i-?BxvN`{1)bC;ifP_iC>9Zs94TC&cN~$=PA@#?#fA_nJwQ^^DOP0qyIA
zBgYXEZSRER?^%2$cfsCaeG9(jOC(xWf!^WK3C9@=x@G25&9J0(4q7C@S*L_2=RTUv
z_U$Z{-w3F2=~4cza}bhm+BgO;Ic%SS2{dG(4W2k!61Q+Y%i|PqpTZ{=Jc@}Uc62+t
z#=sDHjLPcw1&)x9Bqp=HkCI&C@0qw1eD$dLM|k$O^o**li^Y?1qlj6fw&0}l0@0k7
zms)=OQH=j9>zlUF?6uOS`wT+17sA6&XxOux>kZeiq__lI1;MYc5H$%CFx7m-a!YXx`0oDL#dLe{pY&`sE_5+7CUL%hM_wrq|J5U(n@
z15Om=C9|h6N~kFXs;H2D;{a7OMhZehT%?~Ra!3T~Z{|f_X2yT4Gw=-!{g@>^kqoyB
zV)KKBz0V~pHy2i>;*`QaX
zvRnKlUFahIG|LQvNS$y)S*TTm4Qrwb8|g!>4YXwUnRd4_Q>%t@_-|q|%}PT!yHaeV
zK;-%$@``*7HYn~n1eonSZ`qqQC?Lt%TZZouzZV$3#S95PaZ9qGgM$T5ES^+BLn)ib
z2a2eN5&tV<%`b6OuGBJDsFxl^`nh14fj&>b%$cWMXf~i`Q&;a;)Qm=IIxk
zieL3>nxpWZTid+4LwYnc_@qyf3K5Hr(Ny1|Inp*T({9Qc^BBTxEpMOZ2AZK2ghmV^
z?EC?~tDnHCE??<}Gba2la9^o57^z6G8M1U8N_>`@FPjCvaKAcdpGQ$q|J@)Hg335y7H;>B(z8IgOLd7fq~Q>1$F<)4+@I!Z)p9&CsF&YI|jr#8+A$CT^i
zK&AZ_VMd}vhdwIwKMlJiGWf{pmKCzmzS+_!!O8Jp(n3*ZMPddejrYNe51a3V$yJr^}utDpbWTDs?L_xwFj-N4cO(aSb8(f+*CZPdw&&$#Gp30BPui5t0B;D^B-x
zP6fA(r4*!0w}wG{gjMg-#%D)Ror!C9mc04
z*fOOR`5^{&n$d&sj32c?Yl0`JG&L)zy(^e54XDAOEzl?QN-7wc!G=DV-;SfYJ#m!8
zX%jHaCQd8zbZY`f(kHH`tCb!GE=1bWln7;QwFPN;ye>p
z;XTDeLu)5f4(kWXws}wSfwC2_IlE3f;>YPJb@{s8J=}{`BzJMkIhlPlg`T}Nm#S$i
z0bM9XyZmqN3Rn&ngmfDdPdDpXyt|7Qzx3lbbzdaHueC)}PY*)SUWfYN$$PRRF(vLO
zF=<2KTmWRI;{l8)#sC3hXUBxF;`}r&^Mb7op0lLt(hTUfSD}zGx4(
zbv?PyWLJk)p`y>?N0aMvXwSC^SGay?uRx8#gVf8U58>!I-0k12Rt(;%p1nTeVsnk1
zI8{zYr{I7wIcpW`SO^YAr(Qr_YeJ~S;6)p%=!-39W4sm%T+`N0)I!A@+AqfbdEXVN
ztFN7?gGvU<4&RFffwFq2bVGan!3fSaRv)	mQE#D@%2&6JVq>VvsI86UEzYj`=v6
zY$$?tyk2d-kO$K`prUMMC$K(t>j+d{ezQ~B>Bjm~@(D(12mBO3AebJ&0=5D`1+`>v
zhl-?nqF+|XFef_Mvr7P%_Bz0gMG3An&yYIUobteTtQ%f&_+Trf#MH%6LhUy{Uq1aZ
zQTEg~TNEWrIUZPAF6yjc%*>?mE_iV4u_BX5eo~hhSqoPt_Cu36cEDB=v$)RntrN!Q-^+ZF49m9JQYp6Y&496`&P+%POih;
z|J$sov@pAntGwzYlwYDYi}qdl_H0*TDm|Pkq|{SJ;@SgM7EbFrA!O%@Bnho&ha4W<
z0uW{ZLEI7$b^syBN+dJn4{DEfhdTxp8C>z
z_Qnb`a^brQRkD=zt@+uoyPUI_-f>!_HE94?f%=H7sI>R+nvK;
z-b*Diuac)nq+I7sMWwpq6-$BKX%{TlLdm!wd%7-_saQyUgqGkpAlEkt{D
z-l{{oBWWihXkonXp_&DEJru$z7gx
zRni{xp7<0{l!k`R>_YYC%yl|2WLal#8z_B>(m!LlP6rXYK}
z4hXY=zz#-G3EN45!JEj0s`0@V;2>U(^v0u#MWeyu=sNZk1|)5fO91D%HI%PQ6^_72
zY>K?O$@|!snpOI1Kn6V%b<@Re{nJQkLP19)Rxynkk_m-hDAv7T0M@*wmv&L<00N~e
z5HuRgE*>*}2Xuc33()B%ob5nY=Z^wN!07?~FMZ?;z$1~iYQArkSdbaz16()(K+`~~
zTlN1B);p@HTA+U_`SKlyzN~hJ*iL?ImhL**ZdA^r?mVE}j#_nYF#^rh6iT_2FMI4O
zYbN=JVSL!3jl`O_%(#95nBfw@45e>v>c*6906sVh@WI3apg75((2U{(Kn#gGrAI$Rfrw#r
zG}b(TfsSqwi1!`u0DqC1HH3>xU)H!L)zc)SQfbDbs!nTP&<4ou`!pxz)J3J2?P_=R
zWFI6k>E*_G@L(v!Vu{*CL|Z#ZNOKHg1{{VXROJ4~LTS)NsL*K8Wt}KgC`+VgXy)6N
zan?vIt6La{V)TslAy9{8L}JUqabhxlLo){&MyRl8z@6~mGD5j!MPmoGjQ1mmuOAqP
z=GnW{NGLZpYm%3)>QnV0{n($0OeY$X*aHAdrm!C4vC!GaPwmeaio_zODaQpIGWU>kDLlXMGTQ0P71#
zduM%M>F=x$!Z=P{N!(0U!3ejs7un?M$#F2#%dLxVcIF!T?@pZ1?USP)(&)tf%KV)_X{D7nG{4-`J_?O#uLMpU
z>VFls1OBIkJn(-6<3JLOw+h&4u}_RIUZ^{P-!+~%Nu{8K0S+k=0q+fPNPjeJ*G7yG
zXkn_C52R2qKuwx3I>Ft+u`_2+8`oh~A96DrzY}bAMoJSot~vDu7!N=a_j&-5hz9UR
zNfv-N;*tMPQ7{IG2$~D?k*B3;6fFc}IeS@suou<@WvLc}aX?vjVNdd8TvWrM%3|!$
z(?F!=wz>jm9SCHPwmfosqmJ_@d6QNe%ch*P0e5Um&zpy>t8w^0a%5CaR$psvYcb+~
z+R|smjLQiH<;13VDo_(LUc|Frg;to)|y?XTxeUoo?WA
z%L>KLY#HxCP+T`R3N5j(t(H)0)Y8oVxyn>AHD`yTVR^!X$OtqG#)dFVmtVz5mNCZ%
z!E1~$%v1wN_~
z8j}IJHGnZj`T}*=0sv#&0JvoTF%dUc>IW8)Lx3f6IXm$KEO9?EdJx1C6LpCux+P6A
z_I4b2P<7A7RU}QIhx^w6TB(u9Y-HDJAiU6EVQjbR1#slZrZf+4wwAC@w0DHw=N8|u
zt1;riK>eING$1DgkqrWb0stgk3IGIs3j|0P2#^2}AfSdQP5UO)W%d9^`P>Mwm9kZU
zx6Ip#XcV0AkTR;cWyPnIwu}$TsjnY^ngLhAuHDoCT~FAVpXLA>V!OO|H?atct8o`4
zxzYQk!gl|f8-xd4>;x8(w}0nY1mjAK3sI3*_e)|RjQhw)W_wI9kSS9cIX(
zFBg0iaJ~~jCzYY4h9-9BMcLcAOo^ROToy_
z&DUTdXVxn!JtU9NvIz9NwAxJ#My%c;
zz!MdR0iNg%;)!PYNOq_J=oPM77{~qmw{e6GxRjaSAs;=s;
z`qf>l)(U7AqywJs20OfU{ypD$ao6Cb9UNUGSkFY^AVpu_@9fQW?>s&QhS{TBAm$qU
z`W>%Wos0b!x-j=QwlHz0wH$Kn02>bO6520}m;@*UEgM1T=M
zZt)}*=JB6g1C8hhoYKxM%){Ss#&A3E0YVZ32+7dBHreFA!=Wo}XB0E>(Alm_-+mJ#
zBmFH;5fCSuoYJ87ju&{&DpW)+Kc@R;C_)7BPZccc9Gi4Ii*$oSY^>DzFqT#0l`=!z
zava&L)t0Ch5Q@xsbM4MdzydC?z{&_LfalHm+|ZLbqmSJhYXC7gnhu>o*1RdvE`Wnk
z2aK+c`m%p8awoAMH%r*Ah0>r#Wz#St`$zzN`Dzo3k^iEM0zi{Ys4n_TpbUcuR|73~Iz~urR{~tpd{g)wO56C2&(%WQI
za)6HiFHe@%qyzE(q^R;l{Glo{H!BgXijEq=imFU54IHkZx@JWBFLoh7kL`PEau9j&
ze@v+04m2U@BoL2WOaF~WSQCr?0gwMO@PCSo|H?876YhIz4Dc+p;f2>$1n(0lQ~69v@!(!yp9%>`syJDx^fL8sGm46
z;wCF-cVW-_%?hn;~u5z&>!f(Gcw2i1@b*OwPJ<1|w@GtyoQk;8rf
ze4!2h!Gx#dcC1lumyaNpQhX9>_oLEPyUzdFh!A7{ZN&crlcazD89vk{(EQ)x-rMcENK2XT5vPmoWVMHN_n{s1q>W)ZF%wKc1CvX
z*=bb%IsZHKn)2?(-KA3lr;_L8hXRxL?$z-uFw$j;&pjId-)@{4MDxp$A9C8t?w{3Q
zSN;
z94^mC_dke400T#rHpbuxe#2Rm78ZjU;x^l$2PK$UV(@M0Em7Mby|1RFeKY#^LQ@!hl<-Q|4UKv
z?*WjC(3}5k_-|%FFM>`3y-1bx-(G}q`X9ackNp0pl=v?ufyxATc=_i~6}K}x!Ts-H
z65j`SnEYce?YS^B0`50<%1af)e1>GuM!9kg!@c19gUh{xp9cUbZ?v$YZY`2keI-Q@Ew{h~-CGOl
zlic&KG_)hR0Vd^%0cNr9&;vFr&c16;>uZ5eX}3nteKh@vdaJ33ng@aqfba2Y_l$3z
zT_T+F?w0w%TRku&9=E{&tvtP(xjI1bbMJNKVBexmyQ;fG1&y;SoVZ$An7|<6
zf;e7UYbNHv7LZ$LO3S2WIpkNzM5HBxjS=SweFW0YPm*9ni&r?&FbWclb`L-=wjH4U
zR3;V#u8!L*Z4(>@X8hJeiFKXwObG}pL#H*s8%ihDcuawM;yY_3g51LXR4LAu!e=Jd
z*;v{Qj41dKN+0zt&e%|)`(WhA%ajjPRbWJmfrV>6R37*YlcJI|H82{u3!PJ%iOEIY
z?&N>btm^)6{N}ltB~ulPDD8|xRSH7!x;<^q
zXw9VCFBd=p7V&Z}bzYE2C_MBYk`EnzD(z+%UdX!EtdBe*%`_tC4OsycnSn`VkG6u{
zi@T;()U^e42WfXP!Y6*^UQj2Zy!QgLF!45HuSRF~Cu>*Cw=H7^T`Re>yr%gYOy)?~
zvQSQyPV5UmqZ7A>d8uvrUW3`wvy7$hsjx8Aa$eCFp_P5lke#hhYD?rMlHUp{w+Yp3
zh;EYvxZQ-bg-eSUgZoK%4u=SGEeiB2$`DnEGVw_~q4_Dt9g(+*;8n1)^F0g2bJdNE
z^s~gOjQBy&YIV~T=`nM#c=I<0fp@Ub^1E4QA5**2=yD1)%yG+fH3lj=PVe(ue=<4}
z?P-K3GOZwX3-JrI?Vq|9imIYZV{1`&Vl7J9F6f`AEFOa)=(ahT=zpVEpnS#%Y3%^d
zhg_CjFr|ts$fVG>+di$7;?`A9Kuf3K3ElRfM~aiQv%=i_<`aeZ2fef+0B4XxYkFud
zg0j)FO6}|b141>rUCy~T!L*7e{tdb-08_Y4fR7*5VJ>oQB+lKp+`l$CfMGm7LD9$=
zu|U6NHSwlraou^{*r;M<7yWkGW$Eng=;HBU(V@}Hx634;%da4?G#^Nr!V?@uZ;Q0CW`JH5N7(iL!UNugMFD4bh
z+a0fX2Lo5kL5}YYDOmf4gQFvwxVe6G0q^CUF)=jd)&y2^wsr>i_}G6$o#zP+y+6C%
zY7sDG+KFRk_O-udNKK-0hQ+eE{R++XapDoSGgf{u_VK#kZMKB4Tc>&_zk=qUdg_Yyq(ltZD(iSo>
z39~48R3-}Xs#YqE&yBL{nQk;e0&L<`h+^f~b`#Q5@E+Dxir#(XZQ+j+#CkuV;(+~O
zJ!AcBFS}6X_|YW|c?=p~GaOlrR^{Z_RSxmZV^JI3d^J+f;3AeL8_cgr{+S+U1MZ9H
z(fyv_6CvRG{{6jllA9ur@j3Tbbiot3AB}oJ!A8MXA)R&rbB;?UZ@3!1f~f5W09Kuk
zD5rC-!M_=A%q@BNR?}w#)>jDQ
zX?y4A)(|!lgL5!6yJ$MCg(KpH4TZkyCy{ZkO{|{o&yAyR`bBYZieGQo!q|l)kA@1%Q7Ow>x`QW>3Xzjq70uw^Tn4i
z=;*_ORTbq?sy3A~$nDg`D)-i5?bO8%>n$V1wpNS7WXvrMityX+2~CAN!#?qgI5Jj8
zyiDby
z!J}5l?q#g(H*q}Y25}0Xuu;msm~#>DY<@TpUX^h(Vm9pFolGem9&Nq3G%zDo^DKMj
zwsyavWv@kU#XVDh#0%UE4(3ypzwR&pslGEH11l!ZH#B
zuBWOW2*A9O-ik=!0Uw*BtuL&=iP(gJ5R>ofm=($sM78um{{m}*zJ@yk
zFApyFDlXGK&}UR`^(lU1Be>tHrkG$KdcWzqUz)t}fKkstr;TU$O3-HWwU+yn1*6ZV
z2&jrcjR}{Rv@*v<#G|(zD2xUeE6;b5S%%}=&J*=1R((Sa+P*5N6x%d2lEP3&O|2R2
z+2Q5~+&PCUBX#88>_p#X*(kVE9%;|zBF88
zB5>Pmtwy~B`8Mfku1;-;t*0HT;c!8DIqe~3rBK?9HUs>H{jqwiASp&spoO9hemW7;C`$5jcZfq`19P~8<5YmUGvAam8TVoNTrt+J2@=u=^?yG?b-6=
z4ZFk{mYYvB$-Y!of`J=yuClmJ{e1ik?eavQni3C1%~?NCExlp`ypXdGfZ-yl!%h9l-x4D|A45Ya;hEfYaBy9JK@9$hw9wcTV9Ho{dA(BNF$aYvIks(`BQa@RXjp*fG|T8XDTY^FpXeepN+mh;W>OHa0|%kp`}*B5
zM4Wb*&!1*5FOp#Lzq*e)G!^W~6{7=d9lfP-aP1Y1CC(4MB8E(0Q7!;W8WRP}5Hs7I
z$rBL9;Py=XE%IajJJMf;LF0_#7$tO^OGpID6H`$=wLhFXphah|Wch(K^ead57%k%%
zqnO3<_P7m=7+VZ-nSqaYkZlapQua5+UP*SmI4FK=n?l$lL18-{^wJuDTNAGE6mgde
z6K95KLu2)tKtb>9eu3C>0dSXM3b4pYf<+sW+?cdIH8ic>;6OK0J(6$ZY#Lc>+jN)gCps;Iiu;|T`KxlD0
z6)!j6H1^ZKy=sB1t4bB7ijElTLqdyJ)Q!rVxVRWknUuN_AV}#QI4wC5gar@zDXc3%
zeA2v;kfX}=98*3%`5S&$;HM{#5Gq($gnz@JA$joK^(@;6=?NWRRGq^3GT_VOggRnF
z{3N2tV8f$;#vR^)RYCd-11sDskX?_u?KD5C!ujirCl1dFD+h>=xkQi@B)DxZ8LbJ3GQ&^O=RWdtlkxMbNwQaU_dNP&cU(|}aAkINS>
zGQ}i=QC|Rn-F6uiHz4sRk}jb-Dk<2{#YMcKGqP|}kYy-kg<(+)B
z4F4H`#6I_szlf&DBVG&rrFn-x%^W`@`F&NBpbINkjUjqlr_(
zJJ-~5Fq`*1en}mcLs8N;Ovu&AQt~Jd-4{PTXc!`1uhu!;(hf&o!gG$?T<*%&1H_Ic
zP9}dl)h%9JS0o6Y48Xt4Ed&>?X#I+zY?@AAsO~qZ7$T2t{O#G6qlR>4-_|W0nAMMl
z4S-xF354$6%aIX&0(}OzgsGp~np%{A6(j+w&_Q2O7^2QhjDHntTtJYe=@#9s!VZ_t
zJFJVsDhHYDmg-TcUSjX_BNDqC)%#8@*|hABdIZkkI^A?Q-9RsXqvUPrVhRk~sQz6k
zlwhv3MwM}K-)yc^jpI%Y$w+r@SeRE}XkGu#C{pZD-9&x4Y3y&sRv3?1n(s>?Cm9uu
z9X@LsQqFU}g*+p}S_}?2&-t9!IUF~UWE4zxDd^xKDS3>hBKzu|mMkP|f>cl#7a-P%
z8aT?W)f7?pnr)=NjRc_}Tvr4UMhX1mGz2K2D5PO2H$hWcl@*n!Y3l8bMY?tIh`ua)Y%nlpBCkzE~4eyPykemkQWt_k$baY8XQc4r6
zTs(2}l}v|1z-a^L35f+|_F)L^%oWhgLUR5@(iRS?bLfX)RTzyX#ZF)b{o8a71vq;=
zIH*QZvA!S%G-Ls_a62v<8k|JQee0tBATF9kf%f55IkF6MT|cWrz-#Z`(t2Ti9Y~9`ISZ4@
zMSF|-NBMHg^$H?_m718JSt4ab4Cqot`gnu|b(F
z*PHBKdSAx|W3OZz8H~5IAL8Relg&Io^niEk$XPVDcj&}Zw>+h=CCp8m)Ns!>fBC$$
z>V9?b=mxk!ds15vTX3J%M#`{J+c4zo01T7-+L2vQyE^z(a)+)D&I4;m=farxA6P(J
zj10Qz%OCeh4)LaO)V2v!4Q6c{kitN$EVtfaofBecA+q2|P?)43Dp)l^5&iF1nn^=F
zzW69ZrO7jgL+>V1DjHg9!tP=FDnDVM50R^P#-QsaD@1Ku2f$aBc4uGkT(CZO#9)Tz
z`l?YSu{C=84lo56n;D8xJ~=cM`nJGT=mXAC2OSE32oN~|n{H#D;_RU|Y2zQRJd{V6
z;r}yk1e{`*-#d&}`r=E0wp?gA)EV{K{89FI2;Rk#i6b(;@8UL78oX=6eJ`cjqwr8_
ztide4H$O6Ygk6{uSVNUZd|K3&WIiOUUv_T|Dvu0od^LEtZi!<$nno9O+#miH0<)Wz
z6;qigVq348^2FDuSr(JZr?M%HBQiwd&Nt5G4QvhbMWtY=goGLuf+jW&_&
z4012nrw_AF-?_K^uh7wGTBGP&YvR$~@egSmKW%|f_P2hrm=vFe7g^!3{iCp&qO)I%
zlJ9Awuqao2Mp|P~HN~%y;yM+PLj&SX2kJipvV+ri
z^uXT5+)1|dzN0X*#-^`ErLV@Nug0XWCZq!&Qv$H*7VN}eM1K3_A7hq%z4!lNq0xN4qC>`VwB4glr9-kpPyn7
z^FLWSJ}7>I;Bu`OT*6%7R$fC8tXCKEg92{XkA^mquiPY=)TcTb9*
zk1n2HIT;k1bb{h`dkkWu4^kFFJsm3rIFthz*Z>s<{eUY}3ZXKzssRN~71B-jk5&{<
zb>sk4jWM~&VgT5TQ>=UJ(u}@q)x=Xk+Oe%!lMkkY#%HDNUI2|A<_7~ZF>5?~2DoO{
zq?&RlYl<~8j?Kd>bAj43yr|kr)DXu{IWuwb75Itt)$=kseCoL)5FWYJ^WTp
zZ+Cz7*Z|%RAs>U@htq*jTWyg*`T%c4OJw6O)^37eVZ&a`jTY>cp}rYtOGk*G+FHkk
z9bw)R29KZ=1)Fo{f6c1VY=0Df&aOTU?d1+xwhEA?&qGjQR@+uelG(OS-{`xL8y$q7
zUn9rNs3kF50QSHQ%OW?(ofzPHsQ~MnuL}^#NWJd4FFsIDYF`Wv87VWb4nk&whMO_(
z47U-%GN~X_)4O=|i+)~S?oLeAR*Fk(5j4FL`iX{2M5HaCE^3=hyMK~fb%i74CMz)Y
z&4Q(N$AeohRd*4gSp$0gy`QuM5Wp~Q>3W{&8;!O@lQtbNBKR45(^_SWN+)ivOTMc+
zn9cjGK1Qd45FciW7=)mD<>N3pRH%dBc#)bddK>Aj)14Kb&Klt)aKHUtNS%O);@ay)SGE~S5;wb^$+up02Y
zPrG6pguT~xl3Od85+iODh4ypIkMcF#1!W}Y7I263r>8P~!*ZG6@MWoGe=dB;QC
ze9)-csB+nqvU$1iAp`pcPml)2Yw9rDOEOXX5R?fCm=v0}eL4!y5ORLHxM&aGjV5!vXJEIVJS?qMXi;l96YZW6R93MbO6uq-Bq&zLi(3Eg
z66_G-_i}x_hF-D6CgTsbyIA79afO>9?!mNBKm1^p!oIHFh3`CZbqSMH81jCRGUMaL
zRQgQ)))en)L+zh0f-Db!o(&`89F{R`3Z;b50`K|JsoU|l=1Z;;8h|x1as4#zNQSD?
zqZNP~%^Z3gBh$S^oNnYXl##J>;OKkf9;E(u1IgE{hUHHhFmPrR&HQ%641Ht%yzk54
z1!Lq{n@s*(AG1U}fPJF(&4a9`i>4>JN)T*x8=?6+LQR;b(4wyR
zBTWufRK4J~vkHu#suP;m?fIj?97J4dT$*R`Y+)A@=U+79@n5v;UcaTUMXK##2cB>tsNp<_`SKS%t=8{~11x<9n+n@qP7qg`@Ux
zS5Zs>abCz0_xs41ZS!ly(wS-hUKjH%M2sWaYK2mF%Tcn@hzZt4AN!lAuKyX2Tu}j*
z<_=5!Yo2G0j{hxBT9>3in(u0hbRd0a#~^nX>$}ng`X0z{KO#*cOWy5MM8nMBGybIS
z2M%DCRX${j8pngm)-G4XJ$}d=(m!u%m_3x}9$>JHw)*696AKQUKWt
zZ1Tkzn3`oklG7IKoo(5^j!zIz{WsX$H}FqlH^0)OydFL?nm`U&H1uk)>1>KL!TstA
zq+;U}HAADxoNW{g@E(Evj!srids_HsI-|}ZCwqDc=$VX>*+h^(*Y7~
zEnjCeT#&}!JRGyUTGs^TRG~qlN1yrs&d94*$=Cz(@xf}
zgRY=bvp$cJO}?$8Kx$~_Yy;Po#=$vc%%9a?$yG{gvl+jmZgiR@7Q)!iHD0B2U~XYI
z#c)^a4d0h|9qpP=asm8mag^6{y4f;*T`qF_+=QXivYlSvMuFez%|iA)ks5&iD2|_{
z;5b{!MFZe;7;!AGaf@1MuB)*xToM@Ka#;1Rx3Ba{uQ&XXjk3jSR&l7nXVx{9e)?{_
zJ}f$$U*+mB1IeUon&bOzQ2AuQLtx{iD#aYXtBGbh%PQJuDgDnX0btq+u5Lmd$BMPR
zlaH4t;tTu&aJI$E3)r*jH-n9|
zc9iHINE67aVY=I#+GT}v_7Jt0+;(E*UPrB>LjuJTYQ^g_Aa1n=W&Q+7J(K)9e&mXn
z08=_x_nO-0M4S~vKoFEuf1=(5d6At()a}(0gs|;=1c5EKwdri5gmpY6#bv&R7c)KT
zVlPbt-g1CSaM~`^Mi6Hb%EMPF;nAw~;*;ot5q}pu*q2S&X?Kg2{5U|5cYZoh{%rp>
zvK^?sPrEGA^&RkV+2Q(wX(4%h|}_sRY}^P5*ou
z`bG+e;(S_T^=%Pt!jwANx@9LnOf>lPdZxOx8mz>u9g+q>%#YFWtSW2GOGt@kZVV75
zbu&nC^`D%-lDE50QxU}Jnz@dGryD{7=7nO
zCfezmB{XRt5=WCM(#y>x0|jK4-RGbmNV@1Lf+4jAmFr{2Qy`buhX3>~r&i*`*N7RX
z&5L_MQ1KXyImD`pxO+ir63ml-W6&9iCek3&)1m|APT$TrCd0>}Vc)0SJly|+A^7W8
z|N5~J$n<#{InRo|Gt$$G3a|!DHXPINH8+saBZIuST^NEBo|iwDxmTVjQP!rb0>ZIR
z4ZfjhOC62z0hg{-Zp!_tx>Co|cgnY{(Lh;OE?ARnZ}9Ij<(BL2yE(Aes!p^mp}8cN
z@!}oYA)C5mr7gb#>QPx&@vqM5Wy!ddV=cZo({QP{xFxDHgKK;i&n#ku`Xt*BxsXJW
z=C|eCN|M(&IBi)jPo&lI;}*B$3pnxDQuS?>yYa@BA{TsFruaDUf!+F66LLHKVB8ec
zB<19EbEXNUX!b9k#bed64Up*;9eb2wUPoP?s{7_?lmq_tM4tEh-i$I!hl0Oo*Mk@#
z{P@I0t`{F1;(PTcY&d~6g+l#MKdKO_fd8^|Y09vXJYTcQzFg(as-a1u2M-fYM>Ter
zUf%YoL8{2@X`~NHRMs5a{hNlp)Z`abZ}T!phF_JUKn6En-+91pUS+Q+t>es%-pW!HrPGtL!E?O^4&H4G3_*gK5~8-%SIX8;;TYK%wI<6Wij$}A@yeM<`jjoG5mB^8)G?K*oyMsUUF{J~~Vc9Tj$qAY1dn%B}<)
z{ANj}blsf<3~u3{&t@7OJ*`*QD#@TiP+qe5@e?u=H@D#K7RKc${z6|+b7x=pRFs}{
zZSrIMyM!%!=P~@-P=C190Fb=S-cQXLiBg6O{D@<`18(|s12I#H(@>t}k}8yVnsx>BcaKVC>drp6sOJdy72
z{~oK_9{k8vPusSf=f|0>XYXd5m2KxnVA^y#;X8yGND^hAi{XUcWi4&R?K>A=tJ_3X
zq4l@->jTEBX(pJ~zH!DGVet=hLdeNSU~<^}BQNlWCv#%K3>-mZ4iEL8+%t#(rEyLj
zSk#;)De?xnAQYx{OPzkaQUl82wafZ>sV!V1AWbTI_LF$(t*o(93Y`kMEnnHcqbRGk
z+;Wb#B%KA_l^pL3AItClLjlaGE9
zs$)J7pGOzksdgGZWqkHvusDYRN2Kocas)@`#?#u*=oMRg2ABy3Kgq5n<`5vmR7#ND
zY?QS|cci||ky_W`KqluhLDi`m>`$jc4e!Z4b5;I|kJ}pzzsB*@TB-9=R-MNIaJ}SG(rA>zM~7|x_VIh4CL}6VGRy#E@p*pkREv+0ylQ-$@$RRCtG4WjQFCjk1x3{gx^t$!fix;3&f~%
zIGP6p);3JnwZ769Z#C81mZsg>G(zm;OmVaBaQT6(vQOLLjx8!5u`x!6wu2Bfc+COfc
zG(WI^s}M6p(9`wh@5}AOs>k;}gu)ioRW00=T1fztJXgb@X;mqy|8unc+aw#2$$h~E
z7lolgw4-kdH9@yU{sH!#QIGRR0IYCdVM;qNxKd6h$d=bW4?04ru%%Tx;>kb?eGWH5
z%lI$?Sx_~D-mnIfld4lT6fflF%ROA9ZC7z;V~a$|aj6k&;c3UJhiXTiY5Y;|_G1VE
z@AYhU(}*}iA4`oW_NVI!mbg=Gp01MSWUXe2Adfb;5-M*NG;CoR8gx}LoB)38iF!6c
z?NZcOX0a+4bzQ^sa!tlx=)`85N~6>>Lc+&;bFI2IL1@BT)4IE_&PW`(&OA47H!lC`
z?&!$$?Kq^!XN`A+(>0_;Pp|H8eu2QjMk4}IAVxB7v%Om3x}zw~-W;=N^KbJ8p9$W%
zL&)YOcPk48y4?XF*Ix=T4KI<9)=wm_hKxgMu1_FFU>%XR)Dx*oY^9OaVUzo*nO%-l
z~xKWp_XvAJu(HIQconapLyyr>Y&0IHp&-kr|~*A#G~m?4IK$onKjGWeqMm_pHi
z=S24RQoQglpKsqj@5BURsfr0c=?o=(xg#^MgBSjWdtoUAbX3Lg)HAwlW#l#;CJW2F
zc-+^`To#^yd!P#G8iYBVGWB1##}ufAF+DDH&^U(lf<#$b2u}*7rxZ85U>99@sZy15
zb~#$$Z2*W%JSS1Bk6nnB(`F3@(cI3pH3}sA^iS7om#P!hB{U|=_P`BR{#evPm9uB{
z-ABtky0hp`HX}*#YmVfNo&BH<0(Eu2mn6EVhdy+#fgca^i)TVwGk^ehpa;=DD~@N!
z1i>(;1v%Mg>594S2SZ3y0=*Z7lr%k8r4WEK-W{m{+KRXT$UqCk0=rH^8FVojsXdEz
zxn2{bi60p=iAZ0~_Q&$rTD_ZrC?pAR9pFS-p`>e+;sd~PMZPodzo?@?zSPnkvkSF_
zNNdHII!VX4dZoQSA42#ksEn!;-#GkmYKfOTv9#2>F7u2>YC>CERUX&JV6D~
z&gZ*3{8m*D02G&MT$C`ehSzy*Vs^0VZ)Worr;C!+o=f0D?A(5dsgTc~h_{@GW2`PFkv)MAU`5$#&)^6DTUT
z;gi4PCQk*&G<&3)bfWDVy&_5T*-*nQx)oT*GaHXX?VT_iS;8-XU*};6-w;gE;hrz#
zcjwV3+3NjJW!o8OZY|t8Z7J4$wq+UAt~0*rM(CCQICE-p$#j;Gy(iaL$y$IBBp^+y`iGjjZ2UNmtv`?%>Q5
zuZbfHrfSv@>}eAnZ4W9Kq@mg*j!BMG-b_f!8>AFcKT`!o8<9v1`3{_EWeR9Nx9%DsfM&Rc?-b4DcfU
zK}o`Zu|3SaJ>9np!{9!0qy9_)Ft_#;{&YtjMlvk^!O`W_iuk92+pEkPOI{d~_33-6
zFQG?voP~ju76T77G*l>-TXScIYOpZ|baTpd%13xBfU)t+6r-=*q&axg$2Qw4@_D~%(m+oKk=4YdYVsF}NKR|(R+}(|I
z#vff6nH(;YG$W3*eV0xnW(>K{)5Hw?>|hMI^Wb$Bwnvxm8mL5ujv0$&~U#LwbS
zXvb<|Yn7%bVe+LLc1`&|^*OMGLNLEqziI7-4#s_Voe3_rF~CyUv+zXaluR?^IoIbY
zXV@Nc(v+HEa2gpg)2Mbvd8yTzR$^1b#w7e~4lI^pw)lWIg~Q`)vjS>vsk|^5_QtukmrSG_FFN6(xtiQqKN`nZFii;N&n<
zhKGt3`ION%+5GOMApBA7>uj;7o-HVJrs=-eW&siey^B
ztnm~@YeGBbk+ZCI1n7#4ZEgK-+%^_HXb)ErJ=~6kY5L$zfV%^N%ZNK>dHr&8#Y-B*
zZS==sT!>O1&9Hnzm1s#Y4TE7$1|A`paVI$`2InS&#jehA7WmzwEWu<<=X>_J5_T0e
z_B?K!F=<{JplV&VUv5{=&mBM1@m>MPJD#K4hl;&;zY_+xn4Q7jESGUeyxE*2!C=TJA;R7Y*)j8Mn*yq9-Pj%A48rj%d%`-**Kwma6nWB)VMfvZ{8Nu|1
z2^wq+X`!bXtzsaPr8ku7x`kAx{Q88wB#bLcrg^k*`ffDJPBj_={SnA3s72YWTiKfxin#;;A}f&Gsl*gX}WBUwyL_
z6rkX<(YIs0AYu2)d>n4**aN3XjHEogDO(w@ug7ext%R%$^7=`lDb>zX1S3vCXb)1#O+^Mt{(W0*_0K@O7HhHwC@{z3(KPe~xjrwsPR@`OO6pX+u9mFt
z1~lrrEH7!OeyEk4tb(v?!GI+E&FtgG{M=1`UZJYRPv~iu{dD0zM@a(qMw#%phwu4k
zEC#QmF&&UKp&)jSd_T!A7I3%sNKM~oeI>*}0om?lHxC|NDzGUqmvKA&*PtH~6o|R%bubZhR6dI8$%E
zse>~vJp*Xu54{9uqiY|&wv?ZXMGu-CQS;gx9fr`x)pPc@KNSfgq<9VDIezuGk-u<_
z6AxZrqsVk;?|64kXgpLOKTA?^UJbCiT@qq+Hnarpn0xWG?c-|Bji}8G2yO0v7{3NV
zJ{^H&_z}uS3SP7S9Pt}2lR@d&5ie$T8{9TbLEN0KNi_mJsAwyh!4RUpIJOEZLeTf<
z+zKpQMa$@oYotQWQTyyeT8;Kxt+@s*=G>Fr~ofS&{TZzc2M{U!s
z{(Ch{Bo_gVG~taMiXYzNkddXi5LI91VPwma)QYIo$$h$`3F~-Q`)?p<3t=I
zwLmjd3C7)L!AIaQ1aGC|BtD`J6*q&ak~I4Tv7O@q)GI5@ko#K%1U7gVEJtQP3VYQ$
zJQ{?Nb(WEK&0McV0bb7r+6ak-JL0hhj0uGZR5)Q~tmnZuW1ziQdpRDxWxsEPP5mxn
z8$jmkF5-mtn`rmNF*BGI1IKEp!gOoJ0v$h{xG!XHn&IuCCK8#Y0zA2Lw+`e1mzw^5
zoHhwpGtJ?Irmj*E?BC@^C7c@dVH5i(su@6I2=|=Q$2kgAj)N#~U=;le)h}5LK)>0`
ziMaeB6$yRKM2UyEJ5Y&g4~*+z9+U~)>?3asR8K+&2l?B-`J)603yI3
zwU8G>TZ9SE?AKVqO``Nrf}osrf7LOacKeJU=Lg06L(Qq(wMGZ@eODSYT4}&hzPgAZ
zX<%Rrx`sN0YZH_8q^4fyOZb9n|M8o4gd58uy|FBpIHy?&^;CB+ce$Td
zvMt}yIhkMiHw$9{S0+&)z|;TQO9=1OXkDFA%37eUP+NtosjL*AD~+aseB>`@9TzT~
zEGD$d4xAL-i}Z0J&A9x+DWh(vJVtaV8El5igH*1skp|Rx9q#v!SG}%S%~|}5
z(kimD>>NI9B$Tb&k3ly8BJITAh{B7L8oFeyoRDs=vi1ngSRWv#6h*?!CZ&*UoO$PB^(czX9^_+$D
zs73;-&?G}EVbHsAchZtP-SK-;h$rG0Wcc&uyi*=Cvr
z${qo|UAU9_jIJyvcpa__9Bgau#z-tlS5)5Qt0}Snd4}#!uXL%As%}U`9j7jv#W&{I
zT*~5TS(O(!Rk+1?=NyKqFv-PkJMQzpoXLmt*-BEerwmg?5H^`I1n*#-aA)>}Er2a|
zq^23Tf)_8IAmCU{At4bpWJXpVk>-pT@T7sr#Y=tDf~!7uK@=DhQG|-8F5pQFIK=ww
zOl_%WTFK4@3x=*ZE}thPS*NCc#n22O@0*pxk>1<9T-u4(JyN;(Y$BK8iZC&R_l#~Y
z8raYEaLE#B2r(XeDiu(#(7)4`CU~iMunu9xhw~W*VFM%B!~$a<8T8NBR6WxSCBQC6
zLabw#1{>Mo-EE=V+0;o`x>ZTZZ`GQo;DB_KGdb{(psz2P5pN)!RNU3YjBV0+7pWVP;&~PNO4SLROd(Um;p*mfZ;(8H1g+y*cv4IJ
z6hHFge#{Qc6Pg&y{g%X9F1_5N987a`OkZI^vd)KD`Llk|!FuuT30GaxrZKq#g%3U7
zp7ub#ZK0pI()zaUhCVUKq8r%!5wzfaZ}x$V#?jI(PvtJ`v_$RMq*%EhT{Ni=%9azy
z^~1(R+2pcvkRH9fNge4qy8#XalBgoM$!$e8jHl_Uaw$r4x@gxbB%RKXSVt`M;K^7C
z&nUCmVNqs!P7O8<@h@{d7-JW;X&)TUiBB>HxH?&33L>Jaya>N7>mwPcjD&tt$xoJD
zJ-S*$=qrcy3XSKGYV|%Q#|l^0z+UX=lDNN~Hv-OpL75}85v(~0LSk1uR&38)IJ2gkRKVBmfCOFuC%p!}xB}DH4
zdEAgKi}30MDHv!D(JB~y!ga1Sve5bf($(JdL!Qaqs?FmF_(WV@bEKPTDLr{Aub|@3
zfJ{(*iz~9wOoW@2?cQ7U$XEa_$W1lM*&k+o57nP%A{=&;+Na7k*kTxs^s}RVy?-R-
zvXmTCwHNYIBQ4o1^7g=zMpR9pQBm%DpZP+csH>?UD%J@zJ@EEO7sC3=x74;{%*DeD
z;5&|*xvhT1j9Bog9|$Bj)1=L$R=s1|fo#;t)SO_H*^Rt0Mma
zQ(J2NOeHcYD#MAZg_LZ|+^xMV?bXi8btB5V-k4nl_ql+n;ZjJ06e{9IK3H(TMmPI*
zqb*IOpek{?+Loxxa9xrb+Q)|_?InN1Q<3lC$82li=QXh&9JY(4vpn9^oZh6d{#dVx
z8fT|tDqrv1S(zl|xnO5J=&EX1@?k5mLx4)T@Ig5XWC_ik&j_Y(qI0PNN}n8jy)cgdeKNokv!U
zCZSv}hGyQ1(q=)C8?e598}l}5x3SQ%6+Vlv2vy2^gF>QV;!6$SAGVCSw7>QpRpuqz
zih4sd@R3F$drb)*;Z;+$y|JKH#|pmMFQfJ1=6Ej!nH-tq2o~!7&Coh0Z5$XD2KKf&
z)eKcsh*R1B%{-YOnJ{}xk*Uq!;*uf5NkvVEibH&jjL(F9ZuJ+ivFdwU+)<>OGW+Vo
zS%Tmh^r}PV7m_|0L;6pX0ml&>4tH5$Z*wdWO`bYmF$9iMYUtySFu-Mg+Q&`M_~#Yq
zr@dof%~yz~E<7XTpL-eY^L?rxi6u|rr#vdT>?5#-m-ftX7F>j2kU|M6}gc4-q*
zDKwL{5G9*q
zgF0|K#B12}Goy-~+Mju6i`!qmQr@LkdYSV0il9u4ENL*A1$!o-KAAlQdmR;07e?%2
zs`VijwrE<2@@5`YnzI{62__0lUZc!`9#;7a?KVLidt1+D
zz4;Uq7ER3-p%($R)$sq!`-8e~0f+jpaj<(Cv>eJeDo-+s(9DlAh$}pcsOkFWGMt01
zGc2~D{!7fXWHYGXnas0I4JR2TeV&eg}IiLjwKf{LoPeo`j0Zo27blN
z$8f8hi%nQ|pBZ{=ij6rT+uXPGuMpDP*30tPwjy?$6bF7fg1U0Iy2noqJAUV?zi_>x
zsHo(UT2tJ+Zeojs=lnW7{193)*DXh_pdcU!Z^V0Q(w_q
z98pL%tq3i?8W<_7z7gf+G##>fDptro3KaF>K;){P>=1ekfGCL>K3HiWaq7d2IpvM?
zt)K@45bQal5H!hLl1*p0Wg`^y!IvD+bP0m#LvJ=KKtp(t=b!4+HpQwkToT7B1T^qRPywK`g^5=9;P$u)69{M;GANIBn*X(TIJSCog!QdsIO8L6USd65g^;FAjw5;A)
zz+77%sjcqD{*w4d6$Fe+$8zgp;dEKHu<;M(&Roa)HHnVPEQ?|yfdRjJwIAr-M=v7R
zqxi?Es|#|;P`z5d)X2|pJkqAoSJ_v24^xHoK{Y|-Kd+U5
z5}HFJ<=_EZGEA>QZ&GPMU@Ic3fSf8VCYE^rQ|!G$U!N!&+b9_WKnJ&b7{K~{E=Q}x
zgkIuwX)z)#d^fM-n}CD3rp0>8(gsNiim~{*>0VpI&;mdPDEC1kP4gj~4y+5W3w_A8
z1!?r|2;*C){hwqsT(QB0q@!E9I>T@Wnh0L^?VMB)p6&e)2Da0Uu>QZYI
zO=oI|GkAvV6;Q2*!1~vM*ml=rgFRO)wbPO(#_tZ7=lagmW5ZA`S8d7eU5GH`DeZy9
zyg`27k}kdUv1yQ>N#6T9olVqwqiS-|=YoO=FTeDeXah!tV&jgeJ|#D?LjEuRFbPl&Ab&BivEa*%r#wN$uiNkOH)M4GXAQp
zixd~u%qG#d6x-C58RN~?q)Bk}kivepSPgmAawUKRs*KwDXdWrE`OLjb29uvi499*V
zVLn>*HwlFkW^!Revn4FE$JNvx*yU*O;Cj&L8My9tQ%wD{2WKVfXrGO^5fCsD9o
zadALzK7a$~YCV9nsc6FeEm^(;5}3($2<}0yep(^APL|9_@K`aUQZ02T*HgBzl!W=D
zQ6}^F-n39sz#O0RXeLoF{A0&;fXWE3Yc_dwf*nRpGfbBts;UCjigS3##+PpmdD}t7
z$vQkt#d-BnBouq^2%wBReHo|n97<%urW~0)fAehsn)BO5Mtdkw9Aos8o4rj^b&3(f
z{0dWeH~buqwZD9uRvAYkX7JND!Xzkp_x0U{2{0n7ln3PBQ3L>MiiF=D*6J`3Y`;hw
za1t5c1gA{`0cT!(#`JkYVC~T-0$bVQ(11q9n&Is8*_hD;H!#JQan}S0H*II$2_NJos3E^n?Ey46nb9`Phm4jvg
zOVDxrF1Yx@a}pDfWz!Zp4&~4!tXOs2=h&fkc;AaGpu}Sm;A|26>-{$BXH(@t-!aa}
zXC->!=jeRLS(S8PbSW|--z=|@vwx{gj)_n4QVWY|;FFc6RN|||^iOi9E4fsY9CJ6b
zP4UAd!m(wGi*Vu;3iFkeIz#GQOyZ;!=>_$1z!|!PToi6={RBxyCRln>I^yRY^{Z&n
zq^HNX^_NJlqsg#Y+{rTVmRdf@GW6$Jba}df`J%{-vrI80egVP^3Ze(37Jr;P$)U)A
z;l?Ix)n=%(7KF*cQb%o1WIWn!kpG@HjE6kJHI#Qru$4F4*4a4O%O~gZyC|)Qp+uK1
zN0W(btB55DyjF-QpIc+ep68?d6${KqAsG-?1y)#m43?9MG7WHg^MTD#(fVMKofu*1
z{|5A;agEDlygbJc)$lFCNdg3g$PHJz@?Mk_DVbdoPn8n5_kY%ZlFt$SCiQ4Sy_6~;
zG|rM1Dlch-eS?qF;VP*?HYbjWR3}T5-RD~t!X$LIcRT>@1=ZsY8F9MtSpNL(4dBca
z&{q6ggL|)>X%EQw=w2~pu@;Mhul*@A@K)wklBw?}I=8-ld@YDJb)m^w
ze4h1HHz1RKE4KjQ)Cq)NQ2NUV6#lf_1cTzkZ4uD9ZL6RHvTc_W)OBpR2R~iz0}0V(
z75{-95N#aZ3LSQ@V^(R{=dC~$QoU0Fjkwzn(VYW6=h32fscOv!BwR?Hre7dWmae&<
z?;4r!7)b2Fq)nSkw{n@w4LoasMp63f{CvSVX2Ew#!KI3zBs?-SOJeUCi%E?bHAoXE1J5loX`?{qn43Bu5K4pgl-
z4g8b6V_H8y>l5vrpjyV*IZ5RC3WusvEe#_gnydr&$aar@;qNw?5)(*uR|z5edvK!e
z@cUKZPIzB;WMg5BlZItO^GhPMJLC!?&~|xtpF5SEZ3siM(H-bL4PLH!z<&3azz#MBDr^Z;?g9SN|CkD70$HM
z{2i&P0}%;R!b{}4vXfP`7ezg@xlRlmj&qEFm&;hMe7hj^J*pv7qp(;e{h?&2&)pNs}w8c!m6zRi+Hbg*LB(LrFV@A9yRKVs%=MTYds-O
z>!~Z|8`1lWqI#kf*Y#^wX^!GFx&qHGB)(m?xBaMRlMP^hIfFDn9#Wz{(IDFu@IP=k-M|
zt@Wn@I+hgZ7?|I4c{-4mUt)iH4=KPGq^B#7cW-&5a|yw={m*C#-`)yY-Y6`Nve1)#
zF(*M1+*L!L<((%Yp!cz#I}-tt-GdXksZ_1DS3SlCe;E#hRO@>FLm=j`mAe&iHJPc`v%g>672l*JEp_I5tR({#0&1VRri2)
zqXf}-$r!8d$;9yO8Tx6jlFL5oMcV+sK=ZVR
z8`R;2^y)jYw;WH>LVGU_8*uJ8QCtEL8ZD}U(1mJd&QUUgmgWlBE{iqnV%i2ZsSW`<;R^3vnVM6pmc?e&R4flHd`GeHXc{2(h~q
zZUv`v-QcixiB7%hrPAW6UTM%k`6oEM3RU7fU!Lt&S?yIlZ|Po%HLL}nkB$e7?x32e
zOK2Vn{tp{OfD*IT!*Q%fRiXO$-ij{M9U@r;o*XVLD~U*B^wzlDScBVd!%JEe{AyN!tZ_&LLKPN!6sbVbp-QQaiI%S{LwT
z%fBl=jxOn5C2vxCZs9ZWbXlsZvs@~*R7bj#Xa_1x|7GX;){A^4)p>r^Vl4-{)9GPI
z(4OPE>TF410nfn}BE(NLgvetZ8*5-}tdWxrhCNpGuOm0hGl6_PwyEYIz)Z;GR!
zl$^#gl3a|||9aez{Fknn-vF!3pK@OTQ9Lr{~UV{(G6?#t~)Ly>6S`E6q-Duq%W?thYMK
z@=e&y@JOh}3FAdW!mcpsm5yLY9V1*>;k*$%c-Q8%QRB`3bp%g#czd@3u06iV_!^0y
z?Ro@V^Ja$T0S!}G*7Ma4Tf3&|Gh&%XIJKoZruk$a^leYsD0U3aY`hG1?$7VpJ%74`
z!NWwABlRiv1>G#nt3oAy0i?D&Vb>p7wWPf!`pU-3QF-dSf`foqZ{n#OsJ_AMk;Es|
z`P$@K;-~IG<9P3}O5{-_%6&m-5DF>c7xehg$}fhza;b1tV0;F$*4Zo6V~_3^`%;HW
zC6?aFGZJ#uKe4Yji8_rx5$@fi3`dh;TsEHy`;0jQn1CA?P(u%|lvl0GS1*qsTLn7W
z2!#TH&}~$Hm)Cb#IHqpOfjWKyvDF(E>gBx4oTV6tUNEtzc53U1R1mTQDK)>g1H|;H(JMl`Jwd
z38i6#eaGPJhOPVBA@;-66}e$d_6d`Rz&q6BF#QJj9scUC2p!V~Yq#Uv_RKtCyfAK4
zm3v$wG~NCDcT_@{J}c!EkQ
zop(uA>Sg0o-+1wgQh9bnCs3aXim`xKmrsbjkk{#FJ37C#?ZjO}m$$0zyUc!Kyr9e~aY;&HpeZyxu-baQ4OIkR;dVg0YzjQgV7KrW9L4Eh`m)8FDb;>yd$T7*}
z)!VX3wuJC8B&$4fpPN)BP_R_9R}LENxRNKBJ?*V~2R!vlRrJ9d$6&JPGyI%M=Hc++
zCJ(q(&S%tjZT4X|Av8TQ*A%nO^yGpd`E=xhMCxQ#e%P!w{D#xRf;!o!c2)~f4OQ(n
zbC+wzjuz{m6w@8!4G#wj^*-X+Seq2~_Kn2yKu9@#neRkuXi24#M;khx?;9}%cv`;q
zRi$>EV~01lVL@S=(KMb#$P5|JNGma)5lsuD1)njv%Ac~;FmE*vFZsmCGJ*b|i5Wx>
zTH=jY&UaI_sff2Y%`-x$v21p9ludgN+}BN;=E?Icw`#hZqvC*72UmRjsEeek+e2eb
zzH&4_pWq3DZtp!Q>gq&iF#fSlk%X^&=oc>gy9Wjp7u^@M8NxW|)*~6Fw~Xtw2B}3$
z!qSO4VA`#bx7h+NQFexuej3meHqo%js&R6LMa(=2JHW{UG=YZ(&6vNfa4GTy6fD@Z
ztJ24eYpwjV2CCq1VrXr68$R!%oZ@UDybvU2CFs<9od+6L#!tOU`HfrY6qc~}0MQ`W
zGgw>+e}qSB=W;~N#p#ewEH)#usZwKV!O^)C&fR%Yd!`O9w*tV%1S{GBim^FYMwC6`
zJa*CEltBjp%@XP6xlp1^MLeC=Cix&PKnh#V-pB-ij8nh2(BeH_eZxZ1H
zQ>e_pa2|W>mPtxueWTrUtPN5J^ZV?oEjmZ3o7%p-s&tbe11isIla+dV<8Q=Z)V^QC
zZ^Lhn;Nv3~n+4x$z9IMPO~LezyOl&=6BmOCR=u@+gxw+Vh)boJ?@tp!^d+8Z>UjwF
zID7<+?NJ)Z?>DSHS#cS!WqgNU@Rm&Cdl)Yi0kr-LSOta>808(WT+6Ky+Dwssm#0lW
zo#xj`c9#bYNlk&m6D$5`c+eOD)`M8a9eDI~`iSBjTn@#$I%R?RQ(Yx|O7sqQTc?$K
zEiaZ(*68Atc}Sn#!*qKzx2K4W@tmA3IlV47&0^YQanLStIHfsWQLDP>U(R0*Yar3_
zQJk9Pem*+%T3jiJn?IdsO>LX^<)D>E@Z>H)WLv?1u8x|NrNhlJn)Clc7WGdFI5=d>oY2(oS2X(vLqTqam`
zto}hmo*W4dtN0g5+3<^nGv!e;ip0JCFe;Pz85T55ZE`hB}t$l5|=Yn`EL`|2(^3U
zz!C3j3kdLBkZa?wsE;NHWvbptqU$vQ+({mtQ_b_yMcw-PsUa)@E$PD1U5n;}Vvcf3&{fZ4+F-a;_ms
zOc@6u%?-?>x)*R}-V#sO@}?xmPAF>y_O|8t4)5wz*<=X3$r6IzFuei}94zL%1@u;z
zaaqCcfW=uqoZLg|0!^HVN4&X*HZz2K0+jI@>)n<3Uo?eT1wI2FDK=`O&aZ5ri5*`x
zM)Ek2+q7&nu3Ts8Fd23o+9Vn#t$`-{_tE#`_syV}i8_?61`Jq
z#2fc{atuM-k_}62-o%)u#Au)314aRD?f`Ygo*;SQU(9~28^D^lGuk&g-nL037899u
z`@hgWm5RIzSE}*yTr{1)s?`AM9=NEH2Q=Q0elRPSGE}BQa)rYvUSTls*3;onm|$DQ
z5Vi3q3itK(B%%jkfQW{DjEiS%^pY7wgH3?p;IONWzgr&tE9xK2C8Tyxd?cIKx8eedM30myGPpg06?98`1$EQb(QUzs6jZDpRn6K!ibI-A)zi|3L^ep{As6#ZqFP`SK
z5p0PNyMRh`sQ|ke-qwbx`5TEx#QrQPj7uh|@H`#0k&)pojoLnB0lNsFi`6|V^
zCGrD`!qQQ3azAxhL(hYTyCggrYAhdM5TzuG6ik|G;4tFjyvHawnqiCHL~hs!j4f(j
zd5YAy%*BqGlhZ*T0$SPoSvik|(~7UhYoz#xgI&$Lwz9b@WCpTeH1E(zF=(Ff-a5BT
z+rdRk;)J&Gmo7cL4`f~#aq6FfO3-Dycs};mv%(IlE=-Cr=gq7ESZRF&K|d(8=6L&Zp6p#g}XzDV1RT(8&GFA(ez~&fySSs{;GKXN+-(Robi*K
z2#4-2cW0kUe9D(%Xt4xGT0}9@xlx8CFpL?S_V{NrhFKDZFyjr1Tdo{+cJ*aDZatER
z&*bhc9Xs!{opnUlI`?a@=QsK<8XCKDkYN_8z8i;FzjaKsPiAR*PL@@CM#FuhH|GQ4
z?qh~q(H#Z*K#>q
zkeoPrq)I3Xkp+nTkx)d)@jPrHWZQmmlLC@a8fa&%tKvka%gQMJOpLE7?IJ#o^GI+b
zZ4^G6zN;4OvDl?Ca%PUU^i#*aDHuV6;;gWDSlpP|msIZ$?I#1r(a}M;b9u4Lm?V+Q
zlpl5N8oF*ya4?3@ji|D4tyz3kWq9J9M=NptnWPc@^VX~F)5S@U91&>C^YIC3&JgAG
zuKB=H)V8c*dU7+Y7(3>aq?CKPv1jQfaP#@;LuwsZ;ok$yG^>F9;amC>3Q)g6k@WfC
zx4j>^1Q{xmeW$RAs*9$uwe{u)NWb486;(+&euj0#nI3J~tiKN26wKxVZ?WT-G
z!(~|iB0*nO#{sRE)>QX)`nt;)vGt+1MF&CjdgScjFH5++5L_O>R;GjqTS!1k1Qk#Pyoe$)@5)2P!51s&CY09IQF$(_p(
zZlm3a?5>F>r?#qmECT|cEvlD^YlMp&R;*U!&naXDrT5EYb#jnpgu>5+qBJH|qj;r+
z!&cOl#k>K948;r+m!fS|YA=OANMD!S-{;FWuBB+W}v4+b-V3zs^KlRMF
zxxprz*qk^-fl89I)8(Q4td6Mu@wiTnESM%9$%p_ys@B;!y#HCHb?FWp({d9xvQ;eo}(i`2d4tzKo-u5M4v4KvVTyyE)iTPY@Hw(
z2)pDoUL6ssXUR3=u!TPjxmVR}c3ssVG2TB@TVi7A^RXd?0NSNCu88kM$!W$*O`x9%
zVbWg}9bh>}B$3|IFfA}p%y;mi`Qo?qdxngnKL(ZSHJY&3yRfLUt$UH@S%mwJF3aH;
zV0Q9{mpw$MKD@ep^07iHJ>c%~TY=-!@%q=SwbpN;qO+M#yj3oMGu~e>kMzmXN->7>
z(sAh@(yxcxIxlB8$3Ul@6t|A2zx2n$m)mjKNR}?R!2@%VXIcXcc1%a!L*B+*lx^
zUFC98PB~UiDMTH7p3bSLQPJxi8Q%RiyM#zOFZtZaVTh^6y*h!9LxVbz=bvWkye1@C
zdfPWDTxqs-3vgiSz1$RdC$VG>)zuSHG@}mSE~dCIY1*ohwk7#lbqWzmzP*qfCKKBq
z;}$NAeycdsLDecvizuq*H2pR)0||Zq5bHo+dH`|$`}~O3UJ1&nQML=J-+icza!U#q
zhFMIXU0UQ$zuaS~?~+xX^xe<{QvP$fp@Q#DVOzC)Y%W}_VNBT
zA$hQ|WSjPK_i-G7<;LhJy?((zZv1?s9?5Uxw`8LWhUYLYo3(0FJ@Va87?q^XJq|v;
znF&F~da!cYvv;IHRMqg?^rw{ejc6S>U%Nv*JNz5lJv7FzHd%stiiS)*jD{{)L|*io
zcuZ>^07gsp%_Kqn*ryUe_%W%mCkAt;Rp`31ylUbhR@~4{mK2e>P)F
zPzt;X<-e`{6VXyFBuNA_-w^6ee&@b_0i$ay89Wv7M8V`I7{}SaS5nEM
z#fz{VdL%P$V@jSD&t+`tTh+Tb6>@RZOg4qentqNlrRtys?nOfJlR~oSNW7#dS8W)V
z*AYLQKk~BsufIkssd3utIQgAsmFd{x+!*BKr3H~4p>5xao(W~vUyBR?P*D~D=hfpn
zqkc?$IhobaB4AuOX?z~8FsB#dB&=~4wdM`}@uhjWiK-NF)Bo^|MS%7BQ_#b2ia9iqW*oi%h0|CIA9l-7Y@aFdf|MeWUUk1Beud?-LK!v&vU3Y&$
zq=`Dr^tr}Psi6NG;jN@oO0Oh
zQ#C($QfgoCBBE6OB&BM1n?3ls@S_Am@+Rx{2IpZU2MKWtv7#3vtJtRNMv1Qm<8Qx*
zxA*j9p}_vr^A4Mu?BOL}iUY&Ipf2
zvHCQG$Hdo7^-8WnFwO{#4n$5uDjI3Va%PoKCnhbC26AeZ6emTkAnrpA!J#B_vz0XC
z>p}bbynNFhV+1Od&+A!F{`t2<1<7!B7Ts$f-yaw|FKvX>?%8{uVuG14BFxsRbHf1q
ziqv|`Io^t<`z;H2pE!U*Lp%l{N3)2uvu-5xn@wj3fO%DvCfW9u9!LmC;ykFlt{W;k
z4^hSwI^Bqmp$#R07iWiZvYCtrD?9iPZGZQkSm}FX-W)aPARB{$y@PG}smL>;DEx43prIcX!T1zS4#Hx^w)JtE
z)Je;QOA@m*Vy#fcM+}=n9e(i*Ty;W(!cLFsAwm4Mc(nJm@m(4%IF&mxj|3ka=C`&_
z+=y~nk@ijNu009_RE98I^MF+{*7D&jh&PUqK0)PV90f>Y$O*saxMwAV{{o9N_^W*H
zAt22E4fcCTpO8`6er?k`xWW@L=6&Dma(A{al8m*F{TC77dVX{Lt@8cQ-uTvj(SKBn
zaWl<|(tzIpBB6R+>SmnzYOvQN(s|>$vIweM~=_9Lcff#>TFk-gFUe
zKtS~tUWsj**>`8nRwbgMOCWyJjH2R*70;HV6sb-?f+gOFu+-|hlD|1TmEt^n1
z)eiqKBfOJP6(%^n=wCOs!RlaHj`mS<0aGF{e`n5A!ZDY@%9v^Zh5ueN_cIw&o`#I>
zH`sQA-9lAd#}y`iMqSxraI4PU+K>!*!x6YfKupyhVOv@vKW4HdnUYP6CfL`T%LI`;
zb8@mk-^K^3Oz{%==;83n{9UWTQ%KZc!Jl*ZRPH<@+cV19@wx^ay;*@AvF1pyqIEit
zcm-@dn7*#g)xlA|hRyfzmh#EDBB6zv8Qa(KL0zj{)Tib}rPe|51bG~BsE?f2+BaX7
zaypEQWv68_SX9`H^p}6ws!u$8ltnK23u<+`WrG*MNK~U+q3T>tGtM3nSJ_Bdr%Y@y364SN
zwXkrnMzgykdp{;*xAZ)JBHB>!Zf-h5=$7$63-|-nCuu^0&ou<@M+^U`pi}$~Ta*b@
z7EuR1nr&Lr?*|&gY(%x!=2EG9`4_(s*Qw-8fEg<(^G~oYh%2vO#p$cU{8U%66%WPb
zs?WHz6p^P`k(0-0o5HwY_~*=*ewC`FiBu1(fe#oyp6`KXr`u6@|9UmnWQV~Cm8SRf
z|FV|kkhckiv0n}+y@KVwy&h)#j@K`J;_)dzouDk!U6!F8qV8i+l3Ubc=mFV(E@}MB
zJ@~-_GaUlM*&_F4L*!ph6?2ClJT#cPbADvDCZDC4Fgu9p9~-xwDjPNXL7-kKRipOo
zK`l2~0cp0aG*xJVTfCCColPqSm?I%8yP1Y@SM
zEpEmgPlbdOzdt2#V@C@uCtIs2D-gl#q=R$~^6Q*s@Q2p7V`2R<%&#Ys6H~o+@;j*!
z%JSB`cJM*az-4aDu^FT`Yo6>+E?RC;v!#(#cm2)h7f6Kc-{z$pxLU|!8K;6HcqA#Y
z0rDf%wwm9^*g-%YMVz~)zNpO@fW|J)JUiE{$z?kiMqC@_pLxpBUl-xj>>mf
z8jZS}2k!1&kT`Gx2P>ax(H0>4q!-XG@Z}ARHZwqA%oeO;7Ix+Q6<9QV%?KO#O294M
z4#JaX#Fd?E+X;_}kUPqew=r9nBvyvT0guq6$Zn>@W?f@$7azSkQCX${G@&+R9V#aa
zT5moBWCQ*4ye^mNJaG1wX>J~}dIu8vm;aTcpm4ae=rSx~mv)=kvR7!E2i2SX4cOp_
zWfDa-YXq_qv2a`Z(Cw0+UL7{vIFe1ch(z(|zA%HC5W+x-`=F%6*$#Ri2Rv$J2mby_
zKsj~Nj>s>L6$+4WVMc}o_|c~D5IW?;dfhQgGsf@)K~sjo#W@Nj9RG;nCU^Be^%bN+!BBx9fS`a7>;okhcsm564nTlZ
z12KURfPjD;oL%)T?JQmN%^hs$EUvn(-Er6(*xo%KsNb`{2>(UXCMEksoKEY7k&$Yf
zyTD2g&*ZX3MWIth*i$IcOTIDne)EKAgT{bh6BK7hpj3C0Hz??;3g`w_i1B}1c7OZ4
ztloZWxuCb|r!7`qy55&PwpsjWmZA_B*ImAkB^^0>*C-?Z*{DGUsMcp!kxj}c-6P}<
z0?>jk&nwz=>1t97vp{3isIBBSPU<6=rHpPk@d{8~k?m-XoYdt6s&;@w37eUxZY
zho%bWGdc9pqqMzl7}vhEro;@S`6JJr8|le8=}MgYzn>4#Q92;RWbPkPsoxxxwyMd}
z+#AV*L8z6w_;I_qdGS%Nlk_8BuJvktnO=`?f%Nq08Mxk963R;0TN^3OB8zonPcCcs
zav5-MU$}1XBtEA1=lAz8rt&#BaI>#oK8E`(Yb`L$uXpz9oc)$=(9BP}8yCO%Og2Wb
z4H=;XO+x5H;!~51cr@cm8dK0e=;JS8wx&mhpU)P-9=g+I^3jLO+5*_lU1JRJrqLg%
z3*;8T$cwSRy3_U0ABW#1>p|iGmtNgHzF$}Cr?YwPH7D-eQOC>7XF%ir&sV*H0-w9x
z*u#wno#rnQcUbu-FpmHoIrF3gH&^!TnbOPsiiGuDq6vv)7i$`o{yW}u?xB=xm$}hK5yo$oZr9UxgqVtN+BV?z69^L{S95X^1y&2
zKl4Vyf`U#zVn%N8VNp7Qdv^D~+Xv6Jo?;%SEgBow@jAaw_!5|on
zX`6trx{X-x{;u9EZ5p6a1@Q^6!gk`phLyU~^#zR)%g$x`OgaO@c*=nANw9&2_MC$H
z9OXj168JC7>I4Fwp3Seg|3bi-ylb7AuEC}YE{}lnsPr#j0TrF(n|l5MO@M70j17Ps
zE1(V(?B29t$8I66OL+7n07{VGjc@%F0BUdk2OQ2nep=n<|LyrzD>}_;({l9;1yOIA&k8>s(absI|dzizj-80@f37g=U@m(E^lT%_ER%0M7u(
zhQbTF08yML5F$}t58*AT0G^ZmHShnEJK*PBq`O#S~1v}WxSHYkPZ
z%cxCb2b(Rikk5|r<>(bxxED3-)2%c0{ayu^n&LdTJvCk6jK_AVxu&u|-(|HSCZc)#ZVQ9+|7cCP$lm;x`C2+>&XXyi|tw
z&;N$(F{+j#Xgij!#8S=0cm>FArm#9QS#;_^gLjhKOk&|AAMDrXM
zJY`ei@Nn($u#2Z-*uxgMRLIe-TGF!@S8rrnd*R{?e`rpUV0S!=LC#+mot!$BY^R3v
zMS0}Zk=*O|%uYjC=BSkGkMPqp$TGD0flPh5+MCpZrb^LJ5SD?Z=-_uxE_`~v+7dwS
z(s;f1lXNC7G=pd?SQ?Rd)E($p{Sn)5&-q9XDME4PR=6StEse
zwpif)Dk7)q!>5<$!>*2mBp#d@(drE>(a|Q5k`s_ia_WP}M@}A$A1NE~Wm`Y8gl{7d
z_jw9F+0i8M+<&8)2jlZLyq`Dp{`-0MYzm%VLTiD0dHCO|!@D-<>X-Y&N&&BM!A;RE
z^yb}PhP|s1)*0}ai%d9lC8lg!W;+Gz7c72IYt1pdo7zo6HQOT{8LhuEa>7SJ&qh$c
zKVk5`-0F+u5Vq3d(!iF&Ow%JKw_@-jU3MPhRtq!$i%G%e@SSZX(6UlXcz{D&
z^~3NJ;^EShQC|>I#*@z`kSCSCwmWN)naD>1d|S1mdJ88{&|}!h)T7RUSpKTkf`C-W
zfr2UIfUG?=q$&@6aDmsoP6_F;=!>xY&DOwEDhGBrk^Hb|kcUowxJQDJoB}Wl<
z`Ha}h(xhn4SCuRAujYwUdt1V6&OgW_pZbiPsS)mB;(WZy^JQFkQ+DDfs_A*tppvTR
zg9|G$TA8$D&>KQI9iQ&>zz!=B?Z4}iiNY^h_3CYfkK?C_ydq?u_?Eld7jiE5e;Z
zoIR!m^nw>;t$`a3!*+03uxmwtEQMcEFIDG-XNhq`ppm$TKdhUM60C?S2rPdbi<>GF
zqVfw-2p8vVII&_vjPg+wW}L~%^l%ZbR0Cig{vRfSZqxU|2bARL=U6nB*V#s&1Nyi~LK1+x!>&
zoSSxIE^;Ap=eZHt3Y_t58hWrs1wTduW<1xDo@456-whQha>7_O_eo}J!A7kXttoS^
zdG555_?nRYYtV=+r8B|6O(I{x3?i>=Hduy>@RRVC#%B)Lq3eO9gfdCl|EAF3?}b$Z
zt*lO~(sSyy_1jUB&|-vRB*P9)j)jajPB^$$AnroD<*t$gmCF@A)HGRwoPhrkdST{tRB2TAb&d_~ztq%?<2wIE~C87*-)m
z#wU;2bgksF{8r#eB827sew6u~p3_ooZThW9b6V7nSEB~5J8suDi_F2#L=mu3#&%07iJX-v@m4-m>HN|Uf~U!LaW;y
zA&&LHURmL-Gs+&HEV3s3uhfG%c|@ZYwN~SOXrcpE*~oGmxVI#ZtKjBE);`PEFf^*Bn}rvJ}}P{&OHeWySR
z7Fw2iQ=5anEUeD%ujz}9TCLN`QtP15QPc%b0~atC$zo2h)cGZtg>z=mmZu;uQ$0;K
zRo**dWx2Y!`D*JRmBDhkb-)E`UrAbXwj{dEeMZO@ZCRsrvTcunz{97xpso*7K}SWt
z@g0zkE|lWge<%NZ63O@0bF4OJC_Ie-A8=Hfq<>%N%TH9Ra+=&%EU!k?aaI3G;&Agn
zeR_2C2Or~eaQa}u5@5fj&
z?nCN+{3Y%(6C}IBj$8-L=m&&yv2U2BQ+ftrkiFn(L)&m*bU3+E>>P{H=`!u*)QGNz
z#RbeD>c)0G)I1%ZGi=ZFFjq358%)z4*rL)(dvWrBLw?`U4mzlv0XhIX20Y$C**Jo9
z=u~IEt`f05Y5cpWy&%B@elo+=S(rjXeoknY}f^jtph`
z;cIysUfzwe^I}5hFLng92y3Vb3bR)BQ`Ec^zm%g6**;BRdPjSdD{(z#E_-EG+LLRb
zrlq%r1a_UA0(Om@1~%R1RAO*(y?GXvGW!b#wYI^~qwvzS?n>2zt4^#bX$KyiXe|1^
z()FdEbgJ>V?QbdTE>rz0xl9k**MUjGv0lPT0ObH}`#U
z;vc%q_SR@eU@EV~cGuAqrBPUjg?i!T-wUv__@=9-f9mICRzDckikgSGlc%kyOs3`S
zhJA~x%1Uc&yj(Nf*Lps~{`*rhov$O8eep^H)9_g%aRJQ?-?(KH)Dr(dABd^&`_agK
zNib5bwxi;{@m5K=(0mt9Bj>wa<@fJ!0I?(hSMTt3OYy_#rBCRX`mbcQUuTCWC1Pp#
zZ#Qh@Dmwn~Wi?Qe?dKQ(wPXuhsiRBE{G45)P84hXgfc6DrQwTKPq5ai=!mOBore6S
z)CQnPJbB?D+ETO^;p%J%8{zthoSGJ|s!1p4`7-h68+Qh)LR7=#
zfMgPKWV1@rpOR>}qjpJ#K+5C@!4_!RfvZhCqdMAOoxG<%P7vViO%b5z2_Q)(OQx{J
z!Hx`O8_JP8)qkw>P9nt)SZT~xrs2;WwznY46Qt_w><-st$Qa|y|C2#~mS60DGN?K`
zJI{LYRRy(kpcM&vc~++fTVm$C)GlTF8hawPGP`@d9SPg;qnYbtVht>p*Q8P0$#caopnVId_j_sJ4nK@==W`>xVnVGhk
znVFgM?L5z0=X`J7y0_~7*d=XgG_$6A)VHv2|0OZ1H7#
zdBDe3`}!YjJ$l{6pP5-V!l_Vcm3I(uM(3XQkg9)?Gv$bo0^WmiZKV+v3AwJYQTceK7g+0>tY
z{2wBGzT(>SN1cQ5Fk$LcX=TutKf_Dc*^$(%$e&P7D(gRHvkYBm_m5;aBT}`!=Vgg5
z$CKKml9jM+qUPhe@ge{c+zP;f#kvgbc7#ERf=U)4up(QExpR7`Zxg@qQxAHqE|Xq%
z^p?2Bh5^C=u9VH$k%%+jm1s9~(!FN%^-xWpB;>w^>I`4s^z`sugPbmN|0VnMkb%+V
zBK=|C_+-A`gutM{>Y7_@S*UVwC9wy
z+alH@!Xf(loX0s-_Pt;x-}2`{L(G&JCf{uF`Z|*^Jz!@GgtpLV`y3po
zte3}bkashyBuOH#28m_Cf~Di`f7~FCrs5a08Vf0pBA8tRM?W7-?}jzQB?5Mn=_*S|
zaHupp+Or?WI5$en%LMc1>CbOd@WkA{~5;6j==*w5Azc
zFZV_-w;3=}V4d*98fQa(P9;eSEFZ28E{_fSqLAY-T0-DfLx3gC<(59}b=TC9&D7An
z>sxo6l72lj7ntxU)yywm`@@~rOsM0gA#a1vW~sjCZ!e1BO(kF_)4<0Jd(4D~6Z%&a
z{A~|?*$;Zq`&Z(+eIA%0k<65kaA=;_RD;2ZfxEmOR>V~2^jx_BPBZonwqr7ed7DGd
zTv@K`dp$e1jxFMbn5okjm;g%0-|JxM9b@y#Ds!(FLi1lmbN{NUhUC(%slR~s*cs``
zupGs2H4<`-OL~8!erGCV<74h0{Z||(Q8yTXxi09xw3*`^l5*(v&&mdL2pp3$
z_4XFllL!}0!+CI!rkN=PPFKRA2>pJr*p2aPVNpUB3#|jmV!aFkg(HXd0gw$
zLN6(HeQ~XD7(AnJI)bFd@6<*I*Fd%@wVtJgY>EX0AAg+Td)6QzNuTk4<4x_CeKq#w
zB#lP5!_e4JUjQ|^26ZQxrZGGDGI9`>u>7>)#~FHYMeI&6;LBWsPHjFAVbV{VoO&|I
z847yfNV1qqzZ4q9lO?`~v3LILiDO6(%AQ1wHbjI4W-RJi`I|*k>s=#~VR24AVb`IS
zesL)w|0%Dfg$Qtzu%erjgiED5a_&WP(#Qk;XKl{@+5%mOpiLt@TEvtUZKTcSj7tib
z=a?dz?{{480~xNRxDX!i?}cFRNj})BBGtPYtKwsy>?+2ph=+W$=|7RhNUtF~ky-HqVl?^G4%}<7F>$!k3;4tYZ#U6?lkqd(df^0$3r%)U@xNf|R~K
z_w!e>?{cnj@11Vss}62R?NykHNvEh!rDcdWIl*
z?TMkf>Si3k@FsPeclX=4Zs68NYju~dP10*8QlY{a)SjPaZxMA0nCuNW1GIUa{1Z6R
zRM<$C>vyt<7r5I5_7w2rdQ;yz1r9h+q>5-G0%Jr;eyyB_9isjWg3m
zJ1_*q8e0Q5Q?V2^JRExIzx9bN|3}sZ*cNFxwj=)~?KPHV$AJSakzv?zJ-~nDJx(l>
z&v}fXFBVUYbSDCLMifsSeW0c8^(K|rC~X6W{sbu}91oGc3$2BOc9&@+uzj5wnkk?E
zE;g<}&lpx#ecFC?NwzDhMHZadRE{|z1dgFIe`FW<4B#b-2Os(fuY;MaVgc42{<1mWllmnzme5z<1
z?z3nf?sJF}g6u+FV$Fc33btAT{gj@uvs}cP3SvBiVPgg@7Oz5`vnCyuYu(Qz6Dn@c
zL7BSt;YGNpCugFqY<>SS5D26|G7Rtcstmxv>6RZlwiQZtiWN#G#|nvCn^j>>p==3N
zAjzZC3Um7*$)ZsN#f-^$x|hH5unJ;S9F^jriDUuXByTKj8+|YCd1=0(r?ru?qL>7)
zW>*uXGZGrY;ba^YGbHw^tOPZ0!S<}{y!Ru4K9_{e*0as3E(M2aR_k(niSSkT7Y+aQ5lb
zO2FkdoJklvqmgQnK3J*-*EZ2}1W8{OQ`=?a5Ozq|
zs}zgE7w6ItSo4%SsJ=*`{km;_CN;#KX!8_W$Q!KlSf*67w7S1Q}3|*bXRDXuE8V2
z#fRsQr{@wOS9duK6FnIOcLg9=SSKK_3sr>8jw7vu`qz#SdXlTU#4QsR+{D(&AZ?zz
z@QgSFAKw~0O5INTR0?;FHk$?u%3bym@cISY^K9WPk&2TsX0Pki!rR
z6^CzF?AySXKI5%*V-X|W?Q5j#$_|FQ>)4!e^suah$Snla#ad4}e{Th?5apOR3Pl&7
z%{j{xwmT>%xWSnKznk;E2W0pLnEx_1sG1
zm2Z!R_Mr#g?F)wuUSBt^7_d}TMiGP9hgu*Tug}cW)Zygk=lyCUv1h=R
zCTj=(V8CFLrxR5iacK8q416ur=;j1`VI&Z3C*Rm2Qs1J*U^CE|VR~`7mw(enLh#3P
z^Idi3XLq;fP4(@mmSY$Pr2lPs3@yDUj)8ITL}yxQOzW@M*F=0`#T@Br#M{Q(;bTo&
z7p?>~H|li8`dUirknL76tu0H#?zbR-Td>N@WD%H)ak)U(aDN+GR6ix~liz^I=N5sj
zsc3gOw0$)L(=jaGMF_5BHHsV
zL*P^|0cOENdw}V$S$TzSS8t=!Zpkc8p%-;Z9zhO}7)PcIW-U8|}y*IbaX9
zrkt*iJ%Qw>K*gC2`AG%khACR4afVpmnD+D^4hsQ?)b?bonk?s`+i0vB34x;;3wbhe
zw3q*k-GtxK2pv{5*E%vywFk^F!Fby4D|n!xWzuPXEpldoZsX4Ka7Lcy-%a)oyzj<&
z^uiZ}>*jG=%#Pt(WT!?hdlhqIM+S4lqRYUF5)$mGZA%O;`a?w3k|6WI?6
z^g}`Ub|64ML`Mh1l0yqqlSx-@%L~_Dj)B}qZx!w!Ch{$U4d^dn8E#f8;f1E}lCtJ9viu?RP@D
zoG#9G&qSIU0Ay}LS!DEo$%q>a(j8$l65m*e9+G8rOPxrK{5LFruD`xf_*=*eX^=BA
zX{sTYs>+r(Op{6}JH%TJ&6qJXjjhZHw_pmmbvWA}*++0VkL)=Uk(zE4uJDH+?Rp)H
z$sO<}`tIg+xgDyeLXPW!NTya{euLRmvXl_@YW0I@_GA}m6~SE=Fi3*`Fr&XT5;cXj
z69UMMxONSM?ey3j29mJ-)%|->2z)0|RHz}KzX=r7G$HnaCOaBGM1|J2o+^uuYx=L2PeK_l9LPYf$-C*fK@psEiVQF;y~;0Pno8x;c=sHT0DdS_FeHY*-Hki0TERTV
z9a1lf1Z~T`k-KA0^xanZ|6|J!Tf)p>Olps$5>_Dp5euq6aPUm4HWq?7g_j_lV(9-R
zUSh&_iC3)SCc<_gKn>jre*@ZX|9@Zx6k^83Ytd{aahQx#s=
za+6(v^9<`O$n6rQd)5#;qW$XgHpQMPV;j*Wva+jcF(G637i%}|mcUZwc2@nJ{?$tj
z%Q4}M=JCa(UWt}(F&)2A58{h2DBlgJ<2rIFn&%Y*cahGwi}s0$+lD~CU6Y!_(l9y6
z5=Z$CHJv$2YxJL_Yy@8`AlYgjgqd?6448A>{iQJydb6ph|5&TI%-rsaDr`hx@Y#=J
zSHaPH(<8|*2&6v`U)@@(cqC~t64rmXCDyS109~X@lHp+zCSU97w`F!Xti&~Gz5O{B
zf%ezg_=AJ0%P;A>l56@O+}{>cZDRb-$b
zK-`mArL$^I`4Wie+1ZT^v^iBe>BjrWPp=l@#XkI^lX1KITt9Tu3COSLI7bM$#+(SN
z;xQ>g_%>uiTP9mvfyROaaVimkvhb`aGO`=~*(HPrJd=b9JcEP=JcEJ`cm9;ZxW;sJ
z?CJDf(I_nZ;gnLQI8nR!s(UMPW3j45#uaP+CPMjWN{I3}Nrs=TR&IeVWDmH=&{~v4ubx}kmP>~utzq?t
zAtJ3TVHzjr(|twR$CA~Lh2=Ms%XIoVkAw+LUoGQVdXb1rwvV9~ZdVXgJ48@3opew=
zog&a}0*<_QQr8Kzp6oqJ9AcuL^e?Nt#5xpa@7nn-2!B=JmOg^u);7&7YEn}S4|qE5
zh5Vj^d$!<=bm{iIWi6}&d=?m2@$vxSmL1IZ=J(~&?))B|xQoty{n(X*{8tmmCr2@_
zwv%r(CtQF&Xe62W5JV3IVs?q_TD)J8X9M#j+xuSGju7c-B|vigt}`&K`Hp){ZjO8W
zuVo}K4$Bj%Lqw%BNo;SgzV@Q|OWLhRs47*cH*
z&(_HgAvGoOxnzsF>T>5HKSa~e;ryYK3RFKe=Lo%!g~DtxYzF{6gs)#J)(B^KQXg=Q
z7O2e4fo3{J(0oBD{{huOl&t@ry^Ee@~
z3e{WLVmB+K@TyCX$(QNSoU3aY3&w)4v*9ZfT{^LWuL`eVI%Z{!&+w$-WpveR+A0>p($k&=dnJ@q-&|^+1zW0bT
zEhG2RkNGU7Z-pT#fvo}P1zXpHWUr|E%~j?W^b(CzB;yRF+NacArmI+S8=D&MU+YJstuNz=v*VUtfxD>gzBIym#s
zpe5oIl7q7MFF>$Lt{~Ga!&#z%rtsBo`pLUUuYO=%%IV*`JPuwgL)(zEd&6H)aNDHx
zJuKXmOY_Ipv-cQ~iESSUqO;QBxo~BwYhZ4Cw_j%QYV1zijWsb}=nv99W4nKTTQ-&8
zHt6T3IxvT#lN;;R8(|{0FQ((2
ztJfLyGla0osI=-YQQ^S06WFyC^y#Pczs1J4h187KW_~TP2FO~T-8kU_(}l!Jz|DQHbX1`L6XW|tqrKxwlfXEKz=mLLAreUr-qFR-Co
ztp|?9FvB;$mU0)YpMI2PD)Y*Yob?UT&z!5ZfvQxg#aO+crGdI@4oJ
z1_8&GwW(8GSj1E<&Tpp{?6}y!#~+N;&oQxe8BNd~d!Gz~W!g+5B6J6xHx_1I_Uj2Y
zXkhrNZlR)H47ArPFU485i2)HO7S0^*ik<~)15~0uby}DluH|f~#9qLu#5^${?Op9H
zJT=WeBwL=5Z;(ids+36az#sD#b_-k<(P4*K1p*7z?tlO(_YwWZ&uK#oG`R_=k8bg%wy=-6OivOJ!n56U@S&HgfxPQ$0|C{e+R
zerJ6=>PY0}xqfoTyH!8z%?&GAl?^LVl@*Is0^roA+t5`Pv}@7_s8P&Cq-X%Sq`K
zuPGjzq?uo+k}kWJw4-s&n@2H<-m}OV!N}BYE-$=}^_OAXe1XEAhhme6;~f4|Y+%P+
z`l@~rP175nvu(-xaMK}O5nen9xIfj%jNGa`UQ0`0e9onm8}EMaT)qY&mQtQX{p2G6
z1d$U@H3FA>x-LyG=}{sK9hcS0Heen1BceUJrNEqO_rETUk2=&9
zIxqbcqepj08<>vG3Sja$Cz(>u2aI$J)_865O+=jJQTZFd^P#YgPJ@@`qf@rxqiMmk
z?{{xfzoZiNrPH>Zr%s|r4&G0rr};+=+@l1AV5}!I@eMdcuXpHV3g~>VrvHsER*uiL
zb-`)Rgv-0&*RnpZ+0xNZzVHvKBSY?P-%^cdU#8AJHS6z3J4#;PwZ9+L7QbR+&M8rN
z$TMXfamh5eGj$3a8(qu-Lv$l<*SSo$+wNqRY%cbBn9U-9kYrlmCW%5j7vxpVCr+vuoyv`n~7Go*B+$|)Tq?IF}VIT*1#_yOykzCk^?;j
zV-4Zjupa@*qE-sIYIr!}*dUlX>C(AHh})(5)Q35#Sk0<;TR=NOI3HESfJFT0GHoDSZm$Xkd_}OLRnQf=?
z`Hrd$vg1R?9z4olu}7VM>qj{d7<^UBVsHIfNS*M>A(cU(lQ2z7vK0iJR8}tYwAbev
z9xzy^CPGyuQ9o|r%p+9n^>*HYa;3FweWjd}m$}*gIOF%{!VkwT>!=2GDQqnma7!$;
z+f-}%60_*YXq0l>RBHlD$UA4;_Kdpe^}E?X+Ff@OV4|@J13_Fcki_%MTi9#afd+hL
zN<8&zivcTM`nt_`Z4iu;HnB8!5SU0Qq>VH=Q>cV*JdXyuE$WO~6LxCA5@#~Vb!uRr
z6};a0hh2~R;2kY)tp2y6_G#JabNtfZcW}kV5cgk+kuporJY)2g^I8e6AYT8!IxcnywFZm>Vodxu;9gS<(W3>SwZrkK+N}&mf
z6UJnKf!QRhgpOW$+~>lPAGL2%xSou<`rqBJd{d765+KS@s9@)fce^0VYD}La$Ig-}
z80(HwhU_nsW3Y%BMGM}5M3tU~nEmgszx_-d`lCIDPe!rB=PAxc@0Sn89~-Q3=ZZ|%
zYJW;JPCnWaK;v6JUvj1geK
zHC|pD7sC8B3)a|wVbu5~ELXnT0N{Y3@gbQ>Gwilu!#I=U;R~vCw+%LXv&{^cm`F^D
z4&hT`xAGbiNvFZHHp3LCdZie2hC=qVp<>|qvF5aYqS;+ifuPO!J*vCPcY!+gV$8Ex
zwKu7f*Zj0TEr#-`@A(97d}ZwS0(6nKV~`)lxMt>bh9>2y+=;uMjwmm^?Gdk4a?8F-
zm=}%TaJKQ8ch}Gt0GjHpx7L#y-vGYpX?{Y;Mhs5`X0s2FK=E?BbY
zZoh#>AJ8An(&G!%%;;Yx?A|@x@3zGjH=Yevw!t2uNxbUSy0NCmM8rfqINP&-FsEUf
zjt>qRHEPhS#<;#~cd*cKtdyD95t#YoQ5V4K3{m97o#_jmEePsQ-7;BK4OfbE5iRp6
zM-pL>PlkiIhJPNN;N=hFdIo%&@@hx%Pui)YO9KA)tMV=y`f=VLg=^KpX8fQ@_A_1LgG!9QfU>0uDNmKH%K^xOg1H808&1=s4shu;+Zu@
zGtA0<)m%rL>2o4a?P#GL)J{i@)J#W*^cZ27C{7i|BY5N;-~(eGJkaIUt)ou9RH@Pl
zWM2h3aQ5*It=|jW1Dp<42bzIt*}Z9)f1c%Oc?2;n)i1)#+b06!*kI0SEw+B#TE(PC
z8kNsM<4I=0uEd$y4_nAFYavwT&KV@Uw!T7kIz~d*PRP|(v1bEF2J%nWT>;2sve>K5
zSKH+g``k-qanQMQtn{aQ;Hh(sGMwL;t1&)Sdq&^*`FkANT=)`Ws+kX8m$=ioKbcWE
z0j4dU?(T?tRf{7(60trZ10_R(crnZ+cglUBmz
zDHUeOXZMv!uASDExdcyXa9PwUDM^V*Q>f+r?r^s?TTdyB@>RIre=fGaYOv$sdg1p%
zyLA&&_Q-ri$k}^3$<4TX(?8dI{`fX)R9oxaeR_7{1?Q#pr~Tn=)1Y;-$>NsuTGUu+
z1YH?mOfeW-xIX*yg8$vyj4K}VBJaIxIQ7iRa`4n`>gTa&ZCk~9vl`)~Qmmu5K!c~d
z1K|2?cQE-ABnST#;g{R!&Gk|Lr#YjiD_p10u_yTkHzQ2Nnil%M`|Garo)@%zzp;KsqRf&Wrj
zL~rigbJt7-Z;Xr^yeHcD={~$bWVla~=au_dg0cSd^}Xk^!0CPPJv=8`PMY7J!YyEw
zsOzcD0;1
zB6C$1)%JbxlU0hHxyEt*lFdOJg+dyCfEV9weo{f*B5>NLh3lG`)1^?m#+sR`rQwA|
zp}8vEe_f-ambPl_s2kI$QDnYkQ{^%WJ=-YL
zS8SQm|D&^pxpDlki^yHUWpJpkl5G$oQ@ov9vHew7^=wr3#yybo`DV9FP2Tp}UN6nQ
z63bPlK#eXgQ5O4dNo>#AUa}P1OC$C68|;#&_PLLOkC&56!RMz^I(gG*K#vawL1$85};|IG%zW!zlZo+M(pKd&u
zaQ;7~XrcG`Po4YKV8KsM#Svx~qHy*f+fe(vYHbE$KaWm>A7J+spCwkAoL-MihmSw<*cab_Wt?-BGX_
zCDSBfnivIQ>^i+Y_9mue)0Wu&*7>OC^Cyr>n-K7&G>`2BOXBs~2<5jmqNS7iAGU@#
zLrn*Mj~Fq&UD$R*^?7!1|Ehtz`L#(O_T||A?q0WF$p6^__h6^+F;ZSM`
z-j|c=q+183+JtP&b>1@ty3YlbY;4)0sjLc3Q1!=2J;8PDn{QciN88qVK;A`BSFy!<
zkaC$xaZA~~3e1lAi=rm)e6n@!EVFU625jKt2F>`@Hrgj_~aWIYN$
zgeoM!w<0SKP2tcs-DW9?jTD)_i6v305`x2NV~}#+giyQOAy`^8tsA%PlNhHMI}VYhl&kS?
z+W)Cj`^5!0CMEz@$hbx{`5~job6dJ)iT_0+*1`B&gbu6~bvyIr+n(+uHhL3!=&mOs&NoVUlZtS?MhID%EC98bnj>GDrbqtDN-74Y&YOwLZMr
ziVEEuo1derk;%sn-g5=zn%p#J#QDIQkb2P;V@-@VDsE^@T0~QCGV%abZgVY&Dys)}
zP=jbc=c=rz{~Q%xS4|SqDI9zh!FD@%wFufI&t=u}Bui8UvIo+|^K(W9es%q~*Y5#5
z2UUVZsgD2Yw1*=A5Fs>!>FnW|QrFj01Mu5~aAb#iX7%U~T6($rKNRAaeu
zY9pT-+4!rhl8pzQx99Q|1n)|39$%_hHN;}#mYoLHErl>7Krf8`j6IwiQL5zE?{Tg&Xlt`#=Q4Na?
zei_AuV&ke~?dsMkixggIvpU_TFyEnRi-(i@4ANi4nKh;$c(FjYMTv6%$}q7~D2n#3
zJGib~XCsG1axY8U!)2KH1lLaX8QOKsObI!)j?bXR=uiI0r3&)sX2%5qbOU@~Wvx~C
zDX7S@_VMSN9@a5}wRF?86CJ}_B&|sY8<)u1EGD+98V!kc#jk$fP`Uv8SrwK|%a(Mp
zk*#5B&44vUm%V{BHyT<_(_e;T2sTo!bzwzZf1Flr6Q8w}9)~&dsq
zhr1QnrEz`a@#!xznz54xzq|OXGEi1DlafC~2te85K6R124M|&3=;6-MPHyXy$~-Yr#&yGpmtf1mH3?ftTdu<0LcNRENJmp9R0T#$`O47)AKvNR-$ZZ%yOjc=?!TEJWcb&hfi4siJ|g
zQhWnv$H9uFZY-%gzj{E;tKXopJ)k}`H){qETF%Ac)lassFU9j)GyahRaaKQra@GXc
zVzw;0gUgonfIhIB*3jPq*7x7C%~1_aoOovCNXKH?yTXBnpqU(Kbe;VF;z};yQ-3;E
z4l&!mCAn3fhC1|6jN-L2A{xNj?+n5o;Xy^O2HQtp(l0nU{|Fi)lvqz^YXX(M3Dt2f
zj!;EKs(!L>#nVK8TzqSB(#THNGz9L?zjN+RSJYO*dLUi2IH^rUHanRZ&)@ey*iW_4
z1=rxNxeUoQD$}Ict03sJG_mQ64;d$*i?kA~$2K$-vwzvIo6Gs#VO+q@Fu+B#m~3Uh
zB(Z{E!)03BRzZV*aX_8XYfZ!AV3P)EOq~*-sd)J-apnTcer595q#-H1m2ljk71n*(
z{2#ewx)fVq6m~$miZ_1&6hMa*XN3}-b$AX)COaimf{c
zoZ5kPQ3wy5f0R11u_G&KsrtFT
zFxFHFo6pV_-{(=W_&Mh=;bv%C-h~)5N%7mZ
zh-t&+wMxTBgBl4kei}~)p|$)J(CL|Y0xotc&3I(VneAVuLx~ujHg04~==}ELzg`{x
zAmQlkt7np0kF*t8N2Ww;T``9QHd`6$QN|D!@?l~8x368GFAC7v3;R^->)N57P{7PG
z_WN5yiYn>tY}xXw&&?^5no-hQ8EmhYk+wqXU+XmoqWD?H;qh0RQuvN;J|&A
z0bDPtT_!Krp=Pp4YOT2i6Prs0QGRggEnWN9&4!1xFE%kp3GA<*;d4(aQC&QHnkaw#
z?ydrP36$H3Gl7s;XeCCXn3%?at%zi@unXHn(g*@^i}8NDORYt9{HvD8+D0v<-NQ@a
zeU{wF3+TyZjV31hfr}f@*`a0c?MQ2Ec>GDdzqNf0jbQ9+F-1djpI8oU!QBey{Ou6P
zYhpF|7qa1({h?HxG$4Y%ioj9w{ilGTReKeU{r+DGB-S=^8Ll-(h5ZY8Xz?)8x_W5&
zZ?)Y!WcZ{ULjx1*|IbR93>|@eCrWK)D(b2GD`b|TrlWK;iOrx9Q$gG{{K@4GpC`44L-WWI?)uBb!25f?ixJ36@8S`P&3KqL1a|ya3tXW3nr!b&cDJj
zv|yDSqY1ZgIM
z1a_l0rK7irL;%Dn4mAaSvn~7g`ZQi@+>ZN;?elL0aFw;+e?e)X4IN=T0W+Aa=-xP3
z+}Jm@JU6Dw^2?eGI@G0CM4WiC5z2=T8rODZV?fMxzp0HN&nIue7;nNAyJ~y9J%brP
zob@WGJ+NbQ>mshC;L7$)-)*0DEg!{U#rt_USsugoE)hnRlJ%i~bicoSZLQ2CtXCx$n5*RsBXnTy
zuclSf&!D3R6P
z7U5S>jH-iXG?;>+1YrEya@9rmm?voa=0XM+x-r11IR`mhGeq}~KHOUZC-2O>{1=xY
z#+rWcu+3mt@ivh3x*ZB9Dm6zD%@5#THsBULZ`ixGD~lA{itkpIc9Yj1JhioUEjKw_
z>mTk<99aJ}+FAKDDxJsVf)W>7jwtfg(qc{Xfo;+tU0=W6`FmjGz)~^0IXz4*-Yr#j
z`oKQ4Qdm;;6^InjHb<fZ20ApO*l5=Oym97Yt2Os{UTF6qdgi)UA#2VLf3Cn1T<2z>CU-6!X!z@7ced
zGomj&KltId1Kw*c1?fY5;`>=Gnj1#^exzsLoH)XTZ|({eB5;L#((m+96U6z0^v%v!
zcyR~hU=1q%cj}d6&C!~;!ZaUwHgNZFEqJ%JA)4Q-zWmv(Ij{{tc~}0>2=hzWufS|;
z*-+9+1DL7eth{|~Z7}|)Iu2&$r=cXyRIH9F@#=5V^_CqZAs*`Ou0CBR72J*@(!gny
zMk>fI+|7%|Y>eM8YQTlnTFj|j3NCy(IsrFJ%`C5X5dQX?e2d%^w{VHVT
zyxBgQ!=KK?nA%!WD+*}BAy;Vz0ytdN3NvQ#
zu+Q=_#*S!2S3d1vQtGv;QPwH%cHRE8uy{Jk=?V#~3b^y+J`4v`ySN2nGQmfJLAIKu
zo@`$?JlC2z6w!y>w_SPYi!|v8n^^e;MlOS`3V3pt*+fCR0$-=)hq(_;81w-t%f7->0N8IrL@U^y`CL|{eBo}Q(cpgvYmlyKqb%2xgEk@~`^
ztKi{>Xkq3wFt#|lwsz*R%SA#e*jm%UF@X!KQx^;%O;cJBM2R9j%FegEWGWaypHW&M
zWZwk1$~2%&QDR^JY#xVfrEkPN`-I?te_|u-&#J7J__3L^p6vBbn^}XPhv9}IhIG08
zxgmiS)X*MS5(?xkXUL
ztAfLzQ9(QtDDo?-(1bPl-P~Flr?OdBEZn;fh73L_w&hXYkWL~P6_Z0Ph?gZgf+haO
zcQe?)_CF^8cb{be0Un+U#85FDWHE%VNeBD!b&@U6rrN}^U0M^DLl}?}ch!*mNQ{Ng
zsm(2qxlz;e#9adCNSi?c;!8pB8d>mI4LsQNTerI|M+Q^P9VQX=JlK|92U6|**!l$<
zY^cCAZZI#diZF2)WYSu);xbm&Nrpc2-0t*FMX2tg?%sKCG3it>%BM!mzawTc`~Kz}
z@@6AF`syl2>ELYSz#ecbw9wOU!QAc%M<{~k`V}m)uO(e)#$^5GSkDU*kkqQ{ml}fa
zI^bQ^*{&3u)y1&MtpxUAvCEod>OQ$xQ=$gpMO@6mX-?=8^Oz)Nr@w#U-5#PzD{rwI
z3Xi2|j!j!I!|=09c=(Bx;n6c_h(C7542WMCed<2o2ieq9jjfyTFW#k5xXBw8G0Ptn
z#T?fXJPvzr?rrJ3d1`gE=?Bw09T0(6V!XXrZ^68UKU+xQst1fRJ)a&#)bpCb@gq9+o>U2(*^H_fL}Vne~oxM-cn&rp57m$WjqAvXSmbR
zHN5c~A(6#Bkzo3fkcozTv+vinrW&Y?18&7&{EOe|6tMywwe*FqMqN-2b4miWY@Bm+
zv>0s$4?*ANP03|D?FV2_D>b`y4$R4-kN(N
z9)wiR{yAg&U{Tv}l6<}WA+UQy(|_`#d9iwKz15n#^=$@DM-|g~*Bd-i4ak1lK;M6P
zBXmC|p-`x;UF}4|{ym`6aCdo6pXr!HLV89^Dy*U`Y^0G;v0Y#_H%QK0DP?$slrNLa
z5+(ITSv+XYtWl=;N1j~S1TfS^(WiV>Do|R6hC!SswM2Bt$*A~a(#>AnRFiXgQH4GG
zM=F}BR^P0iujGWP>kryhWg5kbt)%CEi`*d*?%ZGzxNU02faX|~gR>CU2
zFW{+n5sJRz;|d_CP!C0k1GXQ%s8wG*LH8mlBXkJn6m{=B6Hn`G6;)O@(T!H0f+bPg9vGp*D
zSKBb;jS|k@R}>rF*JJQ@j%dP?UM-I8r1A$M^Q>b@^%7ZS&G!cxKoR12ogyU0%i
zJEit_=#QvL2U%=T8=jOuBw59^N4q(vrP#N`x1}j!u1tTtwVjS5qouQE2UU?qh$<n71s#FJ1RGN>4AOdj1NAjxxkxQi_4leX^iA!#uc;W9@Ua@BIn5k
z?%o-M8KSG@KEr|F#UY(6qYPF>pk^ubd1%omtL1IbvAN`0<&x
ztp{~K+U-mD-ucjW!}ugh)QMq--~4l4Q*P8YvB4_UCi^|kKSlApX*)Ll5rV*C&7+YMPq07JH&X?)9)zRdB1tAf7()*(+4uFSxWBfCXKR@xShvo77jr8lr#+xzN^M|<@9E>e3QLJxI*E|#gQ+d
zNQv^PVwbus!jMNzTMS~p-4&-T1=j167hus;N
zD?paWc|=gD;z})3x(HkP`05s{<$v1ZLBCqn6}uMi49TRhAF%5L-E{@uD&kS1juZ#p
z5G?ANP=mfB+}%*#FUv%&b(#`zs<#K5^us8~jl)V}zD(6r0*ul|0*u^7f}KJl=Il?L
zo&;9R!?RZCDUGnX_(8=w722nA9sNX!m6}8vhK;TIJ$B036vkAMW8#T`koo9CoVkJ_
z_4&b^Q-SPRTDV1GUT;JSZvJYtT%6esis!5C3Mlea%ypn|ZNc6%q4M->EjYQJ4Gc|w
zINj@>J`@xrn{cSgMQ8rf306$B2P1LuOj2br8EXWIF-#n8|2Zp-Xgr-0Rcw_1MG!UU
z8Yz7pR=+|qoF;gNoa_Tbyd{J&l7zu
zmT&HG&0>Y^2m2=$QDlLexA+BxT0**#$vwaX%vkZDE{P<1%^y$HEd)r{0-NJhvCQm`
z(m~cOp&zSysQ692w~hz1B(w|FB-OAgCW2+qLI|_(b|va6&_Z2^35B8Tu=RV)>7vP=
z>t}PxXBBJ7KW2$`N{q+Whi#d=lk|Sb%{1o47taizL~@^n3JN0ox`+1Vp#^(1{ZWWTY;S@0g3kDqA7{qK3Za5M*ZR7S!IG_Y8ORwmE6>ceb5y2uZrEBm(Nj;R^7Td
z#+VFogmN(yzg^6JEzoH`U5sV#0&-96p=c#;MIt$$e4%dj^#o_8)g!*{KHfmsM*u_0
zB7YzL+&((zwK@pQsCN*S(eof|R*GYkrlOKT?2>C+nIpgBCKWkdEqS7?nbM`<;BpQ%_z>O=s484M9C}E6|Vf%%jX5$A9NK5L3B_`$DwrW%DX|dhsvEb
z&U}_d6ZB2A(5;+!)o3A!!;6O`SdO-hmUld9}C
zze$J%P$gmHmn&D>4a+iN+!wDuS*j!zejwVGttND%YS1gwhA5MUD6H&E9K&yt_D~H)
zWSl}_cc5(B+6xehGZgv4qCQCx^*!;jl`tXG%U1FFpijHiIuE>m(tdN4=7SYzf@Uhn
z1l4rOr>c*Ub11?qQ*t;?MP8&K&D2f9vdm-;#X%!_Wj{{VpC>2><4t&@K{$)o=W{|e
z(ODG(k$s8Bq3P^)nF=%Q)S}=@x!*o)b+0g=h+pkO-KQFF2cyLy0B@8N$)NF1(e|
zBvp<@n5M=CalDLISQj@U?{v@#ih7@Rwp?6K=~TS>nEwcNY0zc-Z=25P6CS8&@!5Oq
zQjdoHLHie|@36mrgml^3o9NYi!K
zVR=t=Jg6-Nay<0(P`TZ9NEaiqk(U<+(eTaU6Fj2Q-=3@Y=!FsLP9;wyk+TH?GyV&0
z0!s2~I0L5Rddk|mXWeJVXHX!k|3$p^tQ1)=ftN9L!E{v?DfZE5@b%d~*++#Dt;MFA
zAV8~7P+2;6CLqwK%9Fq)tV5`|npQwxm7byqpmfDKZq_m?p(0vZ0!0+G1j^J+N7{7p
zuDx{*@hKik{+~*#xsNncHyxH$tGVhLgF@i{N%%Q5_C^OQT
zQjm0RvOuTdvWN)!vU^e&5{-jj$tD3eS-}4B#Js{Sn#(XV02$
zrZ{`|3;F`&p#**}^Bm9z%&^@VcKXBfzIa1aXX(Po#W4nTv59!Kl9w*f?IGgCO-hH}
zE_}L@-NUMr2rIZ=TwTrZR>;9A=Kh{MjI
zQUh^O2Q{Y9S%A1yP^p|bbhU3c5HFD_OG0A?hY%`97$i#dM(Iw`uH^#{A=t?4q*kw~
zSqz%pqN>8~6LGXFI!};T%PHZ!1L4T__o7v;OI>g7w><2&J?WDk;VF-1xJ
zQAfzAzh2xvCZ^;*#AXEa#Y?=HVQj{QLk_^szf;Kb@s-Zp4i1OnM6+{*mYl-~{ppZbJ8!^Ib!*k}59HN4l9C#>wC**HwqC`ZpB04)8mj
z9SN6U9U_@u;j-*R9Q2D&z|V-E-Ti&seDZ!@-sC_^w|{^`1NUVZr9B>O*qS`huo-!v
ziT0zSpV3J^oAt0K+K<9sX`u)$M56svSyn9+NV1lw;2>|3$*8iUs|CH-Jx5-2TfQM6
z8?{Dsj}SGA-OxMQ>Jmk(hWWkDJEvm|tIHZx=a@hyP8Pl|9?^EIH#mN~BmPRq4a4
zBv_+y4)#24BkYxfc%^X;(mZW*SXP}I0gdB4x1A2DHojW3aOVuYza?*xxx~9tXA~AuYm|FJ@+Qg+n$V2mB(Az;_V>1mD#g*o8C?=WG77x|
zQfW^{-zM{&;v5~quZv@9pBMe?*tX;LFv(l;UKC1f&MOC}!w!yC}7K
zqRuwW!T0~W-`(#}wfkavN%y9!PII(Gqgk4=H9Ez>CXx=ytEfd5JEb#DC>PH8p`S87
zD=j1VGO!}LV?#QgJk>i$$(2k6)jL+H>^*NZ?oeG7FK^7Sy=aNs9eQY@jRmYHuhY_2lh&Tl2UyeX|CQYmZkEG
ziqix6)iUi2dsT7GulB08u3O5<_|?=SK2nu3_o;WR9&A{*JkYR$d7yb(R^wbf?0H(|
z2X1!J^0Z9nxXlBhV1sKMc3&^>2Ab^tK{&PgCdKiQ>Yh}a46z%aH$m~DwyA}}1>cUY
zu+f1>rfTLb8ZhC++Qmf`5`K~n)aevnT<$|}zG0(Idn6h%+~6N*@wm9AyWJ1H7qG=U
zrs4^8B(APyEUTUJalApkF>!M74}ky4CipGRNmB^;~a
zNtAW*rjG7rUJsX-7sL7DhW1g`={t_o)!~{x>{BIw8bA#=gaY){#tSFtSWc`=@1Xw<
zQr>Y${r7+4qU=iq7}dLq#nI`{Bi+xlBO4ghCBwM&%egI(X9M)*TyVoFy^lC4;(Wv{
zzq%8osi5fFK+^(>z5RE{Gkb4Q{8c9AWKSVj#>hjUjFE>x^NqYk_qaN}M+IR)i;FcU)eakZG;
ziA+xyGjQoF-8f(Cq!v
zc3)bbj0cIN2_e`N52Dbfco3HZI)O>}p_rTGK@|2p4^n+2KC}|~9;DGUZ^REEI_qdq
zCJTQ<7YS61#9Af|wmPF$PQ%b+vM}|EFBAc<#NXj_Hq=0+!~b%0iCr4OiLaGGVe~EE
zq9QQLDwh%>bN{e
z?Fc>hWY?5V#7XngX(>chf6+Ra&m7cxwd~q=agGh`dg7H3KYVHE<0uK6(uYFG1^9
zqW?}GN3bxBCmM((hPyjf>!;$54H5)>JptR-#Rc`Sjgb)GQVVVFpikX4)JQ`-;^0{e
zS@!MMIRr`177rNf%O1=tjH65a7HZ>Djz5q^|aCb{*AaLhYH-=oawX8?K(z%B$Y@o_7-l~Fh
zwEJ;Y6=8}RB3C3?nY|nUCF9iP8w4$}wUxf<
z4CX0r98w1Hcjd^?$m;wZ_1+4k3|R2rDl|bWFGcg~Lfu40XyLED=SZc=WUNLkw8bF&
z>Ef`w6%UaPd9{?
zw9<}Y)*roD!#8v}ir%wDH)|erOm98lnCg1KIa{_`)%CFFBwUrkad_!+@-2NTqu#yu
zfk)Zxqq+pVkBImc9v6AhWQO$SDO|1mj+we|e*j|W
zhX76U6*1B8sW1_J-IOF8H}L5jvWQPvJ!0=Zp=L8AZFu<-ISRpA9U-tv7z?oi)4>)c
z2t%ghf4ieYAO4^@36@l8yjl#`(M+YfJH_$nSM$uM7=N9QZjj`fzD^x=%=!_FpnoSa
zAb#Gw>Fyef4SuInX=(*BY_b)=u(?(Mb4-<-yU~6AB&32p$5aV>rG=7Tgd9_~S$-)a
z%|LXwO3hF`ua723pb=0+bxC}K3|C&Me~Q+7d<_o)WvX5n#iBF3Puor
zWRET-l6Zjd1oE0vAm_Nn1nNyXjsG##eswyU{po2YC6)TM&
z@kL2hMZ>ae{17Kq-#5QUo2~r3gHQ>x=e(NC#f=W)>N?wrisz^hZ$RNE%cgGv?Jqjw
z#b25EYfM^EY0C)}lwOY1SAT{WzsVaD=#sexK7l8;P)`V={ChL-_m=*<*s?f}?CK$P
zJO^e$pQfM(tk;uNc~=@Bc3Nmn&?i@lA@DDbsmk|RiWQX|?q)Cy)y=FU4vtZ=oAkc`
zNb|RjWEb0Mp#9S1;vzSEs&$*^YWUQ>KTxLL$wn0aR7qpkEfS7|Dt_fd2NES
zVVxpSx-T<-n`4a86Jc?I1
z%N8UGN28DQ_Bl1AQ0+$?5Si{2dcaNqX#Rc*umy5N{X_9ip{~&oM`1QW-(fT{co&Z@
zNhX`;X{l5@HvA
z0q=Pad&loZ$~n2Dix4YeM&S_qy?&>6{)UyW55>sW2V&&w18pi_N;<0BKp*=i@~s>y
z`be`PiB=i}LHg0}Wkar%;p;O(#0!1!4|?W|h7tx*4WK{ju0ULPvEO;t-S5isbQ9Y~
znDbLngOXp-LD-;EL3#LL&gW^fcu9xPmq$i_Eoi59uaqP_q0|WXyO62Dz}4&)zPkE9?cuiE>MRMndd`ky-wC(Rxb9
zM33&~Xez)*i`I1d^H|*}@z-5&PKlyh!ClIJ6LX>SI`z
zC&H>)2iz6m!w=v%X}OTyNi>d|chC%knw)OjLz=3;B|_%}w4pMGp?E;bl|JIqc-Axr
z0;>d72)vNTEdW3h6+yqkRxhcNe5#?FMNQBH!*MF|>Z^HyWyn*5(tpU~!~xPt{nBvR
zrH5-5sIx`BO{DvlRN1oZqL=S8sS80wUW!XWmSge#YV6*v`&}quw{PtbEp!XIw2U4T
z?nQhBis}ULPiE6hmx3sSINn76oy18QFP&feUymZjv9BUL^hLKD>bNb|x7S~RW;ViW
z`#s$^M$-d*`%qLIZ7N?UcN>b3ETzG3irk5kUI9w|yx60O>KVRsC$8_MO%*koWa%%D@kkmu&Q!3u5EXs&0
zM+QTv$FSEuYV)xv0?v4)2s9I+BG4H@3g@4cE#f%P^?MQQ89}O5NpT}sGu%_-%dUJY
zK^_Lmx7*O_Cp#UHe1eROMr2Nxvk^Wzi55%rI6>VWo%f^8?eL71R
zPw{>PFF|>-A+3l#6HV_NNkybW0Q89wK?1Kih!?00PRxFcu1P0OCyU!%ez~8H$YZlMa2-ihS$YAJv-SqiW%DU3w+-58t+b^C04!XO03z7
zetSo)JmTUCf+DwRJ`X_cLtxkt#qZLWmm5*fMaugrI{0c~$U7GBIk>fmnxrepRq0cH
z2n;14;?=AibvDpf6U)UBwKI2F=v`jSAB`3B@r>L%p^zT>nNdNZVX`&Kh)%3Koz)5@
z5s$e#B5Sqa=j&=cxsh_B&LP!?icpA>3pFv*{Tvh#D)gX?RF0-gYSG%e!u6c^9F989
zR;{*L<@HQuOB22%`Om$7Q7cD-dbJ--#oB#;M!i#D1$87jzwfm{fIba~kDQXVotzHn
zF!8mR6n*OyQ&AsgRNYQ;rZhvZ?}>O;-T1P1oFb$oh$8glg1Vq=oxu?%=ws29>5B{$
z?dsH~qEr{3Nx>*OgRJ}tXPj^&SYS(L}C12u<
zfWjs6ZoFpzWp(;asJJdW=`XGqw=}HN+egR!L2pNli6P;r;TE1Ph`wqba{G_$r>Xpc
z_d<7f06BE}b_h{8ZG#36&)U7i0rIx}LGKroy4s-|)h%rgJr>vb&{J{E4?UHj{|TBO
z!k(c2mAeXn2`dR9G>0Li3Hq-zA8Dx2d|<*?AZGHNPULLrh_UqOwD}O~iMN$zcl7m%
z?y=rO3VkOGq=U?OUDG=>PxLYBrgzcf64#}}6MTT@m_3=QtdD}M*BAv@uOu$*^z(xH
zoS)?B@SBXhco}q$7SaU0a46~nlvkyaNIz2abfg!0pg0-0Dp%)T{)Zb+IP|LJND)+qp=y)K+^t^%=dN#Rt4hF`h&%t}{S{
z6CVoGTTgvH`*}LXYq!FUaocZ^@8Qw`TbacBkSP83CX^-Ot$ZAqh$BSmiiY!CV>UyX
z-k!bRIc|U0rk&A4_Dp_iTQoM(n>W~gns48MK6Oda5{Sw)T`+*D(I>h^`5BL5*NB6R
z$<=7)oWrs`gT`UDa5)N{sLJ!8+s{L+UeF3!XyUV1038J%;vt`XB4!Wl12LmuA4s(f
z(lC6z?s=oq16VE(H{(>xsP+KHv8I{^cy3xffDdC8U{xI*hD`#;>d?wHK=02as>os{
zfzLsL{x&92evPdZ4eS9fA>AHqj??VHd!o)Bya(#+!F%9d?ZLyIY7e1(6Pd7wG{YRI
z%>yUlV&7DLG?LO!9SU&fCND@pT56T;D1zXsh>Kr!&5q8mWREI+o==?GS>1ux6Wr{j
z65Ea%?TK>L!QsIvj;o-K;+q)ahK}3C?Jb?R-=T~q-r~fGoW3|wCdUj8b@FcA9U;DL
zgd2nDRv8?viaWtXKbbf^MNJ8Lw$5f`kicOV%^hDSTB<9%C5SIay$u
zE$}TvnkT{!;i0)n1d_Pmg-+CQ^A~+;;A^obKRSN#74%_J)=fVG7I6#5a5ybo74%6i
zb$UmiqM>sTwM-_gOLA?T$P;meK%Tt-=HC-^x8p2jBofZEN~uGvzr56dE*~@12#yUo
zB|RcmP#uLMrqYo%I!X-_>iky8UPzn5EuH+Jm~Zk0(8tnI-zr_P`B{n6J)N`%kEiVx>DQnU)Mrnp;<
z)<`_O`?@$+{q*7r8F7^Ph`#?cSt|Vzhw3zGDLa%eo@sid0s_t6Yf(Z1eJ^npd7;us
zHFFrY>~)r{(qaRTt5P^(4BS5H~)MHHcnGc`L=y{>j_HJ5dvVQ5@VsIv??#)iJf|J%Z$aJUuvg
zOm%%l>&N2!7$I8M@0?4r1b@6v6?1n3hRdn}F&CSDXj
z-NAWNIVo!~K;K@DS0OYRtTgFc@&f%#iJ>Wjk$DDxEqkp&e-pKFa2UnQ
zU}9G-H0Wna%u(OHZRG{}@1DM(#^w0-Fm#lw%}SUQ?d{&39(9LG`BBS49GZ{Iz2WUSmFM(h7$?_ImvNRqYD&+{*8
zt@EMr9%D;@FYP&g*Wqe&np+Fp^vqs+X$cTmr$M46(YEK;pXZ6ZR904IRi*&<%xwI=
zdm2zEGOO~5$cV^@$Tj8C!VO~;8OuP~T^jC(F3yx>jbaUGLSB}*5o{yDO9xc|l^~Kx
zt1=Uv0%rUHVMfdrR+@5~k8L18
zFWmsFo)@Zx>8`%x$59oMjt-9z?)YiD|0@@(LF_!jsMvXQQL*#r9$4%=?%87J2TOx5
zYXPzApv0?L?9|?+!vzm2gF39FB@wW5)2AW*zGy+nV(9)q@2hfRz7VXE0KEies>1d@M;KXBg7GUy8f|jY+fEac3SC@EDr9jXsgPyM
zh^iNe?oCG(?%6WpmpEt{sW8nJ5mVxT#sac69o*fVL4yG!`mO@tQB@;oGe*gaE?3am
zjBIm-*np(hOB)T~82?{Pms@@TDU;OoroE!JVz}dAmqJ5X$^D-&psx)Y+o6$aoMBGs
z5`v3&xAdjEA}eL8pAOy)3KQ#~6nKt~h=($HddDXREgBegNeB@49m)u}>Vy$^)d_O}
zX6%1IPd)r(xd034;QE|%5r#Rt2UeRQ)8~A0gG;4Uh#O(wpzmVfWg@#`8ks|1(+$wH
zo0=MnXp^CHiQ)~4t83uvjCVtnVRXsGMl@C;+2%qktGG|tp_)iW!x`1nUzc#P@1R`N
zj8kF-ZQ}87OefcE_cb6H@(vjST|{aQ*7sDZY3v>>wX7at6onpL6oejKE(VRlz^+=i
zziW?`i$VV;px`UWg`l4D8*@q|bqDZxM-xURp_q^$pp9=jyN8=wJpLgfc?6-3MxX`-
zmSJE`(qRP*iqrjQz~U~0M~HUhQLogcibBdIisH#7$_5iWq-Le&a?b`6xradNGR+2)
zJ7pb*;r*dhD%z7Hh}1Tz(St)TzIAj8YsM@FX$C^nl<9JaF?B*r
zU_Bi#pV+t@;ktmr`1u+fxCChtaOf-X3`WrC#++zF(ZCjK_03-uUvbLzlk&ntTh&Tm
zT8x~mGeLZF?{M=cSWZ#LHB22vRETvHP$A+BJQ+42A)EiCj2ro@MNZpYwQG2
zjOn~n5q`lHs-6U3`#mTeb>#M<*nk!CmR1W*?ybE&30Dwzut~(mGFA;*on!AaF@NEW_ou+r!Jl_{{{Uxn+GYdCgV87RKropy{hKe!}oNEQ1rrFVQ@CmyZ-#lbM
z^{w{zdr?%%hY=9UXA#V~Ol>eP>j$mGUio*1Qr|eU%HmlPhfMbJc}lvxpE_UR4VGb(
z80fZr)Xji>M;IN9YvXcUi
zv{7LQD8He=pq>whCOA%C9x}?QPDSJd95)ldi-kjq8R^^%DCW;2f}UT;pJ~!prcv!_
zYwq|~K);4d!E(qKazAQF4yvy&CI}cG$9bNx^V$(5?Lk2R=LSjOr%_Shhf!H@_~rph
zQ#Z>(Ij@D7hxG4i-#*V`JhlF%I5g^C3{$R2D>_Tk>h`SlUkEJw=r;=}m@*HgTR)8v
z8S#5eiJ{5o4&SZpd>jG6n)-4C1^UyRZP$DC8U;cBQFB)_^S+n%Ye*xyPn5>Rr%Km|
zt5!5yVNjBaj!>&#hI7^Gn(%G8C2||I+kUrX5>N&5;Aqplz4Hr_$13Ft76+>_WuU*@
zgagake_tuTx8lIeEQMK(CgAtE4^*R1`h%LX)dv6g83(U&z>dVN>(QCYGR3y>kDvK^
za}9dzvk1;hi|IA~x3VP|1K&DJy0+@OQIQ`OBPuS>O)(9i|rbZV*T#YVU2XXnN(T7)K#l@;|&(=X9%~Rtl&z6KW
zO~g4nwit5Z)cx%yr5SN<8d$9THDJ`47TT|Tl?%fP9x4tbAh#L<8j>7hSYaBG^ugyl
zZi%?Rk_396I*OVQ>nLik4?vCSvgSBeNC94n$uzvAcF>eI+tst+S;SK*r@IhIzxh@ipY&dYuw
z>xYooI}en_t0b-)90`l}%Gw@_EFN`L*iPW%yo#9#>cfV`vwX{^%lN5n@yxt3SURKu
z!E>I+AEjN`hCF+=EAp9If8efr%
zZO_Y*a)^w>h6$M4XMK{Ho}WZKOvlO_``CJNtncuQLe2z9`Dkjqj}8#H$!6mNBF4Sm
zVQ=@~LlBqE-w0r}`3nL3Hh&>?YhEA465@w
z>W%?qR+>~(2s>@wY!YHAg>G1HW-mfvRF9ECxz5dA9S48THebOTE61>1
z%XDKE^Zv?|UA!yS@r~KRXNZeu&e;i58R=S?fFW7FH&vwdh#h0!jQtz`%6hSf1RGIFGNkmK$Q|(42ArjZTgeZ9E8i2a)KF5FYA}B;Hgk9bE6g33l3LHl&^J-(%u@b^u`RTn!eze_ZN>PtVj@19Z0~%0Jd`wc
z!8h)%2YNyDi^MKJM1u#ER~PH*!DZu9KSrj=mtv>hh3&y)GrTZPiU5+Ar~zbjo}-WO{Mx{XXe2)WLzx#!AMF|(v!4ORhjAq+k*lOR
zWfw%o!Prt3oRtB7mu6YRH=8_*!%rtipH9$^?Uy!9N0IMW$s06YfVx5R1*kJj4y#7I
zxPwtr0q&{Z1az2pn|cG&43oo7c}+Cmdd(kpRi89+U8e0=eB$thU3{$oDQpf=ND(SZ
zXvt&VASY~;b-J|$7v9wN=xQ6>E
zm)2k5r`PfmH01hQ{z?ec@@T=IufuO~EJ@&D=SmZhD<
z15fz%Ww9tYlQWrBjE_&`=QWj$j1Uw%K)mA(Yv%Pa93-!h5(s}%d_ARl@e25g4Bo7a
zNOlYEe_*F%#)Zy?=K~g9@T;8Q7|AlD3tAqCcby|!dUSKsXUo~Mt9~hVHfrG6;;;|Y
zHnLNd%Qg{q92gi9li~v7O9)OMx|)h&DiuBwH@y;Q@(L;}mcRq?2Es0D#UHOSA{rZ^D1)@n|7}X_l(V}
z@b2-c>|Pb78Jkx*Wp$6w@tn6H2!@n$5ZpK$l8M6LHbKfD`;xoc8Ijg#**D2E&{LCW
zd(7|4^R|u>i!JEnpCN$9UiG3d=7ZnZ10P!w=&gBIM@j}J0TQAe=*mR)Ml$cG|_$}LIYyHUT$#RY(;8__l3C@RA)4t-Gepx)
zS>3E89kSd~K}YtgRot{Mq~RwE=;0lf4c%0(3x(loAPpJhjv1hGE0O%mva_14-
zF%8er5d)He0z)QMseQ&?7p|kAMyh4!pj5y_k|xO530b?&9a84PK27-C^hj2cVp3`t
z2f%(U%v6cJE?+$7z9NmGR8X5--10JF{&4HW{TrptBSZZ!Zz=jRJ)iOM|B7>f3GD1hr&S5B
zSiHdv)ds$&gK#UTD-eBP61$l@0JYu
zRjbyN&o709cy$cseLvB`3C
z)qN&kb@sM0RHr6RQk|MMNp)5y(S8g=3T-$hsLsl))0h|Dacy07x{sI0(@eRuqmnXm
zROiOv{5PK0jBy;(GYXHZJ!80r`VL0QSkf$%VM{{_-&vkdmib>aV>RDWY7)>v#{y-W
zXc=P2L!xzPjX={8)-?{Sltsp&tWl)j1}+=AyzG+&F3s%Y8``LaAVV7u{+QtEQFY-O
ztU@I_h;-{9q7gs_?9k{AQb
zte4?u?}eQXwR?so!>rJaR}#@n_e+f^88oIRteG4aU%6U;V0=8Hw)QND&83YJ?$9h{
zUyytsG~7~-R)GQr_V1X~UaNtk3RlkL0MnG`nRkSfwFyrzc}yx@%+xCxsMmmg-IMA3
z4)q)|z3RLDh<=2Y^z?#fuB=Ih4z$n()}*SK2xeIa>{
zMb=xKI9w>*52dm{N(rN69hQj>T#ijhmu}D~8A|Y-kYJ>|Qu~%EZd`w?Jbtp_A;N0#
z2m1foERxY29expIMH_2l+TX~B3f7oW2NAO20JqyS7(C-=7dr1tq@p!-KuQ$EDXZ!EB?U@6t7FR4!S=9_5l{S@yCgwCzzY_bkg^
zaS!_pF4HW_-kq{3G&id+s`zX;|1w1EL^=BO-JlAfhT%?9qy%4(1Z+0y;^0lTAi!;r
zm40XM3hC^vo!R+m50{ck{1AFXg#q81mQ%n;(S5}Rh3GSE8X6Y=51JP4fBdKTj&gMa
zL$s>@=_PkEoJ{D;J*PMjS>|x>^^~tM0NSaGFO5H{tN5;m-cG+x<~%HQgs>Bgdj|*p^47$
zeTo9c_(tugTh53AbWbEr@i}J4Zi%u_Ant_CUA;{a{ajh-NAOKM>R0MBsTkT
z4GgiOhH&EM%)n?I(F-=n#X4L&d$~@u6CLwWc|$nj3@dCI6N)qVGy&D)lLXX`Pm-^4
zD8x`ZJKauqqvJ&teD3)whur;ZtbMNeI!Dc!ZJGE_@(boW>!&Prg$XIPki^v9a=CBV
zriof+wuIm02Xrpse^o-$4Eql#tSs%0i?=X=@v-VU2O|Q_x!~R6!V2|mb4)ovPy0V0
zoIGEIl*9T%CKb_%WGdWq!GM`eOEts`0X7_l3&h2i$mr#Y+A385%xNEr@m1tYHxT8i
z?x0w!K85W2JT`XK4zBltQF4JJ75oqEdrlb;_XMaKJgjPK|K!p@9~a@SpEe_3ku(8c
zQ8eMcG7NE%^RE^6?hJDn3$0&qVsY<0RW?)c3DpJe3irMB<0aVC&))I612McRTd%>W
zD6`n^YtAWTXL7lSQO=w=Y}ne?{B3v(m;f&@^oV
zz&!49_u0!8j9=RolqIpRZ-$nv3%6=H4p(rFUc}@qogr(6t)Xg$uAy2$YbQY0a9==c
zdp)iKkH3J@R>rMurZ>m@q|q#pt6hdft6Ue*$}$DcnRnqCW4d?ZV_DoqM(T*f(vHBM
z?`UG=x=Ek8x!gFWJ$4u;&~zt9@WGf7$BTgocBCB$6+WgW}!nAhydjjF{?9V|;`x+&#{Z@LA0F
zw%Xk5E~0-z)1(hHNs~sXj+803ts0>+$4ut_p}qfd7E=i_
zH)*16WT_Ip;*sWV$fZFfXAs8T_H-!@ok(GyOxO?&p#tp
z!-Gk9EGqvuLoOU$s-|IT%VFQCCm>silTv5ut&wLyP|(#xsp_TROp#LQgfsx73UZHFf@(N*-j8_OVMVz~Svy4}`
zXNq{tRpdpI&il#~aj{gK_%n8em6xk8m5WvSUg|1nY?}BSUXA-f7tRgxZ*eZRzK^5@
zI5!|uPLw)Ogq!5j_dYGnw|+j}{0Sb>OJs5Lo@ur!!nc62BMz{%^>e{2WP~(KlM%$j
z+nBhM;QiQr-bLom$>psoR*|n@cw>CYuntYp<0t9aOv)xLewmCV_NgAI68|hcZAVR3
zEGbqpoL}Evh}j{=77ww%he;yuaOSc
ztT3qfTx?O*b{>xBzvGPr@e^@#g6l-Gu;tS{NIehdE8~H@Y!t?>dXL6B#|5wDG3WE{
zVw%%?gejyDKpQ&@c#TIm@23?<*oes?$V2rkhH(*~2ShrWDkcc=*u(hbqYTsvg!R$5
zSev-G8$k;goS1+vj3}12wsD8x_V&RG`E=Ml;t*0cMW9R(n6MQ-_F?Otd
zd_Yg1pHmyDmQ<)2zHv`-+BsTH2Hh1_WV~e5$z{P1O0!}7htO?&IZBzh9tsnF@J8Pk
zM+2nOe6#KxOKNl)5XXOHwWrtdJp%IZkjKbhRC9#(no{*&m`prq3>1?|jh2nTsN4pv
zwXl(-r~WXP2p|a$i}>@*CWf$SBnflWllwilARgLlGkMR)YBiYqWdJpM7
zkz_-w8Wl;C-cuA!dap9fgX=wahPlimktVv8d^7jbd(?cQ_r#fm5IC13;rhl(LY)#6
zXe&`)OZ&Z32K4uPJ+ucoLSd(*x-exL#)!FFQUeS3+R#3j;c9cF^=iY^G*T#7!K40$
zU0?0^p~luWY=kD-LbcjR)y4H9$_{xa*N(_BASOXOsVu&m^D!_!EIa;)YoK&!OwB`|
z9@>x&%^gwU$Lw26vV!3|)x
z!{n-do*1=?%9cK2$z@)2{T@}WsN8R3kzj_(rNer>qs@mBDOg-e&q+2Zwh01O#i+&O
z(*k9V!PpXC?Lh|MG*ipNYofD8Q%TJLRFnxv)10m%0dJEt2$e8q)P{k*0u(kZU#;op
z27pfys#ucX0M8FD$H%Y8>Z7W_
zTdWoxYrZ9^E!=NO;K&UaLqMNLr)}6fGN4IZUn~q)3^a
zVJ`EC^=2M>;r)ntCH6WA9PVzxy+ZniccLttfH_Vk2E=v)Ix4X*eqf!PG7^#yXQz$_
z$ObpS1H=n_mUz;vCj;DN<=~l+owD>`L`}X}TMOJ>E39ie$&GF>J~}C*>8y5>-3jQk
zM$8Lwo)ucA#v*NWbiA-#cnevR^X*1(8hGKDRi#y1ge{ZYaep(B_=c9#5KymcO|ddjf|LWgE>uvInt1zqw$MiT@|5Plp9yx1a!zf$Q$Sq
zBfo`vw$xxhEM-PL8?-cMjF~ucgYgsWBo$>=2e%Pj%r)UFY|zDqq#3Sc(hOH;m|S%U
zUEBs&a$gXxkwic9+zZ1Ms<=$_qpg8dx*iNtUmY6|8I7z9i={B;hrtijpX%qcAHtC*
z3s-RWRK4O2xS)numC!VB7ehYnD79|J%adua;%5h}W2xGS^+7O3edS1`LAN%CeMHBA
zq#3N7Ycp6$@rb(B&M;RJA~|U0vG0RbL94EG3Ff4hxu`&-ffF-Ft^QQ{&QD^*h1V5O
z!JF+*Z=ItSoqyD04~0*_D)#ClIj#%y!sH_!U7Jm$N2sLv=CI#
zsCnwQp@Gt^hQ?%TS>dBLTpzW;+K!P8yaXNGGxN)49r4clw4m1Dpxq|6p<=+e*^ZQ1~c&Dy&CD{Mb!x
zcE{Mwaqm~O2G)15!0d%Dr08(4c?MYNz@QnG)IFTI+@P=61=vFhcy@`{j>)6u*}IB3
zzLR8b6_as(=8m%Y6T*`pL5Up(Nz?oe9ccLkGg7~YY4CAv9qWa-?6becr`tCP$(ev=$Sk-QTvE8sWlr-%^
zVF%08;fX?FW|_x4mS5#PS0+=nJ(L!@i8DZ*vS$TqJ}z*56*N5Je%K(;en>V5|92@4
zL&sl83nKF>qj@Nsh-yCx+dAWuOlkigtWqS8YWIg*1z&*AGc9O*S5f4=@G9I;k
zYamhE)J_+#^sX6Fh7)Z)PFsC~I$GK7_KIwuZyo
z;s}9hRQx`c-85B6xc4xe?rY=#pUPFqwEb19U>l>Ab3T2NE&Hp<3(=V%^re{POgYxV
zs{|M0n@d!~0ixI9Mj)NSS}`F%!l8=q77kH-yKsmWaU~!QEBJpn%?%>g;l79~5%DA(
zu8W8S=G^E>Xz#Wr5R1FjSk8!F4LrcJ<~0b+Xfz`WdDXf~cdWBS1mj=15&L`EK&FNS
zQHL}U!T64lAie635$bIsc9dQBMjzXuN|23T8@39E(__lUuX;br+lnF~e`n4M%7z>A
zuX))Tp_}ZwP#n)ExA%!Qd0c$&8`zLx7<=+0L`)2uJOPh7lkD(}*uc);5n5M2$pkl17@gO~@H6PZW|ip>mda
z%p*3Lk~8~QnLKS=w-br$Dx2)l%`uo6a@C|06s^Z_bHZ4Q2nTSkQY`Ysqn?#imffUn
zKH5IR_zXPjda^X}cq3+7iuw6*J2`=8>Jmd#p^JMpR5o<@vA2=%sml@=h6MmGcn9?Emre
z=H7Gu@3F*hm;=2e%94LRMb8X&Dq>{k!*DQ_m>BaUQ3#Qw*a4M8HvI7;t2{?^Tl6|d
zZf+c@uF*xG7D;exu;a(g^u
zfAP6iG1BuHr$wkzo0g5>=l!p<{@2x&h-2~=yMcc1{a;sCOl&FSx%;H?ox!J!gWjji
z+$8||)z0c#ER)XXp1Dgze0ZO0<~Gs!T5afyx4*t|*o(p5EV>j2sE#EJ(F|}(a{e2F
zn$ju{J!afv^z}28^rQeEs9QhT{qum2@gEMu@)i?8T++6pxFl_baY>qo<1`qT-1Bf8
zakn*$ORjl1=6<7qtg@DVJq8jZs@q~XjNcTbqKZ6@Q^3gSqW&l<`V&jcWV^Y9cBRq%
zyeyT#_$+3SYN1#JNWX5pq(q1s%2t3H!d7@1!aQ(F6h1-A8t!@EtX;;YkKeu5m4{7p
za8UN({q?vFn!LF9ao`DbJh}zZ1W%$f6`pA(0I6DGNupLrI^$(ok7*jSoM#sEh_$OB
zX`d^Pr?qxskE*|;|0eRzDt|h1t9!$jL4;3f
ze(ZB(-VA9v(=^$90qXd|2Z-YU2oUG!C2l`bLlJHp7T}(vmsZ24nE|djimCGz6}IwE
zZJClaAFOaNXDaGinWpNA@@_}TQs-4@`pOXby}WI8N$QSlT04|Nnb?kIEcA0swT{FL
z7}ug>p-vlZzHT-7H`}
z<)|lSBJ!ongxXN4h?-HUXqr)387y&WHCX~G-C5=_k3?q6_miV_?a(sivd$vXQ0TaN
zOGA5ap9XO1_GQqde$yX-QWB72ZGWz_n*L-W5?T`D$J(GR+$t!iKN`k|_RsE+Car>w
z+j{m~sE$1i3v+_;vA4l5P45?!6h>4&YI{o_jBf*rnH_CoJDToi)2urTQIqa4G)=n0
z&^*qLX1Fi3qs2@&!}LD7!?fm^|GLjRD#Es#6tV0d9q)4+c!bagup^ckxa0B(naJbr
zV2)MAI5x(=<*lwrN-ZPVVN`az(rmKNw;|UlJN{lM#2loLV>L(~hi#BN9l
zm2S96PLO*#f+NA^AlGyV`@!b@qhI@bAH%raJno~?4!QTAC+IsaTNWV3oZ#t58i@}t
zuF$+ZLl0KH0N|#uwSa0O!0lgA2$;Wr8GEYH%E!Ay^CfxWCavg_HDb*&YlN7kN=KGs
zqO?KGa!*H=4xWEfxX0b=ST
zj_zzInR{`hHCpcW6*fAQ4pjoqwCfd2d~i4|fHH)l(qMMHPjZpJ~|rT-pvaX@E~85*NB*U7bq*I{oyuxfa^LO;oH39
z0t~(FpK$|tF@OYzuL9Xr&dEp-w{6wYpfW%=SB-=7!@${
zH`_pSH60>r0*!F9?LC4{fV?$L*9IF+)`pwvs7XSuh>~zqnQI2~NSv$dzJPq(XzgS&
z5LFw-t@WzWzt29hz2VgecObIHc5XaXb;rCi)DWOK+FFDqGQdL)^(A0owJW4Wjh!8vZHHPw{`dx|cY5AM0t7L-P#LL~)?f
zJV<)7*L^YXV~!jj^Xp4{a_sB!oK$k#8cYso~FiFEo~yT}szbaL4L
z$In632gm}T4^Ra#AE3&IJPmdh*Wrw|>cIrK=R>|&?Y45w$2{izmQ%(*Iku{T-ZYv~
zP~U5UdV!7|Ovqc-eQjPI_m(B$TQw>`zW0mbkZrl0bk8rJan<9VQU-UZm&&r
zEM2qgSh8l}v1IwulOQ~nd%pDe*$s|JTCVxh<7GE!;Ta;Y3bA5oVgn71tQA-sKnqS^
zW}gRaLT?)I@y;HkHt!Dy;~DfX+DOis_N;QBo1_g{)5wCBUia88CgWi-1$f54Q3?mj
zkdXwLxn_$0f-C>`SpIiie!=Z|q?Ph#SVLx3Hhw>2n|g4xf52E}@`X$ueMlrrck&0u
zpI#4;h@mzk@4=aBrXK$LZX(z_dfUgl$0vvE)Un>%4x8Z`4gu=8SOkdU!Vw_O5s?<*
z2yo94k(D2VJ4=9Tj)-)=%4V3fvlxgGzx#u)qno=M-QD1L@CWfJwtJFd4(<*Br|y}i
z_lHLqut~>b{40pK({Dhwj!03bMk5U%hVjxAxkDMptj98rSC23Ut8@li@al2T!7910
zc;VLY`^v$pnsZm|AQO7{$IrZ;Mo!f2hKz6$2HTTARyswf4{+-_Q>En-)F2<+-JF2~
zAXoOZIXFBr(F=5Eky_{hP4B(Jbs~Tl+-rM18DBj!+raUBFr8b^f}07gGnIHFS=brw
zs@&$FjPrN(@*g}n#ve{&U1P$>43*ar<*&Mjr3eJZuciOFt9<+srC>=iQBt-DMM>Bq6(wP=
zShQ?$g5Q#Ru2_U42p-d1slb%^4|fQu6xDzH+{5iY^Q?_ZzEK0a{51>Q00j)9a29_M
z-ZDf4;gOT?CVX>zL?dpe>c%k2eE{K=O)VvC#qw{9Q`%RAz<
zS3vDq19hpvJ>71BE^&Tq9KHmmcxSQMRD8UMpATn-Mayz~tWtt6(6P49X(90X9+^Q3
zwT!pwZqBBGXOn{=whG2qSKHBJveUA0v)H`6qbqk^lmgp5IN9#~vW_Y~&MI!X=*0|v
zsRiA^@3a6t_?;xoYu()l^dR>n%r{6+kZBU+MR)J;pXlyt*YC1<=GM+`1vSRSK+VBy
zHk|UVP2%BVxa|CXi7?NwkgrbAQFd}&(Dof%>lhY4MCwQR0dR%@6c6)<#nH#VFSCA8
zN!;b&9HFS;5b%&+EuD`DA?IO+5dpEkDXm+8=UkQzujB^dr;;;6ebSH
zT9h^*V^P{9*`h1We*o+oIS%pr*fh^teYy32YpJ6#u1UgWhUQ65&2J->#^nO|X=KR=KNiaZ;If4TMC6n~ymbA`;tFAHzW;`x|n3U}CRh;?p
zEQAjOkab>g4BTB|#uTsL!4a83n#o$SLbYSdhW;HgvVij`K+vrakdw=z=wbZJA?^X1
zP{fOwx@F*8?yC|n>3lLp2dH@@{lQs|-qzOo$$J0OG5V}-MVczd$y>1OF>gV$N1cJ^
z6f}F>llBUQycNGaZTx*?;F(*7I^2^j<3tK_n5ady>nP?+92v-kY$m$~dxX)Nq
z2M}uC;~z>ffKcd-gXi8=@BmGtOBh|U0nym5!bi1gmA}nyCu3ZirH6wk6s4A(TS-v;
zU@)V>{5f_rTqt-!qessih!q2?ywMQj<1g{s3;85U{+1Am<7I^+9{4K^#q+ysHE~4p
z+$k7?40FY+YrNDDRFKe6e$Xg`Dqizurk2*t6QiR0go*^e)zwNUlBp%lcIpH>=HkwAyq+(qd
zZ(K4!xPw?RBKXwaq>eU(LT@~i^U;7;RI6J<4OB0tqd&0oi0Y@BE!o-KNECHschLvn
z&L&ezLVX{LS1SOE?&hhs?_Tq@BB^9Y^!TA@e?*T9ImWMa`ewn^sEerX(W{EF9$iav5K4$agJOF2{BdFJp(|N44Z(__eR2iC8g}8
z3o_$Bm!lz~J@`Q~Xz5qrTv(E~alN_?1>uZ?ApD{81HI+a)c^8%bp9F28V7TduQjya
zhCih9cJW=w$)lkKk!Prjp(`qS{3_3h?vsNH6ujVfqcf^Akx*4=IxlotLvJv?8onz!
z&x_UP#TqUUdtSVLE@ydfgV^ty0MR}!cWs2ePZ>qNPZ$NhPnfqk7+uRgM%6Z1xZPo2NSg+w}GVOo(Gd~@X$c77r7)x@fG7-zpo1QuHb&JT3X(G5pLu9Xu^B@4BJ&*f;M6nX3n<6;N3i5TBjC+c!o
zP~mVu8BsVba8otvos{KtL`APK8l(K;`|DSQ&8|PYn7;4gbz$S_nqZkQ7as%Tzf*T?
z%o;U>bupUH7>sCC$XoS9g}PN$RH!qwMVhLpaL>>d;kZ)pePn10&e`c7(5fm-{-6~8
z(9WntZ}|sq6c@M}sDFO_Ti;xPsuhS4d%*T?JRjjq9A8lGIG_%w;8!`q(+6)lD;41K
zj`+@aU-n@7jSemZ68{HZU9PUw$lG;J5)+T~IKCX}T|Cf{UL)T5nElPYpIBV9zOfgn
z78i*#Yh3$EEADIGXvKc*8;ST&!+wo>BL0J}cJ#F*!e39>xZ3&94;@`+qyKU=MI9ZW
zCp{FLUN216t%wJI;R`gU(yhXgaj=c??a_9jj<&zA6l@>l3W5Gcx(w(qq>DgxPOaW)
zrU+E#-^x7fN7qEaea3d4){oY=2_0(>lRhIhdl(7x>)Sr^(p2jh^i3F`fs8U7Tu=9G
zg4=@2J5`=b`5h15@YT=g)a~66N$0v=S^)^+x)2mb!y2SrLqlp-IqRK_zu;~OBrMtc
ze&}t};vB&J{%Yf!5S%vv@t483TCyh??;UOKn7oF)Bi7`EGoT}+VZ4QyhJhBMOw_Sv
zK>;-B?&&ATHO|<4x%IyRmn1ajL?vs6!<@C_DiNDsjCm_j6uJXcoB-RG!EZwtq1s-M
z5R4BWVuXe;TFMMj!UnX!rI@02Oh-=e8Z>e>GqydFM1-%bO@ft^21n{AuOYYxhsD@TXVZ3ai)rqU6t&%-&#pe7Cb!
z;rAAlYn>k}41dJm-gbYia9k(H*Q;+U^V`55S6AM=u5jcP+OJ=|TCK3$!XGjIYPa*I
z!j_k0ue@IAu2uN%;IE&?*GO%m(ZP!R=I~MITbNg70olz
z$Lvj~bbOhKf$MHAP)qq6SN!5`%K!M%y3LE>U$QHssmIiP3@(5z%AOh{fG)rUJ*2o7
z1=69L@YSOA@y407kcuo#n}RA$nu4h642+g+`EN3!DsygOYCjG*m{pl{AJ2ZP?FS;N
zBjs$_iobHJ&b_rhG&K-qbo}?%`hYsd|MRqd7hN0v@|SF_Uw2}wpwNo?IGRouBTo^i
zl6i_umDK4Xe4>qUzLhCi+?)f}^kUm*JEzToS6y%<)m?LUA
z$TV3on<+1@mg5qds-;cL3(!o7dSw9%`YIh%hByUKhBgIEhBg^URGnsJVgYEo?uL6Z
zkc4~KWvVev22y3pO3#~6CePH&#cP8b94gP{*p2l`CR
z3qjg<8-=1l2-3JW3Pm6om&UbGDmZ7S7fnS9bg#2}NP*7c;&ICq&_Y&~ZmTgI0H#&+
z{*A#fHr=EIs&5Rx-j47sISD$SPp|O>oIUTQ7aEanQ{_RX(!CfYj@CeC#
zad7_IS5o1qaEPJ|oDxZH6huWOkxO4&$f6otNuBANt3*%bXO?uJZw&e@Lm8;*s;g?VPvC52w?~6k~i6
z{Q`FQo4!#&`q-On7q`c6F`1U2&Unj{-AO8|>y6o4yRhd7|fBPsaQH^+un>(a0AW7{C3I)e-SWmoTE!oj;
zkH-D47+)Is`b{QsRm}RY_fRqR%L}L&``rapjQ#GTs2Iz=QN`3P!A1>ZnYL;e#3i9+
z#Gf*Cino(%$sHEJLriu0Ad>GX)f8M^PixchAp|&!eODao{tuJ{xvUbY?Kp{on-Khr
zyJ$VcvcG%0DT(S*#)PYujt=*bk$e*EW)S~E7$|Z2FgW7$jewvfWB%Fw$7{w6*^6^;
z1cc$t|JLKyai)!caGBaEuPJbB>{2mZ%jF3=op!6Y$;t@mOnY3&KUp%IMdDkRcVpaJ
zIzeL)?GMPI*NDgc%|ons)j1=%1=C
z-lUi#J4CA9R3gcX;*_>VSm|ng|s~eg=k<^c2B8uf)!>gGD`(a
z>H-g_G-ZUjpD89r+v(la_>1(6>HE)YN--cgfO&^q7U`Rk?qf<{$(*58+&I{KRh*%D
z&U$x6@9AG{Bww6mR^RIKjnIITqC;k;oAZ8e^}k>LkFO**c5(d-RHGPm2w`dvRQGM4
zD1<V3t+GE
zVGj6!JVZb;z=z(LVo=^2d~YJ)J4HGbJc?%Ul|*syl{9hil{Ak5zLNVw;PWj`1-_E$
z{lKUEh^_r*g@?}ra8rLx$JzDdioITS{e(puz!y<=_Jn{gsa2E2X{iRG&hCjsjE_i)
zIgG$iqcP%%Ji$`X>qR&eT%+JGg?f^GKF5N8tx0P{9(^Xz@!`o
zP?CWtET$#{9Z+%8)`j%MetB1rW(=6p`
zkl58tS#(d)CM2HuiwdhQfW#jq2v-N(l~!B71Sc-3(r
z)`{altkcGUSf|YbqFG=6)L)~g&OHl~{()zdYc?j`^7c3;b>kkW$JzqJ+N*4=Q;pa{;dGmxEK4%q>}-_PN-E{WHs$1($+H*fM(Wd
z%>5GY=#;ZHAP;2quDo3A+#y8>J$G>9$py-`>3h)rR}H|MHtX}r_1%p$7_%1TD+W_O
z4z4fL7(xS9EztnW*JSzg9c~!InacxB^G%^NIPFu{#MKsV_m!{8Uo}h8qH3Dshb`PL
z`mD((fj5HDTFl%PYh7#}?)5ibHL3O*ZQQn~k;WB!jWo-$DC1XQ!?ead%d#l^igqnn
zHLh85#W}kb?GGzhYY#72BC8K9SP)jRi~#H;xr!U?_wySu{&$e8@O?93G_5skSRU}!
z8uqIi>0`>3nRDWHRqJ#fdlT7mrEAc|VtQD)T77uA5>b6%xq_?)<;vfuT3n7r_bE0W
z!gnu6kgIE)-!M-QZFw(?Py09-SwZ3fZu4I6ZM^S_W4^z=zuDjT)H^=u?`KWE5E$a!rqJae6U9{wEs|;eK7D6>@yNEh6v~iSc+MvYN5^t)>g<
zYPyix86?V4i&0s7zP!!PJIM~qsD8S{3ET4~iV@uR88j0JEWK}z8A;rBEpV-*_B1PpK3A+Go+X>ewu1}
zo1vQCHW*Z%?7nR>VlT)jz`t2gO#WoM8G{T4^1_I!C;emF)@
zW4eG?iC{f~qavq74}0(=lKQ}61yRist7vAGIyPH4R`7kq>UD-#y-pXa*Xd$qXYeRu
zW#*j7JmUX*Vx^xhm1lWWrn0OaHuTowI{QX84JkQ3{xlYUt2mjU+Wa@Tb4WInKbcf~
zdjZybr2NCRA3pCidH-!3rHlaMvwq*@m|;T096t%?F{Vlz#?Q)QOx?t^d*5V3i>r?D
z$A6LyEtvoqzsxTEzBY8sxnHX~_g$M|6iQvH6UW{AI&Iv)uhV8((Jh;OoqN`9AKvWi
zOtW@-J>|za5HNnT=b#y{IjWTwOloOWf-xiE(*bUl-(q8pm>x96PmAlUPP@*+_^`0q
z5C0)@uk&>l#{cs|lJNU6KI4EP&)?5qdK8_7@p-5j^88b^mQ71b(OM?UER8l@YuQPp
z*(RA<%gj2BdBm3TwU$o(OXTU>QYrdkiryn`O+`1D9Ngu7Xb76u9p`S$a|UWs&5pd{
z2?}t1)(JW5uk2RZJ3Q@gG;gJK;`mltr;UTMPWzBsX`Or4RvHPF*SY5IrEaLa0hMLS
zu(!Z7T36MO4k`Q)d9ox5
z^JH0cr;?&^TQ-RJ%u|@hlF>q3Go(@GEYg^szVD&3i0lx4E>~=0&?l^y6JYT>pg#$P
zjb4@a%1sqU0$RHbk)9gYtbL%|>cbhvHSSsaK%{h}#xw(Xz`W;EEwT@=+d*gp@Uhnt
zcl?*aUXJ=RMrH!`nyN;;g|stBQcQLsk+c)6<*aef!(JlOg|LV4z1DlWS1tE%CW4k(
z8`>#f)%~$ve>ju8vK9PS-S)+-4Q!tb_OVNwoUuC8FS`NKZB(F3)i5hfp!d+;mU$`A
ztpD9zd)Hn4pZD)qemG;24=*y!VdH<}{lb>jF2UZ;(3-*wt7722|W
z*STlG7?%_MU&?4=Cex;IJ?dPuaNPO&mZ@_1*S39^#qqv_XL7MCl|ykGdLOgph3%(3FS=hK~(aVwHa17nE-jK>5bADs8G;2xxWU`2Jm|jf1jI`;hy0
zoqLv589srpGtJ+=%XGViwr^9;ooZCZO546KC|@rCN}DK_0!owjl}4KmN;`=(#nYlG
zef*eNr!kLc$~x0UK$)N^%cCsmigY!d+})bEjGQF}qv)$zVb)uN)%7Jn=^otrXG!5<
zAL>YH_fm?r5Jgkn?82ilw$|G0bsnm3=$ENhiNnCMCOq=tOx0PHvC!0_=v<|eMrZ`
zum6i6Z9}LDI5h#$B+_I^+ZiOHE)UXX&WX$;_Ou7-%ph(?6gO^9o3d#yVCF*_Y2b~O
zX8)1)H1bp{=ShuyR_erYi@Hu5hjpDc%cgFDb)9>bO&u|*>s;mel7-~~OlniN+=lCx
zexCm;aNXFX!(U6&@gk(H>$K^(wv$LhNhYq%tkamstm??~B{F>wt2%t@R=eP&TaO-B
zV$uIAaNT%r=dWc`my9}XIp<9XyHfLyQwCS+6lSo5JCale@)0juB>-u}kwL(zyE!Uqmlqa3qhUSqwqX&VGAVh2x3
z0?(FXSci{a0!(udZDmjadh^@)HR=U$ocno#Ly5z!6V29
zuiv2Vvhx+Sl=2DE+~xN-`uA?<_3LNC0GFnAzM>;)g~4n6^)>J7W+3%-d}Y;{#cO>B
z>oSkBIk8v8UkhBsc+}fo-{08V#&4U*+}}Uk+OGWhJ&v`Py7SGS^t(Z0(ZS8x^$-(Y
zDVA0OAC!FFql{yT4Z*=#^?N|IDaW_J>w*$H&o`Jx@6*y8D>4}`-3-1ydx;UAd54(z
zbaUrJAG60#{f~!xxa>7>9a4ZSAT|N2fV>2#as)*ybHETN;Qv)6C%`>NWHfi*BMorP
zk(qMN?ja9F;$nC`_=X
z!iCcczON2
ze|~e($7S=y5?=Y>;{U^Y6YaK%M`FXLXO7U}QT5Hwb)jpPx~=WK^}i>GouX@%J4Mzi
zc$HBTEhLhq37$LG4CXbLxhi~
z9OJj`+Ws3YwNa0&6Vf@+T{vv|YI&+`hZWDUDtGS2)=Ji@cq*f2Y-ufZ{*F4;V`R~o9#P@d9EemiRzkD8@e@1fK4K7!rwKgkkceuMLd$&zca(*{ehOpp4
zjAOY68_Cey1Ad$LCx1rS`@msTEWx^^sd~KCTi<`C2Vy%k01u|E-3`;p
z?UbgpWL)!N2H3eALel79Fwdux>uXF++roRt8-G)CFqQZY0rOPH!>^L^O!gqg_-qLD
zqS!I<7(T#rx!#cNd-xStoL&CUa6EvIh)$w2zML0DS&x4$)%cjr<>=~8S+#J)X|SVB
zzz{wqnBPob$&>l4j(*$=-tXZS=5F6E?anW-Y<*bQ=)${hjVz4*8d?6ntDv;9()DWP
z@qTLD^U>d}!@tILQTVSy0PX{SrLKVr0sMmKKO_A9MD$bd|0|(i2R|Zlk8gY?&^O;m)dH_!O6hiG>UY@Nzh1>!>*_i`n3uA<|+t
zr}c=)@9^e!{!JpEFkojm$Qg{kc>(JgV$LwcVVZ~ueJyvJz<>_$yHr=A!U|wpD&eip
zheW~Gzp!*RK{)&K=<2f+g{KKHQ9$ukWtvc*t
zy`^03LMupJ_o~?olL@~iS1tu!oqEaiguaZ>uIn>znHv`)oSI$GTY*C$RX}`(k`xZY
z#fa+(zk)|>T$4LEG#LM|R~&8kb`E>{>j#_L#o@u;-#z&}-u$?|h0O&*vb(jn-Twfe
zA!I0p=mPQ?A`9#>A+m+{m`>+aRr*8R^YcKVnaJaJB+dbLE
zSw#Qi-;YnWd)vpm#|?`U`9gG+BJ|PaiqI#on^vch<%)1mUN^s2kXo(?*W`8MoOjBD
zg@e1BGiU`g#l;!gbcEoBjzG9ND3(g%nA!=3*2!AbA$2ox^K
zq+eX$PW$7#o4y$X^v|FOAOu%
zu^ip284j*-SP6v#-3B$J=YjD-*!-k*#vQWI%(}t~$BS)jWFMfGLt8|NlyGyv_)SlA
zfbh~gWXu%Xo0~lIbb=;I-KzH{EsfOc2C
zkLZ$Kb8c=j7O(6s4nf2h^-Z;|m3=~AI;!a_gW}dvwZo|`W^;WX*N|i9;Fe7N&xh~r
zpW@Ts@9+-Tuo2@+Yw5||oCxI4h#N7KgqSgb!*FX5QFWB4N
zZqh40WmKW~gi%f66DF$=ZC^EO5}$jr3enuXV;QALe5T17q%!4Ib1Z{6IydR(g%q>{
zEWZtJv8vqdb+PXVYYPy-K4YuS+rbru8nRHDZ@`3=dkrzbNLgrz5t6eqyRHWiBEdFL
z0u%yBytP3R2Mn0`P01=4s3}o4?4V+doB`iohv#=T|G>Yq_Og&y)qTP5A=_a#>@&q+
z`kqb@6AMOcr;2Cg_{uO+b`=Am954KJN}#cvo?{BP*Q0a12-s@s*4|=?-{q-lbwbae
z)4stXvVuIujlM9B&IcTyVQIcx^@=gXKo0!1S%t67zYH))
z?;nqP>MaWaDb;uM`_%zkuAzN<6lAGSAPvN|*+Zr(ltk%eS&
zIpq4^QKqJoKSmd_@}r9{f)%yshkR{Z$xV4b@>RjE5=1Rd8@v<4gE5bDu5ydnp)
zA(L^5Uhx_s^Au-b)3|neIk&bqK7A1HD6){f?Var&!VY3NWhMZ{^HN2t
zN2`yi_7{wGS~3U?dN4tUkn3_>{k;SCdvZc~ZVb-yHBv>JFcIF5XRph9!zPS)1do{@
zP?wj*#Ec#oNr?yqiayPVA~oUNU)+Fc3BgH0%bBYQgy|fD
zflC`9loTv{0U*2LwAHHj#V*8Q5R{wSRoF-uoqN%2bxxp>0FHL)r#RWxsZ=RB`4d&D%KH0`DpjqXqZ%~WDhJ!tr!~SxygLjVq3+P-pxmgX
zsQD0?t$Z)-e>^)i_zH4BZl>&N(sdq8FscZH@VA-Dh?G5gfEeG_&j|kA-qNqp$(%GE
zzTxl46X`6k!8y?ZNH}L?!283*EVUn~=n(8#@S1%Y+?Ja-Ob}>Nx{H&G3q3q622+p3
zf;|M8;27alKzN_wfZ)RLkx7ka?-Wx;?>pG{;WObTRT+nWT2X&mb^f%b{`5*5QH;+i
zk@U6tI~qQ8QBJ9imB_H2cg42KHjNM*A*RRBpTwXMQ@$9|^_Hur-?FBu1JiB~@!6#xrLJsP#*YG0l?=&w!cKuTyv~ukU7`vB=tO=i$Hrzg%CBX3Q5kmy@o|
z%I`dxGAS2weIDX0O4uX-K)6sMbw_I4(91abC0H0T74oRjVMgkcR$3(hTN@ubFD?Mg
zS^vwqNQRU*s3^ZX1wI^t@1q$LCSYb?-(4s_cK(GmfET=pjo)XY2i_LtLG*}mYrjmU
z7l
z*)_bBz9y#W;$f!TRVjTU8ql*E_Zncp!x`?d^_SE;HMJ8u-E3Y#eBQKT__%3>O71By
z&7(1o>(@-XbI(&)?f|i6H&5i!CjV@wtfEhqv;?~sbDx8Pz$qcs1_e_cKJkp^A3tv%
z8+|2_O1RZX&A7V4Ar=(PbaDgRV2bk{XsJI&15tCkhm`zz|G(t)OzX%l)7C`^vimaj
z{f!Ts`&%#m`FkJ1tkGE?zB^9rIHdlBd+2}l&0M4;V?42Dg1X>@qhbd|(8AV|=!&T8
z$&7ttbY(%eZESbgv2EM7ZQEAINyoO;v2EM7opfxy)8Bo#cI@7O3GgpOD)MtZXeJ{t3n;3-+OPAWg;D!3R
z_3d}~?N*kKnHj|8PBFJfpLd&TG)O!I(;g%09-gxYR6+=e#y@~|3(AZGPBcExY7vKg
zw{xeDjZrs@1xzln;1gZ#1~)a5zDLT
zocC)S?vM~eLO@GD
z&zvk=bZo%xKDw7fpy2s_bnp=+%1h^3v_L*XCE1N#4clQwZ%H
zN`k;Gj4Ym&4=DXcV*tAk_v}*(?N0B!;LZH1Q6b|gdiC}UnRUr14M@uj!Qcjhwr)z}
z&gK8)^lh>5KA1C(oHlC-l!Z#s9M~Z84l=uFn2nM|6$^DB?6?ms_k?5db?=^6zlwG^
zKv-+*iGUzK*q4~-A|Wcu6Wl|-NF
zZFR3_6pYO&uXNKg9?BEgUgY45dIn#Md*tMGc>>{#{y`Ac+jGf`2%sEfXYl1iXA0TnJT-bzS
z6mq3gXcU%p-!2xcXJQDdF$lztPw{z?1Ky*tjy^X-)#JsE5|(_rd6&H_?IWeD*hq5M
z_PBV#vDX!-z*#ELAV6g(Cd9(tzN$@HN9oa!Qwu?&$(C$*aLQZFMTG`+j$xP}<$z3$
z90`K;ob|hyuWDw0huO8mT3Nh+JDxAw5i|JseZRZ!D_Xs3h8
zostyIf_@Iq(K11$H&x1pVR>yx8bTr}D0)YTQN9$sCFDTaL;|CCt{O-+!Yu&B5$*eQ|*G=
z+FlC5>GyIfDVD;fSapq5FnIFapp0e5#!@7oEC0buqs!r%jbjGq<7?P|I57OU1Li*3
z*&6ZF83IJGXff;gKnMzk&|fIi1RXS4g-!Pas8cT3RGX^OmC
zj6|N$^t)Z1@qO<@hD3T`3j>9&poeq#ZR!d;?yjfU^&FXZncd}Mi$8C|Q%&EhY&KP1
z=!FQdst&o92rl->M2qXiCWhjqUXx1p8PRV|d92>JxIN?vQKW3)&)1_vJ1w19JF9Yq
zuM#FXS1Zcj)($WH#$ySnUiX+vR-7ckI%B~oW6SN(?|kKwHmx~A0j=L}sNF^L)J)(J
z;uD=uOPz}mJwdqYsuf6FGaw?Q<2vcSF?ZOO{!1*zQL&{pQ)}$-i;*XU2VZYv$0J|c
zf4}TFN{~yUj26wYhRWpABA3jv-Zq`<&WBj~=?O6^%*MG&_AaM}61F=O@_*qbP@;ZT
zXntGO8{HMY>z5QHU*P9`J)3^k&tJZ0!H`Wv%!ix#iW
z??%4inkyT+ThIywdI_wF@l5MsJxBRT&5iHn+gf;fHMZ+mmQz4s`yzx?1^*zp$Tmw}xI)p`UNzgxtBK}rE!7%e
z&E&I`wML^C6+&TCcGc)t#E+-}gi@f8PZ{mExE(WGPhoM7#cuCiU5PDBbtTCoTn9Y+
z3!VUO1mO#oaI72L#?YYRlhZ=CxcN+0D)f)6J4_q`vn&S_OfTlnn&B=^#t)p8kUGSo
zTs>^Qr?uG+ajyaA>YKf4@;HN!)VrweTb^k{VR;#F^Cn>q=|5}9N@gVThCU_od$V6g
zPo6i}rv8%I5Oe#(P{{~SmrR3Pr*p4ckH6sIib%TL4E(_=HjJq%`eFD7Qn|^vm^hBGy);sH2qSo~#ucEDQC7=jM{h|T|BN!GY
znWPGlo7yQ+SmD3K^O4Xsmd>gjOkpz&p|za`A+M=D%4z5g+38-?H=JNK4|vSNfiZ;enhZe1~*9-Vvy8_O&gg-cONQKNl-1+#^iMT<1VV?$!@8Hg9pVVP-%P&QEm
z0x
z-R#ECHkIwntxA`K)J~hI>u$TTzWq*9rGyhR^8-8Em2eNe!sK8(6yOHACQ@ONu|+;&
zENLwwX-pSQIDxp=Y_Ha@0vVd$H&1Osz40Olw+2xG(1%GBP`z
zsz<0(tt;Pr>4aWTh=Z58Zu6^)hv%rj)QAdCDnAzzm*L%w8mhZB(qMM!IWd_`6MI4%
z%s%~6TpHMdqi=aeNdo6&BxwEn?i(&f!P&I8O69$-fxl`S(!s+tnViP$D54Ridk|-|
zXc&7kI|Fnht{g{l^J&AwOWvj0YPB)-oh}J3o{ng%lK3Zti0vYDChua2;3sGx{QkP;
z&gV*?@d};EP^ed#8wjuAJHmh-ITG+@G4Pf2x!5$$FYkwnvz5pYaz>Be;0q>8+#^?k_$0gNl55lr}u
ze6X_+;Bu?buJ*Hc>9?#rnDjZABUQu?lQI%HbdrlG#_c&8Y0_sC!QUKld+w<;5^mG5
zoN-PtwzjkAi1XQHuE9#^YbfNEb;Yt8M$(xL{p;A)`bHDH<{?3NCO1Pzl{Z3oMOqu>
zb>B#IB#Yqkw_hw6CytHzqB|L*-fp=Ga@_I#%QTU*sZ}-6aB0JzO-iEM
z{A@~fT@86+(HX6MFkWlR9}ktqzNoy`ZRTfdDW7Xhx&l*L=2qId6VS86k9ky9QMnPLJspvKYs;^kCPg=n|)lW%wt
z=`vx#P)@R;T-f(yU?yw?H)m|WhoYWONbeC+W!s%tQ_Jx!4{C5MXdj7O9wWM>uwb>J
z1a?eHfPbj9L>l^JQhWA6u%9R)Kq&Z^$ssI6hed|>eUyPf|6g*fxH*%#-j|XUf%Jh4
zil0smqr}n>S}I_F1I?kRqJrf9Gzk9iOfgwq)1bxvCe&w|+&ti!kpJi)(Za9$uo{qO
zGDn7wAjd`YBqMvikr2RTm)`FMYoWVIi`2q~yf|_rtTnyP>nU5neg1JO5k5Hw_6f3<
zrDp9o{K0CBCn^ykgwfJ?f6Y@mqBpPo{fd=nv1H!LpPGASjPNRx{gA5Gc}d|^vU~jF
zMqB*ixVCRij)5+qE&=AoPzcxbkH9foDD#OEvn`Z>Mk}s0kirP>(b@)wd_9
zPJn<>x7g}sQK?;Y%~iKy&&1vT{boV3Mv^VqE
z;+lO!o>E*PH8&u`oBmewme7fJEVReWZ3?tyKZ+_z+<^(K?s#-cGG=
z)7TH58k#4wp-XvEWW$)?wRVPnN&Z^`Sp2GOS#_Q-Em}x18diQuPM0i=rx!uO#w7?`
zr|@NRN}j`>D6q=%4XU%|gCWlrYb6tI$#Qn)D5^`lr95M)vARW0l#}LJ#Ay+jw+!bJ
z%#vD$u2(@JheaXK-=CkEGwAm6*%s5v_{Mf37|=-sADi|hgse|7UO5zOXKsp7ut`Mx
z$A6~(kpt!-iK(kjGwX-K0QS>8{KtMK1ZQ`G=jg}~-cnpmW92(Nfyme2lxGk8+-HrO
z=9S8E1?IGlfjLc$&|b^)e7|#=HX9yndefbjDoxveWi(BzNX=Wa6P`5|LDRwgV3khT
z^-__nPwCSl=@wKzN`Jhgomr<+NjK~INI2_Clv7s`^CgLQQIRIrEhCv|8$(rS?!0Ts
zDKnoJP3J66P(Mg7ge4!Tstr09CXXRfQkKQhwHyaKy}?;7MeNrwUjQEsii=4s9l&1Z
zn%cfnh)64X0w+sEcvzQBAv0v?WyL*9YZ%8?#ic-(#PO9XGt+w=C{<5C834UF6dZA0!z{xPWvD3Aaf~zSN$%GG}@oD;~i~=j-k3B*$7V
z)yE>1G5OQ1rl=LW#S2)6dxW_Ol62LSt4_EGd6T^NCW4D#N;7pccpUBL
z79&7ZvZZhWkH|SeRMI`i3ie91a*x`xPx%Z$$xn#m@pa^DB3*N&P`V?FHo=a9xwWMw
z0~lfR^Qhm9n~M%t4ITq$!i!EJqo(Wc0#Z;%f3I71iv#|#
zX-Nv5Pd}L2dEr&-_N&zkZh@S;_z8a5h`655@UPWVax&C6N*#T_PNJ;+t^uY};)Bxf~TGg9^LSGcb-lD;I8%EPC=7$3sGbv=GSrBgM<
zH%LL-B=7cmm=qEgUSo|j)$elDOJ&J^e-B9^=tM0t@hLc$d@Ut_MwZMXFd}uV_W^E`
zeG*vctjLS~L?5Ssc9z{nzs$lIrx>G_q`+7+(>`_IXdO=BFpQwJ?T67`&jOdzGo0Yn
z3~*W!h9>QlrYs5ayK*aZ$`p|~6QMx*!I$z+3!V3QQ1lb;Y2>e9W)U!|
znq=MFTqzVlXHG8VM?Uq@v14SyC;UH=KS;6JHN>QAU|*-nB2NlkMG8&bMhg88_ueo)
zOd9t{fVbqsYAcRCHpgX*=3>e;ISiFXA<{|A*Pd?U#JN*RxVfH#>=+cDa;)IQpdV
z_h5?mGz=u~=x)cT=3WTTXlVkN8)G#GcQNAYBIJ7+VzcENdJoIl%z2RRx#k6G(W$0%
zR-QSn?LX+p0yyBAh8NqRM2FQnoi5J|kbguep*BGwK>?skLM=Z?B^`LnNi-*bKm|YV
zvxBH+DpTz>mKTW1Wg7JS#vaN@1l>3Nk`ll~tUgeJ(wyQ|+JStLhPjBz1n`1gvUqT}
zZ-_FbQ9u$UA-x(&2>%1)du7SM@s2O`i#t8-l@y&;Am0=d7V`n{R{j!`!=eFEz|Wnh
z6QW8Jg8iowf&ow^`UQY$r+HfAm&siv@4)o%I?^rv-7_5XGsnzbqQtmC*qGRo?la(7
z%71=6Cy{VK%}PF&nWd7+Z)&r+767T1DuHl*DaQb*n&FwB`Jhls{^{v@h#n$|=1C^m
zWpW?^@+sZV4v|LrXp&*p8G3dQiB}@e)^&vqS0kV1U9bG}KhR+%IsW*R
zMme9@R!Ts66WXq4PbCR{;XkhD7myUP80W0`Qb}Ow#G0Jpe{Q4RZY+vpLz$`5A{;kHIjL)4Qt}`)ks1p51O{9c
znRlM$wj=h`CrOeb%5esbK0rO2CcTWU%JR}}MXcMve%fKLtfG+9{FBdy0QuZIMs3qZ
zPOVVw(n^w_gz(QwVn|VVQb~GHNv2^mzX@rjqe_!Sg0w*B6V(1PQv?*6--qjztP3I|
z=Wdm`KK|>)r
zSuDG%LvvLKm{Yx%k5R%ETQloT+k3Z-8Y}=H)cP0)Os9Rn12DA;^}`9+r11X>RO6@7
zN2_9Z>{xAk3Bgb+CZ{RRepHgZDJnQJaeUn0JZTu9zR#f5j@>^GexLZqCIq7(vW`?8
z>$HZ`m;D$7_=>ngq5N1X%CUfJquj3Ue#meAFh(h#$)U
z=>X`QDNVzx=qCC)fXVI`M4Sij1W1Q|SkE{B^Z}PscK^xT(h1>DZnf+&RP#Em+5C!?
zHr;&j!z~%z`DwlQeH*K%&ZEzXlf71pHd8w_8u;!HzI5Kir_6!d-OHbFRbkvh&Nr{8
zZ|%LdH-OcAzw%FQFNcHgOKlV>UhC{YfPaYiXC!228vx?tq4FrF*c@~^sltqQ0erF2
zwM0n@MeTo0l^>t{Dfeq)qhw8u#eP#JcQLeQTskN&trV9
z<<^U(|GkNQ@%MycO^>faCq36}c59I#AFhsG%yi`aMW2mYp8SN0)(?I$d`}V2@`z+M
z(NeP`X)l>yd=wzR-%IfjN~r;GF-
z9_lXJXx`#oCvV5GCvWSq#}#6=@H?`QQG$gl(PBEKP8*|ZkGN7o^mK<#-8)OB#2vhWV9F1rK4T2dvGp!|;UucAY1fKNw1{bq(SA1^44jZUBkD#!5cAoqN>EoJ-bY~-
z2$<%MZ*}YRxaZG&n>5-7UnjuhB3fnbKTpiT{ZwQoswrVGA2^@2%LDd{9_Ca
zsJROYF0T!GJbsSulp25ZOO{S+T{MoR`Ce4)2Nx}H-T#y2Lwz<6BmZPM&-mOYfx&^8
zo_J`!Y3T=UqFgpw9cK|d?6#|Gz^Blr1JuF@2Cq!64c96=rd}??v&lPG0X{(Jt>8L;
zeMy!+n%YZp!TS>0uVp6634Z|eH9o-^3(HZKs(Ydw{&b?3Iu1^@mG|v~sN=ZD483^i
z(4}1J;*?c0mK&)8&2eiMpEuoQbSWq(N(!-z1PA|*wCd7fNEls3r*c=a@5oHcn76Jg
z#EvjX#~D(9y+;MudwA4heNb;
zoo>eVr3)v5b8@3iV*UK=wxP5Qh|HBAtc_S=ZDxXsuXFoi@2ST=i28lowBSt~AwfQo
z!PQvF>4Sqo>SBxp4uUyj*v2M;K{AP{D#kZw)d`3Fc}<)Bd7~Ia8ds0R56G2(
zm`2@tQE0(tq9V4`?r*25;45XrS$_{h1xgsx;lyFrsTUVP)&H(c47KI{SM-jehWdjo
z;b>yoGrzOCvp>%%-quZN{HOMQFllomG_{STGdhQ72<>wgI6{eQ8-QbvX>Nopb>%|@
z0T^Z13MNa^4`WvzGEWN%uQ#={{xXkuO-@#CD!8{mkMrBmqWDokUiqhMRZJB-
zIyQ3Z|0jjsP;dQDUD9R)Xt^px(7G)|@PF$PPt^ZSp{DKPW{FXoar#)<&P*;7ocw4I
zhSF~>^l(&)YVB%_pVtMYMRG``2^@kcfJmia{j^30P4Z?UIOV=T=>HKU=n%;jHn{mo
zqRoTQ);5;^tk!X5?bGo3KNq68mj`)9SNFfT@;~nicqrw=I2jCA^zX_JssBHAg9%zj
zfeHG@Znfv7|DD~w6fKj@mnYb120{e48#MM8@okX4%NS1euh<|(JZ1h0XnWzFa`6~F
zo&^!*QTu`%3Oa@-mPUq(Y6>K>%u_MC9SdP(!1yg~gqSCP4FNO1M%{8cZW6j|0y9tW;IByL2F?4L0xy$WPF?IKw~(
zY9~j@OUT?BH~qcu(F;w|U10^a$(EnY?+Xn3?;c)wq9ClTVvU?eQG`FVjf`3XAl)$_
zIFGaRo>KbrW-;zky4n~h2EQ3oKY?L_gp{W>A4~fQlB1&IU|6KZ3>9`^ktxI=!!7av
zK3#xuoL3Vx#3z+vg@%SN;rh;A4O2xpg>~Ax!~C!b+nYO^5AnB~(AB%@g4rt5yW6p#
zIpH`f>~Hw#er3ZrJ62q#9cz1in%Q9(l+b_|R>kh$JgSLQ=PEa9B?-T(=g|=ce-R;O
zREow&>9|i5%Ou8Mm~fP)Uvq{CPE!@5L4bDyP~B)i3pWV_FO6L!zfCl7%{R*IDM<|b
z(t%}B@C^jSe;($3jh=%V3>>M
zPkPL^R%7MT{gFBcqoj`bAp!_6q|m2p$*0geAYwp-Z0pwh0JL|~O0qhpirk_Z
zd2wYOKzRc~jkWy%fj
zxSAYvi&y@UX}~^++Kq!dcQYEWMMW_y@1EZH?fiKkmiwHD&j0(@Q-EpFe)@#kl==9X<{Y^}L(N9$L2z)8@2S6Hv`ZK}g6sn^5D+56G*l}fMViQC=n
zRnSze!(E-X`CLq(=e^@AH;$okqBBIqTMye_tBFVV7@J1`a8J-?mUf|PtWNa+=kPr%
z7s$0B`f@NgBcw9{FoZ?*U%P<2U3oHZ8MA@=TNkL@t*NEbS1a(-DCOMao{cP)Z5IU3
zFJt34`q$4DFTt+^FG24`JiWHY*ZN>>nt+jKS+6Y9qd{x`@LWz(q)39Kt);1!>q#`k
zr`n6mym9WNVvFT;7Ot--9C3B#n};L*~vFh5iCe3OPrHPl(@
z(j7@{wFBqyY^60Oo<@fA&WH0(UVXWX=ijKKel%eF!jLxqp-);b(9?0UEp2I>&wkWn
z@J_*2NB2d?*gCz(#}3MqeBt*qR-iF;v>=W6^9Max85P!u^7l{xDunT)#_wfTSphpB
zNn=VaG)SeJwiO_yHbx311W-cgLjrUL1TEnGyd@;J!aA;f16^Sb?!cn(AXWH1J>pS*
zHi*wU#?dJ5`=Bv?JGk;(qTB0rOw@}t28y`F20@xX=0R!-GZ0sWiw%A4HbzRij^AIPUk4TE?thnnZ;T^YD)91kLCX{|O<
z#UnkvC#J1_H#VNN!w%vqCZ(yq=oFYr4ca&ANzg&V>dRD^NZ~&v9(dPl#_FM@@tGOi
zz-Nc(1E2ri>0}HSiPW4@U&CBXhSf$k*TJMJqpllG;kOhT(oAh3Y)cNg8vjLBdr9_5
z)=HzT`9gpl1jWBLoVSTMJ{s0og@8yQJaaLm8x|LoygK+TUg=H?JX*N6~^sP?>lZrp5~5bXAg7j+T3}I+Ejx
zd-&!3)__|nni(sQa}ScHRyw4(?yzD9g=_om#8}7IKf*mpFrp_?hho-h@&>V0V6ewu
zt=ah-E6kk;A?JT{F6@lJjdD?mosZ}3V7eGA7qweAJKkK!>N%u3)nrVa4586v47qkY
zoNi%!eA)k{d%ZpK;L84db9p(b@n>(b8|dGiUvXRey8^L%q4y3x)`|j-j<7Ezs*&5-
z+0|paotfO7dBlIkbfBHY_Sf;`U~O#f;=XVP;d_(k^=-%gFJDZK$fx^G(*@!ze$)&i
zWa>-L@RChee7xyzRk37B8LZ@1DA5N?!|_#>MVM`?3I@}t-;r_bSXNEsKj?;TFYGE#ux`-%%xXd57Mjf-qn%%{T-=$^Y=uX@utSfaal_f%
z7_GDG~NU@teNOvnhl;3k6oSoIA-pouyPC!=|q~qbmerH_iEczuz)U3-h?Ww&-
z(7ffLY~%0FA1bcfEmltKJ3PpktD=Vo)eNL^*y1%?`!RU48uo&Pz`#6)9UZ;Bd39&&
z)2ZCgSN}{D
zRk(xLIbd$SO}9uzr(=O&n`2o^h4voJVRP8yqzthIhq@V@)R37&VV#@YeZ@z2$UD>p
zb-WJCQFm6Z+C5#ov<#kYnOow*WB~PK%Z{NRPPI4ufJ970zh15}0q=Yy)rdULxAAr=mPuW%ojkd>OiPoAc4w*~+j=RN2Ef5YOMzyLdtovJPaWjtdDq
zxbRosBI^-Wje-wHT^aP*nMAjY2qZFl0>T(i!p$Cz9-oC+UB~qef4pT2CMi4k2D{om
z3E8r};0ZIb84j#F4?D>m|91O=&x|huZViL)PeZ{@k|!I1hokLbW(56ywDNOyMO^B#
zG|qP3wL3C)(4
z>E)x_n@>sBkDxCd6!|5BuK9pbUt7=uB$Di=j_LJ*kfuPBc6gG1?)+B!6EuO>!HGZL<4mxM=-YRIZo(dYz
zCe9|&L@YCqs6c`@%Axo{K3c4mm
ziIb_H1x16xXf|)Kl4WXa(1ZArWe^wibBy|$CA({i458MHY*fe~gS2#Q_nGJ3*{)pG`kV7e-tix+*yEcKYu(x~K)i#?gxo
zZbMr6(fsp&@9M3;%$5XpcN7#
z!sIfqA!`8c#LdYvC91BH2r!W;!ej!`J?;SO(nu8Ov_~gzRXVtd3Ua641pBZ{X*g3AA{L|xF2PugyHhsCZ_uypjz`1_H
z+0=+rmy%?>l5kF;w$@a6A!O00Z?IBdUdZv%e!ZKH87N_?hu6ge?xKL0QUIkwFI(*X
za<}z@sRwp|`Wi+?tE4v=fBO?5V&zn$bzW0+zv@DR1uk*SE?l?3&5I99zT^ewSN^dm4r|TcAJ3@+
zh5O}qMd^}f$;X4Lr(&}eLTxKV1?ZS3x-kCRMxj$}TF5HWqt&J&uHdC`Yt0oxoG+E|
z))ZA-p&QSed6l4M`PPrt!6iuyhjkNYubxl1QrY!q%Hr7!y{sI3HKGYi4l%j@I>}tr
z4THH-s?0(0cu69u*asp<(L~XQ`q)vkTK?OnJ78m_9%l>5J9X=}OGGX^&$%=x#aANHCa{q&f`#n`T
zSrS>xn2gf3Q6TNsE3`5~)H;42E8H3`G
zc)%K$L0z;Rt-Tis(>FY$r0b&!oqyQB
zJfz1UPu75;LQq0-%nLkK{F!giB~P1bCr8dIS-TF2z6eBrl`*5kg6s1R2Ma0nxH)%G
z7@2xP4(V^Yqb?x%n+pLc-Z4B}2C+z(*T7(v=H`;(soNHac*~|dgNwF>-j;t4`e>mcr{LZp
z8T8x9>_^Tv@=j9e&FvAm=!cvWn9%HtCI_j#kQt$I_ANSZ{w`@>ixyeV>w@P;+^TsK
z3g+s<8oz@ek841L;0OLZ>Hi(QnG~q5k~cVF!L6tusGbjo*fgvS>!wU$(8P|4$&d)%
zQCsBGzS+A?u2E|8Zeqjx^x@>?!siKZ98{>>OeYaepT2Rr>)<{n_nW#ck32GiZm}kkK6xdK|{t>}rlMZd^;XuyNH1#*QHDarF5t
zSSsK!n(qbOFSA<7)=rwyHmCwByjc~%A&;{+YbLHf>FnG7G)l5A#4HVP1bAFbWOj3R
zee{b`<<|Gb$!XK_c36!+UcmDWPA9PvFcRSfK*1DmgD@uaGW)S)g?sn8Ob4*-!k6@TE`LF*t@P	HMpibALB}7`z|D#jCeDd)la8@PbN)Kv7VM>>DSUYKV|{
z{9)ZTN#RZ~d4^!Z?6st#Cr5y)6d3Z;4H=s8KSIybs;LYuHYBBqIg}iysepufRJ7z#
zH=YZAKG?(dY2gR4t~BmU#@Zn#U$SU3DxxPbxbBmx~$)q}k%YC(^StygRP
zuwWHSYv~n?fs)}}i;;MPI|DC-%y1)|D|mWwdZ}bRwM_DqS^8Cb%Q&nprHIaOEVEDXbZ+{@Q|72aEG6I)0~Ecr9wBu(sv)V#fL+Zmn%i1(i?QV{TUOr
z@~04dL6h{Ls-h6Q%3Lj^7;7;SJ^`z{S8X(Itt$pwY6SYa6zYESoIOS~g8v1V6*w>mf>8IUPIFergXEQ6t@LMR{a4L{-=&kYfy
zRzaeCa5!*QfRQx|ns^oRyk+5zM?k~cp)&Zu5Dh2xkg?BlFN_NDJb%_K$4o@4;!9axu_XCl=rf}cE`
zIhk^gL`JBoRcKd$6@XHjBW+sS=!AcibE=Jsnvf-9VQJya$uNb4UcHrzvtf$|HF?3((Nn6R3=Ab>ul1Myp=1VFVDtEpraCdB
zADlF(yt!-YPXuh79}*1dbFI)>w@dtL?)nDD=qV`apf*y1E>CVcI^c$DnBd~WP#km*
zSW;9VbpPhzNo@CoQ$GctR=5vr_tnubcc#tW`V~0b?ou{S?rPaaO=!qbDh{DBWsk%xZRvHr1d1lv6_CBl-hoDe8MoNQs-w%t!~Ir1?<-Lps+v6t&uH{G%6V0(?RNCIIz6lSPDNUR>-r&+
z)P`j;H>oNm3QA!=6A>32N}>Y;R=G0?=V$C1a*dlco%=pR3hDPK~ARYA)~eLZkCqf+wpkjMi~I|Yx7!5I1?a!c
zNv3MFhFDtCe{7$qXSJ5AdhVj8yDlz|1KA3CPkhrlZ>K){*mbCZFnEpzj(2M?!d}4W
zoB~VWNF>H70!3i^%q+k~YpX*Hst`M4q4NFbJ@(@iAQs>c1Hbt3h7$29x*vMGN
z+^QPCGba{+NJ=qWHP24k2?Ph027;@7#mCR1lvC4=0F}VexK4j(sGXJ@)F|Y2=AUHf
zox3aHE0+a3;p)aPua)O^L2_hPxNU~u5Us7C-5r;NJ#C*2Vae8Ms(WlA
zQuFnO23qBA4dy}=B~h@{R{%&Cog#gKn^NP^vwLoaWec7F
zfeFSbS4a{ZK`!KCZKYzg(uJpMS!9N%$Yp~Ren`C{FqCMUljjcS!-!#hWK`k-%!oQq=Em`~3RwAa$k_ZTPZZRh+iuzpWy-e`-I^8ZY_{pT%weL!Vrs0S*;A!QgT2s7i&x3$_YQ;H?o`>
z$0dRW_t<=>%HIss%6H}5rClv*NV#3~%#C;L)&T75B$nsUOzFQ@ynDx?CLX5ioBO;;
z6Y#;CTO*GjPs?~MKqDk9_$k&JDa^jkU!Wg5{%qE*r?3yLlPwH^p$js8ynK7&x`G3Q
zZe|?qXNgIS%EcFz6@5SXVTfzuoLDuC(dgWLf5l@^8hwmXqdCVh$N`CSyr
z2K+Ccytq=8*q&0Dh#S65ybg|(#0z}D2vc9bJt+j9cZfcqIFY!qcz*=4D9{)6)!^3p*QN+
zfJiQ(TsejsBl7o${h|NKh>^mrLGvYw!K`^Ov%VWvWIPb@LB7sNck!V{2ovrwbyE(m
zXETR(#Uu*5OTg0MQ)y8=8sNjWGNVVvyFOmQ#MG{u&HQ#rcI;{hgF%4R(Ny(GKk8?3
zqd+UGpQl2&_n?Ki7W3N-Av|0-O#a%C=304v-nTqK<6OxlW44;Olt}q>o$2midE{!0K(@hh?`oHfjOyQcbP{+4
z$ps!ZnYJr1XHFqio}6(v9>BEh>QV5cZK;A$-^HUqH7lmh-_5c_!V>FBKW0^OASMMA
zeI3d=MR+BFPc2GQ+yzPeHGM!%?vy~t(b+xI^}v2r;0#?O9##Dloj7Q9rrbp0oYSaL
zD`pu@{U1oa?Bt$`Q>~a&Bs03!!7mMRau=vMbM66?Sy?|$8w2@}bfFI)f6z$!9-5k#
z+&lWP{Ka26BPOUgIK;aEhphtS(o;=D_~q)a`%WM73X@9Dg>VVBgDPEV2S0F8G|fXUH)Gg8p3i%~N8
zG443_)Y)+H(D$$A1e%!au`0v#;o7q*Lrgt>f};wbUvK_caQ22XObTj-fndCOczx{e
z^SoIvdATVHe(%3ZTZuoa{g|!#YPd8Jfhz%_P`M!atiA4la`U+c3@_<)uevxCgQs*}U(7(MEQce>IZldj+EY|@
zx70;f>Z>EmHZ`?|4oPR*{C~~dK(1lAkl)voWWv|1Wp=z@oxIa_k`8t?kX2t+ypPfI
z%lN&{97F4nKy0M@8|>H`^m#e+y&jq9Sl0wb#q!z%@@IOIqyk@Emm?Lr;_~0;eN-T1
zNb?HKGKqvEqWZm0w#iw>3zI_9Bzd4ZO`_z}T~2y~cGtvftQbw$ES{MKqGuYjd05W4
zdYyVyxFE>Z*6rF*n#XfSpr^od7^Xd5x*u}?<(srAUk}j#Y!PqX*v>JpOAa!%@V-Q9
zEu;mcZ`DF*j!_Xust4xMFAVB8XfoEtuxk@mAz0^9bG>DIId6|_4vjLdUP3%uwKjIU
zjcHwZoS~y1F0Cnj>7ifC@ufPPRSd#mFJBN0>eoFItGdVwc2|AVY|jE?Mk!bT?(+njhZ
zv29Ll+nm_8Z95a&w$b6lHaoU+`}h9e5BIM7tyix;efFudtM=aYJWmz>JjvRm94FuA
z7M}~z9k>}KV`Cb6ZoHzsPPBiaP@ZD-(|RB^;-3Cn>w_P*m<7GQGs50{-!U{!K>}&O
z&n9!;5(UcYRPd!l#}lo8qi|$rPLpDv%9ktGO&1MnE+}9G@BJFgF8MwoL`yQALU=48
z@V}0i_mv4#6z%;%flfHD|5)j0-Sf90oO835w~X)PVT0%>DPFV6qbt5sfT**Vvh?bvi=e@olktYx60HLp
zzsKU>?Jy=l2MbevDhvlNxmb@iMqP_!hHJc|`fT~A>1A^=ex*X}%cUORFMDnUXf0?u
zzuoLk1!%dZYMxw%9-MTIeJ$HZlMZ<=G^lmFbYmlOn$x#`F-EmjCsT&J`wrn$rJU
z#FSmJFa|G4Ep7HV$eSu|saesu>NwU{{@+%VycIad0FxKYkhK{ayO@fhF)Jqfy$7o+bonY1P)e70-BLk%_4qiIlq|tRm;r&b)p|M
zX#<7~#%6imPsUcxfukY8B+1WV#mr-PyQG?se7bp9T_Ie)*qJ3Oe@&jj
z@q{9mbZ6Ad!~Z;W(6w=A3$RSCs>jPaNLbvHgdpW#>WGZ?`CSsWEY}+u-Q3}Y%)pIm
z>2MMoqnB(s@V7^-*0d+I{#TlKCX6wlBir2UL5fNIfVZI4ymVaGDTFPzv)p$+*-nB&
zendZh9gtx;M^o9=RVOt8e;Dn(o1zlF)sdahoZDVYo}}+6HfJ7Hadl7Vuy_4#|9EL1
z2_G}TP!#z}-M8S4X-u6qr~;KOS&46UG^_%;31h!G=N04^PIOq~>gjsamoo{4#qv3_
zTvVrcVU&>OAZ9R|f)J%R2Eeu%9IXm~+U^dl@tr;h#8MKq
zMRAbLQ>C&3SMwUuQ5mkb7$jfY)@tgL~&da
zZ(qhKW;0RL1jkCD);S9C@gXLtuC(u`iWP9d>OX9d2?5YE*CA$rnIX|;(bZhlZd_F9
zG`m~p>J!Ct>Bht-EnXMNr>KSGqYo?ZRSvi(wa+o`6-dtGuw7tpa2~$}neVS2&RHok
zfES6^O48`Z7UWlf!42U3C02ooM^LP*LC7~->F%Q=g;PrbGeOO;a+Za7aL>TZfoXoZ
z9+jSw2}@YME*`N$P;UNSL^-Jhgp1$gpeo)_wjWZ1pElbzq+)g0dtjgdbqn=%{j6yV
zFDI)dm5EkIB|n1}PuEZG7ZBbQMhMNyLPtlDroz`W*)0K!@Fdv)ZUQ&q7tPT
zK}Gc~gZ(#_MS1V-NU7I}BzY%>e-~gS74h*MSUY9(@wWHsrI8uXiIe3=zvLE$c&;0~
z?{fq~8#3~+sr5WX@nhGhTPdp(qm&4EaN8|(QFY>{HoV2l+&1-G9XuFS$^JHWcF(lB
z<)O~6dUtOO2$w#*#u5nS<>d;Ewr;69ci@pxRDwz6QOi}(cyf|z16^zx#>>4hUG~mb
zwcwxxAgiyAZA(m_XW2|YYx>>9`INLeZz
z9vh&DBs#S7@o3!P>>RUf>ohhuY&qc$gU8V$zMVFsi_+YEw1any`8Xfb>GyP_3)0&2
zt7nY(w-1}PucxD(Q#07*d;DsHCG43ps}jJ}`-kk&!pX^)dz+uV%EdG?LrzWT^tk2N
zzfx*a`C!@`Rl_dBEw(WH_`+NHtq=Uua2jW)9Sv~xS!rEQC1)WWaB;-t6UA!YH6sEt
zgtndLnX!rO$+u%x1{Ik4iqWmGtd_iu&8^HksH>$TB<^1EUHH%S?bwj8P0U9y(PV6B
z^e(WSHurQbIjupQm?dJdVmLz!3HR{1j;;Y#_l(vVdsE>tW=!FI7N57SK@}`I$;BH@
z>YDl}LsjlLnpBty)f;rx{DqE4{iDdLt{H0Ilg1dKc^8jolq&V&o�j9C7kUo}X*6
zW0Zar3>1gT^A5@6dLxcshq}1|rcVplvwzOat~~!0ge-CR@D21DUN;KKT!cjU8`)p+
z>dJ4-wf`h^59UW-Bzsx-v%Yy}KUcb%==`Yxb8f)np-@)MBIo&ij;8;Ieu>}QHFLBh
ziM-m3@@4DUTKJ0OXB>|qB{xA-{oL|(^8s5lT|0j1fANtQj-@jxlFKMDeTVvE@D*PU
zk9&K1o53#iitSyw?a!W!
z-uRq*;p|ZVyTCb#Q_6v5XHVxJ-(iRTYY#(9$H3MXxrs0ioKT@516VvL$=Nao12h6O
z31j}JKo>ToCOte4=t@h%C382NNFN&G8lUV9MaG#-3R~ff&!?+QqVvUg-~7IP8bTY9
z8@~NlBKnM(Hec~sUUL4cUq`un@_!bvye}hWblH@LTA|GY_a=P&pA27ad~JY(1PZqz
z+-ceW+9xnLc!J?w3DJw6lmbwTi@^l1+Zm)hZ4}7S#HW&?9`I|>0^5@azTGxb(W4f#
zoKp2A5MvDvI(yJoNp+`j@3%`Qu$(I4H81v-%gWxRf^k~sW)Ijbq67+FZ*ESxemcx`
zWywv6c3zo_dC&t@4mLEWt^;EjC({NBUtv{=m5=7zBBbmc@JLR}~+
z5qAwcx-e5i3#J75}^!hplCprS-
z^>@y{dlFmdYzBhV-Drd*08^jFl}1U5hEtxy>SzGS-mX`qOwr{=YhW0qIRw8xyip$W_RG?$PZr*nWD~OzUJ6^i=ovXm1Bb=
zY`Yr!`O&SuBb0FJ%}x$ZeYRUan4|w1@g3S-&TP1pN}?_Gbri67niEkXvqU>C#$wtb
z^cRUSNteG;O7UoZF3$exxtVPD1I8=OugMwtGL2)s6oA>J%|Vo_N6Wr`1fIRd^>!i4
zzp@im_%FHq2C3IPerFj0$%rpm`~^C%1uga@Yr{;%6?-id;z=Z+q#Gd8IlClZ?X&%E
z6=dU#%l)!Cf(XxSiPNArF#C`=3g2>Kd_exTkkg0QA1d~S`sn<&-RB(Wv}^e1xvopL
zjE1(}@&_%L6>woe_^h-0Be9iPO)Lc%)C5uoTRjL(q9&TVWnH{usUfhBMlFtRux*jE
z%{SgfIZnak;(~z>d(ZUcBP$#vB`q1CT-}dk>4*lOB;Kl&*C9r(|!-
zu(0)p0X_H!{a#u12fH%0T~n>vL(^*g=xikfeV<)$k$knqL}a|S+5Fy|&1?zf_~vmC
z*SxPoARu$jg4{f|pHO$nYFJi=e!?bc-n5}%ixX2O`7;Jy0cg*k&N?Paw-HeIQ5Mjea!V|Zq
z>7EoVxFPKc_42pVE~)EjPWHW_glx;U_!!7uLl*vafOcg4)JFcb7%DaI3KO4eX~RSb
zryRPZm8}<~ksyGV5B5X$q}ab{HEoT*3ri{f%`Rtfv_<@Btu{c=hvikvAF7R3E-lu>
zE?v()4&aTa?PA^#m}uzqk3eSFcL%Poh(Ah7!$dSMaZ8KsghaVO{ndjCCqBFf`uWck
zfn2QPdU%-F8GtO*GlV`1%#Jpc5Gz4WZ_
z1!YGzWbg8tOGznjZn$CoXHnn3&l(nTI-VGzWvp#o+r8ymN$iU@hUKo7K&b~6?NYO2
z+3BVobenD*}c$w53yCkaA9K-#%e
zNKkXlwBOgcPSQnE)wG}8Lg#s=wLPjWMW|?$JCUv6T`7HVwg1h@w$sciT%~BH8ey44}r;H)k|7?O||Y)lcJ60y2RQ=TYNF
z*cm1LPS4_Yz-{0W=Wy9Os)tCr^5T>qmhJHp!VP6pC`sV;HwnHr4he0x?MBxsYPd}J
zwep%srdWU9=(b9rX;jhnHZx`7+vt6zmYlaqr@ksg8hpP#&UtUyNnpf430@C1A(#j)
zF^}QG?-Ig3s&$1(wru_=c}YODb@(Zsl07-*vtTa)i~m!js)u_5ts=H=sOsm!W0nZi
zK|`ytE<8iy9AlEcmS@X$v{(M5;IaM!yO5c|Is{Ky=&7?mRA;6On0UOtYqF&AZt*YgVXbaDpZm*)@1u5r7kQZ{N!edth2}odgFOk;
za1Q97{G#2_ulXT#*PHKl12x4-oxn*&>7yHSYzkVW_uSn8eHOv+2g1`zu!x=qMkFu6
zTS4K(SDXjIop%dx2=)7ZA%7x+jH6Ps_fOlLi^~43k=67;fBiHn5OM-DuR9`}sfV37M|HlfyKx
zO^fjinDkp64+=SP?YLR#)=41P@#=P#0Oy_IB0Pl7elsBcBIH@u`tS-sSzn4xILo7-
zk2iWiR6VAH$)e01JFTFUXul9(b
z43K1q6_fG5LC&1F+_umC5O(&kVA7$ro#J2iTKT@?%D>si?YI4zT-g;h9$jqI!(hy$
zpVqDb!lbXOJ~A%wgYsphA&<#B{FQWRg(XwB
z^)ttXajTVZghia)xGx>yl!&R{)XU^<{2h4v_}M}N;(P@i99U04MZEOjlN|w>;Vrwx
zT|1pgzBN8ym;1tpl%Ix0Vmg@Y7?kgcQmD
zfB@927A9kmW`Bm>OeVLu(e`8hnAfVw&Lm`S`3>PXY4y&835X97DFf^{0LBT)5uKT@vk2N2MOow~MgK>3JYu-0xx7>u{{H;jjJvj)$mEu}?0Z#Xm~xy$fOerFmz;BFP&8
zF6QoI0vpx!YpJ&7{Ug52{5;0&J?=soVQdOwiM)cjntGZ-M%7OxiCNG0l9!0X?dKHy
z=GfS2_M=-2FOe`k!wjn>eUcLhAQTd^cGk5FKNJqquA3rkgO#EQntqj!i!<$ml|rWi
zFSh*U8cdG1qep)~Leyl^L)%^8?j6n7+u45PF}14*VVq_nzH85c*aOH%a!Af-JbexY
zd&$>w1>+0ToYt-ZpNc%)`jq8;Ab3K=TnR0U6O@lIgh#nALAV3_`LdmoUccluV9|h{
z!9UJt7~BFu&)mXkhQ9913L+EoI!$H#5j0C0gjM&EjrQ+1=rL!Ug&u3%rm?~acl)G>
z>~#WCeG`%S58#AKyKs$`jE-EhVp0CS(u0Y?vmG`5;5D_30RQeXa|WA;jh0H3i@q(a
zN6F79<|Y2y*(2-&S0J)fg?mD2#X0zw89_lRA)v}wS3A!X^rc$!^CzD&^$xq7r^-_1
zFKQ?|*5UjZQaZKhO1w1--6+gz^X1H6<;zAf{9%%*$TPPmx|$7I!wOuH`z
z>WDPI0i9ZJ=@aVP=Ed_`%f&r~*_79292j0AvoOS(NhN}q$S*_*FXEg}w7fyinRxB1
zq06=5Bm>$55|!BPNwwY*RuM7m4jpq~+e^0rDs3sqq$U(VZyCMzB&9Jnu(S5WyNs9O$Fd@YP*Z9x2%aF)mK
zH*IC9ncClcKk`i=SX-m$-FJ=o4I2j$b1gGw-1I_j5V+(uB2mLZl(dN+>E>YY_T@fu&nheTuXA*UF~t6T4ddcWeC@U_caX6r=Z8
zAraals8;Eh=TkF8(2w>AL^~B}Mx2M@tKys$Vy9Z$939&d?~
zM01F^Vj}MeDF@T)r{aWl6FjudG%@>C`hmdDAA~#n+92-V{$mH1E?*8kwms72t7|*+
z(-Fpw%y!=-^A8HO{=WL}P;$2jR7v^pR8!4V@o@{i*FSHdmrkbbT{-)$R`^pZbkdqr
zMAd8z6Ew9~S_?ecr>aISi)4O)*zy$@4XK;G2{P+O5Ozx%^=Sf&r=Uw;mVHr@z*(XM%du3UK={tYR;Bwl(!a;(+P`T1Dd)Ft^Yid^oj7Mff`dwA>+h4yMUBe2PGZRU#ktgh
z73t^RVspFtH)JoyGfj6rIY^l&e$tHBjZ{lQwWI74KdxUiIBgEiz5`Wgy4{23o*e1~Jcn1qTgRea4
zjV&9x)kcp_%^lss*Nr;a->nh$j(-3i2WRA)ND#ju0tt*2YxKhwXM?gGy}ai>4E=gJ
zhsfa8hkAIZTZ%>BmF72VRumwK`XQ09Q3IdaB=yyQ+dDJ!^{Tn8RiZ7Z_Me-RNAdP7
zLJ#36lsAnmwuw`|GuM52EH{ExqtPgS6*q#w?m?2yi#gLV@awvD!jE>0BP40JDQ6N!
za%f(d_gpa0PK7w!#o%tFvV|vxma&1!os(NfTA{zgKqk
z%qT!G-%^8Ec>Y{xqw+(n`ewKHECs(!mYkG@B}cB0NfaDk>h_zGLU*@U@zUJ_?jCAz*%{5%i;dZ6iD(RAf63ow{Cwvj
zIOvyTA5n2u1RT3iSQduUuu+O846`jy0p9itZ_p9=
z+C6P^;fMQ5Up=T4)1jxw6c|@<o&Y@fnX(aAwVewT
zgE#%#xH!QNut`wNhQ8p}O~2tH3GvbGK3f4)q)V7bRWx0R4IgV+fhq^ebG!d$0x!B~=NVnx9Y}l3j%Y
z=)OnMkMP*;_V%k+PmN(Cau>D^0*cEyc$otU7D0ejz+E2TH<~P=6zRB=B$-bZ7H6sP
z^}PK*AE6A5tL3KX4&AmPO9A%T5GP&CMvnH;zA>&{ibzm(io(76FHO2AS~kF6>0<8S
zpjtNPausFyjMZP_%6|ofq56^n(H%YznYIMU*9!UIZ*6eSJ+!TPnS(E{N9)L8`n$9l
zR-9w^m|c=|BHZuNH&Z!oSigA5RIcO4jD@9wi6G+th6!gWvY$Qvu;_Rb!86z~7om)I
z2-EB4I=;rh{_&gRgXiNhJcZiQeZbggX^cPO+8x=HJi>Cpr*l~nGXY+}s1{7lU}C?X
zZR5rDraju!(^pZ4^6-NNkKZ;rm_j6vOeQA{b_|8+qqfK|u0x%LjOq%TO9D#HXm2dp
zwKB9c&8<>NG6Vsq+&>~N!7O80vd`ZISn!qbe5Kf0C_BFy7jTZ?DfVihe?j~kh-iKRKd{ZJC<@Z=D!6u`hc)=J
z>Ct8h-B29c%3}Wm8y!#&R8nx7Yii(GMl)783)L1~NZ93D
z0w#tsE~W`+TNxz=1g!=F|2YPKcrwO>85|YJGE{|wAF<)n)+z=KDCveAR#yrYJWQfC
z_9!*|Q4eb1|5;@}RHdy6XJ;J8p5=vu(=PdUaMASxai-|Tcms_tn=UfOmoRnSzA8Id
zB!wS#{_nH0Xv%XLqjk}SNx~J&ADfOy`)`OEj0ns+zel1R3tM!Mm8!CjB$umm-(yJnKykt63pm&Qcve|^6oXf-IJp*5C7OkFMF
zW+R^W+XRWiZ|xG5fR=)T-p9nv733yZ;2GFxuE}I!`wbM!%JBTK@h}!;Lg|ha#RX7?
zRoG^D!V`>8ectapM-LxsPyj6hP&HdyDwSR``}2WT3DLYrgOzg1Owb1
z3mr&?h8+b-=-k1s*LWpA{ylj?sfQn*-gNG(&ljfEy=E0-
zx#$F=I?*;-$f^Sk=@&9YftDt+_0Xs>XW&yL>&RoSHjR%oP2QWmGYBaXradzVw&<(I
zvzBjo(w-m6_1L&Ek0poZ_>)TjHGdy1-!UE7%fR(yjK^O|aXgo7$_ooWsd%e$ja5jZ
z$*z8Vlw@KGzu%U&)T
zLmioFzOqu8kY}C@eGSJvC5wcuM__sI-7ue1zcFsCt4MOCZ|l?&D&Lj+hPBjL`k{~2
zi-w9SGxF#9hA(*q((O{!Tk?*#u`%PK>Jk6-b2<5Pr`VfRp~iwpz0Nv!r4z$iSE7&&
zj6CKXU1SmeIIWrkq_1L5l5QYtz>pUouN^T)7%#XAtJslgX{M3@QZ6Y3W`ozO_SaqO
zTjte36f-Oj)9N!)c=LNChmOTZQn^$br@UuZST{dj&4CZ%Iv#|_NnZ;!Gk$yl-P+^U
zsl}(w0>^Rau^c>d
zN^LOkjeqWp{WC9hT2cnBYZa1F=d*0=xT}>8)lLq*m@69gK*4khQzbiAu%x5r+
zE(3cWlS$SKG|ZhD8i(wQzYYJ?7YJ;CekUaL4l0%J|A+8?bFuem`%#TQz5nM%wvl0#
za(80XBpR+pLnEYyHTW9kxAQ&YyVPp|kBe|pH4VaUMvDr<#{>drr85l62U3CNwFj?0
zU8W%};QBv4Z;Go6vnw@WEc%W2zvGZ#34WMoGG8fcG1>9}q=>7avD*ObGl?e&hgyJ{cqw|@Ggp(i
z*C4>qfk;O$JFcRO9hsq4RW+!m2&qGR^=?Tu#^}h@e5(TPFJBm`vr6M8?xQ{SF}U>`
zA0IDQ4q*cj^417T55NdtTkK=tP6woR-^^sn!<2FzyEv3qXUUZ}-$(EIweQ((F-C_Q
z!>2kIvztXx8n&JBGjUT4iqn_15u#{cui)|gB$zP-Ulm4HRvmd@Ofh6u>ni$=2RC0h
zy~BF>D7v<`0KWaDKku8nFF1VllwrMmi5EjwA(0%|?NsYzNWwnsQc)1#=AdguQHIq+
zBZ3T>I^l%GumM_slYGXuGFf9;L>TCWS?MXYWZr7C@+fLOWSG;=rf~}$_n(Z2Ay#hC
zboc_yLwY#Lp~Rj2^lsMYh6wD3c{g&-oO}+YWpNL3PQQ9*<#fy?c%nBpY8T6mR1qkR`S0Uv*8=wn_$U8@CzOv4Cg7cPwozUT`mF2XA#G=*O
zP>UO&lI?#krCf_`x-GSPD+~m=VqyjF5V3d&4+8WiMLY4WorT`C4_$l%D&VMTDij(>
ze-WdHph+#rtDdlD1kru}mB^T*=$&Hh=A$jOddcgjVQf!|A*j)f1JyXJMx(0USG)(;
zr&0w*1(vS0{9EhD_Dp!|4=LieOQATz4qWm{^4>nenu}Jm+lwj>kNxGh@@KO^t-s}Uzj=$9YBHatPGv|_$cj7^0ylaSbj~haM`>-3lcaUc8rEdCa
zH<`jc=$yHNPSzviDdaS89x{rfg^}E{Fd0qo3ZlSF6y~K)5#u;&Jk@>2vK@R}bTNNw
z7W$fmKynGO33#ibt{SlkAYoW?YYq9LE(V&UM`5=lB6;Y7NR!5Jx%-uE`X5?4lxY|b
zv!TCOnZzC8E_6+ofeA`$!ffhaJB3y|wbcF}!)_e*&jVBMKhC*(v^gqy(nB4;Sg)FH
zFtM}CUS6RoDZge8(gvY~9i1Axv<{G>AL(N$+Nk{;-vKX%Hw~LrEm+}0v@>kSLVSMF
z!hLM@H9rBec1_9@&grxe4e)a0Z8!xlFzOcr9d_=EtKLI{#GtYl1Go8ymf+B3?0rXz
zyFe%`l7k*zA0H+jzLsohk?)*Nb1Qvc1p4^5d}%G|`x{G+`RiJ$2w@hKOns+ZsqIs4(rmE-!Nj9@(s#Fe8!AQ=xBS@<3(oXA>
z%APgCnOl7}peNqP#Ol(nOBm`=?j>4SQARY0B}%9gn>t8VRSJTpm7$H_cS*EL>i8We
z=HXQmu9rgrSne*!Hl1=gUk?JfazOh#J_0NB?}@@fsa$;3vp&f&MIg8R;b|i)k@L>1
z`BUKNbWf9&N_H%)jUi%owzk4j9i(B577BI2co`&6%0l+2OM}P`{ruP%+1_9~Eu5#i
zWL;_|>SE{z0vl=b9N`bUeM$R5G~3_f#y^D#f1vVzXE)M~iUFdBoGXQ9QvG3^hxL=G
zTE&Jlzk5I{;hDcQHyai%AK2*R{V}s4jFC!&>G%v1B#OIexig(~z=v78D*(0J52q=b
zD~h4{&GkZvcE&Mlm)xH6+=Se(rNkId-2H_{?%*&pi!+poPpThDIPGCz`){^G-~6^AH{IJ9
zjIl#_yUO-YMRV}#+QPf-=s##z88&96z_1&rslRQ1!WNM^L;NchUbBv;b^ru)Wfy>v0$}$N%dT+_Uy^v
zGU7-Z+11c5jsSY#x3mjFx@Pkh$v!iKfT`F9)&RPrGKmudyp29@qf1c|IVQ7JcimR1
zi9ej?Spz}uv6*hHVQ-PgsFfbd*2bofuRs__&Tw
zhM)}ooCEEpoW)Dke%tz+Afc&u^)Ca-VYYM?Kp2@%D^_;AEP9lMlDrCM)D?IFd2_`;
z`#k7pX6}uc4NTjDf4_cfi%1r+CH{Ve`JWFAKLu20D+C0WvroPCbqmC$OR@DZS2h$X
z5fZ509+W9T)5|5MW{FzrLf7z0zD9RpyIh1+O$%Z!{BTZenje+if?n!t&yDu~|IPfv
zrvM2$jYZL{Tc4fA4}rK`CNONhEY)_@Uo$Z<9=5-qVKzW9{`6KOhJ~Odv%J$-^O6=YM3rXQ5_eIh=_NU~X&8UfOBRL3PD9q@K0AnhlKT
z?V!R)rmPY8^mn)2*Z$vo)|Xb0bgk1pi1hUdg_xXakTi)PP5a0&zem
z%LP~_G2oJwVUPJG<;-zN#TrE3X32x&NwM`z2nJ1#)clsQ8cg8Kn90h!a!5ubGbH;l
zh!uAkKE=+iU2hSc$#m??Yc$XPXUfP0(F-6`c=Xf08oA#|7Dmj052CPTn%R=*Cq$u(
zDhv`$wf-2V3(OiZZJ0sl3@NOzOc8R}9)v}m0}df{pG5UU?4
zjU*Z9f&;X!x-_p)<~jUxS9*LJZEGioeh$>OaHOeoJb(Z2+hkat#S^BucLfWJ<9q4N
z+P&+CLqZBeA8}}{QQjEX9mqO*^^N(O!bj%xG0vL3@I*3CtmSt#>}BCN(=*6TW>l6W
zWK=x}N}yg)uzBEohI=Boh=Cfs^e|fJz^iD^%^)vSVG9Rm(;IGEc-*!!F7_~
z_qB%i{wG{)6jQ%p!3^;nsLgQc$TY@56F-S%h@fbkJ{dK4;+bEKE6uh
zXk#g6%`@`h%!>U_Y+7iHiJyDG#7wEEIxNB$4N5^x;PZ<$mQWCtp`Pv7AHNS`qJgb5Y`LPp0G~9f1f7TaM#O18?546RQdV$*Rtj=TfaU;A8wR$?J28#8Av3y6u@ev~YCYnZJ0
zo_I#!&t+5s@MZq8w2fmDw9OA{wJ~@g!yo>Ky*mEP;Js}7iu8+@RpokN%vd5df*-C-
z6j>CjoYHBox)e)E^r2y$7vCq5QNCM7
zF!uSx@7G6Xrw*BIa(P}cPzq=t#f(yQZ6>p)Ww``1&GpM1@zNH`XA(P6BtMm()I
zFdD>M8R@F@rH=mhZ&E4j7X}Nr6mZpM+!}aeD8`M^-b0?+wnDRmfzNIwf;f59PW+`$Mh;2R
zsnY6m!>1qDtKF+x#g*ftTIUd0`;_;f?xSIdq;&ixSrVVUD)pK`OM}Pq5Y)hO!@lFs
z1heh(!`AZ0h^D=Y1J|OI*p7=cP7@}qfglf=`*mt&(9&kR!bjN{&wi$S(HOysZbklY
zy44=i8q6gqm+n$r(47I79tIo?B}(TjfeYd
zqR$0y7b_f6BC37x35(^;@=K3Y`1A6M!-K%N%M!YVFq5n*x^4gktM?q7#2{>dPfrjV
z@eikwr!;v$r94%oS$jZx;tYH`*7ye7CBFAZi+eM!V%^3p1R#dDFl%DMuiQxl*gXK3
ztCOk0h481ME$wa1=?5>%hA%%~uSG6?jxRR$IT^`tPu57Tm34>|-{Wi|IbBlIXz4wGIEp#Y?5cO)4g@`uBy?hI%-vCf!<0s39)|2Xw+-YJ(iWK
z86T=Xu%)-XF?m>HD#${f{kkXYrZiX>HP~nh==uHCIEQ~IEhv{vrK{$P9%hj99=?$E
zCGw~fW*n99OKh}_6dEQ@BH)cKWhWSRC=LKA+5M&vO)qzt?2M!3L)QJ?iw{1Qgxw@g
z!gB%{X@XvrA>+nScdhY3M<&%zyYE^{9Z*W{I*%Ks(osb;W1u}Oj3S4)-CAiFOzYg%
zp@qsIW(jOn=J68R-8b#MQ8g;iDZb<#nC3*9-x&Y<@@Ux=|b0a7ExrO
zlDi1oIw%~a-j8WDgAtj5dL0#no3j(J
zNB?Y7WQ>`ID&2-3;ot?aYss+
z#WplAMOZ@9^*{UC7jT-~{aF@-QzNn*6N`*C7+X@j+Yk;ilKr1iTcPnATpUG2(BO0U
z66NN?-V=~piT=OOobcC5J94r>qlI9gFI+Eldz>F5%zCQ=^zO+1d4`kxpkfaEZ+K4d
zsK3QnLrQv#HAR#Z^jmc1RI-Ojv`5VmC4r5OV~^R$t;dP>BB*gTyn?cH8)JjQNO!Y+FiUq0wZg)Ki6+X)zi9&!*A4$Fi4Yp&X&F*KFLbwD
z#vX;)On_xv)&xwWwLh2q?=ut;T4G&f+c3kd2`V$)fovu}n9&m$=tl?7eivciY*djD
zs^2pHDR1Tmqqou(p=wjWZ+vO8qJ*qOW;6R~D#mCAEc37}5G{{e?USp^_;5aWZmJ%W{8V>F}$=G(sR&?UBe#A2~(8RNNe6}Y{`L|_b((+Hbs*#
zP&Nc?Gjv1RKC?^p?;1B|x^oNJ!$SYZcG@S&K`nU`-IA2DL3x(lk_>zGnj$Iog~;&5
zO7}u&wj=*Jk>j7)qof)`jA*SiH=?ElG-ZOO<|f_-lt0Zv+JFl3i9HyJe{sLXoxe#3
zwWI>L{d?-lp==nQ8NEngSuk!UN5B^r2BJY@6rY36bA(EL5ELKh>twYUWP~3_dy)JN
zqND}2Y;X0=@si+NTZZhdpJ%fo)0R#e1E^d`%+!EAIB|NsS866)Kq>bO<77uQ7bYnF
z!8wehxQwf>DS~b2^=W=H*X#`F&qp!GNi(?#MoU~%oaSWY$ud)2Kv^d^c^a~%*f{K!
zIj}Ph_;PXa{xS9U#RaMKVdpX}&7Eu?1g=+eozTN_$YpoGx*&*$bY*vQQPPc{o!}TP
z;0HxbBv<8o_FIO)Q(5Yc!&RBH%ey%Wj!(SudcS-(o(NV!TyBfBq8(zRZ_=t}je$p0
z7k^A|>#8k+E%(KDbz^Yxz6^n9m)$>PmP8!W{b`(QX$g0PmZ35Pp~N`!TXFUzV+Czo
z3?vmnCaKF^1>~0K&J4ZqGPaVr)1Kna6<4?3%pLGYJh~RDs2HQudz^GN%UtjhX62@-
zf6KaTDOxxtSlKb84V^leC&)E{8^!526u0MPv^ESw#AtO}E+!m0z2Cb%aMtQ78EC`#
zjgXsfC`@5N2q|B;MdRGTvpipPB|Lhi6g
zqu0~f<_!z79US{~YPsfNec*R^Co)4o*|!IIH!=
zOXtqXnLcc@IWF{8)W_y`Vh56G;d9Y7=5EZgD}GkhEq+{hamFKOR*ab=LPP1>U01z5
zU5?E^ZI3O3x!@8x*`~`&@utwMV+Y{>hLn%zElF8B6M%#$3{$nT5pr|mmUWd6&fPKC
z^ox<70MROU=cDT=hVUKa`h4kG+kOI5ns{oF~Q@wc+)0slkIPr}+
z9OeA;uJJ7^t91EWe!CunU)Y;N3vl>s{}J8!k>0E>0#_@)6nOYB&@9O%6V$l6gT^$q
zrTfW#m{}0p08#Uk7WEuvn1Cm3vn6z8TYz&6VUinE_d-{x_^Tl;sxVfS4$!a8!g65#
z17YB8rt`Zu4U|MOuOR6G7~1a7Z)8i0-<+5%z|bl^{V&(RI6AS7;$wXtz{2+>G`~Up
znz8f54dxXf^@i{Tm3GrV3e4W#dj2MZt{%BN=||-4(prq>i{jro>-D2??a-h#?iiqZ
zomDC>b9*0tje3F#wDfGhaiGAypG(^)6!8kq8W!)0t?>A|xbseGH-Tc;T=#tR9v1gZJm;y`$Q<72hZJx4(cr
z9{wsB#u8@2Mvf7u#|pxH$n5S1!hDuxIj`w0OXOKlGK+DKXz(R)@_oAY>-fVgs$b*W
z(TI&R_cN~bcv5hRm{b@GZLU5&Tn@1!HbO%^Xac`~j}f)fQeo#Vz6x>p)68~=Snx;;
zmejI56*5gq)3sbBtah5dxn?lUC&7Bc&QdiD*=LI-r5u*YWSM|kVr=!YCR*q3;rK75
zTpdy$d&dZuU+tIw*sxv9BUJg?!E^{usl}bv0dp6}!w=q&SD+)%Hb~q(m{Dbf__Drw
zevgR&9HA(2JH4%%t+$TQw5Fp2R2QoTREp~WI^c93iyLhg=A)GZ8u`O$QYRzQyW4gd
zhBpE=`sgemHv%6O+aQ6|w!?}6bO`+x$kyO~sdBj*cLz>u&$2(VyN$ymB>+s7>;5$>4{}Vx2
zK(oMbJC`={5b2JRMx%Mplc<3~?fC@ZV`Kjy-*VK;1G!TL#n26vOt`c<$??!I%rp*t
zsGS%MG_)ovGilZoF7S2*61bW&*4`BlU3yhM(ilmrVR3u49a$Xr;FE5$$_-gd0kkg_xK;z&%^o}2El#vjoFMa_
z^fEcjE0cNnP=
zdFe@~vIE)4FRa8pWYG8k3z!DO;qvl*(`;8?DWDL!47yFDYahw2+nBnZ)
z5L~=CgWSW_6hOj~QT=%*#Gi7XNzIg>KIxAM$yC}?oiYFfo+Kk#ZM=-skf-zuV~U7d
zEsT@Ywb58rE-v(F4Ue&PaZ%2-<)d4BGEYfPG%jh@CKeJ;A`<)v7RRz-?oMDsc6p_c
z_k1||B~MK)UgWa6OY*N+0>cOcaY}P@n%`LjArGnqKu6alPgft+(F*+Brx(Lzb?bJW%ZZuA(-jGdDYR;iO1squUG^66N=vZ
zcS3ug6b4x(&zuLTO+DFBGWj?SZwOBij;nVmE5+~7VutZ?wF5)~R!+`;M3SXxLw?g6
z9!dYdaip6rjY(nZK}^z}8M
zf$FD>v+=cmf(E{?9ToTNZuS53UXTUo_f>X4r>bT3gwZe;VKiGI+8wN>@3um3lpBFA
zn5}zdeORFeP0%fVz*p)4{u;!9G|S>)HpuRL2!*>qVZp;&M`A=hOI;qFktF#=rJglwaI9ynI>-1l$-HrtCucS+doTMj$3Xbw`0%dV)N1LA*<7|?V3Kb~?O8W6xqj@G}JQ5j+O4S@zSWwb~eZS+y6oF;HK9>Jp1J+
z8s5O7Xjot792qIZB)7S8_uq0u;8J-M5r6Yhze$1c3=E&K4fQ#xZo;^XW;UAthqJc~
z%j4_PJ&^t_ki=a0momQyBJ{
zogOVO&i7W8t;^=RxT7=M4><0AR1)XZiWUAwIXZ5j(193)zSoH-l#$lH`7CBTnhoR_0Ss&F}4Hd!XNE_Q9oU5)V^=-=3=*U
zbZ2*QU~k2H>0XxAl2LBR&7%U7ugnXN1CuH>JD49{f%OA)fXe;rUo7Tr_HJ(OVxy?0
zh9Sl8->o#^Y0D6GSdQjZtAz>^jZqyqD#+$%>cf?TDb|!_>X#TH_FflcDI$>WGO>E!
zvCd^5@JqlA9u%dNlmt^anU?SrrRygalq<#vMJCA;CyGt>TONRp*-^EZ7Aem+vN$wZ
zHV+STOZnY`Zs6vN>9t*cZRt
zIySUIAZJ~6?fU+jH}-9nRWv_&7?v7isQPNpKmBg8B72A4z8kMUT*U{~`n@GF&e2ym
zw}Wsygu&sWSD>S=g4l+W@J!-MP
z13V9q;``O;+LpY-6UQhJ2v2RQTKM#$S4v~)*-KjK?9;NowZj=eC~Xz8if6sXRRy;N
z4|B>I7CVsVKU7#JI4^y3)we^$j9jKpBPc8TVSC<+B)YC425$$U_8D#bleD6KL9Egh
z@T~R#^_;Y^Uyezr9(nh%%b>jg>j)p_Ay-ETgf)z$lZ4wqkspQTA?7HK=>`e1wDCIZ}!GN_Z
z9EYH`OXN>+l+*go3h-HU!S5$9dvNmPQYM8mtqZsUYam65lLA69Z3t1Gt-?!&gMDcMPzg!!3A|zPn9TaKE+0_ILU2wO&N-T
zF$dU_PWfC_N=7;xIED)v?&F8W6A2OvK}pHBT$}`^^nH*BjQCRBpAdT7l@H>{=ruq4
zCwu3<@7`-SxHKADwY{~lw|;n-kn#Q@+vDsj04p^uZX69gWFsoY_J}lig;EHcp
zkVG`g`e{?264y0m8?bY0snxUI1G{O&ZGpt-;s*L|vPF
zxJECMElPMLW7W;M;v5MA?GM3cjwTrJXR?QbkyK$vj6pG+c;s3)m*n{&qV{}b#Lcad
zcK2*T_$+g)cHMZt!&T6{72WXAY7ZBc;ByU
z=tV<|P@C#3Osel^l2{n)WL|F=(^eLFZM*sx^Z(>r1ak=t^vN7RHdJWLrOpXet)<^6
zNrcAI`*aRDrS_a1#D3r~Q-Olcrs7~N2#G>G+N;5`5iH0d=S@l6C^R4l@3rO6>6f(L
zz42Wn1>`uWlUc+ZE~znFA&?!9>A&prUgMgFnnLG1)v%W4gC%9imOudt5`CCA-!GXE
zUic5V;`==2RK&JN)Qx8Z@n%cG#O!jmMO~iAU!Lx07zUKX-p2iPt1JQUou$$pIK-*O
zJ9)NKY@U!u8!o@?asvCKJ)99S&5s?zDYLE=4DKi4d`JMn@Nc4TUhhI&Tq
z+L)jBh1P+@j`Z9(adMx?#g)M*)i9^TD>I?+*Srjx_Z9%tFKhp2U9
zwPp~?#$d`R6SG$Bi*%%ASk;$S?l%lb$v7O>32nMd(PpbKt8{w5YhKE`$OK!B_Uojh
zp(|>sIlbRB5qNJ-+E!Fnip?h!0y9mmA5hR$r8?2B?=dWA8b8R+7V-Xl9D&sAy|!kJ
zrMMxqBeori#;9$S_BU$FXN`pRqosa(_F&-cUt6!E8erb?l-R{M;o~ojew0vz!`d&V
zI8D{}H}ad`9!*B$(=pk8o*1!?heH1rsMJrG&q`M6uCBr%kiDSiomyN2-f>5qrB&yl
zb?>0N$e5=oNX8BCy4ok}SOCEma(x
ztRN_fVR`XsVbJEOemb0d0@;B;m405};GITV)6rBFe}HL!8MvfGtm5UoK)(tDQU&R3
z20ECzYQ1~RlRhs7BHr+pKWiJ5;i*fp*~R$G&QIHWZ|vDzyAl-1%q(3B`HgomGh0+2
zxNW^&I0N*_+Mj;uOH^IGu9yNTbx^@OG87XW+VuBFR;)pGiZr{!M)k-fN?$u$m^y!}
ztHUtY)6W}`V-nkH_sgJ22mJQ)THNn~+Hp*zVk`hEf{S{3nPRtjtn`5lYL08P@OLrG
zojPtXY#0qCR90}D1d5T007Gg}*IC7!uhG;(AtkeJQSnZ4~
za1d5ZW|FU%Rj0rS?8^|%Sm+wVJ84Z2Mo=D1Yhr>I8EXm-pvNBNh;bn?$A&5{
zEuA{R3pzHms%K1Ud*!HW#>K=bGLTAt?1}z3KrgHPu{ZgM=0j}IjOefcY8p5SAGNafNxTS6e?Jd#9Cn&l`HnHe)tQ17;X1@+zJ`Gx#LV&*V(e+)=
z-X*2Qfhkm2xXt)VTg<6ZWnYynyT)u_Ks|~XOV6ugp?)0eN!lm`eqTSC#PyAvpJ+aa
zZ(K_Wgw5_^_@9|OlL{0Lc-h7@BbXLZ5oZygc8He^l5t59>TD@iM7hQp5B&`KV*byYONDF1ilf~3m!A}Jhb9Vb};mo
zq8cYMA;g!}rg%h^u~dxco#^;*tA)|^A`4wYX@l_ZUlkx215oMLor)gB;C9x5HHo_B
z6LLC=0L2BYqf{6>2p4!kks&6@;R~WTF*_?#!UUDM9>o(kJu+h3C)ZRq$3S(gaa`-B
z_0==$?vmEgB92h}seeIkt}8vsWjIlC6zEZo2jNMg(2p!L$y>8qN{tmI+hqiXZAi7aKba(qElHy
zQ{02`DuVK!RR)@ZOu$qCE0?)rcLi9nPBI~Fk>E!Q8|G`f7>^p`mI>1V+eIwInzG{;A=^L)cPOb!Z
zw~9Nw;1DzjDtC6Q8)WE3@)G(DW|;48eKW$5iY-kOv^GkGP=xHx3U=%=;I~F$IM){v
z9$Wp*mo+t|RaP(F_+Cdc=dE=I%Y4Zw$UX0#IK{`9l;>kaOq23*u2N4QiQ2o`IX-zV
z^L5z28IDn1TYc7+zEVdrxig^IFLS#JG0$c}iiU5I=EJn0HMRhS7)_32IlpFKfKg3;
zFGU`9D@$$ik%vUgud*>i+ANvPtMz>{mL*B_o{v-OQ+gl11wX9$7~f=_Eca;
z`g=nxEiI}!KXnz)b>$huUunYkcx|!)l46YJO7_cuP4-~Gu1Kj_W87+Sbi-v~jADC1
z=fj1c$*US9H1A1OfPI}$5Jzn_)%JbQg;twirrG8Cy)0ksQ}CuEjsvY7r@KDhEAlb^
zkxW7_z8KI?Z1Iu9ayUPq)EKXE==fgvci|KbzQJTGYhS;7kLJzZsC`HIjj|raO@MB^
zGpoYDW%giSDA#Evd$CQvgT2i#$v5+<^`&FrT(R{mboV~{@z>LZHJ+JUAsXwQ=mP)I
z_eM?n?mv=Bxm9K4SO<@6gC(szI2Gc>T<`}N>I26$M_O(a{*Qf)jqdlff0ni}p!E4i
z-Tk8QfzYQk(s7u$Q#1@zjukinMb28P+8bHw_V4(UK{>Sgb#NjhdY6VG_FFYP{UJoT
zXm1*e-zG13*B)qxKy91Jo_9$0?TF!_MYR6m=0rWZ3I-DW^fi>7)791`LZSgWv(6wAy_L+C|+2lFdaUIe8!ryUC>g5%hjmZ6*?Unmrw~53GUx4sjuX)r8U%;fcqBol10#6Yo%}ydDYL
z7puyGTg+#YW-&;-QnI(Wt`@$DCKrCZrujg7c9sUNEDpRparI}rgd=x^9XzCX0Dx)(
zozuBNO&&m2FTL|d{P?zTX+r7DenDe>B0MMFA-)tx(+2z}2J7t|Idw#^`cFC9*y*5c
z41dvIEi5NuwPrGzx7{qqfYGM1>p%A
zAu|VwSB(jy-?%I>XR4eT;Ie6mTMiF@1p&mcqV`5zjo<26)C|sS0u+w}2+$>OPeOJZ
zDC}^7V{d%#1$#^%TtWV>All70(2I_DU)boUOVZ>=BpZiQC8Pim6UZ!Bl_;^3@!H*#
zw|+5Otqy|P9o3w=ibtu?SnK2(^x$mgZp+Oqk-q+XQM|4<>gf_7DhG9zA?e>iTP~aK%|0RV8
zfK}Kj`3tbo_
z=@Y@v!k8qftL8HQ5SXIB5=obkn6uTonK#DH$S;`
ztc;j}Qdfgz23_(uAP0gRx%V%b@5%R{$N?DJwbT{65JMs_dG=bdKtb{V%tjWSx~P+QhAZ>m#Wl2k
z3rd1WWt06cx)@*=Ko_^&`J^TiOCiyf27i+gG2qV_d~<6LSQSrW*UXzQqmyhoxE=MX
z9#=sK;*Hgs1mSug3mI2K8H*2Lu^gIxM-2;(frXU$u?;wXY#Pwl%p(53CY}%~@W$>Y
z+A`}?G$!oK5Gw86M#v$+_w(yGU)ZNUb7fVN?iZ57q2a@h<)a6|Q!Bboh58{~1|LVN
zKVv!)h;l1Z7QZj#z_vobt?Kn+dq_Y==8#iGho^ZQ)=RdSQ?1wN=iKn`#SU{IMfT)1
zsZ_W|n$-0UY;%@~LmmmT{?97g1D(ch(Uah0M5&rQY5V5j6~#x)6x!W1ms4|3?dB3w
z_s1RFTwy65K~}$BCx7j;8Ev!S8#QPd`i3DGUV{6Us+h>P1upFp;NmC9nskaR?cQ(M
zpFkcCL(dLjsU#>5^<3=KH+NmUY)D9blGf%kLJ%WS;1`LgAk6aFAjXcs0qZemrc7WP
zk8ubM(Zk_gl)~M^jvf0V!}@L3t_QnY7JYJG2peCTC2_VJd#EtBE4__2z(DcWdBc>v7%Wqo
zN*3~LW9*lVO50wwTd_lp$O-ZHD5>b60mo%93d3w!r+QAtG@~I|RXanO6JG@{&PV6_
zo=mTOS01gs(UxJ)a7^rRU1Dq`j7)jp#82Boi6=6%s}6>3msJb$E=MkI9(HzqJ`P>a
zG!GSn5}FUUf1cmuZ;xzi>XMN=8m)mfvY{Z1r^~x_SGkV{VOBI(^OkQ)cu7>y2`IT#dga
zX^EExtU7HtzF1?fA5v7@jWOHKi^XeynG*aI%`@@lpLNAp)7O5HZvnywwo)X9;OO`W
zI-ia)zQ{J;DOeo*IE#7^WrXTdpjTCMW|WY{THfjbQ!-aDZ-b_YRji!JaNWO&Fy}Ua
z&10{tUikf<+EOLf9qNZ*ULy6Nq~6a{dVHxG32BkIcuYv+N?8O%VUv&Q2!oH$#Mm^P
z%pr0fl<>kQ6qm-JLO(4?jIaz%>EqN7X0mP^TM~8_8j}s5A(k8LH?uzTLXCY37&Ykq
zV#9hm&lmlb__qJ7z(-SAZ5Jy+LasF1+?R$KJT}Z8e&p@a*r=IPN1jE{rC;0~8XB7%
zK~sYbW_&8NJUnjXl<6xig#8~>8SdNfAoM%pN_ygk96B11sB=2!2>|WBQt(xb)#u6o
zGQ&e(8HZ3+0dhjwHv+{?xS8~!+vPjQd%`ub^%{d*(Z2U}&`-3%+H*Z{Kx!gnldliBq<3f2Vx#%Hi
zfCf0K&KpLmTn1?jCKVyH+>L%@AIRr4OZI6jUkX}sfhK+5J&Lo5HRLM{vw^qt(E3qt&sJ#U$D~^~uFV
zM+cq-L}MT7a{5jue?&8IJ6ID7b^~fG;#H~H@KmX0?yXY)HDtc3)3RIaOVropM&+?g
zt6iav2AgP3w%|}kZq5*zU9KuD#nn?#qrECSr;16_{Q>b9y2DBy@sGd{mvM|CHng?r_M1$T7i=Fhrz<4u=e(xdxODsL|
ziwlWsh-(f-Nk}}N;;Tx%95nNt%X)}b&1=#!?%Jh8h-kuU?>nYXJILu%G>r*+N*P!m
zi+_nqdw;05S$0(O5~XQ^uqsiD;ZCJ1S;x3lKWV`~e+*i<_V-(#eTkX?I|yNF;M5th
zxC-%+kb$lvzzt*jeYZEa6^D(Xvik1)SJ|Yg*LLm61YcDW%L#<=A!s2EikP-&7JQPT
zu&N7mc!mU4F=65L&zSGCv>7+$sfh-roy~(VZOx$&%62Km@p0bEHLao)K~sgrZ%<6U
z^JHM6u4u78H!Z7LfS_7vY4p%%GFyHhG0Rs)RoazpLZIk_qP(ykVRr`&HlL{H^?A0j
zl8KzFJ+oG}U33|^I27oSp^iAbWU~i94blQg^#}xlCYp_^)(Y!$P762lhEdzEKiA?Q
zEt@sl$wtn2&57Zml9h{NvUPMYJj*J47u|1laYg4bhOkU*K}uZpcEBQz5>b|U4l!jN
z_%=;bE+Mlk93}GIr^Y-g{usCeGf;=$yX^ABmS*`bw3f_A9l9p%sU9!%y03eLgWasS
zr3d62miXk@m7dV&jzJX0J%Xo>&&0}kjeX+ME3qyY+rN37>ufu#>^x!v)qwg!7QJ{`qW*kNa#Yyz=)V`!UK4G4-g;b8(~z%pa)>?QTAs%4RRw#ll&G%fyHC=l*rvAsB8*gwW&%a`=V!Z#5ycGLmeVvY4yWh4iE6r+
zXTO$gMR9TRDhV+Nd05qN8rz@aF#O`|hk~fgPUDdk)QsktN#6mh-s%YG-_zzyO+1QP
z^Dvn&Z_xWzJG_cnTz*K_sSd%pCD+G{C@*(!cslP2^Vq%H(DDhmiU?(u>FV2Ry6&9m
z-!BkbA&gB4>)Qh@)UpJ?UaXxYo8pw(>!?47_I9jbOCEz%#rFfFDe+}^2sSvP!8<8T
z(p3+eT<~Tlmd<@ks~u_Zy7oZ@9{Rx7Ds!{Zvs#$4X|t=#p@>Vyp*?x(Q72V>n{bJi
z`I+_vE&5pn7EwikV;QqfO4wCohh|1V&&0yci3OfmV;EW
zSLR{&h;KCaTZ?8lpdNZI^DOUH02im_VCyrD?a8>4bZ_Q7vOG%>D*v%E7MX=vG5_PE
zNx7TECIwTjZKG8AZ~Kvlao|_?n$okk9*gKUzlin8N95m|UE_P^SJ~u#c@CJG8ZB)Y
z6t!o+&#Up^QCL>Ha=dzpG7!u4AiM1Wdd4e=$){t~-Dy>^y;aFp_x4I7wsqLq80zq76pO_?gelh)K<
zqYa@DZO;|s{@Q===UB>EIC&o={{7N0d~%^1pY3pvJsJmfL$D6L=J$8s#N1z1GY;v&
zyD6@BXn_~J$E~)bCX3u78l;VE?&3(qA_cY+klOgUY=*&zIyj}p`0b%4^&(2;z@CFu
zGEZ8dFjz8v?MGE;W7+_VNmtY|Z#Z~gXeCogq->*p4-F>sqcF?tS@HA-QEftr?J^d2
zWT6KMuHya=WpQwQxpZL$YwttjmRgTk5B`p$Ild~+J6PKH!#+DZ&-d#mT_ZEYrujgI
zhMIa(vxKw^DxmeykP+1ntW{N*G
zno%@w@f*$fuqK3)SIC5hX>Sfd*vCbW95-lo2N?yBTR$-Trf^Ld_29{QJT)0R0%?pf
z>xTyniCGOVN1utAIIe&6X&85pP)!Qb-sq)d#(z6E?H4{~ntpgDzONjUkz}2^apG^B#^A1n)WCiHSh}L;BAzQNvvFwih#V
z1kc3TG(b%8^}04x5Vnx?;G_k|K~yQ`-*q<;`m7b-!hx?#$5?%a
z8rRFl!3&Ey;S{KQ$4f|fc2yiz}YO+NgJB<7S(iB3jy5i85Z542_0Wxb?K|nJCR-6
zo7r*QUb$6pxS)eAXAI9XFzYyb$&3N%@T%Azu1-{=B)r!8E0t$rRpuf9t2uPu&j2}T
zk-FHB1Q85@{Nx$V{_kiF-%0d4&K|z=pK{KqwG`O5;L~f+SgFzx7*WXO$h+4qm4=e3rp2HH>o;cK
zdSmvl*S3YkN3F^@G_XOpNMNB!xlSXz7C)vAS<*QE{$S=#URk$YexU`EWrftJtmP(I?LY^Kr^ro+Stl}3)S6-rS
z9~aLRfjulY9vrZG{vcW=6~gl|hKnm%uhb`t`vY5W*H0=lPnD{U?K;RozpLs~6!_(1
z0LQU3QF9d`YFVMJu=FDRv90Bi>6Wk?;60WnIhKx>Tn)T>0?`34usq4yGz4<5BaS2v=Z)n=XLMW@
z?a}!t(}6WXfe|ZE>`U1;4^C-+QSLpGdDGhXWo?V1zIn?!!?M(Sh`N{nz4BXI-f
z))-k{kEyEe^;ZvvYLSCDHKk!&hKf=TeaHwqOT3HEtyn~|k$BY^7a32O@Qr%aCFL)9
zuQ!LmDaxi0qRj?OK#pX1OMQHQQ=k5wSgo1A2V_4zZomPK*U3kX{t_QK+^7;R+L+##
zD5PZ@^39j1xLDgy#l9r;apO{mS#5zpCCg!D0J4{ap)6%G|Ah)6`P$EZlkvu7`+LvC
zjcM4dz|*1+qSnVu=J6+8d>V%UC)>1uBUgna0ht%d^e$1OUaJ9z1OH8Q8^hUyAjXROrM79;aS1jb?f!$Tx)RaoRrCHLMp)BnI?
zmZU|#s$yrb3Nz93>!}-ZRuxQ1Qy~blFPe=
z=msy2#KxZ-mb(NfEigYwb~6JFWkk(en^aS1z<{v-0Ut1qTcF|z9zyDjQPzTr_+ek=IrGy>`&MOMzG>`
zJUdF6+da~l^#R-4(g}Ra*Up>0=Y?|{gf@g6si;Bw9fErHN?*<*?YWA_gk^H3M=5*4
zGd=Y6H%G|E(A9tK_W_o~!BU|E_RQB+Y9!7;Yp2nQsh
z=ue%>fZ7r@lN}U~Q?5j=9JIIrN2qL4-=lcyuGfcB*YL^u@|n05A(b`!`E1=Ahmkh_
ze8ZYm#X_#n2h%yLHo(AVyT$=zYg)T#{65)X4}@L%*+!N^Pc`IVzCjKjFM&A=vfb)f
z#CFADtL#}v2=j-1GO`t&WjV0K%VghX5}JJvr259ayC|M3tIxz#$zk(}BV0hJQ@T&U
zA{Uh~Bm28zi5vh$?@1=K1LJAw6f{sfDkFKw^&@@PT@wvRW)%Mkp)#&Hdqj7yUUzz|
zou)Av4PGxm5EfxoloTDf{96)k7D81wBDZ&y)=-?@MrSVTttdi?`|WcY*my+C$4jW0~s^AM1aBmL(BHzFhWZOScxnII3h}T
zAAsx+KP#g`350)s#0?v4wzSn5UGOzae~DVfnN8?OD5O-})HFFRGR;+kY(%ZoFyM#;
z#K#_s4<_}1wp#4B{}v9;&Vc8aJoJh4yFS@*lA%_E1&2e?N7+BVj|1dqQ=H4FH~G0F
z=DSCSWPE&Ds33#qN8FFer~GgRismezflGW7pUHk{s{>&gSA|^kqu~AkJNkbUn{lPT
zPQU>|GoAVWiO~FCnOET#cM-0SQ&f(-183h)5sD(a*suyeGS4a?SS-BBeyM(W)s1U`
z8v|>nh-}K3rwQYxR40p)5jhM558}+_w@o%Moa;zR-%}6
z+#B~#$gv(1CzJCjP1qJ?42@O%z=Vrr#0+2b2>sjSLw9EZTH%DD&wgb_W`p)?f3H67
zu)ek9=aZMsiu@BtMXI?h;p})jaIw>c#D`~L
zk#Go#57{2EbO_jf?wMKFh6?(+7ZjL+=0gY(^NSizIybi(4upjOf_&4ft$*1XH*}D4
z*Iz|kiBx=Jv7nO|Rthm4Hx>V(SV|gZwdXB!a$L>ZV9ao&f4+@WJJS2bTzFi{a!tb>GL1TItx~$BuKly8je~MYV0Ge3OtEcH
z{i9jO^=GV4T><2g`J!tPb0i^X%_w1y?
zs|XEoZ~g>lYPbX_^Owo_3T1G^qyA7LKnHEK_O{9$mUcRx{9n2?XDe!ob0$LiZ)Wa6
zq&M060$}TZSFH#Bt7>gOs1B=MHS(9O1Ig|^hy%_#Owm!yC(Q0;Nspn;7zW%qm3-73InFDqO=-!wb4362j
zG)IPt)n^cMpVxd72De!({G`itw+`Srv9M0>vJ4VrslQAe20ZSFYge$pTqph7AJ=SN
zW1Vxaa%iETXUX%Ux%i$D@<)9Y9o@xYNQmqlW}os1w_o!!G3csxGrz&&Rg9ks_{{cy
z2-ljiVqp{SoUkkukh)4sz#(R!*i8G@Z>GlV2P*{MQ6n-Oa4rSy?`niLbxRk&GyQ=G
z2-k!NOj~(`h?NZb@x+6VAEPxL{;VgV;sEM4-q#m=k^d@M`*J7v5^~FO5vb~a`A4)C
zxfl=7zsLi4FSaeL^(fcWU~?=HDK^<2UpFdU5BenZO|%xAVCeC#d@JC&1RWdi7U%gG
z)nsaIV>8Z2Lz_aw3vfPs5){yFI|yuuyW%?Xsra$qAzF&T$edGsF9wuO3!7{x6b=bs
z6L#{k7zx9iiGKy_(A`uD?72$T#jjCwnw&k5BtIXZ`97*Hy|a1kM|U)R6(h^`kpluY
z4aVo~v#5g0K3#yQZ*BTK^YN5Wp!wb>*YAX1<5|JR0m~q$_jBp@Y;kdnns4@324DvuM{@`a8>Vj2M%OOC7~qxNJ)jvBwFkKMe1Lp
zfgM{hK)r|SSmLr7DZ1YS6Xd;>_&&puW-E9k<0ALfQAK!^ip5JZ!HWDu5&fLElZ`H+
zoc2V6X71vmeyO=@Y^XY)YWH=fO+TZe~<
z5peg$R(fpZpESl;y-@>al%fD?qJ%LSw5)cwx=DRXLlsgp>ASdDY}T)^UO;t?=Q7S0
z4Zm*-sG%BTA8_m0KLgBtgUt$PSAR*ndQC-YL3pOTyA|p*U7P1#f4Z7v@e2Yd=5Q8X
znK(cDlbw%@H7fzIL+57k$of5+EsIQQ7QKG#gRr3;xb*)*plGbZzURR?@>tXd_yr2o3I1UEg0eV9egsc{f@=}cu)vA8Hs3$7-=JjsAM96xmb|qRKoym9c$>3
z45UV)B^VRQ(u`*2fxxEf4IN<`NfM3w&e8HEpE+;x&XCYT}zHGJ-$rIS1{vuci2y}DBeiAy`IRlaDba!w8j
z_*5?2RY1hb6Gb;+k{76woV3WB{ws7zQBVh+L{opa9(jo0RUXQAIHf(MeYGE_jo%zE
z+}tn*x7CCJZEGsS%E;wz7WQqLb)7LG3yU}7hr5(q*Vs^%T}0u3TUE=M)8=}N-vynx
z-~X(Cx_@|XUL_F0mfHsn_+8D6xCotq2Ce}VM}bUwaU*K_w1BN7tl7Cq;X{OY1evPrXW4L
zE}CcTt#|>$!YNm?6amC&eJ;_5gHsovX`dJY=+dy-05gaxMUbhP*1SaFm)12v^eg($
zZxr3C$oJ{1YizU7wN_BqLp43_S2VDS42{j5BJR`JzMkK|+Fbn30ketITjRPfPfwpn
zISoL5B=G*5U%hiAcOz6C2qbb!vqwauoEeuH4{aIIl#0}LjFD4T4sUa9JysVIC
z0wb+2=6mGS``1Qa7!*m&I4Y|RjVc$hL{jMvDaJ!m)Yr%y^+vv_W3_6D7H`1=i7w0b$Xszv2Tpt_m4&7zcKpEpKpKtAuVfsRp+s!i5v5yJEcIQ
z5}_m}J2>-7A1@fZX1)L_Agd<06lxm?a$)&-#(t)Iv6yuc(*kcxz2tBA5?8z-FFoqP8;F{4&lv!EUPK;k*gCfm-
zhX1h0uhE^ixDPKfA&Mvig6ucym>8u^sE&k_On;y7j3RJOi&eiMK)KXn^D5RmRu9hY
zag|UGRnIsDj&4Hu5KNEkCOqGX-lJNho+aJFR(Ij=R~XS228`$~^W=m{c#gUCMaM~p
zySM_Zx=$N$YaCL+Q^Ng@LH5)oHjD7}Yh|%btc-Q=6v*P_7^F;mPsr`5k-LIwd=ZmP
zZE#Mu^ruHG`!=4S7^nwyfj}yPsKQ?hObF{x5q1#dm#!cepw|#Kz?!(a_u7N^08}uRum`i9KV5q7;7{81gHad`n6P=YN>m0Ogz9ZZDu__tvU6ic9-eHw=jy
ztpijo4a9jL@qIR6+uq0ByIZzL0N@>A#&&^LzUj1_n_Ydr1c)_3T(<}RQoVPYW8Q6+
zeTZ=Gux=v`k=+h)>=@mk1>u)48>C**Q#rRCvf`Wgm?W0Rs-`SCUd2f9GHtgJZ=4md
zfw`Lj$8TgKruz8Uk-74o)oK2&<`Ck+BgH_MOwZ;g2MR@jv|fK6FnaX`c&gKz2#qB3
zVfuZ6Q(b+3e~tP_F|OUXIhbJyD)@~3xR(IHN!05p`=sMA^i`Xnt9^ib?O(D0FQr^>hqbO=Cyjz>@}=#
z?8z&jH?f*_{J)9ScF&w;lg8p=PwSBFiGX!QtJxM*$LK`%2WT*v3k0sbKh_?ogk^0)
zS_<^e?4>>nhkOCs`aB&x;<-UM37A@}euZgX%>ts9l>Hcyz4kW{n%GO07eB*&laG}j~EF;CUIX%NBHslv2t|%m(jb4
zSpA2sg`9p1R2?F6b5D`ww|eOJ?r2};Tt$@hh$LoJp`@9L_1lQUbfVR6MhQdNvN50$
z*z1rWxrvbhZzs4nSuq$&hg>0Mx=21QQeu@=dp9Rfb8!f}Y4kf5)we0^B<4%jN@RY*
zTg&3~!}|7y8PLEo=AW6YbV&Mxl;&VKZD1=jqmy`9rI1+8`N_iI1^Z50cc}`m+3!Qx
zzB#YlYro;m-B+ROrp#X*K>JRK9jZE;3`w14trL~GM-V?exqHB{wcSjk<%>N@%
zuU=1|r?RxUb~Vkcq>VfitIL$wW!tJztx}|7F{s8;FhL05Fqu6o%va;c(;ivOitz!}
z2Nc2KD*KkKGlM`DA%`LOp1LG6Ml%2Q3V;Rqssfcq@gqQ4>vIXDzQ@1n6nU4ZKx+IJ
z7~@+K)dfxUDae=-M?)i#H49%bpM2+SbM(01>8-tKX;W*vJ5C5$T3W@`;W
zKNn7d&ukK<5n~gkMBgMi9-LSyh+6icUHJT;n>f1sU;uD7>&v7%))!h)wW`R9FUAE>
zO8FX0XD)n0bQ=w#V%7q7<3v#4;&0190FGk`Fg~1M($9u|M8L}N@YlnE7w;!`
z_QOFwr*;9)l40pq`T5+5_LcT{yXU$*AbI=fVXk=l>FnkYC;Do?_;0Qp!0Ey$2e5PC
zKFUn^VE)=4CjX!%P8k(9w?(t`Nv@g$5us02+>wAVD;1hsTfS$(e3|QP;BmLT?a}V#vEXd;rEM^0c<~HC^voC`hBgod0Sk0izUeP8ENp`7+b7lob2C03D0zYVZx-kx6tvb~8NL&Hzsw0rs2-+jCts
z6uH{AAPOGfZ`8~TTL{_UGjf-FPnE-)#v8hS%9vZ>_yF+6}>Hm{M
zBaZ7o9U2R_Zw?Kd>$m2LC$JIX$cS0l+%9WF1}#p3zeYsNhj&r|yIb*-WGJ+m;ZY|0
z#?HrmBFyVy8Oi)R@VX1$oj1zhU)w0S+Ew=`3`F~OU_?sr8mWUBI0v!xv_bPZp1nk#70BHR4U<0sh
z4B_rA>`?Ghhz|o!Zlq;C#!;mIbZkug@7i^F+s*&2cKsh#1}0C=N3?d;Gs
zwf`D2H~~WjBnszWL&oL-V940}zj*uVu&TB%T0%ftMCnpMI;9(wR7&8`Af1xZ-AXqq
zDIrLANJ=+KcZYO$y>-x=zy99$-XDH<>)mJX6?4rw)|g|i4Ky{Zs?A?`0_mkdr}RC8
zLi7))y>muEm)!1t0OWSQ+nKntnTj@|_NQ#c5QmJi4cDL4_2N24`lR5CBEl!*fb$(P
z)%gP5u=CZFz5su1UoDhK41L>7@0pqg`#hb0JPUh;PlH%Pa}kikSBuYZNxOPlhQb1tj&`ng
zj%3C~pFcXa_X0MFCi7GA!4*RUyn4D)*4Ufak}eIi_p1AuHr#
zCV6Ol;q>z8WWBbc^e_hDzTXTKSKa2xEUEC9qNi2mAElK~)PSm~ttQ~=MyFS5Gl($<+3pF@80kmc3g>Qt>2i!<4R&G()MAvh#Z`#Uc^5|*|pLKGe1hp&KG4O~QrFb9iXi5AD
zN>|DLM<{(Gs9>Km+x@A~=#)?R3omVC9T$dyv23+I!5=$&<;$CGJUJDW4|7V9nnc?F
zMb)rq(keYfuF7Lk&Bg;jUmfKj*^*(##|802cCP2Fu#PKH(hrZn@BuLiHJ-yy@yD84
z*J&udSPWDL^h`+rXsVqTo5ho8wxHznTfuJSPWsq$@%$Ko`+N0T0W)o1_WH87iIH8&
z3m|H!iqrOuGZ)AwB=RnTR9_6w<4@n;bo0XWvXsuh`QJJ!6xp92+*o1Q=!?*n%|ey7QpL@?HLd0*8(4>wv;
znhSINA*vSR5@JRKt0Ndu4k`QV5UiPfnl_Q5H&5Z==2YEtwb8(Z-!
zORjyR4nN4Ll1ejhI$(o+*^Ty7{*hx|-XO&Rg`X>pdvt{n1O!?2!DfJIQHIa98NtG?S$UG?k)MZkR<=W}1_4|8s#
zVmN3VAgd|1a;u3Ww2&c|rT>ROuDu0z!R+WDzD9#mBo7M;*-yoX?Suf}
zVf{K>55<&cjyVs)E^;^Xm%GqPr#kCu+6$N%#Wb~vjNWHjRd}RZ<(|;w|5@l^8y01H
zNsjP4DIKdsIGIHpFd-{Af!u+CRmhdl08}p;I@XfW5ahveqGp{p!URw)HIc4fJH2@H
zF&#zqRzuTchLWSJ2>f^ty%><2z#-HL>=bj%e(<1=^1*G{!BBA={BKju&mBj-BKQs-
zys!D}v1lYU)2el*&HiA|s2izMx;nJ5UA73`!GAE~vr9BiFaVI6dHy>#yJbZl`lTsA
z1|YnUh;N5aEYFVj)Zh1~e0tSk6iH{Izwc|-kchwkYYx)SU$tN%dj(N`<%v%ryWClyZ#57+nD+DqUN}r
z{LIj8dg`WhUI2}8?wL(dCk_WX0FI2mg<8SzmhWI|sY(b9u05w&y4GhuW41B7FWB~+
zM!Jze;!#ZZOX2}@z)+ab?+Q&$fK)>K+trv44U{%@iDosn$30z3bR+3IYi&zQmK6>G
z$#F)w4gon8^@pTQ2Lt{NcF~i4(AdX=FK~CQlmaPS2V{6rEu|maNTnB8O*TkRt6aA9
zfdnNoQbs=}{MM(tjhqzwEN6*i8KOEFQ#SLRXaA0rz9m!o(qFnB_)I5%>B6xY0_n`u
zf1>^92T9xiPWWM_*)M=CJH;Qm_G8nrQO50mWucQ*J&VtNf$0~auGv6&pG^X@F)n|R
zCwf5-A4
zA+-Dg|DMq<_GZWPe?LVr>~
zPg_aO!okF(PxYn)B96zAH_Gbr{=8AD2SrFvJhxOPk;7yz-GYRv#2d^G8F{VyU5Z^9{5zJ-;r6w|Fpa9NK!(R9
z$6@pXqTuy_c6R+?a!GEc`BV2XhDb-8S$kX_KCTbdeW)CoUy_eyfmI@fLPid@8f?;5
zUN@R&RwwUgUtnykfYKva?AwPFFrn>h-Lz%1AKK`%dU5x(J;Srnih$VTr{4J&l>Ru-
zTI3Ns|C`!l`DG9iQ|Y)VW*1_YbmZ2Py*vnEULoSvf59Vfa6Fi2Y}Nuh2ThQyh>6Cq
z`X*T1uiuOVk@-7~d^!RL6?=RF`yQZi-U9N{DumXTs8^c50Q4>l$Pgjl|BXHV{$%GG
zez(Qkcj(dA0hdIo(Dx38sdU>$-w?r<#ry%8oYwX!$cJk_5ucJrUhF5G>=~eLq5#F)
z#B428;~VF6zUT+RNL!@%=(9k~u~Gt6Oos-9>AxoP4EP`EWZve4I;(t(k$cj8(
zF>frB1xj;tGs>kd#hC2f{8D?RvKM*Kio^V3B51{-E~kGfNG|3KHNJ+*$s8S3)4|p#
zVn8Q?hZy^EkewOmtGf-`S*AN&I*mF$gSNywz
zx%d`#PeI;)W|Dg@Jo}#m0_N7H^Op+xtdYhIinN+=ojk>rVSJK9#)c3xPR77_y`3`B
z;2#M+pwvKrAdAh3NC=JU?L+j0;lRSs;_v3%EwI#tn>Zh!@n}ZXm?s{b(`ZhQCrZjK
zoBPMbH$}kp1VA%@KeN_SQxMHps;mV&3*Iqm&*Cin3sNz
zUX9^7e{TqsMCL|2c$)rNpQy{LVXwjQO-fgW!z(ogtEG7e@&Y@qJ2XN6^0kbSC3=jC
zVzG0fQYufC)Zks?Z=I?p6}LWIEQ0jTkG$L+-!~Cr+YJ1WYYChX)0>h`f?g2-gv8>}
zKRG-g2s{UEe_l@iA;JmK83d&pnKMfN?a$CRug<9+yti&-3o5fBs;YW8d0QHFU7=v`
zcM>_#bW+Q3PlHsHAzSq2Pxw2VfVrr3f8D2qA^Y+w!t7@u;Wq($Fjn8+acxi0Tx+bd
zL8)Jmu@Pjf5){mzYL~5vT$yr%s*?@xR*lRSp8vsF?xf0
zfvOMNVav|xCo$dQK!x0@31-`S$yFQ_2!gWH5yr>K+pgWG?WnS>Db_$#F(z}NQ}@Eq
z+G62>0f)v5pvn%zcNo)s2Wb4oaXp2TaxiGi;r)U(l*ovhYem$HV;eQXdQDno&65Ck
zDa$ZF?2>h=N_p&e!y$V`LpfwSXUgzJL<+M+aBhh$(%se0(B#!_VhPtz^VhD^mO^mJ
z;B)2#4hETrVFy}Tl4d)Q#_>oXkRl`UpOJDYB@EhzQiz=NER}#9V)Go|N6W`h@gTXJ
zPq{njmDkpKv6>F^SJ`vLsep&%*lUZ9e~>&!heGUy7-3;J#u@GaI049M(MiB#NH>E*
z!cmRtOf4LMrkMkg2?)KH{C+-lgi)&}53@JO$0MO99_$rLS~Yh-)}gxpWwYoIk5J&-
zPK|6vEd!@NxM#oAPnDRIfrw%Rl{IU1FFstBRCo!D6js&^!OXJs_EujzM=5&mB>53RHkj@L1;fLbRY3;
zG)Rz~g+HGj6x`eYf*mi2^hMlok#j;x`b}!-?fgu&#S!e*KKE5!$+hAkeks&es4YPL
zEX~+hx*{R?t(Y*yMCvc<4As!7KV#uXsQ?R$YDFWGGoh@jtOn*5`%I>|!4&>dW~>i+
z6Q>wbpZET*cGlA*Zh5!I%0pe|vFJ=;kJl~^(>D#AZI6O5E_PUhQPZI&zxa*d**uly
zr{r0OxsI0ij{A4~v*NLLx^J20G-ZcOn=tMab6IMhiF`twT?oQ-h#OI^2L}u=DUUdG
z6>!D@eb|O)bo&(=6dGvn|k)hh?T)SToS){o4
zPul3pUWUqW3_;rdF=Zbt$Pf4icfj*qj2e9l2zpkI)h|#2GbJf4Hkf!HiO#g@i#*8b
zDq+IdZ;qn>q0jK8mr))s0krQA3t_+_
zR~3eX0O&j91y5YMROXAYl{C03csa@O&F5#9u-O>Xy%foy+KsUjwN6b-<9f})CqeVt
zxh#QnnnYt^p3sTu8}S{>W$Hxf;?X;DavT)R0lvFj!olB?F3I1@aWe;f_4`(PWIz0?
zL{BMlFIt){EI;USEdt)=SZIU|BLOSjDQzfbc7Wv?jL3s&>d7hrG-
zYHRtq+4Ei3enfK^HlXYInsGmpt!6JE#`T+2eK>4e@_H(VjR
zmz`y_5Wo;@N~z8gN~s*~FjZ334EfGs>~;x;3vnYg=)bhnZl-_G(p`Sf`5b|k{1-9(
z;PhXY4)VYdjaWP#aTDJf#}s@0-LL`~t0brvsF|z9plgYE7M!Y((eZ{MAp^$V1>k;j
z4qZKtZ9oI7FKMGD5YgnlcfOX$m%yyjI}BUI!Si7_sh9y7oWzf@!w%yDeQw*mn7G@q
zK!p{wv^3Ro7~f>$RHi|1>24c#zplQLM?!LO)eP{-A}u%DU}}LE2X`*6p|ylMWs-#;
zm*S10mdQmaSL&4{Ty>7c{Ljk@0Y{x#kTy&s@ZIqGOQqFR%x)!WpJ0tM9QORbK;8J@
z)02s*QU8vt{_lm>|C@~C&|v46jH5bR?enluzAuBaDqyS8B>pS5ddgjxQXnSYnb0*I
z)a1dgFOF*OL}p}AEy$t0Y!Pc&b_o|z{dHmop{%O++vO2J!FD4KcgVNM-4NPp=88T~
z8`JK#G3<;5PlF#AcMDX{_9<-Nbu81jM|L)&_+mZDfh(%hT%zR(+cHW3c8$^Pw{C_OBo>m|4wp%wTnBdULExUo&6)Xe{!B(=w)~ll
z{@jr&ryt%+`w>44pX#}71rW}mc5^Mf{RUf0x^<_tB}Og|%kq|4{=yM!)XG_q0YkQM
z4rQ5A+0Oz*K;vREss%It8JN4P-2n6O6G0%q)A(oVjvGq)?IhjuPfD6+j`ts7xfOGO
z`pi|tm*_XCH|QA=`|u)sxQ8`p$)DT|;QV}m%QdPak{yZr7N88T`FwA!Ge!t66-sL&
zI4ne7KYH%FsyX*eL`xPl0aDi0`2DNY06CSwo=B2+t7gTj1mVLb*NpD@$q;Lzk2W({
z){cXOF!g0ESvI@!NWUHL0T65tQ7TF3UDUwv$uO)txAa1Pmv(5UOKI3=KdWW2PJH`*
zhVmCM|2N`}uzw=zK&_7{M3`f~fQ&PYNkKJ4gs~;l!195pLx}ya$9rhG{|$`Kbnl0h
zT_nG9q4{5B9cN3>(>K!Ir4&6-(Yg%-qQ*<7&H16pv)LN1leWK}>wzw&p_un~X|!I>
zeO{sVc~=MHI?iekif#~hXNyciY9?&S*p#1CIuzxn?E27&AR)O097#TWU1g5NZhx9tdP
z_qAoK5%g}R|Ib|XXcvWB9N|qdI+l`;@Idrm_~;uw2l`+29H!Uze=9be&iTFAP+`$7
zu9qii4A#`Yc)R9rnhxlp9ynb#DxvoqpodZz?kj$4X(r!U-Aeb|Hp_e1N~s8T_QtF|
z13(>Z<_pzEQ%6V3!Zftrd*+IqcbBKGBn6ElVEh5jIV<1gYxy$1EM-td6mmUuSisa7TmFB$Uk!Q3k`3
zL!*=n25&J&!~;QNn)jdi=E$|rhjBmvy>NDXR^M(S0hM(G1a>WUNCL7I2k#}z;ojKW
zYG2ojwJ|fbA7bk7=VhB8C!L^TWuBlihgjEf*B-z3=+a|)^mKE!s-XTOjVZ!zJ_p-W
z4!X9+*rjOCOpba_EiMXz3^N#E;+&KFzu7+@DfH5hy4uH0(phx2{b@cY8tD
zN97zd`;9wn(U~ZFodxAi@QA&F{D~$pJZ%#_YC~5lOc_1OyzXNHRh|<2JIbMr3U0!^
zYQh>V%TXueF+x3w-(w3HCwX695|ZXyXo@dwnUQpA>{e&Z(DBCQQ8dtG-=bF1%Ur;}
zM$)89vnM1!elB03ptz1em{!@f_64&_(5t^>U0WeD9=9*4D2Wpu(x=6>i#wj^rE3(6
z;AkN4se;2VqhYYgVVF79RbEDA-hE;Eg9khBE&pYcEoxC_pUz9+d-L}x9%#6pSR0EX
zvo$2uz669v+<=89Y@1Rj285tssFA1Al6Bs~y*e?IZE6S`U-M~mG7M3?HVj|9wx|4?
zJ@Zl@`B9HJskt#@gfwPfZ50-HSqF%V>*ZW$ZL`FBgaV@7h@FSi(zI2OXIC*y5j{#u
zXDV45+km{HDsMZr$+nO7n<{50;|5<=jH
z!6Y4Jv->E`V91bPbFFCmzHI3m8qfaL?&b59__%`Wd1tk0t?6maV;8kzEX{2^&H-j2
zNgSQ%r&!O+5N5s7WQ>XPHnRm&uIp;OQu!fn`&<7*j%xha{nnM4xSp1!
zsQ|)bn`addY+R1dgOZ6wShn8~Y4LfSUUV4O7u`j8N0|Xr>g>qV_!a4%T0e%EGReU-
znf>YarJ3OC^;e;?vwlkZr%@QC@$ju17s%c8fe*V=DH?ML++7#t;S5_D#A2BClJq`Q
zZ~SutCiZz7mLO!N5a
z_O~IbL3FsZwS-1L-JXIe3R9l-qsu>%*gYBuikLqc(k80)i6l!0GMc2ML
zKX94PM7k4QW1V7oKh9`g9PZ4;Ee*+X223R9&(srAMD}U99{EM;!CqxiWtU%GnA?UoAd=EMl5WcO3o)AjADe1I8H+#wXGI{`CkV}Q?m5jg}FT0~3
zL&uoJITZn2^~ABBbmk_XD}-%d!pr7EQelerOH%HU#ZrU>J&>X|3BzfczR!6<$BBpA
zM5KOd36fgta_IZ=6&BKSBfvh0@kad3v-0?S;I;7NwUy>V_7un^@+Zd
zi{tf`eN~NGZ=H6MfcC{J?p4=!4QJdeu6y|r2!)1aFhlgF-Y5z^~WZqp>Vztndb;a`{jtY6pDMIh8tM=-74Wz9_
zP-x}K7h7|2uQM;SLQs49v@HZyte}pRul57|fej2f6C$&2+8I3T^|!a0{BenH+U5xN
zk%|;(lJ!a6=`L!uuWO$+;boYa-~PsZyS)q6vjz|5O^E5v1C%Uq{tTl)O3cZ(2-Vli
zhbQ|?75pi7Yxx|(L!*td_xu}~?j+X65w<~{NFg2f}y4~)4$JgjGNDpC-
z5j;p+DEEr5;cnDhQ=rJpr<3Vj({ipThN;QLNr@E|)-V?%e`Yjn5i9~Ec>J*Qv>dWZ
zdMomm{_$6@^%;<@0%>7EYgQdwuZ2fCv!+@l@>}z3U+R^X5%7j3=EOu)b{4}F(4*Yx
zN^N_alRMS=+?lob@I%OZZS<9#qOQ>zA~nt1Ipc;;?>4pskOn}ah2V2R6kvqtaWa;C
z4^+N2kyBKHRT{vb--_c7*R1*Yc05b!g0gyju3$od&;v*PdoWUkjsz8OEqb
zoduRtl}gA|Wp^vh<_Giq)?TsbC0&&ehKpNoDh=;IT^#e3TvCWV^HsX3`Bx^gkwP(o
zoTB|VHPmY86p$IdSoobCuQ|ut@yqQo_$4^Xj7oaSb#U*a<;fGV71%jKR7OPBLkno*
zAIRTQcqPnDe~3*Wy47!9Z@MvT!tnw*>LWpX$O;7hP$yUHp2~KDQO%3sJA_&-jdg5y
z_JChyz$BZTH<^41AI*7Q0ntl7dX{sDR^-$`#W5wvV(;;Be&Y&G@YUy*+C~7ymfRNd
zd&owJvy1k1lsOOs8cynJQl3MmZG*ddg0k$qRcjEi;a**Zs+I6zW*0p+a%dFKE^?WN
z5z8m$tL6?!!>h7)9g5B_YI&lsAawQPRZ>A~uik#DF?*zn+rA10Obb#hX7ME=LQC!|
zC2EgtP65}`T$@;y@%{z9$3vqAqhALuW5~ie{dtVv$m6S6tMA|MeM5^yfIhCh6f#>$
z6r(p#S~}zR5@ofm*KEF!fVYJ1SyvW;`Uyfq2|m0AsXUlYD>v}|vNZG6ylWDtUS++N
z@9_k>i>&#l$akQ~>Gybq0u~C@S0y%^Nk~W{!>s7{H5zlp5KWp}#=Bl43QA|VTpLHZ
zty-iX^tHBU$n!#mM#pYx-OHQTJ?zorhQTGRbcnw6cw)_Bb{_cUnpP2N8&9%-$W}fA
zb5se&d+jnCj3hLu#K8{;egr|qE@oq*?~IAwoX=1{MzRMqZFk+qIOd7cM6d*0^V;0|
ziNP>v6i_0+ev#E`!N(zKUI*5kcHEO3q8rO5gJAYuesU9gtAt|)4x#Wh-DuT|YBtO%
zGC9a5Qp;>Gi^qb71=l5xB_^;f?ttjtyX@Fz_=Me_&GY{Kuzz&>50&%^h>T!Y%mwV(?aP@)
z?vrbj(0j6j^TJEAkZGT@n{f)?&nZ$bc%R}NFAWwl8w7Vs_DSQo?a^flL3|E;Wug4K
ztMDaZBHN%{O<$&P}nd_Vqr!Qc9y4O;b#4;M4sG;6^EkMOBh?TY+B1n26
zn%%mbRNN9m`fY+wDI_t#!0vnY$}_)xIW(ANG2+S)j}SQ8@;&V^0nCR3bcqWKku7;c
zqsNm&{zbr|-r7Xob^kbf&mA_Y_~I;;zmnD%NmdoOr
z8qI@*LqHM#cs{u7A!9JKtex#Gg%p$=t>zO?qg&1B+hx(1MxU}a*Ts|JAp&+i>$GDP{XXF#UFHe>j7Q6+
z8|F_{8U3N*(({cOBCI1vJgtcF~xl1-o1_lkrop
z!(Po&=M3mp#y0BgyHL9s(ntkgI?#7jenq5CEY}Du+8oL`-hj4GFxoDmqErWz(
zzu$U=;i9}-mZJbXjW-BqqL3jD^2k57BL=%dMyF~Z@@W{RFTa{r36VxrT>8d?tOeZ1
z!|v?4pqT?%=EoLA`H^mP+uW^7%V`ijBa5wDGDAaWViL9}{VsaPgYbB~!^{Cvr1HTU
zymh9XE)iy7v%4!detK(3^t&lV(b;klbbCRsqk7GY5~x}Yd3Y5B{316hRdg$IieYw9
zS78RV^Q=p@B}tcXaA!m607QE>xP3eZ6Y^MLi;4>Lc!TdHMVmi0znuBR?T&Gcd+NK)##>bNUcDrImX_Mgqa=~X)j#SoXVR}
z1NH-Ap*)=_mG8Fig62)Et#PXq+F48
z{!Z3Gt0QTc^W>jd8ZXGBw_aGqj+C2j1c&5nfz=+$6+ZWP2}a}*y5SKCOklVP(&O`#
zTJ4Z2>i}3iEeg(~*1C#p1xUdFq@SQ6rmz(Vg&UMDgrq7smB-OfnoT##w$UyUdUiv5
z{7pBEVd#`dO7t3^ynb#k5!#{F;I#-2bE^bCQj5D6u6N9J11vdh;5I4^Rbk9<5V8#A
zu@&E$4qJHBLi8%M9t$6G#DmCYoXhwn+26M;K$#1(1%}alP#*DXU1pU37a1G%v9JKr
z3{&$h8bWNr^gn#_N*u}xP%XU);W^O662iZ)-euXA3?SFmXBshE;PF);xOvWXiqPi?
znGY7NNWdW|nr9@#ks?N{#`Nx5JMaN`G~=L5*b0TZosv=~e%=Zv2#%fLhzYQk{^pjE
zfWJ}oovI|L9zyAt!n*ZjqKu%r3_rca++O&{m3emSBl5ixa-}g_2i1G--k!NgMYnVe
zhK=WZoQ985gdGb!5ExGon%DZ^K?K}CsZvvYwy&-VqXj{ggW}!BT;k@KM_@fn{o$Gk
z%wn-#$OF%e0L9H|;i=o-N9T|F!C=Vvxr~(6n+KOe^j3;&%UDI|{^F6T$i8FnV0P+bY>Cwr_j0oi6cP%`429D
zS91EMkr$jBt%^eyD+;TqdQV>;tu~ifKf3f8h)^R!Ad6M1I1W0P1%S$zJte4(!(@|?
zXtsWPmksprLA6DMabsK=nj1a98NDgiK!Zjx7_1RAxE-)YTS+@hzGJi|D~2#YBfzi(
zSb8K8VCi`^uf@07z>o+q6JhEM5RDD$0=6MzdNig$=#jyoL>nYTntZtI+n0r$PD6=%
zUlrBmFrHodibYhjO%!n2ud@+;_U(`h>1nmi@lp$!dIPtfxF4(>h^5<WZ&tKW
zPCzC(k?RhIP>K=`=Ihvk4B#XT#7w7`Lxx86g_JPzqGq832xy?X6Y1+)j~8x&8Q_65
zhy+a8?U$EjX64xJWv6XIZCfT_T0_~pKlY2?BOeJZ_yE9qAGza&Q#{x@?T><;N662e
zhtRGUCH=aGxG;;^h*YyjM0OD!l;Yun9efT9rTm^KrmHLzheA>E>+vmFeYy-@6GgJmQup
zQ3@pah|2reF#7wbWXyp4j6mN&1wyQEB8g`ZW;ce#4pvJ`F0t{VHtGIGEzIS?x
zTI3UP_lA%CPUl|p3!?>T43F}|*1G!t;C$(IDsOOc4DEl$#bBrV-{ImWx&(00EiQ*?
zB2$(}+E2%;WY-h-f}P_yI^->B!x*0?m{LQ4b@y+u?#pJeS9}?l_YD-yhf2$4B!@;P
z6%>M(!QwB>WmG$K{cJ@N2wZ@?>XIG43i9QN^Gr-TZL79~%luOXo3qj(}a?dKDaY;|Z;Qc|x%VP){iK@!(F<
zzo9Ld|B<%n2b)guJn-I_f*bRfJKV`xk~%@Ur)W@=Vs_d0e+`8l`FArsgm;BvH;LI
zsk-LbbWqTacLGks!MUWhgijdH{IUmtdbKt?A@
z9I~Qsfhkj?Ykynn98c<>cy$Wy7uLjJNXSd|xdCdP5KLKdt`kp@9D0%;^x7bfg>(fE
z*7OkO6m@ul-7nSGo87M}yX$WJ6*8dWp>S@Azm3fyZ5Y{b7pJ?G*R)5nJ?7au;R7?L
zml>~5Veh-Z<5h7v+S_7?v)F9Tj`f(t-LUYg&QN!3JGlF2-ojA9eFqEh7Emt+ULI3o
zB_e4D!>$mb>CYhg9ezdu%5Uf@A}+i43oZn=t7+;S<^gZ)vkFDwx(11O5Is~umb~CJ
zQ*#}(8*Uv5JwI&kk$yE-Y+CN4r^ieWmN^vljKbL2o7+$GPLW}XPZ93C`;9&SN48?G
z{U+8j2v~vddR${+RP(z)ISBmw>wl0Hx-WktD~Kk3UM`!dvJ1C&OMba$q1_s`y2Ki|EW{Hi36*p2(TXzHZ&qs5vtZIQ
z+QKp)P}^^ZM$KmMPq^b3h~v>~i_&0o6`i_6kukrsj6L9fWCn{AsW;9ri}RVlWr+)w
z%V@s{5SMPio6LPMfX!9Cm-0bWT23chwHi4a(2UMKw}vJFyzEUY`trk_;O;Pq)*RnG
zD19*zEPTrQi@u;%ccWC&vy~ltck&>iX8-^-eSm&>>Tl4mnE7B#!J-EgA{%I~10VJ;
zAaYq|vxhM3eRWZ#M5aGuWRJNdx5rR3lb3n%8^b(&J2Qot&j5IRZ^)g^Wm9tk5)kVQ
zuQwtM(+Rgztmdf(60-LUH_7tZ9)q+Iq31|{0GO;V?uL!kN?d}AuU@C9wygGG5j=GiUfKp7PnMSj;3mA4+E
zfY=BcA7@HOdhkEs=~qYb9lMe#H;TUVrh=~1mc)Y%*}np8E8fke`ZULPWyQrqoM34z
z(S=KXPkdgNyz08YS6@w4V!>p&oo|V#npSOtoR=0+q8y8$OB3`k+7z`@{&Vt6DHj|)
z?2Pn5MB4ZZgTRlLS_EWOEkX>ox}Tin(IVoSZx_ue(QkCQR#G*VyN>7{xm=Qe8U)No
znT9=!X7J_w>Z#dEjtb9mXPRH3Y0Fuq+Gl}m2nrvn^)YRh+UBh48?*X)cZ{4N)5XOy
z&OT4R%hR}~>L8FlTiR_o@8aadh033QNsFts;4V+Dw-?0w>OeM*AeH{%LdRX!5A-Zv
zlq8>KaCbZ)vLd@a?;7UIW=6_nUcTiB=s`2GeU8KEQBzaxSf4;Vt$k6>S6#zHf9-02
zv=J3J7=#+vc`TgBEytuK@Lk9N3turdT-f04f@kMAmGG2$T$SSmD80=p42ck~ik`FD
zuV||FuwKci#^hA)y5^qLAhp27mEhds-k$JS-T!#FHQh9FTu8|z)mcgq!&)l#trJ7@
zq_WoCU(bW5dS|E+w@hs;@#6BJ>!eirP5!n8<2J_D-IFDL2mFh*<@voea8{{67Ik{7
zyd1ecrcR?MEWQLk;xg4Ec9_UgS;X)CPWZwua@{xwX%*bliD*K-eM#<@hkFNWdt3d9
zZ?9yzunwJWb!2)tok=};;TvtW`vg&x^<8Qk0mWBLcxKV_d-1)A;df{btv?DCYZP+x
z(GWE7)zy8eu5!PgewCY?DA;(XN}Qut%vVAT@##ZW(!1{)6<&;7;U|{L&Z+Vo^YfAR
zn`$;a{Me8=dAuXbh5=z_N=0~fqSbn*E*8sb(+LCriuX2_VZ1QSTl*~o$6HI`68(D*
zMm4q!YHDn|h9*>oGLoNZB_*4XU5v0IUFQXReJ&@GiY0zY9lJ#O?rOqG*{4lNT>phw
zh;;OVerSiYFw>Wns+IWZ7DZw`W
zyuwYz(bd{%C7;gn+WDj`S=Y_M{b*0SegKk9@nBy9jy2pFjg{b%8Ro@Uz#6?x;sh^?
zfVXy|@O_;Vh0^y^(;d4k^VaSh^AQyKB$7hQ@?o%~3OGbNSsPvTU$0%hxF<0pwqx*J
zAp2@!3-DfS?o4ZmY^+friQ6RTJU1LFOyDy6L
zl=i&4Gp={@nXE5qw5Cat=oVW4TTB|}gDkoJiR~nsvAlB|9=yp2%$n^|StOr<=^2CW
zw#Rdh*HQY#yy~}BnntFztX^+Qv)b^5zahe+U==rP@Gb3&P@Q2pf)$o(l7HVp5jBOM
z#=JXG@8E8Bb#X;HdCh;)RDydY*tMT?T<_M8dDpV#^qJi?ZO{+Tn!AaZgssk{Fr)=;
z7=6X=;xfxmkPO)0>H1Gc?5}tn9|vMKN?x=iUnf>&y4g3zM^WhCmJ~9S3)2xuh4twa
zDA_Z(JR-FJW{dR#Z?R$qrlQD~+M2U)FLlOeVSAoBGis*{?U5^gg_V;yW&`uYhDz+x
zz?Np0&C|y`9g8m3yUx2C_^&Fojn6k_tX>OrJd{eIpkxit)r;(akr)=JQp=k_^OcxG
zGBApi76=h4pBAqvKtP?^tuF9I!;a);`G~K0n&QX1|NI;+`>@)dkLuHFLnZPkQvZ^x
z1#zF8h_*1cyIbnq&nM%GSAw+8HEiosn(l1b=~sV>X1YW@aOJb*3F^S~Ua6MNIgll}
zI>ibRIni1MD@D?36FY!|?5laaT-`x3A+0!DT1j{%uB76zi6)=M)ycxg{cq`Eb>BP4
zU76BuYj;ss9=#1_UD9Tec*cL9=wF%Fw8YY?jo$(Ec7qq
zFa{XkP%`m^SO*ZPZ9QYTT3{mIa|peMFKwkk4DZf`#f;__3QEw0>3B|<(haM&^!txk
zfBvZ5c9x{@F3x*Zc!8J|PnUA1cR@JsP2d-~t->JO_`(t3VM*{?wQPEr;oYUMokS^0
zGP^Jx-2^-DS&@um6wt`P&EOR||LhgC&{vcoy5|4!VkeAABuL}K$FDs3kTi5Atca;W
z!$BJaezt+66I|xm>=8l#8T1Fj{d<2pq5b*Q0v1nwL-doh|Ih*_3_cj>yUZHMf4hXf
zmIQ`Q=V!MtJ!1;N(B6#8qU6cVLq)*Q{q0qs(B+n4@@xWODL}J-d#5Tq3EdyT4@KD{GqN8#5b{q0SL=#Hs>j1`#Kn-ToWNPtJdLf^zb`^*W$6*1RW
z6xhH&yMq3jO1802!muCac&F5{@5kdm&Hg_=__u!N!gi*?Cx8ES1DG1ymz4BBC+Tlj
zC5Y5vn64NO$-S41b{_seT|Ja|-))o9|eR%s$#sIrlL
z%E;aey@+~rK&AUaKm}dxvn2Mg!fueb$LR?6ae4H<5lTR4c#kKgHCJuDy@TY6o0}L`raS(>|&Qp(Yu^BKN4J^uVj_vY|>C4|`wn
zaf#}F#QIP=J0Ref<$4D-1U$kGMV?!FU%*eyco;4OPTIBy?(T=ul>MiEVSbK|Y(4DI
zU&6g2`NlRvPxet2^=yBZ4_i(yiD5L56Fm^RA`s*puTKzxvubxAUulf&x&S<9@ng
zsa5Crh0opN@~9ve;;tlPvp1gM$&{Q+`$hljmn4bU9Mm9vZrjg#nS~O=Bzf$2Xh80|
z-^v&be6$ICj-6RoPO(gwmp
zb8ecXllv|hjXW=Q&dqDiW?QyvYVN4lZ?$D;TO*_rb#W%f!^zF*kd*4W%WsR0s-)&M
zYyQ}9&lJ_OLpsv!>w}pq^}{E)yO-M2*8|?tDK0;51$r+a-&<?|(X-No(Lf%BB4+T?iceCcSf4ODa_pU}8C
zZEw=NU%Z}|ecVgN>5_QS)z&xMI7Sp{-)g1Gc|{czpHP3XT^&R!>2NZ!UR~i~m&$at
zk|VCoP(X6MPSxcj$guTXxn}yauEVl=Cu9ylg
zk=e4`4%e)C+!&KDO-`-mG{Vci)N^Uq+Uj|n|F{^kaj>DrqY
zvz#FpN2)&a#v?lNY(f~^Vaj1
zI}$q!ZLzxE2zj1lM9RU6}o+=xFaJ=E~>*5FP(QQn%2!Y
z>-rwK`5z^o2ax7lx?3oeEfObxo{E0Hxx8~^by^Ym$&U!q+dn;Bd)!n=#9(i3wNM|t
zTI6n#U;Kz+(h-g=mN3A8eP>Ij1B|8F>Ic-Wtk*pB4pJjq+|v^INBf6TFW#dZe`5=|
zg_P+SN%$NglDCs4sWe{Mm{OWNV?beUk=o=#3F@-}39IfqQUek*MR;4upCUT;(ZW7_
z@{8&ne58IHr}AMr;f2Aoc^+A)_1_PL4wY+%Sbu3NDD5xr5R=NJ`u6$*&h3f*(nHxV
zCLbo+Y+cN4K0r7sC-YTDXK78wO~ZPSSDN3XYYHqy(M0AAl+q`0j7@9ujwNLBlP;S)
zxF54$>f(yMsWtv|e<6T^VcIWn!gz^VP$Qvx#c=!T@hiu;MS9DEA5`!>SvFmrjn<5pq9}AEMrhYV@1-6&nqP%_<-09PL!@Y$g|i^
z?2)W&%4!1ro$@99_2j|?`b-gvZTd$Bdm(+1`OR$4rg+sU4c2QP$6fdrLU8@@C#Y{@LOl)0F>2?TB>~14Zn-Jt41o
z^1x>Yv8j_@jLqq+u8n!aN}3Yek`k%HQio&voA!6(9pEn3oyvQ4krk
zgAU0&7k&~LlAW6&+4(snb3cb0MldbV?xOLN8Bj9b%JrJ!uIvgXUh*i;x==9i^cj%w9>
zEv*A}$(L?J1<7@;GRJ1;pQm4S@6dKQGL_*iuvQP~cJ*R@Io&Uo-I?^s6Y#NJ)tF@C
z%&@hfg{a27`xG(DWuDf!TUAZqIP*Hc2u%O0!HE9V!YQi6uHyq+k>kDEYR+VfA7+?E
zZh^}t6kIQ*ZQzH24N!i7`iR^ZzL02{5&@Z{<&DNYw!1`+efQY<9q9efS4{Nx_?ps|
zO_F6+Os2GToj%y2#AZg!I>HG%5v=kK-x?Q`C69s{dlE4AJz(rANwKU6VJCOgr3Us|
zpLP#eXoQ4Le6ler=8zAv$$1{)zV!^-{ip&`?|!wn%A=%*pV$>;@kFK#fkvSV@`
zd1K55hU;=q$V{HJ6|(xIJSU~Og$%?g>Rln|rTa(UkON{m_q6-VQI*Bl!1UU-1(4&J
z?5z7_>fEop2(^P=pol@gmfoXtI=8cRY{__V_Py`hB3SK{l8jtNn)~tRg%OkTl~MMO
z9Vnf^R8NLQ)o@oAf;-yKJ}!c%2hCk|5WeT@+sW#fFdFE9uJ*m<1aC^IvZ$o-MlU(|n(j
z^yjE5s)|0mbVWnM?u!Go-
z*CcFst7HMVpej--6I**7=(F%eBnek}ahfipI9Q#M=H#Qw`!b`-x0s63d$+?|e`!*BY=_wC|gTW;LaFXV
zPe#<~NvB*!@v=HO!%0&)coi~Ksb8ljPhNT)7ICta5Gtm8DWNP7zGQNah_6;9IPS5W
zJUNxNI6cTuPA@X=m6k~&eOsXuH?m%H>NdS1@T6~+#J8@3fj
z|Gv(az)nS$kr$Hooo9WU?<=oVxK`ZMI|w8Rs5IzMD^j0cvHDpZ9^Xqlo`cyMjvM*4UMj*V%usA1BXw1w5#YCLxb%jswGLzBhrfTP~r`P*h(;s%nxXKOqh
z{m%Bx=PBVPO=O-sYQ}+%ZF-_4Kw)-QrX|V-UqT9Z9dW>HcazjVp96
zrPxaAGCzR}d?$k{a_xBuQAdXfd(af&9ajsjT1DT3{+zWa`C^ai5B;b5Lp^@{<@1uJ
zE#60Bt*25<(Hmh=p6!U0DBSvXyNeuQY8A35rl%CjNQK$
zkqT%COP0pO_+A&d|J3N>;3hokV8D>$hT@aN^hM6S3_anhd__x=Xq)?HIhv1XTGjgf
z7;jzl&sIb7?R^jBgxp4%ppL8oNXor90ez)rkBXP%^z0cKoa5r*uNBBnBe}^xKcfDD
z4k4h6v3{R-V32n>EP=`*u`3a>ZOE^D5I^l2T(zw3YQ1Q~NP4(e|4siFopa
z`k=AHLU>x|Y|Mslk+C1&jQ}e^YfOUR38vc^&F-S@-yfjE0?UkxzGqqWRjbdxpPDT#
znzW0)r*YXf9yFWCfGrBKCwdH~yg~aFi~r*xkb%I!3@HQi>Bz(WwM}-Hg%-XxRfnH+
zU$aQx1Y)j-40As>Q%d;8)p;lb9?Gyb&`gPCWH{%dg-`SGddT+jTFZys%uyAiwU#eT
zx)bLou5D_s`X5TErx^&h`CiCx$?4&6w*
z1Zg-;&PEX5*JhnFz9ZhYEfnsl4LuiAOkj*=BE!*zY$*L=E4Qha)%HkX;d*v45uw6HO~Zz67+($Ggy
z9@ZY{=1q#(oct3uySQ`+^EO*(b9=qG%4>3y833C)1HY6xeVH-1W8!oaReH$hdqXNU
zW#=a}O^1kbGS6SW!1tAMU%gTzb*8^NE~OY+sB_rLPH>MT$NrU9d3K?o`muHF{6o&^
zxs;2SvC6iE8-AChEaChJK;u=RB@sh~@p*
z8QUpVZPw$kJyZiN#w$K)TbcQo4KcDQ
z`@TZ2=#b$QSp9aOu%s#eJ8NRd)LhdS+t8(ggQtb-4xBJxHnPdQ^F;&fC#&
zKHYV;4UJNZBCwZ?9DVp@8r@vHwQ0~(Do!J~LWuP-9@EPK3ve!0G3!6EQ+g*{^bqdC?U
z9+Y34@qhyprvrU^()?!I&54vI+J=9R;g1>D-TguRO39X+^LSFPvAf#8J~Q1(NA81p
zesdR>r|{iA>z{!aVl02`lcK*lEPd=iZ&B!Z`z`T?1$kswBI-!5e~$E8M_bz5C2#vC
zUS31sRZ^P$XJ>Ljo_W{htQ>2^JH`A_rttNi@r56&kXQbvD6WOGmrpOQX~n|+-r^s2
z%a&vzw0@f)fX^Ip@uOePfJ!LqEG5EOR6OfJznticRA>a-riEO`*hH+VTn9awMeAjA
zoa%dkTCJ)HvqQ_Jl)>Lz58K99G#)^fg*^Wx@vaQsJvcTY;K&It|4Y#z1uw2_dvD5-Y~J`-^wf14cGVV))T)_~&C`b~dd9vdr}C_bAAu
zF_4h)vS~OS|3QP>Q4>Q;J;t+Ke1Ab%t9M2?+qpd*@uuH$$>_%>G=7L$XU1!2d|K~4
zS)m#ir@&H0CGe=7K~5=FEYdkOvt<1<4PpITlYy5^lZ?s)i77g90JOusN}3hdH-|Xd
zajsiJ#WY&~fJS{19wf`x>2u;qdxD;87=2aTSN)VsGfu_Z`##^6)|_&QB9tlgej$y8
z%f!zabBRv)@y{6ziR1@9suEKi0)m}eRo)rsxipl-h0}zM&6<~K&*Io1SQ_dQov@;n
z#&)0ggR?82^y3Qkqt3SuYKN62Zmydj+8z`smz4C)yk;u>W#-*}nv%Ege(bOhH@qT#8(lW|u!=4ZOGR5DhlxK*lpG@}*XH0xfPlx=_JEF@z3+9R
z00FZ^G@C){Tzov6$UVj~{lK&Mc)rx0hOB6=!4G%H8=)y-cNiJ-%k!e;AeJwk1qetK
zv11U{OeX5MF$gOw@9aJ+t8xZeMlQxQ(iA>{YAr3vz=U{SshjYRk=K5R%fk8Xc~Yls
z;*Ypl{+{Psh4WoUhhck-pE}<|Q-QD+>h?fb`j++yAS``)N@^i##<})UZLIPTb9Y$C
z{*lw`^jbJf>4KZ6(4m0gs=346{Uqee2sYPq8QG3n;HOG)I}}0~-PJZ^
zc;NscI)KnS6hilal8_`JheRlg2hY6CUw1@!`b7dwyYI<5JZe4-H;X#8k4c@_aiHI!
zu9xYjp2xMDTgAX22P1A8AP`UEx0#s+c~5{j|K)aw2h8~w0#0u-jPtAI3D*mHHe8ME
zvb7bdZnHl5b?(cb&1K%H-@>1(b55g6i;>TAmb0yVAKbAXI=qm7K9?f&2&Ns%z|NzU
z@Ubzy0npJS&p;PIM~^%|G(cfd1`iRfwJw;;VwNF1Y@so(oK8VWgh22!+^4RuS
znw=)a<3arkJ)WI%&m+EsUwgLi|6$~j`UHD-qFpVk7H@{}HE!RUXQ0lf^r8h?LCV9M
zp))-HZg%yx}rzh#xz9~oj7@4b7_nct%7$Y2du
zo>R7eisH&U|8V8sD6W+Md!VXedf(|rPw>|YJPNn6Kt&hlFlCzHk$XrsR!nKN&WXVY
zJ|*Tn@e3JE$@a6ccuAIgI%NXcgv1~~1WJ3nXn+Wm*7Ki}%Sp3)8QC(UouuK^{*vkr
z?bK+qG(65YRmBgwqG=J~W*mgJOmZfFGRVRb(~yPeML8kn+noa|U2JW-_c0R&}V1X`e{jLR~zV{KGo
zxxM-`dEyS~s!`M>YV+~Gx`gkp@X|Ui(U>i@__DUEMhz4^g?{EYEf=Pq@z(uXU~|v1
zhJh6ieiT6k=iGGArUMTqDEbaOSm^rAU3?zfFdH+viIl?Or`)^N|~Qg0hgif~-T&U5I`o^2trq
zgO_Ae5xWTGkBD-v(e_(s+3iQ(H_Nb27$hqx<1@McRN3#XM;CslSf4mIowc)oT}q1j
z-v@TNadU|U?9$dOE2#=^!nV*u?{a59@ZoZ?%y?hj`=z~);yYFW6R*k6Zcpg$VmHzx
z8sw5%wYw$1u+IA+gUuWf(Ssob__ykm)E@9}6@kp|)wGlT=-g)gHtuq}|B=F>R{@mP
z`@xgjxUTy4tILB`?`3r-W;yjS7Gi2;pBAkz#}LI)V4X`S>m2QPnS90*xd-2tN-`am
zA8WndPCE;m-V5o|hl#OoY9`PPLBtHGdj8^ZSbob39VwKkOPy&u4(&d8wDG
zrtbELlLu*X9G02{T~FU~y2>wU<64LNU(treIkg1}FDkRruWrVQ6IGBdwO&ih^i;nR
z@vredU#tDX!3rfYe{2muD(vD+1Ak37OJ2U--!Q+~`*Xe0?*G^++t`GS72^4IuH39k
zWpwt=;!9!wfJJ-ZKY3ECSexv_>{+)@+{2FrRUjCEk-6YZbin`fuT-7_|Ifct{-*E2
zB6GJbf!nBc)u3_>@0IqQoV+kfG?f&0B07-dVsB3_`xDVc+qe`G|FYj$3X?J)!L^e+
zx!JFT_cq^d$FmS;3%ZsU-E7`o9W0hk2Z}xkxLiD`Va084y}3LX-*%$8UGbrKl73gN
zLo09k<}k1FGT3eM@zVMVtT5_wSrYS$5+eLA*TVx*w1$c%y|1X)(j@vs3c9D!9Sg1P()38h+;H&LfCg_CXJ@5C}y@#d0q5{oa
z^`J0$LJ-Iyt8)G4@^sQYDy*cvu;P+)#LO7M-IkK8t9)4Q*XGyla=ANj@N?;j?7`&I
z+nnE{
z78cho<|mFQabRg>i*m<6Cy|K)cO{Db@v-}&h(19p4B
z*M!iTcI%La^rnsU$@<7WZV$QqfzGAli}v4JkjYYcO#w(t)P3et{DF;>G#M;ILw#J!
zYVBUQ!rZJq$T#hN^eY3k$COfPWsD{!0oBKxB_~;zj8z}v_#b=+d15OOm#L*gZT>Ix
zg{Tv@z1T7n;A6Mx)vkw`iAgGuyN{VUNuzR~@AGhyqU1_qmJp!h+=sTB7o%;cO;(g$
z=PAJ^>e3BBs>T>k5Cu{-Mi5sa
zS3sVczGzC$17hn=+rS?X2yu1jD2v&I_Z_7cu74WuH!^PMy7Bkr=P6RLs8qUl(_`Y$
zXD^LNSt!$UHyB9cI+o0-I^lvl{@oU{TtxU`9$67gsZ^P*
zP<@%_pDu=*wv4FSt{c|+zmH5;1~!3F`oSq;8~3o=TWKR#RRdp}7{u0lqPob~`s=0y
z1pTn*M#MDC_a2q}sU1)zwukQ6E|@fQm3Q_fjELQH#`h!8fUX+^UOU6@)sbpR-YP;A6SqT!Ee}#YM0$LtXCbz>O3(&CM*M)t10dtiQb1}a9zU+_
z5*t#PkSz6btU50!9x~{Oq)gU-Dbt!(f|a?)Jw<83NkXX1#|UI_zs!s
zV1G4&J9){^D4&}(uwpkdG2JBDbfMJA7i2P
zkS!%BlMP=XBRCvu$y^Z}j*C+Wj@%#No8d>I2YD}XP*14-ByPl9mf`(*gx9a;_1aaot9-o3F}YnQ38%ac;fZd_U?+r>9!cn*z(5#d{Dl8H#cP17z90F#-n2x;IuR
zJH0{8UK)D*GWYprd@KoQu+*X&EF_@8vYVy*F!C&qL=O0OA)18?(GH@H&P2Uy3Gy(R
zR88(-a=C@ai=37Rct9LH73P+UkB4*t9L#x-nts~Of
zG8>9Xm>muDF-r8HBe%}Rv30K1xrMWk5_y0kYat2PeP_X(8|=QbV8~7KyTu6lq8(Bf
zoM^br_lCV@K&c>2v}nwJHc+2#0hqfg<2-RxEk9A*KnIEr}FQ9o1#j^VuUqq-C0
z0|OE-ahMCCdy7D&uHge}{oO7bg^TO`w(HZ2TB(D@zIrD|@VNoR>Nc)Zfq2Xyc~a|8
zbczRrp2Qn!p<)j_$VRk~89W%*vbhR)Fs@}o6_T}Bgd5a`DDg)V{uO^T0VTdY
zf)9CA786`ZiQ4@MGCW3%Ro^_`Qf<1qNK&PJLrD;vs$(U?&tteO1QLQb>7(dN@qOln&vmvv>y
zDH^;GjWyp1@(ILW%{63t1b%p65Of2mBfUQvB%1~cAUkC&!#?O72d}OutvOyjV_*o8
zX9>+sEHZ;yjs|XXZH_-9zwm>AA3ZA8zx#zvo+ZNvKc(9xx<0FaWB$`biia*k0jae?
zf)8M8!ylVSwvIZRjsk2Q1)42FwM;2Sd$+@8fB7p8v$IYz{98$=EXjaCZrzO00S4Kl0AMB~e-B*TQ$xwyc1iK0;?N^$q45a>>BY7A6Z17)Q^*?@cJ>M@
z)dsjIftn*&I>QyzuC+RK#XXZ-JWgJ;-rLC23~Le**U?jG+$Dmo}O+uOKP9m_a5JT
z^rKYwnxT$ZnSf06HCj|I-(F?;FIS2e+Qyp#8cBMU0}>)5H2v7sv}V*>2)D3yzXosL
z4{Vp>lH%b%FVF2ShPkCi>L~_u5gOKw@T0(sqqHWpYrfq(Df2NZXmXfqUF%{D
zYje6vXsif5=Kkopfc0D^{vUcAg^Xd(T_*VE%{w~aJA8wj4b@$&MZeUy%ZSorSunCQ
zJbkmUj=VqBv9FxA?s%P?D8ejA$77#dT#NpF!IeV2{ki++tHTT24WT+)P*bt`k0v?^
ztd-DM*!(ua@hCi0h8^4fUazqe>Na^N%$`)&UV9*`(bnEF-Le#qmpNF|ptQHOk
zM?|&y>*7ZFc^#dWr!%qB$LfRYeryS^37(e<_fsh)V&=3LtY)cTdskF$e-zkX%o?D8
zsICc>Ix{$JnX0dGGe>kNMYQz5iaHvazZ-+1vbW_s=av-Pq55{wcVq6E=SdU8D+X=x
z6K1O^1l`w|pnMgv
zNE}pwvc=2$OPn;CE8|0tgwiPF1weaY}JFlNZF|
z-Sb0R`qnuP31;uZ#8NA)G;1ZTPDnD{S2>)g%Vg}uHqEuiL05rFR1I{yLRW86aX{ww
z!fc!vPBY;Sx(ca|hCUKU9RUK=TfOx*3y#;O-G>*qqOXn5*AG^
zr!0q^d>l3vHe>(AFyvYASUc({5m)3<*nOy@aQa#(xKgEx?rUrpQ9$XNi#oC#7?=E%
zqW0c@jD3Z{JjfICfobO9BSYZ4g{}hBF;=sj$B{+fEFPTqZw$_+GP~&AeJ8|5lo%j@
z1=&RQ>)?5`prow3Qjr39)mE_i&d}ewVuM-F+P^&jvU;@RzS9mkv*2Mf{sxqbe6K>Tvqn>Ah6fQ*_
z60?<_h?{jM=H{HeyU=#3HQq|=4cg-Mymloa@ECt!6I6h@&8|vC0d<>s3+W5`Y7S*g
z85WCDt4ggFv``N(7?0#LY(|$&B^@SiGN%p?*b~baO6V|ACr&oG-rd+jbUx8_(spx&
zL-tKtDK;Y@Psr2qx5$1VqpuxphxDP7jUc?EtiTaBLjpd{;ch%)dj)J!F1_i@r
z#QarK_0@csaD652zSP2k`le)`9ZlX$;xJn)I-2v)IPsgvyHxbgCq8{)RanY8_@
zB(u~M_l-yK+sb>e#NVxpBh85;wh4ar0Bzw
z9O+)Zko=8=Cbi3$iPs>jc%)w60V}fj+U^)UIBStS{kky4S^7W{l|c
zr$BD9Gt!sNqA@N~@1}mpyk_Z>$)4nBdpa(wDYi*bN;;y&A`j^jkG+hSQNK(fas^^2
zs(%M!tTeQL0Aj3sByrUbaeY-+r==LOP<i-1^03y3gI$e%xS)oCMD@R823;+I>C=pG>Gx*=e~HR^EE?rof@s7X;_Tf
zjewH2Mc_ciHj6g{*kInaI6P492lR3Z4M~PZA0q8{AhwM!rz7(o|*-!P^tG31|m*UTa?0dn?sxee@Fa6i0w;7hvbD$JdG$NFgk1s<3O586Ei
z8B*Zc^jnZ21$s`swO+=myaRu3t^IdSo+4=c#kmWD#@}aD<4+JY{_Jqa-oi+W?`S1_
z`;PqI5SKt~P@a*UjlUhj8gIK_rprL_Q}xRiq31Q2#dq=pA=n_-b6yh!2^2-_l>_KA
zQpb8@8?ZeP`ejEw`L=ZQy@!GE-^!bYFC$7g#Yav>=N&h8-Le8Sb~dHGJj9n=o;gkW
zfA+PEDogC^*w)W@6tzFV#u!2kCWZ-wZ-B3A@A2*cU)A2@*bz8uUrKtB0&xK(;X=gK
zI))EO;=KrxB=7-AFiR>e0Fr1xk_77>iX?iFB%vB99-}oe)5xEZ0}Fh
z#zw81U-Urg@&TPE*nW!RBUT=x1*Ma;ZUZMCa
z$S>l*Hrs>zBDS{0Uc42vbI82`q@pEiB)24!r=H#o3-j!@zVQZd=dk)pvw?yA>G7Vv
zwCM5O&n^PvU$FN@-h4eC%oK+exODYb<}>jRv0c;wV;XvsVjeX(Yj^snpI7wT$0+Ec
zEClxvW^%>v@4R4+Mve?h-+93tjfSZm1f>9EP)amM1*OA>ASm_1Qyir`LP{@nn-yvc
zHhhy5Mrb6`%pULtHh8n^`zDqs8OfC}fXer;!bp%J{xxGx3{u3uzL(~V4-)z5x*OT%
zN4isi>8E5`(rDSfjRlip3baN%Qp88ldX;+bX4`@}M~=8ZzFuWh%wMl(dxg47-63)0
z_WZIdjZ}(iE%BuGamIS<$1qUV8v`mZMCHDqte?XKWxa#Cad~e{bXDm;lZy4rQ&w!J
zmAu8n?7f5J+#pDNNCJ%$5tsiMz9FzZRDi-a!OjJYKx_JD4EJJ5=w!UhAKBiQHmAPgD7z>VyiC3Hb=Bl$|DrkO%afaZHYbnF
zyCg2>c1`S?-1SczTe80SoU8}`*xj68v=IAb7Le4Xvb@kDj(4W7x;w*0<9nFH^v*wD
zNo)*_MA4$sQLgH2f&_T6ROK8&AfzrN;hvfLYmkw)T$OS+r1zxh87nr%N6(3sS8E#&
ziYwq0L3Ecqd6X4VgB%4?B<>`O-nfrN(YkS_G(
zx9?ZhN-)3kmGWk;S5Q?npVT2z!E(6tNHEHxUVCSpYj$~_8c=G%i{UyD{H^FW`?Lyw{<)hd*Yw@`T>v*bRR
zVBxA`E6VbMcs{iaQzOoHgS|Qa>DQ73{D$O5a?&vWmWx+L^je48-_7T|^aDUCMX|@-
zKJaW6o|2xZGQbNx&TL})y`s=TuVHGitOFL1oCO?iFKUdZG!iUc4&n+2j%QE#4QRCH
zZk$$D;x1p`-0rJ;*%7dpfM9LpS+$w;uUkLjrX%D%uh!hvD2jZRLyvX%vqz8
zmUH4+&XOPf-n;Y__}vUuI}GC43aM9fJrRJZDr_jw&89wNj_5a0BXHUVvy00J0$atK
zvEF7FmO@RUx08z=3m5P38k>oB`e)>rOk#meWNjA2N^=@d-pBWI4HvE=9>v5YIX(Y0
zV~}gPZ=5EWLFB>)i6&C-2H8w}b$fX5;AXt589wVx0s{^+MoW4)$OpX6NL`#oqlCF(
zvD#SV_@1C)3)^yqH{#qF$t@JpT-Uv?iL9={xe?QIqb&^w&bHR_pr#i$=
z*iirVHOZ49RZ?Aiwk_at=b-qNPM`wyUvIqVvX&P%dAG`Y%`CUndYMoOb0;cc*6~6m
z%sL|FOY7|Q1Nl(&=)BfJ&F(4$@1lvaXht&Bk!=%L*%&kRW+<}j0b0vhUO)(!!u&Kz
zrDRiUTBqfQ+q_cBW5>JO`eE~FUE7}Er?zNuoR${bZvL$Foz;)Ktt|Gnx7_?(zNL#{
zkS7Oq!COLWK)6^tyaT^neX!E?p%LwQY#@=~WgP&C#1cZD++-N07FF%aJk4S~HdOtj
ze2mCi>WHW2LRZL1z=73}NBn@1
z{VK!Ct=!0yhb4*N213xKu}jb|n2BZ?wlggK?OI<-=+)
z4x5WQ+1lp`dc~ib-`Y;cnWiidRHjwM_`RUOE$9_H@Fe9A+@SjpT|}FOx%%X#>wZwX
zaYg>+SN^?O(3V+3{Q*$J2Y()mWb^KOvvx^e>8=`2Glu%CiUfC9tWzV)TFzg|f9;-?
z`(Qfd^%0$6b8t0$W{Xg!UWtOE>^+A*NA%3KR1A-LFvy(xmF&KN%&EVj`98>;)O$08
z3@%*1Iq->oOnw--sQ4fKzvTN@|1bG~{+G;ylbnpmv8Re=#-ES5YX<`bXp3M21t<*M
zP+;*CDh_xHeLPpO=Yul+aizc_QCwLx5AJ|-E!Ez?VyNg)2c7U4s@Hv0UuXjeOb`F`
zGzYiHNlv-d7F^L3IJCJq>$e_VO-8|o_Z7`EN%Yi0#*TvM2O{qaXmB`eIPvg6t(8~;
z-I$A$#b6Os#{B*PtbuO2HNU?SD3!kE>v|a#+`VFRcmaY84@9;#$-qXlwZDOB5;*ht
zM;#|%_Z0h;pwxUrv0t_{AVXZawD!|jyY=&b>VpZ&f9rz@;AVDU>40!;v=88lVqrTm
zr0W8%K-Ri|D?qJ_y={PAu4OysltZ(`JrAoYu-mQ&
zue?@AIf&{6jymCHQEk>w`p_wlT)yVv%(|5ooeG>gYoFn1=k{&8IftFX&2i%#+oYZZ
z9)W9YK6eV1utJBdYtXsx4k<61^jB%COSUhN1f(`KiZC|qS{}ef=DtD)sot?<@p=jq
z@3LIosH8t)o3bKHumsms3an5yT7?cR>1e_iW-lwy^3i)G1Y-$;_b61^
z9dOKAMx^!G|4?2qxobJDMX8hgF214BwY}&u%iPxz*;hts_tKVJ?A|XZ=Lr_UtX?H>
z;4nuN|0os#VkMpFgD4}OM>o&T=vzg|3sBf_Zo&kal3Mf<(JL>#z520MOvmzo3Vp0u*za;YQOuNf1cc6+I9=e9D-YeM;?&@)zoTupM>
z2(SFz&+I3O(vSf_ZtHxkBY@nfmdrCji9ofapDDjT+QJ)lkg$ct41%>mQ(o>c0L~E!
zT<$O`_wqPpKYOV@11Sc=y-_a#!tGqCfSRv26Ka1cQ=+^(c_Kdh>UbyKL>sX(xiYzJ
z+$dUS#!f$a?0Gmi6gE;Yq^PyXGQ{Ws>^t|}_-o)kf;*M-zhfP#exdgu=5mV@=ri1G8t-c4rmPXUNXMrHU
zp-@MF{6?#${StI*v=a3L3sVRh3M)-Br?gJ$yPLn%UY^yH4?_ds%ns`x2g>5zq-+j2
z2llxND@>Emp5pr+UMw&8HAwK07YO`PY6LCE>$No+ki2AF4T4t$GO~OJTa`1CeO*m>
z+0VcQR8*7N75ASe^}eJlu0l=2S)#A_BEs7|Rc=58Nc9)%Dv%0&#=I9ug?{c%F6ll9C2hj9daFzkL?_$yrA>j61
zY+B0)@z$bmq^4(^imP!N83;4AtB0@-v|PMg>*9IXLO`BAl9l%Cw~ORX
z$rY?{M6FXx_iEQ2x2u-IB&beWh%Gn%Suh(!)l3~53^n_k+bO_Mv%k5LLUqB~$9$L{
zB~3Tz6e^>nf&D8@^7&2BmzJhS4?ANbC8XKZSb@|8j3I>Yfgk1V@S?APAiu+kK3F2H
ziZ{iDPt`L)e_+_vy1;1!Gb+Yf2zf7<+}GZ=h8$j;dV8fXTT(qs6i8GO0`ERh2J0k(ha=gqWC7RAV&e4@kJ62q
zH(2)c{GTqfS3%vKdC{oZ8;Pji`GVmQ6nU|yFh4Iq*Cgk??_#-_P$XdlxXq2F$$-4g
zjkUu=0B-oacrF!hphsZIP^HH&pA%bCLSPNPFo+mh*3;IyasANVk}OB4PO6U34H=G}
zf%<~~_bRVV@s`7;KgW9*=A^*qOdEdZwXg1mlvb+6bDCTG44rjN
zftM|aFD)8>`we55i7Do-v?=bX^_w4F(3-bz`5C8$k{2E&gNZ|)`x3bBQ?_8b!42{>
zc!e0RPs;Y+qV=Dm$at6~=J*VK@{X`TQHQ+MFc=uuW@R!A(#;mbNnQ?(ln;Xr;)MLK
zp6y7G=1D>LQMTBP>;$r3MMSjK9n->zRxJ$KrTceU%Hd;C&{rf}WqD>Wk
zPNHpgvY4fI&`jMq@?iv{cA~Wy4U2BWxuGBfp`^(qJ(<-!8->Wrcs5hG>iQfEf}<^&;_+sa`;26&GF)
z(Tj2dt!R%lSp0RGw&kmynKBs;1uzgp{sWaL@*luJ4EzHah#B#lF;|?voY3lNpim3!
z^Cj0WXG;OU+@8#C!BlfCU9h^lA|7#0y*F5KNXp6h**_v06M9gsW%(7fIxT&46W{a9
z_&w&HU?cWg<9*#yde=fwy!DOVJL@RC%DeDCcG_sDRxe5p3rtYFX1?Kd1b6u7u1dch
zwhb43Q|QUWgcc-nfQE5=XECy2tbMBg&RJAK`&8#0vlLyyU5BJ_Ou_m`6=r&hE?qXn
z+GxtR3CQIu-%-n{&XCK+sg5|lpr_45gz5w8z4Aao|rH2y=#7h7ED#*#oOY
zuI-9Ptrgirt_4=9`{Ke8?^z7E&n?8W-DmLXtM00H0}t)(3$ur1B^3%pDUZj6Z%giM
z9B2&4klQoK+Wb1u>Tn>U8B2J)G;RUT6Uv{Xr1k3p3D
zHD~@C9=0-U1k3D$S<&xJuaL2;uo=CV%$$|5aDm3M?f1H+(mQsnyKNDg3S$Z$
zvoavHjL=sj*uNdJ-7h_lz0QyEOo;=wc0drR@j!MT&Sm>5Q2+;d3I8{E-Hd)j17ux?
zWWEA83N>Ve0VpY~;YA;mn%e)~4%4OgB
zxj7n+T_njrOn*CZ=d@4K9HA+%1O-Ln@!!RnV6uit_W`}4n!v!5dtj)-QkglRx0LOJ
zykud=+*8$LUs@>dGjTHJnEuL|B7Xzl$8TtVelw~!fs+2ga}$$x{}XLjiMD{_^WuWp
zfz6*f9Z9C_UbAdol_Vw^_qow3)iDQZKTV8Uxp~-{i2AP{cfnOj4iB2~nHCG}xgkFo
z)v@}s7yM55;+9ceKeC{~S#Loltp1C!JTe&wE+eLolNMJE`SpVaw^+V+to}&T+|1rtBYpQ;fH#4-_WD8-fm8NbGd%i
zPT^8gnI!?f7_qw=g}O6-3A4Ps@CnF#yjeTonfbdMMx9pv9RXw_B_p
zY3CX%cz+=aNm)jKPc&U-N#q@7M=-QvF_gpY^6Erl+*h&rGc1*++X#DcLvNNCOzS>W
zMFiX0B6jJMoF=sL^riFap2XCW6vjKY(EG53y6=ixER4a7^GZns9+T$jM)@i+AL7gV
zu!h%yPhw2L1jk~8<#2mGRQR(-(?+j;u2<6MwtB^*BvnY$;<>7{e?NW-d{x6JU7_h9
z^!I17vAX^D2VJJ?Xs!12F9?-*dD-&LU`qRF|Mw~vl>#cf2I}|0d|DEPtNEGRA7y1FSLKhvaEbFGa(S
zk3_~sf|VS+DeSn_85g}|k2SG2=R7;lSKRKSPLucX?x067#2!b{jTvPs7)6aM2`}ME
z5Xm;3X7B}^2T3E3(}_2WSK?h=$sK%t{*q@zAS0?qwSEcDl*qE_0IX`Tf+=pZ2q+M5
znUdH)dF$SYF?-J6(f9=0gV>B-0Wn3H6J@E{b%%*1Nbt&}mwV+v`g6drOib7Z9${(9
zyIW#dvZRH!TR=*%424umug~6k>5qkAt)fF2_)<~I0o@p!<&~_a(F4ohFu@6cL3>{|
z3Im=`Y-6Z(%FLg8yOdJWzF|w-QAd7`8rKAJAZUV7a)2jPa>G^lJiwXso&uN2)KNzG
zUcLukD37`3@Dvsd*+>=pt<@vZ&2+|Xm%}5-_IVqB1)(5fH-N>
zD|Ip{6M?F{#s|Tgh58&ALNuyP3-6uKmABtwnWl##aX%xQK;h0zsFv!>hwkBn+-wDG
z_E#9#tpESo?BIXfOcQM83^vRDzcN}amK?z=s?bSW4k%y`y8*MXwt1iI;Mlkr8Y|5(L3UX2nbsUUHlEgkAL66}bZLE)-k6X^Wpx
z+DD$Y5X@inzikvWCdL8q{0#i*QsVUdAARxT=Qlo()!as^KaS1xwWSD9|Fi$8e$wM5yOy)ZEbLcyOW)bjnJml{#3nth4cd
zDu0g;Ki`9pJeNQ#^*=JG^W_Kvz4kIF8#{&bL`ugfK#_}PH@>T8AeSh~ZB{eoF3om3
z`;3gMdDCtcG)U)0rnov^)>BgsDG1AAsjBMaUudIiLjlF#NL*eUn5l
ziX$OPi|)_U**|^oVI@!nTLBMHLV3VHTak?e4{%{+^ca8VQedU9m7&CC_r{K}m7cDA
zmEYYZ70GGyFI17K5)6W|F~QMa5={~e$+#`Y70}7*($H+
zEyc(sl&E-aDvcF9xk9)<9uZjdk#+YC-+YyE%QKF9;V8!R;~A`N!t)cDRgLWsP%F(r
z3qMuA%ZoXY<_~KgeX1=5YjzR+@vO6rYTS!z(~&P0AoK}X{u5yNS5L~PF1)v_@`p9`
z)tH_r+|7OOFIsf)bZk-WcWb&H&BCN-
zIQCCc-8~80>DkH||8d{{I#X-e1UY!J_ePIdU62&joc0&enG*i{WGMRFvj*xYour$n
z7L5q<;ib`NB8_Gpg3ne8y19^S0ajU-)f5Iug55AZ7Ug;ID%{sRTNy??%I
zN0{&bpLHmf@%?{N)_=78Ut&80to(nF>HU9=2?#)6bdoe6-AWtBwuq|$T|eA8n`jhy
z=&_AGx=&w3i83bpkS0fl7ta`!kN#oZe-;W(=r)9)OTKEQZ(_SIM4{!1G^bJ)0vZkc
z{EL6W!Jd<)$jy;EkA`fFJoGCv%m-7%u!$NLKbp`b#E4@p`gg-+z^O$jP7SyQbPqN}
zKH)V03~4Uk#Zj!v2v{{C$tRGoYg20udS(k44%b8HNww^=sZ`#*??T0kVOPCACmHYN
zMwA!HV)!yll5ZQzCa&V&j_r)GyqD!OeSidU9K`(kX>lvV0wmnS)WvBys(kQj?R`ZU
z1TZ2x&K*1I#D5u)<^?k9?*YRR6~p~NH<
zCGv2d1TduvHvcc`?lP>(t!o^;ih^`Vr!*p6B3;rcNGXkU2+|-3NOyO4cb9Z`BOxuN
zgmj&`VDJ5??|#nvKj*`_u5(@Dmo?TLo
zR@}^lT9)jF)TIfj%Sn(=6-M{(x;mpF-wiocKvDk8
zH^3tKA}Fc9RsVg5=tcELFuOd{(?fo;aF#kDuTZvC!^}K(_&w9*X7HUgMsbU4^h)eg
z9FouNSR~*At;oPodbMz63}DOO9w=8`k2xv>TOyhswS|U}=>Xh*AhMqHsFvJUJmX<%OmKN|eGxBRo~!Th=F
z{kpeMjTw?x@Lg`U_cjq;U927LE?u63&m*|9t8RE+&+g=O@co=forsY4a(waGzB!gx
z)2tIacn8}?65Z8-()GnwSm1Skl*>t#-4(+5k7%Wq#gudl}256uaA!P`h1&vu$z
zPFFrFF{tOS!C)JJKcRruzwu?JT&zhJZ;L5Y4%dLdT{#M;`+%wEV4tG{^7RPmbkt`p
zhv%H)wJ{U)V2#!%DHRl~$Wa$-DLt~mJgULG$Kam~`-&}kzx;3%Y1`op4&6~_BRs+Nq=zOUFsSvt{mvo3d|7s$1lOon8P?#Fnx3hj13_{{vONG+@%
z1IzCT5mju=rf=_%y>B%_zd{P5XpI*C*O++vRm5-jc}z
z!B3nl&wcfC)$1tYvRqUpbu7~NIk=(Z+e{3Ea6@1f9x{2z(A`PQaR7fDn()eyF`zwU
zvxK^JAxp`78q`bjN4@8x+PHqCpw|><4J2V93Fx{{eLtp!66?;OLW7MIThLW`wC9rO
z;mwr%+W@Cv0AJGa$qkguRKCp1!>FHEXK8SSo7~ht?r~E$^pPz39InedJ@4Gq+PznyCAsY8}I>m-8bRO=AF|bI%
z_;Q0D_JPwHO?z+>p)^El<{*I`SUd-Yki}El)O3}--on)h#<%lW6^#rkWZhrYfoue)
zw;KVtfU);li8_!9TV9g&icI31?lUI7>-ymon{~DwxBa7tce92{#^+Ih_o`Wa3lk&+
z``<%Q5!Y+B-|FAh%5q2+K-gFcga0TD2iDZU)fu9ENsj=n@f;SGJIK@!y5Po75>P!P
z*{VfyvU2ZhOzvc%n7+%U#g7LuNHZEuht&8~wPV@v{VcfDp)#5}FTgDiextxB!PViQ
zt?_p`B4HCG^%eG`^I68OTt)z^=44*!Hj|Ewj${^j)Se`2Qc8@`PjcB5miQkoAc^;s
zuFl6OTT(?GNs*nRg+P`z18@tv-rja+VuE=fIRr<(XaAepHhOJMoUAo~{Sc^%zTz0RNYM&IymS*$Prl`7HZX0;7~Tt^r;
zYlQ>cT#ociGM!*D96bJI>EF%<13?vJHo#&_HNfBSWuF=SXP*NBIxb{@KMwKy7c&c;C7-aCs13U2Sy^CTZ|qoNbhC@eZAD2l#$>R!>WWpUGY?
zoc_s&$2O<@&UT?eYb>GVAa*nP!?9G6u4t`9o^U(9zQAL=q$*y00ZQA$l0~XP`!45;
zOr_xT1j-^g#?BaJCsrPFmw`_<-wPXX1NY;-wnxn!9>n0T(o8sCpHvMx9!FvmMLU|c
z%AIH6I-42enS@;)>^UNCPrcdC@Z4T7cWCc2Ow$fzCN2yZ{Nlp%2)C|I*qB{>aGmk|
zEKZ$&Kp1@L+k{=itdnQjkr3>lzNx!uY16{OH@Vn@=*ugqqGAQy)r_r_J%{H5@5VgQ
z*78k@rH&5n_!DM459)?8aPU|irJ`3O4Vdh;@JwS1XSf+4iAeJ&RlmKYGvDY_njB&K
zjatKc^+0C)ij+^!Z%VAcnFUQ1c9pXAaoGQ}tdKX1N52ER|cS1O$*M+=9yW#<(KAH_2`G8KJ6-ChD{is+O2
zn;ee!^3_+BgL-rf96hGwPb%_IGlkk$nDHB9HJ5IOXlmYk6?m9^;aREV&Fc|j82&_#
zu^ab4kN*IV`&v({ST-KBYRhWr;u?x8NS1mQQAD#Fn|c_IbbA?;9UYML*cO($9ysNr
zdcl#78px+=hq8i+Xj3tMDj6o7C=^%WLd37dO(T=KgP|=4MzQ!~l%!&Z2nSE(-XsHu
ziWM565MpLxaCbTEjo*Ky7XX>9dbm6#oC#~vZ_|m35_E#tF~ad^7-9J^ZT-QtBU%It
zG8Bq96U+OwGo&ab*$hkp?BvuGDy>S7B%Rc6Y9RC+&qLUA{_1jtF6HvZ}Nl3@g*<=-f%6b~2+ABTJt_
zBk)3&x|q6;=g@32ZV;FjJvMG_Q>dq)rjTn@3X{OUef}Cq%3AnlW}G%rpVqIbJB!K
z4|q+N;D6_TPUNZd@I`w{#{XG#-ws8yw56_>0->W&s>;
zjr54t-r0)G&LH)shn;GDO;p;DN;~ML8r7b}u^=VG@X8FylI*83t2VaQ(YCqCvhU^U
zsGj{SV4zxr+yz^mm<9w5{}XhtsI8Z$~K+`#NExOp$<&
zQl^75`!=ixhiL7gOnZtUI<-8rAKrIW6SV3If=Dq+__ohGnXdl*_ZaI1ys43-NabQ;
zRc7B!YKMI;*eRCe@OiA)$yDa3Oya$W(V}2sfE&;=*09v
zH8fJ0?Zeq+CIN&ZluTbi36b$a@AsbEU_xPUXAE82LHsLW6uP#Z2g57;D&aIH)-vSx
z)y98cW<9t}*xBX%zXljJP{`E7eD=>PHV{Fm*LhaGm3QvXuR#5*%^+AfZK>L48|8pG
z;lm0f2cGRS&bFUpo!ktZE9(77r<=$cS8Lr$KVK0QsG8;S<%M!4ypF&x_mBxP@69Yb
zdu3w7ETAe(P&)oirWBXy@);TF%GlF<4BJedJjHwT#0{^L%6Zk5tg+DMXo4fti0cJQ
z`J@}Pg=}vgt+;*kEmr+pU(n5?OuW(!Zbpdx>f;&B;yzx?7f;p9E@ieC^XFerY%cr|
z3h>-T>ONv`hmXJ|$>3m7e&ULCWv$XCntiMmc8L(AC?dQY*uBes2xr_t{4$r*Jp#>c
zQ6uUFLXpD)>-6BJfwk`aAJO@N@D%kR&C4Brya@KHADgcH}5Y^awu0D8)^!K>LJ+<;bP|
zY0+gcJuGH;TheWBs?Xn3se33w*hSm>ee=`msby55{HtS0j%n=vffdx=r4f6=kx+C-
zFE8z4mV4+05i#xWN;*lsl`nt9aQ$Rv!1ca-{cPo6lO_=}eBcu{aVj=Vz`Ym7Z&6y?
z34D
z2uS-Qp!6vSAWb~7kKf=AcqfMtDf}t5g2{VPJ4ghj9uDQdc6@{So@Ef*pY0Ik33b-C=
ze+mTi%mL<^9|6lz4eR!`h(SSYv$8UNLm|}q^tS*mH}CQ5L@~RSZN<6{cf^^EikTh;RL9+iVlzT3If
zW4Z|66gD+Lc>{#Rf)Ki$+Yopuw@UDhWO}dxTyPrgUODrKdMV!0P;h&2ZtR0bJCmun5)(er#U`}%XD4{}dm
zalJq|wX0N`Tu$!BbEF_dE}W$qwAS>nY^`Hj=FTkZ;`ajOGo}ClV-j#pGzRk^aYeK3ZF^
zP2_u?anu@dl*xy$a*Z4UTbBuZZZ2iOi#4vkEofhXzV0=ojyzDu%fIW;V>5zWE}Zv^
z*FCkaHX!N|!~
zS@Hvw-nS?R*Fxq!^OofVh7HOY&?$GFR=yac}Uw8s5AcLb
zXG=s7`WXRYli>Rt0>caFr!1&H#`pzb)mFHUN
zGi|;Sj^2A{8)oz*&t~S-o|{E3xOnCc=J8ZIvtS0s1$ycm(D9Q(qx%)n$f~KV_IBz~
z;g{AropN#uj<09ro{qYI9A+4LgCvYVHKC}&SNpCfD(J35xMtRD1bP|=lth-Jo({sqm+uBRAX}9%CzDnlUNEe
zk5mKMM4@(4J!?Dh0VU&kD!MeTq=`kTZ+_OUOHcG#h9YNh8>uc)2rtgiCQ@VL*154$5T*Sdr69jpC?EH{?-&4VN2b`tSZ#LE)fO^noM;FamWePzm)4~Zc2F;RYf?YrPd)_@fQIx-wQ
zf8-1(UQUpT=rFT@J`BUX?(e6k8aETSuW8zAe*EGNIB-maqW)(reQGC5*j-tmWD4(pw^Me5h9yC)mAmT{e}=0z?Ct3+1?NPWOqlgrrBIf=lz$P>*l=$Sct
zmoZd}W~;t|b3|Eh3Cv(>k(&ju@0gUB
z0-SWD)*|I@I946}5F_W0XM80J-S=LOcipTb=O3ed;5;PVI!6GCs>up2*&S5*Q9z;e
zqXHwKR6and=Pa_|OvP|6Zs<;r-o-w`;5&K1#!HRE=0S6KHxD>!a#Kw00g1~C4u=Un@`JMOR?i&I3J@oB;|67Ql
z2*&1Z#2AP``Ypmx9cKtd{Q5nZ+fLk6R&Z;!|F&sxaQ+B#EMn<@#sQyU2$mt(S=c~O
z=WWn`N^SD!@e1i#uG%(ahf)wSH4w%P13)YA&$eI%5~S>>q~EK!jW7cdQNKm71pP2?
zkUxF*(v`z({n93%*a58fsoVAb_q}Z|-~u+em(;SoY|VSj*3+v4Of7^*0BXnD!7c|D
zFxbNcPw-^hA(LDFFr!v#7eV&zJm|e)&r0+JN7%H-cdHZH1y@PMFB6XA)@QHd6OLb3
zp){o67@B}{Aa?o1(ZHKkWFPKqoC%%>Wee&i`Mnh8o82^PwJQ0)1l){Jb^yrw-Ve~E
z#4WhH2>0t2^4E5o0CHzvWRl4>k=oApx_?{z(d2w_aeCNVl*Cha1=Rqxkp0bUmTj{p
zJ;34nzy+aUYi33`+r}{$0cZWCoFSs+Q4ixLN8Z7K(b-u
zVL1Ngna1fh!8S#4&Up@T+OZu*EU-TuJ)3j;7~rND0T>htQDlb@VbI{lVwZu%ItU}r
z>@8Tqr?SCGMi|$tBeCFDBMr_p?qi-DG^
zik!QY)1GQg%8u4)I57%^EfalUHV`Xz>`TT!R^4uv>nvCJ5Ie?5Ir=^E${>K>JV2s%5w?*AJ`fRC?fcJj{
zgd4OTF;n#P5k@^3wt+{@VPFp61Yr7Wsj|uq;{DqeIOwKTC=qbXqf-EN(b$|=yW6yG
zKvmCUJP&=_A_fCYsfi~Q^9l_a^_nIm`}=Pss8t0dqOzsF1VuXjUF1pM4PGMz9Q7SBvrkfSmHXyWCkga#UpR+yEqT=PvmQdI^Y4ex7P###FV8!h&MyzcvRn|-
z9h6z;I;&p|dzilZ8G6Sd$f7s%Sy^2-VWiyJ6P{HE1o0z-x(BXbVv-d5$&9t1e>rQr
zRM}F3bJVu2s9vS&caUrp`9k~c3xn~i5+C1N;NP>q0a1EWAgX%Y6su`Fm@B5(IK=G*
zLBG&?Y0}}aX^QE4s|hebHW*;M7=Y@;?)Y}w4ZW8pod7W9EP^3-E}wI&MkJMojmwVy
z4`}Q19=C2PL>?y3235XRCO{$`W&H}s*Z7|ki1Q61#jMhNm<*Tlxt67O*fDf>DgQ!q
z0NxNXzEi>x@s^tkDt!lY!n3u@>H+(&hXdWtXx`&FWX7fpTV=KNMHQrZ#6dOomB#_3x
zGpRxb8858&%J9H8Bjy8nEFdInUTxegwtGXeeZVRu@PPiFJI<6@4x9!&eia|vkqSh!
z9{gG#^j9W)km*N1)j^%f>*t`DTu=;Q#P7urfsjW+a6d}luYzLoK{3&P6ypnuX)sOO
zC5$4`uJ-r{$&+!L=K*E&>n}iOONIIZX-!!ICXQ{VEgd>e8`9N3TL&3njPMYnD-PdjBuj>
zH17jwj=ygXf#w?Mwr%Ak+YcX-nCAuNV6@9cmtR`Uzkm6{t^eamtd(n+#5-&H)tte)
z#>URwMx_Jc#5
zq=Ze7zE(pT*3UBI|6)U-o2TeTU-EhGEdBDdcBU@*+nQH7KH?rh7?I^BX1R%XQSP{A
zM%#slOU7WqwNJms;e4s$^?U<#`gjO&qmHG3^qiXwV#-Tv-2Cvb@Yl5r+D_x=h274C
zqIsl(PMxz?7GM;khY`8MfLS$8COuG>ZqSPeGyS-oWrFHe!bvT}O+Z>PrqRo%{aULcTT-Wx$^AaTT{v(kBxaw1M
zO)k2u)J04;QASlO&7E@RzUuQSP0%8W>^)r!w*C-
zcI-j`JHfz)qPyCxk!!RpwpJ@`7&qWiJ9gI68%W4sgU}CeV}x4Fy|bt5cu3N2U>Faa
zmpSN{3kGlJ9v1=3#VJSg+N9EDVoWby1eW#dU_bz@*BL*%ysE42>u
zCa0q}&S%t?7M?2Ob5G1Ctk%m_Mz!XbO=qkuNoql3j~vWteIGkDLCZUMDa&Sn~Vin%bO~DBswPXu?{R+6OjZLfC)?Qrn9E3x!?;)0HsLbkwk|R_l
zn=B70dG(F#tZZVt?*2NQsEf&py703^?lq$*5)J1DwTfGg7wn{|Kr1fi<95YH>K
z6sYZgj?228^?;<3edmwC@O-Vj6d?G>Z+<*|&Fj|;GUeZ%4VUNO-C3oZA$FB(rOiL;
zu-Hm9yUlaP=nC0)x7XF8FU1GG^V?&AfldMhM-S(IJGeVH#MW!FtR|1Q8JG@W{mRaw
zw%Pydxm#&cgw|IZdFC|+KcR^MAIEM-Z+Ssy!Ca%rlckboN`8D=MoA7aTxiRZnWQD=
zeK|4Q$k$0|s^B}sy;I8jlV3rM`zlV_7
zfe@M?UngZZuT@NKC0H}uG$6L5Kx~r`EN{g27$UaCGMuUd9KEPb;_t#TDV9y64p`A~
zxOS($hLufgz&F(=m5D#5$9n^^Fy`O440r{y=s)M0N4>4XUAb&l0`>{=QR%{Jeiv$|
z_`6X%fT_68x!6v0*U})hl6iqb5JKFX-dK8rLR3H@Wq%ZcQF0z>R~*!f!8og0%D6Ne
zY#ovt`vO4tuGr%n2;cOctK!+ORXU7EJ|cfk+AO7`n3HR`0+nh$0{`K3qRGBh;5$Ja
z6Zh2C#CREr2+h;KBX*~vLt|75Auo&%Ii@9jovr{6LrI$@d`Ui-GL_$_Y$XQ3Fz-}v
z-bMaGZxKo_xR~gFE++U!erJ3<;=LQkl}_zLNFyV@W-{ghe6|FIc0Y#TGxFtYcAAy<
zxdCsjW-b&oR-ddK7v46x>Mdxf@j6}Yg!yfWEbv?%7twjcv&Uj^SXAnrA`R==Q_g8_
zRI&|c_BWEfmL&A&3d*kh8mqtqHd?;@P`2S#D)W#Sozq=&2R#!GlL90|
zp=D*Xi}E8GdW2Xa#L%GNntSfOWc`;&KUQ2m?z;`8aLGAuLa=4KJcq;6D4)!KWH
z6etMWcK)>!r6$W&m(*MLwvPfPz-+{BC}pTN?hEheha#S;ev>PQXPPVsEKxrI>OKMP
zlW^-kan5E}0>=$!v*o3iX(7gQb}J4eHgA=PYHIugv1MsSOFs(Le#z?&u(6E_j$1ue
zs@Xiq4JsfCz*xylTf~X&o%X)lPC^5(prm}dUxEYYl~1Q}B|Rv6XrE(r_4Dyf#t2j>
zUvfp@J4v^`GrfKSQ~P6Ff2`c)giDhJPGLzb=7k$bmR$PL%KDbBx1}dtQqI*sO!y{T
zUz0$BZhU7NmWFtR@IG~0G#!t%L*vz>xy#)dR>L)EmiaX8hzt(+G~Mq)CXwnS91zWr
zxY5hMH6w;#*saIQUoX4V?pNaZ6?Lx!fp@Uw%4V&`F!Q|#2i(dCxb?BZ$qL$6z?y|(
z%&jR8#(RyGc?tv)Ff{?|hCoxL>vM<_dFAXLOqes(}k#9jMyLK>?K!-&o6SGxs+
zmH+hFdjyP_4WZ!5saqtN?iA&v2gi=rUwm5t;oEiMazdkB!}0MQBEXu~Uk1*K6bS{s
zj54WDjt3;ckCiSjBFLgvq);YyKzh-bF?etY$}eI7($ZTOB+;FUj$}k>6gvsKsvfb#
z-=!vjC}{7EB4uUB_$NWgOUvMJU4kdpYU3>mjUN1%6&?R>g6}r~UpmY;)NQ!&Xqgfq
zvnjUf+L
z#%g^42%-MXJr6N>V${;FA%I?yd3ik%coQMC$I{j+rwBWsVFYPlD7aeoUl$yp-0{Vw!*NfqiHNl^*nCbq$(Xd1+uFbl8
zQcyJZp6|s^h@yjjM2Mn)FJFT3g)qA9d=<1ERjPtUj!v>KLX6G4#t5J|>gv7pw0*ka
zwEenmF^t+d(jp#)IF7ylJEmIqZjR+2mg;pQw!NgbH>mp%pl+`4->3@?ZO$nQ;xKXf>{HXF48NW8tnJ)IO!>(R
zA_0-Af=xyF4}e;dLJ+%r4jUt2{VY*yd!X9eI-Nx+|A
zJ^Xz>!?oPRDt{__i?Nu$F4upKld?{#lJ^(W?^(|doYN`@nFG;{`(1PgH_Z801;rm2
zO;fO6CDd+P>f>l3JAxMF%_VT;m93R103vH3KmqBkH4vb+wcW%E+)wV@
z9y70fpfzKEf{XD!c^#v7ciTPf=zvXYG+}tI>>wa;kw0j<89=KxE1YV+Jq#xv=&iMC
z9VWP?)`ZIjXd9Ewqi8=rM$U5}zn_Kq^Ta{xtE*?44YH?xd1W)(^unI`Pb%&-n4J@l
zN)GQqX3rm3O7U?xjpZAE%pIw!Vk_JSnOkX~xpwH?SSA{D0i?N>`95f_>A%FElr8A>jsC>?;`Af4>Z>fr7^()5uRoRBCPm_
z2;*XN_qY*87!Fw(PtOsNdvag+_&%TT14znXTn@3;$I1jXPcP@uk(1h)w4DTr6uM5nfJ
z
z7p~lN?x{PNzkBLmvYZd;vGot?%{Qp6&}9~iA=U>ywlI!+pj6MB9$SBS&|^Dg?fC7K
za9JW!5Yz#o)M6N+q4dl7<85aOVZ0-JvT_mG>5!NIgKhOFJO1)i1AyH6E|NdCU2$-4
z@fdX5K8$_S8~iI{*8mM?zgt=OEQ!^d9evJF1*q!a0npLs-;_dC;oRqMsC|w2(4%v80c~k
zD}2Z-i1Z>;5AArV@Bw8Y9;ClC=dtO$_V`_OTU_a<>gy|)u+88gq1}GHRsY?jTiDl|
z9@Oc_(B`&`j%&1jAR-`H0WfAFV9bMm{85aOxb5psp}x}mXf1?y834QP0p9(UUBA#G
z%ztOaia0L+X$=rl8XzXZZ-^;INec#9^H7*?9T7mNLP-Xo%Kita>UmF>WCUamKeyr7
zQF*?8AskFCEu{l#nVo+JwDeXg#gG{7>W=loPt__5;=`WZdj&8v=y%NQMg}3UBp$ZY
zHI|?lMNo|7AH}?Y6yuFPzx+}N6jKa}ss5vw$iIp?yP|t7J;>e^HRi{_s;jJPL}5?=
zUG)-s{f5VdLI978?-tfc{}-8^ozdFOTr##^-T*VF2?6Vz-)GJW6+*js(RBaCkeP%*
zhi~FK6tnQZ7dpTSdWg^Jx3h2|oet3AN%EZB*B&^@8P_#FjIf627%8`RgX$6q!mw`_vgEcCexNc(N0&b}Zp*+|5_R~5iyqnmb%e%2iFmYn9@^w-u+egv@EW-BS(
zmGgS2kXRvC8g$S)Eoxv1``>oZLK#}?djE+2!V5-G1hUKehwOeA$s;9of?0KruYF*O
zE0D3t{5z{UL0WWAka~{Ut>Hn7u0m}r-tROV_}2h-@wFZmb12km4Ty^3yB;oT*o=*v
zA0~Bqi_*qJP#fL%Ii%-WRLven6iz@tB|m9tqVvbrIBYa7P3j%q?7E}jV~D7d1W8f_
zl5qTyfRc-uf(UI_4)=Vr0|+YY-|8z(qU2y1(M0lRvc1Gc296YL1{R
z@{IS4!k;0-2!OuVj&~(6WL=PMUMoumT>rTXKaag)e1Ff^4{?EFz5$Ba3c6K4-p9G=
zR-J!Q#=N0_SX}Q10`NhA$sYlQAV8(#ZB=JY;`l>C5a9Gjfb$FYk~r|mwr}i-{{Mlt
zb*HGKol>#Jnt}ffX6XUUu5i&6Ex&KC$u?%eEf{8(^Jlbh6$UcfP;n!(dvnFF0xdoe
zBn2@3L(qLUrk4epqbx@VzXt&R|Ou=a31VgnbN?mL1zHuBNn|V8uvSmh?&xot~2WN?@p4QY&
zqh_Yjd}o|S^?V&%W-*(q3ffuAz(yXl(6$XZ9y`Y}h`#JuA`GL^s($bm2<*K-1or!<
z=^`*d%_A^;Ux1)IZCp-FJ2;}deXD>jZ$!(s654UH0$eNYw>fr}h>G9d&v3;2w9lE`
z0=XxjVYUU$96wh1=XXISUY1{tH}yr6PiDXU@(?;Z9vU|5Y>SaOeihy3EhOg=J%YS(
zqT6{MNbt%wVYsbUwTH(70NRB=fYwv%=&9H17Q^-UIc2Co!O@KQ--TBN2l_jGz1sQv
z=oci$>un7y+-*6;O~kKQC7kvEc|Hz=bdZuELe(hm$n4?Np9x)i$8fGN6f53V+k+ttJY4dCW?HKN6Pp
zq7)1=3z1-Xh-*UhmH!4UVF>|R_NI{#MSj()@tAt$7T1ye^3`b9;y;$W&%ND98&K{)
zuoz`1(yOBXdZj%A}Ki8~A-o?6WR*OD96pR*pnD#0ckk5@|f@>N+E7NBj|
z6$8*FEJnZ>?DvYuelE{JamD*Bd9`65=z9&oC&Y7N>Z&036r&7l6BrO$*!&-m`}dSU
z9GBvZ?SE5Tn6(&XGva?S+JvX<+l|&ClS-#5f{bGX_=;gHdJ%j)`i8o@2;Pli^gjg|
zm5wbFYrD4c>PcLj4tIA~*48eQH0m#kT3h36tBA~;PsSIQc8f;of2cRrb4!wgKPZ2_
zywln07e#N*Q||yi@1S+3e{ri*2H9Mr-i5yDYV+L_3<~CqpY4llonKz^`$~<|>q9kh
z)!Q8#UG*xgBwbBjqvgF%@v9jsx;mYtG+8YxOyc@*)^FbEbYecKy_b5yc6mPpBUeZ0
zz=24Ii`L;){Fo=`3w~HFB#5U%#l3aeoHiK3nWdAhU(RbYM)jt!E``YX6h)H?(XLK;i%iJYbFzc%FqPKnVHI87@zOcVSoQVI0P+)W#N1yle+!p`nG-}SE
zXwt1&Z^K#I5*$VmVRzEZObMss)vCb+VtLxUrA4E&ath09~=ldpSs5O@BCoeDk_(z0>;I?n~Yc}9YZJ~I_#4q
z^jLuy@lgw_XZ?|JbsN-a>jodPrlY2v5>w_9q!p(vLl!%?t)dav!v;r9*b~ya14EH&
z(YJPe#Ohw+BJGKbv5!3^Ukn*!5h=kePfrkO6w2V*#|bNW{&S(yFK)whf-pYt_2u&3
zopW26^Mt+b_P3@^!&``TX%|Sv!NFz;F)qeLjt%Z+1;cId4zvdEXcz?g;wz#{zIN$1
ze@i7|{Tw>%TjLUNcW3rv;@uP&6q;3vU?b#urdj_Ae1vafuUUUKTS8IOFti)1e8n2c
zjd77e#YXtdxlLq_+_8g-{rp=a9x^8eiU4F(Y!zAFT-L2j1b<82*+%vs3H7ARx$P(+
zqd4!bj7V`&NjI-Tsj!V#*kg=wOoirB(}=#gAmHI6Wx)xFiZ+RH0#0IBTTSYT+;xPNW
zZVqrb+ASIQA2dA34QTvyizA{K*^u0No|1j*9oc*HT8>OGAvTu*XO<)oza_}(>IIV~
z61^yN=Z{5`*{0Y&L>wwbjJ=lPFOB$CtLuvE`L7JA(?Y+~sL6EuUoNW_X!RK&(|4v#
zs1WfOvKs}^c|~kDpcNvt3{sujZ1MR|ixrJ+Y6QOCDMX0vk*nM4dd9M%htl{?w4ox
zE;4om3SIV?MLqSu@Q%UZI%Rono|#wCG$9v-(QRBx)SF`$h_3aR0JcS$1MS^n`lb>u
z$ENj#GDrFQ#dPT`7)dWhy2PHh-w=J#`VO5qK6Dl8=WXqnJj(N;I5?*4oV(lmp*EC3
ztDH$|$sj}XUW{8>MglC^(mu9-A}QOa)(V
z6h}tyj5P`qU}LRoMQZk#bq6At_@5?yA2v_2>i#f4!1L;RA
zO>~3TOLX(e+3JblFcF(Pur*8~*HwYbcgZ$ut}63X$*dX(ZSm&`~Hy9-&uno}%$!
zDMwDASAXhfH6nkY{6jV>w}N(??+GFis{}`2EIGbNKiU;iw#tmWY;V=)TE4RIOm{t`
zgss6wZI;X?Rdtz3W2@byf-0rs-nbq7EpD?i+soed?qKcvr3*#m$*Q8C?^He>{0zQ4
zqf|)cgeJC17u)SDl5uFL-?lz|O4jj2*W*HcYC^tb9JYGO$eylJ_3B(RucE93k@K}r
zfnuzG0S6wss!dMx_Tz~B@D{G2bQ
zB@{4C3jv{f;@@LJRodZHc(W5dqrNwQ5N3)%^o;XPKy+WHR9dDqH=zyFr-ae6GMh@w
zJWqXPN&jnDzp|OvPFRHHHMj#QhqvUt7={IHwirX4)(c!Z7`
z*o#FR*jvUpvAQ}FwfsSitwV8;!HgMC*RX5@2kA%Tms2Sl)(36a!7-YGZt6^dr@h@=
zj>;*$uH5Qh4)42LR;V5^;Yt38N`gHynM%wzD=x-=jbmheG1AZ!J3q_kVJB1;iWLpD
zBgs2hn8m*F2(7iQ8?K4Sd@?wtUyU8{W%e5xrKGH9Nb~5JQZHY1LLZO%4S$>DiHx>(
zBvQ>%KBrMqj@E|D*ej+CZxc+GMI-dO1Fh&YbS;%cx=0`thj$`FN;ITnxN4DoR3VnP
zvnzu@J9Zq%quaXE3WfNs8Q%Mc@hJgctAsaY`4@7RT%Nt5!s8&G^vAR-r&RD3JS~;1
zuBDT_4zZtQL5rzB#+wZ!OY|&x9<+icFO5H
zk*d3Rw(_-Vk#?w6`>Kd2b&Qqie$nmeF?MoKPq`W7XMRKc&4D|W3f-4Ir$=A_G+eK
zuJdPR*asVK{D6v?NW7z>*_^RUs%W3ClZo{vQ(LdUHP;PJky#?%HHN(Zb6@BcQZ(2Y
z7|JLW@elh(V*O)q@x4>MDX_mM~`0LwEeX
zf)|owgA?zd=X1a?+G8IL61szgZZX{LOC6HNQXT#dpX#(HMDz4jMoZ+Fc0@
zVR#Owh_SSTeEpdEpY{9>ES7DCOm>`RNoZpW!jbV}Xs&kHqQqj1lJa|=U~|muOOBO0
zP#CFRoF`{i9LV{V8``*Te~f*@_Ks_MUN^5>FLthvXVC1O>d1Px6Xyp%S}XdpwJ#<|
zhOS{@W~CpTO!4vS`z76+LIp-T-+yjq4CJIjwrhWceitleu%OF`*~kWuhuSO3hzCT5
zmc*w~jKdtcH>6+}?-J8=KIi-#6Dj2^%ih#qd=#%oI~lz;JMTXkb`B${rQIXm^N3#b
zYV%90Zo@$0w17(r>^s~$9}-#lf?M6)DX6r?PQ0{AyBsC5l^h
zODVRiXjT`a1@YMk=E
zidtuRA|&t9wuXJzC!OXV96$734}ABJHXS2a@2>J?`X?ZtG@^GEN!!l7jK#69as~0e8hW+P<}uo-xKIpS;F$dJ`(xi
zsk%nJa;UU>fu1H!}C}9Fuc7;5hFkxW}sM;&0SHe`T5E69qa%o4o1M-LNp|v-Xz=;Fn&LwQ%m?
z)txnXMIQM(58@5qvJ_HPr!>$YhxMyfNW^;Wd{Z~N*VSgl-*F$tiB}S9KNa!OVo|!V
z>;uy_R;T-1ylxzy3{xj@5VkZU5H<}I$Z$sjc(k!&n+cy_Wdx!7)rJTZ!rJYg=zNJy
zp5?HcZzh7gDr;s!NF2y{7dZD%bp);++WW_UP3@1b=e={qMQjZ%xhYyhWu2}Z&hdZo
z_0B=IJTbuN?!9Z&(;$i848My4*7@6-(jGJ>pB4a5h!Au2zRkCL(*K%7dqvm0xV$a
zOApJ!&V6Ls)iHv*3T}?)$v)h!h*Hs%|3Zn}%q8tbpnUS8Gq%Y%r4Rj?8Q>$1Vzy?bka2>#WG{t`u&%uv3@1TcRPf^C8ktm-^GxQOEV;ozg
zZx(+yej_N0_TDw`gyqvhs_}+#zveZ;wu5J`gt3LDcsTxW{yUqn(M>);DpFh4!OJ|2
z41<1L)GN{-yRWPOnijG?wn1YX<53;+J^5F$)!A@$T>$UU!`=@cx
zYx>(tjbWpn=Kizz=Q6=CJrZO>1WEs7eZ8c}STBmba9dE>ICWNDrp9qmyfaop#u-}e
zU1V50#&SZS6-d72)hrmsrn0G27U6Ikh253YE
znU|SJ6H$ADG}y>VYWYhz|30dILdr9(Lh{?r~nKk}d9HxyHQO7a>q8cLRUOJOn-uXglsK|}w%smZyHQ1QoyA%ut!4c0jV2K|LIH-|-zlGK|X
z_V<5iIUbCwJF5eJb*NyuF#3RAk$+LO_=~J82s@#M2shCXs2FJPkR+zw(U=V^!`KN+
zZ8A_L^L0=)U#mB(JGyI*@0D+0xC;26&zIQH@;lm^c?hjZg1~v*liQcX`Z4{C58o-O
zsQE0sFBL3XLG%%*0}w!7gaKWfh)-I#v3op^F>Qw4(a&5_*vGicR~;bGV?If!30-P6
z!Nc~)(B2opkoqbRmK)8?+H1~!2x!s6s7b$ow^?QT?
zQC}p%E7X-LQ5}{O8hjl6*vF*2#n8hNYRUVtt+%rt{moMaW>m5@^
zXlfR%y8O7-N)9~-R8jFoL61oO=@vC!q2Z#0w1-&Y^Aa}%O*X8OnE2rpESaE5(Pd1S
zW`(6s8kJ4*)HF~Pl?>*Es;Zwxsus$+3^k^Le`UPGBpJ*a|3lR-
zN}T?s)bL$VIZuHqWzZ$!hyFAkQmUTFAEeDWONEK&YpsQxm@?dz1)3yFa3J>esAiD}
zD6G{b>V@}=GWc`?=le^OYOj0My-6c(_xcoo(7QjF^*m4hGfbb}srb^>i+wQ>s
zvH-g*&UHMII&;}PB0!g~b8_|K>I&)8Kt^{xcT}($U_&a%qIR(B7kYS(4*Y6)ZTS4-oZ>Uo~1q1}QmBUj5=(Ua%q(M3Xes87zk~S#Jj|e%gN%#h1WFwrsK!_pC{){s|rS1pdLa>
zpcVokzyOOhQFcU%Ihzdz*N8p&8?ew@C!M@h_Kw;*s{(CCjt=8?X6kaxcyL?j#GeXUdf8Waf65JN=E*v~93=TO!9nBUT+^
z=C`OH_!pbjjexb4Ag!|pT4G(d`Hlv^?J?jdA9@Y5UHsu!`&(M^BBf6yV~(>0CL!E1_{vW#8m8BxuvP?8ni*F&ljEZ&h^
zO*3FNIne8T=qw5B9WaUl3s3b)S{-v;xn-^g=PbEp?$Z$FRbQmP8-KHzgKN*iwdSUE
zu9?LCN^ef7+T>#Bhfeok@0R_Yt{E#aM@?xdll+sD_q@tJTxhmpd@%)o7IfYDp@O!JPfaYijs{6}@3ads2G)f=HrIdSgO0
z`-u9jGxdMaky?i8?K7#Ff{*EZ5gN6Eh+acXr~AX~dC6|kr3rP*v1+H=e}Ic_r&g?+
zZq8hRU+;RD_FV=8kHOF@*mTt>Hm%$zeZf_g5r=42)M;FOmF_cz?h7FqX#W*~Kqo}#ADR}(IvZV@9rfuHCj=Ku34yrZe|(B6C<93cC{R=lY{#
zg4EM9{~U)K{lQPxD|S--xO-B?ABt$8w=blFTU;|tbo;~Jhd9FlW>%NBms@SOHf4D?
zlzAF4ftvD+=~5OUbLm9GTCb8G69Znw%;hGT^AUMpetI*!u;a7=^MAq3;p?u|$d2zaGyZd+4X)lxR&B6WEom
zSf)*n-qIk4(NR$F*G@D|03EZw$g^Mxafp3^Rd&HQ?lE|z?br7Lzw_0>c%4&lWyQii|sqwygei7k#
zk1cP8p>OQM2E+|GJlbDsv0{K>VB*I1OA6upoeuLma&j7M*Y+*|SOD*v7;P4}Mn7N%
z>ZhX&fM^8Dr^(#6#Y=BnDcVW7$p7?jFvK+BjLVpN-5!A9{$RFmN=fSgHYN
znEA|idp~*zY49%`smLEnP`f#3An!?&{S4wLQ=s&q;Ial%)PFUz>VWIvjKhLbQ3U;u
z1!>UL755^9+wy=$kccxaC4=bUr24(WNcGi?$BX*W5h)ZI+%ZCT5&ocwU~r;|8h_bY
zhE#v>LmiDC%+A23o+412BE6E?aFjptY@UP#o_hqUdQSEYkmJ<}eO2C;y0oRE?4m<$
z^i9`8P|Ima9Pc>n`hVbpUe@;!nwlYg(%6`D-(q-Q7=6Ck|6Ltr{uMCVM1?ZdK#@zs
zQS4A4H1b^N&1U<&?aoa9t*booPR2BH13iV_&h)$tn$-51m7=3CZme4d?W|CVYqnrC9vVy*Vli>*~_QFwX}P#DC;r(ZN88m_VFjbO%?l6%I~*3Q@L-K&>GmRGuCeX
zSr5H1yg56~Pwcll&CmJ%l;gQo|a6S1E<@)Lum%{GH6Rm+xm@bVj
zN%FFamV%WE{6(hFg^UADNiM8+tE~CG+Pc%T`vH{n$!JM4-sbvbzY)Orh40BM=q1;pv&e^)E9_$@ZrX)ehEzV6|$A12js>@Uxv0X
zb+QP!YU6s1f;}@wL9XG$0Q<->(7miw81`#Y9YN1=9EH#^(4rV4#{=*L{3+wP$7E@?
z3bhYuI*E}~ZG>pXHiAy%gnLq8l^DI*FJ);u3U8c*4F1#)bFv6Q;4$Ndjj@@-0H^={
z6C(k-pPR7_`zNFCrQFbAz`QsEra$9WAw!OSic8dTaA^hnVUo=AMvZ4^)=*HOGZgNT
zD2}EVZ;sA_v*5{qR#*l3|}R{`LDVjhoBsk=w8O)YsIBF!;jXrCg3|B>Zu7mNbU*Sd-E3x)h<
z?)~tdJcTryGv4DBS?2Uej^(J}1$n6(+BYAt@bV|JNmu5;pGtm!ddpx9qchBb9+iKQ
z=1!tIV}f_hu>G}O`}4|)eLIB^>Ls0|Tr}?Qsd5};Z9X-`S|%DSWQkPmi`qm@QFL*u*ofu^vR!GuWY~_XDbC3c(g$UAb-k*|&=1LHKO`5W@Xsa2?8_;?(|v?d
z$sEA5DmyR8tK=TDC>QyW7vaeKX;UYKbZpxXp~&zdblLs!rjrW_9G))KTbXdedjFj?jKN+&Z#y
zQPTSi@+dxQS6bQWHG&D_#052^f>q6pi5|JQeA-e{ZHh?D?G}rKgT=tlCDy7AUw;Lo
zI_e)+bEJnialUVH<3GdJ7s9LM5B|mjQRxz!uv7D^%h^&*
zmZEtK?<8vMOumWWskQ!z0L0DM0e!phLFaC`n%VC|gl>C&I@vA|k|a#IpF3HEfm^N{H2tN{cZWFz5A
zt))N>@(Ncf3kAvX;P&`AAGA@D;_n4u&CtT$cC^(Z
z1a=OFKGIoJz&u<@hXy3;a4N{xQ`15Lv?m!JY4g~yHBlNnQseZlD?>aE8Yw888HF<{
zrj(*ub=5m9a73NiM`1j514-$Lu0EVzjJQ7-8oBt1!qq!rGDc9_!8
z5j_ljLvWMqR}O$UB-cXKm`sRuBu@ofaU||ztIeMYtQ-HtR#Q9@SSRvHUR?K9Af?^q
zRg;(q>qw6Mi0n=>uiD%fs+1a#gJvmraqYK`?SDu3T&^#Cz0_Omrxq9jW#O|`u_X+e
ztoKayDBqX*!BW?g0!`+VCtPYgku?q)5-vi=!SbIt_8{AKXRr2zSfAu5Um?)5X`W&>
zlp%Or$wUMvsxv7l){@XbN$E^e-;(7sU}>S&btX%Pzrqk&Q}bkeq%ZVRucAP%@URL?
z?f(#n24(K%0P%`p$h(DpKrqNc|tbiuG~Tg%1SU
zaE0y?YK@)O$imo?i>))f)Lh7g3Akpqt2l
z<}afJUSt2iiUGO>xU=j~>j;6O>A6xl%L`z9wJ`LhN0h|qDcvSXp)
zF7fD;jlL5NBkcFa48L1tg3Q^LI8*nj%-52TK}kF2^K%D>V3c-{EdQMFI#9>=g?0Vz2#f>KGh@u)HQW;_`
z-gBpLUJ8l){_v7ZFZj_?m@l>WW8kwy>?z+1pnIYDhRgo|ojK{zf(kifz>VQ=QDb**
zXeyqU6y=yv`IWBJ9I>)3Q$P*zBv59gqA0TfD6+z0C+(!UL~l{g++XWOIeJLxYGOT#
zWQD_r-rSB*F6J~J(lU^2m0utV7XVC=IO;KG2k2la#&erco}7xkcs)vF_6cKdZNSB>
zx@n^N80cc!kGqOl1x4G83T!a=fO1I@4XD7fnA$|ZTDrM_1R46k{*NW8gHG{D*Bg;R
z?s@1~$3H^$bID!NMdItBdEyxXg=JbLhH1lRbF*BEChiUC7)7vf(gc%?GOUSC{sb_+
zN<*&7rZR09P{zz17!8Q3MQ;>FJU-aJsOuk8A`Je
zuyXQhkVB*IrOd3|`AH{nS({sPAZ2eUfTcmFB9@lOA=hk`LHJsafp|eNNd3mdGBy)Z
z8e38#rYt%2%u)u!l-zCa1}xh&bm{*cA6q#LquXu*)qA&tb~bzjWK=`Ce`9fsgi4
z%HdUZkmQowM{=4UARQ$Srm@voUh=7x@?2!bfJu5{`lk(e9i&L3k^69%EyyOF58Pe3
z=pBLL?u8hD`>H{^918E
z?#xM;iD%K3tJdH>;ew7Ka6<(Ux}bpMWd6LnlwFj9V3vnM{lJHCaS!fsr;l9-ASgcK
z-XN8m)Omx8D0zeHwv3sI(_tEj(_#Fy7v9x4D>;*p8CR5WD>WC29YS$+8S#RJ8NB3k
z*v%2+KWb4pmlZp3!&!V;7LuPG-F%{rzKl2qm|j*7+e#A->mWn2Z)jb$P~^RmSec{b
z7B}+!_(~)e&+_^0-4sQuJc&Oh?@<&zr=(&DMjUoDj9wTxldv5dnvM^KOHL59C!2)t
zWr-xNzovK`MyG#CU_l(J=ZT7$>WV7HTkyvbyg!V3jE63jf0cPYTLp
z+DKBti@G8vSL#KfP=39luvB*4jVGuF=(DhNOftg~+krogcHS+P9nq{R;a&%0cRu!S
zmy{sV86Bt!x%^qLiV%-pm9s_7K5dg)2mxpl?0Qk`UTINRIc1wj;hrg7yltF<@}5O!+=4l`
z)lF^+ep_R^(|~}0lc8hVcFmq3xm#^aox{tyR^Rz+sNaQFyB=U>Li|e7q7KFP_r#gg
z1L2*)r~TD!!tJ##@YFPy206RFOWLB332bR>)ZZH}{@C>OPrFW=XZSJT19LBpF}7c#
zJ&sb|0>$a#FObz{*SJnrQKnkh0?el7j2@#MzPHfJ*N@=B92pUKw%GV4#VGxTd(u)p
z@vwGWO;|cDFW{7a9U*hHwU?_)_)Csf9HUhnniy1#7X$s~QyJ0^d@Fz?#jQ@%FGr-U-wKWz>Yx7|S1L3eA
zr2r;A7$vv|JVkpBhFjY$n&HO9_$1=I`3Oj1@AN~Ru
z&KswF@6F$~|F!If-mk~>yw)BFnml=z=$%B+M^!%%)`8ntP_fZCsgt-m0%b55tVJs^
zio~n~b|e2Bu*Y-*_fnY1SmKmfVw*mPUi3xj2>kk9h@kpEAEq=n_qi6CT|0i-!*Sv_
zaZI@`hb4Xf7FQo&hfIB&IQ*8sxxSEA*%3qjHv}7jJn9Zc`1=oi0d1TUY36hKAJ(#>zRQ?$
z@vsOCFmBdIUm6_0^I=ELU@t5w5cOYjy@?N|hrgADXDz?~^AH*M!Fh6-qgfM^E!G^F
zA~3JmZapaCHIyjWkkpLj*)oo6rc;|0Qpg4|BBA{2#emFD&?_%B7b^2{T0DP%xyD#8
zNYDdtBkFFAPtTsEAy@g8ll47WIWm5o$X2_J-hg{r+15`nb#!adtt?zvw!boE(J`eD
z4>D<4@Ah$7=XS3eCk)A`e!rGy*Tl#dG$*-New`fdcXkpG(P$5{(`fx=qnQv@K}n;0
ztCgio7BY)AQ>R1+lr^@_0;el*uG~}F?zLrCRktu}f&`YQ3m=g#yeAx72~2z2TNNc0
zLSU085V>WdNJA){nH<4Vu@-*-#R*huY68;q%PqtFba8kH4Gw>;bYnOz*iR@i7)&5D
zDEu@*WHTp+E{p0ct>58YE+#!52GV&$3|JdtV|
zTrjE{=@BTFfA_7bj_uyY*V`lnJ$-HjFe~d7=@gsC?skFKUD6+C>d#;A-dxuk0Nk1l
zk4}7D&6!13^LmxYCpl3YCBC@u9VJK0Q3-{iMC77~lCn@_>BAWgPE3rGT3peJWWm9X
zchZ*rJ4rxx|HS~So$EL^{S}x#pbVTB?OYGcwMQ%uWk4pKg9t-9={kLE2Wt#;`b>Cx)rnGPyjj98%ewwU&PF;dF}dho}iy+
z_fg8D4fmTmU7+@7t-TrWy#_b1tNx#8+9CI?&uIwPp_{lr5;d`Up1B2aZqmdRGjMV#1}pmC*%|S1CCPsHoL$WZ;{&
z_Qug1*Da~J!N@Q`-#;G`L>qAB1LMMdxQBPFkYiJzYo+>B^i+MqjvVd^pd6}CL|f=B
z*iE&-dPs;FFTZ4YJ)gZPHKCwVE1=qXBpLGfN3i9=Xn#PCHH49rBm2j>O0_N{C&&3x
z0@g&B$c!oiupI3!mg?tRno=v1)ydPNOrIAnFo(m$DzLqLviqbYzN{VdU?Kf+od5|Z
z|Eizup+_D(T)35t2lR&q9R25X2?6g1WNR7~uh!_bRBuJkC&G2^r@SO^E1KT+SfN;^w@$^myUdTK6z2<38+j%
z$m15x{i6-5@l9w-P!At??@d=N&ua*;Ee#d4K8Rwp)jcMw55DRX)7#(PG0~CZRCb-i
zTG}Y;Jp24me3}JUUZkYv|>E8?0$edi(q<$lB`ue?kovY+Ih>Jv7sTN6QvLg;eQgOQ&Sf~b=8bye^ow@mhzj?_RJo8WC)#ZbRfw+1igxd|=;Rn7+9O+ay18kW5?p>4RT7l+jR=
z-@$PeB#bZN--3wlAf?d1CAWSUc}Zz=cf{2f`|WEYXGt|w^+(KE)~oBu^}V82+X@c8
zuq9}nl%Z|S{$@rMDIA8SSI)Dqg102(C2)kYHEk}=!;nx?lQEtdZRo`3L+@;C^3&Fw
zIXMRxBy$HccWKapWcN4Lc(-l#keA6NpjjfSm21h_?Wljij7;a*t*onQ@MH*hK>;Q4g}tw28e-m)Rtp#rqGLVY||h@zGFIv{Gi}eZe&_@vMNLF
z&L$B1qQE={9i
z`jrWfF_c*U8P14V07GOQXG^kSdu3+CNXjXe3&j-*e*fmyrNf_VyL;MjwQtFn$)CxK
zuJB8OZ3ULCRMaM8pO7jEuRNv{w1I;Aph`KYNFIU~bt!V8Jvv2i-kR+RTwFQ6s7>fn
zNFSjT_C53t+p)NXqde5I*#&8#216n*gFBY+Mq5Qncek#Ily#r_{gmjbI
zJ=HVdWde8U!a58N{sXC;V?2{c9f+?>qi6JimkmrEKoV{0=R?ELS|p5pQq(B);hiey
z(1nu@{6chRpcwK{8IMPQB7^W2hdBBz#^J3F9b$*mc^4u9l)wTCLL2wwbuNc_T2D59FI_!UV|>gnUf#WQ5BSmt|FktCM=
zuPBmZMh4TNJBLXpsWpRXeGOPX89q@I`tNl~;@Fchx5GUz)sU1^j30wLWaGdnbH(*i
z!?p{bS`SRwJ%eiyBylb4N$cSz(Til$bx|p#20ja-M&5=<+Gt6><3z0VD>Mf=Q}AS?
zVuX)B1B%Y?Q=NICW6db7morsyaYa@93+CInlfdTzv@<;kd__a`dQ
z!yJo7H~l4edE-k+{=(ak>t3F@vS^*5G_ZSQ3W#GN`C4t;)9lEtab_oz@_(Oyjj-)e
z2`;`by_szZ7cMHVef`8Y=1hc-Qo5GcTBee;m<2zp$t_vI6enb))R&H0oyBvZPdBOq
zlJ4fJdOhB6fJOk-izunT0;_vPfOF|X(L(m{dqqZYm@n*I$`V;-*eMLM%_!FUpcs*O
zg!^oh9nXa(Bn)mo10eP7IRYT`gP8>K%E@sCZ&d7F&YUPV2bez~8geq?I?**@>bta@LtPTRpK-c0S4}4f~?(i>tp|-3zNEy1-R(KB+baxK?VP#ZW^;(
z(_-b~nqwZpNGg6*UTfG!n6bs|;zlO1L2tm0gg%#o-@~ebg1_NI$?z}gizSWWy^}b*
zIr=RWtq7(led|coO
zC^LL;lI9Iyq|yP%P(Kk#Z%v&?pvdzh>`h?=*A5nr2I?p$(4W}MCWfcuv?ev+<&Pnh
zm6DZ}QNWDkd!)4MiJdcJbxwIgjOslhLIDdtRo+WwJSDS?T!%pP4(FP=&RR8ftm)O0
zk>w1Y+US{DH9i+_1w*1l6MN;+A%YQ-8l27a^p8ctUg5jt99?768=D@4+
znXyJYEL{Ta;cJ28@jXn%I1(QNA)n&s)3E&uut#V-OjWF=1I{SwY&XnDXo4AJLF{xh
zgcI!+ggovWpdiEBP$Z^pEQ|KA=!*_2+Y`zz&-m_0sP1oIXhIUIN#}@>0Uyy1#F~H$
z?->?xL8b-^DxsH!yE
z`Um@uky^c0HZQi0HM<+Z#>UVS9_D$=Bq^fo0n~x8T?u6!+;BB}8SI+mbVr0>~5;X#BXQzwwVPyt7?yn>kK{0(fY>w2I`K=t-kU~EZt5Gw^@6<=)p4j!0NF&vff!3?sVX{U4y9Vt);tRk8W$~}
z0iS{6eNU|_a6zu29~^9XsbDFtVX~duoToF>S%GD5kpIJM>pI=w=}!4mWpN8jQ3*~m
zC&^C@wj|j^fguVia)l#_qMN)MN~QwW%ehm#QP>_BUtYWKD5UZ_Wt!#BKfyU7E&Xxv
z(@mS6Q(%V=Igb^t$xcMIRj=ak@s?)ob
z<=Fu;9x=Qa5g$hx%CxheM4g1yn!zERd8RVe#{+4r$D)J99JiPBGucbn;Ob7VfTSl3
zJk#b*OeIW1owfUvq@6f^Ngm(qPsphdKMB(OyWyL2DPWOX@~Rl?VpZX?6;i?#iZYTk
z7Q%NCe+n$a*??rw@+M9v=Uvuh*r_^g3sGiKsmV2dweZEiC_18I)oB3TrnGCivKOFy
zw`U($d&jvrl;YY{X)3HrSlYF}&ET(gQ-Hip5Q{$D=Fnu!I}ufKB~_4KG@=V1m#^ppnZ+Tj?)(3A)Y2K@(oe
ztcoDYvzS5Ue-X=!Ar+`
zl>28V^0VTtQ~Sk~qgxyxPF%iwZ$KY8=~*2|${4{{Ei>j5%dzE`5}{|}62
z$8FiG1Yg}k$LpZ%)iE;ntE`uymE0b()~T(RW7$raoX!+^mr*6_ASVSneEk6PhSvZX
zy%UQmGFJ0|J$!JZ#S$x?_rx2LGBp3Zce>luxfZ}hp@mG4a0hY=nhN
z9!%vlFFS(5aSPlO6!jk9pnSR&u@EJGsiEfJmwdV__YAh+ReXk085UOU>Z&1E=jQfn
zNh}#imy@epY*i7GMp%-RwE2U?yv5Rg2TNn*g^W6Mx<0fkiADm*BH#20#2zjfkpmmf
z4^i&*+X^q84EfCH&u2NnntLW#uY$8znG!#nzgvto_d{g_CtSXrB4uoJB1xjT$p@Bi
zEnImzFP`ba3g~QcuAcZBWgULrPwU}>lOcHBi$y5LmG<+?ip^>DU=#?EQ%y+)50B5=w5on`>vOZO+O1DmWtF?FXZFqNF8qwK~3@AM+?I0J6%E~N%Ry|{cx
z_rsl$T@;%WROed_nMsL-n#Y!RB0ZFF2{SZz0#-Ds&3GH%;-G3pLhmH{$aWr`t%Y={
zlU_C@B=NP`bqB`!m6vZc-?kKbN-{51L*$M0r(A>7%d?Et7vLVkOP5n#Ys)T%gYVDR
zN7TFOo?c(e7b4AkuHLrVae0(H_xKcoZM`G|+-n+ueeTrAN-YC(VTIs
zRj!;#t5v`^rEY=jCC#gAI4fBY8agePbB9O;@rI^ZM(BgNRb+6d%@%7ormUz_z$f_v
z>+}u+FW|>(XxC?)u{tiq9J0=HXa|$2UggP1)Grjf?`1@a=ONaodh1ENSaReW7`
zZbByB%{q8CQK^PgM-Rlkbp<*0AE4?HYt&+896i6T3pR&JaFb}`YE&^o}liiEz$HyZ^;0M?h~
z!qECWV!+`Hj*q94bQ#6p&2JhoEzuUB*AQ|1shbS;Vv)ca@SRWt|33E3ph{e8;wycd
zz0|-a6C=3gWN#{Pt8*_Va4YK1J^eN%Fn%0s1DAu4z|R!dTKn=>4wKbBHbtCDTAV+%
z&DN8B>-BO+`Zif|$NDx!z7XIW%7`>XYmE@gP*lbs)GS^r5Y4w;MC$8Q;VblFwX0J8
zzD8Kuy^BPq2~3)-u!+%3Yc@nU9pO0W85PK3tacVW&
z6)AUACHahi!x-jg<#tE4V@jfPF^+n)S8gM#b=>DqVyi>=@y~lPtGJ%D)$Nki_A(=@
ztHGxOBCA8YcC(>XuKBu9@nsR=ZF8G03mji&JdKTh#u2-TVVoY?cjf4vC9YM}7p0{Ug{5B~Ep%e+fU`DLi-vhQ_yjt)nO(
z&LqF_Nx-`9N-yYL%){1W`bSAR$_M>F{jx1pVe|(^ls>$4h~&Nh`(_Grto}yrBZ`-a
z(5IcAfKWAmsYbl`dJfm;HCkrTt{SPlB(1Y&uq>;_9BvLtwwSZEK+qEF$B0(_8ebNB
z&oakOEUHLsmvvx)HLW217i^~l_uoR17qa2E1!FZL%=9E7amAV
z$A|Y_dNAa6&?A|hKk~c#Pk!$I$C3EfCtT-2*~Z_Mzm>flWQC#4rG%V
z^z!JQXwZS|3VDy?77$fJ88!yN`7%$l8b
z1?~Vf{&Q&1y7Tt<@QZwdG?Tq=9%+wuCJ`df9iT0pa(;pRXzFvOZ<4_N^Bla7Q9ax5
zVRCbE<
z;{eslM3E7{E%h88bS^sXma>0EVaF`s_s|4yiu2
z9{46_Yd<;;V@5hrF4Q73?}IiLuD0I{_P%O})!aI+4>!H+jqtC{Jid&?NdQpglawXP
zFH_wkO44VfC>{b6CdE9+3zTeo8_1z)^@bXLUifln(A9^_@;nV9T(=h_az4AE;iCZ(
zR2J6Wjl4fA9b~Nw?F_x6xA#rYZ#q)3HbuS}82B!Cv{CU-akMbb(0nfZpZi*o$+R>T
z?y1QcnQV#P%(A`V8Q5*Yp4-dBSm~#3W`y?|ezZNp`5MOaLuO_Vb5*m7=i@4s^cK8R
z2mE3*n}@|5M!o`%h3kmZ$-LWxRS))M#0aa1rLDGL;r1|Ut5sDsh~0Wqu&Ub(YwtE^`*z*D2zXM@T5j_-9$kfCoq9}9ANvz~>%FKHtRy~$
zG0p`TmfuIfL>-R$^z%IEOu01=f)~^bmNuQOf6}~CmMc2qtj0furZa(ToUHjNSqU&T
zWq10(w5XRNK4PbXZqqrepaZ2>4m5yFrPp^QTrrNwvSP
zi1ThRg6voLV6G8B=Ov&Q!!_rps7G0oIyD7dwsrDz!}*6M3!`}j6Fiohr_?A1W<)0&28JIm;h&$s7Td~s(U{2a452v3+Ui3jA0sB%WASr{!GFVYO4HJMv
zYD(eYm%>4>we@j+b4Qp3tZOQ07@P>^R%Qq1UG>{55>(ett#!jCaN*t|k@0EQQ06tD
zJyWBF*Zf?He(qhwk2nz9A!5t43B#^S`H_C~}#~hEE8DQf#mt8Vf<70bF;NYX1DyNvK48OJd$ymD%YO&HbO9
z)A~rRMvXJqV9-C`G27&b9ETSU$uQx&+t6-x8UtCT^k+2D
zSgSN8X~ZAWFiO%(hw8t!N;gT?nbh;9e=-70!*9q|To=xFa3_1~fYMPFK_W=L1GLI}
zq`UVlZR1KM0}7&G!P4Qn!L?k0)tS#s5A6&_kpVaC{BmyK@b-1)HjAZ{B
z5Fj7`lW@gEY6|wps_d0Q@iFkqW`#0NapZJH!k-9BpwN)TF*M;KomdyHgaNzD>xZgS
zR8WKuJC2wcR4IU%97GlA$L^z#ckNGjHk8-ZZOyMqLK9CjtEs{yPapkzGt-naN8FlL
zMjg7+8sf(1?OqWrsYZ<;VhMHFpwZnd2)n0G8Q8imx;aC{H|I^I4y3HgJLkxhhYEI_
z6{Kmd;i+^evYlGyZ&o!4qHKHo-_+6p8)ncb6$GD{<9R&8{32c%i_oy-
z|A(z>3KAvOwqx7I8Qb<5+qP}nwr$(CZQEyT`^~*|Ki@~XtE;->?Cf+_)>5$Fg)o^u
zrsuJ-{xF?RpEa{s%wcLR34{~ux#7nZ55(R)J!j=n#fWdB&8H
zJvS9A$`z;#nB$Ses8+n4Rj{;vOMD@#O2;Qv%Z4#mP#Jyd;UvJ6ky~SCL
z7K_xB3W430Oe0_(UN>RnO_kYEASq>2)?7Qpw)i##GptJe*6%T&=v5z!ft+t0xtD8F
zCa!N?lBu^&1GZ?>Fxx23n(PXZ@R@a8Bcu$#ad+j@kmiM?+O9v~&|I&fV98GsoP&Nc
zza!fI8Alv%BNi`KxmDHmWbeBXtnv?bi?X`ZpTbGBKIzo(jKXV)v@)M{zwxo7-uHH+
z5z|ar&C{i=F!PYL=vZO#3<D5o&U=U#{`aC|r>tDl5t`|W4@uXD<1FeRQr+N;2#z9!`ykC=
z{0nZP4>3(M!u*A+jNb}P@!VBzgMr1k^)8_R2WCGfCS;Has?D7HfI42K*Sq?MhHS-F
z7yCXl@AvjH%qCv5+w1sN)(7gDX(##d3m
zv!HLFsoSx_IhnGJLoH1y^{|woPwBLZwY9rDS9=LwPFU(PiZQLTp-VH$5sa?IR2!C7
z;^;*ZYqC(GrR@NOWY^grn7b0_hCmGv?PyOxvi)T|BXDzg`k_kZF}TemZ%+kHr$Lp;
z>b4x*Mk%%G7Lih@2XSwPDv54d>cl)QYQm>8nXy=~ll48K5lOa1REXgGu#~irq(HIkO}0O;J_xu$x$kfG|je(BxQK+GMl_aKqJ
ze(Gq@a5k~Dm*iy!efOoC<;>1IKX=WJx8B^v+!Vh;~umFvxs_)Q6_QK
zBdM4gbZMN~u33hKm4-4f+#qHc
zspi>>x%e*ORL}z4z(~Y4aE?Fa#xeYSf_5edBVJ>ce2`O940^&ztV~}+3=Ot0@POi0
zV0v1oX%iem95hh1fo;n4f-a5N*WRyH-3*1@qMx^G>Ddh=!qTI-lbStU>{;XHpUOt|
zAOk#EqJH5M+C6M@-iiN;eTbYFzbV?r%Fg2xSA=DtC8dh0V^Y@*svUoa2}FIh_2A)a
zPH4sk0~hg0OvVDEN_-lt)j1TJ!j{7ShfK}iPw83@kCGo?zMwmyT)?(|cIGyBmD}Qj
z8!I!@Vb-`*HOw@J-pN%nbmePMq2$(2)AdiXY6j((N>r+wx6B-JDOB;cxyWj(liSwN
z8#*NYVgLBDA}<(iYLNM5VoJj->@_;$Pi5C&8#X>Q9BB+aYZ~jojGo4zkSeyhmLfqF
ztOc8tlQ}%i3XBDdl9PEdYvypqAjLKnMS#j6|3fwPQU<~LAXV_DyfZJOS^
z9=~i8JlQ!VsVi&rFwmmN&_1I;;X+l-ESLbgGTaN>7uB>?3kx_sJVFA86VGh0+
z;dTrw)Lgj_jauiqI#<9o^!#d?=rlb+QN=np7@zW(HL?j>n$k37bfqDOY5|rUv
zU>W;;|1y$7a*KZQC=Gg4QM@P(Ps$kQ7mUb1p(`0sMpsn&VuGJQqx;VmU$B{7H`e4l
z$_?ZfqE2q^+@H>3dJ4x=y`bl&v`SJ3qid-H@GW$p$j*?g6Vu&A%ca@j9h)!jNsI!i
z)4}D996l<;O1R9TSI!Y+1vTm!P~9@AVZAabVnEr{GeO#7dCjBgd*ye((2;6;$|Q?V
zy?1v~1CdGBPO7fXY22}ql=Jd;41iY3OVK9Ei_m&X?9myEg)CSjWm6mm$cqyOuLFndXKU?CAt8>6NvJYIMNfzP8C_mKOanKacxc`cZmV)(~U(%40IC*tSyU
zmAu!o4&qvxgvh9=1S5`_(6Q_edW%9hZzp7-E#n#3Jby5g5i56lqEF
z-OX&xePup{6F1cE>6-3KVHj3K4>2_N*ye34+LaZepXJ3k*rjZJ_suy(}mHi?s%OCsiVdJ
z_}%{gL3IWH47gT1IY@ngfN_4rVSlchn)w!63zGFilN_ISs)z~c
zhNnymU5=0Y#Q7G%6XKF1I&F6sdbb2q&7EqI(y*t+hzKD;zxr_YNZ9!wD7Bh8ah|c?
z>-Q1HSI5kM#`;x_ZvJ&M%Y
zJ&4rOZ*YFng%+42dRn2AA4{;(-7E$#Fn}0Q^9)U%4njO|CA$F$lX%=VZZo^HXGvh-#?^1!OT)Y
z(B^6wr36}YGXrflqj_0C#`@G&CBQMp&ba#u&^Q6zGkA4R`n>9T54F59QDAWw?E42k
zZ{8|)|T%d`^3ocf(gfgF6Kk46FH1;={22gqE{b(_iXy8?cC(9_g
zc4EHQ6h-=Pev_T?n;dS(T5_CA?Fdd`_5Otk2tObJ%+1-Njfk4g5;MEp8~2pPz^3<1
zMTzrhF6@!gzTR2w{~YfB%aIHWKX>Ljqk%{V&$KSx8c$4<7Tp!5Z_gu+l(2#A&a4NrpWc=@ZqOj{nMU((DdYGowM~o
z3HJA+w4KcXt6HMgSHs5i&w{XuXi#KV3`8mYrqXj)aJZSQz6;Td2VynF6ltb#=-(&u
z3HBJ3M%i41fH`&-6yAPfQa6nhz-%;QfKp*aJ;xBRnLjHVih7d`7%-(WWKJ7UC!XN_7}k
z7(t@*7)o=HNTZt!6DNBW3YCm9m%R;F3Bp~Z+=&x5e4K^;@clgj$R_^*>uZO_i5sCv
zHCT=#PHQg*M;5#e#{ljHM*(gHR}RwV1enecROhXc^~4q{>@9&zzrZ0;HTA7cr*foW
z*{ctkz{yt)lziVU(ig3yJOQYrJm#;cYzCetq1;lzluvtx)I8IMz^Wz{w%hiB1h*p+AAjXA^v$hB=YW(KhlWK*
znn9B>J@)MR&<=}%l{W?b_V@tq@Vm9;^ansr5*P#p01N;E0M6E5?BetAtTq!60G0_F
z00sa6z|PTG*WAY3iPp)`>ayF~6-&H<_WfT#
z`UBnT7E$2+5TEp`oS?n49g%rEa;FLXE0^!H_U8$IezVNm!4BaH|0?(V#^uL?KK*(0
zI@HGSM*DGB{&;a`r&6W3q5Vmh?&kXwoM(L1Mx>C7Hk2;v1G$R>OZ230--)}UK9m!`
zBl=mO)u&ytaZ4S05PH+cLn&4H=S(?Rh@pN)uTm(J<0+^20A!JHQO
zzcE$BIPPvgpliKnxw63@k-QKGXa}ZlsNOwzS-PSp8!?kUKL$wB6ybgG*Z^0^LxV+J
z*SapVwm#vvUymL5(jqU14?arON(H*$=wFCCIbYQkY@Te3HGb3h`5OLZ9|Ly`L%Y0R
zJY0gm2QH;MPYih&p#wyC(-DdL1Ye4_&s{d66@(NSe%(_AaJ_6QgqdwKY9u^uC}5!_
zb$Adj1_H2=A|eAYHBErU9om)}5TPU{&6w^Y(vp|MePSR{dl_It&JV2RTUT2N9Jml<
zKU5C0=2VY61CS2<7y^_UPeBN=o*&0U_IM?_f*)_b^z)DTug7b=$AjRtfM9*~W`&D^
zfr@Z|?JH@p6L}(eq~O=;zdn^pEtQ*|$q}#B3gt?zF1MowK9wLhXNBFx&OOmCKSGc3bAL=k+-X
zt_43%O`%NGq`%H0(?Wu7cBb2QJLg&ie<6BoXn8saDg0h2Je22^gy)sPYYJtxq-C|7
zOKh4yKx3{@5Dr`(aZ=30A!Br;$c_==ntyp{te?+nu-_Js0df-5ae9kuL{Bavl
z*9h;)3G~dY`?B*h5i4$vyd5FU;%g+jmxp>fum!q2I;|#$x>HmfFU(uvVtsAQ1!T5N
zRgH4Sy==Z)%VM|LG_;R}zX}t)B$jIV@43Re7!u&kG?VN+wzj#vb7G>F
zmLdA!e1@?RrEfAsNx73a9CK^Hf;lci0YCyjj;5EOV(
z)2tvxd2#N&TdU1{-wFam(b>`R3IDvff~k(@WOP*OcYG;j0%xn-3O{e
zlgG+r5gw*-`T0c)WZ{rNzNZRXHZOjEsa|7)uDsrTVc7Q(k;0Pg{bv
zc~dNCfk`egymX)E#xGW_!dj%FiK9@N>vcKKQj$Xk@cpBQdA9a(N{N{g#NbdO)lNdsS{K*;jvs5PpbLu4$x
zoTgmHkq&4_NosnB5=oH>EJDzNb*EQJjD{HNpLlQZc@wo%F_8s96b;#SPk5Y$i~jGE
z+8S^HY0MPOZhEy$B@IM*J32#Wt;M3KQt5v6F=4au)-&C;fpK}E*Z6?pd`JNk1-hk=
z5KR%R=d4*^Zluss3gT!Y*iu6o9j>gW7(dN$%3u9{zYUmkRk$*5vN2zNGkwVWlTb7?
z!rjRsr+doNYf)AOY3km7H<#HNWRlBm}){4uFyu_qFkD{z6XhQ68K*;YexAVQq
z#7QP&6G01D;%{#+y4h$@3AR*8XgAU?0{P6P9X9FJ7~=4^wRkuZj!lGqxZ$WH@Cc_(~=-*y2HU1;MQ
z{%gK5UJ6x=%6HlxmG@0^jxWB%M>$?9^aVxSOP)k30a2jiAG8kT^kb3VbeXs7OHPv_
zHGHvPq-*Wo9EUGK^yegGA;=h?3+kE1N(NO))w>s*2bgTU@GuumLeg5|B@?39y27kM
zh}=3+IPtrCNbAw!;pEHY!p(;M>Lg1~gFsFNuH@~`XHids`-}}yDl-3VI?#N43LdKD
z>Jjgvs}rOyYzhqdUhl$|Z*SDB$pLc|zHJ0`)Xt2KX4#QvQBX
z_BSCs32=|5BGFuDpw)i9M1O{gp#3BA6*tm{yYH6rvZIgwP^3;P$@Z%FO+7_O^R!rd
zF$Hm{SNMx4{9TmfO*z1vaGVaRBpm5J(7ZO_Z^Ckb`MN;whu#L&YMNoPV9tGv&f5<3
zTR-zK)jyHNAQOCEC?&zQxjS9*jFi8kXJ#3bPGD|S8>}>Tw_hbmF(p?^lr^KO0As)w
zi!DNVy!51r@xFQ)Z`B#p8`o7N#0ZVDy
z&!skpd!rtP&EEuffQ3s(D@X1`=U#YH^O?9j0aTy4k^WCHCfFkTLX|Kdr6mHCfU%q(
z97x`{+4;r$!7S{$jHp`bE!9;uEB$mj-r?mcXL04q?cZm46Q`kKWW_&B6?s3O@E!jG
zaw}h_^qzdtuA8&Zin^O-Tk6WH4Vmno*+V+c(p{`W`
zn9pxw?F)tZ{e-coIKQ4e9N|68Hn}HO`FSyXYedgp6K#q-W$~}7alUK*-Mh|-{TVjs
ziT!8rEi>|I^2!BpR{qA7c3%GG=~ChQ;A&S5`pVTe$2PXR5>y1@TL~#n_+4{+?~1@j
z-M>4YwhQA6PQb(B3$FNknU#66{g!!f^~<-7>#eqQh5S~r%0uwA{Y@nfpYH#8y_wOM
z%lFZ-gL)an-Dcecf%6A6s!X6<;w;X
zZI3Faq+uCI`EYi{g!Kp|q2Jn%Z1{7i5Z^*29ig6K9NsQ8Sn&mbB+Fw!<*li%D%vj0
znCJ5zXy?o0{LX~KdgzQzapy;V;-EaXHz~4%*
zx18XqOOq;E;{)K0*jbZ2r+Rf7qs9yj6Y;vU=C!GAQC3IW<2rR`+RSNa_T&@`epinc
zGULW6CE0P4H^u596V2Uv+T86I+o);ke@ufW?CS08B_A3LxiFdg)i|u1m#lnC@b^pV
zZb*moOX?;a%b3+|G2=4LjD^ZQZ9DOjEGJpz5lkA#la&KrDxWzEwj{1VypslI#v+~)
z&Mn40>LIhwl(i{$>9|GWcj-G5_v^CRiC^4ko;-9d8XC#PCK}nDN%NFr2503e|7yTx
zm9sjxly)6oiMlbV98(A5DxE!`BIgG(nPS!#ZbvPH*_dL~WnK#xxA1
zsn?=xV@6vf!7!*cL4l))5fgrO&{enlkGuV`xVHFWu07D_i+mSXqdPjnogEl3lsgaU
zwjVNe3z{W;*)H2Hu4zXLH9JpwcD(SEcSLXwZEGuhV=Jy7o-cYMchxUjd_VIi4SH>$
zu)cz)-EEQF@N*T0mFdWtTT$0<^i+1Br?nGk_QUeWQ=)c2q^BVm~K
zJ)n9_@!!l>P-|Lc9j`*KM&a3tOFR_Tp9y)E6*u62o0@VnYjnE%{aONo34@YiGiOF*
z_ZOuW_0^|2lq))quS*)8%ohv3=%e)3WO}Zc9d9Li~qx-eCC_tVz_c
z-l&Akv|g{G)TDmB{CnC!pxz>4;M5w`xdmmk`Nv%Wjmn%NKscfv+M8?F!5efQh9wMiI%>x>AlbXkFFAv&gx*<93bn4|1W(3Dug2)%SYUCBShZqCP
z;$nl^Z(lL4-zrxzVOagX>4c#u`A;f2Q|OhKQw%8fx{n8O2QoSNVXX~>!UP2I1Nms4
zk6{KD|0$G_{I5I?eIv9n@nWUJRu^NW_w0TQb4ZT>8Wpzu76pd9)gIpKb0t0gTZM9Y
z7v$8?;>VqyTkzu_51J@iy29V}ZKj!nckBvU;jCaWZY*{vUBUQiOYG3G+r;Rj^B0Kj
zO9=Y>cH57oFMD*!;f~z^7-8W)aR-+D8oP7&FEg?2
zqYI;r-sl?7L8>pL=W7TRg#>?S)Azyh347F1hnM&CbBjtdFy&``lgpP)Iievsj+#Fq
zIWvHshgE_sK@PAic2W@Oufw9@eV7sUYo6CcyAu_(BXT!
zBwWgv=d)SYZ!_e4k@<{EKSfD5f8o_9bX~$~?nnN@n@@~ts!!PVi3ib7CV2D6QN$u|
zL6cDmKR^_t5q~Tx8Jp=S7K41dt_V;B=QA?X!SH1F)uy7pJ_P{%6v^|Y=f8=I|QS{D^>i6oO*{ZXQV}I6;-|FTrxYy7!8p*cZV>lj8ejRWW;Y3AEQhP
zmT1WT4!)$>`|My7#Z38_e!u)uDkAf#@+A$G1zqzaWsBpi3=R%4DB1wZgptBcn|&eK
z8U67L3AA`UMeU#3VVXFFO3KoK9#1%E)#WplWXoXodkdZmoPoEZtLsq)1Q4K!EFqh<5`YIQhCEWJ>i
z=hOXviGfB1WG8jM_MrvIv{YkT;xh;NwcPs$jl*gtKE0SCTVy9bJu6A(t1c1Qrw>bYkG%h8_Z^{!t(Xib^kOzWr_%(mgaL>
z12MdXafsv67jFEf-iB#PU}FM^9`2Pp=5!L!+!*jRsi2mXY@%~Yux91Hpo@c{Oy-L@
zb9?TqT3_9YKT2EcEeaX&J7l_p3->k%97rga-Rtg@*?jf7WJOm2j~7e&pMMi0hXOX)
zxm%8T8k;f){7?9V2o9=-YO+-~%KP~=&-jT>(m&Z%$^Gi8e|+Ybt&AD`H=%D2Z%4Aw
z1bbnndq99&v9Yu~i0DOgx7Kz7SVd&V0gp<%c<8SvFB4jO3R{xxdF~6#(Rc1y2rlc|
z)KVrQcck-B#n|<{om*~
zxKTDYy-C+pG~Ye_>3=(ma7v*Ya|V#>KQC>nts+Uty~-F&Hq6k9me+Yn^G2Tpi&6eH
z?{8OG(XNQJTf5zDlxl>-Tb8Hr{RBj%_3LAb
zIMKcpG8ljr*+wBcK7=f9JTo@hd9vD;wK`zbJ8p~_4-(YZC&3OfNYLx+GvPT9*;b&Y
z$tku&5raShS~29<=iKRtr7eC)XEJOuPudws1qx^p|#T5+LcAfoe>>
z>x!W183tc}y!Yq)
z0%d&qSTez*mlQnUgX*PI)-1z>sS!X)k
zyPeR$zyZrA%}3%l^wH>u0jrR2vTwiICSoWmfs&
z(kqWb79#Kn?Cx^H3CKY91Qxyn69DvR!z&m}hgLHpZfx>~}+<
zWTh}!{x1fxVzVD}*uGUq1-Z#`K0453Zq(_1Ar3=
zDpo;2BD*{^V`z6=H%5HI|4v65L}aaGiV&0&w(v;hbcJ$j!B19ees-OlP7Kac?KlCn
zn?_`OO$*PQofuyidc$Q#3Ln0W7_nq?Y^UsGEI8m%M}BcS*HV*x^@z^A@Fi-1Sdc2O
zeCUDVHD4>Es%;tNlE&c(-%&S(hGZry0iEcB_+fT~+C&kswoCP8~}2CwQFG@>|o12*56ReWyObZJz8x90NZ!
zXS~sewnRX28_y0w_?1;;2rr$E8>`f%A6?HZ98SI-UJGw)JXJUN#?~vhT~7w8;h?~j$;&WV|wovwLrw|shcHed=Q>iQDx`2PYJ2mK^E^kwbcRDy=e
z;=C<%&4T#etwa_3zQg55Sk=N}7qr#qViw_mPvtDZmgU?*&7$_|!nvgiD^b9?iE%oK
zfKT};{e|SF0H1;cu%(gwX=fTT$Nlw{aq>Q8Pf$!97>xlugU|SQgfP!@A%RVceOhq#
zT(iC-?Z5aBe;}!^c!*eo6cYNNzSVLpHx*m@yITpEr+8mW%dRSNFBO*Cm@byHCrr|u
z%9Or!!#ZVtN_=B31Q0^|4(EpkoX`>s-R6JjG5*AQuXEizgdoD`xT}<#?2L;0LzH#~
ztQ~!(4&$o>Y}7_{VMC)gfAE<#b*4W#TqR#yuz7NtztCqX;Rht1H{P?CqYa2Z<@zUX
z2-+!l0?153=uem-W-onXvafqV$gtx3AyY|dh9piqumi4&2c=!6iPgl>uExAPb5<{+
z&+B(T97dj=y!VH$IF{@dm{s4K+s+;(OxTixQh9ocx4`($&~UlZd2oci9K<%hzZgCw
z706M2+(0a{>i%kfk-~y;y7bPU;4Pq_6KQoYw+ZjZXilB_z>J$(4!}y-7EWxMkgK)O`Z(l8sCM8{A&$g!{-ISN+olz6%R{$1%%FB+gIheu7C||uqeg+>^
zw_3f#-u4g9zW00#$Sk6}u_`52x6U;QwgULzv&|d=N3}d61*7bcz8*HRMYBex#pK}l
zL_jLptfsM>uMEANhw4Pl!jEMO#H}A@YDB2%B7;9k=Mfw|=RVZQYQ+5guj8BcSjx`l
zyW8D{;R-(3-{d);`CRZr#GThww;uBx`z-r%0si4z{Y#dM56Z_J6DzYh3JzZFvScHG
za#2cvxO$!CqAojsM!X)T^ne=UGjfSy6ZnDpc5I(J2NROmAABjW;qF!9=!=$)6Wv-m
z-y)^N7+QjaLnX$!wcc4ai?y~MBm;k_<4VNl?DS6(a~xSH!x9-X-py1UNPA5OoG_T0QQH@(%b
z^$0dQDR@xyi}_TVq^VOvFZpA1u5t9XIXGP?eaR`9AYPNw?1FmD!If
zMIPRbP2bjYymgT`i-(aXGv>3-b5P&d7vjI-u`0#R0Aq)Ddlvlu+1w3yh$}PB@NBrG
zx+nadt2SSc`OZtPk}tPy>y*GYS$o_jn#fvd?EAstPChm_wk3hiTUoD?9)YCT@|B?$
zA&vbgb?t0+e(r0ruXR*4-`o?Ps8}M~ieQW5yB4)OD=pu&PFv>Y85wH(2R9m<`)lhrTevGrnnuXNYAH7lnA?*U=#vZey)65K)h
z>9PtUd|zkrVCb-UO;0YO7r%1to4S1-4NIqbz*&N`O*(zTpqdyE+!yh6@)JU|$d)k1
zI`?hu{4M7*p6wlcUD>c46NTva3Qqhom62X$pNna}LA=wy#U+VmZ}vPtGv3}Z`1~VJ
zre6Y5U063+I&TznTXRI6m7WR-%J^b@uC})XC+vE~H(KnWEcs8RMhi2;ueim=5$G{L
z2O)8j4j*UK#fkqSCv5ctB%f?AsI16ROl`;Hp>mTAn&rrdd&&5<3#>f%>2yX{r*i3q
zKAkn&)%ievFK((aq%@UdOWgt9nNwy_+z52zJlZ!!I15E^^W_RSOyg6Dw}1&mUzB~D
z<5LfFDe&pOgwE?<)Xi^y@pn7TaeA0a#MfS19l@us+eDWOko)ro%XNg664$Wrxd1Jj
zn6vSKC(RzEz3AV~fR
zX7&r;{K@_JzQyUzx_&Qlj@xMLSI!$wZ4|Uj-0~YV>e@H+f?m(&I_hC{pt5Mfrn48g
z(tAfuV!-t!Dfkdf@zWNve7*ZU;K*2keRB9v!xJhZ;8tS^k61seD})}fR}y*b)Ql4~
zV6fm;8VxQ)mNeZHrZmJ9k)xbLa%?yLT&IoVwY2aaxOqq;>fVh^9*-zKeRls(c8@x4
zdk@Hnz57~UleA=cwudxJc%6S`_s~D8Ilkjg`Y6s=j{v+9Vqa}
z6rVVq{VgZ#zHmP2*bP8NG!4m*r=amsmh=yx$9gy@6c8=ah2boK*(?{zo4C*V%4aNa
z#nSD-?$jK;soJ-g+>B@dL0u8QWcMcTJb}tr_^L>MA_s>}E|M4mSo`)3Y(eUhon9`=
z!pghujO{fY`LM@etvs|fY;&rBy)nP^CF_tm?=_q3ZmRxkT1JJQt}Sr_e!CC_rQMTq
zFWU;q+(u6G#=N6`e#0K>XzBCcr_*-iQy8N8>wBY8C3hoAAnB~PyKiDfF#Z!KeE&nHnu+syPK!l7V;aDFoB}L
zTp=kfsZ5<)>_fo}rJ~JW{{$wl8b%EEsMgC|t35j1Kkv%8cSo^7DOA1tuP{B*Ausfi
zmSr%7f!3|kt{&a#1+qJRDoFXR;1j|7iS>Ne%v*`g2M>tDnNk$LAKe{uBWU^ik>VZyX9+)2E8NE{?U
z!L;{TT@_EoN`K6zl!qM?C2cB*G66{=j7^LI!uwelzmdp7H^p=`FVbcdU*UICi6Sv@
zco7r&{nKSfHFa5je`A4a^{4G?d`sYW7X;Q>$etQyz19HN6=3l>i=7pq+4{34hlssVJUzh2tGYiCiG(X5o!U0%FGMyq`cQi%3t*aIeX3;
zM4+Z8n$~Xd5l@&_j21K^BZ;)`8vQa#W?a<06E0qAc*fp%U|21yO8%7W_+H;0N4gV<
zH;~{WTkJFXD~4;%L$gkiDJ~^Tz*N>X-kl=SIV_zrN@^3ZK$XpqG6ttvo(!g2w1QZp
zI9udH(JnQqICW;Ks9}NVzQ&L4Fa!b
zO?$OsvU=VtQEhBe&4ORexIx>wva!{?f>*axm2WFk(KeaFBHFgfP!+m+S<*|vYcVaXNRDrf<#NXVkzP@Q~&59}~%#ZU#
zzx?LjRnm>o6&m|ZQ@tSQZ}=E$hr9`%Oi-c$YfyoUZW;H>tKHnhaLgo&Xwp^S55G%{
zT8JTd!+7_QUP1d9Ry=MFhue}^Ti&i$(BGIokabw=kOXS6)R`NDfG%K`T8gbN_jD>p
zZwE+khHL266;PIP1Dod;a^Vv;dT`VIAdy!>PtK3XqlVh#3`m@)VK&8@^*D28a`0;O
zqkzyy9dwo-7g^Gc>&h2veecbYW2olY+WNH*I`loya48q&gRf=p(zy=%F~-;xmhttC
zdqA4|ap?Sp&A+%Welk}G%!_ExF@B$UrTBu-KD8hp>xXwC=1C6+s+s^HYn$s@UXS!j
zho`$39~3#f2)Aj(=S7-`*Yeg&E8@CVvyT5fN%~WVuub@w@LiXE>{AO>C3dGBSAMJm_)duVk
z7=FPN((4(}_Y4puHH*pM05eU-j5T^dkCOwn#11_BZT(<j%$gB5#yBbMX$55;R9
z{4}QWk+$IQcIM+Y0tC<A+5fG2PuA6H_X9V~@>`yN38$pipfCWs)s=9d0
z(b>5jJzngH5PF}eFQ?u~F(CyUEe_WQM9k~=t!fw|`nG)=id(pL+MF-$8aY+6;r2PV
zZQfsS0o2RU1ZvJnP;X}=WkPjt5vV;e`S#4(4Ha$)>w#j!*n<
z46WGfeU*SjVl)J+rG$XlN(0^myhLm>$4lBBLp0hoY#O1i1cyQ0XIv{<_&c
z2l)Ly5J~|MeOHE8XS;l+1F;r}06g$uwyi;T`yoUvrv+9OLj0Izt7CM
z>XE@%DVQ)L-+xEoeShs?{Cr@pR+v^3f&E=^j(1)KJ_&EnrLnJ&3mza4v=WIhI{}PP
z7_x*uX(4xUTZ*>04x&DG+$;Ne6m2QDFnrM;glDSG$G$tVCwc~uqH?(5KDVDPaoS^z)1Vl8qdlA1WvG>c~p2
z8u|zLjb>e`fS6LqH4R}S4s9hXHTK1=$1^xAV5pFhis+1dJ&mK-w6c$!Wl6D)+but;ifVZk?`~9eQBS50yM%Jqz6d}l5g|bn@R1CU=hRljL+Q?$&
z>*Fe&e9o&J;{!KS@t+TQ+*sKSCIOR;>0*Fgx5P{^ZUdu-40~A#PK#OK<}^7fdL6+P
zqbNelbf@+*!@SO_YfNN_oF>{tx5W=|%u+k_({C=tHuPI-ZnjvWMdlDntfiFta!@4S
zpM;DGxr=R5Ju_egdYbdI7iWH|+(qr;P^|qMP-;y|sw9^J?qHJ_PoqK5$W1{%Qt(aDitz7QmhShtvw4
zVs#wp8;ddDJDvWg+XVV;8V%#PSD8yZwi@kKTe<|HyLU4@(edeHI?|8E<6sOy_$LmFyoQ4e&zfNcz8y
z14D$Y*G3C)@@eFtu;46*lI};Y`ZQ}NH4$d2NgDQwvV;gCkE&Mc^K*KBEm7z|hHEEf
zQ_qWSF_3VZS7N+ykB#8~S1JK2n*p0U==7sBu+M-~h-lORcdobc$)R1w9H)mtEsYw4ZdR{*-=cqQ-3r
zf^xbrOpR(J#-Yd?G#3TAJK8eI8<>@G^kOVB$FFL+(S5Ufg7rZ}l3L{r2LP{qIK=MZ
zXFZkXe#i|fqV&E+2Pak7)28f5mq7|dC0Nyd85q#ZOB0Ma(Z{WL9i;pe^0hdG
z!a(c$+fla8;Z*Gu_3u~+YF0J$njixB22hv=8Vb1=mfxZcs#bcfJN|5;Eq+`rqD;i?-E+_kY`fsX#ecruLPgQuT!fyaPuN-X3vmKhvQwH{kCT56Fga
z`NNmLpg=~WKsJ*Rl7Hy#9n$(t44X*15#3RZ#JH{wpAh6>&L?MDgd&{c7K5#1?Ku3+
zti1sIy12A#tnITws=3|e?EVI-J$*}SfoVML*ZF}Ci%5PV_tb1Qwbyf6&CUqTsX!W6
z3}HkLdNd;Lc(?iV;(ABLIe9L~-Vp?8Y<7-v7C_vIB8a`y-2)X&Fx}%{@GRaDFicAg
zCDYJA7*JtI-$e2EXC%O<$|RQTC_eE4De&Xj4lBt
z+hA^O^4h|l>CBF;v~#?-qHfey0j3)MX&petmljNq4_5Q04`_2;Nss?7dZ9wi@p2JL
zt6Cu*6B0_K*d~mEnWq2BAbHZHvHm0QyD_Pxkgi|A1gfX46+2qQkK;(DtGuuf+fo)!
zP$!fXi#r^25|C>y4o!4JUK68u4_tXjWWSxCY?whY7ny;N4dX9LcJmWpR@xr;n)Tb*
zex)5xBCYdhKBr|;}992AC$Ppa5uB3NqAB7zj-p
zue17JW%Cg+v2foB3}85ljya-`sO;0SYlua{(ecpnx>|4@=nw;U2ctE%U!n*4{OMrj
zGb!vvBj0LjIOUWGqBM2L_h2Xr93imh7FnzX?+RkKNJqgOm&kaRhu6y($!lJOy|Rdg
zW;&WET6|(jaoWjZ<{Bwr#K&60w`c5F{Jp;ati7F2*DizFTgnWrO4dLCIzZ`7u-v%l
zT(O9(Rc~^clBI2!m_>6#pIa5Y%IWB?ha*x1A^td6!d@wX(~##P%bHXLPZE0HCR|3JPUh&At7uyhR@PZ0>hfGH~Y#Nhg-_1mr~~MOs=m
zx^l^}g}s)_#=Lpq!X-tTu*~7U-GaP*Ryse7k63GVEFl+~ZdEZ$LZza0UaJ3u=*=EJ
z(_0ZK2X0IJ5zH1^0fNA1qhUe1px&#}N1s(uMEyq+8&*wN;W4T&a6`Z6ba@p!32&4tF6p49!6^dAw
zO?e1HJH}SXemnbd4f>B5g$jjJaOv^+ENino1wx$xU0UtN2t9x?Z=y3BuI5G-alAJZ
z$Gfr}Mvs?yWt)s1%X`Cn@yA)m+t3_(Wr5dS*WKY_d=x#iWCrIBHbi{%*tVmPvwW3+~}P<-SDI!CmQVa*VV386pSh&~|GiFzY$UrQxIkUU#r<_FkE;(
zxa5gbm;6P35?$6Qt!ZJx{27mChn6NA(7_U>;4%Zv%U-i@6w;7L<|LC=DSO4LR<@<-1vNBoJHb5U6z^(idn
z6nkQO5wslfQf{lVgG$52;l)i|sOR33l(V-)j~)udp4xkz_Xs|PwTWS0gwt!dyVtxH
z&I0t1K7lzPv)ZMdTs?x+G;6p}N*IT&z~pzmE7&0FPSXE!hs+h2q#m7Tp9CM$rKTtD
zD!Wgqyj(OG@1aZ$^QIjoFTo07;~vVAjs>CHJ_%~uqd!QpNOLk
zsWU$LfCvIxkG1m0`WHj8m=QDHyeB|j3xWO$@6l_w{ceBd;)b~SCGB144_HQ|Tt{+i
z)An8in}Q$(s||k{x-Fh!(*5T;eQH#B5uvUS<*x|!jE3hZ>Erz#uuOSAm6YV4TJvCU
zxQTEe1;?<3D;yXhp--Z(JWK;%R00c4#&hulLb+5L95w=90hx>v+CV$3;
zkXT&F9ae)X%zIRXFb(15^0;>i6OGTQr3qH;Pqw;{02vYZBWgfK=Y|#>7CQ(1!SlZv
zDH%x(A?fcZJfL}kz$%q>QVjQ@cZ2#ULFdimyB>1zBvR^x$m(+uh)qF2t0Jz|b+d3o
zlP!jf?zw&fh@{`6&QmDDv+;RRKRX5o_TY_5v%$jVBB0dXMZH-yN
z4s%Uzcx^cd50nl{Vu=Y#6MdoLf2vDHGS)@kKg4}QS@dMOuHt2G2T#SrejS}NA9Mjp
zjRVboVS<3seg^UhC){?w*_JdGI5=>>j{X}?a;`_)csl-JC;nj%SRM?4Yn~WD5C;F>
zR^#8i?DwY3tm1EA0z@-0mekXm8*eB-V8YjOjr?_d+i7mUS+DJF++AFnDbA-~D$a^;rTGO5z_sC4Ksy!=OegqAXH3eFXbkD@{89SA7t&Z@oT$!So(rEM
zg-(A1n&li73K9@l@gD0--ytssR)LN4H3CjdD6mdE#wGUK0dqH+Oi{p&odXS4Ke;i{
zK*J#wPvVD~{a{7A@mASyTlSk`&IUT7_v==eNs73?Gj|BbA{qL`{&?P*_I{xYWZ@x%
zt5rFKJ@TR`O|+1|Ofycn!)9hdw<01$0YK#cIv9~28Mwg%kQmG;csPUu!9oc#!VZiT
zvxU($CLcJNlBhdF{b%S13@4OJ%^=-)FY1#v@JMnSrK(d{DHr{l-dC>NOLamb2vS%f
zB!Jx?j#*}(=-lMW{!<+JFn&7$x#@_4+ur|l%!xE->U#t-Gf$c@hFo%D7Z|=&YINj|
z=x|ubp_%u%Jz9L20YbI{!rjL`?T{PfIE)^bQvw>3d{Owc&-nw(Y~{omA?IO2Lmo(=
z;RmL7q-%Yl`_yv({#aPb!*=$tK#b$#o&>wd33Yc-Y3|kHY8wz^zwLxuHtH0qc(6#^
z>6ME+!5ypaZMkZI8XMp&@yK3T+{xaPM`mwn!LuIOW)OJ_Z(W{|EPhE!xCRoE1B8SA?
z(YY^Rv^5HZn11+h3xf75SQu)ze*^8g4&Jr)KJH}vDW*fb9ka%bb(HaSBN+rfRU=t|
z5&fwa!fL@bU-NoOuh9!Srs7b!h>AZbKt3B}9q4`I8L2-a4N<9sX~bgd?Fs9u%b)63&WBd;KX0N
z;I#?8G5APlEMP%kuclsIrD=U7$i!yl{zE@kLQBf4wBH2cU%J$
z$TdqjQ{mzTj*~C>6TE#u-Ti3`jhB9Itx%d2<4xYxv+6S>g55oG3<$?mbcMt+3zAi$
z8xpeKOFar&P15dsv@>d`KGG=NkL0n7rQ0bmqcmdOZg^Jhik18F08<6si)10a;1kLB
z)j8kS{P(g)Qm<_KpPW+(aJ6$>hW{z3=5c{sqa2u0h^TvS%YlS7$hAt!W}*p$KleAY
z2tx<}2IFk|CP4t)#bJ@+Eu8W;3?rq)8{r0RQQ#=|61I`CHcl>bj|cn?xW-`k#sXAI
zxFte&9z`NQ+^v6rXXt_^t7=2nko5xwlt1E_>f-pM-9WB1%ywM<
zh_|#yZGXzx;*$t
z0Tf&eF5z&}1Wjta9WOZ=kXvQyHdzL?Df@5K9H}M
zU1Ak`?`<~=_<^;dFz^UANf8L_wl++d0)_2<3?ir`
z2l1;>G8!b@3^25_zm#esLAV!lvX{?k5J6uE0`MYjX3}s966zCx%HF9o!e@TxZyF$F
z+;Mws;_j(NTs=P@UsJaV
zq5zUaITFm_`HxN}WtHKkO{V{Fr;b2xkKVW!BytIk;$*IS&IQ6o2!<^cz=9y%4`G22e&$F~
z_0Z3p5tf}3+;6dLvXB>m2tA`}Bge=}1Rffzt!7;Lr*R(P%>1Rci#eRyAs%nsaFK;f
zEK30+0lc#r-!idN+o|mAE-|r`0(S2y;9zeFyB-RpfYBMUvG*>_0B;B951P*OW&g;@
z`S|_}k)EG*;!P4+V%Uwa(LX=84yQjvo6pYJkAyaqxE9sI-S*)}sp4OUyu|r9iVY(->HHvq&a5!r_FyO1(
z$@!(Fy^pq&GOFsfsEfut3Lls$&D1`}9q3Lw<1xrZ!Q
zD9k@cwRO5yYxhIM+R+kdN`L9O9oDq>;Nq%!9qRMXQPrNF_pCs5&jXiWf~qwaw4snC
z{~^;D**#@vIZuxFJI6=eU7XQa@n5ooI_{_5tU7QSuL0BsKW03#927SiXFHJaVX}oS
za$wy+2m3Z9u1qTNgz}4n+!+MdaPKD|wM`
zm~ttX1X#DN3FY)>VqHF|2c?yl?OI(xeCuWIPgHbAT07%;&Nn1uK1#;R!xlpcILQ&x>D~2L40F>%wKP*dp|g<>NXgGQ-AAWg$5*q*MVls~%-p
z08B!~;LxH>lua9whhwBK=v9LxGaa>Ie7mg?1oQi9{{RohpF2nbqXLFDTJ>!;+M`LY
zoT!ult{U0fhf=R>5O=UY;|=+fpObyO?MLE85D+)fe?`wOs#UfFsJ^Xb$E_bV@&8kU
zyP<)M?&M+|{eT|e(6I^41(OK*nBaBZ=z;*Po{G#+!3--d(9dm)vvNg}iJ3&2JeCp(
z@H(Y%+69$#+s%XeYJx8*i?jMcBnB-v3blzTOv2GXxV-71;~kQ+DDcO2_0YL_+V#9+
zcJRb^2V(UIeB;rblFRZ-Kyu_CZTz_JBc0AGZ??5IT$|vl%FvLwH@;A-p)))U^PF!R
zb;7IHMFQOX=wlC*P8}al?xuSwiJUj7n1d!ut@!6zOVjs@1x<47vKufuW-SgQ-cV>9`io8yM)+J(E
zgf_+=BmHb?mmo+1!8B@E3@jXA?}ryR6jdAq!V&Jt%a|BNYnB0vw=iyLBx2EPX<8vr
zg2-LX#@%9S$R)2K*bzZu3B-vY$e9s|^&XS!ILM8%fC&!Eq92e8Xt*T3Cx5?M%Uhw<
z-`{XE3&;{ZU)H0w0ggLeM$b-|AVX(N1jcNI&pdMo0{*04i{w4_Rs??EY6)z)h~>Dx
zc`l`8tK}+Zl3Rq@)%92f3MIZxiTHN^oT;vmcEFQ@0H}AOKvoXQUYNddWXu*rCyef@
zVo9WBi(9(7fDf=TTp@*{)+TX0FkG=9Ait5dS6ngn6o)-swS8=&v8ut#7q=yt$938=
z`IW5G;~-gO62P4*{D*p~N%YJbHL`9admTg|p6j?R>$Ll^j;2>QYP8y!+t_uIuygre
zhYu$XZ~KhC4JNk?w|O#dysUe)rUbb}kM|zujU#g)96`Gwb>OOq%*S%BSr|SwI=qA{
zK+z972vs&fb1Ef6>0lKkzHPSm@vN1&e$!99s)O?6rBx_+2T_T}I7NryYmiw`=`*Lt<&~j5UQ&eZDkR=4HQs~-i;NMLQ6V#G~pR-A)i8B
z8Sa39x6nNFwx{-mzY$Y8zb`A}(9)Dc^<^ANk}O;?n!R@c!OH(qD>l?eZ7&!?I&~>e
zXLoaTDe{~BnF`FKO{IL;+gRi{4)iw#B{Z3`DdP8I)1rQui6sFLY&P$R>Eh!md!0g6
zf`)|G95!N@7hnS~IU!7`?W}W<4c1N8bHABLT7Wj8A$eY7x!};^F(D(-DDfF8XifUs
zOu;)iILxE3$rH(M3Clrn3WA)CLj1ToAM=jgR$#OQ`3dGhQciim!Q};1F(DTAY#Z`y
zaeX%K(0*gLlB#Z~wybohLC@B|hmZa(;UngUz{{wGo^5bf`_F1p6~|K5bx>I?SDE1r
zA@BX#4GZFrJcCfu8&%=qwyLHNF~WAxuvxB|g&x3{Q*21rG}Xz+jl=qgYzh|hFn^R0-SjGlu+EVPsz!;r`b%(PGivdI|(masGL%$J=#uY2V1n0=r<<_
z9@R9{%
zteX)!%CVFS?9OqxKJzqedO<_K8b`a>Y2z#UElc{He-#9vh2Z#$o(9k`zu_rNA~vmZ
zb~~Ht(9CqGibbhSSck92>D>TkyW*LD^pUKGE!va9b$TSWmfbE`IW*6g!4t7`bsiwL
zEdPt}=p155F*>$L$i`qe|IN{WcAWx_w)22_Fejx20T9Tt=u{X{Y$qp|D|xi
ztNk9htdCsjtF_&OYUMc=8H#FY~_x!0vNC38y#1JL=c2X*_k)c3cys^p?7xI{vUYk
zv%4k;R@^xx9(WICW~nPcSPStj2+9ypYLu7+R{&$vAzKh+m$M2fZ#{I^1i}0D*Q_~M
zY^>|a*^o=k#aYB(u(Z4Hj}Mx>F%JhyK5Z?xwyT$Br%`##aR6(ax=3oXVK=u|d6qx!
zc#V68Ug2o}^C!bkR^l*R{L%l-jhnwC2D8WW&I)kfRwC
za=;6R+=6w$40@slWv}?Yc`Ag@UXy@lC%+768Jg*VyQAGGIFJZc!0bJYJJ*6z){h)y
zUbyKDHY-18)KD&?MXM!V*&s#aI8}VygP&|SSYvT
zMS?F>VXE{1sm4{}4P>{PMf7Pmu&c#%USqO5M`$NdxQQl{3F%eZIu_avUeYdclM@R?~f
z!`a0c*QdZ`X#CiUu91_X^R7*qPo%!bpfBmFR%%=3BEg_%As%+p_s0v2MM
zY1xiE@xUI1761X#%)~MyBdG1g7YGsPdJ5-=A$-!mz+A$qFB{C8RH*g?YA4iU3k1W&
z1J3@?hGj4U;ULrwxe>RP4rQIXa)!|$dl(xgTT&zBOR)t3E)!o|j-3>;I*h1yJSIc3
z9@X24F^N6Q1Y2PK**lpyh*8qXF|IJjK6gK9$7U&I**9^+hejSHnS^nk)T5G>^Sm8#
z35#K^1V}ndZ^mSP=jUzLpMOYiyeB1O;)pSnL!sxaQLM^y9TUG51bSps#1p~dw+H5K
zJ@1fz#BCP@sW{t`t#7v;wDSspzBaAw1%FC$#R{=-6|NeAy{P;PW|e|rXA!T!3S4oJl+gPdM7Vs@oNE(^;;
zYw%-KS5gt`O
zx+1mW-|)vS{fRPML}nE+4F<8~LHDAo8!hdOEqIcUmMS9Pgm!YQ|0a}G?bj16Knd&Xop^e09Jfyl7m~`yy
zl98Bw9SR4;Ky987uD)q=LIX?vx7xFo7+}gWD*A$W;E!hMdR*!;!ZsXv%@gwBr
zGCL^!d*zEuD=enf!X9hWJXR1HRimfXN^P_9Y6-2%V|DKtt?I2jS`AwrG#mf*^6t+j
zm}tJgHOF6@E0-9%jB9Pjt_T44zC&d0P{dM*HV+PDlXCMRK$U-B%OC!ZUK9wcdmmQe
zH$KC>1Ae7b931_-v9y46C0lAEI;j9eD$&5}Srb5b2-H7CQp|-mMI-)j(R%J0O_TcZ
zXBlV{_hqCvf91a_U*6!>EDb#m*R3qFC()a?+lt2$;ZzQE0z!m)x6*^Y1o1|NnnqcbO+q+Pq%xe{%4gT03GTh6+hG4(86
zbn<9U+kT{Yv=Z-hCIU-~PDEWb8AiXP9Dyya`eApybJcFyi|KWX(-(=!w&ePGx^o&1
zlPoRDY0>rb?@7biTUvL9USEau8n}Lc{Ru%h`6xx}WK09EkBh+{T#F^OIwWg#};jZ#X1=>;*1#nad0N|M9^%jwY0lc2
zgHZ1d?r<507!^Q8B=#!;SBL}Lfh$;e$pKUKrrKI8v0HZF%HA^$U}c(E50wQjb7~U%
zb;tpMKLV273hW=Gbi+~(<8iyq%!UIUBHOGkd3-gFZ!qwYLu#*isaPO2OMHyozha=i
zibZY-P+ygRFL8SWrA=;4r@1
zM^1lW_Z{jf;dkjc$!8eTU|AT-=rVbkGqN+r1*&;y_{O(Ba~j9eB;t84!KE?2AaNgu
zEs>@}E^q+|z6EObk%@!QxdHxI?QOht2Ox`s1Y~U1IBeqB`r)C@uJ68s6W?whxA%|U
z6(^`z#~
z?Q!@$Yaj<RjtswSQAs`x8d0EP}R>Es6zx!7M87BTSQm2YOLFJ#I_oB##3W@6NI__Eg__RI_4=C^QN0QcTCXBG2kgBtVOX!M@77JR
zu7f?CUCmX<}DzbaSU$YN9Axi9?Aau}q@?
z3)2A*yu()4hIEHcNasGP=}`_G)ot+-R`ziYkVH%j=!QF-3AO
z1sBfF;s2Q`yctgOmNP2_@)=DKq?t{-^wL;P11NmHkK(?I3rHQBU3Q8iBaU*w!JPga
zvZx~%TCk#_ft5J;J;;}KG_cK-^27ecqXL
z!O*koLW&YC1+Nsnk0XLxmb-@+$NGO=9qW-ue@ciXKf^DgRNI#2SN5=-!4p_!fC{fE*H3)jTh>6&#tXh;pRhEd=hF{DpFHlVdcxoq5TvZ-39N?l9Q?^zS5{$~V@Ic0ThX%d;NJ?yN5K3sGYN64!
zh%B|V8Pc3fmMs@Akbo^1RwW`VnhyExEzgS8U8z67g=c)Ybg)QtsI6ZEu5^g*i7lj<6Y
z=Q(UOyqF>(Q|5L_jST=3No~JTv1??Gp83P|;C&wEikCs@M6_@p5)Mp_!RldW2%yM`
zyX{0<-yHmW+CtUAyLYI>z{TDxHUNuhODa5jIGPwQ5@_6mX2VGO7njEKuVokA?InHa
zHk0c-XZz5#ad|{0?iD0rj#)7s*3AW!pDv$e1jM@7n=g@^&a^xU3Gu3@;%+s*a
zd2Adu8;qq^Ts%p|JCMxGMztN&XeO%SM#j#a_gp2>LyCmHMZ|?FTV=x(v-*pNtnj<<
zTwqk{6Ebv>AoMku)i=9ZzH{+~o$JE!Gel`PPFSHvdOL2OhToCaGmoKGmCdt0kIyGW
z0WXtqFRQA5d%_|cbJ$UU4LO%On`!v{=_h>Ll$LsmClaZssNB--e1&W=Yd
zVPoM8Wg2yM)Xk6(#M*2Z%pr-jAtfA|$2bwk9p_+<07jQUp*403cT0yX>=F8CCTPN{
z1yBLCsVzW;lI^VFKsAX#ASOEC41)gvW*LI32RN0@edX(E#;|HpovsRsi{ZMu723M6
zAzTAoMG7WRK!$__0mjZ?%-}6DAxxeH6B^EgB6c=e>VdfJNF-E?JF4Q~j9Ui)+Dz!z
z2^2(q_x8H{qx-SleOEsz9`)6e$k~``{uV?KxCh;yu=b?m?{6f5+{HjVS^5YPXne7n
z1k&>&J(EDh1Jyy6@r%lmg!dttY_K9?L=ZfRD3LmlCF8QN1;vOUC@M-sEyX#rm?#hg
zNon*yK@#g0*_ZH6=#!Cqp*(OyAF?`T
zdQdIlopoG2!~f#6yMN1=UdzYn0n-|e7Gl>N)$dg8uz(P4H4VqfVs+)DBD!K-UUoSI
zdTn;`Msh>}(xvz72wh99w;gn~>?EF7pkqV1R9%^5<&D2q2i;BXgX
z_c_fxi%HYy(DYaY??6xQIHyNd;+6Mcu=_EHZYLn!;7A}eEiSe}EVX4DZ;fa%GV*!E
z<7IE)9SQCR=kxpKM?|RimMg@N&XhJ28I2EAqLY})Hm4%${@}gGAc?@t;$MXWEYnRF
z6SVJ`DaX(aDp{vgBTl86Q5@V-Y_|UlQF80h@KaHEU*qZVguw8~!q2??R4p|OF+D>C
zTBYF1!h3|t1z;M(nM**uxyn4jh4oYluK9f7&gI%l2$5a$sd!WTLov4eMgXL%K?j!pcQ%)4Yfn(_}qCfNl=_9Q&ap
zu->m|wxA1(z!Q*_Xs3X{3c81Q1MF5m8i@m@3StWGW>6PeyKt#zM<3o4&b;PNj
zo^C+X%+%RN^uT3v6Xyg>KenSEEcyZdhCBtU?)Woo+Ow$oiYIK*UcsNqjs6>_ZV%u8
zLpHY>Fp+lbTsp2E({VP}>2!?9i;@#@o9j9by0KPaXI2P7VH`)pF${{q!zNR}s^s!jABE^#X1
zC+RE5H0@zx$nW5^u^`Yn!mMYANoqDp
z5CP;yESxjrtf{{nVGFIZ++)X{S>UDBa3rjZSl~OTb8v;H)4lpf)QhvtdvOkP=>^d$xtqBc=V}NiN(4@-V_91b9(~iZm
zLCP>eMmOqT{249$pr;s9Az*ftbfqoNy3K1G2sh&dC=ZT!Yhz)q(Tx{Ls5Gb-ZKYQt
zr8A?EzMz-y&@SnM4I-eihZzb#Df>v8R6|5d)6n=3wT*E?&lT6hPN
z(@iNM>bF6dnI}hm%uezp97Sdiljab;PLKc6zXKMKm4*t{(xgU>)3~E41VZ#6K=oG~
z3^n@&j}36FX_oi$BQiMw5?r<97Q9}4{!)j-BIJhBylp394_&ikC9}dB@VPsJp;v2-
z7i=HOyj`ucK{$IYmDg+Yw}ki))Y}SZie;eIHrB~~+Y4$4p$q`MEF=f#?!`PAnC3=7
zz{~NtPntAj%ej84=S+8+Svr03MwPto2x8G)?`GQTG=0}m;p>%Qz%UQ6jrKVFKN(H9
zU${}*s@4`3qq8+a@}9)By`|;O8co&EXbKVm(@!Uvi_gM#F4jK~7tGRTQq6~wH%M6<
z{~>LI1i#od308Zv7G59e=FhZ`%o0%sFfG7h8-cZk8UA!~KwlA!-FvG^20@UabPkwS1BK`f%>&Jd%q6%gWc8<2
zW2Gs{5DSLW?2gHjl4}lpC*m1`G>`*GlIeKqRGkT(Neh_|9y>jOX~L{6+l6sUk=M{u
z_?bM&-;v$JZ$?}=911l-EtZsqF|G`A*2+`z-ye-%MD5s~hRxVMq3OuCbZW5)Ra@@>9Q$p(!`6Nlu_x3R4~oP8hR3q2wnY;N
zJ%n{-U5Osh5Q2b7ff#u^#Ldns3MrPfrL0XsaOKYbxWe#^Ey1fs=SkWHa|Wi*
zLYfx@u_!Tr?TKVW!)g#=IbrtW>(<@
z4H>GH-~d#|q&ECqECE472J_5Gcfl4a4f{gzHb?+dvAWjevUl#?N$(>#HSqDkRFYK#
zfqI=nvP(PQZ!%&fSnceF6$3$cv07~A{#?Xe)xg%S4^{<;?xJzcN^n;zVpKi)wL*l$*HvH}4IJZ*sZvjNblwgwI>
zhgJ}HQO!UaL`6Cym~JA@OrYh^$Nq>LZkxSP9GJB|E@B>^SE*?9k$PA;2R+Ks}DFL-vQ^ZUEQBZA?;P1jY!!P{a6$??npx0M981#K-Kj9le>{UtSK*
z2lTIKD@?C(&>q@wG##CfZYGXJt!6<0WWA{xJmq~}caJ;oj~ahjkw57vZ@Zc!qj0FY
zgu=D3fWY4gkZ4kc9-q;vQUL%TUj>Z@qTPUpjwYSFf${nP=w_nd=`I?8${XWAIN(TTO{B=#g_~s&!JZFdi%W6;u=zO)|j-W-1OcY42w+wUbD
zmf|SVLW<>R4miI+$aP_91#p!DM&UPtOo~Ak95d!xaH;rwhGp4dHOPTr3gclx@ECkd
z1R2|e#uC#-!0Hdace7`(Ac`q_Bz-lpEz(F
zx>DkZxhN1z{=}$WFeA)xpjy&0ldP1TLY&+BoFqIxxU#Z43zz)X_R#_!N3y6~3Rz;I
z@}=)gUpO+R_LLF@t<&w=YDY1R(g9~qK5Y`1YV>jX8>O7pO01=`W~
zB=wm>3yh{43HpO8k-Lx2>o8M5c^y|`hZFr>^wj3Ur>ZE6utDFdd6;6|$Mq&juV
zg$P?PIQR!z7CXn^Slo|T;4T?x-BLBj{Z1kVFgmO&Cq
z=LXC?lS+qZX{eyU&d{2o4a)iBln8N=j}&8la6O)g!!qgebqva1;R~(F_h1BRCL$yV
z@&-_H5GRe5^hMk!6^fV>W{Z0OFA7iyVg}X#A2-_|z!ykJk|%)6nP6Lf*dk~zkt5U5
z8WT}H2t|v*onH^`7Kj#LvFyJ%`<|ac)Dgx4WmiyKrYxl^eL(jWVzZUT5@pE_I_Q8!
zeQ9M^_LeX^t1N>agvd}P%5sXkE@5;cW0Z-{OBls@YHX2ICAM$IS}z~87p%QoY#4X|
zQ>-Cf<-q}AtdunN^<$=3p|Nm#h*xYFJydyBe`tDeD+ti81RXG(3lW0g!oq+IeqN2n
zfHwjbntmDQU2|kb*%nkA*IM>p82N$zm^RQe8e4cuOcI%30ly+CbuYe{>Eli!IR{CB
zKeU}zTO4ns75;3*-W*5I9a~E)GJeWT6aBX?2hkgc+X$(hvj%l#+#0EP$LZ
z5x655yX=OL8{=3Ucccx~mSrlx3!blBIkbwcp7oxQ2ki6NGwFxtNh20c@&)u2Kr6v$3c!tlej54cJRzBQ_dC)ZI+H9G9r
z)A*6n`xb4VaW^1OULd`u>?Gf$OK0xlTh)}9w-J1nzWEWp<$F9yZ|5xxySVnG@gwH2Keya{
zFZR^~Bo2ddw>ap@TT@NJTL4vOR%Z`Ih6brJ!nw7u5|b{IR<>a_hANa&@%z_zIhiczAI
zCKN%Z?KTt~%}0#{+xVMCqSu-SPTwSdObz5_^Q?uW{i%xXU=9B5BvFV1B<^z<|L)D0|RmyzO
zk&z_VtQesS^~yu@*#Vaiph?Ce46>W!G2<^m;Cuh-k8DKXwJZ@t)Jsw;tX1|~7t#u>xZSzZ_6q`DRvCwt9;jq|0UZqUV%skW0un$9
z>DK{@xAGNLyzigNDyk*>-q6)go$2WAA&y37l&oc{HESX|9+};j?2g0bx)XP1xZ<>d
z0)N;dalJXs6MiEI;%{lAxaU@)p7gPq)hI_0gucgP2@ii#vH%@5Iwi>ny2T|&@>N~Y
zCj3x4Ue)m^v3cB8G{!=~@e)<1OStH9<2|Z6_m;7fuU?JQzd;}VYBfy%1|d*++~$Zq
zxt5cH6ReNsft8_LLBI$wwb^%q!+o_dHTS851Hzrtx2CpJktA^UUw>*Gyx{+K
z@lv=+`#(V=?R?~Ub-GGB@UmqJoSupaXuQa1X})KYl1K8VDH4%}?k
zIqkKjj^_GXo={g}OXd+*HXznE
zq(RPO6E_r$)9#l^_seE2-yqw8C~~MTb>CC0NT(R3zI)uBw}T#b6?WJ`4Ehf}#FEZ`
zfm^JTmpDKZhKlQF=;Kmk4~4$^>Ha@&4+X)aZHEw9WD*gd{;Z~Z6Kc93NyeCR^ii#65L>Y}hAQq^k1EJ5A?(P5(e^z~1tS%e
z`syUC*v#+VB7m|Hmp5Hb%tn~;DVUX9aIDu6JL?lb?_uO+c-
z)vQFw9GUfot^+qNGkbQr3VDc0>+T9WcKX=JjxZJS%7julwfhCPch2p93<(a_dow2)#~+6l#^+e|!p7q*7$f_E3Yur;Qg{CiaFykZz{X|=P8y&5*CsRhBf>8C?B
zkjYn#DtkFR=^RoFJ%Ir(V5RslKKjB4l&6)Ufy$zTD+qAim-gmp%j3vU)Qq5YPZ?k-nzz5P4OU_^=`kQGV~6j?T_mNrL$
zu7(L)L^({j8z}7TShJp1bB8?V8Pg)E#$!lTTPDR}?VdF2DxfNf7hyt4Hi&bcVQbbO
z121lfk+uV)qN%mabNSguuz>OU2Z(
zRY;5TZ?-YI7`*=B^tcN&l=&AM1nIr>73;Qx2a9%)9fg_oSa${TFFWmZT7kQ!1$ap{q-#)>~}#-FT^(r>1U9E}k6qvMUia^2Q
zsT&sm#kl<6j{diZyQ>o(!pDg57nm)Hbl4>f?ymWf-4QXq;RPcm
zJ2H!BO2iQGn{xbLVGXr9`<>I{cDM7s-o_OTEB%WD;R`w5qloxFbSDx+hUc1U*@
zVwPN<6}6}N_6eq3#Cd|?3U>$u)u3YO{K73z8Wf@AExn<#>=k1lq|0t4{$#o70GP0(
zYkirjNVOl(DVDiH{eqggqx;)4i~zBh6uBQApGXCw^*>6rRlV1v);fqn4Q$eGh}`w?
z0JA_$zv{VX%+9nop2muq>`lRHac9{nE0|wutYB+;J6n{1r3-@ocwQNKzE7P(N$$9i
z31NnIQIbOt+`};N=uC%3ASr-0h?Sz_-Egenq-5MDe=ZRk4km+HB7BHNa0p>6qQ9cq`<`l?q
ziF5YY_9r*Gv(i5MR8CsZ6xm}zkWK3VVoDK8LiUP
zRddu;$K^DUKQ^FW3PJ34=|xs{
z@iJCnFS7Pb-3E=jaG%$tOTggh{eWP&Z9;M>#d6{9cR>)`-|F5vh7n`dlOM9_t45%-U5G2{UA``voOl3iv!oygiRFAw%M@2E^p9xN`KXrrD#sS@
zRkpO#+D>=zI|H$}OTF7{9n@Ft6CKwQHv5-2o)0;F-3Pj{36}$0f5?{5XdC)6`78L?
zwGcNJ@1sP%x%YcJF9w6yDmQSEnQqibhR3T2OEI#+bqG(D4bFnr6Mj}%*8wUx97Hz<
zSN6=w7oPL4aHtq(*(dM-FFZ;f;7H*RQCkpP_R)=Hq)RSS*MG@$J0Fcvb3S#YD0)6g
zcm|u%ZZ_+u_3npGtIKIt`4`8TPUEh1B>jLnF5%~=szh85H&RK$Sy;o&d;B8VMeM0#
zU&a>G>(2C8fMEsK_vxIi>^diHQjdMd%4914icq=oNp5
zfyea4829-i`v8Pr8?`3`#-c$SGl$V#2r=OIWGiQd%6#-PB5))Krnq{L4LO_(2#}qY
zm_$2;ISw~vp#GH`vO34Ps!6Nc^~yL1AkqAA)sn>RO#PmHAq-oqZCp7V?h=lwEXAnp
z#SB&f&5B5k4VG1}6EO%<_6!nB(kR75ZY(L>azUE~L~dgKSdkITvheni1^jnvd(Ifk
zs{axx3)Ka!OYb8#uM4~PZ(K{J-M!toC~a$JcV}r)+8b-hWbe_;cW-G6VmJ^dlzkEU
z_iqCKexB^0I_8Dlk|D^?^{1cvVEI@!kT%Z|+Lalfk{~p(u
zKnpv*ghg3M`q&5zDkF_Ppx2{&)MoL@8&*AxqGy$7H02UCZntXd?pPS1{NBF}d&lKI
z@vgPFr_6#Yf}YNF4@`F83#}EI&>rq;BFGge>Ko8X7K_F`2Eq^5U4fZuK(x$_V)xH}tZSt9`B`ebAE_nf7ozwQ1J
z@Az1Cv4xhph+Gqew~T5Ntwo*=B=gi|%_g*Zv0j>jH@G&P=Zs>y;(Zqdg!NTu?mF09
z6ZfoDol<~??6gOrA|JBs=0=62oOI6(2L>U+)%@%ec!{2X^*=@u{~YVUmb!5)8Nokl
z8`adHf*?`YFrnA1`4-$zJ|7~?ya}=!6xh#l+`z(MW|s`O<(z5TjYHTzzK~mToJgIjEBhF3ua{c~oIUn(|W4Sg{mFJY3U>d*x-)SX<6e?V_k3WTb6
zQZ%^C2|+ODmP8Y{jf=i4hckaZwYOzXNVE@tHF=dBja(G{rzu_&->d>ILQyhi2H4
zzJ7_kiuni+ZRPr;&jiM
z!z0VGqitLANOC)wU;jQ;xDX^kiXdf5-DA%swnPv>p{h`*dQdfa#?^ZS0d)EWO7%`V
z>;MMfH+^ISw;q6Ro(JEffjPWakU;3xvkn0@+(WP$;;#22Hb`j?C$R(7o(I2Mj8N%K8jbL(B&LE?31@tK;4W&yF
zqAUY_Lg{<~AMVr+_Cs%^ER6emdpn_5QlfQco1JRqAoOC&v{>7(
zRd+*gKE|h?CiggJk-f!dVURx^@+Cq-))ZujP*55w9zpzkXs{W$?5h4#`%}k9p0BLC
z0X?S;R)L~J5jcni-8B&~pTOmcgbX*pIsHnaaPu^yf1=#RX;R0
z^kJb3Pf*s8R3S4XPM$`abnydS+83@g3DLzx{6c9T3dwsstUh^@mr7%)vi
z6{S3`PnjDJcdzgtfp9p0`CHvxl2YnO2XrGm>cmXXYbIAE=+{bm1(zwlwZTh@`
z5y*oj3(DluQjI_%Bd~_C8Lh_%4;mF_SclRqR3#?1qlSAd+cFLMFA5{iGdaqQjjmb&Vf-qqa!AM#My&JlJg|%OnjR;Q3mxpM}sDDq8Y%4on$UN*XUj7?lX|
z^oSrIA(;3Y)!f?>;R`xSej5#+INJJkG#LTa$6g!t5;#e3#MTZ^Dh~U?7be|-U&nU@
zyn(|GXHhtExg}2U=wmYcP6LZ{tBO9+?XRx`B;p!)^9QPIIDU9Uau?;#R$&n7L4uQs
z`D=l0Q20$<1=Hc4&{#EEJ3#e`8(pUDNQ72F5a5vTr>}8$=Li&J!QNquwWPa5G?=U4
z7FZkU#ix@y6~{yjNn%k)gW=Z*MgLpa^H@2iy=XJ~_K14|2zXJnY%#mXBETc_FY+7k
zT^xp^%?7ss%+P1oGSyw+hcz1xhQEHJr{F#rA^r}Rg9=)S5Uaeg2QI<#6B{x&s5^mz
zC4`^;UU(^_Z~p9z!xbTX-aRHPIR-rfs5gbH2FGrGCFsCiAD!O9+?5_ms0GEZ`A#r!Vn(1ry2gm-BwkD{3eVv;TrdRJh)agv
z!xQ|e2vppG)#2H}szOvCz^Sdr6aO32fUhY=L9LGLU;mPk{YMgfKItRz)kOLs+ezpZ1zY*0Y9zH&sxj$LT!>7nz43
zHZmfESThL=$%BN3>F6`~3TJrKXONImVlK{4g(xn(Eif*u-;v7XA)4xl2FU7&Q8~yC
z(z!fCz_RZGjnqfkRs+B~3J_AF2a0one*iV6;58&yJ96kF{TRGNXm$HELCvx$5V8of
z(t~6dlC-BkXQss9si8;Z^8vn=jddZ!(gP%}SQ25y9i6x%j0u9CeGJP-Db4Hwk-%uu
z1mPL*W_UmTw?GK02&ybRFI}!bcvqxI15}cXVbMn74YYhGZ6E?LaRcPMZq5r_GM-t{^fW0*+$4Bd=)?(Oyt^dUi9M!+>$b
zKE?Qhh$KuDl7num*>guPRKCdqZp)||#)TCoYoI+zSXM*U=h+L8^{ShXtTO!tiCsSe
z!K%@8GfA4<`4D*15G)d&qh$#{8)D}Z?UbaU71P<2w8kk80>;MIG&a62S<j!?4x{d#ca5tG^(smtvu6IL&(dtmk!>i0^R_Oh9tyV0QfvIWoqz2AGa_e9
zB1ji+G)}tLRL)utUvd7_rDP2rv(Pp4r3+zsYA`(=2#YIFt0C-xov=vjN;`OQ!nV%S
z85Q4KNGU$ePQ&}@9qtg^%W$=(BNH}(N%fH!HbB7Ov<3nDf(;8&nMV+=Q8u37phET?
zOBC6y=iTbgKlc8K&2EfyBFHht^|U$SmN+d*>sDfQ@SPACt2DIE^Dh`lMc{xre@CJK
zhb>>eQmTnM&7vTiiKfUBk4w{Tio`rFb?BM%ddGk^)GCIGR2P6qcYQcLCQKGi)i^KH
z^>aFwVv#AgMCc2wHT=8Cxu!6gba<^D2sGwSRVS+P8iP3wi~BGz2x3at%J9aZ8(tai
ziuhUu`MK66#zAHW4U4TD*z26hhI*n8HA66Li9xQ6q+vZg^>zR+iw~RlMLtl8*yD;!
zzWl|<0i|);ub3Jz!|z}VnH#Y#33)zv3@pQ}&}A%@u=}DlUgyS_uiA!G(2%|QwP=Bv#G=$@JdHwrd&afhRNpk07-B%FVaB7gY*->HM5m+{Fm&n{O3YGx!_J43_S|
zHLWF@muG%sFN0zTJ)(~(t7VbhmtYa*yA`tt*pBxKAyD$p3|UQy9Fn{d7c^42{(Dil=W3?`pAtcy5h
z^USYz8$VXrcsy^PH~q$^Zm;j3wJ%QkAAYRj>X$GO%~)473l@xM__{f#g}keFGevld
zAoR%oh8UEr{UwwY&MNjpK}03(WZ<#TBQL~oFt=B~YcUtEnBl<085wSg@wG;VJEYK3
zMy|`mMXqNEvXzASYqi|6dSqcm>8h!rVuLtaF0tHn)l{R{AX9Nu%l2|OzZ#?crK?;GwcQAvEUI%b6dtZACTe~FNC3F?UnCGhL(nG
zTwG6~;S4}d9s^!LehUIagoi=_YC5hq>wFX#h5U1<}ec
zf0gC($25>x3RVGNaF;(G!TOHWu=9BYbc(gv`q7x%i^w03fE>OyTR)==x<^#g5Feat
zB+DLM4GRH7=AhY%Cv|hKK9H#+7a2CoXjuF9hpUx0
zaYe}^FnERrXd+OI!BUSa0-y*i;%}T3jYqIYE6xBLa>MZ#oX0!Xy(BziZ*MsHHmh@m
z+?^}r)X`h@8%eH$xK!=Fga|X$e9+tFNAL3~0Ea|o@)D#p8tqFGPU$DT6?Jb)SUg^^
z=wUlTLRU)(IGsW?&cF_tXl6uQIDwn=<4eEej=bTte{#)XzZ(7(_uI*j
z4=qARLb^A`UP|NXcU8-yZD5#DK~U&G9xHAI6Sx(+=O5MG_tl+${`h0<&)3*uprdfN
zXFk56yjKLh1pu0Xwz!3d?k3a8w(Jr^vvyVoDoS>RNH^Wr6E6tvuki?QzjN9BHPMk>
zpY8kNTYvwg;bYDX7iGqrq;jh!Z;l!c8Bx)&E9}CUWOdY%j?YYq60Hv2gVOQG`w^?d
z75Cyt;@E0Z47Y5;
z?zj`y6&+KIuvW-1Dc4Fhk4j-@5EKTPFbGJ6|BDv%Z(F%*a!A`fIOKV9$x3bydU^!bHM0N<*s8g{W
zLZM5u?hr|UuCfWc?@n0PV2viMRo*yjS|)iDu^Q>m3GSvt0GIfIbP66kO7bRO!K98`
z$A^Zz)r?q8io69UOuja9hm6pV%GhLYf%TwCW!_2b;x~ZeQpaPJ<}1H3>MgK$yeg*w
za%l4iL@@-qLuT&}w*OM~eW>NMaRT>|qk(K3wu&r>_1Nli=Y`3kAWf#*#!i?OEd=)(
zbpV73>U?;m%_s#w$u%Uh$Y)LaY3UA2AfHQ5udtSdP*OW3pUL~-ktv_q{Ir35MvqJh
zC#I!B-PtxU2Sp_rF&>WVE+(rHWi=Xh$RI9J!XIIah`f{T-I
za*Hlb(t%B_O=-T=9|3O#7wP
z+sh}xbbA&V^`qWiZpCUYZqFj3@;~|(d@bbeO}rDDykRQvV&t3?Wi5m_Q;|7;)D5#*
z3GbM$ICO1`<=QY6ZgAP+EV-V|Ts8a)MOjhriHK@;_y9+}$@t!k7u}
zo0wWla@(ja^ABojM%9|T3n=Y~SxED)if)w?&_9?^Y`B_I7sO@xtyO0Ps}#1`rc}
zcUY4VFSgNN(;5r$mzwrZ9yg7^Fg(7+a5cE_8=
z?KS|tgojgqA|VWVtOpoK_tVw_>oT2eA!YNMcj)5{6Ha^N!~&z9vyb2W50__7#hbJ%
z6l)+naADpsxt2L
z7`b7PUK*HG@Cw|}KQPCsMg$G!sm(@|C!4_+i-9cZL_jfQ7e*p&ne&@o)B4yW->)pw
zjar!Wl*rAV&XLWlGmsXgcTvPE!cqZO8V`l}%lIP9XmD9?8DH*rfAff)Wwv;o?m#6a
zCMuCnT_g>gBD*)|3g!_Ik22FjvNgXV`zMmL>YUyWH$Kw7dRrj;;O74*jW@kb)dYTH
za1*90Q)tGyDV3ev%XvzM!mtH9C8`+6&P~7wE735}A|zp~Nm%p+DXH>@P%ja6f@KXq
zPpT-qq-q(U!$3k(RQLqCNNP1w9LVLV6^HpdYYQHMMKL663<2f|_kdLcuQz`RbN~j>
zZRtHxiLd!%C&8;TEj1oV~3fYCk8QGK}Wd^`f7$@I1u8cmMPQ<6?hIAv~ch^TLQ
z1j}@7l&*oab!m-kGL@(~xx?r_EM=;=;-uXHiA*h(r>Ng7-o9NC9Ychxa(vJfw&gy|
zMEoz^+qcWnG1(4Ek6O_Gc*0@Z64^{m+tP@Qor+8l06vQJu-Mg+ScrCfwDJ)2*|e!6`!##corIME>I|K$!G|dXcvUGlBN}9v9x09npms9w|%({eBn+
z%Fdt$$S*OQKF+9G4TrWVc?3)b%B{*dEo4&ndkjvR6=%K1e~VElWGJPWl@Cx*b~5^g
ztkWVPDjwz$5ME!@7w2#-O+u6`Cu}`6!t-2oTjs>3k3k?*JfWl-RB4AIYr+-^7=cpi
zVc+L+HZ{V;K1^X2(aS|#!DLCSkKaX}%qpdvCYH+aqxbThODePirpk+$b49NOLD#sV
zLcwg%iVBlI$AXeb3+pWBin10BgcQhz|3D#ShP26AWn*M5=feEXWi4f4iinJ?y#*!u
zjyDQ3nKX5oX-gIXIBcgo_%Yo*=^4grs1XgJmF?uO_$!uSyx08DZW%lBp5g7`l<>6s
z!9cr3sVZ!43#jBd6%oP~JYUc@g7fs~;c@Yu&ysi;89Z=Q{~mD!%yE{-t}M5^!9C~B
z!Cq>4->t|E$csXECiv~brNn9^-eikQwNu?9#;Q?qBW%@Eq}KlahQ>!zz-_R>)BPfK
zD)2DyvvU985m=_n_JEuL>Wv9H$OQU=QtE_Gg}Qjm3d=&c82ooeMeHa|6fF#WF!1h2
zceolUkS=s8=d6Z20$p{2mqXn^_y${z1`?-+AT>E$p2xUP@|99!O;8}|0a>nKz9{4k
zH4Ywy{c?k1e7L@X(q8bk(2Jj7;qVA9yI!Z=J-$RL`io}UySzC2nLpRMjF|{Z4AOGi
zI&1qUF!FNz=(POeVz{l3lgnBYWv5QzwD3Rt-0Qbd=>D|l(3jrHf`T)!n`UE}ozgZm
z*~da&tQN10SgOC${k$zsad~m+Uml|_LBIPm&Q)7XlOOIMXFf_1`l=5+{{}qCQ{(l+
zm)GDDWb{^#41ODo@44cM;DeFJoUJ%IJ|wPs$Zj+q7-US9_!DD9^};DKMbV8S@Pq7z
zM}SAuXB&TYgP{zKyV)e?o?*}m-WRmv
zo1j8uNq|EWV&TK>SMW9o-uwwF3=24&paj}T7{6Er*#C0vN#Ag9lup#U#A8IR@8a4d
z3$9FEC!Y^>i`;cW=?Ix`*3Xe96{1XfQk6sKo?qcxS>bXZQ`ym%Q3-%{J)gm06MvrgB)_(a7q`rXsEi&#hrLaA0|=;3A^G=K!rV(Pz+9x*~v
zB{HrurgDm$M2{}2Jr3@OQL(zg4grSKyetU@qKHiZ=Mh4o3cY?m09)`{fn1;|&yDf`
zu-8{D4z*>M@IWAYX|;8?tm{yfFsKzu&f{nvzgv&RvibwH8{SXnBcBUW{z!(;Z=@z=
zdRs99nRiy|T#?S!{sQ7ErJCPj5RdocA&7zPKx8xYwrI5EJPZ%%4P^B@RZ~>ViEWj%
zuc{bHhhfT7CHE;>3R?36^rUDbX)KS3
zw33>FOoKTU4`bFO`6bzy4`)x;CKKayOm#4IJ6a=R=kQE9an~)L1W(bc7=tW4_f!W4
zwAa-=g;g=|CSnytUPoFivJA+3&5t8*OhMjde!z$w2iX}V1W
z00*!%%K~te*FGrxw)J&<>kr|Umro);X&UbIsy;
zgb`d4@n}VxOru~T*wo-mu*ad-=)b%d}|RZ6lf*!@E9`9L;m2ipYm73@MetL)uSn+_C(yh<*q*8VZ=u9fg10FuZG{SARAo_2V4h3;9h3kvS
zju{Kt64Q(KDwG3yy9!=m>-K`m%iae)%XSxLJ9cOd)eabtQplD%PJl{b8Vc$`i^5_h
zFAiAc_SS2Bf5ZYoM4;VC*m>7bHTGbS#dQg$9v-n6U0hyg19j&iaO!Kqx93_MR?bH!}7YAGzWHK5EQ_)6Nk
z_~iPHr#j`aCRhz9jEusj@4bFtQ)F6VHD6qG@A_Zr&A#9LbRo0PJDn9IB1nz(R-9_3
zK!*t-(D_Gb
z!0L$XEff*NA(B;sEPyE1fCeIJ$p#%jq5QXUolk`5Vw)3TWSK@!J?zazK0VkhJObD#
zs=gxUHdu%*hXZ6(z}`PZS|L`aP)L&@?>u7duqh3H^#mZmeeupw>$%sjcRxETdlWyH
zrfgg_k|n9dBQx}7pM5c+474f)4g3j;K`#l9?2|7>wWHONt!!d?6_!#1))g>eRw=z&
znUD%VXQ*Fo+7}U0%+|juAfXUu4Xg_21H*p!t0APC4lgF75{I%z8C4Oi@?=!3U48-O
zwNo-G?1r3j$&ffDU&2S4O)d!%r`n~+W$PoNVrJ^KBV+TdlTU??j@YBXbR1;kJ#c_y
zTGnAU6?QOj0qEtUO>5uc(2r72(urXEZ#MLMm<8Ups~TQ
z1|h?8dUGQOfc-$>g$O5x69kMWI5YU|lwcV}b;X-_SmXJ7@mg{@&^7|Q3Rh>jC;F%+
zKH4!p+7%z|vBAnCpkdL&`{Em*$WdCph1%l4x+Qgt!t`xX*f(Khok&PCsbD*g;BksW
zDnT3~hX%29e(SX7w?1-U)9+omdndJL5~MTT_+I9`Nk`g|PhNNjNB)s=nhziR`oHJz7EF7`~A2jE@?8b9^8GzWVGPIe?%^pUp_W_N*4IU3bPo|gS$J<`Na`#
zR4;*h1`_bwc)%ibdPy9$@c$CZT`$l9EMnu)J^VUiq(A)oUp@*vkFR~$-_U8)sr-iY
z8s2D77)5OdB2NSLi-PtzdT1buL^yHf=&(PZSt2@Z;o!GT8#IZ}c0Rpb&}`r8
z>2f*WjML!}s41D`kCzpLlpzB}KTv>1fC!U@DU%mR;MJB%HRBJCG21
zLU>KEwKTy9ZU>Vs`)Zc!L%AmwK@C;b-XxlTyLK3f?&=
z-i!E&L`z|F5HFSfTu2R(09(of5f;KjLEsU11948KzCLOSJeMLi4xrd=5S|p|2I}xr
zrv<$|p0i(64f4lmdQKr0ezV^_LxY%Z%KE_yNy^$`>z9w%79qjnSWV~X+2YN+^G-AJ
zjrOb&>6s5fQbwjNT>w%Wxrr}NK>^uCK!-;FcE=?8X9oHI{V!17JLT0yI78psxVY@o
zz=fw5D<4uMh@*f{PT{>F?>bQeCNO0gkD9lnY|)r?7LP!30b1jF>Fst`DBmseFdzWM
z@Jr;iCAHY=Zg*fX%x>VuhqIHcKk-FtGHk2F3cFFZ_fgrF!?#d*SVzfrm~Qa6QqJO0yjO~}5PIo&g-#~i0GNj{A*>?=d&VRm
z%*RAVk5L9BUE4kGeE|FI1kx{uT95~4p2-wE0t;inzO?fNF)lYU4Jgk
z?{@GkR9uDj8HsofztMORo3@B5!`aM|svIk5S`~o{<6+uzZh!)b2sO_L4g$Y*dExAE
z4x~B|YH1t?voXgYJwkG3S(i0PVMPuBhh^0%tf*bevUZxG`=7Xd`L}nEe-|gt#uIE^
zKxZa*a1#OL0CXIA0mR1M_^wfQTjL+F(_i2Fc*du1fBX^Y<-c@JMI)Sc2m$xqtA9B~
zNkw`mg5tm}0iid3gwKe=1bZV8Tji7Zd9UC7;byQH
z&|c|tWqV8;CmC$5yfqv2Adar`wuzI>2rz~rhRz*I>x{GA!w4b=ivodkBw%Qah%2df
zd;vZdf`K!~CsBU6Q}6aq0gt=t{#cdv5W7KOPCpNS1X1u-I4cmI!x#p?O%Z{@zQ-Y{
z@xO7J^@l^;6U6R};)aMn<7u+2*l42fcoqByKrDj?gz+URL4&fu_Q3vYHBO-)et=mh
zPDwX}g8LEVP$yQ{$n<_u(mA*#j1Ku!%|QAfk}vOn8!2^)JXA9=Opz#drB;A{QnR
zy}uQ%t`Qu!SW-*V;n(Toj}=;D_=CY5Sd?loyCKf6f`d@5`}k?XP&2(UjFTbMlCeC%
zP~liUVj67Mn+6N=N7_PSJ>oac{PvfQxEdX3NQd9FGVKry2S-c5h;LC0*1I1+#N?en
zqsY%l1)Cx2(6jT=@QKkL?DAuT44>#j5iMq1DSp_VP?S*nP{fME9aEpdt`?%hgJ1^%
zkL+BGOt{+(qL>;%c89Ox75-x7Y(Aul0Wir9ynCP>!n
zN)w2tkilTYMz4Lb)vzx%9fpF2%A7zu^(%}FrkxrEii>w(Saf|OO0iop0%-=L0YS;3
zAtA|e@#1xrya?DIp;G9YAA72Z4LBME8Iw{h&Z_D|GP}kTLIPufa17;#c&IqH3d2Bz
zBIr#THV=+rFe>(atT0-Vj$v>q4{sTl@**-AD}hFJz2FV4ydWFv;2Io-tc2r;I~o
zo#yihNTq3GF~&GdJ-RE@f&YO+2SUW17)a~WM0%6_NQooM9J9epSV$pzO5&u=BNu^%
zUVTT}O?yJ+ZAc-Hv=9&!tOU;%)CX0`M+sUIB%ILU8bqB>kI>SvAew`~vZ{f?x)7A-
z5g3{a&IfGyW1%((dM?JQCnYH$_Xj;cTy-H_sUW}{XhJXz#d5)n$UQ;MtT8q$3Dd^7(#_>~xLOZdYWDLkKtGGWlI8Uo{vhfnu|nPSMOqge`>
zW|L3d6Trcp-OXCRSlMK7$J$n!3k<}gH56bxOlLAeNLt7eiQN)TuAiJcP@0##{a7xFb{uwAt2~uSmF!5xqG01}<)oEjrw5Mpy3?l^*Z$@0M4ChBaRng!=
zw9{HcSW{R%+>qcAm_+9g4vn3MrBN9%Epv~9=siH?5-yI-LEM9aQLo^%h~;?4bVQ=l
z={9d8cr1DwMeqU3h2|%$0j(4`ijQ-c9C^$64U%+(4rUt?0YXtuUO7t?ZH3h{C)N9}
z=^O_-Y(Gkw>0v{^$XqyJU_P=A340+2E-#fNjXX?VvB7ajfCtT^!y>>>ENQeQZ;0VU
zj~O9!gYB1CYx|jL0Q(pbX?1BuUopd;O$R%Sl#aA?MX{_ig01mHdVQ+OV()`yei*U}Mw2
z!pQ|?LYu~W9mpZv0Iu~*;ls4m?jrMHvl&4}h50%FEMS5;Pd${9s>Dsk$j;wAy#)UK
zXNOZ1J*sOQko0MWoZ26>FVip<%=Ap8w^_D6ZFt)03JCR2a*owj+
zE7eZq5wHauH_kOjX0a2q*nv@NifuqKf)&|;&r9q;vW;RkAddhi5(HOX-VUVLM9c={
z5lrrsokTpjVjIa+8@ScAdK>AAC+2Jc@?$MCk~kr-Y$uH*YQ>aPqhP-p
zAW$JA>BxxLwWTYKmwggDigQz89ys}tLdK`|76hhco||yHM}Z4665L$kf;`eL$WU<8
z>Vo`u*{g)9Wq2Vu28Tm4qZr9)gM%~$+Q_OzwBQy8Yd~P=3L-Qhne;dm0DbcrArqCz
zmX2shK8uCn^8}#qxU`ADc)bDI|O_*
zra@d&Eu2u(=*ddlDr3ioILrZRPZ##c;1Yx3$dNS1Fg6w4ffdFhP=0b9Qp7Xlorda
zEiR-p5FVmDs|x&#WmVl5Rot|VE-Lt=*s6lVGA}Eys)C6Jk>ZTY${A{2c2%8{X=}e<
zZ$yqd&PBwhdL-Ht@=BgJk`=gH12JWS)18<97S1N~8}KETyEDZdM!K>hWe2VeU>)Ee
z0u&rx7lxr!k^h%I7v5V)aku{Q4Fy-lx5)KL-%5`Qe;Oi
zgqK|$!k+>U0o-b=$H@-kRfVf_1Wf@i4TU8zXKClrulyF_A7h6k_bk8HZ^4#^ga>ul
z4AP_nTlzffzi5|5kbqIL0W<_+C=xs^2Ae^G&)T2cXHEi)P48Mru-sU>bW`Nxw3iU-
z@)*jN#dD$VP*EAQiocDyNzR=gUaO_^0#HN4Xp&WqmTXb3;8
z+FPV^O{^JlLntkYT;EBIe_yw&azTW_+RwBCrnY>d+Njl21~4Z|Kubh*5`
zxU`E4)YIXv0Qlf!&1&{Zq<5-|>oqEhL^u@mk@sIVG%6afNtvE64j~w!G}7R-{aSWR
zlaotveDT;;@ArC*io&X5MgJNV{gc%r_8Ju(e#KcNdUk(}isBUG5)}`Fxa?vEhucEbGQ5yE;%BJwc?>UhLZovXi*nXN@i5cF
z&F5%JHX0Aesdy%ZHbs0jIkcHO{#6s0&J{;Cac~JoHf!n5`0%%dBAc)AY8AL&dAvHd
zs!ri9?S;-EZxq1%97iF%#;aF=LWr&EYU0(k)Oa<+KCJO-E-1GpBhyq-BqelRKpEdD{r$>IvUgjt^kH8wqhGkSr6kF^h
zxMYS{ML3eZkTHLYPhM<{fwtx-wv)0BqS&v9g+HN&Ln&*mN=Am)nK{65t({aj)_Uhf
z5DR;|!mEffU=`Ho6oF`h9yBUDsfYzMBr8z1qhDn!riJot%Impc_Np0+-rF@Ci)A1d
z3{|`Fh=urAHvzGLCFA3QGhzV^i950)7HUE2pFOjhz^nTiI&SGb?%FG2AvGTa*%q1Z
z>aZ63!`|Z#*rZIav=d?>7-A_-=~u)8;C}!?hCmyEOFDW%C%TmJ`#G=oxC3l9qA#pZ
zLd2yT%dhvixq#~{Vxjmw?m%C@h&R4V%0XH6#LO8G3$WjmhdFdb2?vGrD@tfcCL?|_
z-Qy0KjK;y@)nr_5GG6($SH!~WJ#GWR67WNrwxJthAsAyR#^EbsK^0yJSulZl_=;F~
zMJynr1?=1``Fz%fSP0a{i`YoH5DRiP>wE8)3Bi
z8}_kPeMKz1@&2O_3kCK_<8qS`)O$rNydoA1#6rLiW!i>rh=pK`r5J~=h=o_g
z0wru;QlaQI$HImq76P^LA~sSk#KL|xCt?8&<3>_4V!TZaIoee=O?ALQ57SK?V
z3Lw}_ITk|HGQ5y^?tH)A!L410hs1@NLIjP17R6vS8*ZL?F*WxLhb!f4i%)U-J(D)XX~<1iDV!f;SQWk3bk
ztXXg93spRZD#j$&ZgI(Y!y`zp-NIjoN`J(-m$$!g0Tk%hDVl%M?k&eh?+u$d0(rR{4T1N1Z+}f)Wiu<
z6AZDGpvfzu<~0Y1taOKDemdm|XGHY27P6EYDr(*!*&GUVZhIZn%Y)7Jy@Fhcl$Q44
z>3%WZ<|24hc+*Tr`J4*6Kd+C^!(Dqf)91fd&6SLTX
z(WT@(aLfmkL7KgLNK;7}hI#d52UOA*>pJn46my$vy5b#fu1sfeX^)Q{FfHV)9M+ZLH=o}z{YI_kIN%-0n;Fn06
zAyL|XGcTg1>4c~;jHH7-!*iLTYRT?~AZjpfh0rEsjNyXBA8$PGFYo?~e4!76`LDiE
zSCucvt;#_K4Yl7f8=@veEyD|$2YX=;UI7n&*6GUV75){qMp7%Bu#m>8oN!Wq_T`hB
zwiL(qPANMNWPkXF%QS&QPyTQkSVH?yb_^+E=MyB;%_{n
zCO+1UK-3)UZC?>JvmlOS
zQNS_o-5^BG!Cp>84H{0SSF>OIZwM)0}L$2X&EDm^Mg
z5?g~;M9uF4Q4_F9nNbrbL`^WnQi3M0h#DNkUaRVi@4h1T^opn%5Nv49*>zSIN#S$-
zcrn5~huLVzz@+(WRUL9vaoF>2OztV~c09UAbt}ZHP$%>T2NQfa8Qddu1&2xP&)1cT
z#dHkq{N2;b?rHyL6KS2{_sX~MEuN+c3-j_IYGA*q2#8x%9W<0CW2UM)A(PQ?N+p^w
zox$D6J0C2DU%lJWVDU6VWpz9(Bam+qC>$b+4TY#9(JDACBhf-I)Q14jAzb|=Tv~{W
z@9UOAllcXR*FsF(OWQ|2qyAXCLfvo)gJbOW2lB1UjA
z#nSSi^ysB^jNmy%%?D~CgUNRab@RFo=HC4j+<||I>!2TRWN~V!hVkTP^f!iYh!4Q~~P?w7qpy98vczh`R=NcXxLP5Hz?G
zAh<(AV6?(R;I;K3zmaBVy|Oy~Q(c{8(Sy*2Y@z4@zFb#>o+>Yly#*|)l?uAr2D
zJgBiCn232`2iMq4GcYN@B6GZ77Mh;y5dTLT{k6Z$A_8X|os>>-0qed*bW?)5(3Wgn
z5aTkMd>=uiwp^>EBO*(I77h+Y`<-~sYu>J$(dG&<4-m5d0}YcW@b@Y)7{?O-z&;vF
zEp*$`Dy*}uEl<&i~gXa*E`T&gC?+6D0Kb;5k}6LkFh%jW$^nNMLiaJBY{^@!xSs{6XJ
z2l|<4QUJGFmx9jSL(@>whx!-{{Eff6nj`o1m>c|%6MB^8y}Klcz9u)X9iBnm(&>xF>=TT#4f=BIDhtFnGdKb0P@2sg<227DIFnaK2KpBQ~52
zWrs#178q)Ko_A3zURL{ZCpNlCZ$1x7IEeSizC1x5S^$
zy8c0o!2_4bhxpZ12NitZ1-RkwjBGNCcc+`5dspgU60-K9oHOhj!j-&|D|vHnm?v+4
z4`++Tg*kO3;$f9XSw6p$-2hY{&YaSW?X|c4U&@_Ketqi4Jv`zQMBIqkLG{H~`Mf(@
znDazG`F3>|@InsYauR)ScPbX09m+e$NEQ(5JL$giVMQ!+Q1-;i`V!WyUeN1qtRW>3$(Xu`EMZl#OmwkWuj5-*
zNcz(o-Iew^WO<#Pfh~`;PC_LFBg4V94j$jo^~N^)k6iD!A6VTPtZ)yeq13}hoRc1u
zE?Isi$p}A!q!G1IF-}IPcXi5{O37<8r_9Fx8O{)wJx`0_FetnGuKLRp*2tZaT&V_f
zH8$eO!066_218ilr>_hr0y^=~R5ajaI|X#~f0n=9CP!_*s5%-NS&yhylhWt~2bRg2
zapgk9V8^vl&a?hFPkBW+bLINY`;MD{;()Y2YWL-3jf9-HWe8G{oHB3}j~UCO^|9*q
z&(VceyB}+UKs&U!j79OfH$+xP>6}W3aahJ|cQ6MQd7x-w0D2-`Ag^T9A2GjB&$if@
zTHw46Wes#2!#6nkU9$7k+xi7M@-PgqJPKT;?81s$MaR4yBvJG`G$Jv_EQ>8=y8sne
zFWq)GFTXg{L~$4^E|{Kg5HLt>5^=+#F&^+Y!w^AvjsC8aVrFFTaN#LaCjp!J7!1jO
zfZPvbTV~PXzl56ncU^-aeO^x<-e^Z^^e&pcEb!G2)&s9z+CH~8unE9I$_2=Dki0Z!
zXAhe0#M52|^~V_dCcwd7aCq)y$#TIdBTV>MxkUzgJ%*3-!Gpq<1wDGXWoTRK-dqn;
zC(susDUVaP?2>|v!rSL3W546yKFBS?0=p!dkFh)gSi|6?OZhVEueyYT*5_ih(0i)v
z9x0@rSNHeW`BpWrpvCGP*L87=*KL+w+&-|TtWH@LRCaVILMAWlo-uIHc67-3#B;vj
zV~cCQBESV823hMgvBR61NmYbg!Bt1_r0%{z|E<01@w7p~|JFc3;{3xEugwADZ#Wy{2!XzZ3_t{Tshcu+fYBVBEh6IU(P_xjqAaH-Iqb
ziaPj|D3-X(YNW8x*q<)@4fFWNC$c|Yf{p8?xw06&#TaD{N
zNaL*2NE(l>p4@_s{}#A#Ftn3BaS@j}W@ri`>H0#Pf`pOPLY~RZCQ=fgq^(HbN&r79
zSPwh%@r6y{E*GLCNeh#VJrtI4c^xSNDHXZpP%SE|mA$1RO-Q!LM$VizmFXN`tKAd^
zR-=x?6h4(GLkyWzLgU~jyi!lA=1I3V-*de2@XMs>*(own
za(R{4#(=+j3E7{W1~_6RmT7ev)L8f7@FpCUCy_zh-opc#es53rWsujVd;R87eM|LT
z@5;r!ukg`>*A263t#%d8P^=6aW}H~!WlCY{D)$L**2IhWue-du-Yp=xD;f7-_NH0?
zmi40q*#=HLl~CnKaw^*mzKZYk+)B<%6nd;-9!2HLcb1cRmLTmn6dACy=e
z03E3)xUdKS%Hi(*tsare6MsMPb1g^IZ)LbxhGKL-?5cuSsE!&rZ-uZ5+2H(~Z{Hm{
z9V$XB)BA&Tx@=#P`rG{uZBEqCasG16OXubdkkRjg+{3kP8}N~l0QB+li3CB;DrGQ{
z3c^i(_jWsHutzqY2_HZ}$7PrL^{3^II(3_;bju!c>|;}C=#PvZG2&3?InUYjvTjYW
z9og{&+=#sK`gOJJnip!`e2HW1<>V+oX}uWsAIY2!Wo@
z)>7^_!A$>!H`%oUo_BlU@M21nWu1%VlcT9kY0|}ZuNWiPeXdR+_;u0wb;d}ao$len
z199#|`8t(HX8%hWN6vA4$+pb|9x8@IvnML-TS#mRp{42>aK5C8)}rJc?L14q+D_cc
zT*PeFd5RHE^}O2!cpxcf^}>Rfrti~81skm|bZ)aPH~s1_O~o>pDl6#)#YPZsEyRIE
zSx(6YLn2ATwHw!L(_Tgtv49N%)d`n+k?ipok$Ed5m6ipN#od<-*Zplb|8jnqc#cm0
z=sjL;PD*KhGr*25Vq?6fjm^7t^FmCo$Su4VK8xV|aVyBjCL*@z4K+_-6>t;xH3zBI
z@90(GLzs@BB`!j>@cIptuCau`IOlJ?_fc%Vt1hJ1Xl^qXdi}N9%MYoiZcexP3p?(Q
zQ@76nvRl+s)!X)Dz^>XUTRcAuZ(sXzN|tLB!HUntIu^uQIyA#>ss|ZD3XNl(CerZZ
zTEcG;X!ANKE!70#fo6S(^6wjAD>R6Mc_PR)HVf<z%Yugli;o{(>@UYX%0Ef|15&f(~0hlcTi%>n7AF#WJ7
z(p@@HS0SnD53j#=H2T-cRXj5gx!y`cMQzZ`xdtGAF2Z?~y;Gu}bmmXIOp_|fc5a(c
z?6GnFwSW#0OEAgs0U-jcdTRJ~T<+I<^#r+Ipu4tFep|CuyH{~E(b!RFIv3RtUzXXH6H@4F2)#z}ZZMYRJ{LBh
z)?pHskd$!wl1{hj%W==Ff6w_kyK%WUu1qR`6A}`9pp^%wcK1Z3@|ip*TUH}cO4z^%fjtO
zcb2(^WY|%}tu7FwzehJox9R!xNaL=<=3kPqnMGE(lPe(97BSDA{(&&h$yeMDc=hohgmKAgsWbbufN6I?qV
zXY?fq6g`}7{Zmr3VU#n)uXg};6_{C;@9NzX*2pMm?fImbm-wEDTbL45EsqE44j&P1
zJV;#TwP~JhgTY>r7^CohGFIp(9tycUfU(kMlhT)^X3$_@U=pg&*a!y{gU$|YY^Ak?
z70UH%Q);`q$ik11I>Bhs!`klp2ew|p1epb)KL?7XoTPO}xear4JtY&_S-(m0m|7}a
z$Vx!U+lFPeG^7H(!Yi-f6^m(U?}x+keum`{R3TOp>by<6o
zh?UUr3|TLvLV|jCj@ow?HLS1DwyUzK$t)lnC9}^fVkF-DYqt`s(bX*hb1q1)w@JUY
zG}SlIWU|q9Dejn3pJVM_0_ECZVR^**$?=l(gB4P%7F5TdQB}v_Qwca{jwx&BBPQ2jfS486zWv7)FJV
zRDQ0c2%%uEoKJ^R)u14skMC;7SZ~sw(iSq>VYNIwc9q%a7L~`v5GBEiw3?OVvUC&I
zfVQ}9$%1F5?o^8^APOo6nyYIOhLI%8&&Sqa*I2V7_h=d@VHD
zWwh^ybH&3S-RBGs$Kj5t;9i?3n@5TFZ?*Awy=5u=6T0mzk5{y8z;@8tv(MauH&jVb
z&$_dKqCzt}16}yG^MJC=POJKI;Q`lfd1iJ=^8P^Q2uF^eR}S57_%KlJ@8+Io{3LOA
z@Qhbxz_Hoh&Ei5>?Mp6m#c{OfwdF*Yh7#0YC7?bvnrXt_o^J9r`AF1A#0~UW)VllvIwaBgH#`?#TXRelLanmH>L=Y&F
zq5HSVJ;p$v`2_2y3AI|giJ1T>EhYMIedg7*6Mkj}Fl|hbu?U$AVjlTVP&DxNPX3k_
z0vaYFwyQs0La7Cc%O~oDQNJvry=L8#*1_t24ce#;M7e}$&ZF)UzSZ=wM81V!U+1y>
zR-5N}Ti!Nve*FlD$GW(Ew76cfDKnk9^8k^t^oAZO+6aB*1j?67Q$PvvQ_|Dcd(P+d
zV>e8VbN}o`_2bFsRYz&5nU$zW$e8&NdD{?_mxgZz$Q%}SozUXVZN&=NuGXZYLbw**
zJX_7%+WMkfSasD=V-{^DE_?p?Ho3Q)4rNgMi+9z&ux@ptEc@>d`XRdA^aQA8R@$(6
zJKW!nOKMQn5)ZcHZ3-Lbv-)S}H4$9jWgC@61J@9Fkv`!cAv9}!Itq5od4{L0<->Up
zggbBDACJ}#pUwy0e*B!=4l9kjQF=KKpu;>gtAASX6d}{bUZjH4MMDY&YAMF`eEQ^W
zSxTQl@+pd0xt5Wx@M}~M6>0d6OhpFZjtpByXRtzx7q*y*ZFgUX%aruVgXG?m$EP)l
z>3iMqVh`zY`*?RlUUsu>dzvZs`SaWJflT!K2Y-ClTrj;NG-vo<*98b`Jd1%PN4B!{
z8|`Yr5kU9PPzQO9>QG|fXi;*|`m~6N3FO&c@1pa#7NmuroBPRc!zP$JF5cUH$*bR-fc!zG?R*mW1aww@K!pS%X_Vgi(1UvHuwNcclD$iib
z{E#ei?*fclu9_2TWtZMFNp<(5A<~lefUBSoq0o(bIF=}ZTqV5*`-n-nAC!u?-|~D&
zaahbd2F#Ifg7ID1X#0QP*Vvns4Y;V|!*rY;eO6DTJEUK)q&-W8mP
zM3!6TbIUEY+Pu&&rH1m8sB&;V8_ff?MVw;{RX;o#s}48GfQO5YDENy4FxbqxXE_*h
zWcdv)(?&^X2wktM=Ld^W66uLP1d~$B5)aQ~(20QVc?`fWcE&)0e7ZfqSkX!e);qQz
zyq*X1$40p~0rD=*`FAPK-LE(5A1Vs$OA_h3Pr|dOI_Z%er&f-h2sJ0wv>CAaBp3YX
z!+I*NH1lWYQ_Gvxp2n>3I+(e#A}Z65uNiL<0tt!
zM?yJ!(%05P#Ine6+Mx*cF>2>a5aCO0@_AOxbom
zm2$!?UfU|KN=V55WKwIMoN($Wax&MM*OscA4>~C@Sf>vH@0)J0ar7KGP7Eo
zP9;N;n*?m;miv%5l4-lus$?eoujl6pKUdPhEDa=YrGGI}Ub?FG(nsGZ!
z&{rH6C!Zj##nv@UVu%ktz48%(8PUEYRda-|yDV&*>s!XnVHQvZscb@2_}7%$$gq@a
z|N7KH4-M4mh-rsG$4^5?1wFXKBgYmn2(BgZSES{cWd0-j7uvaI9-TG^40lB=JE
z?QVh+^RqzCP{`x&8&im1l^CGF-CdXvQeJLj^WBN~rLGL{2u;}2I_gzta>{1Js;>-Q
zT-i)%sc5kWovM6rwK3g*4R
zK5>u2GfLEx@u$`)jt*xE+AT+iG{`0&%eVYEZl4oj=0l!bQT<-BN*PL{652E#(gXx*!O)Z8
z0G13Twc(f!9yO&blBX?nUA&UedRRX6^JTS@YSAWk7F}Z}Ze2bh}czfeDW7F5T
zMyTAelwUuNL)Y=8xSm&M{wWO&-|=~q(xnETSxYRqwh=nEol-wI9ZnN3_VuyBU3GM(
zh`NC{|Hg8xT=%R}FIC!N_1%QHO~vBi##`LTZUsL}
zAs0hVo5+n^P?*|ygU*HU!qW|iZrmR!IFI7Q@QV!b*
zUh_REw#Og#+Nff+neyjH@|y;=RYWr_c1k6{I3b#m{S0ZT=fpp*>2oV+fi|knm`~m3
zGT9Z|7QO1^jd^p9?b{E5y07DXT5qDhct#N6{Viun4S9_G(&OVj*>n?})@77_4F`>7
zl|>iU#j4YYCw<`8J#bt6m=OH7oEhAAL1`&AU8-d8_^H>Kgx%Y6lU9=C$v*
zJ|kGG8D2NV>kwH^7O`*m?eLT3d*XC@gqGrVLi|XNA3$R^-D*Sq$(P;@#Y6LFxkc|$
zahEW&)4R;zHvYwEAf)fZTz4@_+txBvB-v}TN6G_ndnY}EG^R>rTyUycu7V)x0n$#x
zH(P=?VWLe+o{F$&YOmhEz60E%e_f5-3ze~66gk5yC*$87&|>PA2j1$t%ETP)Q*hMN_e}R#(nFBruw3OWn|q=9NVss>X+c2PZg!rU#240StI`1
zCPepsEdLZvH@Fjb`_LjY=W!jb%iAd#mY^5;ZqzQoFgNkzx5Zf9SBwcY7UJfG6sE{l
zjvbsvUOehylK@Tbz%Q!Jzu-(DV?}|^D6><$uL@3g7#;nc?c$tDr~bD59(&FfaRQg;
zT`~K-y9w*($se-!z6be{dy+~cuT<4O-I#c;=LY!#ek*biQ5x?0CkERMkTSCqKkh9c
z>c7sKsj?6cE*R9~#X$X}jM$Zzrgq9kbYQsi-#9bCby6t*+fQ9U@5T1%>tgR2mbZ&E
zW^XIf0T;R*)4|@psbYHk@^8+8{cq0QuuUr&qr}vUwxZJ*9R_1J8}1*h&#xQyxa@~e
zmoVN*u+ocd3twfcGY#mSKH-m#Gp}D@Ghksd7e_I%duZY!wX3x17I3nqv{36murx=^V=sINa_`8ZthQX!q@KuuA`YP_Yy6A1P$p_le@0?IpQ**
zddT21F^dQuFb54K0I5L1zjcU7_D-}YUR0l5E45)l5wirPN-y`fev6V$J{6m1c)u{{
zJ9dg3cJYx&=W;j;&~dNt=Cg^ZlFVQ87@lM*f1=$inLGTL8)^W3ZJna^V3LnXClS`y
z;)o*?)<@XZf)W^|i7rS;=bX}`Tr41VXjIAtuPz?%O?I=OXq@Y$-QDD!YgVd?E6?k@
zr1;h0>RH}kI{|(?q*IEtyAzh0{nJpcSUjF_@856kA8&@)NjM9Ju~^j4Ux=k%6#UdR
zx$Hbpy37ceURM=PL{=^UX^kOUuutC6b7rRXwMOrP)Rn!o9;vX+CcWB!G|?9HrqU+k
z5bI@bN{D1Klo&spjv(9$lSrT@`HG+Fi!G5@(5AEPBFze|09y)*UXV!0zN~iHAW=o6
z!BbRfTzd`{>B?`m5czzjIwfKn0P{B}Qa(+j1qGW1QZTNXGYb8Y42?~S@c?YYUu
z7Z3jE_VDT;o&Izbd+P;?%Iy041&}x`R4w>8X>^KG*>1u;-1LpKNQ;=$maHVNWDY~2
zP|bZ$dnt;p{-?zKzGVBmEzW|v+(}$WTim+K#_Z)Xo8LsTn*3F|5lfC}^LTPyRv
znF3XwCUY|&L&)m4mP5^Rt!N_e2jD7yhTmE3z{1%Xwjixa&l<5#X9(=!Fq^C5)
zK;h;&6!=Z|`M;F)%76a!94jck3YB+CsQ2!La{lB)vONkpu2$eN?-`4MYQrdelDnI%
zh40$i?NuDfgOi-)S?>M*gkoKBOK&1IpyXA)nw2!@a(UMEbM%`iDbk^qyL1xJc&cSi
zAJK)fM!|`ZuZhYEHJ=9qd4z1;8bhg8%SPx$!9ATzfElO1L7^jqMtr|0kKn6X-{;PGhy^d(W?A;M<2i_4268>c7sA}5amMMMGNJYf>{p?2$0N_KSM5!~3GmVXs7i
zH|+0UKg`@a5>7j|VDb~+0Y;X)E}4!HB>I4IoLkJhXc^Yumq=Oy;iZKqsJT4_KAtFr
z;X~Ng#kA_@6vZ!tz}Inic4(0I`-qU@!^c+|)ma-qG153@eLZm^7hCRMey6RugY{lc
z$8_e~V>T(`kw5>UR@sCj-<;6naHCujRcS8LV)z1N%5jazIB!Y10g9KOMaR7(v$~^3jIkD0QY=jgne=rCUC%Z#%
zI-k|$)6i^c<5FR-X`(IzCE&_vq~n?bMaXlHi}@r?T@p%x0{KfXQyg1oo3Z>?jx@MXc;&}K
zt@mqgWfydKjo5hE(p)z7qUVXv8b|vNPvJqtkDWh1QJ{r2eW*}>zqm2%p_KY+HtT;`V$Y489O)yEai*hdOX;v^0>k=HAQI
zp|keMa{by*(6@(lVD&pa(v{a9(UV)y&DQ-dLKmSaiEq;ujftUn!mC-;@?qnw!%Eq)
zGe?>GfhF0ol|zVApI5G_(dm}#6iH%vi45Vf?5rC#k+NfjE^WuFu`*(3-pn9wBJ2qQ
zOxjpZjGHRG9~j=kr$)icD79{WN3!bXSV7=ii`7j$nMHDzNf~zt;i8AZm2VBIqVY74KDJD=m6nV$sp)>KL(~eo;>G@k%HJB
zt@w>{=or%3S?ssNQ1SrxID5itDYN-+{Ie+jg*|RQk$rXqE1_Z}2;uAQxsas5!X}-U
z3?EgliN4SsicRy_i?Bks!G$Zs+Hl18}{Z7$VNxTJVSAvM_WCpG6ti6o(lWOF;oec@@@Wb!78WpROT;~e~Xa^OW?
z?m6=+ByYn{#o!qNh}BX$uS-!OQ5y*TqlZR-U~AEjmY33Z&A&F
z75Qskh_B?`mh}=cfXvBtY9&vnaLmSwZD3M#3gF_+w?Wu>8@E0_
z8f%rBY1D*4aHI1CPOeK6Wu38#QrfqQXyTflQMGD9mMF^?G?Wn32?uBKy@EX
zdmucHY#%|_uP_ETIlW9@OeQnqKEMpNcnX3@+N!AuL#W3c~mRCM-kuhCg?60reqNq6GzD>}9mHrRP@)
z5{o<9r`Oq+fT(4V$ONu}pfU${m8h3dXkp?s_wW({C#vo`xy*DB8&e5>l;WVeHFr5-
zR7Jgl<4E(9Ukm2kd)z05l#;8PziAN0rtn3@l5(=NHD)iI+p$O-R`zYMi~EJM8Kjle
zL1UA5uWrJxgrsOR!Fks*HFHYyv#g>xa<7%)fB$@8^2B=d$zWK$xSRak!Tj~9!U^N>pmj4G^3dJ5j0
zeylcr$5$V!&~_*EbhJM;sR=-8B_Yd{&hZ00tW~HgluFuDRV3{F$fLrks??}(fWblY
zIpS)f!m$&0fQqcZE{Ezd-aX|XKU%|o=dV?3vQP`ni>&6wbTiz|`W;Q|^qtE2Ofp`o
zvMreW^5<5b^YA#+BD{H3Td=gd=+#+j@Gf#E6k|`1&ALkIkN3~2e-1R)jTmwM@&+NX
z)&F)^uWZoIL1L)72#6_1se~%9ys2udSfX{y-n0?o)>!X@lma&w4sOooM$7kjrP_9*
z3YD{`$Dx|`a!EQ2=X{B2CoEmtK{nD9l~E%uD*7I&;_7DNf;|-}e55j=XoJ7e68E6Z
z5s|^7Y5i|8#R$y7-$~gJ;Jd8(z&4xKb)FHfnk|pzp3v3lJEd7d2b*;z)~Mmz4Tt|u
zCJ6%P-Fl|drPK6VU=z28Hb5ZT=ZnPX;pZv;!A+oY-D$b+N5@O!AHZq~`jCI&Zi2#d
zJ=>X>_QZ98zsxE2u&VfFj|at&N&Nedj$jxzt66I!?wCI`Hh#Hk1$Y#g1xOh0hX%2E
zt;3iP(d&kOGwXIO1HXmbgmVkmjVriMkNO_&Jj@h2eu|J97ab?4s66Mtywinb=GL*E
zxH1WtzmP_qY_U2SNgFK8h?b|hoGzCjHWf3<1Pr5IHUjf8r
z*uP|fAyqeZ{bFc`&ih&4ql~>Sl1G2#`sgWh!G?>0;E{)Ot@w(Eg#qEZi)epT64qpg
zOUFt-CUw`nhv`}{cYmSrk;Q>78I(t2cm^9rfcbW5=!ntr?fcs#_p>jf%EBE_{pC+V
z6&7>y8+5f_d++=6G4@?P=6sV-IJQ5BSb2V^h25f3EQ)<;?0jGyZu@o_vx5k5v3(^v
zVJ*49S4kdwS19-Pgi8G?M#tb>(gXM8Y{#kcbFo40=U>s@+Mn!X8HhF1pREr5iBeX)P_n+Lugg+Y&7rvPj$3OPqQF0lu#BC-kr<_|G^-blSkwv81TEw!<04D3o_eeSj6S^?KCZb?*a2
zIM$@v{8aJt7jT2o2C=12Ls^pV34JQ2tSrcJl>~SLOP}hlwc#8N#lE`W1pO8I<^HzyMiDe*Ohzr;Ena+0D2%iLyfl=nj$Z93srT9>Mly?i?_G|atkNn$GOn>)a
zEx=US6?<-lNuE(j-@!TZMDz2Xqt$U~rK)wC+_&>x4URk(wN*vd(mn}2
zk(=u7(QdBSD(k4w&f`}5CwZ)LmaKh+VB5cETlV$2^(zB)$A4esBEP75Y=jO6w`u4@^9)f$gAZDQ5#+)xa2F4cNB8Z3e0;2@0
zXzD~i|G4iR;PR0x8B)7>tCEsIMGA%a9aTHsUCFtmlb)Vquy6u9A?dX39=4+)ho45F
zJ+t9UVV^54*L)U#h6^`?Vio?yv+!*WLCmKSIRgV_*Vn3XTaK#EGe)IHCkJwcFIg#5
zGB)Ij@W<1_mC<+NL7E8Y3=|wHHIDG9m846)cuLyXgo-mhGFcQ*lG1A&$P6yD3`m@}
z(o0@we#}sG7PVCS$|g*Y5CJJX;=k?3QzfGs=TI4`MZUW6jZM_@1;nMu20i9J&pz)<
z^J(>sD?;Zdf^j?jUDl17(_gvvjesflI1LHskO{68PS>|IC>)%%c$_&%TkjO2Mz24xTyZO1Q&n
zR2-Zb!4);B1#-o+6$b6em@scLR;q4#dm8PCZ+v3xC|?v8q0-H?g`G+$UMy*ri(sm@
zC~WAE<6nRO1}7616UA!lNoSSYQ6yAFeDTLJvM5?m%ABdYh^q;cSVO%D^ZO?F&q0}^
zqhFsPIx>}!@a7!kC+x{4YVQ;8OjZm#vGHup4nymjN~eV73kkS@E0#>To`vhS3|uN|
zrlV7vZuk~P$&E2RU#4{KD0waD8}&jqld;n|+{+)HD%rG
z-jZ@RWo#!<)ry1Xp-TvX;5-y~S#mFbX_bYK#7afiq8#NEl!8)vqOnoP)+A(mkS4G*
z+w!QTitEJi35$`jY@-a`
z6h{WU?~(xIvUjRKY{MnXVf_i4)d>#PkI21g0e1V*=Gl6zT;;Z6f0VY)x}H1JgCYQMJ`MRv0J8;aIUQI{w8Ox%b#fluOXjVJ5C}txefdaPPZL=8wpfXM|UHMeFxFY%zT+0sZV=
z#_;cyOE~@Im~IAei?D}w
zz<;tlMkC-XhxSLP4T>1)BKTt#{^+{G`^va)A`dH!AlyjVl1!sUMltm7Lr(s#KaJYG
z`0r49balr~J8ZM;c5mwV$*M%|XWIkD#JD5I7y_{Y-1BTHVf`3}^{D=snVy-C(PLAa
z_XHg>XeqNX&HS#G
zgT@6WA)Q#)cuVZ>yAAa3LH~iNN|UJH&O{*5yX0N33HXF1CWejWylRla@jY4WuoVR}
z5`YJ}j~P6i?!{Mlv)sG~ZN&b8VH^i(0sR%B*LboskH~%!Cy&T;XW)TwnK9pElWzBC
ze+|u8{C$PjHa`qA2FuRLbvIkHSH`UYrpEav*-
zx^N>M#uVgI4o<^ZZB@782^<;~+m`a1F+qTWtmy%%v>}Es6|W45lsOEHN2n0Fp##3s
z40{qb2qY)&FEa76*Rtuy1BiLvL1<&l78`FW#KY#wDN(bwoapU@FdSB+e%Dsl%q~^N
z$78?>wUoxQcgAvNVG2c$@c;tZxe3JC#!r22GfUh}?!I~1cdFKjJmGv+{JGN!!486*
zh5DKuy1ax1C}TW~87Gi5H^ygXiH#c*8(0LrE4s}RQqVtBL_JT@oY)yc~N&6q94y33zgg9$$Ndj%Tq6F
zRb6{nzblbVyf-2{o+*$zDd?8lcF1NBtF_PDEf4}T31U;m>z7Pa?yB3*^9r=Ne%_BL
z7-?e!fF+nq;=q4g0)&$=_AywZIR=2@qJlt=z7)m%+_SmIUiJmuV^fnbn=%%lx?ckNta@NOkuBZr{`c-wu(Vs=V^qpdYd(h{NR%mTYvXky^JCIM`vKL%CMA1n89
zl=Lj4bw#6A8O$2iyrjc#RpZ1%qr%W;efnoh9jKn_7+gBXyDL
z1h*O4$A<#Iqmaui5R#8~3j|SeZKKQ@0#s>&L6n>6uw7W24%o+NS)*keX~Cdb_9oX!
z4SDD73A8w3oJ;?niS#{OB>u%*3E*qcyacdl1>C}Z&Lp^5hmUUsLL8N?fuQdXNI%sH
zkCp4qI}3z1?f-SO=OPZ2urv<_N&lh=1c8MXscQi&v;eyQ5?W^VPmCNCn!hJtx{wbI
z(7W*mk}TMh$%~f(Axdy0MNb;FD3vUm00~bQygf8
zuk~D&YIs6a(EU6i4wPQu`3@ccaA1~qy>PR+b1#D6ocy2R)|p^2FUN+~#Rb<4H)~k(
zU{FF21@6c8wq8#BE>s){7s`tUu#B^B76+~t?q-|*2MxS3YyTWkLAMt;7he~|@oSkD
za`8uhivuwkYmfnWr9nb+r5K-SBtt2G&QpRxg|h+41o@j8{g_oU3_QR^-<{y=VZM(=
z7>*-#1usW3bukwRamUbiNzalfZ9{A>MgId?;gz3tfzaGNxY_@Xs{BBGqyTV=*{}e3
znVsEeLsQYuL&wtT3y0^^m%xhB|h^z;Q47Pq4W@W^$gjBmg`j
zjn0B@od-7bE_Fi(#$&Yq*oc2Iu(#Wp3;BgGqAr7DaQ|^|kl??(B$P}BpnKk8pEV32
zHxB|)i!8%}G48`94xE!nMd^wL7~>u*1G>M0dnL?v(MJRKn&F}_2566_3Ww~n1z(?k
zge?VQrTz?Rb6g-D6`YdyL2;m|8kn5pAe^{zFqw=dT_k{A>zoq6q|t)_P|(Z-7=w8V
zP@5;A%s7B@Z?JeM*VTSn1_N&}XA*Lg;H?%KfLC}87YO>6Jv>DLo3HSXQme#jwY!!g
zS-s$Xv0*l^&z2Fu={&2jO*|fr0(U8$4c(=_rwhgwN|6tk!ay*L=I*;BfTq~CkelOm
zd{6+opG}eAGug?Q*S_kc`65Q>F2ywwZ>bHQ5!W?x&XUZzp@M&N;Uy0IybV?;g5G*?
zAi9p)?X2Ruznj(pTc37isX1E$m%aRuCLgDpO;)ioipG?MKABcXV5zjt=+>{ynk2<1&c2WaS2pXAmC4jSn&NAt+fbcL(nRJA%;(u)V
z{7-d$X#fsV({aGg0gOJ+%zxtd&pDJr9J6xXf-{$x*?q=7)q?=uy{F_YV*+pgyORb3
z9k-FOuJj+sm{^659r%#I8G_v$=L<_&`7Hr#lt@MHigx?BDG*vZC<_7&SUMlhK!K5j
z;7SKZ;!q}tPzEegee7mJVd(eQLjnuA$KFF=#s#Gyb|v5G;QfnX8eA~oH93!2=Y4hm
z<>+%DsKDB8!d~DQ4b^Od1rpF6{vSjN{x3wN7Wh7gp4YI09G(S3uvq}3!v72$2G}eV
z2>r(_3?8ZdGfDr<0{?rE1-OW0!Gh1Eizf&q{ULa&N8Qy(Ih%_=cNhR#^jJpf!V0GU
zM>j)cFsFJQz(+>(#DPs`u@IZ%jdqmBXoUP_cU*yBDX+QHWa^&h69-PG27)5$z*vlQ
zSb^^1dNzUvE3PkCamT#s(E*mTg#fU$Ia=Dqnv~%E0$8G0pn@yyWvAR%7;rx;hsKEk
z$H;*o6eN4%;~C<0i$G9=)Ck|me>BN1D)PTUO!q$!D>ec{>=#HkP>UBF+5bTDzz_ph
z-O3#_9mH7+PjHSn|EVHPu#g80xzy+LFaK(wvca4=B$%+$b2LF9tAE`3uMThwJ^xpU
z-e0ijS$v)Se<6B6%3}vMlrCFb*v;#gA2ApBqKiM#Ey42e{{dm~|3R3*{~rj$0pLw_
z5`)Xwwjg*=2^}$x(c0vvh}Et-HNYk%Y?@+;F|NO04NO-p2{2t9V!dVJ9~!!U(0HUy$vKJpM;N_-)E9MS1Ej&#;s*6P33J>APEbv-(7=!=
z`rX@seM$`2r%-DAQ-LqAz=SUpF<(NEWa3J7JqO{sqSXdT8a@?F-+)Wy_y2qa4tVuN
zJS=84^w)=yq%{w=Ill
z!D{0QBnivJ0}E)G(eNk$7Q6-3wZ~LiY8d>JP)eb7}z2HXQtr|F4M)}2Z}+IXT74cx&N)q<~H(#
zB^nX`&#GWks;@e?IPe0T#G=DIf_s-VIA8Z)NG(l)pkel9Fve6({>>h6HY6BB*%>hz
zu?5mB4q%D?1IK|c0lbsYUC{~u`O1HrV3=w*1%V3OcB5F4!NrLxiWL(ey8zbme?9o+
zR~}D*^H8?}Zg{Fk@n5<@&nO#e5dTNr{degK2E6NqNwfggh0Lz*EzYvMug>PMn-bAF
zI4f%ZV1ScO0svybZnlEW+&+=igzZH^H+WtSyZPq-cdJhzmU<2E-CtBjc0+7gbmi}C
zK*IUaOk^;`njn=fb3vmeoiYZ39xf2W3UV#4*SYT{IrIK^z2*`(Y_lZ^kx)QaS5s4!
z-;-LVZYAgeT(Y`0XpS9zNb(Oi_30_mMT^4#q?-$fSZMuWv~SI^QHt1ZQK{=;+*+WF
zHVh0F4iW&oKEqQeQH@?0(IhstFP{T{i^C#mD$;!sezOAKah+Z0&Z6{
z4@PKFQfn-y*Jwen`>-2#ukx7$(*kZ)H^i_VQVc_8vv?;X`GMCc#C)-Nog@l5LDwi-
zA21z8TlgxoI-cKO
z@OA)kWXG}>A3%(5nm1wL?NXC3dxqD{yzX)BQjb@-nuTYlogP~xIGw7ZuM4^c-?Z4
zoPLaMRTuwMh+Z=t(=j@_aR)6m2utqgzD&O@UFz@Fr>Kb*$F<
zEN#F9>oI~n32Iw3quVS4y!INSo7otECmo~fR~(~Vm)rDCGzDLyYsIY_zGGQu08cst
zIBFJ?cvX#$`=*R;5V_j2lR71GbpI2|)*7(Uwfc@2hEtk;_)I$2bezyXNWQp$x)gAa
zY?5}opgWCp@KmI8@n_Q5GhucFg+h;I6F9MTRRFiSiK_McfziZsScl@NT+vy`X#No$
zO-oJLneYGQ4;akiTjK=_dL#4f*6AMp3$aqEvE0pRra2PS|0J`*VVVEzla`KD?S=ef
z-_&!|!B2ChRiQk)`EAm891%qtdE0;`?U
z2KtX2Nx(v-)kVZht6Cv-rZ(lYjVDVYR0sRyVU4n3V&EM@Wb8{tTI&Kg;FSNCI
z$=lwlfyC)NwI>twK($#{7h^`xI_{b~Us-!HGdiiG20M?x-gU)Pbr3zdTy(I#P*CwX
z+qaKKk@Yulgh7F{6SrwZ=@7BhYtz`SUR2eQ{3w<$mMou~*)qQIS6$p)@cq)3*wze8
zv~6PtLseE@<1ck7;d9A)#b)ICPYv*F@KvKU7;|gibJzJ^Y(Ea>!un@<(X@Zot@oeI
zWbHb>v1k_Rnj-Cco4Cx-SBq8PCmWeYQuK#;o#eV+cKLZt?_TWR@00bewjdA%MLpFPJ#*cLF)W^KZ3voxw4i6y~EB(MLtT
zO6n}hOAQ_;9U2jUIu38SlKcNPyu9~p_(TEEGDntqP^EK$FAchy&ilISu1wMW@Eu1J
zWyZWd-jMNUgF(ToUG)q9J%*wUDXvYQE*kZRES)|eqyI?8UsGaw{W#g65oI{s80MlB
zh{c_c^j$xyZCb??dj?9q$K$u%Tm#b!$NQzN@gG)%r!mI)lEMBOycV(CJsOxx5HRxc
z&3Sk@!@^zXb#=&?Cb=uL#Fslg1thywYZ7nE0+nM|cqQKEq^)YuZ$+PpSiI?>!*!A_
zx4ZJOST|?d6fml_Znxab)3r1?na7irQZmn{3nis){Gn2^jx?h3kEim8Ywx#3VL!-w
zz!kdN%ZU=I&)aSJSP!99RdA)0rt|3z2s6#?wgpehDHQXBq>m*zmSjze+!aarA;#O{
zK(bu5O30#gI&6&nWjq2=afve5rH`dI_kqysqVNtRKvE6jffDK#_2u235^A^SLwPxZ
z)aq^~mbNCPly&87oSY2Y2NEyK+>5?gt12Y`>Sitg>gvn25-Ja3M~{zXf!Pi(%i4_r
zptfES8DUT5&A%4mukol^=d~nUf?CH}=jR{`-xg)vUdlrbmlL$D*@yY1ObUbLVqAQp
zd07P3{>dQ71*j-x1Bky(_qHrG@v$tW<8AgFFMW1(yYTN_?3I&o_5P8YdAZ#Q(0(~l
zO7{M60l@qIR9>!&xDTj+)LW|_p!oDZBHai9SGo>vegL6qh=5X7H@qy>lt#
zw}k%^_8SNQ;$QwFMF3E1r+;b+{Qzle0GN-L8>M6)JkfG8&h%~%20oToa4v)6r4Ru+
z&kmMP!E#sLZn@aqifpq+k{Ndsbi6EpGY8%m!Aw4$%OiZf-xq~*w*fK-jqb~{)1Jz+
zJ6{*EDRVX5{;{CE)8MX8Zvcb&
zMmYS}wAa@&0KV?`l#+a|wn|H$z@(Wijm99Up37bS<3W?{KU?{yrxvE%gCQ52VCG-N
zZa`lbjaLBL0G9XsdRrc$+x@nv90vJcLfRL=fO^9KsXhPr&;EEQkHG)>2kQI(w2AgC
z#0#YhlQJAt-ez6JEs97bD}ZNUc780LrgQ}4EKWrB-s~$G=@1mk$;h|Z0cad41<-gl
zRZ7OmO_sYZqLI5E5+zri@mQX%EH4-H9}V7?4F`h&bT8Zgl<5H&$o<#)OSN(`Po7AC
zD_u+E|Bv%LUn?zmf{&pvIlWjDM^Q57~q#`s|SPs9Q9a93GY8gRnvY3xX>5=0Dxs)fb}^4U{VH4N}s^hKpYwet$mP)pU@h5x5f
z5Z{;g4@=mnDPUDIsNi4^w^o{`WK{U10hm!mDs`RKt+3PJ132Ryz!@9705(6@NDts*
z2EfYW`ATVtC(l20^v&U406TO0XFR>2fQQRVWaq!u>!G?W|DqR4U|L(+*0I!->l*}N
zq4|)bOj}>0Q$zE=m4udYSmV#14Gwk4r_>}3G5xEE&I-)Z);{6GdrPMyY|1oxTd8bI
zPmo)%X3P;2IBm?>t0h+!e(^>imoya$F-Nc++qu=>_IGcE@%gh=_M<{t#7-dovYqSi
zuN_$o0X9wPZ>XB%2@3bQE8XsB)HsdeG`gR
z5{&O8M$O|U-FyZ62EN#jzO=o1O$HSgh|xX+N2E)SavepZGo#+D*9-TYEFP
zhL?`-KRqf#ElwR~tINb#M=MXQn)<9X*Bk$SbV;aLi_yF~FI|6^F4XNKl0#5lV^e51
z?ZR8dxvKLw%)Bx*lHXCu)?To!rO|HgI(7EPw5g)&25YJ|i8!#De?t9T`9!V}4f+el
zHt~mmo(VGgE3KVbkU`?GT>K{PQ&$B1gm{tZwP$(58cmi{p`ogT%5`B3-boqF0L+r`*@36@|r~!X`NA|?9E&RDTSbBJNx!tcF{5F}@
zs4D5D=I`uk$3v{$MM2F=OknJ(h`ED7dGXWsT97be)1(Z%fDYuVY3Zlkw5M3H#NaWI
z@Ep2Ir}z!J?39=ziohfARjQ9;)6&;7c8^ZOseeoT1Uq?e*ZdbGHFh^cA8Mu#+~(qH
zf^Zq;Bme@#3dSj6tL08f|4*zZ`lUXo+U4s#vt9sBCL&sIjMYKun_}#v4?*hPmhqdH
zyjR4-7*2R|Npn1CG)uq|wDnKdGIW^U;DgdIzTu6VzDa~ShewXp$zB@rs5Ex)hj->=
z;XO?4X?~PR2yVVh?P3B9u(8qr+%JuST@#>5-}l~)G0ZpDch+rLzp${6zZ`*DTcX*y
zdJt2&AgfA|Os^qVl@)NaY1it>5*MpVmV6ZFB;`hh-
zTdhF+!0xQ(R`|xFJN+pg+!<`yj~f5^h*TYL$)Q{683)EAo1=f_OjV5R4>xpyJ>*
zla=NX--FFpV~B`aKkNS;b)AbA9V!NK!9U|L;MoRRW!BOh=%OFyrcQ2Y^us3j$vNpq
z)dM=Mf)A~{kG|m3nsB~ntBs(Gd!|r@cdDu{UB%3CT{C-y8$F9MX1b($H?AG)>;BGp
z8wApNExA3;X=bHP9RaCnlq=Z!4w+uzT_gp+LeT6Nv~M8n5`NN;X^vo|9#y0sQ#aC@
zy#clXI~4o3Tb?btIvn_pHI`oC{&
z@0gC(cF>0|80cA{zS|^uGWZOhh=XkNPT2FaT5Kd@xErg{ok6*}gxC}=AhyoPIA-B3
z`6v$GW~-eIMJ)q~aEXsW&8J48Th5@u9yoBFPCh+UJy$49O^
zYV20pd!{G|cTJBO7uuJ^bIF_U-FZH^T3^ugVZm$d7u4eBpDg9ytEwvCG37h*oQ1?J
zsyRn%D7NZE&lZ#3P?y<%B|~_|q88(DQLJXzRLf(p?%@?jXtE{CvPI-K`HRlhVM(8S
z$e_71?$R#SDKTU(*I66^67bnzifhBLC7oi_C|Bq05|wL;D@CFen}HMVv|=du#}X>j
zLEEBQ^3qpEq#4N_k}8v}gv65RovV<*`K1z^z-MzZ0_e;UD;qtV?39C^(aeaQtuRMm
zhS$Pf?~Qt7w-;x5tET^cg-<7H^6o!8N$94-dm0$d%tvE#s%DCX0(S3n*!OjU+?=tt
z3i;?m0EBQZcI^3fNZ?-+OzZW$v2IY=ar-EJpUWj(JrbSP^nd}DtF=j+Yk@0qS}WE#
z==|U=kUM^NbSLiSSp)I^(?ptUlJi3ZVb`autbEmLS{}%NVA>yP1^6(d{}klD4y_XM
z&6JdoAP`Mi{|e}y$dr)X|1$#Np37qX`aO4E=7HA#6
zo4RL&+QA<|bFc+Jz89i&|DlHNu~~Epc}?YYE+BjW>~Z;fEs2g0!K%R%iLV@DXu@+w
zNbJT#3i2+y>%{OKdg$&FXIgqVs+5a6Q+1B2-xYmRq~C|x%ZH5;PS*ktD-V=s1p2fZ
z4~Pd~h-_EiXf06BR3t_4;z{p}mR_r;Dm-}P5D_$yk
zCj)mxQZD3}<<*pdNY_#pBvQ3|PS3T=qCq7FvrfYaV-kintMkOSRsi2OAUw~`_4`(U
zzR4oEG7>P_cz=F^&GCSYyJU0c^`e;{mx@6g0@@Pf?F@lGXKfi~Gyrcq;CGn|=sm#2
zMWbcE^Xs>QJP`mG;us=B=d6{pl<&1d9R{#BPeV(A$#Jz5
zT1?qU`AtR3b94O~g#>uR{fw*s=VXg&JmTdo!kch4&S7cRp}=?UNK`liz?zQB2F%1>u+yoB`4z
zI7rncno#z35dk8u;~3=y$v8lxipd1LZ1wc>(1zt_QB`lx^=WOG(E48}%UpVjo${Wf
zL0+ZMSp|0qti%;oz0lz1dBGy#K&m7n?^O!HWjCXo4+%jqYT3`bgSQ7!YLs}{9*{&S
zn1rw6x=>Y#DqM!g&lPmALld@^#GmY8q<_StiRd({qP5u=6Xzg~pcswIxmV`{4rwiO
zDEx6Xc3uC70ecv5NE8N91d@)Iazy@1ekONmqNg(ouAc7fP++klf&jO15K?I?v(7uy8oiJ2<0BOPnsAfA
zcBQg2{G6>QTmF@TkmOWoy|Kvzc1ZKBXyXToDm}3}Zc{#-Y)*pMqv&4BL;lu_0XTt3f9g@7}H~T?DL2?hm722>xLaN*NJuxquuFV&q}$48^FlEMc5H
z14oC1wPXyzc8`J*{ge1XKabz|w7h>R5epjQXQ6kF9UPpta3}@{^GBz1O}tdNH#HJS
z^2H4~eV8LreKpkg4{IU4hLrgGwZVFYYcgGP^0o-fQ8q(T|M*kvN|uv}
zy<3;)Dtd^X+9%x-jli60beuf^<2F*=#(pok_oq!vO4%)hvG+ih$gJu+F>hhxK$g%Q
zzifOWBk2;CLCA=?Adwm;C&wI3v`kFO>U*9Xf=r^ZFeT$f8%5#aYH#ly47o2KuFvjG
zq9NLe3ZhY%S;!RH=@CdxmeY@oab(jF2yd`OUBY{53%&of}{_x1^i{FlnYZ|czVflrm+HjvVtL9+z5gqJaSPp
zf@R5a3IE{a|ASNZADsNe3;`QraW#npi;HtW$&Bv+J`0eJ+hob{(NvbWolA
z%mxf>?c35=_~zL`G$}+R`~Jj{HE*`HnpGDqFEKhOP89`De6zlMb@Q*01HhK9StzZI
z!Xl9T
zg7wx5t>)h3zc_iTPc|qROdScwa$?{F7^TJ+DlXl^wkB{Kh@wJ({2OuCiRs6ofH|Qg
zS*tFSLDtT7fM(-y!TCF4P=L_p^>PS};IVqtqyq
zq(uvt-DJzi6OZ+CC-x89R
z-b0`<1imh=$ku;La#O~`3{{jd!Gl$SknFMOdii^r3?Y6o8wK?+zzqrY+(T0n!*Jgp
zdRKkih!e+%w;Bn#(HuvnwI8sH+z)BB2~ux?6{VWCJOx{zPKJ?US#lvv=cg9zIe~{Co1W+wl0;Qn5|T;{?hj=zC|JTdeHl;;$!+o0Z=Q6r}8)
zt{9j{@VR>Y#z3o6-=YoJnVlTAuphDC;)171%wm&6OG7xyPZqqWWP$U^P|+eX7@7mc
z3&_ze)6eky8pZ~SLK(R7zgXJe7F8IpurMCqDG1D4QRu1{R$pj9$`eMQXGvyt*?Q3u
zkJ7c{u4~D1`E>r5mWpLs9^dZ7#%Avau!LH2`L-#KBYqM1EK0DwF)MobCr(IpKmNe2
zGQH!%ZR_djI_5g|7vU1FXwr-&sy#1ulgaY&RIK{Ea(~}5o2fj$ue1UK$p_T%q4{9x;x1x=QJtGU>N+NYoDoA-8bAMQt!w?2G^)OD|O5eA={CiUN
z#rwm>*B6Vyt&>x)Z_!kpT%L+@gR%C?>4|~?>?!KogkRQMG+?F^>+xO6{4WwXahfxW
zwkzq=3&>v|7LM6!?Z00d4$a-FEq}kGSCbTMYHLpTTP5FbV1xUkZEz^zOn0{_#2G3G
zSk*cvm$(2gJEcCUGT@}r40@Ic2yIBYYT^Oox%NU3qN`yIqQMYw@UK>V^$SI
z1(SPng}5cf?LOdq!2MGfvpd1=ok=+Us6RH{UV4VdyJjFI~1IgGoitFKwAIi!r`4rmwUVBdV2(}sge5Y`*n
zz%qq*;wtbeTtnXHXh1MV!Mcj*()PD8#RsCLIVI63S7{vk?fnY&oT(6Hk628b&Qe*o
z<1NE%yL#@>o4I+Y6d#>&lqhZ1R+>@s9mu53!}iuxRN0I4VqvF#(6fSjTzbZxI8N(}
zC4{$PE>#NhHElxwV|PWL>2E_YN_ta#V~R>G$C$>fTsY%Mtimr(C^8`68X2CSE~
z;4~^~ggrhEV}dOTDk>xw1p`Ocv+e=1IsL;r!6>j6yih%r8ejP7M3XuRJx
zKU&uiu0JmFV6-tgvJ!7ddmoO949tVY_FS;SkTJf@VbqT{eDPw2Tvb12#*diilymX
zMh-zywFkieR2gDo1w_?3GJ!F)M#|4GY@)&n4b53RM~K)CDG1GI^HzTk8FFvY%|fJ%
ztW=V2Hft0uuyv7fsF9I%kYg32>Hbvm-*BCBq7F1V$z+B@xXu+vBkRZ|<6khFc0_Gl@AxPVPwUL)!w<
zEfTpV+-rSMktoOcxmF#^8VoQQ3pxr?%_e6rWOh<*)n`ihU%gXj6u}rQkui@B;t`$Y
z4ic(%;mS$x-VlkLAKXJooGz(8_=z~2OS4M3Gp?M7V~Ld9j*{bOLWjzOR-w)&qTwsi
zfWxB`3j!}eFsXyvk)$GFs_%G(Mc%+p<_iL~w`>c3Zjq2t#qQY$Nx{^srfF6}Ug)xemuc*;{4psgSkePu>PiQ_<1jRLQmKG91};w?b+x%sEX-6sZ`=%mPdXgsT^&us^`v@QlZC`tOAI<5)^v2AYO9e3e0EGH;}-38iX&h|
z>dxoPVq;3hW+U`Yl&YnrLPT)=ur3k+3@Knk>EOQ(4fPZKqM41KjYT=VSY4~x{lMXt
z(k2|8>^A04E~^$(r(w@quNKxd^3Ag~9e`*$aOlVdjGBHdy(b(2-yho81pm?qqNtvZ=
zd!hS}Dmo;#F;Sa1V3Xi1*BtJ&I*!?YaM35qbPDvzy$*pW_b2JEkJrY{gMNh%_bw`X
z>{je3A+0<`Bc&+s>%g7Wr>&Lea#8$c_+@D2Ic1
zc>f%zlibYNS`|BXFU*|0Yc+}E+wQ>kJIy$-qvreGHBeWq<2T`e8-#&zq{h}w8lgs|
z`+gWn8VHGo!rUu3@@LXV4%=oO5V6vx(RTf%F-{(m#;TD%v8kXR&&9S(M#jJ{F6EIx
zP+v*tteY!%cDV+2?!hm~ae6jrt7S}PpdtF%$qA7v$CRzhE%kt%glV{>?0}Jo8D9*M
zZ|Q%colp%QU@STog@2#K-2!KMZ&WX-oe+bh(p^}Y33d-aD-J-La0-2BH$jkKP7PF0
zKQIqohONsqI;AomkMDPDnpG%f+X4OmUml+S)5F3(>t=rg48$V`+@A^5;T8h1%
zl~IB^C8(olwtM1029Fzg6Y{5Qhb*+uvfVC;nk(~_oa(Kim*
zd^(Sv-!{L;5|$PiEGi#GHON;Q&3^2;jf{NL^ef
zTO*O*8&12$<}Pnz1o|eio|GwGvaGvljk;JHInfWR!d+dhhxwpHzw=5k+J^{f%<-W4
z_Fo?IyB4-g^=3@Fy1RF}FjU1%P~jk)Sh5hG=H3o&g;tK>4tNE=>hC>Z9#Q@T+Bzx3
zT!bd*5*9Y`zt^C_AdKzIyk;K~bY_fg(_Zqd8Z-D^F=9-jE_D~uY2&x70v)wQY9q#r
zt!>N#YD)C#CzuuNe}dhTHGNzk(|p3;C=~wM@>rE6uhG~tPs)-%V#-=I_yA5!$!KH_
zT`+Bhi>Ou4`q4t&3dbeQ6YRvjK->72O1!Bf?~)~DR~F)nL2oL@2`W5r-`J!?opUV2
zhlHA~QbN`C%DsNv218)Y_07bKDF&ZRJfO`VYf44d%Q}vNq5+b-O*g8xP_mTFcK+A5QSKG6Vi5
zQyXio<8W0>49h7BC$NOyzj5uMu4wW6Df|~vk@X7A!1_XnS%>?18=|t7j4@j$-fuQy
zzduTHbT(_Y{phuw2H1D+SitvKWNNX7F&z7>uI+Ph^NzB?XWtzCSt#Q{2ju$Dd>QcW
z=}lS&pYARCp9sRI|4qC?X-BSvkc8qo@NAKVUIfxZx@ZpIjX?SOSRl2b>hHkO
z7spY$h#^jaY%e6C!YipH`+hH_!>thIm6dTPc*XM;NIvD{Stf>Vc<_GD7TuY>zYcoG
z=*eO8?u?DhkaitIInv85K4!952R!ON1U$s&EVtmyHQ%=bdFG@gg1|CB+Clq!tJLxO^DtZym+sr2!FD=~T7s
z#u(F!S;(cRgL)F21k5v4O6>7K24tPhvF*Kjl!)~LjXa@kKV);iYp`Fdqm-SogsgxJ
zcaxnQ_q*H9M%SbO<3A7stvYj?4`U3MGIgLEu7-4WEjRk>n4oUfs>K2S(3mjq(5a?`
z8j3X{MKqWocIS*)j@|`$BiKol2FNQB?h|gGOE;ciD4UkAW!9vZ;mqBH)mwH(CQW4N
zY@$e7wxCoc1n6S3kSMi@(h{f(i$?v42c0XiyjjO8tiR?=B+t&+pB(tb
z!;6$LsgiW;T8(-PsUfQ#D|~sg;hImh*#k$+k$_B=dSFXr@%Bl+-6dD+{lk=fyu?)h
zY)M_-xMt?Ol?ZJ%IcZTG@KZtx^t`_wJeTjEXa)9skIsb~1Bv%U8EMDa%a~w@R
z+8Kv-H1{8o>9k&x;bJr?(B&Z+>_hy~W2vA?GS~S$??5XL3;sh+$soYE4?Od*IN}sh
z!6CJ4{Yl8A`Jl*Y=~9YX8X2B4A|>!{aP4sG^cIV-0CVAA;}V5~?`r)0N(u8Te_@&<
zt(&&@<)`3f*`uB(lqb_nvDAggNB2;Ve31sI*8y>K3hqSA&m1r5@vPHs^Y*F?$OhLs
z9p1ENZfn%`*t%?6)F7LqP!4UNPyEkwbmg!$r(3Sjek9$E_RW`sk@YIFxMrp0qiqN0
z_S{pCs_c8Zmpj)78XI0Hr~Vsda*(3?+f;(p!-@GM;t4$wPwt?Wy0kI3Yb58yfZeKw
zy=Y32?4^SPV-8R+Z`NGd(_|*pK1K@+X&d>%Uz+NBY`>;n+Rb^g%`Lex0b@S5T5s{i
zh-81Ym3iRW%aI_|)3Yi#C=VB+_k?mrBtL{yUKH)bnBAb1{e)XH9gF1`*AA>B?@jyXCeZrE=JOMNZTx_)Cz%@E5tdklAp5NaKDbpJ?AY-yLPHt6G}$lXUT*;PZX
z%w!4d5mOzBm-P+>
z>=D0vD$wfxHDwm4%BHaZLF@5w`%6bIEZ{3s^@Yi9OcqUH4>e8$X%)Su6xBi%MsFfQ
z6}qs(c&C5I^`4^A&{aN8WP5&|(2_|rMhC=SqSUtB<%0$G_xS)3_|xmRwJ(9679j3e
z{=?e=IcLdoOS;s)S^^haSnoK?rU_vid?k(T;QMIgE+U6?jrIm@*)2AM!dY4*%$Gdsx)TpXcHGV(hG0j=@Rb=ZPI%Zh-iF;9INNF|CwnGBW
z1@X8$o5q~agG#vU4H8NzBT*6!P4{O}-VZC~>fRZBm4z>Xx}3r{wLajQyy^N$4_nm&
zap&dulq=AJKJ_4^R^cZGEg4@!wi!38;5F$T8{o0W2d3+XQ;Jr
z5gZJ#7AfM#cFqm5oV30sAvyY4jj98jN|v|JT&OP`G8PJ^TB=7$gkOeEZ&icytG~l-
z>-vuY9RTZR+}+>9ruCuEiY)RPmT1$%xDC>rMS-}Bja=wYbSex;t=>-z+A^L7|6$ns
zhXL;5EaX27KT32A;0JXdV4d{c-|$kP=3Q?vEA0fwj#ALn*SDUDVBQIQX%)Ty1y6#j
z0zNeI9^``rjYji;7`R_@To-RF5(q
zc1dGfkILMwT9mCwXxfc6t*!YYQ2ZGRc6K}cgNNL{=t$tf$DL?fLch!KJ1ZrqE>m2{
zU$nQzJQWRUJ>42^MWFe@Ld2G>4D*3|B#0>>cd%q&cRRhG3-n&;a$(i6dr%cnS#Ps#
zQG#xa?1h{jF+zcZ?84Y#hpb&HhLJY4l@YP$eoj(XoDhYxvy;N8H!HJ%1iH@lkHtGK
z^c%>i#vLpbfj*DFS9;ZaTk_!5wI=mu-XPF^4|L~jN33}BL+l$;@3CR{*RSyg+1rrvkG
z?fIB@pf};O@zV3BFBzJrTgJ1!(SD=U3C}SJ&LP5K10pKP{eNy%MB^TNHmx#(c+H&?
z!ED~T5wv@fFCCsgjdNCb)x=uzsMWS66>`G*;a%)zyH71Joz9ZXO`OeQ$yoT95@4pv
zK|I1P94XyN4muZ1Ho;4mW)10U>W|!cG&RzvEE@iTDoZ<m
z;NzymLfTrW+?0S?R1%`x6qdKV_fBnX&)VHFx!SWD>(d7~s_Iv*By)hHBnHw3_oGX|
z)wOwVW-2o`sdAUpG-YJbTw40~0TBln4=Pj(()SP9=;`&H?yySl%*;u0K`0S5V5#%1
z(qc;vitH$6BR&*AlM}7WXiF0c*7FQ?KIk=rMH~n;wFK?6ta(KWMBUsinwDa3){!4!EamF9d{_;-!G}(S(WxaFekM&p9D!y^`e+oMgdU#DFD1x
z1eY9i4d7z-i(GptCkJm0u);<%f4vKEvlU^y{pC4n?2S
z*l#T~;8Z|BO0NyGeRWKTRhB?&f47WkGEUA7u@v$x;7D!yi}fCR7aJ>$NQ3GwD=pZM
zfVw!*vj&{%dy7cM9l>;s!9bN3{Rwm{b$=m|YUfYIl1qq0?RgeFC#KbutMTnL;uz
zTKbFvqSF}Z3r)qOCJf=Mj=Hx!7_QVC3srcd>N%6Q^GzY=Z?GEL?`9%-H+0+pYeFGM
zo#7TdqD((!TO;;b9g{!HrI;_;qTd)dXOap4rp3Yf$Vs8UyXc&JI*bhS*jYm`0;sCM74vEmnJS-R_^f;#Otp|NQNh2K
zJaN>AN-l}f8&o8yNc`<;NE%z~!Jdj414f9Q!)zGl&!VSxXyoN06e34|uo;Hz8Vih{
zXRMOp<}LetNnw2SsiLUX6pZFrhg;oc2)KQ^t7??CWWqzkBmx160n!|7V|8&|GpeK>
zx&Cvcq(Z0X>nr!XgLR%OJzihQs&AV!=OLg5dK_sAq6;8<^1LsNmy|W!C}j#N+D#0j
zJx-_yRT3@s;d=PcE3z?oHFS*~6TmBxFT@AVhUFT0fN55+NJr)`B|MJ9Etql~`X=YT
zj`4__xgy#zw5(Tr(omY8mrK?09;|>F+&Ck4
zH-xytfsXJ5;RtnvOC)75E6;Ag$&pKs9#o~G(DREZF7gW^>Dbc;H&C2o&&lZ2lRzAZ
z)I-Ua_S$Ye4XL36e&5p(&A(NfLIa{sNP-8Xuz)jj!;0}uW6K88f4ZyNYx8!`8%3`A
z2zfe%lkbDSB9vS>@|@ZMJ}cbh%4g^#idChgJ%_dY&&GACElVzLaP*XkQ8%PBY|IMdYN(%hAHT>(qe04NH!?r^~_hvyifSWD@%q`{^JoM8lsg
zFi^m`O+VPJ`b*-EVcK^ZI_CC*4#oHR4_!VPhGgS$3A5Rx$xkxDB|2oJm+mN%Y2a2yf00tU_>Rj0^}*Xq6`G^Ziw`jv@MHFyu*j{crEx;_o!VguU1pbC9n
z6_ItRABGJr5bx34cuCe6k$uU|5981+4C5e*L(0Y6_obBUWq#lf3NK?n`+1BT;8(QN
z3~$>H1LayVVnl@aoNxyFsu@D75T=vvBU46nly~h;=TKqt9{Q9$P1fa#$16QG@&onO~6dv}VKo}*Ak
z8viz%^p8M~5=`4D0R$WBt0Rn2IdkenY5PGKCS*aoiY#TdKnCYyBs(b*T)i@p0-=vt
z1>Wpf!Sy{DbX$_4U~uD~^P->ZDrwo6Hyh_y5t6^6fX61r5my!k|r+k>2?tK}U
z<+tG+ptlESF3fdUKx_X^^IxP1lps=O7-Cu(K)ykW*VH5hI|hFO!fOs;kN-B}@g0V6
zTI>fbOX^Y*2dtw!gBMotTCa*FK3cFy%s(}R!Mm&sLhwj*DBRZxOsWI7q{#Wka>!p+
zK(Ea?l@0E_RUD&yQTnT0f(%(2GLz=lxEJplyxfa!LR*FvK#EJ(ED%K#N0w|*pe-p&
zoOz7#4XFSPc~ge$@vm1NE&N_PLlKH&AYadi6FylQj%%a@JJLDmy4`;Q#C&_pdogkU
zFy)3y6Wt5aEWzSdm*Wwy1X4gDkS(bw>1=&SPnILF{o)66QJwgBOFMCCf+pM{Kb=YI
zw_rINjNy*+Dpl1!EKN9bxT%ASjsD43>iKS8STwQ)5ZRjZx?KhQxJiVDWS_^CkDve*bG
z(j10PSMln*>{<7lCaFz5S+7uw
z2=E3^{IPYeaJBWhhBoEOufv%9LDpFp_TKjB*xQx6voVXB)6?Vorumv*TRDnlWO{
zI890)#%5+g1I&f^xjf
zi|YojJa!`AS;6GFUUp5=n;p8~>m+M92!X^Thzdq}frWd7?Cg{uD7dHVjXKZ2lYO9L
zLxXmAi`Zci>M!A^hyK?OEk#@~NOF_^tpGe^f4{_9+O9b#6oROv6X4F-KT*ZtVFr*a
z*>f%J^i4LLg*Hxl<{QqU8zq3cQWeRV{Y$H+rJOe3*u-3C{lBsu_sl*IVcEz%hqRDS
zn|n3TH}L=nLp5t^-kkiGupiyhQp8?(6#)=u>F~d0N%G16mzZ-2Ya{o2?%7!Hzr5st
z7D#1UZvlv-1*pD)wb24-b`;f;(zf6zq}9gN`E^OUqq1n(WhEcrORa}|*;G_p=BjIz
z?jw>8LFz4iO1)nV<1M0jl-=QL6FsK3=opXda*y5*UrV}X$xx(;kQkJ-Ps3r2nH6-n
zTXZSq*n~^+kEX=JBSH=UuZg&{kYoR7I%Ic=$BjlSV>)XKqFL%w`j_gEiVLWWID%|s
z<6#}(k?&})_?tBBA33lhkk3u3zvnO%wO)h)W|DIas8;sea})FWu@zQn>5Zlg+Ow)=
zsC1i^|9GEl(JlM=08#^-B}h3&Gj_`XLA{FNL|Yb(UzlUp#*<)_Is%R+N9?xoJCc4%
z$k@VyA;KBch6)2T>%$QylvYod2kP&^9ZR%6xCj<`%_I0HcWEK$FedGE-K4yd~_Cj
z+Jq-QMD=vOWeLyP!voT!@$uz@&`b}AEgkI
z^_qVl_@@*M9KOox+I*GOwfU%MYC4S^+~6~6oAo<10b#h{nwjdAd$|9Dw||bVEcn_+
z(b%?a+h)h;m^-#@qhs6XBputflaA4`I<|3k|Gx9xd&hm>_l)na^UoYLs@7cf>^19|
zwf3s2Ic?SISPUn(=Vz+&yDC4@OK}k&88DkAba6ge*>!w_Nah0GZlE_E;*+PZ_8rc6
zO%HD)l`SJ%*aOtwG909AoN|rC>2)-!ck$TR`2>*I`J`gObs&5|YjHS{EO&wEny!K9
zbUcCR7zLE~3);O3MnqliL}EjZj)1Mx)8L%Y+{Gp**nELEpY=Sh|7Sn&Xvf?YA^J=@
zY#6A#-^EMEAk>CScpS@*m5fU$>(b80o|P*FKbd(;KAdjMo~2lDcNhP%-0ENJ=HigKOg;5_>1Ug7
z_)vx1LWb#
z?mo0?9T69J>9HKFo*S&p`@nrR03&lQXVu*UK2h*E;1iw52a3S`WW2`PFAFum;y_TE_s+|A#7|wQPU*lpdAWt@=V;rg8&~a>VXf+f_fjw@dblRYk4r
zP<0z+F&(33hlOe2n`*Zz|I_+TLwj`1=$GTO%nRVwo4(fB(=&2nSMdNRC^#-{^()my
zkvGv~as55XBowaq0Ox@VDEbGOd8MYOfnw>O`14O30)_c^o%wxGC`P5`A5_E#Jbeww
z&IEupXkMhc^AG}Ptw+%~aE3RMQP4EMgnf`np)sdGGvtGeSnJwyTd$rA_|$3hX2VMY
zY`Sbjo8C<)>BHcpJ)@$MXPIZDDFzN##+oBIr3t8*d>)7xc6i-dT7Oj`z^1AA$ixh<
zo~SaL?EH_MLETl>OP+FPp|*VxJYWaPhrYnB{y(LHi5HSl(bPN9xDdMIkpEnbBhVE_
zNDajFRO~rA4n*|-2wX71#S@-CoIj$qZvOy?RCgrdYW@r5c*d!)!3?8)CO6o6pI>Ly
zthir^pr}7HtU4WEn3fpPp3O>d1)o_mF1A#kDXR#BmuqJ?kpMq+hW!7xM3*b=Y^%l>
zf3RBaN;F=t0^BWTVq*11F$$LEmt+DuDKuUmXqJDV)z_fp%m7%U=EbTzPbPrZdX$NS
zWcbfzg8xh5xJ`NOh+%`;BMv^*Zl=M{d6X#i4}9X4rDr-Kk+2gI(F%QH>%{h*85?6`
zbbxM-)77X?hC&=<#xupJ*zg_jcK=N&Eb1888RjgoTe>_T00xKJgAAiJdR}v_N7*>s
zwC*I6aI^oZ3aFIUs_6{G!wA&dq&F;hY$Bg5;d=V4u>()eP0fq;;SK
zZsMa+olzWmAUmx7Fmo$A3)aOs#PO@khfJm#jbZm@2;GOYrfQYUB4~U(P9rOO*p6nR|s`wQ(nC-N4{~M9IPti~4-gmZ5+mb8lB(eyCMy?Yew99|c5WRuW`2V2_`5y%SU;lB|fd)h8n7Z?H
z0&<2o%2Alf|EWsTc}l9o@ZZCnraty>chM`i72~e36dhGQ|C(s8$r)okbp-ZP6b9^?F9#?rchd=q
zk&ge1Xtb(6xd91zW9~W%ohStIc;~;8`TvhPK?IFf7nrGxv%Nrf@E@BCd_9ij?u(gC
z-Z|v*LzYgT{rG(ZeESk9*hm9{#5eapMKPaYuoFuKyR2382+yfL`WT4$$AI@d8l*9l(DSLi&LY!3pSuyo7(5
z<@^sW=>LlvoEOMzleT{pR|FdSc9-#-=O2eAbykgzE;j!W8+=%a5N!A#vHv|)8hf^N
zfpo6_o7j2(uMnGniU>mJKSoDF2O8Z+&7IkODa)AqkBsR;nRO1US{zbN1MCYcy{`B07`Oah1MU;}Wh)tv*!F~k2<
z1ylkuIqBaZ1nM3B<4D-yMJoStIRS9I)fP3q#D#l}Kh&aRfJU5*seG6|CyE%e74)^pTA_g&T$!4UeC!qHIvQ0GSAOXorV>50Ww=I
zJO6^2TA(bgZSC8(QjQD~ueseE(Ccm9$i`{o-vd#4{6h%^^nd@I;QIXmoI1^bv!>A+
zaGKP5l#4@6`=6?Szc1Fc_us^ltu*uD{12C}^JO}JOSzujy00`jKRM&(ucjAmHb$VG
zKbhJ(+W+Ra@(Y`QwgFK5G96mx`8=`p47Xy2w}bz4t`Yc0R;T+XVU*!AfB*lEvgE2U
zdEwpciM|+|e?7^TWe@Ia+~e!LWgk55+MzRhG|AlW9>$DJM6INB{h)v%2JVX}s1L6(
zt7{DsZ*-T?yQ9vcJ@d@`3^NaZbr`?&Y~pb8^m*;>>*c~vWZ(v6;zwcPX%;&YmLHQL
z5}|M%;M?xDPK*dXLVXS$qqGt{??C|Jj}+4H!KL`9@KK6|U
zVdzL07KddfKd?Tk5>gjRGx0!D8?}V+Q~XsRDK56`RG}xVruFQ^lXb>Ew>ccQ9zzFH|avu|0$iFtURq2dvu_GUH?%(DZGU=dq-vMy0CIA
zBj*$%1!CT`Y_)dNOvC%_jCpJw^m>N1sixjeG<(+mW$?Q%blnVhG>tdh&%1|vuO73K
zIUYFv4@a*p{5HF8t+L@x-MDHO_LKGpvXQjSKS{;T9^h~{oIeJebtD*W(Xi)b8jl(x
zX>OBR<(P}$3qqwboBem@|(c9e>N$cy`634o&2ujzgz_wtG`7He0+GWU--<+9h7xT}u
z0RGD-n;D89hpoik0}b~e(6TIjcE|OHRB3%<&AqDdin2dRt<&tk3)sfHYdg1P&v2Gn
zC6^KI@v+0e$NknL?c%A-eLN3^bQq(6XqJPICSBleP(O`Y><50k9r1HokKQU)h5kd)
zt_q!vQPa;M`xD99<+oAM<%j30`el(+xi;@Lv`EXzYX`b*5oBA$++N5R>Q%@(|1%2k
zXg6UN=1fwA`Y>R&-dL;EG#~P*ol_dlT}Ub$524i}>p8)7_ydsz9}9
zTp;tM7dxmv7@seqeb4BUrl~8-x%@JF-E%*q>R=_dPrS#xEmUnm{#-`8wv;IMD__18
zC_z&XQaCa|bSC)j7*Rm{t^u)tgsaCDy}DPb@m_CuRCIx}s{=RI|Ke$?5kvg&dU}ny
z|N7-GY$~c2`Muv@54cKQ_zCv?ZMoqKHGRi`kSp*jYi;33woVMwYYh!Z$4UCFE9dK6
z(4er4Cb=lKuhJZ3@3|N@hsX0M_!?l=Ed!1@-RF<{#*)p34WRai
zd((v$y$(*KkdfmS(PJ=@x9f?t48f=RM)dkLMXYk8-K^0QBwH!~e%`0Z;KYu<<>W^K
z!@zfxrKC4TR?M(X*>n(LXW~?k*8-(YZE$ru9WhZb{)5O|
zApnPN6vc?zItokKoT6{2gRlEemFZWbxHS7E9e)I$ek$W*b0CsR*+Tvotz4nHGp$JH
zy{gE9_m@p!2`IB#hwy@;Bn4yR_j>)2d&lFKP5{SkokbzK2XTmm+NdCW?ghy9W$w}>
zc&LvBX5JY=Gk`D5P1n5Lr1Rc+^!wgNG3ukLab|k5{Hpd3vrmgqA(1+b%;vz0h7~Z&
z>sH66IiiQ8%01s(0sLC(4NHOSfZW-l2OMBJHxhW}D$XWXG+&;+2=GtGYqti^xUK&2
zrL%$?ri=jXftMEs%Yl{G@$pU(t^)fTk{{K$6c#ZDF`enXdhR~p9EUdhF3;xGZQy$T
z!bVyAZtNl*9kwU{H+DjdH%^|vOsh0u3q=~8k-6#l2l?rZ;Ys`0*taGZ6#27;MP^B(
zg*Bbz@m35|#sjE@XK&aue?3@65cz1ic9sI$H{^-(`%FMJgnfuCpz?d)_N^M$AeiqX
z{Kb&bvs9VEV>+yJb2tD=P1Me1fBmk=v&kZHojx?*{N3|&%AV%Y_Mlrt$}(sx(e(~I
zX_Oq9ck)}5W|*SN=rEZ0ZK=yn&&hbz0m1wI8qP`g3oW}?dkrmT2_o(yA*xrBPYE>m>
zsXAtgD#*-HhAG%P*Ja#Y+KlFrHb5meFl7!*KN%3IMV*NYDjd7h$AR;gH2%w%C3RN|
zj2(103PYB=gYt~4B+`HUganoOAzgyL3XB{CV7=|x*$c`CCA|#!3uc_}s8XG_vm=pq
zR~8Zhd+jTU0J++~e6KC)WBVtt*4XvCafC{Ix_8)*W3qJ;
z+e>FHM7tOwGR6>?5=Mm^`g@V$p$IT9&Yo<)68ER4G__JX8mXJmbS17_2DOx{*10@jDHe6;o
zKJbGwqk0YB=(&!kj3u$|05G~xl{iMT`5=P5aaV4h@%VPa&hu;HTB2qQAq@den~Zd(
z5BY_lUeh9cK-gHuZ4>8w3K3(NEL6{0_FHMJqHZ#@Q!~p?ny|9rsH6s(!d$hKf$zrg
zb1NiRL}aW*DQP8{@VODNL!Hbgyvn-dJf7gyn5D2S6n4-}sj&RlrrxMXIL3!E@jAi-
zton$L&j((e-l3yEMLGPm`n@*zwcfu!?*r4pMO-i9DPHw~q4c8G%QEP1yRyzeyJpTn
zzw4PNTAxmhTJWHTp6vMi+zUG29FlI67Y9quXg%cKw{J~Fq9h0_+x#)l_dxMC-)We-AhLBBOb6~-$
zTuqi`rEFI`elPmBH-Qoi+?q71(amu}Xc<6YanI_3l8X$UULLp_cnAidIyQemAV{YV
zY?7f;u<)G?@QDO$6jy-jyxO3M!6Q`nLgRtjk^c5)wLlMF4LqW8VY?0kks^aU3(=4b
z8e|#1{}Dd&7QP}7!Uk{Y8vn@nOYdGj;p2&T_V&g3!G#ufgeqN^KXhXS#u<#MUYLH)
z{6+piCo;&ro5YbgzeYs}-GN%PGY{??uXGtGnZnOO=(zUBoom?9(ZlOPl{BYkW$|%6
z1)dHb-yO=)zt{6+f3*mNh8S4YnUILB$I5<%4nk*r#XCQT;*8!fM<7dWsqbIQu-@k{
z>?Y$Jsqp%uHGRMm3RR$EWc7);O@paw$up$(C
zCHXwOelbiDj_t|BF+@7KCVfvSKwPP_+(ifjLZlJFU;h!W{3BdI_lkr!Nj(}w*bo1X
zOFE!f7$yMYy-QnuWq$q7*U;J+V)vNIXABw^i3q_W#H(x2Umgvs#I`?-(
zxEn$FPlV8|Z6xn=b|F@x55^;&rsrTxhKvZ;xn4vJL`RX9Fm$U*J_K8eq}rQEB7n2K
zgpdtQX2lI=Bp5Q0V>LU(ul1FWt)1Kbw?zjOk~yM34IS8cm8~cx;DzdrJ3V0#gcVQ^SGG2GWLH%CRPlyzs(t+72ioK@M2kQ=A^(yN-Isw>(Zj*b6*)Q8m;^YKhPG
zD1Y&9%?8A+U-iR&K~C^qn;_qn$4KI;Gw-2aRR>@qkhZhw)M{dFvM)cNIcRfZd(qGnY{s=s@@u(&Ia#Y83KzjTNGK<>?Y;{?Wo
zI&T#Y1vB$VKD-jW7`>L3RbVfO;FrgA)U@egaP2On7>DD}7OvL!UOlW+<_$7Ka*8Tlrd7ig~B8cmTLubOug#P;_=
zcU6pu9BRt1IyITEqy2k2c)P#|y%gJ7(Fp%3YyLN^eIBCnDq0GfFQtj{{?<0GHCXXWCUb>&E
zZ&SyBj8iYbX(mzKIrT@zIqv8rxr#m#D(}_vripFi;pSbq?LdXT_oWZ<#<3>K4m*xp
z@NU_p%CR`euHW$ms{BiBe;M))5x5o0B{C=`ILzCtCp+AFZxeHE9j-#kPxPBRs2ap(
z(#l^I3SRMSTiQ)9u1{1vU*vtVW;}1`Jgd+q_R+k>j<+9CCxvvXDCI9ruUJM1ucw~|
zp#g09Lbdn}eilDTashA8Xz!gXb6CA>Yl!h1dOUnYB7^S21JR|
zUO1-kV@+FIGHcW=x6v1Qj1tdku)RPMFVi7S5QsZur=JUz>(_D@?D5hibD+w>+RX|$
zh)~83fomuW2vLnRk=)vSVjx6!9iBLxAO|GFRHmkr2p-T!KX!#1+78n7OidA+-PcF8
z?7EiB`OOzln4?#EgMvNkjtcEX&%LVCh#3E@wVE~TmTi%oZ27*z1ir0oY&j0GxI1nT
zL)uFJ*6W6U<-Q%C-?{yG+Y-5g1q%l3vBNzg`h+mqo&qCv7EeAd9d54|PvT=Oz-k=8
z@O20N)+I)bV*wYy+1f5>_|T%W*B28_@5YT-V>5vy-@;H9Ae#3)+`uNkahi+
zj&@zJyPkHTj&_{2%f*{+djlKwpr2VqLHW>xw~dxI8x7ogMe0Ku3kiOsrvhY4LsJ)n
zmi9wHHG|k8p{9m@HG}j9Oi7ELc4qQ!PlG9&Hd^Bh0=*nXvJroCgO;Ar`tXExdFtWGZl&L`;&IowqoKAMs?;~m=~`qc?Yy*c5$R=^*lLE|fSI{5
zrfJv2u1e`yu4Py$qkT4<0sa;#OEAxjLFCa$_nW%OiMxC27;G`f!X}3Oa
zUf%HMmT5R?B_zX!8KOtI;b|fuox0U341~V5WIYyq>Ub7<=8)hD(&~-Ns8k{E{Bki<
zUqTon0gs`_L8-_Qkkj~;V}B>Rsj4%Rnb&}9czc|RCz}Dl1}0W*p$Dg*N7$aKyC+sV**22*zw<#NhOKPRuHR$Z>
zqs@tqV^gQ|Q3G9lD)Y@Gz0@%z-MJzBE{6697@`6qbr_T3NLc~&Pe#f_X7I6u;VQdJ
zK#*>=Adc87C_#d_3hK4Nus-2BH!nE(n7@Tp^n)$u)J;%&%WUaz4
zM13A0TbbDSEtJ!Sv!FcpRAin;uQ4_aENZ>tfNd_rlu_I8hZ*IHt-~m1_QNfP#TwVV
zC+-(aPP1v%L(;I(A;Vg*iv|d)E$|hCQQLp!7xUWC+`b&vR^vv}w6{-G{Sl?jxYiqH
zH2C+N*xFUGl;QBC#@8r?VulxgD488~#l(P}AP#?;)
zxTBcVE{CmBuPZruF7?osFj9b|;PKyt6{}Xc=`@we&N^!~*(ThkR6s#kzE%ZQ@5-dv
zC-kqd%zSTzH5%8
zK#02B$V?^ynSp}l$MUjB#dv{~_`)52m=1akHf;zV;sa|n=de7DJ|4}Rt0r#Bill8`
z`@wgD*nnViLIdkkoSNz|Wqv~#eU50ma$8b}drG_Vm>_ym2#9mK(1tByi(j!Q){diA
ztR{@5C~SsCYRnF(`ohi6
z4o8a`(LZd{IBt4y{hjVD9!vDRPsdB?*~X;4-8+?#+(`B`91eHnm!C!|zzy
zs^zVXlt7fehnU&ds$aAtvNoil|7=qiT32XV-BY~)CSUAfArUMddMQn-t2ZYA5bPwe}Xr>97cpkVIt%x@wb#rt@7#ygaDRRg;SZq+Dls?^(n+T)2~h`2FB(o!
z5dAc2%y=lmMAv3v4+}f)`HBEZTWHN@DoMhffYRs!{ZjF>{-+YTFD=jeaJVy`jWr%S
z(r*Bq5PC$Q3L~Z0tTlGl!J$AZI;?#%bHY;Yu;PW8vEm=a!KQ
zm5h{0;Wpp=5O+|xJ&`$2t-vIYU$eMoDH<9V<&DKBGfgdBgPyWtn4vCacxbckSLH_Z
znw3+fPl)J;2QE<2HRLjVB2~ZV{=pxS`F0>qhL+9wsowA+_TWV<+1Lr2a#7kTd5s01
zmnpfq5^16-yThf#U8o%B4Nnm3j*l33!y(D-&duygyK1?rtQhak?Z6(Jj(DIzz}%_r
z>E({Sd0&2S3=)@Hybdo1|JS=3ROU9
z*P40NpL?Gq9I6&~HtuzSU9p|hoPzEk%;O%?d}klpYhLphiygYUs%2&#MqVx0D09fb
zh1*Ur)b68$9ehBVRo3Q?#-t&x@T+yPc$h~2!{^xERd!}G1qaq3a`Pz`e;2|Gi3Wo&
z8*X?)Y!#WJ?z8k6$=g(ns)i~H%n5m}7tfD4+PsaR;rA{hu*C+dQw&c#K
z&uEIoGpr`2NbA@d&wKM{iF@otYI%PV(g9$bp~4S=h%00)#5hIjJ7BtQ|E2Iu*C(%&
z#r=%AVCj&aAgL(si3y-$^wY%7c0rd%iGRU+Z_GhFL-w6vlY*n%+?0wUM+FayuLv60
zIS|>saxSn1Xn-S5BBv0mfEGV5ZO^`oA+(Fj*s<1V=#W`A=bfVZPZybBSkq{pRYYCe
z{ESn1wv~;B$hO9k88Kb*$YfafRh6Dmg@O(#TPsVHp2<2FekTITxKN3duA3S&lGN=@~`?1-=c+$
zA*4Qvct58a`QJxx5);)1W{R~HN&W&avRta^nf8_%^jC>il%xTrtZ&-96E`nO_aDd8a9f>fsq;g
zQm$=-m}`Wra71}UHs@uMDlRDB-P6!*D1?W5RxMZth__Rcu7DG)-^U*+3>BR_VaIF`
z7k=(P@PztsOPYRTKerwwNC~OOS~AcgK;c6stNH-9H|*K!SA>7@I-rYh&D1RH9%5);Q}9f7lAbRSD_fz^1y9nB@!%KkwZ7=emo*R|
zs2va_C)5Ank6c5Yk?dK`xN8^R4M&YH8!YNo%asD&WskfiE|VF5HL8qY>zaIpunVm?
zPQ<7UuSUN-QW=MFdZJ)S^HO1PUDhp8KU~FHwY<1|yYNm+R#2u6XZ_T<<7VTIRQcGf
z)lvZ5S{KVrJ)VE2tbx(sZXCb0<0s=-hGTHq`iWQCWSb?~J~KP=G3g)wYEijqoH$6d
zQ=Q8cBlp-yr{;LBhOt}m=pCpejo644Zi4yn8!8i*of{Mym%V}CRNNu
z3udbVrIp$IRmctUH^7A-&Yr0t7!^n7{OhIX?{?CzBo;D;(C^Qmb{K7w#xbdOH+dXj
zb32q2CouSFK)ANTzR}oKq(kBe@LZMXMoW17O#{`^vAb*To#!R?X<|`
zR#=KRO5-{@tOVlC`D$$}m$3-ywZ%8|c!vtddH>g?8ar=O^bz}8kAPwQ&
z@fBi$PfCrfsr`7u)!dGm%=>Q}_SNn`3(-?y!6VqPl#2(Um%2%N!wIRnoS#V|r<;h{*tgvpIcEVc>bfI0uUhyM<N`EDW$IZ)SQc%iP+!`Nh
zJ!HSw6RZ9OhiHhwf_i2E)x-vDupfJgl97EgLPl)m5LEGC{La~iSz47OdI{g#@CNG
z^w$sNlN7&;knH$$lY0Hp1dqvJiP|7GI+P9_@i2)Lq1C}`PsriXabgtyex@d{E9w--
zh?kwG;q7XTjpMSN;noOVwG%3hgmMw(!|<+5VhLcr6+w|`@Nf~O67iC(2>t95VQ+?DL-rB4vox7T>ua6qq{f0j*{Bwh*r
z5pOGkM{M%<{e?cyMeIgJ?pO&7w$0zCoqlV|#2U#2xaeFDU>1t?x78F$v?S{oq$`k*
zhqWzBdx+(qw)5Zj+YWkyjLI$3PzNqIzo6}XE8t^Tl}^;~@lG%>lbCqfX?P=YAZdxv
zkeT?@&_;IS*I%pCGh0+-Y&)O>pOr{d)$fWglpR_CbFA#u5$Dvgb7AGZHSWn_$|E(0
z)&n>WO0b^w@9z&d!442-%LUJKULSLMrUPSuVt$4p-3yIeNgsN~Or`k}6}U;OooH?j
zij*6oJ2!x)i6|~BJF$o5IE~!0e=}!LmNXdN2?s7;`svpDWbB5+(8WDcJ>P>!!N#K6
zlY()7?Vr;3!V|6{*_!{HK$tlxr<3Ud%@ZFmDMH|!LK^}13p=G%MicTLe0^mM)ggAI
zleUIVO^YPs3&Vr8Hw4vC-?vAY&1y4EL6utBaOq
zDegk7rO7yoYimiDhs8;%{6l{B30w2xG62n?iPsM~pc1^9q$DGFrE-O@zB|}l=0kxI
zM{qEgR{0p;b_`YHk3VPtPPN7Liy2Ey;A~sS4jal13jH*qJ561%?1^1L0$PftC}xZx
z0)Fh$Lz%QnP&UL0N^W!9=V#1#VjWGSo~HwGa4o<`#P0(b!h=YRI|Tb9dPdIoQfPgk
zdWU^cvcjMD_wUj&LlMyY#|Jr$#&`c_t*V~F@5t&HzA$fDCe5zSSFD_90Ra%(+vJN$
zM$`+rJ4n$E=th&YmMKr5p;{`##->Wvi;krpEWZH6dyN2
z#xli5@P@1&LJ5SIt74yZG6u_b|A3^*qRC*$GpY;-op`tc`+d8Hc{Ybd<$wfvr7{a`
znIUOdh(IomYF*yWClqj^7uPHq&y+A?^+#V55a~{@Vm?Q
z3t~)!lxdTd2j4LQqXrU&I21Bem_+GEspE9AH+l-wAm0mvDvf6l{{G-KW&QU6ctnLR
ztNRb^Jy3@s#vE7<1U}@u2lR;VdmK;rungfp_L_P?8g`goA5P!iQ3053+5s+LHusb@
z1X@yOOXps2K9aVqMS)z*jOG+fCIoY79_piWnLCh3P>&2kim?@hWyC~z)j|1kzC}_R
zgl#qEZF1N3v~hqCG)08M}%+ga*QlM8<7Ikh}Ci&lJC<
znN<7ZLDWCPvHv~68|pMJ~k+8T0j4tzk75Nq6%2Yf#606_ty&DpT0YSHOKb%o7df943925
zOBdmZdHxG~>e2uUIzm#{hp}%7(1xK7*=-)eK3Bfv>p4*-1C`$y60dfx5fwr8*2=xY
zu^Mjrg&h?OLeakn5*BGw(kp8A#i^TXTp_);%z8p}3{6-M%#zpv2AOtI?#XTICfg?g
z^&9OF<&7mmm*26sph5-y=!v4*h~VTq7XFbl>?##1CXH}>0W6ZooqUlitY%~#G=M38
z#~ZKjacQ4i@tzxt7$i_yGi-Oi&r6LOuvffxlp1{nx64y-+x8R=y>R4ssnt0tyic=haf
z7W5Q7LlF9S?()pqR|<_VJlUgMe+iX09`gJS#}vX`Q0u6J3po)8k{M$El)`Z8C(w&$
z5X3&co392ub4O+(+?Ue>B?%7|1y4wY{e{*88xnmy9QS-~Jfb-sWkr
zzyallN9qOzhvPozU-mG5KyG+jHwaOv8EEeLQghL0V8F25iV0yNcVMcO>O3&PC%AO8Y07=ha+aO?V-muoloHUGP4Rg8-Vy&NN|*a
zL~=gIvyYKnCxu=skGr4LH6mzd?2Y^dJnQP#_G6Ch;~mg+jof!=xr6
zw7S8>;hGeFVSnQ!dLI=JsBZ%25l2c~IYXvFW+1R=sH_0{dwK;=HtzlObCZOjI8$KQ
z0144jF@yxjW|brbG1J0>sbo6|(L97ob~kfmHUxL!2R&0cM2AB8%TXqKWs}fE5Ku4M
zoHWJsflh=^$c9J*J%rs>A9zd^xQgRLU#Q3KZ$u%2e%Nn8;v|UG$^e=J&7`Uayi0uq
zH2sooGE|*GB|^e)M<|e5BV42_8Ck0Zd3z=4=P;CFUFb{*kzhY*F}gau3qg`!om@$m
zL;eJ$E{DK@pYoi{C7eNYW0<^KA<&PSwGUyUwu3CCG(tZUuja_;6Zt?AfNO_HlgVlf
z=4@|xsX8-0W^KISfi$T5pa%6ikSlUO^UWe9SRe-NqHBR1|4
z&G7~XYzOL$a{%}lRpVsmrZTKXH(gJWf0w^hKN{8%%<1)?uqf*XpOI3_
zEq?EJJh+hpY!@H}Mq|b;{iWj9iQT~x1>232k-_!yO2LbPgZNayhwZ}B;5@^714j&`
z$2*|$NztGeC{2W{p`WuFkCq5&GsTeaBf})(vd66NX`&32rLQOa5-Z+8^KUL$0`&)1
zq>6%3i+JJiP&W^_y@u#f!DWYij@*;cwb(
z{LZu()Xu4CjRyb&uYIor(6)z0E%MX=Vgd^@RtC4u$W%Y~2rL9z1U>8m>Ija2r|vH)
zoVmOTv~FBiC2Q@$*Y?&DSF01n@obr4J#WWM61i+A$TQiSt2&7R&0-J*SYVP~OfZ;C
zq?mj#f{2zH!Ex)cSBHhUMbMw&;FQZGcx^Ly_^GKG*V+3w*KA3n`S4k`M{xW}JgEG^
zq6y<@z4mo;R!p1UG5jv%1~F7sw)WL=FvH;w3h`|cTqg_wvS+Z@NVbwedY$VV^YS7;
zA_`kv*NhzGvVtP>L|GXx1LHoedNfzexeZzem!(b;_|t>jezeyZk#tdWSz-9DKJeC!
zC0|gepHscrtX)%owlRv#`-pr&yVX?~wQ%BhSOmkAQn);V%6`4AI+J9VzsQ=&lA=0D
zwZb*ZoZ!0Rr$nv9Pux!_TQhg$%~d#szWE(GqJLuDC*Wo{7O&{32-LM~wlGc~Asax8
zxnqV~Lux-Hwb?uuH9SLQicaVbV3!X66g69s-yp7U!fZ|MzqOPiX6@n(y{);!?%AHl
zsrZ;Y`%Zu*djNKxRqG5jgFMEV8vj($T>`kLI=A;^tNSZsGh8DU!Juw=9*OFT4bV&r
zPpqzl;V0g9VN-UmR#7QMoV1ht8%jk>HpV%3xfT6K?m_+ZRWX>m{#Rsd11-lUmpY@r
zJbmF*;Ce3|Gkw>|$b(h)iCM3;X9X}rJm-)rhk@%OJMo&_(GE#$W$j)>Y;N_288b^E
zvCjZQvxXt9vwYyNVH_1Uix}eU7ok6t7NGzcLp0@L`Ze)LAiLww1Ulr&*LxZ0PD9`OSv-4X%>y=s92-P2*J6mQu#4
zgb?Jjd-O46hBq+421on
zPFo{gysQ91eeQ&Y`Q+hW?hvC#jnk#uW>B_w=i1lckG%yGuH=jTxZIG02Ih;zF
zUO{2uulNe-BGjmQ$_4v3xk@KC{Z{5m-BwOe*gKRt@l3E2?CdG^=C>WxYhb$$ZI7R<
zL6$4Cx-imi5Axsp4(7&bH!7H>;N*1xEFK2Eo@jg#*rNOPV|R!J;$2TtM+v2Hf_Lxk
z!7D!%Pu-MvIUWDtGe5RtUr;SByy%$kBxwFHmQXLk-gx$TJcqu6eJ{mGliR7lPCly$
z+uO^LMAgoqwf8ffRWm0cIe30)MBJ2@GZI)(eKu~@V>0=9gl^uU4mbYcVnOF%U@X(o
znLH{Jq#nu68~dlOGe-YkFhx;_K1mAY
zr0r-JFTUU?4k@|$c>sJ$>3nd`pR3vPTzHn
zy*vTj=E^e^mKoi+2nS80Zz9d?C!{)KtQZ
zcr@P>W8wz#ooT(udjpu*^);_KBfw}$9gtSBo!%zlm4^$`eJ7W0;hHKmPd;AsAOv)L6s6%3HeK1lc++Dx+-0QA%D`XvUTUy#m=Hb&96^>0|ewaxnwsTpy2g_OJ0j%T0h8i4gt{$iSV-Gv@0vGEzP
zd(yekxHwT>vP1S=^6x!cdfq@p=lt~Mf@xR>9~M9pf+U~5z?NVT)51lz@(pZ&yF=5)
z?0H2?{*Cs2C-;HZERJF>6)wZ`1E!;-^Wx?J8z;~{ysTsyp=^OpuJx6-UwG!x8j4P2;|wz>d#S-u
zlP#_{J>nex`8ROuH`jv@)1_-B^1ZEi?YzrI@d^r_%2a(}B(6#U3X#%xjNq$bWhF?{
z{;Sy9D#jl)p<9$8%4k-reb~3Q#h+rRs)(7aWeG`ZHPQ6aZ0f93Jus(>WGG{`yX;7%
zFkSG9bi~V&rdD#O+GkDBk(Rc7&VdL1-KPfl52A7WxyAOqDoV$6G7@PmQDn~iGbMrL
zyU%2h#LlR==|_^^efn-x3hs*Yta2t6&y|DqG_BFwV!PwT{
zFcfW47kK?R>og|u6U75NJ*OP;eg;=pkKW~ZMvW~Eq~C(^Ofhmeupw@luAV%SM#xBcA;%Fl
zMFdg0+yt~E1(n^1Ttol&D57yrbb%e?7qO5j5KXGNYyaTE5Zd^u9nxTM+~bf?sLUWZ
zBuY4>`HtWa%-%}{FH@*In&y_Bx-Nfmj%!D(B7s_hLv4L=b5Z|qaEP^S8DwJO<9|VN
zOsl{HKaS5p>K3uf1QPsA%xVt)aQaaQ;`fvPUHf(&S9Cmc$`D^d9eZCR=S^mMSM(#M
z#3QJw%3D5(h*KZCNbqvvzN2Z>Ak(~89Zv25;R~Zlz(gEf3{HUmaSJ`=&_{<@RthOt
zKurq?&HVd?ca@?UEpA8>?1kc3hLwPxOhpN$@k&Pv5;-nuks$@SnFmMyp{z7QhsMv0
zoDdP_jDFsT$&J7RjAd4r<`wUkSS;f3>7&4m-#)mkV`fm1M^CmaPpS1|_jhItS^{Z@
z^qHW0g;6*bL<}aSXuO%CqWe=Ju(_;LDYS;ERlbz$G?qDDbuow8zX)>EaSt}ia-68X
zj|BG_BeHMWu$lidqKYCY)YaGJmw8oANf)176=Nti{!tQkU1IG?;1HIRYMhg(Ez%b~
zT`|5dal
ze~v~|g%AC;@FPdfBCXXjJZ>USO8YTJ+c5TbYOEUcUwi$E8IwA?rE#2XwO{mp{1tJU
zbRfYcY7vn#?}#T-A@ETCIgiiQzHexXe7kXR>=pboE<;wm=8+R@ZsLj
zK#omYN;0q4nL>>*kf@^_GC4B14BS0(9!#tDbXl1v(7CXEer`-=vw_?8^yVulneXHT
zVNT?j(Ys)|K?%ukrQq^BKwf>xbfN!WM7?u#Wli%xdSctQZBA_4wr$%sCbpAFCblzi
zCbl`Teb4)R*Kggwx=){~>grEd@4b3=b(Jj-7~7G&!?y@$Pvt)=CmtGwdOsbdS_<+?
zWSHIt<%aGI<%a!KquI)5sgS1I+B<6ykql6R$@Ey|@_l*uvPLx1Ax4V~^^{z%N@>
z#Cl&IAwUi^ZV?Q~k88XfuF2Q^a*5U-Ib2Kr-Qvp4CgSou?BCDoU!~q`R9Ez@&ZS`k
zG9YYgLQ}cr)d>rogGHrB536j1u^26kTiw}&z7cRkO?Vyq5CuOLIvW_A1r|CJoownb
zOzF~&9sm7#jVyI9#g+JdEE#Ousn>RS*cth^)4sPNN>7u;a|09pXN`4UO>$^?zFwyA
z#RvB5pEhPE2b>PXyRA-_ytYfV`c$COdYZ2uF8UE3@*CwGPH)LQzlh}j6*T+2Ez3%P
zFlzCui-cV+tR8&adSwTB!gn`e`T*0wTEDXIC9{Hk=k&**V1f}4I)J3(xY0eM$&P^L
zw13~AJ+3k^DJpwBfEi5GpdM5H6Rnrw{=WZV-P+&38Bgufyk|Tr*AalZbDuOZ36G4?
zXaZ7`cS0`3G7^75Prqd&^r?(T(UOi%s3{QbW=&gC<3@AF0js>}=1Ykr-s`3<-DLSI
z)4|X;a-4Vevj!o+eX4;{UqD3!WyP(jzVa{MYvvHSdE)>w<(4^F5=r+sf$6vEz`V|dWa;y}{14N2#
z<23d~&(It+4~hmO?5%=?|0*7XNK!n+oSMZ-AzOZ90lo*jQ#B3*f|s>QND|VE7J@oOXq1n{j^U
zt;Zede($cX1^Cfa?f5B3rC+2yk0q0zOECKA`eiY8a}h{X2>ZIRh%r=rWU#6uj_1DX
zBqLovy^kZM>>0a77Lg(P`>}P2({9x)BL0Z>wD=2su&hi(-`13p(yX`uVyc?&Av>fo
zd@uXa_A0QNsuRC@i3xh_Yk&A=#io>RW&#r^&xkUh;sDc@oos8(nZI|qV}ly2;W+2J
za=x-HrBZsJ(2y9%0~KoVdz76ZW6)<~E60*q+c^@V>NuOhwJfLx^B2V3QZl|4%s=-#wax
zp2=lODd%t%WN^w2<*Lx?{ef4=qVwyI(^PP1w~rD&!t`~WaU_tu4nUcH0BP9dzc!
zCh65o?pAf-%_-?;fjuU^Epf`ka-G)&I4Vs_EgH|`ZyOuoXk+X(Ru(`ALD6&!HNg!L
zC^Etg>HNT&KRtbHCYqPEXgX9y{2?i;_IUaVhWrV0Hj(XF2dKA1ei5qjCUkUS3R>e!
zB2gI$yq9|wy}Pl3#3sNuKXZFt>$$ZoO@ydprE#b2LToC-|Ai4gTKh9(l?yZc>^s5}
zTT7^uu@EsCq?ybXZW*BVvncaMS*s|ecq&L89s_rKkF6@@H#38j!G3LNLPl6^{s{bs
zmL3QfYpDC}0i%R$g)4bOUz=;sY^}U`HDXHk#+J{
zCcWe9rZ=pz+9P@~lwCzJI48#Yg7$IejDZM<_OY5;LJqHki)Jzml4C=|sHL-lz4B>o
zCovnqGiyP;=_-Gk@JCVVQ8P}qupZ_8o*gB;sSSFxK|Z6Hc+vc4M%6sYdE3cnIB+zS
z4y$s?bs)O44$lyrXqWY?S53>idV0vK?*5Y-Tg~kfzWIWITbB;hmh*M_46@8^X+m*2
zdzwNnG#P2nVH1`lYg*nJ$=#r1Mn~AIk}k@4NPzs{!=5@n@@pPx6xOIzimA7ZZR6#UVyaPZl7%y2DJFB3?zWuif`=kE3`g2J-;TUEn+Y@JmSE)X
zT;?>6M_p$R2bLM7VJy&RdD=}FXG3`atR^Bl~UR*g)6n
zPK`NmjNuQI>MDvp>h|${hYC|Ep4xPCvz>r0Fo+6m`)AyNixp}z-d94L$yFJZr9C1-ZGw^eOhG%tF?64c1W
z@4t?JJ|qM~4mbW#3)OQq2GAjg!fV;PL8#A-E2SIr3YumlV;7lI&4=eOvk_$@g0r-0
z_`zQPfdw_A#@kY+?ZF=;HM24LIit-leqU#b@%b#==MN}ZfwMczy0)&tSrC$J^eI{%
zTl+w5WiBU@pxmk1)3@6)`@>;Lie|63s0|Wa2QQKyAszf1kT+jBj2wx_jmWNCTP@Ks
zn6^eB;=MftzjWbQ{kxB};<#GyUjkeB^pA;0+z^L^VVcI^2q&WW{#0&R@hD+f?-?v^
zVFH#$x%r#j;%sdpS_bb32g2N4&m>B32=CTv!grjzDFfD6@w+%YB4??s`iip=N-yac
zcv?zrHuHiJ9QmCnl?rdfiW$aUD4Vte>+hDi!uRLBXX1O6u?X*SZGlghme=`1GgeH2
zi4JmAahb|hA1iPPY&eRF;!^Q6#n!8n!Clb}1wJ1&wqp?Egpw{hk$Ey5}A{HZ(4+b~k7
z+kpprd#E33YvNmJZBpS#FzIVd-Z|i&E%x(T<=#`)3v%nx6LPD47Acn-nfd<$n8lBs
z)r4hc_h3?5a>%O*+5=xA-cD@g)u)={R?2QoubqyJ>P%Fajc7wS({i!9#aT~Eu67I8
z-|6CJK60uYQ>ow-71~*GM8zlA9cb&PCZOlgu8mH@bt^D*y~Nv1Zh~p1b58fdiL9&i
z8K^!xe2awEsgH#3>duHPN5cwcDm^1|wwZsNZAUK~Ul&OsB-FKH-U4*GT
z*wuW7zY6>C3U&hiID!2gM2K7?Sncu)YrCu`FW4g)vRp8Fxj4M9_q?)0#QsPz-S;=Q
zqh++^B{;vksaL-~iE&HlBKn&RQq;F~{fH=qN^?}()tlOND%w4m+La##^KLKt{0m8*<#
zXotbQsKxh`oaiMqT2Ylys5oXq(E~b#`$}idhqqOlXm|gCe$YUiBuQj|&
zM8!gXutCm;EgLaTO6X}Q63gZ5217;hYiO;Ss`*REO2*rt6MMHlpZhnbjoRUfihT^(
zj*q~-9A4%v#~@GjLUS>a@4BgMfsv;9kiCEP#a{)$?Qhq)xeEP{2&i^+sJWrXF3lGQ
z0b_qHe+dD3Yu3nlIKrC(Gssq_Fw=p?nF%BuP86~*4#cw2eqqPJIq~^m^JKd1!edph
zv1D^AU1yNJ4W~Rq&}eQW>UbxFj<{v_(xw648@ikU+`+98WR!9ilJpSvvr#4VIvmdh^NE@%3(KmXwH(Pm^SVBFD(r|A=>>2%T0Q_?R=|FDIRDqsZtUo1oY>@b~bpYm+7v1_cFr
zy17PoHrGm1HqjDCCRo`QgNK(2+5wX@RsXI3vbzYvcE6%QM`~A7EK5cgPc>y9YuX5V
z)T2Ij)l$~F%(X-8DrUg5Gj12Ye`$miC4VT^B7#*wJD8h|m?+zrK?szhplgT|>1~M;
zHcfXpxY;me$uGKrg+hNr)7}qnyIUZRzE&N@WX)%fhz%l2F_
zQgDPtnGw(LSD$7*uy=vpEnJvS5v$BlyZMv31hi~@y=-^uAYR9=U9$NZgIKHU^R+vt
zs}8bG?kSOp9@W%@yTyYVQ#hAtTi6l}T;3%)U#tl2a%sVWm!`Rzr9J#xu&Iow0;$IK
zk=-Cn2Ve9?4}V0B5`{D-bQq;)0v68YgOIqD`@d{2Z0T)Tr2EiGZjZrhW2)0{lgo!W
zZkbr}b>EWW-UDC@b2`rXM5@lF%Y{0w2#8YPN`y;rrzDW!dj#hb-rdrnHL!Np{j}*^
z!jUtQNW8cYH{4os&Y0HH-fVPhpP%z!X?7!oZaoxDL)&3Nv`mLew$Bq|fAoAZjn53L3Sppr~-vHORi%f{;}OWff5EF@W0Ow1GM
z_w<0>C`{SS@t(HeLB$VEvHB*MkaOzJ&*?8Rx8yR!@e4y!ug;j~o?3ZgzpW*nrgyIS
zsUUlo5--DS)e(ki)SfX)KX|owiTOX_t05!&{4)YB1|uo}rD84ApV=_q+mczITkAw}<~lubJUADdr%PyW9u?Q_Fb602XS-K3u>|R~Z*s=OG{>gkr*)
zU)PfySAso>Y`Bce__N=xRC3dfc<~~T$|39x!(&e}p-9Ql-n2lY<*uQYu;uQ2J!37RYL2bdd&
zy`Y>dKxhJI3>nZ*KI>D1#BxkBp&+qg`4XbXb3iw$X)=NroG(8Zf4~ML)uF$|tf57c{pQQjbT)O}c!
zPibVRy0E-CmR4KGIO&TWR!?W$L0kh0OKc$2a><0cX_r69DQ?moH
zWi#Hd`6_gdeLzIhzh9X8HM}jsjXW*FN?)H7Xm7HP7WW`)e0~z4EOzE#FneF}Lg6BV
zV=AKDryQM+5==r_QZ@JG^L4G-r@F9#OziwuB%D0Axt8UZPfqi#s*$E;C2uOOH7FS$
zWHDDafC)db^&oB+zVP4~8%|n@q@1PBOX1(mTsNcmH%D(}Y2=>!`_)MGe$BlB9z3{P
z;FbqxYxu3A*>PmW*$w`G*F!gK>Yf?9TX$o3v2AOg^ZR=$JwI=s*dQ9k+j+qV=1QEm
z_Z_r~25}xb@;Z*X1YVPlQdkHsJ;YS64+ax}+x^;Y<+>8ngP7%_A02p~dze#Dj9o}`
zjqsvBV%Hk(Ghy_yI(qWtRAIJ>@!FBK@`%B_hr2juBK;b9wTi1C=mZ#penT1BTnXF1
zLH#CF$GOb~5_1<2M2n`VGH%ck>YtCSLG=p(x
zc7l#t2s>Pa;P`YSBWW{p5}5YuIFinhWAN^ZwWy&Tj{>vK&~G`b2qrMW24&X8d)wDB
z{CjHf&qLPhxll&`{dOfFb?0+J^?Ie+5!}~Z6H>ACT(=7QG(|Q#*(F#0YsG%)8P8UJ
zRQ_n=l674#Z@3I8+#{QP34w|TOTnclwPWl&59A+h9+%+3=r>>G*kg%jnxD}P_3T;vK=f1BP72hOdxop=oH9g
z4kp%)@YC@_eJTQ!rYmHE?to`8{Y%0R8_E>xeE8}Mks@l+IkdG$B@IfOQ;=Mlp|}5V
z+iG_|B11sdS-SP+7<_W`Jcz?+xUYnAUosCQ8v48dH;;w)^}bUVf&LN9<0Mwgp2>hw
zGD8|Zjb|H?Il~w8FJ|M;MItL@zdWhS2+kE%GMX(
zv*I!J%r~EtRPMrtDS{p<4r1YyLP*8DrV>V3a&t4rWu_#buZ+gBbd(-Ipq?mq5%k|&BC0hQ
zUJ^b3YAWyZ^}5%`koCH-Hq$|AIqSD2WAqtB8zT^G?}(VC@!MJatXz+4b6A^)xer&t
z+j9fM$i#v{*eiZ$lcaUkvV}HN5~+h#Zn6mAyJB%@a-QSW3B$V{hCg34Y=wkkCZR=u
ztuc}}h>0SLQt%0CiXRWL9HKJ_LEOLEE8Oz+B%Qsx4Rz31WqabQBkS-z=#eaVOus-b
zy-B!P2A~?_bf~3Jsp{9_GsU@gVS_lcQWt8ZztqHOf`DcvZmBp
zqv7W{2YTi9-;t`B&k29Le+He;>J-{=)_0`$wz$WFsf!3hV}I3wspTlQXfi6L3waG2
zPr_y2B^cgK;r%k^~#AylzW()8$08o!r6tcb!h8?ead|?_ikf`<2=6;5)MUNCf_mW$eaUjMtS;hNO4E
zArk1|>*G&pfa#+dvJ-$5fM#YV#2dshTxy6CL9(Oje9UwLwnsumJGTi>aRd(D*gSu{
zbZYZ=GcnI!3K_(kc}P|lTYm=Gk0oa!lWsJGmUKFRKw*rOb&ku8qxb1UWU_BZPh{RT
zpyX(0)~YdHm;Y7NKU)1;01?t;^i2vw0ct8fDPr-?|bQvy>#O7gVPavGcJU;
zV5PV}_Jd|e35MsJU)lK~dP>H~9SjeP^t-V9>uHNM>8OTW@2Cbs3G&VyG-TkK=#T41#IhClCT@___1
z7rBsqf1~g{R{g2ySm-{Dx43sDxLD21pyxIT`J%@6JYXM@kL?!6oLu03qKBXj`Oxed
z(UIOddWph-ViXhPG=__jL+^3_0kP`ZkoC!oL3dQoM&F9^tjCQP)+d=hiSLE~C7uTz
zyAl#FrmUm1j<~&13?dNzS|O<_h!T6)b2nsjV(Ec@Rjv4ypevyN_t^ck{@3>q5d_b_
znOlhy{5`WU@Coidi+(|fom;NvdpYcAKZ@yS7RQ+40}F*)p9CYmrKoQY)zKp?tLVNn
zR<~#=4B)Hg7QpYs=@Ato)G|E_PDmw1B^(5`b9OHns{cty-D4^nhSs^m?A#=+@*z!6
z4DI!o<%R4zFc`02hg*!b)>TjQNC2hQPb@*l%fb1vLZ@NKYVMsS>62K8U%>UQljvoc
zn0v(IUHl2EARtq*j|!367hY>TZa3bu%s}HU#`o{P;j;MG9Yynn*{N;0ol)N0Lq-Kh
zYlC~kZ3PxGL;rlrgrpVH?eA5wK?}iz>lq_dfs%5&vf}tmLF53u0VLrr{!_Lxxvt+(
zKl}xK%mch80)Iq_u+?Y|O4JQsAqd$}40j9#cnj$o!#_LnI;
z_pq8v0mB>@vZRDs>zHF>6ijB2Chw{D|I(kCH#Rkbck5h#d9?Xh;NT#mRW74q{f_5h
zjWCpJWHUxUbZBsZ+ygi-|Ad-1>y=7sk{_uOq27eEbb%`K|4(x#2t>pEI3}2>>yH6dB7!4;*GChSuy~xnLI6VytnAt
z`yu>2a?7rejyN^LaTXltl+@#Jc@cY?Eyr=-H84T-?3AfDeJuP$UDZT$89!26PrDt)7Pbqpn?wAu}P
zn9tB!lvHbT+biLWrV82x1;+~FNi)hrr|4aj-4d|qSK-ZqN0m9lVLNAxCveUdli^IG
zSz0|tIuC2x{!Hj>K);rjiFGwDPzM|MXO(~PRb)5#-evj7mG
zMhMJBTTs%bUoy+`7NVgU9A{tWIy)^c6h#nIh7!V4Xy?34o#AE2Hx@`(Lj~Y@#vk+x
z-I&NNqB@Di*$G*s79rn~8DxAU|1r?gb1BtgpHRs?`sq7}K%#-i@|Ck-NQrv6xv2iK!dnl*Dk5i-pn&P=P!CJ=n&6$%GKgX#9PqxK+L``YhcVAXm-&s6w6Gggju!y6hZMQ
ziJ?PCUmFbnv~0Di^_kRgAskWej7Jl@2#-_;bZdh*w-4A#qY9=FOmZ_BVhS-Obp>fz
znXPDYWwvWawa_2n#H}CKQYPnxK!jdwk+vtun1_8a&hsX%Q;$A6@KXN37JbtqBn!TX
z!z8R{)A4FoaNIlKt%Epys-Ls(57qPbE-!SuQsCUEl{TFR8N+@X{{|?@f`Ow0AOX+-
zM8{yM7sDQ9Hg*7DZUF=U4*&qn%w4T59Sm6*tvs#j{5M=SMi;L9^Ft^!FT2LUky4J#
zEiu4D&;#y+0EK3Ci`6vZ#RTeR(z21O+6_;J|0LHN8oQu~5y6oEok>)iq^7**I{Nq^
zZvADu|NeUZ4tP09boA`$<5Zk&LwY7c`Z@F^?C2W!>E!DB{dh3IoBj21Rrvhj;vVSg
z{_NEE>gDw9H1~eOBbliEJ|Jm0yM5f&^-1l!F1sRsQufQtTm_>KMJfLM-E
z^hNztQrPQQ@(Lf^r?02m
zp4-H2KAlgkAC)%laJuPYf@H2yJ;(>a
z@}205@?hDlD+Wo|MWyp3QTLj}UZSYF6Z|<~%2hG+sU5$7$16va%R8n^qDt7hjub=7q<8V1D3B;{U{*@%
z$rC!k%eMI>Qvr=q+q~JKGQulVWqtVF$^EXGz=ltV7zxg6j4%3G;Zukj++<^T`h1t@
z<=WN}@EZQd0yDfS+o|dh07|G(qe0y>rjLtF!O4902wAedXY9yKSp`ver_;2k0!fY1
zAh6hPzk$%dqTgL9zcvxgr)uPBhy!HJ4%FpFWdv
zs&pw7n>ryXjCv)8VRevt>eNTL3QWRt1R)FtwOL1*ER!q|an5cI25
ztsU-+-p%iKi+9vGdNlW!VzA!RB$AknqJcPN-ijLScU79!X6!#N>Jr
zb)6(xn7}3(KPL~qh2{+wV~@$km>eAa426my=5c(YJvCpy?m&aAaAq83|=|=Zs=+e101DjxK^!#PJChL3OYudqyh6nJUhACStBMKlTdRZ3RaDH
zbolP45%wYh_c&BMJ4#7U`pCH^73zQJyN@oI(2zpWQFS_TuZz8rU>IN}!xA;(x^beX
z`!s2C3~Tgdk2<6#H5t7NHD_tbMd%?DCh+7DWnLFqLj5p3{f;BVtM+K4zf1)0uSWoF-KPN6
z=pj+3aS7tc3|s%B!-Wo7$8j&zM!aSCKEEv#b6AInj5b1GYFaGSlGY=0QY!(0>JD_}y4>KedVKHgpbkja$tz
z_SU$M>;3bREgfpg?@XarID~~Zzf*boo60Szg;uA%ScMTx%OtrLURdV-h9i0X`Gkb|B4AB^I8s+<`Vja
zwi85!`4EpTxlI~Yj05o9=Mzd4)}6_%B#nq2$C3*PB=0=%W!IfI#rYEWtjC%P34(*W
z3C2P^@ZmP*6E)yG_-u@CQ7Obxs+B{TGja0qs=az;)Ec2r1j<|9QvEsxwK`286;BOj
zG_Oi+2t#j`ub=x2InBn*u4eVFQB4N}(Cdaw7-o#zub8Olq$+8vm%sNO{0q*>%^eKI
z0~UyqK3kwuezAab{|Vxc9J~0-exxf+r$VfLE)vyiw}mHl{BX=@CLLT?OOX-6<3f|t
zmh*yb{MCYpK@633$6(`7X%4CH)uz%(QC-1kk!lHJvzvn=qEz)HgDunq&QgqP0z=ZE
z0~2YdOo6YTh&rkqC)d-Wn{u@sJ|KtKoA62j}#*}lrY0G&wIN!wJ_n+&~Y;)i`DQX2DOFU@(qwcDrVL$
zi+>kwfQ#$~gB;}#Vn+BgxM1Ar4m=Z!CM|*1W7XUnad-+t@wm&_7~70rlx60U?x14j
z^X4^lD}ISl+%s1QJAiU&Gk_wYu6*E-?~Up*`w~;@GbMz~`o+a4N6gb|d+S|H;XyGh
z_HxE@WO=MlUWWgc_O|SOj;7(e$4Mhuu`6=oLax)U6XiBg&0!lKGDR2d#{b8Q7>AP4
z{Saim-yA~Qe@mTz$03A`&TCZLhv`h5L#bo{b(a=f73VWbGvYPz3Fq9xG9Xled0QJX
zT(e~kdYlhl!5;1A@}ltm+B_>dcCr~95A*t+e%*$3kR
zy$n{SqMJXuH{mBF?M9m^6?%J8DwgOLD>&h6?h?ixd3)ICUD?7J`ld6cz(x&@ml;ORD&&?*Uv({Z}OsYnR=V{QE|mr736z7vp6PZd^}X
zGw`VcbT_w~P&&NnxE(H;e()ta&XY^cML?ZEo>QQLuiRP}Fr3|xQz0vvCc9I?Wm4fN
zX8n$%nv!AMItm+mT;UEYGn)2;j)xf&%31=SDEC2K)+FXJY9{za-h6@c5XSn-p)nyt
z#G3o!`i$x*H9n{y_>A=a`8n~s&Px0(U1EbM%toBffMwSi_a
zRb9)~hH3!yHWO9%4Rdk!XtF0U(qep|CzMZ%KlHRm?HRBm*@XN3_;?O^#RB8=x2xtv
zaNF(0y>o5zBf$NWs{GwO+E!^1iqJ=Cj4R1v>mu{Z?ZNV7dOaTXMf|nlU*t@#NaqVU
z&dQGy`8UgUt>;}X;)Fg=H=fG^X8I>ej8HbLS1PJ+_HjXkd&QEEzgc=p!oVvWhUY}g
zZ6&P3fis*tK0{o0g16+@fU>|#eaw?qd?>bdlZwWJlZ!6FrJ;+-+!LtB%K`8EOJl${
z(hmPlwPV{S*Yo+S_BZbLT4p4b`}50t!K>oZ#lgWb%$NV$UfWk+?5x7sec^-m%Qe>q
zE8A^DVjI%u&d&!dn#|mqhwF>3KhG6JT#g36zHeP=c>pi}(2V%MZrglbi@tr{f(0ct
zUTja=2Asdn^uNx`-mRg(udMI8y_KJDu8CBdB6kW2U*t1yZ}8BAb|lUW5A-<4@Q%Go
zx;K+Yg&@g-ynBNc&!1N;A75^Mygz-iygT`Wl~sK2AD@fcf<$8rg76
z0btVup>=BfpdQtGiEws`I`Vr1x_ZK&#HwF2@zf@sxVTnDMzDowxfpBv7Uelb
zG}n5eTee}rHgCX%uU&=@{(D*&+5WPRff~1`59uMO)Hz@d`s0J{b+$6d
z)Z1=|wAb6i0e_qgT5Xge#z;QWQ02G%09({gX@zMm-@>yKcTwnJcB6r_0?>f7ha!W@
z_kjn;vuqLplUAbI@1#-Uf6nB%sM|y7KYbzOcK>h|gE?AqA8L>R8(%|RqmBMwB46BrrDbuF*(
z+G98UQzeXzOPVEk^{0&koy0;pl)9<$3`_>BNTgd@9#4%>*O?^}*=1{*vWcYVXoQ|o
z1O)~i3z+7-{^g{`J@(vA!h^%@B*eEa^A_FZi>_yCq20)WPJD2>l_E|mD@rApx(XAj
z6y-IaBff=0{k^D()FFjaEq*+N)`#Y5>=KPYZ(%QUpPaMK|FKGz)ghyO;GY*>=Sx#wNKPm
zf%EMSip1(j)5)PMAuU=KX7D;NDQ_~@|L6cBtb~9$2&DS-L)dg}X^&KjI9mR2J-L*p
zy(rePWnr0|vW{RDBOwHxQE^ffu;CnNi;`dog{?<$gDdJh=g`a%$TZjCvkQ8A4ib1W
z;2tDL3xNVh?U90>FH9_;$3bO?dMVO^6kyC=&jLWEFHJC(2SWh&f`%u*Eu5XCCpb4Y
z(pmu{CXS*k2iE=uxk}uG$-K%mebQa1L5c$Nw@fT`y7hsQOr?ULKWAMkj*Wh}6YIzn
zF)q)857kIx)mSIEHI*MrVbR%kKJap0sfNWK(o@MWEkx#|
zy9!-*X?=+f!qM-Lnq}T941=|0<+^?FYjf&^0kjMX?Y1yov<1_PbmtWkFrlb==R-;`
zFRZe?FyxU5i5+b;`#ZPft?V$%$DX?_=8~@oWk(QGl0C}GwDCjDwZihFvZu6=@pu>~
zG1Kgf>q1tqj>>jR0M0ye`4L~G991Y*5=y+DPH*TRH&%!y|+
zVj--@v&xguJtmEL^T$70FY<}q387@|6Dh9?)-og^1n=b-
z^lK&$t|;d%Zqev~#KnFbL{S?uN}F@c=Qo6(qAqMg9!+r1>KQT>-QYhpdQ!6aLq;q9
z#&_>`D*K#-fWo;pA;)eSW%tfr8Dipan~f0-<`XAU6{ELb*agA0)5BcdJ7*
z#uvV6$a169%IlWD>cKatpBe!}wm3g?p&ewZq#De
z>k+RPY5@zXc_92_UL1L
z+}eX^M2s&eBw89Y+^jW)IlE3PGJ%
zQIVFJI{DhZT+X+cCHpy&F3-U@sMlU>88BvbXAz;2mTt{3%0}1|SHZuz3eV_iMS9Ji
zoK!3Eu*Se9TsoJ}k_HH#cZKV!T0Jk|ELD9&bpws-7gl~_sxp{HQ{cWB$x2nwn2Hno
zpG_5S6=F8BYg6k{kw%IaT+A8Xh=6x{>E9@H8
zrbbHV!J0obnBzDJks9L@p=lO{#^&mUBOAr4P18=b>XZQ1&?FBsOYj2hkBdq&alg2{
zV0?XZ6tK>5MA&;(s!$0sLLQ_|Tp#77St4i=lz{QT_3>c(0ZSx+AU>TN(0LOGY3xbj
z&0^vQI
zxzOTb(>kXt^txQy^cFkX#Ru}NkX#6)xPEPJ+1vKijBVC7n={}s<84~UqEhQr9eml$
zrVPLNc6{FS-~#4s09pfE8>(XVkV!)*AuC*LC`}ki)qfO-CqMa&4e;ZQS^oPU=RzS1
zE7DbKs%}{ISTc{3M+FVQW32#rab9251Y>@Q*6X}FH2JQsS`e!c9#MG
z^(o7(hk2uc(~(Ct7p`IHq_^S_I}W)K!)i{Uo~WUaxvP#&d3p?kGqi)(xPYw3Z%UrW
z^$liZ}EcY!M`tRer?qx+TWJw*tiHl_BTmF(=FuoflsOvGK(h>*G@
z|GYx-civ!NS$<^=u3H8h=4wm&dc*7~7Oj3Bry)0I8m-9r5E=+Q461!+Ll)hL&RntTwt9%dYDqB27%6d|1F9}qwg}Tex-xdzU
zDqGQt))h)^_>8L&qTm*frMAET$c*mqD$^hk$0k_qvTjsQsKX8+n~Fw!u&jy$$(^tO
z;ugN9W&nDY$I2n2k|t@wqAmbXbUge8s$^uNaLmH3k_iF`>qO&25DKp1%ih?P`h)}^
zpDX<10YH>r<@iCp?GGn+A_0gO^HzfauyR`*9mtrSsXizPi}3(}HG9H^6tU+7toXSc
zw~8YuptSSg4Q;$f*t2xCiOih}Ahc>cf(W5xfn=gdUk+8CFB(wyE=tD`{zYm3=-|an0N_k%?2#gg&$lv_7Zt3E3n{Xjc{0upg>|68yn$G{%lgD?v9YA_q5+7P2v)L%t~j=oCA*3ibAiwdnsb>n_eC4EiB#%&0{BNi}sN;DJJXKUIX+A)LCH$3Cp)0>>Y5nM;#dH9m
z>bSig+~vep;anEJtQQ<0#qr;G3|&+IVPKQ&|IIWE+?I4t
zbn^cOVO?
zJ1liB3kYgyaPfyZG`Oh2Joveoi!I#)14shGD*qp>UqBkg|6mOS?Eu>9Bb9_o;QzB3
z{lc!M#R33eO$-DevIPR_SS)mfx+VP?{aCR^rR@!2!@1R8QnVpsLQ(`QROGGI>B@*+Apq9&@Km
z^0oh2f}6LPjV%it&Hv0n?mu&gS2&l8E1LmA?*2cjE-_CPOA~r`N+9HX^=v@MJIQqO
z7Spk1^?_VA2^TWN&pF4ZSKrD1o3=G{xc^f=M*M%u>qnFQPcfA(XMLDM#(7|8+$sOR
z(fl_$vMRy<2tNOhpo}}E6a7D{D*Ml>EZ4}YL_q+9*&_dx01(G=^M^`F98{0g38jP(
z04e)~3uR)@-f198|0ieK87OCF1qeNNiqHS76MrT5KeOrq5^w=Kns)915-e{v{cn-1
z!2>~?20|SH>}wiDRAEd-61bpZ(D+b+3##2hG6Y>)FvAB0K&H{gG3>=Ww0HRjKq@xNz=I{u2k(3RbYbPtf=`9Fdl
zs6zu){H1H&3?CrDPlDlXFeRfIMEPwn2F5r=%AuZ5CnW!${X=Ssuxok2V>|o*q#0Hpl5;a{tC4i~Ceu|f2HC}_46T{6Q+I%h{3?Vm
zE!~8LR3-VVDl{?udOALsAuDfM7)P%p6H`|lm&l;xhDJr_Wp9?^u3o8u+)%uaQ1U6N
zI4|$M)EWBM{U0JC(ZII4EFGH={=GXsUeLrDz5j0qEWAOyes3m*e(W?#Vf>k`Nhb`7
zrO2R5L#}$E>8-NFhF8X|zuvdh#KMyD)McJ;zqnF(gkD-4(-DndD(6AcPzh?dQs@{W
z6v4|}P3wl%I0Zzq)yb%-D-I%J_0{Z*D2o;v$g0N+t_GX&WIgsUW@EJP{yGY@-jQ_+
z6kH(Cc7r9!Gb?m+`Xo%xAwJ;lWgYICHz59Vha|I%^qzGMB%4+Waiq-!s7XPo<{9hqL4cVY5B_&Gjg~kLu`!NpTxsWvmQz8*F
z-%U&MFdxJ1`Nbr3E{jq_tF}VCmNIT(gV58D#Tf(T(DQURA~92ho2D+brrs#534uPqEqgpyNJp5~6{Q=W)}k?)wiGo|
zF@hcJf+Rrnh`cd{x3-$ma-_dcJM`nLC-6!7p$QqjFO5Y
zQE}y#QG*=p&pN$%`k=JcbPA4JN`!Y=)Lt@WXdR8Y6RHd^CB(HxWY>e4=>`OLtO_T&
zI_YEj?q$@X6^`r9u`?jnKhWE!t?^5@F6C0JUZKFV;K0Vj#Ua{*Z
zTJF=Z8lZn;uT({YnI?$2H?N^pbGvxSzMOfze$$mcd*`>tt$31`WmlS6$(2!hiL{h=
z;|+aEoekd&rwr^5&x%Z2RknDtDzx&OmQl)DAN^p;qs8qP&T0t-oSZQ9Q8b;qJUd)_
zIEtd?u(;XfvS0FE#W-E3zi0T@@EupuEYYAQ2T%h&Ymk1hu$FB!|=wI`-D>=JGyE|L#2EXP$#b&S)FEznwJ_v3aN&|mwIp(gQerZ}GDw+;Rb^n*Vh|$xCkTxgH8{Ja
zVAOI{O$@kFOVbKq8MHSU?i||8H!(XB;)%hixp$4~(1Z(J@48ZGUB!kcOg)Urcgl({
zr;IL&Cg-HISEGT$jwG~qoNR|0S+`%08x{4n`;1!EN9dW6b-mF%7}7LrAeaSMs_AZ(
z0+YM7gUB_5OhRq^mv-X!FgyE&Tt{|FaH>rt>X&istuR$E%tum+6g4MZ&DVrk0BkUU
z3fj-fMOa$Sg3XUVzm+QI7qLp8qM4tvp$W=#QSQUjhUV1fFz%I*m{~hSEWq640n0F9
z2GEGypy`j|MF>i_!3NNRX4P&QsfG^9w{e;DLI+Et?e?zCE7atMzjq5%kAB8hZC=u%
z{6!B;C3KO!RF8st4PuAAc?B}{QyM#>k(G^@XSxLx9<7=Bm*oSXMPRVE&nu
zy(Wx$G#&F^L$e`XU-H`knGv~b>OD1RS~S)s)-K4(SN3v?C!OF}6$khnZtqz>0HL6U
z-Aco&N1P|V`<1Aat_)I$*9*eA`k%0CQjaOW)2moZqb0U0kn&%_xkwxnk>Evf*uDW)
zS5lpbD5jV0_HWvy?)H>g-;H`2sh$G@nyz&hlbFZi`V)qv11X%vGd1?+)O;L#&Y^6ph!)6~P%_x%7*$3ky7?Bus6i$l
z9Zm4RJt5b6zs~nB^gW0h*t*mK}Kyrrxivtr7w1j_#5<`83r*?D{esX-P9oP0;(&*;E|sV^xeT3I`zYC5a=f!vFT^#%EEkvL>@Ao&^1HeEZo2f>Aq_lcmEg=TwAla~#5jz>m18;|!Kl5`W$QLpcC)kA
zvcTX^j{0`KJDh%R1T7+3P)Gw~xTPqD{%(@gh
z?3Qe1f`@Yh*IWj(5yr;I!+{669UxLhGAoPvC^tcFOw6@N)!aP7C~VtZfGw@LSpzML*of&EKRb|@94(YP
zU^hT+)pts?JH}K%&d!vNa|PB@uLnyz_b>_ICer4bS_b}*?OdjvAk*kH(GzQH(q0cv
zcLC@$oZM=&20DhJZ^oS>Gf2Tzd1lHq(6lkVuw>iQde%0!YlKWJ4)i9kTEn&+aQ&4O
zJ-n1wSQ5}phbYbMDqH8uQ<>>1>mIW$ps?L$1%$&LHX5`y-zSzW%k3_^mbC+Vn|Al1
zCtFu;7+)Z^nJhLKqlerOG`WEck$%})ZSS%tPNheWX6szObm(|WXP_=bEA>qG1fNYT
z1mlRVav_e)KT|mTlZ*h2`zL1-utG5EFFGRzpkoD}pNvQ|N|%9wHu*>@xkw$GphtAu
zFP3Uz=g0$RopS_4T7g`yAeU)XNUdc@zwEt@;K9^yNnP%VX!WA7Y~w9gNC7LcR&Tk5
zPPPOm>u5vMZK=)E&`4o=f|R!#LZ4Eai&a@^!WSxCk8ondf+5lrhnE+)p$E1W#KU|h
zY7C$X9-dOTp1T-AyMrtM7s2Tc^QBIy8?Y5a;Rr|SNQ1biC@~9x;U)*&?rIdAb*PgK3~%>Jxv
zPsWt+tgo+$1Qg0u%eP_1W+wP84OYAuiA62!fo!6kzD@)&q$1_XngJFS%rjJ;U~0wS
zbEl&4y9G|j&P0R%jJT#eP?lsgpIBBnZbrp=A13sWH8$b~)c^8^jUGOs?o0j(hzo5U
zX7PG)++5!t9mZ#DWp4|YA?XC4i5d)}jkHUV9Syl~!3!|E&w0pnPPRCd+weED*1E0Q
z3lBVerlw4_Ng<_SoK34WE$Pc3pUGEczls#b4>%KS!-9
zwEgNpO>xSAxnu|cCRzZ03D{GQ5>M1$`FtIC2u0;sY6M)i`s6|@#e7I4ajWz0>0LVD
z$nl)RiKbxA{A9A4HCBLH34G*28&1sd+%WOFz+uN%HiLi(JcMr4*>arQ-0!(VAu^_b
zeMI_a_7kJiA)coUs`Kb%iF3Mswg7}~(h^JP>nvmJn8@wkI=%aF!X;rQN}7yM;Lcxm
zdb+)8_Bb1~R+_#Nl+nvFFwO+ij(*z}rvw`^t&}axQ5qb=Kf={?%#4*92dNrVWO0P*
zYRdFKkg$>Akd$pIG}uOI^}E+{h0b&yjGHngY`ODB)-(lHOV&Rr05d$6EKS!53p19fZiHtPOd_*cf^>9#h=^{u
zk&G1y+r*%`NDSFlU>t9}Hm}x{DMQ2ck*1hFL%=nN!}IfKb6%E(TUoeiqWhREOP99t
zG@L9&S2Q|H1bM0^M~tZe(o}ttN4?Hus5!I3amX|*DRWX|f``S*dbBpf#oQ>I2~L(l
z%bgsXH)8=tRzO;~oD4m~z%>*Ix@Lowkc^0OB}h>oC;FyYb&N9jrtsF0#pHoafB=jV
zJm6;w4#>cUW1J#7!2z9sJNyV%wbK@8qMNRNmNVeKvvEWATGe9syio`d`_uBN#UWjU
zjZ+}D6$`6c1vW{Q2D`)>X{X?T?>a1!>x^w&U6^Z7@OBe6$wlQhfnnGsnB?Z~AE;#AHpVTN#8@cXwjKUPyWxD(P>vt&3&Z(X
zNDjaELfzZyC~#jJMQ}W8MQ~m#zON;Oc+}5Mc{4)bPQIr$0KAUibA50Sp8Ifl`M3yA
zePSd$@b^!txt{BO_(JGtMSK``@Nii#`0(Fe9r#-v6|RJ98AE4m*s|QtY2q^Tmw+uH
z!w+!u%lae6<6v~DeH*2$yW8Xm)x+oHYY!qK%s65&sYdwXsWdc}WZY9ncvE%5+sadY=pqU=QZhbS`5}^oh-+8&=>omV?
z<;L4U-JJKgW^8zQiU{MwP=h7(^t&SuBTvF;!7g<=+=UW}d4IvISv*zwdszO_IWA{O
z<)j$_nNqf(yI0AW#90Xd`itg4HEon*yXoX*(IHD8e^m+nj7%aKbj2}}gM=VBCG3OA
zkqT&y(if-?vPV{G5y7YoX=`7Ry1hm9s~AN`6JJasoq=tKE6L!-%+lc695@M4LL4sU
z11LZc9Ap8|U($erG>?7f{fI;-0PsBYhinFxX>wlx_?3Vb`2dz8wa6a`PmMUt)*XrG
z8J(WDvRHeDQPiYi9L1+K2Hn9JSoPO?pcMPIq+_68jBf7T>C}A5)6iVa9*FnqeOLy6
z<*Oy=f=3ft3{;`n$HFa!8Yui+U<_d9+A~Cwyb+olyr6>2D@vc36eI@0W5tM!-qrCOWPnBVl03~wC5(2H0qGG>D}?Z9C$rW+~-YDuP<`L
zFYM2Rv`lno_Fj*&%&toK06crZE*24phDwiN)1V`)juU+9s7g(&Lq6=H7i?^TDb%rZ
zNZeM6sDlgI$=IWN%k}<__+5bNsi@*Y4ZkLVRw_NF0YodwQkng4ds?
zKlZ)teu|Toc9~sMnbY@|t6oQCf8~7R|4-I6n5)xkDT37@0`u^WV;Fex`Luiep$mF(e13f&4c!u(Hg){4|GImy7dKk?
zVa2{%GiS;E%zk#XM-5q0Zo!;(l3JO%YQ}_wAVq7}HhHHcAiZf-ak2>isOwY8>Md7U
zE^JO97PclCu|enxq`)nrS3O@QxZR<*UExLi+dN}tP#^8Xy42U1pIFlsIT&xDck6R)
ztE{sUojZ-5gW3D9R2uqLeZ0C{-Q5q!ZeiY?@?HJjxejf)2?1bO#<{y0t2~pf9v)tA
zVAmqctH6n$>jFnERWpIJ@cI%m8AG{WJ-urBIR=1$o@Rwx)>k#3YVw(15(0Rgq8`3U
zaRDo*64mm$WvT#5N>=C;d1_oTTsHlm;udPY9_?3^*Xn*YOF>7$pu8631W&ix(mcQ6
zxo@&+Ah|pd&SHM$Sp^2gK*DvBar{7>0@vp?^6m9FwKIf>ygzd<56R8ZpRXijiK
zCV*I#az!aT%=|8L{7UT7WP2@Hbssp{0AHJe>?!JAXfApJ1$@enr)S{l^HE{TMxSXl
zxnQ__)8w(!wS`WHL17nWoSy3G^4973{!~$80DC9v=aSRd|#?(
zp<4Yfiqg+oOeoi~h8{Wpz{H<68Vq3z^HG$};F@`SIS{x;wkS9Na%{E0__62S5AS>Vn6!xYC;J2a&?=V!aR;p?TasZw>Zmx1}L=KPn1l!MkrR
zko5RRa#PhNhmnxc7>ljvef-CL1vL1sL17?KD$iN5$FfPJ|4p4rkn*OP9XE%
z!b>8byYp_Llsw#6Wm|&D11^4mz~R3Fz6sK$;_+>E-?$-Dy=bAFM?#NfKS;%yPL^!9
zZ`kp5(YoyvB&xo?&hYWVmQa76UG~}G>0V_tzg!OTqyN2Lx1Q}C+CWa#pGuwa=E^G8
z+B$CkhAME|9^lf2--^<-361MBg1*#`rv{BW5Qzq=Pn=@_0$A2J4rOpVd>=uVQ7`R)
z0`(q}(dO>tE!fWD4YYmj$=lv5><>kk)C;v4$3P-}0Af|8MgWmN?_YB70#n(#-7Gz5
zz*4u&$pg%*uiLbD)X$0aW2=TSDiA54Nwbx4vLKD6EmG}6c*va|#+g+sm%+$d#Xu>y
zY!r?11~IEigKWNHAyIl8NFjI0H8KEfZDE`x11@_pUxlT8Ykq|@Ysb1!@an1+D|*Q;
zznggK+Pp9%-wvzL;$}SzTYswvw&o{4vY-RQ&0cuP$ew_@OXr&iaFkZPL2Uw9qZh(l
zmPC-hnjcqd^KvW~gn8Se;{w+&3)kTm{OX32D;{%I?G90Gz`|Oa3hJD#kUw=d=#{^b
z)WkWj!i*ZZXMF$cT^g}!&id$3*zf}n$>Z+~=y`ZUk`tr%zCU~c{_}8=NrjhGrvL!J
z&MqJT{C^xS(l`1+=WJ{}?PKG#Db{f1_63E*?Q(9bT6I+Uyf};UQYwsK0WJR
zf4+*JEu31{b@{Aox<8h$jz9a~?Au4-H@UAp8+%`zpM~G;mVBRt09#{o`MltB**l}%
z!uea-^=L
z;k6*Vz-qClc6MfV%KOU#**QMfy?_w6a@)DMoa@^3dbf9V?s#QReoULXJzVs;cey`Z
zT-{BY`uTY@-?H`U?|9AwXS_UJ__lTjQp3l?$v!xEd3CRQ?0yco<(yoy!#m6syiJD9
z?!3jaw_;!0cD^}!c-`klKYt!y9k8YRd0Yh|S}A5+W#?|_d!w`cxkTA#dwY`;#krY-$wo>W$ISn(;CQfV7B+er!v5aX{yN?HlJ*1s)&ALCT=yiu
zw6>*l`}nNi%jy2@=yB!Er*V^5F(+@3iT!#0TFL{3`kAZx=~hu2bpH%-dY2c4bceiv
z{yDd`6C4ES$?tyW8vpyL$Y|#FCn2PV&%50e-5NF%9q4
zcn?P!|H!yf(+xSianQ&@7_4L=d)fE7tF;g0Xrb!cF=&Ph20BQgAl4SZ-y>v%z9%-<
zx9ET_M|q~o1};m!Tz4za80)Lp$j^JTEMcFI-p$)PSKWT^hqUa^ziAGTp@e@<+_&*_
zalNkIUrP>VH+;lyPY;s4+E5FxbND2<
zid?o8;O4XRnb`>?r%`b&9NV7fUwzQSYM;$bvx=hi$}`;^qoH!dP~_ELJnw)f`Koq4
z$0|IWJk1aO?A_#Z&!zWM@89+AUgwYNW(4_#AN%=vB>#GQeS2N-G{5?`EuX}dB;l~)
z?q}`Ri>Q>^RA^@Dyep(D($@W)Q=wgDblv^_d@v0*s1<#74O2he%Se_;Sm7g~5U!}W
zxrpXLe@!26t6%$h@80q9aCb1e%ipy5agchM%1+Pjl}v4K;Ley9>tlBqmUz3B32)lt
zwny({qK{*xx|Y~B+Rs+tGk{
z?TKoIZ_{w;g%Lp0J@snC=buEa=RT(xJ^niU7kIUfgLiOK?g?v2%-HvPPHL8>=@y4p
zrj)Rp%mR|^DsVlYyOs-2%;qp%-Mc#hF_)@j${S}eVw|x-X;BKi5&fD`Wq~V0$xPBj
z--T-vN_V}UGrAc@SgC+bxhK=uLYpe&M9va9K?~OzPHPL{S9?d|BRz64vFLG=Mm4SX
z>#Lf*V=L^y#N-QDh+Ka3%oeL2yIGj$yiaG^9h`EFuo!*uLwS;qt992f1*MJLs3u0L
zTul!IW+^oeoF;hpzn^*fzL~|CoZ?WJdK?ct6WDlmlrV+n7ml*B>hOoL
zXRJ)hWa?5GseZq#G3yGJGIP{@lpV=G<%#sH6w$W{=HUWOx5w_JG6jvf7hFn
z8M3E8TfT8hDIz=h^$1^^oJ2LVUn#ry6J3Az6sc&!so{yNSiYXcUGR;ZQ5hyBa_{pO
zD-g?mFS?$;PsB9q{FQZckdRl9{_mI%JEWHnu*s^)?b1>DKXmIBfLO~UV%Kc3UK`3B
z1)zYx=?_EmEQYvpi~}CQ6~Dx_2y9#7#Xa3f^e+CWKy#q)Vl>^m1aG!|`59dR1B{q~{6LR}|Jf?Q)jLTdnP~wJ
zX{?!Bjmhx9QTd{lqAT4KmL@Ae@
z>ERFe5|vGVJ$Pxyd9CKRW4uYJ2V?PC?}`3LZwuj_vZD+^L`_n^gU#qw(wTa_8A7F_
zh%di9cj=;J<4gS2%M!lQ_v@S&Ep5$AM2FA13%~p^*PK@mGcZmq&S6|IdY4}(Fy({Y
z7366RX~>jt<)M=UZY^J!H(g+aS)CAajQce?;VJ~Z1T&sQR_%hoV5t=)0~9eR#4p7yXL8r>+V{D~NdEEa9I@gCp8c60<%Yj0cH`)YR|<|r-pVMO
zhrZUX4)#W`dacWk7n|<*B=J@ep{B60|J`LNf-DkZ6Zd}Jfb*_Lb{EDhvTpOEQmAPf
z{jyF(ywIcxXR07_{Ev}8ewST!?a8elC~!o<{Qf)7gL<(0^1>G?0`s5c2(iRsejQmf
zr)%t|=1S3&M0P%*x`&g4<&fvlz&ogG%smf*0^HXQsC^WnI!;gc@
z%LAX{4*Rp-$DYgj59M1IZnHnry3MB~!}Yk1JO_kh4S0@^$F0+C+S6eulir88)K8ae
zi|?*MFSv`|(ien-Oy4KL&Ah`byi5E4)L3+}KE)ZO?;d6Bnq=(SF!YWx;VaSHd+FSJ
z$=rLv9zSay3rCpv=34pYTKM+%zZ<8#d=K}VV*N_9_;d(*A*Z<~9A^3ow)%uzd`|?s
z*FT!B&A=cSX!t-~eNva%)Ms7uwcM~RPmeRi^qXM)OtN^l2)Zq~TuB&b$+6;IeDIv)
z<}6Uabxqg{#&zr}hYF<00BG0Bn4_Evj_@W&Ou5vF0SMvQ#O4qpA4Rn06#fR+P6G(#
zam-#93>Qfn_pKtGw7*c!3oK23qA_GjlbIvPZ=(|4L}CF$pAB>lA=M3LNTD!k1cEVW
zZ(zaSC=f!)molyZs#9&u>wqXLquIl7T;F}pl9%r`_gmzr12<znglC}P}N6xkI^x1gU6ZzZ)fhB>$?xBCCiIV^QE6zCM@4j76d$Iu}FSAWs3Ugw~&XqBmAOWS^gm4VHD@215
zo@28i{|q7sb~X85AR_(-K{4PEK%_zr_m`Z8zvc8H#X!^a8}TJl2w*dNq=|fcP$IcF
z3e56I7X4a
znK*%*8Hr~P|8iyzFmVo3$8Xz3e@6~Q6+7Q3B2By*(>IIoH;WAx1`zpCx=RkWYsucD
zAU`ETaD)j>xIG!g*ew!RU{#uM4V$4H)I;8cD;c{#Rmr7{?YG;tptlKrN12iR04W&4
z;c#~VMi$D?zbI;d$DQV1amPCfMb*kDmsSMeD6^Sf1ORnzGaDahxtX5zD|ix;U~DoS
zOwN9QB93H`ibY56dsz;!Ir=4Ikk?iS|1!rU)ZgZy9@Et4t#y<=G38mjdG(%+$JAa*
zw+@vyP17j}m^e&}nsy{h-ebZfi?{g2=>B^l7RZki(*AJ40LydN*SD+dNhmAA@%y94
zU+?>nemtX)68Llu3)?qOt))xa3=TLlXteP1xjkvlp?Z^lI;;6w^{X6OFnSoi!u{5L
z(xg^DmM`rPBeo(x*j^iKdjB+B
z{*r$l{v>;KT=aB6zkEKkLK=(*o4@=B+g;cdi+y$%!@heRd|RnqKWVvbH}<~zd?m7A
z4)yEkU2oZGeMH|#IhX#pUbeY9*9Vz`ic)-`O`-%AVFzWNZcZOAM1(}6ZRv-|H;`{wASz2mEp*Qf*j$FQ(kL`uTgWpp=v{5$h$d|1yKdQACJ-KmDbP4*!YY
ztX*C3urQhraApvs_F&4W3wY-9#<;b$UlfshF>ooi_eg>vhbig|AlPZ(k7U6f>6{_jAxlJ!+J9gC<;2qY$1It)aGd~)?)Tx~
z3xaKOwC)!Y?Z>@2hYzl3k;Lh#YivjHA`#J)YPETX#&<^E~4&*Q5C4jeH&lZv;DMO*
z#>UEDyxzA>o$M-3mY^T`qF*%PVR)GDum3&<_66+H=E`I%=$(SY#!C#XKi?ow5Q|I&R99;4TNyLiTcpOWolGjT+
z#U9SbvDr$8h~@IxJ>A^*aYK#cKp!Tsj)9Wm$-L$y9YUTjs@r2x0pTZN{X=yJ27!O#
z=O}Dx29{x@^O@QYM+W*DjSUU{)H4VKYEYn%qiI~Ki{#5!PQ%T-HL4?Rkk3h^e3d(&
zd334{9xz{qFE(#^I`>!}9KtqRs`+HBFV$c=iK;B9+0cq;V~i!+B&&x)=F
zBx^s)9tmufbX1>}TvSTCCxes9F1x7-a1*2}w|j1>Kenyft*^Ql0`Z-nXGG}q6=}Nb
zFn^(AOLbMs!!IM5{Wb{(!COMYg)-w=Ln=^Sqzq+9{GIj+nE#6f2^TnVC`8y9MMlIK
zg-Bep0j`!(9wh{asy^Xi{rkgdSXB;YA`;BW&M`a~rhnW-mMCO#?6Agq^
zc4Wl68LT$V9+5sxSb=CFqNtkYmW|UuRuQs@DPpCY<>`!*Y7Iavd{z7CzcdXlKzjis
zyDKZ7L1p$eZQ9i_#G3IJSLkidQYp=1TO8zXTYcna3z@$zUy{U&uAZ$*I(bNLdwd~<
zFk+r78MD|=MQs=C3afH*dIqSbwD3krVKq@MoD4CO#elpO=P;PD>f@t+&P@Zg1RGQd
zLfz1yJs~Rk7X_4QC!;ZRQ3S7ParQL>WgTb%4mei(@3psRf$VLXW93v2R>W6<-Bm6s
zdts%b{`g$KuaA<_rP0rrZsDC^Xitq&S(%;!OY~5c@gy%5&z`CDo$X;&SBe`R%9$Zm
zz(Q(vZ**uK=eYtPpMurV3pf!Z
zZ157bDsXetj51`b{-Nspl2=2FRBeI%sDdxLws0jbu7k4;OV7%jm1J_RLbDAk(cLsX
zR8~P(kIeBT(OBDJg|Li5XnAewD}qrAcJC#ZJ^qwGKe)8k|aVxy;~nU|p`bOwtys!%iQsE*E|0j*^nv*#{=>4N1JGY!@f
zHXTq2tl9~S`VDHmp}9DZac*&atCEi@N#yBhG0+l9EV5v1SmeQ|(4KhFwlv8=!@x!b
zm8CZ-fismOr4p!qXUOZ*annnkFIQD?{O_cfO2B0)tf_oWxg!LgTF1Dd>a*sLwK0C}*wdOyKs~(Aj)?pMwKcOS
zDGq8R)yopV_||lglAcaMZraBVU3NV&P90NH{KPc%T{~mHl{!d+Tt%q0DtOCK6V{TJ
zP&5Kfnu;greH1!_wR#3IX=-TiEJ%-XB;Ys
z!oHi&dHVrYfk>rR?D>vu5xQk15C+&(o#Hf;0ABHPXvYTO`DfJU5k3tX;(MFpmhOt8
z;+S1sMFh;Na?{dzEFWB|?E6J~G;36@@%{4_A^Q#Gc$*r*X7go~rlJa1(H#paAh&_>
z`DyiaM@ST~;@e1h!TY1cEpdo(oI7b&nIEbqt&4|1EYKpddMd`2
zlb(PHp*3`gP#Ai@&;~Jc=qq|=lvd?IbOF9_!)t1M1^e#Heel$
z4dJv)j1Qq&DX&HQ)`Tk~>x>r8)k=i`i)l!d7QjF#NpLp#zO;2SHXPufNH~_?$gyU2
zDJ3F|BLki8z(82V@gC)5YK>EKbzI9~1${$<#H!u9oVKBXLSVsgR$&U5C{pPAT9`Fn
zJ#*QZLWo5_BY%P1MmeREiB53nbg;11NAl^Yb__+Pl}0UM8<6eN?Sqh{7@qtPoy-{0
zcDczFI}DQuJ9E+GG-VXTSi&Y6nZ_c{&8kxeVH7q<^WMHcOt7_7_Weg!1hj~Oh&&kc
z6LMdaq%K!-E)CyptCgTlj5Oj*
zL^!Alw`Bx|8cZaC-aCZJaTCEUK3AM;DAb$+g_0
z)<3U_Un7sjai&9=Hxh(fC-Bt9=)m*wv$OXY+A5qFCIE0G(P@tJKXABAqAV1(jS`U1
z)-d7xc3D{eAO5cz#-Z)-;@FcAPIE?1VFnedEoy;?ncrOX&{OOh|_ka
zs{8pv6b-PiX)J3Xv5U@*K?yBA!FjAWR+%o6#6l!h$4ZWRSd#YJ(ImlJrpUhE!e}yT
zjxurJG_c&B*Uo_5uWF6j*XPvM0c$b|vj%mpt4hNvnU^_>8*C}KHrOl+rjh1TRcIqs
zc=pti1P3`wXCpup`Zo$9$Q&Dc`PT_}a${E0*^g+>a(8-^#mpk)q*|2PnsVsE=m!PM
ze!RH5AWrvH(14L9jK}w3&C~Sgd_My*VAY&@T+7tDm77
zIwCpyG
z?nj7nnOF6qv0dmuLv0OB;kY%Ln~+a3{s&G&L{y5gsXfiqjDEsN5;`q8gOHMz1ZQcT
zIcET3LV?f(C#mQpWK>)dvQo^X`@?%OmkQs&mbAE?mQpoEv?Rtt@pckNV&p@Bw|Ca0)gk>&3Wok7cgMk!A
zJe{scF|)+i)6}az4li^Vp)Sbrk}$>-qq7-$9h#05%g?MS@x(m?)kd*`RolLYAM2)z
zE$*4*dMU3V_kU(lkukGqZ^%e83k`q075=scDhX3~E`Xb%hORg#XA4(H&e~#ii#Ez|U+1NSL`6oKrhMYzQ2?l@G6DRlA}
z1h{LDwDpB3zS(vOgv&AB6I$He>G{<4K(^J-+I5&^B-6#-P_Nq{M6XA+(MmO;DpG_-
z2Q^4ZNNtR*T#SE?+7JWngap%a9Zk5Na9HGSg9+O))l`UP+&7@}%G0zmZ$(v`JG5OS%c0
zlq(u(n+sB;^O#oUEX}{8TLq$NdU{1ERVdFGDhVePBMphN!#?9@$o#KV$ZSI+)R`ZtuE`h>
z;Uid-KU|1HR@pbShD6CiQRvokuM;f#F!|wm#>Ek+*C#qjul$qydLEyyN+Wj$UYon7T-9UDYRY4m2EP|#sf8~
zq-;FW1o#T5$zG5$-N%w^ag8;RZ_n;OEUv>=YKv`0!=(iM1(mgZk`QDKT}YuWl3&i+
z9VV6_@+C$c@8fq~v|M@7mfgbA3yM42kgH!6p_QAQB`FY><%!b@j*d)LF-Fe_*0&Jm-nokiO98;METD=7#MS!IzbLI@y
zyU|!wMQw1ovT|rvf_FeYtkQImYteL3B};+|ZW%zaQIpvO``(<7xkb-2h@PV?3eQG;
zN)2IIS`dlhbd?;E8U4a*HnMv^LJFG_uVWZOi|UYwL{h9WJ{vRbqF@^GxQi_Bz|vM6
zGork}m?O<=99Pi=p?Z|2Y0;V@6YfC!soYh6$6rW2?z_BM-t@k1upSZPWtLb$OD;@;
zX`W)5jFoiggimgwp=V`j4(+f9?}guTx}BtwNdhC--8+up&73zGrhggJlz9+OD|fbJ
ze=t8{%1ndxDn=z4OybSq4cH2
zrz29DPFTTqVKLZg%ET}v?810sb-JM`Nk4I_b;@J=IAIl|;VrmhXhzzgd%<|P#H;nd
zuxezJTNoC3w18iOvP*&m`)O!`G-&dZ6p})mLvk!QBt7aOn;f|SUSGUgt~;%RAg^@q
z$o1_P=%()J3j1Yht?g0!O;}s}m=ZywG(;un_J}HaGBkos(XumR3>raxQ6E;GGYCoQ}CnIIG3ssr55B+Y7`Bma3H}8EDvi+g|^0zOC!cU1#rq7E*dP1GlF4-
zlUVRUx7UJgN8CKRrRVJS+y#D1j{|r=`farQkCASt#C6XSH-r7?s@fC>c+IV$TicF4
zRzu!e=hxAlFn)YCwxhuxyhzn0Z8w&u6Pg?^pvB&hUkg?@kDrtv#x6yNfsFw{u0pgk
zv%S#Oo+Qe0_Xf%9LqoN3lOGP7MDR16fJTME%4~ctlKrJmQ+X?=!X@Qogb^Lo-NSgSyWHWaSeb+
zc68I~KOifdZA9fmu+CqQ8eJsVozGu3kOUFZ5oY1{=X7Y*HlCJT2#~!FX2qeSL`8u%
zXm@LOh5-nUJ=VJh488X}F=@yN!ks6pSgRH2P;g5I=IRRTbIg87*zm4Qr#hd9_TSaP
zzj?~GDu=XjvE_wfpPkD&S$~?b_HhqPze_LFZ1J0{Z%mEUvn;MY;Lu&Md#v%=N_`Z7
z)KzNI&sC$AZJ!Ldv~EDBJ#_b61VXd9H0BbjyF~^qfUB+*$`)wgg%wFpk_0t(x#Ut*
zkiygxjV-wf)2KtI&o;_hdq7{hOloeXFsu-6A}p1(|5oDa-%Ux2+DwXU?U
zti0>;o@ngZQGiqbO)t*3JrZC#aj;;tW*GnsVlR7N=C|=Q8>6y!d@U(XXPaeSG`BqlSvsSf+d6~>4d(@8P
zs`E*)RvoXR0#iqE-~)I*bB_T+aAd}!7}P@ARV3&>oJ+PFz`T`Kj{*RfJR4|9>#A(I
z{t#U6G>p5g*%_&z#bnKpmP!0{wPo=)Wj)qqf#+x{p(#DuD@nM_o?_*DpQJY75?xzMow!Ifn*u;^`cs%MjWjTVk9y{n@TRaFg6|bN@wqqm56F-mc8X|M%c&T7$EOHcdv6UZr=gT9)V8&z7wHJMBv5c^0j5Bde22;x(Az
z6c3GT@{-|%CHh_%E;fN~5Y5SwgV~YootWPqu_HeMG|rSwuJ!`Y0iN*|aN{0m?4DHQ
z9{~+V^82D2D(;rHflH;4w_n|SOR(hG;G`m>6Mi)0&?b}9TF}ugPun$cGB
z7zCAbG74?e>+-dBRB3B7dUka^22O4tU0xoyq_L@}N2ev1u&BBnc;{DI6)T*+YPMOb
zDJ3RWX#1K4juBf~J1P~?^+2d+@HOXQigd~)xe_Cph?hT9&WIjmg*}vI#njr+t4*UO
z*$7ujCYVmf6E=sd*!(~ed;k;AMKY%J#Y
zQ7qoIF~v0zEvq!9v-Eh%HXL0@6_FA(25P;7FKYMzTg^H|wzjTfgWknib7^JPlXgUP
z;__%2VKAVwi9pMka>ZSz7*sJ+sT)hhNw90J5pL3b&z()oNzL@ryE{G~7JPmanM1Xp6Kq4v3&#eN_m~=!Vboou{#Mherjd;}|Da~*+
zbH}?2#0b9s*Eo_!kN0
z;LVrj2^Ru=H}4X{`fziQWx9^bUnQZZ=X_EZ`9$}rAE5}
z_O~A@S8wH8&&uJ~MyuOAsoZqW+P_@IWy~P==8pU&Eno>2kl-PDhunsoQ@*(;Piejt
zpv!N>Wy~i1#^lHqnKINP{oDF)j{VN8nF7-KYb35s#6?Y^wm)>GjpmXUoxwA%|NpYz
zoo-J%ah4~((dIep{)I$16_~8J(O;qy2Z1m9GUAkmP{%uUQL~BUNmt0MbKjf%Ke4L+
zrQLsEMg14n;eV?7w}Agp^?%8JM>+F9Sb6^&YxqC0dKqy^e_Qd$8I3mFCv|Q;$Gr-9
zVAzc_TU6R;m(;n1yrePM{#IAcY(8Pl4Kn-k|BF3s2I+sneq^%qKUjVK8*Ai0vA+Ea
zYtO%g(bqWr1MB~m{a>p7i~Xqh|6SM7zmSB{fy+pl0mi#>5_ofY(fpH}7ww-$#{1W7
zvHvpq=suSGf7-$LpZc5cv^LrU_I&c^$vq42R
zj{I*I=FL&
zq%ylh2B6=&vA@!pT|3^fiiQ}}nw)A1z
z&yVH8?YLxaLOrYxITPtndp4%+H;4B?EFTxHBpL{e_7BrDkF;C8lKz;!EN7>l2MioP
zt(1Ylg{BCeOV1I4$X=ritWpurrvJz-Tp#A=?1?fBx=50QGx(4`MFoLL^Mp*|Qda3b
zk<9%)270F4cUlbofAw{qQB5st9}j`hn}iY}K~O0w-GHHklpuuALx)hLNlByyut0(o
zDGFjx1O!18MMy*-2uKH&8bGB44ozvIpi%_H8_&7-ocDUydS`#wvuDq5J$s)0ZJss%
zekhpgSzd(pg*Sh{yYT~PlDY$Vg
zni`zS7dt@o8+q-X5tWj#7i>*jcPLO1+Yt`1qg)F_LrL
zp8sHwn?mdOPZbGUkkXU8RpSU%1)pgpXWiq+@h=CyI&fGSLW7YWsdr$ssc0HZQwALs
z;cA6tj*wt1Azr>SxQe_IqIfQ<&k8nl+dn7y221vBWUD}4%vx+<<4aJLHi3vGGu^Jh
zpRFKzsp>Jhp|y~z4~U0S95yyLNV;=!XLg99V%n7A2;B4ZaC7JrT+!9JH;~#p>b+D#
zj)*3r*u(xJPJzb-`q5f>UuQIvD9WLYNt3!DVcA|CNr3#2KXJa+Pvcha-8P8PHIm};
zYI|OmO{*MV#cgl#&mEE&?MF3c3^RDXRi=Qv1q72P>n@zg+
z7#`>8K8aU8NL27@m2%~AVSFSIgRj8KnCTK7OP3jMyw<&18ZQSv+UqnosbOOaervNG^;Fygs?moM
z1?lq7l%{T7->~~=Ym-qTV|748P3A#&D_PUSFLrxdIRH=bQO%#xfG%wKGBiPoO2(x{
zvpC23;iw>DyO2DD->oXELlq83AP%9D@?OJ?Pw=?7?NI-m^W#EH`DzX;r78|9N^vUSru`X(*kpR5
zoMbOjjtv)V&nG6fKXg~%548m9S#qPXfDFbgx4Hr)XhCN|eEiVBz7&pJlk8glsuDI(<)>0}LjU|SFQ%T7y$ywhC
zx(oG#LJ#|-0%febK^=shyM;!{R_#mP+u}MA%LCny(*l?oj`2MYNO;>)s}YEBQX+N|
zD0vDWcIJV_Nww8Wh*!t;v|C?Avd*SsFR(;TZ7$aDOs}eO
zbA-u$Rh9LRdY*AXKZR4vrLmwVzNhtdw;>#{oAAf@K=JTH=&^jC6dy`lJe}4$kq4z&6?y;KcD1~E0qM)akWh|(3At!5
zCh}YL+#0Ai=9|!F{1hJAkj(4eCh1L`Xwmg$2yF_cO`5JslgN~Q(cN}0VgB5elbgMr
z9-o86V^j}%8b>(iO#;x_E`6F0Kuhe4_ol}hu!3s*!&lExdlZ_x&o(6SBiAPtoE
z{`l20QoZsRs1jJsZ+e_XrlHOOi+Q}y=)R&DxjCFJ`Fy^+E-~kszeg(e+I^Y{xF;0c
zTKe?~^g^$+%F?OxHk1fkvAWooxV)-Kw~~ry5WV1@?Y}n*%kwc+CJ7seyl)MzeF~p+`4%w
z4&H1_27lDoPDpS`n(An?s1F6N(1q>Bq_<+qAtYUMJ=t3dTJ-cXn8zc(FMjJ-u|n0g
ztg7)ibDfDz+G^bm`ZDn(dhMgTAohC7)j}X$_;7j73ErLXngEftQdN4%tG!5J_7?+V
z8`1!NUlRy1Envq_d;?(vSY#FtBtB7Zc7n>2ZAJ|5F5?9+t=k)@XAEJ;Co^vfjl=Vv
zc7}A88qYX|SZZhKu{!36Ew2M#B|Zeu*Sv)~iouB#V9$BWxy5`ibcE`bpRiJW;xq^|
zSY~&CZkcCon8vKN#Uf8>Hi5MRPdh6P4GZ#X-e^gbkxw|FDr{fLmbByov|F&7W*ZfJ
zP^3_{+{RlX+$mpyU8i(U2djZxXWKDpW4^SOmKOXWr`|%k$uZ2>NM9iz`N<+JTEm%o
z$6ipF5q?O3$k$(%Z&F8hLO@fb8*etzUoN{#!B_g?!(D>Mja?<5X*9<}`e^LpVVPO%
z;(}g96It*<#I~F0Vy4a@EZJcAZKyMx)Qu^M<4@?i6Afj}5L+{2S658e
zaTVE;8URhojtUdu>!)N4gk8riYrtZ0zErYQuEk~AVe)-)_2b4)9?
zZU?K<^Pd@I3Ce4{Zt|CGy+GA4c!>en40n)!ZJ$jMPX%1d?Y`QCSVr@`9$xEzON
z!E{Y7jBDa0gDEc0-ES6LlTQeeHt4jZan%(Hh;a>o
zhjpIEbrrSKbk<`t+AG@y9bK7ruZXrey-6smknM48$(ck71+aEVhoS)#SEOmsTV<|M@Nd9!WoXm7vDPqiC(QIlIi8_
z-Z{?`9Ey(~K{myzhoau5m0;uR9%+p(jdBp^$)Ul$v8ON>VosTGg@1!;OGL<}8pS@|
z<+Lk3s%u#))d#Q`4(@lOtgK@XpXKv@d^9y`g@?#>)@
zA&vlxRpC>&n2V5wNsBKpH=Wi}yO;WLHKov3=$%`O@6^nf?|`i%b7eB6u_(}*gXCqtqVuAE3&2c@mwj5dz9>C`?O9g
zT)q~$tcS0#a1*yxakdC!%}wI$4C`jN<(Lc@f0<~1LU}Q-7x%_y*-!Yxk92rekD9<6
zgJ2O@(<8}KgD2JW&$HPF3MXw(U!Cim2;kAvssZKG6j8J25Ei+B9+bXUxNOeEVW6Rj
zDdU_hnn9+#8>(G1{Oiuv#GZaI_Dq#Xk-}$8yYo4zI8?lpzc*9J(cE>MyC2zg5fk3c
z*~J5Ru;_@5nd#O(ydJ>6U4Oha4W`}pOgcbv$G;|ECU9fGqE0s%83WNR}n
zBsEK3O!0lCQ?~d5GOZ!CG1S&8i!lYf?HrTu4&qmK#zUoW-
ze>Ng8|lU)t5
zjMcSspFf2D#KlC{wC1i?-4l3c^TqXZ!|LkB8vay*@XS_jbJ*hUO5gs6;mPXe!lt#o
zhI79*Hf?218df)@_cwp;^I5(?Z0o}ft3b(#tN;KPbM#kZJ_1S;e)R&Peb4$S5ki9hgZ;;SbuKV>h{q5J2v`*a
zaQ~XgY=2=)4Rru6Jkm2TG%!NR=XWkp|NA0%9tiMGg#5<6J`Mbb3;3OzpWcfo(E|dy
z76bwOe}(&ZJdhmdZ_d*n7yQ35hjgDCrp*EY4hfLo*pagw|IPkS+?Bn#rK&qD0KStv
zf4a>6v(7X#?!Vbznh?K#@$de$|B$}(JpbiZ`#br&_{2YCD}?uN^50Sv))pZ4UlTZ)
z*B~?X<<7hSC4h=*K-AfjRs=g0E0nWZn4z6{5ZVy!WD`WNJ86fuLi(Ra8~T_ktC^u)
IOyIiz0_y@1IRF3v

literal 0
HcmV?d00001

diff --git a/FreeRTOS/Demo/Common/Minimal/AbortDelay.c b/FreeRTOS/Demo/Common/Minimal/AbortDelay.c
index 349c1cb58..d32d31dc8 100644
--- a/FreeRTOS/Demo/Common/Minimal/AbortDelay.c
+++ b/FreeRTOS/Demo/Common/Minimal/AbortDelay.c
@@ -237,6 +237,7 @@ static void prvBlockingTask( void *pvParameters )
 {
 TaskHandle_t xControllingTask;
 uint32_t ulNotificationValue;
+const uint32_t ulMax = 0xffffffffUL;
 
 	/* Just to remove compiler warnings. */
 	( void ) pvParameters;
@@ -247,7 +248,7 @@ uint32_t ulNotificationValue;
 	for( ;; )
 	{
 		/* Wait to be notified of the test that is to be performed next. */
-		xTaskNotifyWait( 0, ULONG_MAX, &ulNotificationValue, portMAX_DELAY );
+		xTaskNotifyWait( 0, ulMax, &ulNotificationValue, portMAX_DELAY );
 
 		switch( ulNotificationValue )
 		{
diff --git a/FreeRTOS/Demo/Common/Minimal/StaticAllocation.c b/FreeRTOS/Demo/Common/Minimal/StaticAllocation.c
index d4e8f6d7b..0c3a2b69d 100644
--- a/FreeRTOS/Demo/Common/Minimal/StaticAllocation.c
+++ b/FreeRTOS/Demo/Common/Minimal/StaticAllocation.c
@@ -253,9 +253,6 @@ void vStartStaticallyAllocatedTasks( void  )
 					   staticTASK_PRIORITY,					/* Priority of the task. */
 					   &( uxCreatorTaskStackBuffer[ 0 ] ),  /* The buffer to use as the task's stack. */
 					   &xCreatorTaskTCBBuffer );			/* The variable that will hold the task's TCB. */
-
-	/* Pseudo seed the random number generator. */
-	ulNextRand = ( uint32_t ) prvRand;
 }
 /*-----------------------------------------------------------*/
 
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c b/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
index bcbf34bac..34d29e7fa 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
+++ b/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
@@ -357,7 +357,7 @@ uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
 
 		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
 		value. */
-//		configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+		configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
 
 		/* Restore the clobbered interrupt priority register to its original
 		value. */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S b/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
index 5f8f9fc20..5d3a37760 100644
--- a/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
+++ b/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
@@ -91,10 +91,6 @@
 	.global FreeRTOS_IRQ_Handler
 	.global FreeRTOS_SWI_Handler
 	.global vPortRestoreTaskContext
-	.global vPortInstallFreeRTOSVectorTable
-
-
-
 
 .macro portSAVE_CONTEXT
 
diff --git a/FreeRTOS/Source/portable/MemMang/heap_4.c b/FreeRTOS/Source/portable/MemMang/heap_4.c
index f7e3f01a2..019d851e4 100644
--- a/FreeRTOS/Source/portable/MemMang/heap_4.c
+++ b/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -297,7 +297,7 @@ void *pvReturn = NULL;
 	}
 	#endif
 
-	configASSERT( ( ( ( uint32_t ) pvReturn ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
 	return pvReturn;
 }
 /*-----------------------------------------------------------*/
-- 
2.39.5